From 4620e7ccfebc08dbd4c039bc7d530b62c4c68ca8 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Fri, 10 May 2024 12:29:25 +0000 Subject: [PATCH] nrfx 3.5.0 release Signed-off-by: Nikodem Kastelik --- CHANGELOG.md | 14 + doc/drv_supp_matrix.dox | 155 +- doc/nrf54h20.dox | 100 + doc/nrf54l15_enga.dox | 86 + doc/nrfx.doxyfile | 2 +- doc/nrfx_api.dox | 2 + doc/sphinx/drivers/auxpll/hal.rst | 6 + doc/sphinx/drivers/clock/index.rst | 1 + doc/sphinx/drv_supp_matrix.rst | 2 + doc/sphinx/nrf54h20.rst | 5 + doc/sphinx/nrf54l15_enga.rst | 5 + drivers/include/nrfx_twim.h | 1 + drivers/include/nrfx_vevif.h | 2 +- drivers/include/nrfx_wdt.h | 10 + drivers/src/nrfx_grtc.c | 17 +- drivers/src/nrfx_twim.c | 18 +- drivers/src/nrfx_uarte.c | 60 +- drivers/src/nrfx_vevif.c | 3 +- drivers/src/nrfx_wdt.c | 17 + hal/nrf_aar.h | 257 +- hal/nrf_auxpll.h | 581 + hal/nrf_cache.h | 14 + hal/nrf_common.h | 15 +- hal/nrf_gpio.h | 6 +- hal/nrf_gpiote.h | 173 + hal/nrf_grtc.h | 12 + hal/nrf_lrcconf.h | 14 + hal/nrf_ppib.h | 9 + hal/nrf_pwm.h | 31 +- hal/nrf_resetinfo.h | 11 +- hal/nrf_saadc.h | 12 + hal/nrf_spu.h | 14 +- hal/nrf_tampc.h | 33 + hal/nrf_vpr.h | 26 +- haly/nrfy_common.h | 2 +- haly/nrfy_grtc.h | 4 +- haly/nrfy_rramc.h | 101 +- haly/nrfy_uarte.h | 9 + helpers/nrfx_ids.h | 10 +- mdk/arm_startup_nrf9230_enga_application.s | 828 + mdk/arm_startup_nrf9230_enga_radiocore.s | 856 + mdk/core_vpr.h | 96 +- mdk/gcc_startup_nrf9230_enga_application.S | 871 + mdk/gcc_startup_nrf9230_enga_flpr.S | 941 + mdk/gcc_startup_nrf9230_enga_ppr.S | 925 + mdk/gcc_startup_nrf9230_enga_radiocore.S | 885 + mdk/haltium_interim.h | 55 - mdk/iar_startup_nrf9230_enga_application.s | 1039 + mdk/iar_startup_nrf9230_enga_flpr.s | 1102 + mdk/iar_startup_nrf9230_enga_ppr.s | 1022 + mdk/iar_startup_nrf9230_enga_radiocore.s | 1109 + mdk/nrf.h | 19 +- mdk/nrf51.h | 6 +- mdk/nrf52.h | 6 +- mdk/nrf52805.h | 6 +- mdk/nrf52810.h | 6 +- mdk/nrf52811.h | 6 +- mdk/nrf52820.h | 6 +- mdk/nrf52833.h | 6 +- mdk/nrf52840.h | 6 +- mdk/nrf52_erratas.h | 26 +- mdk/nrf5340_application.h | 6 +- mdk/nrf5340_network.h | 6 +- mdk/nrf53_erratas.h | 61 + mdk/nrf54h20_application.h | 9 + mdk/nrf54h20_application.svd | 785 +- mdk/nrf54h20_application_peripherals.h | 21 +- mdk/nrf54h20_enga_application.h | 9 + mdk/nrf54h20_enga_application.svd | 8 +- mdk/nrf54h20_enga_application_peripherals.h | 1 - mdk/nrf54h20_enga_flpr.h | 15 + mdk/nrf54h20_enga_flpr.svd | 8 +- mdk/nrf54h20_enga_flpr_peripherals.h | 1 - mdk/nrf54h20_enga_interim.h | 2 - mdk/nrf54h20_enga_peripherals.h | 2 - mdk/nrf54h20_enga_ppr.h | 15 + mdk/nrf54h20_enga_ppr.svd | 8 +- mdk/nrf54h20_enga_ppr_peripherals.h | 2 - mdk/nrf54h20_enga_radiocore.h | 9 + mdk/nrf54h20_enga_radiocore.svd | 40 +- mdk/nrf54h20_enga_radiocore_peripherals.h | 1 - mdk/nrf54h20_enga_types.h | 107 +- mdk/nrf54h20_enga_version.h | 3 +- mdk/nrf54h20_flpr.h | 21 +- mdk/nrf54h20_flpr.svd | 93 +- mdk/nrf54h20_flpr_peripherals.h | 1 - mdk/nrf54h20_global.h | 6 + mdk/nrf54h20_interim.h | 2 - mdk/nrf54h20_name_change.h | 2 + mdk/nrf54h20_peripherals.h | 2 - mdk/nrf54h20_ppr.h | 21 +- mdk/nrf54h20_ppr.svd | 93 +- mdk/nrf54h20_ppr_peripherals.h | 1 - mdk/nrf54h20_radiocore.h | 9 + mdk/nrf54h20_radiocore.svd | 809 +- mdk/nrf54h20_radiocore_peripherals.h | 6 +- mdk/nrf54h20_types.h | 1089 +- mdk/nrf54h20_version.h | 3 +- mdk/nrf54l15_application.h | 10 +- mdk/nrf54l15_application.svd | 4812 +- mdk/nrf54l15_application_peripherals.h | 343 +- mdk/nrf54l15_enga_application.h | 10 +- mdk/nrf54l15_enga_application.svd | 4800 +- mdk/nrf54l15_enga_application_peripherals.h | 341 +- mdk/nrf54l15_enga_flpr.h | 12 + mdk/nrf54l15_enga_flpr.svd | 4796 +- mdk/nrf54l15_enga_flpr_peripherals.h | 355 +- mdk/nrf54l15_enga_interim.h | 9 +- mdk/nrf54l15_enga_peripherals.h | 14 - mdk/nrf54l15_enga_types.h | 1913 +- mdk/nrf54l15_enga_version.h | 1 - mdk/nrf54l15_flpr.h | 12 + mdk/nrf54l15_flpr.svd | 4808 +- mdk/nrf54l15_flpr_peripherals.h | 357 +- mdk/nrf54l15_interim.h | 9 +- mdk/nrf54l15_peripherals.h | 14 - mdk/nrf54l15_types.h | 2079 +- mdk/nrf54l15_version.h | 3 +- mdk/nrf9120.h | 6 +- mdk/nrf9160.h | 6 +- mdk/nrf9230_enga.h | 54 + mdk/nrf9230_enga_application.h | 539 + mdk/nrf9230_enga_application.svd | 186420 ++++++++++++++ mdk/nrf9230_enga_application_peripherals.h | 1480 + mdk/nrf9230_enga_application_vectors.h | 694 + mdk/nrf9230_enga_flpr.h | 342 + mdk/nrf9230_enga_flpr.svd | 138985 ++++++++++ mdk/nrf9230_enga_flpr_peripherals.h | 1221 + mdk/nrf9230_enga_flpr_vectors.h | 719 + mdk/nrf9230_enga_global.h | 879 + mdk/nrf9230_enga_interim.h | 150 + mdk/nrf9230_enga_name_change.h | 49 + mdk/nrf9230_enga_peripherals.h | 58 + mdk/nrf9230_enga_ppr.h | 326 + mdk/nrf9230_enga_ppr.svd | 138921 ++++++++++ mdk/nrf9230_enga_ppr_peripherals.h | 1221 + mdk/nrf9230_enga_ppr_vectors.h | 703 + mdk/nrf9230_enga_radiocore.h | 685 + mdk/nrf9230_enga_radiocore.svd | 198206 +++++++++++++++ mdk/nrf9230_enga_radiocore_peripherals.h | 1623 + mdk/nrf9230_enga_radiocore_vectors.h | 708 + mdk/nrf9230_enga_types.h | 105221 ++++++++ mdk/nrf9230_enga_version.h | 53 + mdk/nrf9230_enga_xxaa_application.ld | 21 + mdk/nrf9230_enga_xxaa_application.sct | 56 + mdk/nrf9230_enga_xxaa_application_memory.h | 73 + mdk/nrf9230_enga_xxaa_flpr.ld | 21 + mdk/nrf9230_enga_xxaa_flpr.sct | 56 + mdk/nrf9230_enga_xxaa_flpr_memory.h | 69 + mdk/nrf9230_enga_xxaa_ppr.ld | 21 + mdk/nrf9230_enga_xxaa_ppr.sct | 56 + mdk/nrf9230_enga_xxaa_ppr_memory.h | 69 + mdk/nrf9230_enga_xxaa_radiocore.ld | 22 + mdk/nrf9230_enga_xxaa_radiocore.sct | 61 + mdk/nrf9230_enga_xxaa_radiocore_memory.h | 77 + mdk/nrf_mem.h | 13 + mdk/nrf_peripherals.h | 3 + mdk/nrf_vectors.h | 13 + mdk/ses_startup_nrf9230_enga_application.s | 660 + mdk/ses_startup_nrf9230_enga_flpr.s | 646 + mdk/ses_startup_nrf9230_enga_ppr.s | 646 + mdk/ses_startup_nrf9230_enga_radiocore.s | 660 + mdk/system_nrf92.c | 115 + mdk/system_nrf92.h | 61 + soc/nrfx_coredep.h | 38 +- templates/nrfx_config_common.h | 2 +- templates/nrfx_config_nrf54h20_enga_flpr.h | 9 + templates/nrfx_config_nrf54h20_enga_ppr.h | 9 + templates/nrfx_config_nrf54h20_flpr.h | 9 + templates/nrfx_config_nrf54h20_ppr.h | 9 + .../nrfx_config_nrf54l15_enga_application.h | 69 + templates/nrfx_config_nrf54l15_enga_flpr.h | 78 + templates/nrfx_config_nrf54l15_flpr.h | 9 + 173 files changed, 803703 insertions(+), 18854 deletions(-) create mode 100644 doc/nrf54h20.dox create mode 100644 doc/nrf54l15_enga.dox create mode 100644 doc/sphinx/drivers/auxpll/hal.rst create mode 100644 doc/sphinx/nrf54h20.rst create mode 100644 doc/sphinx/nrf54l15_enga.rst create mode 100644 hal/nrf_auxpll.h create mode 100644 mdk/arm_startup_nrf9230_enga_application.s create mode 100644 mdk/arm_startup_nrf9230_enga_radiocore.s create mode 100644 mdk/gcc_startup_nrf9230_enga_application.S create mode 100644 mdk/gcc_startup_nrf9230_enga_flpr.S create mode 100644 mdk/gcc_startup_nrf9230_enga_ppr.S create mode 100644 mdk/gcc_startup_nrf9230_enga_radiocore.S create mode 100644 mdk/iar_startup_nrf9230_enga_application.s create mode 100644 mdk/iar_startup_nrf9230_enga_flpr.s create mode 100644 mdk/iar_startup_nrf9230_enga_ppr.s create mode 100644 mdk/iar_startup_nrf9230_enga_radiocore.s create mode 100644 mdk/nrf9230_enga.h create mode 100644 mdk/nrf9230_enga_application.h create mode 100644 mdk/nrf9230_enga_application.svd create mode 100644 mdk/nrf9230_enga_application_peripherals.h create mode 100644 mdk/nrf9230_enga_application_vectors.h create mode 100644 mdk/nrf9230_enga_flpr.h create mode 100644 mdk/nrf9230_enga_flpr.svd create mode 100644 mdk/nrf9230_enga_flpr_peripherals.h create mode 100644 mdk/nrf9230_enga_flpr_vectors.h create mode 100644 mdk/nrf9230_enga_global.h create mode 100644 mdk/nrf9230_enga_interim.h create mode 100644 mdk/nrf9230_enga_name_change.h create mode 100644 mdk/nrf9230_enga_peripherals.h create mode 100644 mdk/nrf9230_enga_ppr.h create mode 100644 mdk/nrf9230_enga_ppr.svd create mode 100644 mdk/nrf9230_enga_ppr_peripherals.h create mode 100644 mdk/nrf9230_enga_ppr_vectors.h create mode 100644 mdk/nrf9230_enga_radiocore.h create mode 100644 mdk/nrf9230_enga_radiocore.svd create mode 100644 mdk/nrf9230_enga_radiocore_peripherals.h create mode 100644 mdk/nrf9230_enga_radiocore_vectors.h create mode 100644 mdk/nrf9230_enga_types.h create mode 100644 mdk/nrf9230_enga_version.h create mode 100644 mdk/nrf9230_enga_xxaa_application.ld create mode 100644 mdk/nrf9230_enga_xxaa_application.sct create mode 100644 mdk/nrf9230_enga_xxaa_application_memory.h create mode 100644 mdk/nrf9230_enga_xxaa_flpr.ld create mode 100644 mdk/nrf9230_enga_xxaa_flpr.sct create mode 100644 mdk/nrf9230_enga_xxaa_flpr_memory.h create mode 100644 mdk/nrf9230_enga_xxaa_ppr.ld create mode 100644 mdk/nrf9230_enga_xxaa_ppr.sct create mode 100644 mdk/nrf9230_enga_xxaa_ppr_memory.h create mode 100644 mdk/nrf9230_enga_xxaa_radiocore.ld create mode 100644 mdk/nrf9230_enga_xxaa_radiocore.sct create mode 100644 mdk/nrf9230_enga_xxaa_radiocore_memory.h create mode 100644 mdk/ses_startup_nrf9230_enga_application.s create mode 100644 mdk/ses_startup_nrf9230_enga_flpr.s create mode 100644 mdk/ses_startup_nrf9230_enga_ppr.s create mode 100644 mdk/ses_startup_nrf9230_enga_radiocore.s create mode 100644 mdk/system_nrf92.c create mode 100644 mdk/system_nrf92.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 6596de418..d8f461954 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,20 @@ # Changelog All notable changes to this project are documented in this file. +## [3.5.0] - 2024-05-10 +### Added +- Added function for freeing all allocated channels in the WDT driver. +- Added HAL for AUXPLL peripheral. +- Added support for nRF54H20 and nRF54L15 in the AAR HAL. + +### Changed +- Updated MDK to version 8.64.0. +- Changed default implementation of the core-dependent delay loop for the VPR cores. Now, the VTIM peripheral is utilized instead of CPU spinning. + +### Fixed +- Fixed 1 MHz clock frequency configuration setting in the TWIM driver. Now, the supported pins are checked only if GPIO or PSEL configuration is specified. +- Fixed overridden write mode in the RRAMC HALY. Now, the configured write mode is preserved before the write operation and restored afterwards. + ## [3.4.0] - 2024-03-08 ### Added - Added support for nRF54H20 and nRF54L15. diff --git a/doc/drv_supp_matrix.dox b/doc/drv_supp_matrix.dox index 84fc35635..82159fd79 100644 --- a/doc/drv_supp_matrix.dox +++ b/doc/drv_supp_matrix.dox @@ -12,77 +12,100 @@ This page lists MDK symbols to be used and nrfx driver components supported by p The following table presents MDK symbol used for a specific device. @warning The MDK symbol used to build nrfx for a specific device may not necessarily correspond to the device name. -| Device | MDK symbol | -|--------------------|--------------------------------------------------| -| nRF51 Series | NRF51 | -| nRF52805 | NRF52805_XXAA | -| nRF52810 | NRF52810_XXAA | -| nRF52811 | NRF52811_XXAA | -| nRF52820 | NRF52820_XXAA | -| nRF52832 | NRF52832_XXAA
NRF52832_XXAB | -| nRF52833 | NRF52833_XXAA | -| nRF52840 | NRF52840_XXAA | -| nRF5340 | NRF5340_XXAA_APPLICATION
NRF5340_XXAA_NETWORK | -| nRF9131
nRF9161 | NRF9120_XXAA | -| nRF9160 | NRF9160_XXAA | +| Device | MDK symbol | +|--------------------|--------------------------------------------------------------------------| +| nRF51 Series | NRF51 | +| nRF52805 | NRF52805_XXAA | +| nRF52810 | NRF52810_XXAA | +| nRF52811 | NRF52811_XXAA | +| nRF52820 | NRF52820_XXAA | +| nRF52832 | NRF52832_XXAA
NRF52832_XXAB | +| nRF52833 | NRF52833_XXAA | +| nRF52840 | NRF52840_XXAA | +| nRF54H20 | NRF54H20_XXAA
NRF_APPLICATION
NRF_RADIOCORE
NRF_PPR
NRF_FLPR | +| nRF54L15 EngA | NRF54L15_ENGA_XXAA
NRF_APPLICATION
NRF_FLPR | +| nRF9131
nRF9161 | NRF9120_XXAA | +| nRF9160 | NRF9160_XXAA | @anchor nrfx_drv_supp_matrix_table @par Driver support matrix The following matrix provides a comparative overview of which drivers are supported by specific Nordic SoCs and SiPs. -| Driver | nRF51 Series | nRF52805 | nRF52810
nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF91 Series | -|------------------|--------------|--------------|----------------------|--------------|--------------|--------------|--------------|--------------|--------------| -| @ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_comp |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_icr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -| @ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -| @ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_pdm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_pwm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -| @ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -| @ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -| @ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| Driver | nRF51 Series | nRF52805 | nRF52810
nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF91 Series | nRF54H20 | nRF54L15 EngA | +|--------------------|--------------|--------------|----------------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|---------------| +| @ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_auxpll |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_bellboard |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick | +| @ref nrf_comp |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_cracen |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +| @ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ctrlap |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_exmif |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_icr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_glitchdet |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +| @ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_grtc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick | +| @ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_ipct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick | +| @ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_lrc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_memconf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_mpc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_mvdma |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_pdm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick | +| @ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_ppib |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_pwm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_ramc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_resetinfo |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_rramc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +| @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_stm |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_tampc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_tbm |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_tdm |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagGreenTick | +| @ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_usbhs |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_vpr |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | @anchor nrfx_drv_supp_matrix_list @par Driver support lists @@ -97,6 +120,8 @@ The following pages list the drivers supported by respective SoCs and SiPs: - @subpage nrf52833_drivers - @subpage nrf52840_drivers - @subpage nrf5340_drivers +- @subpage nrf54h20_drivers +- @subpage nrf54l15_enga_drivers - @subpage nrf91_series_drivers */ diff --git a/doc/nrf54h20.dox b/doc/nrf54h20.dox new file mode 100644 index 000000000..4733f612f --- /dev/null +++ b/doc/nrf54h20.dox @@ -0,0 +1,100 @@ +/** +@page nrf54h20_drivers nRF54H20 drivers + +This page lists nrfx driver components supported by the nRF54H20 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + +@{ + +@ref nrf_aar + +@ref nrf_auxpll + +@ref nrf_bellboard + +@ref nrf_cache + +@ref nrf_ccm + +@ref nrf_comp + +@ref nrf_systick + +@ref nrf_ctrlap + +@ref nrf_dppi + +@ref nrf_egu + +@ref nrf_exmif + +@ref nrf_icr + +@ref nrf_gpio + +@ref nrf_gpiote + +@ref nrf_grtc + +@ref nrf_ipct + +@ref nrf_lpcomp + +@ref nrf_lrc + +@ref nrf_memconf + +@ref nrf_mpc + +@ref nrf_mutex + +@ref nrf_mvdma + +@ref nrf_nfct + +@ref nrf_pdm + +@ref nrf_ppib + +@ref nrf_pwm + +@ref nrf_qdec + +@ref nrf_radio + +@ref nrf_ramc + +@ref nrf_resetinfo + +@ref nrf_saadc + +@ref nrf_spim + +@ref nrf_spis + +@ref nrf_spu + +@ref nrf_stm + +@ref nrf_tampc + +@ref nrf_tbm + +@ref nrf_tdm + +@ref nrf_timer + +@ref nrf_twim + +@ref nrf_twis + +@ref nrf_uarte + +@ref nrf_usbhs + +@ref nrf_vpr + +@ref nrf_wdt + +@} +*/ diff --git a/doc/nrf54l15_enga.dox b/doc/nrf54l15_enga.dox new file mode 100644 index 000000000..264b75f7f --- /dev/null +++ b/doc/nrf54l15_enga.dox @@ -0,0 +1,86 @@ +/** +@page nrf54l15_enga_drivers nRF54L15 EngA drivers + +This page lists nrfx driver components supported by the nRF54L15 EngA SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + +@{ + +@ref nrf_aar + +@ref nrf_cache + +@ref nrf_ccm + +@ref nrf_clock + +@ref nrf_comp + +@ref nrf_cracen + +@ref nrf_systick + +@ref nrf_dppi + +@ref nrf_egu + +@ref nrf_glitchdet + +@ref nrf_gpio + +@ref nrf_gpiote + +@ref nrf_grtc + +@ref nrf_i2s + +@ref nrf_icr + +@ref nrf_kmu + +@ref nrf_lpcomp + +@ref nrf_memconf + +@ref nrf_mpc + +@ref nrf_nfct + +@ref nrf_power + +@ref nrf_ppib + +@ref nrf_pwm + +@ref nrf_qdec + +@ref nrf_radio + +@ref nrf_rramc + +@ref nrf_saadc + +@ref nrf_spim + +@ref nrf_spis + +@ref nrf_spu + +@ref nrf_tampc + +@ref nrf_temp + +@ref nrf_timer + +@ref nrf_twim + +@ref nrf_twis + +@ref nrf_uarte + +@ref nrf_vpr + +@ref nrf_wdt + +@} +*/ diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index 633121000..089595190 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -50,7 +50,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "3.4" +PROJECT_NUMBER = "3.5" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/doc/nrfx_api.dox b/doc/nrfx_api.dox index dc81fbe7b..de3c7ac19 100644 --- a/doc/nrfx_api.dox +++ b/doc/nrfx_api.dox @@ -9,6 +9,8 @@ @defgroup nrf_adc ADC +@defgroup nrf_auxpll AUXPLL + @defgroup nrf_bellboard BELLBOARD @defgroup nrf_bprot BPROT diff --git a/doc/sphinx/drivers/auxpll/hal.rst b/doc/sphinx/drivers/auxpll/hal.rst new file mode 100644 index 000000000..7bcd38e26 --- /dev/null +++ b/doc/sphinx/drivers/auxpll/hal.rst @@ -0,0 +1,6 @@ +AUXPLL HAL +========== + +.. doxygengroup:: nrf_auxpll_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/clock/index.rst b/doc/sphinx/drivers/clock/index.rst index ff144abb0..a34908b3a 100644 --- a/doc/sphinx/drivers/clock/index.rst +++ b/doc/sphinx/drivers/clock/index.rst @@ -7,5 +7,6 @@ CLOCK :glob: * + ../auxpll/hal.rst ../hsfll/hal.rst ../oscillators/hal.rst diff --git a/doc/sphinx/drv_supp_matrix.rst b/doc/sphinx/drv_supp_matrix.rst index 4c15fe591..572cfcfb0 100644 --- a/doc/sphinx/drv_supp_matrix.rst +++ b/doc/sphinx/drv_supp_matrix.rst @@ -12,6 +12,8 @@ Driver support overview nrf52833 nrf52840 nrf5340 + nrf54h20 + nrf54l15_enga nrf91_series .. role:: red diff --git a/doc/sphinx/nrf54h20.rst b/doc/sphinx/nrf54h20.rst new file mode 100644 index 000000000..ac63d4504 --- /dev/null +++ b/doc/sphinx/nrf54h20.rst @@ -0,0 +1,5 @@ +nRF54H20 drivers +================ + +.. doxygenpage:: nrf54h20_drivers + :content-only: diff --git a/doc/sphinx/nrf54l15_enga.rst b/doc/sphinx/nrf54l15_enga.rst new file mode 100644 index 000000000..acb4d9935 --- /dev/null +++ b/doc/sphinx/nrf54l15_enga.rst @@ -0,0 +1,5 @@ +nRF54L15 EngA drivers +===================== + +.. doxygenpage:: nrf54l15_enga_drivers + :content-only: diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index 44189efda..22f6dd360 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -232,6 +232,7 @@ nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, * @retval NRFX_SUCCESS Reconfiguration was successful. * @retval NRFX_ERROR_BUSY The driver is during transaction. * @retval NRFX_ERROR_INVALID_STATE The driver is uninitialized. + * @retval NRFX_ERROR_INVALID_PARAM Requested frequency is not available on the specified pins. */ nrfx_err_t nrfx_twim_reconfigure(nrfx_twim_t const * p_instance, nrfx_twim_config_t const * p_config); diff --git a/drivers/include/nrfx_vevif.h b/drivers/include/nrfx_vevif.h index 44d1584d9..89e11fed3 100644 --- a/drivers/include/nrfx_vevif.h +++ b/drivers/include/nrfx_vevif.h @@ -73,7 +73,7 @@ typedef void (*nrfx_vevif_event_handler_t)(uint8_t event_idx, void * p_context); * @retval NRFX_ERROR_INVALID_STATE The driver is already initialized. * Deprecated - use @ref NRFX_ERROR_ALREADY instead. */ -nrfx_err_t nrfx_vevif_init(nrf_vpr_clic_priority_t interrupt_priority, +nrfx_err_t nrfx_vevif_init(uint8_t interrupt_priority, nrfx_vevif_event_handler_t event_handler, void * p_context); diff --git a/drivers/include/nrfx_wdt.h b/drivers/include/nrfx_wdt.h index 46d835c66..c5460846a 100644 --- a/drivers/include/nrfx_wdt.h +++ b/drivers/include/nrfx_wdt.h @@ -232,6 +232,16 @@ nrfx_err_t nrfx_wdt_reconfigure(nrfx_wdt_t const * p_instance, nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_t const * p_instance, nrfx_wdt_channel_id * p_channel_id); +/** + * @brief Function for deallocating all previously allocated watchdog channels. + * + * @note This function can be called when watchdog is stopped, + * that is before @ref nrfx_wdt_enable() or after @ref nrfx_wdt_stop(). + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_wdt_channels_free(nrfx_wdt_t const * p_instance); + /** * @brief Function for starting the watchdog. * diff --git a/drivers/src/nrfx_grtc.c b/drivers/src/nrfx_grtc.c index 3e5153638..cc4be4e87 100644 --- a/drivers/src/nrfx_grtc.c +++ b/drivers/src/nrfx_grtc.c @@ -755,11 +755,14 @@ nrfx_err_t nrfx_grtc_syscounter_cc_absolute_set(nrfx_grtc_channel_t * p_chan_dat cc_channel_prepare(p_chan_data); NRFX_CRITICAL_SECTION_ENTER(); + nrfy_grtc_sys_counter_compare_event_clear(NRF_GRTC, p_chan_data->channel); nrfy_grtc_sys_counter_cc_set(NRF_GRTC, p_chan_data->channel, val); NRFX_CRITICAL_SECTION_EXIT(); - nrfy_grtc_sys_counter_compare_event_int_clear_enable(NRF_GRTC, - p_chan_data->channel, - enable_irq); + + if (enable_irq) + { + nrfy_grtc_int_enable(NRF_GRTC, GRTC_CHANNEL_TO_BITMASK(p_chan_data->channel)); + } NRFX_LOG_INFO("GRTC SYSCOUNTER absolute compare for channel %u set to %u.", (uint32_t)p_chan_data->channel, @@ -785,6 +788,7 @@ nrfx_err_t nrfx_grtc_syscounter_cc_relative_set(nrfx_grtc_channel_t * cc_channel_prepare(p_chan_data); NRFX_CRITICAL_SECTION_ENTER(); + nrfy_grtc_sys_counter_compare_event_clear(NRF_GRTC, p_chan_data->channel); if (NRFX_IS_ENABLED(NRFX_GRTC_CONFIG_SLEEP_ALLOWED) && !is_active()) { grtc_wakeup(); @@ -803,9 +807,10 @@ nrfx_err_t nrfx_grtc_syscounter_cc_relative_set(nrfx_grtc_channel_t * } NRFX_CRITICAL_SECTION_EXIT(); - nrfy_grtc_sys_counter_compare_event_int_clear_enable(NRF_GRTC, - p_chan_data->channel, - enable_irq); + if (enable_irq) + { + nrfy_grtc_int_enable(NRF_GRTC, GRTC_CHANNEL_TO_BITMASK(p_chan_data->channel)); + } NRFX_LOG_INFO("GRTC SYSCOUNTER compare for channel %u set to %u.", (uint32_t)p_chan_data->channel, diff --git a/drivers/src/nrfx_twim.c b/drivers/src/nrfx_twim.c index 486955b65..b15cdcb18 100644 --- a/drivers/src/nrfx_twim.c +++ b/drivers/src/nrfx_twim.c @@ -210,6 +210,11 @@ static bool pins_configure(nrfx_twim_config_t const * p_config) { nrf_gpio_pin_drive_t pin_drive; + if (p_config->skip_psel_cfg && p_config->skip_gpio_cfg) + { + return true; + } + #if NRF_TWIM_HAS_1000_KHZ_FREQ && defined(NRF5340_XXAA) if (p_config->frequency >= NRF_TWIM_FREQ_1000K) { @@ -340,10 +345,19 @@ nrfx_err_t nrfx_twim_reconfigure(nrfx_twim_t const * p_instance, { return NRFX_ERROR_BUSY; } + + nrfx_err_t err_code = NRFX_SUCCESS; nrfy_twim_disable(p_instance->p_twim); - twim_configure(p_instance, p_config); + if (pins_configure(p_config)) + { + twim_configure(p_instance, p_config); + } + else + { + err_code = NRFX_ERROR_INVALID_PARAM; + } nrfy_twim_enable(p_instance->p_twim); - return NRFX_SUCCESS; + return err_code; } void nrfx_twim_uninit(nrfx_twim_t const * p_instance) diff --git a/drivers/src/nrfx_uarte.c b/drivers/src/nrfx_uarte.c index 69ee17b00..6be71445a 100644 --- a/drivers/src/nrfx_uarte.c +++ b/drivers/src/nrfx_uarte.c @@ -1508,6 +1508,10 @@ static void wait_for_rx_completion(NRF_UARTE_Type * p_uarte, while(nrfy_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO) == false) {} + nrfy_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXSTARTED); + nrfy_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX); + nrfy_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO); + rx_flush(p_uarte, p_cb); disable_hw_from_rx(p_uarte); @@ -1633,7 +1637,8 @@ nrfx_err_t nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance, size_t * p_rx_am return NRFX_ERROR_FORBIDDEN; } - if (nrfy_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX)) + if (nrfy_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX) || + !nrfy_uarte_enable_check(p_instance->p_reg)) { if (p_rx_amount) { @@ -1756,17 +1761,17 @@ static void handler_on_rx_done(uarte_control_block_t * p_cb, static void rxto_irq_handler(NRF_UARTE_Type * p_uarte, uarte_control_block_t * p_cb) { - if (RX_CACHE_SUPPORTED && (p_cb->flags & UARTE_FLAG_RX_USE_CACHE)) - { - p_cb->rx.p_cache->user[0] = (nrfy_uarte_buffer_t){ NULL, 0 }; - } - if (p_cb->rx.curr.p_buffer) { handler_on_rx_done(p_cb, p_cb->rx.curr.p_buffer, 0, true); p_cb->rx.curr.p_buffer = NULL; } + if (RX_CACHE_SUPPORTED && (p_cb->flags & UARTE_FLAG_RX_USE_CACHE)) + { + p_cb->rx.p_cache->user[0] = (nrfy_uarte_buffer_t){ NULL, 0 }; + } + rx_flush(p_uarte, p_cb); on_rx_disabled(p_uarte, p_cb, p_cb->rx.flush.length); @@ -1974,22 +1979,29 @@ static void int_trigger_handler(uarte_control_block_t * p_cb) user_handler(p_cb, NRFX_UARTE_EVT_TRIGGER); } +static inline bool event_check_and_clear(NRF_UARTE_Type * p_uarte, nrf_uarte_event_t event) +{ + if (nrfy_uarte_event_check(p_uarte, event)) { + nrfy_uarte_event_clear(p_uarte, event); + return true; + } + + return false; +} + static void irq_handler(NRF_UARTE_Type * p_uarte, uarte_control_block_t * p_cb) { // ENDTX must be handled before TXSTOPPED so we read event status in the reversed order of // handling. - uint32_t mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_TXSTOPPED); - bool txstopped = nrfy_uarte_int_enable_check(p_uarte, mask) && + uint32_t int_mask = nrfy_uarte_int_enable_check(p_uarte, UINT32_MAX); + bool txstopped = (int_mask & NRF_UARTE_INT_TXSTOPPED_MASK) && nrfy_uarte_event_check(p_uarte, NRF_UARTE_EVENT_TXSTOPPED); - - mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDTX); - - bool endtx = nrfy_uarte_int_enable_check(p_uarte, mask) && + bool endtx = (int_mask & NRF_UARTE_INT_ENDTX_MASK) && nrfy_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX); if (p_cb->handler) { - if (nrfy_uarte_events_process(p_uarte, NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ERROR), NULL)) + if (event_check_and_clear(p_uarte, NRF_UARTE_EVENT_ERROR)) { error_irq_handler(p_uarte, p_cb); } @@ -1997,18 +2009,12 @@ static void irq_handler(NRF_UARTE_Type * p_uarte, uarte_control_block_t * p_cb) // ENDRX must be handled before RXSTARTED. RXTO must be handled as the last one. We collect // state of all 3 events before processing to prevent reordering in case of higher interrupt // preemption. We read event status in the reversed order of handling. - bool rxto = nrfy_uarte_events_process(p_uarte, - NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO), - &p_cb->rx.curr); - bool rxstarted = nrfy_uarte_events_process(p_uarte, - NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXSTARTED), - NULL); - bool endrx = nrfy_uarte_events_process(p_uarte, - NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDRX), - &p_cb->rx.curr); + bool rxto = event_check_and_clear(p_uarte, NRF_UARTE_EVENT_RXTO); + bool rxstarted = event_check_and_clear(p_uarte, NRF_UARTE_EVENT_RXSTARTED); + bool endrx = event_check_and_clear(p_uarte, NRF_UARTE_EVENT_ENDRX); // Report RXDRDY only if enabled - if (nrfy_uarte_int_enable_check(p_uarte, NRF_UARTE_INT_RXDRDY_MASK) && + if ((int_mask & NRF_UARTE_INT_RXDRDY_MASK) && nrfy_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXDRDY)) { nrfy_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXDRDY); @@ -2017,6 +2023,14 @@ static void irq_handler(NRF_UARTE_Type * p_uarte, uarte_control_block_t * p_cb) if (endrx) { + // If interrupt was executed exactly when ENDRX occurred it is possible + // that RXSTARTED (which is read before ENDRX) is read as false but it + // actually occurred (if there is a linked reception). Read again to be sure. + if (!rxstarted) + { + rxstarted = event_check_and_clear(p_uarte, NRF_UARTE_EVENT_RXSTARTED); + } + if (endrx_irq_handler(p_uarte, p_cb, rxstarted) == true) { rxstarted = false; diff --git a/drivers/src/nrfx_vevif.c b/drivers/src/nrfx_vevif.c index 708477819..ebd4b815f 100644 --- a/drivers/src/nrfx_vevif.c +++ b/drivers/src/nrfx_vevif.c @@ -59,7 +59,7 @@ typedef struct static nrfx_vevif_cb_t m_cb; -nrfx_err_t nrfx_vevif_init(nrf_vpr_clic_priority_t interrupt_priority, +nrfx_err_t nrfx_vevif_init(uint8_t interrupt_priority, nrfx_vevif_event_handler_t event_handler, void * p_context) { @@ -84,7 +84,6 @@ nrfx_err_t nrfx_vevif_init(nrf_vpr_clic_priority_t interrupt_priority, m_cb.p_context = p_context; m_cb.state = NRFX_DRV_STATE_INITIALIZED; - nrf_vpr_csr_rtperiph_enable_set(true); nrf_vpr_csr_vevif_tasks_clear(NRF_VPR_TASK_TRIGGER_ALL_MASK); for (uint8_t i = 0; i < NRF_VPR_CSR_VEVIF_EVENT_TASK_COUNT; i++) diff --git a/drivers/src/nrfx_wdt.c b/drivers/src/nrfx_wdt.c index 76d69a8c8..14e2b1fba 100644 --- a/drivers/src/nrfx_wdt.c +++ b/drivers/src/nrfx_wdt.c @@ -255,6 +255,23 @@ nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_t const * p_instance, nrfx_wdt_channe return result; } +void nrfx_wdt_channels_free(nrfx_wdt_t const * p_instance) +{ + uint8_t index; + nrfx_wdt_channel_id channel_id; + wdt_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); + + NRFX_CRITICAL_SECTION_ENTER(); + for (index = 0; index < p_cb->alloc_index; index++) + { + channel_id = (nrfx_wdt_channel_id)(NRF_WDT_RR0 + index); + nrfy_wdt_reload_request_disable(p_instance->p_reg, channel_id); + } + p_cb->alloc_index = 0; + NRFX_CRITICAL_SECTION_EXIT(); +} + void nrfx_wdt_channel_feed(nrfx_wdt_t const * p_instance, nrfx_wdt_channel_id channel_id) { NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_POWERED_ON); diff --git a/hal/nrf_aar.h b/hal/nrf_aar.h index aec107800..1530d27c9 100644 --- a/hal/nrf_aar.h +++ b/hal/nrf_aar.h @@ -35,6 +35,9 @@ #define NRF_AAR_H__ #include +#ifdef EASYVDMA_PRESENT +#include +#endif #ifdef __cplusplus extern "C" { @@ -47,12 +50,86 @@ extern "C" { * @brief Hardware access layer for managing the Accelerated Address Resolver (AAR) peripheral. */ +#if defined(AAR_EVENTS_ERROR_EVENTS_ERROR_Msk) || defined(AAR_INTENSET_ERROR_Msk) || \ + defined(AAR_ERRORSTATUS_ERRORSTATUS_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the ERROR event and ERRORSTATUS register. */ +#define NRF_AAR_HAS_ERROR 1 +#else +#define NRF_AAR_HAS_ERROR 0 +#endif + +#if defined(AAR_OUT_AMOUNT_AMOUNT_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the OUT.AMOUNT register. */ +#define NRF_AAR_HAS_OUT_AMOUNT 1 +#else +#define NRF_AAR_HAS_OUT_AMOUNT 0 +#endif + +#if defined(AAR_NIRK_NIRK_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the NIRK register. */ +#define NRF_AAR_HAS_NIRK 1 +#else +#define NRF_AAR_HAS_NIRK 0 +#endif + +#if defined(AAR_IRKPTR_IRKPTR_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the IRKPTR register. */ +#define NRF_AAR_HAS_IRKPTR 1 +#else +#define NRF_AAR_HAS_IRKPTR 0 +#endif + +#if defined(AAR_IN_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the IN.PTR register. */ +#define NRF_AAR_HAS_IN_PTR 1 +#else +#define NRF_AAR_HAS_IN_PTR 0 +#endif + +#if defined(AAR_OUT_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the OUT.PTR register. */ +#define NRF_AAR_HAS_OUT_PTR 1 +#else +#define NRF_AAR_HAS_OUT_PTR 0 +#endif + +#if defined(AAR_ADDRPTR_ADDRPTR_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the ADDRPTR register. */ +#define NRF_AAR_HAS_ADDRPTR 1 +#else +#define NRF_AAR_HAS_ADDRPTR 0 +#endif + +#if defined(AAR_SCRATCHPTR_SCRATCHPTR_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the SCRATCHPTR register. */ +#define NRF_AAR_HAS_SCRATCHPTR 1 +#else +#define NRF_AAR_HAS_SCRATCHPTR 0 +#endif + +#if defined(AAR_STATUS_STATUS_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the STATUS register. */ +#define NRF_AAR_HAS_STATUS 1 +#else +#define NRF_AAR_HAS_STATUS 0 +#endif + +#if defined(AAR_MAXRESOLVED_MAXRESOLVED_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of the MAXRESOLVED register. */ +#define NRF_AAR_HAS_MAXRESOLVED 1 +#else +#define NRF_AAR_HAS_MAXRESOLVED 0 +#endif + /** @brief AAR events. */ typedef enum { NRF_AAR_EVENT_END = offsetof(NRF_AAR_Type, EVENTS_END), ///< Address resolution procedure complete. NRF_AAR_EVENT_RESOLVED = offsetof(NRF_AAR_Type, EVENTS_RESOLVED), ///< Address resolved. NRF_AAR_EVENT_NOTRESOLVED = offsetof(NRF_AAR_Type, EVENTS_NOTRESOLVED), ///< Address not resolved. +#if NRF_AAR_HAS_ERROR + NRF_AAR_EVENT_ERROR = offsetof(NRF_AAR_Type, EVENTS_ERROR), ///< Address resolution procedure aborted due to STOP task or error. +#endif } nrf_aar_event_t; /** @brief AAR interrupts. */ @@ -61,8 +138,22 @@ typedef enum NRF_AAR_INT_END_MASK = AAR_INTENSET_END_Msk, ///< Interrupt on END event. NRF_AAR_INT_RESOLVED_MASK = AAR_INTENSET_RESOLVED_Msk, ///< Interrupt on RESOLVED event. NRF_AAR_INT_NOTRESOLVED_MASK = AAR_INTENSET_NOTRESOLVED_Msk, ///< Interrupt on NOTRESOLVED event. +#if NRF_AAR_HAS_ERROR + NRF_AAR_INT_ERROR_MASK = AAR_INTENSET_ERROR_Msk, ///< Interrupt on NOTRESOLVED event. +#endif } nrf_aar_int_mask_t; +#if NRF_AAR_HAS_ERROR +/** @brief AAR error status when ERROR event is generated. */ +typedef enum +{ + NRF_AAR_ERROR_NO_ERROR = AAR_ERRORSTATUS_ERRORSTATUS_NoError, ///< No errors have occurred. + NRF_AAR_ERROR_PREMATURE_INPTR_END = AAR_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd, ///< End of INPTR job list before data structure was read. + NRF_AAR_ERROR_PREMATURE_OUTPTR_END = AAR_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd, ///< End of OUTPTR job list before data structure was read. + NRF_AAR_ERROR_DMA_ERROR = AAR_ERRORSTATUS_ERRORSTATUS_DmaError, ///< Bus error during DMA access. +} nrf_aar_error_t; +#endif + /** @brief AAR tasks. */ typedef enum { @@ -164,6 +255,18 @@ NRF_STATIC_INLINE void nrf_aar_enable(NRF_AAR_Type * p_reg); */ NRF_STATIC_INLINE void nrf_aar_disable(NRF_AAR_Type * p_reg); +#if NRF_AAR_HAS_ERROR +/** + * @brief Function for getting the error status when ERROR event is generated. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval Error status when the ERROR event is generated. + */ +NRF_STATIC_INLINE nrf_aar_error_t nrf_aar_error_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_ERROR + +#if NRF_AAR_HAS_IRKPTR /** * @brief Function for setting the pointer to the Identity Resolving Keys (IRK) data structure. * @@ -186,7 +289,9 @@ NRF_STATIC_INLINE void nrf_aar_irk_pointer_set(NRF_AAR_Type * p_reg, uint8_t con * @return Pointer to the IRK data structure. */ NRF_STATIC_INLINE uint8_t const * nrf_aar_irk_pointer_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_IRKPTR +#if NRF_AAR_HAS_NIRK /** * @brief Function for setting the number of keys available in the Identity Resolving Keys * data structure. @@ -208,7 +313,30 @@ NRF_STATIC_INLINE void nrf_aar_irk_number_set(NRF_AAR_Type * p_reg, uint8_t irk_ * @return Number of keys in the IRK data structure. */ NRF_STATIC_INLINE uint8_t nrf_aar_irk_number_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_NIRK +#if NRF_AAR_HAS_MAXRESOLVED +/** + * @brief Function for setting maximum number of Identity Resolving Keys to resolve. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] maxresolved Maximum number of Identity Resolving Keys to resolve. + * + * @sa nrf_aar_irk_pointer_set + */ +NRF_STATIC_INLINE void nrf_aar_maxresolved_set(NRF_AAR_Type * p_reg, uint16_t maxresolved); + +/** + * @brief Function for getting maximum number of Identity Resolving Keys to resolve. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Maximum number of Identity Resolving Keys to resolve. + */ +NRF_STATIC_INLINE uint16_t nrf_aar_maxresolved_get(NRF_AAR_Type const * p_reg); +#endif + +#if NRF_AAR_HAS_ADDRPTR /** * @brief Function for setting the pointer to the resolvable address. * @@ -228,7 +356,67 @@ NRF_STATIC_INLINE void nrf_aar_addr_pointer_set(NRF_AAR_Type * p_reg, uint8_t co * @return Pointer to the address to resolve. */ NRF_STATIC_INLINE uint8_t const * nrf_aar_addr_pointer_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_ADDRPTR +#if NRF_AAR_HAS_OUT_PTR +/** + * @brief Function for setting the pointer to a job list containing description to store + * resolved addresses. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_job Pointer to a job list. + */ +NRF_STATIC_INLINE void nrf_aar_out_ptr_set(NRF_AAR_Type * p_reg, + nrf_vdma_job_t const * p_job); + +/** + * @brief Function for getting the pointer to a job list containing description to store + * resolved addresses. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Pointer to the job list. + */ +NRF_STATIC_INLINE nrf_vdma_job_t * nrf_aar_out_ptr_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_OUT_PTR + +#if NRF_AAR_HAS_IN_PTR +/** + * @brief Function for setting the pointer to a job list containing both + * the Hash and Prand parts of the private resolvable address (DEVICEADDR) + * field from the Bluetooth packet, and a number of Identity Resolving Keys (IRK). + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_job Pointer to a job list. + */ +NRF_STATIC_INLINE void nrf_aar_in_ptr_set(NRF_AAR_Type * p_reg, + nrf_vdma_job_t const * p_job); + +/** + * @brief Function for getting the pointer to a job list containing both + * the Hash and Prand parts of the private resolvable address (DEVICEADDR) + * field from the Bluetooth packet, and a number of Identity Resolving Keys (IRK). + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Pointer to the job list. + */ +NRF_STATIC_INLINE nrf_vdma_job_t * nrf_aar_in_ptr_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_IN_PTR + +#if NRF_AAR_HAS_OUT_AMOUNT +/** + * @brief Function for getting number of bytes available in the output data, + * not including the job list structure. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Number of bytes available in the output data. + */ +NRF_STATIC_INLINE uint32_t nrf_aar_out_amount_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_OUT_AMOUNT + +#if NRF_AAR_HAS_SCRATCHPTR /** * @brief Function for setting the pointer to the scratch data area. * @@ -248,7 +436,9 @@ NRF_STATIC_INLINE void nrf_aar_scratch_pointer_set(NRF_AAR_Type * p_reg, uint8_t * @return Pointer to the scratch data area. */ NRF_STATIC_INLINE uint8_t * nrf_aar_scratch_pointer_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_SCRATCHPTR +#if NRF_AAR_HAS_STATUS /** * @brief Function for getting the index of the Identity Resolving Key that was used * the last time an address was resolved. @@ -262,6 +452,7 @@ NRF_STATIC_INLINE uint8_t * nrf_aar_scratch_pointer_get(NRF_AAR_Type const * p_r * @return The index of the IRK that was used the last time an address was resolved. */ NRF_STATIC_INLINE uint8_t nrf_aar_resolution_status_get(NRF_AAR_Type const * p_reg); +#endif // NRF_AAR_HAS_STATUS #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @@ -313,7 +504,7 @@ NRF_STATIC_INLINE void nrf_aar_publish_clear(NRF_AAR_Type * p_reg, NRF_STATIC_INLINE bool nrf_aar_event_check(NRF_AAR_Type const * p_reg, nrf_aar_event_t aar_event) { - return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event); + return nrf_event_check(p_reg, aar_event); } NRF_STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg, @@ -326,7 +517,7 @@ NRF_STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg, NRF_STATIC_INLINE uint32_t nrf_aar_event_address_get(NRF_AAR_Type const * p_reg, nrf_aar_event_t aar_event) { - return (uint32_t)((uint8_t *)p_reg + (uint32_t)aar_event); + return nrf_task_event_address_get(p_reg, aar_event); } NRF_STATIC_INLINE void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask) @@ -365,6 +556,7 @@ NRF_STATIC_INLINE void nrf_aar_disable(NRF_AAR_Type * p_reg) p_reg->ENABLE = AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos; } +#if NRF_AAR_HAS_IRKPTR NRF_STATIC_INLINE void nrf_aar_irk_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * irk_ptr) { p_reg->IRKPTR = (uint32_t)irk_ptr; @@ -374,7 +566,9 @@ NRF_STATIC_INLINE uint8_t const * nrf_aar_irk_pointer_get(NRF_AAR_Type const * p { return (uint8_t const *)(p_reg->IRKPTR); } +#endif // NRF_AAR_HAS_IRKPTR +#if NRF_AAR_HAS_NIRK NRF_STATIC_INLINE void nrf_aar_irk_number_set(NRF_AAR_Type * p_reg, uint8_t irk_num) { p_reg->NIRK = irk_num; @@ -384,7 +578,9 @@ NRF_STATIC_INLINE uint8_t nrf_aar_irk_number_get(NRF_AAR_Type const * p_reg) { return (uint8_t)(p_reg->NIRK); } +#endif // NRF_AAR_HAS_NIRK +#if NRF_AAR_HAS_ADDRPTR NRF_STATIC_INLINE void nrf_aar_addr_pointer_set(NRF_AAR_Type * p_reg, uint8_t const * addr_ptr) { p_reg->ADDRPTR = (uint32_t)addr_ptr; @@ -394,7 +590,9 @@ NRF_STATIC_INLINE uint8_t const * nrf_aar_addr_pointer_get(NRF_AAR_Type const * { return (uint8_t const *)(p_reg->ADDRPTR); } +#endif // NRF_AAR_HAS_ADDRPTR +#if NRF_AAR_HAS_SCRATCHPTR NRF_STATIC_INLINE void nrf_aar_scratch_pointer_set(NRF_AAR_Type * p_reg, uint8_t * scratch_ptr) { p_reg->SCRATCHPTR = (uint32_t)scratch_ptr; @@ -404,11 +602,66 @@ NRF_STATIC_INLINE uint8_t * nrf_aar_scratch_pointer_get(NRF_AAR_Type const * p_r { return (uint8_t *)(p_reg->SCRATCHPTR); } +#endif // NRF_AAR_HAS_SCRATCHPTR +#if NRF_AAR_HAS_STATUS NRF_STATIC_INLINE uint8_t nrf_aar_resolution_status_get(NRF_AAR_Type const * p_reg) { return (uint8_t)(p_reg->STATUS); } +#endif // NRF_AAR_HAS_STATUS + +#if NRF_AAR_HAS_ERROR +NRF_STATIC_INLINE nrf_aar_error_t nrf_aar_error_get(NRF_AAR_Type const * p_reg) +{ + return (nrf_aar_error_t)(p_reg->ERRORSTATUS); +} +#endif // NRF_AAR_HAS_ERROR + +#if NRF_AAR_HAS_MAXRESOLVED +NRF_STATIC_INLINE void nrf_aar_maxresolved_set(NRF_AAR_Type * p_reg, uint16_t maxresolved) +{ + p_reg->MAXRESOLVED = maxresolved; +} + +NRF_STATIC_INLINE uint16_t nrf_aar_maxresolved_get(NRF_AAR_Type const * p_reg) +{ + return (uint16_t)(p_reg->MAXRESOLVED); +} +#endif // NRF_AAR_HAS_MAXRESOLVED + +#if NRF_AAR_HAS_IN_PTR +NRF_STATIC_INLINE void nrf_aar_in_ptr_set(NRF_AAR_Type * p_reg, + nrf_vdma_job_t const * p_job) +{ + p_reg->IN.PTR = (uint32_t)p_job; +} + +NRF_STATIC_INLINE nrf_vdma_job_t * nrf_aar_in_ptr_get(NRF_AAR_Type const * p_reg) +{ + return (nrf_vdma_job_t *)(p_reg->IN.PTR); +} +#endif // NRF_AAR_HAS_IN_PTR + +#if NRF_AAR_HAS_OUT_PTR +NRF_STATIC_INLINE void nrf_aar_out_ptr_set(NRF_AAR_Type * p_reg, + nrf_vdma_job_t const * p_job) +{ + p_reg->OUT.PTR = (uint32_t)p_job; +} + +NRF_STATIC_INLINE nrf_vdma_job_t * nrf_aar_out_ptr_get(NRF_AAR_Type const * p_reg) +{ + return (nrf_vdma_job_t *)(p_reg->OUT.PTR); +} +#endif // NRF_AAR_HAS_OUT_PTR + +#if NRF_AAR_HAS_OUT_AMOUNT +NRF_STATIC_INLINE uint32_t nrf_aar_out_amount_get(NRF_AAR_Type const * p_reg) +{ + return p_reg->OUT.AMOUNT; +} +#endif // NRF_AAR_HAS_OUT_AMOUNT #if defined(DPPI_PRESENT) NRF_STATIC_INLINE void nrf_aar_subscribe_set(NRF_AAR_Type * p_reg, diff --git a/hal/nrf_auxpll.h b/hal/nrf_auxpll.h new file mode 100644 index 000000000..1ff3a52b9 --- /dev/null +++ b/hal/nrf_auxpll.h @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2022 - 2024, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_AUXPLL_H__ +#define NRF_AUXPLL_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_auxpll_hal Auxiliary PLL HAL + * @{ + * @ingroup nrf_clock + * @brief Hardware access layer for managing the Auxiliary Phase Locked Loop (AUXPLL) peripheral. + */ + +/** @brief AUXPLL tasks. */ +typedef enum +{ + NRF_AUXPLL_TASK_START = offsetof(NRF_AUXPLL_Type, TASKS_START), /**< Start the AUXPLL. */ + NRF_AUXPLL_TASK_STOP = offsetof(NRF_AUXPLL_Type, TASKS_STOP), /**< Stop the AUXPLL. */ + NRF_AUXPLL_TASK_FREQ_NEW_FINE = offsetof(NRF_AUXPLL_Type, TASKS_NEWFINEFREQ), /**< Change fine frequency. */ + NRF_AUXPLL_TASK_FREQ_NEW_BASE = offsetof(NRF_AUXPLL_Type, TASKS_NEWBASEFREQ), /**< Change base frequency. */ + NRF_AUXPLL_TASK_FREQ_INC_START = offsetof(NRF_AUXPLL_Type, TASKS_FREQINCSTART), /**< Start automated frequency increment. */ + NRF_AUXPLL_TASK_FREQ_INC_STOP = offsetof(NRF_AUXPLL_Type, TASKS_FREQINCSTOP), /**< Stop automated frequency increment. */ +} nrf_auxpll_task_t; + +/** @brief AUXPLL events. */ +typedef enum +{ + NRF_AUXPLL_EVENT_STARTED = offsetof(NRF_AUXPLL_Type, EVENTS_STARTED), /**< Event indicating that AUXPLL started. */ + NRF_AUXPLL_EVENT_STOPPED = offsetof(NRF_AUXPLL_Type, EVENTS_STOPPED), /**< Event indicating that AUXPLL stopped. */ + NRF_AUXPLL_EVENT_LOCKED = offsetof(NRF_AUXPLL_Type, EVENTS_LOCKED), /**< Event indicating that AUXPLL locked. */ +} nrf_auxpll_event_t; + +/** @brief AUXPLL interrupts. */ +typedef enum +{ + NRF_AUXPLL_INT_STARTED_MASK = AUXPLL_INTEN_STARTED_Msk, /**< AUXPLL interrupt for STARTED event. */ + NRF_AUXPLL_INT_STOPPED_MASK = AUXPLL_INTEN_STOPPED_Msk, /**< AUXPLL interrupt for STOPPED event. */ + NRF_AUXPLL_INT_LOCKED_MASK = AUXPLL_INTEN_LOCKED_Msk /**< AUXPLL interrupt for LOCKED event. */ +} nrf_auxpll_int_mask_t; + +/** @brief AUXPLL STATUS register bit masks. */ +typedef enum +{ + NRF_AUXPLL_STATUS_MODE_MASK = AUXPLL_STATUS_MODE_Msk, /**< AUXPLL mode indication. 1 - Locked mode, 0 - Freerunning mode. */ + NRF_AUXPLL_STATUS_PLL_RUNNING_MASK = AUXPLL_STATUS_PLLRUNNING_Msk, /**< AUXPLL running indication. 1 - PLL running, 0 - PLL not running. */ + MRF_AUXPLL_STATUS_FREQUENCY_ACTUAL_MASK = AUXPLL_STATUS_FREQUENCYACTUAL_Msk /**< Actual fractional PLL divider ratio. */ +} nrf_auxpll_status_mask_t; + +/** @brief AUXPLL output prescaler ratio. */ +typedef enum +{ + NRF_AUXPLL_CTRL_OUTSEL_DIV_DISABLED = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_DivDisabled, /**< Divider disabled. Bypassed external clock still supported. */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_1 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div1, /**< Divide by 1 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_2 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div2, /**< Divide by 2 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_3 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div3, /**< Divide by 3 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_4 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div4, /**< Divide by 4 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_6 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div6, /**< Divide by 6 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_8 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div8, /**< Divide by 8 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_12 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div12, /**< Divide by 12 */ + NRF_AUXPLL_CTRL_OUTSEL_DIV_16 = AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div16, /**< Divide by 16 */ +} nrf_auxpll_ctrl_outsel_t; + +/** @brief AUXPLL freerunning mode control. */ +typedef enum +{ + NRF_AUXPLL_CTRL_MODE_AUTO = AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Auto, /**< Automatically handled by the AUXPLL peripheral. */ + NRF_AUXPLL_CTRL_MODE_FREERUN = AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Freerun, /**< Keep AUXPLL in freerunning mode. */ + NRF_AUXPLL_CTRL_MODE_LOCKED = AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Locked /**< Keep AUXPLL in locked mode. */ +} nrf_auxpll_ctrl_mode_t; + +/** @brief AUXPLL Loop divider base settings. */ +typedef enum +{ + NRF_AUXPLL_DIVIDER_RANGE_LOW = AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Low, /**< Low range divider setting. Fractional divider in the range 3..4 */ + NRF_AUXPLL_DIVIDER_RANGE_MID = AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Mid, /**< Mid range divider setting. Fractional divider in the range 4..5 */ + NRF_AUXPLL_DIVIDER_RANGE_HIGH = AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_High, /**< High range divider setting. Fractional divider in the range 5..6 */ + NRF_AUXPLL_DIVIDER_RANGE_MAX = AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_StaticHigh, /**< Maximum static divider setting. Fractional division not supported. */ +} nrf_auxpll_divider_range_t ; + +/** @brief AUXPLL configuration. */ +typedef struct +{ + uint8_t outdrive; /**< Output buffer drive strength selection. Range 0..3 */ + uint8_t current_tune; /**< Constant current tune for ring oscillator. Range 0..15 */ + bool sdm_off; /**< Turn off sigma delta modulation */ + bool dither_off; /**< Turn off dither in sigma delta modulator */ + nrf_auxpll_divider_range_t range; /**< Loop divider base settings */ +} nrf_auxpll_config_t; + +/** + * @brief Function for activating the specified AUXPLL task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task to be activated. + */ +NRF_STATIC_INLINE void nrf_auxpll_task_trigger(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_task_t task); + +/** + * @brief Function for getting the address of the specified AUXPLL task register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task The specified task. + * + * @return Address of the specified task register. + */ +NRF_STATIC_INLINE uint32_t nrf_auxpll_task_address_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_task_t task); + +/** + * @brief Function for clearing the specified AUXPLL event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event to clear. + */ +NRF_STATIC_INLINE void nrf_auxpll_event_clear(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_event_t event); + +/** + * @brief Function for retrieving the state of the AUXPLL event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event to be checked. + * + * @retval true The event has been generated. + * @retval false The event has not been generated. + */ +NRF_STATIC_INLINE bool nrf_auxpll_event_check(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_event_t event); + +/** + * @brief Function for getting the address of the specified AUXPLL event register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event The specified event. + * + * @return Address of the specified event register. + */ +NRF_STATIC_INLINE uint32_t nrf_auxpll_event_address_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_event_t event); + +/** + * @brief Function for enabling the specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be enabled. + * Use @ref nrf_auxpll_int_mask_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_auxpll_int_enable(NRF_AUXPLL_Type * p_reg, + uint32_t mask); + +/** + * @brief Function for disabling the specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be disabled. + * Use @ref nrf_auxpll_int_mask_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_auxpll_int_disable(NRF_AUXPLL_Type * p_reg, + uint32_t mask); + +/** + * @brief Function for checking if the specified interrupts are enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be checked. + * Use @ref nrf_auxpll_int_mask_t values for bit masking. + * + * @return true requested interrupts are enabled. + * @return false requested interrupts are disabled. + */ +NRF_STATIC_INLINE bool nrf_auxpll_int_enable_check(NRF_AUXPLL_Type const * p_reg, + uint32_t mask); + +/** + * @brief Function for checking if the specified interrupts are pending. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be checked. + * Use @ref nrf_auxpll_int_mask_t values for bit masking. + * + * @return true requested interrupts are pending. + * @return false requested interrupts are not pending. + */ +NRF_STATIC_INLINE bool nrf_auxpll_int_pending_check(NRF_AUXPLL_Type const * p_reg, + uint32_t mask); + +/** + * @brief Function for getting AUXPLL status. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return The AUXPLL STATUS register value. Use @ref nrf_auxpll_status_mask_t values for bit masking. + */ +NRF_STATIC_INLINE uint32_t nrf_auxpll_status_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Function for getting the AUXPLL configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[out] p_cfg Pointer to the structure to be filled with current AUXPLL configuration. + */ +NRF_STATIC_INLINE void nrf_auxpll_config_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_config_t * p_cfg); + +/** + * @brief Function for setting the AUXPLL configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_cfg Pointer to the structure with AUXPLL configuration. + */ +NRF_STATIC_INLINE void nrf_auxpll_config_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_config_t const * p_cfg); + +/** + * @brief Function for setting the AUXPLL ring oscillator core process corner tuning. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value tuning frequency value. + */ +NRF_STATIC_INLINE void nrf_auxpll_trim_ctune_set(NRF_AUXPLL_Type * p_reg, + uint8_t value); + +/** + * @brief Function for getting the AUXPLL ring oscillator core process corner tuning. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return The AUXPLL ring oscillator core process corner tuning value. + */ +NRF_STATIC_INLINE uint8_t nrf_auxpll_trim_ctune_get(NRF_AUXPLL_Type const * p_reg); + + +/** + * @brief Function for setting the AUXPLL fractional PLL divider ratio tuning. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value Fractional divider ratio. + */ +NRF_STATIC_INLINE void nrf_auxpll_ctrl_frequency_set(NRF_AUXPLL_Type * p_reg, + uint16_t value); + +/** + * @brief Function for getting the AUXPLL fractional PLL divider ratio. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Fractional divider ratio. + */ +NRF_STATIC_INLINE uint16_t nrf_auxpll_ctrl_frequency_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Function for setting the AUXPLL frequency increment value. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value Signed 8-bit frequency increment, applied to current value of FREQUENCY register. + */ +NRF_STATIC_INLINE void nrf_auxpll_ctrl_freqinc_set(NRF_AUXPLL_Type * p_reg, + int8_t value); + +/** + * @brief Function for getting the AUXPLL frequency increment value. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Signed 8-bit frequency increment. + */ +NRF_STATIC_INLINE int8_t nrf_auxpll_ctrl_freqinc_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Function for setting the AUXPLL frequency increment period. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value Frequency increment period in 1 us steps. + */ +NRF_STATIC_INLINE void nrf_auxpll_ctrl_freqinc_period_set(NRF_AUXPLL_Type * p_reg, + uint16_t value); + +/** + * @brief Function for getting the AUXPLL frequency increment period value. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Frequency increment period. + */ +NRF_STATIC_INLINE uint16_t nrf_auxpll_ctrl_freqinc_period_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Function for setting the AUXPLL output prescaler. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value Prescaler ratio. + */ +NRF_STATIC_INLINE void nrf_auxpll_ctrl_outsel_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_ctrl_outsel_t value); + +/** + * @brief Function for getting the AUXPLL output prescaler value. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Prescaler ratio. + */ +NRF_STATIC_INLINE nrf_auxpll_ctrl_outsel_t nrf_auxpll_ctrl_outsel_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Function for setting the AUXPLL mode. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] value AUXPLL running mode. + */ +NRF_STATIC_INLINE void nrf_auxpll_ctrl_mode_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_ctrl_mode_t value); + +/** + * @brief Function for getting the AUXPLL mode. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return AUXPLL running mode. + */ +NRF_STATIC_INLINE nrf_auxpll_ctrl_mode_t nrf_auxpll_ctrl_mode_get(NRF_AUXPLL_Type const * p_reg); + +/** + * @brief Enable LOCK for mirrored AUXPLL registers. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_auxpll_lock(NRF_AUXPLL_Type * p_reg); + +/** + * @brief Disable the lock after configuring all AUXPLL mirrored registers. + * + * @details The individual mirrored registers can be updated any time when the lock is disabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRF_STATIC_INLINE void nrf_auxpll_unlock(NRF_AUXPLL_Type * p_reg); + +/** + * @brief Check if mirrored AUXPLL registers are locked. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true The AUXPLL mirrored register lock enabled. + * @retval false The AUXPLL mirrored register lock disabled. + */ +NRF_STATIC_INLINE bool nrf_auxpll_lock_check(NRF_AUXPLL_Type const * p_reg); + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_auxpll_task_trigger(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +NRF_STATIC_INLINE uint32_t nrf_auxpll_task_address_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_task_t task) +{ + return nrf_task_event_address_get(p_reg, task); +} + +NRF_STATIC_INLINE void nrf_auxpll_event_clear(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); +} + +NRF_STATIC_INLINE bool nrf_auxpll_event_check(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_event_t event) +{ + return nrf_event_check(p_reg, event); +} + +NRF_STATIC_INLINE uint32_t nrf_auxpll_event_address_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_event_t event) +{ + return nrf_task_event_address_get(p_reg, event); +} + +NRF_STATIC_INLINE void nrf_auxpll_int_enable(NRF_AUXPLL_Type * p_reg, + uint32_t mask) +{ + p_reg->INTENSET = mask; +} + +NRF_STATIC_INLINE void nrf_auxpll_int_disable(NRF_AUXPLL_Type * p_reg, + uint32_t mask) +{ + p_reg->INTENCLR = mask; +} + +NRF_STATIC_INLINE bool nrf_auxpll_int_enable_check(NRF_AUXPLL_Type const * p_reg, + uint32_t mask) +{ + return p_reg->INTEN & mask; +} + +NRF_STATIC_INLINE bool nrf_auxpll_int_pending_check(NRF_AUXPLL_Type const * p_reg, + uint32_t mask) +{ + return p_reg->INTPEND & mask; +} + +NRF_STATIC_INLINE uint32_t nrf_auxpll_status_get(NRF_AUXPLL_Type const * p_reg) +{ + return p_reg->STATUS; +} + +NRF_STATIC_INLINE void nrf_auxpll_config_get(NRF_AUXPLL_Type const * p_reg, + nrf_auxpll_config_t * p_cfg) +{ + NRFX_ASSERT(p_cfg); + uint32_t reg = p_reg->CONFIG.CFGSTATIC; + + p_cfg->outdrive = + (reg & AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Msk) >> AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Pos; + + p_cfg->current_tune = + (reg & AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Pos; + + p_cfg->sdm_off = + (reg & AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Pos; + + p_cfg->dither_off = + (reg & AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Msk) >> AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Pos; + + p_cfg->range = (nrf_auxpll_divider_range_t)((reg & AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Msk) + >> AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Pos); +} + +NRF_STATIC_INLINE void nrf_auxpll_config_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_config_t const * p_cfg) +{ + NRFX_ASSERT(p_cfg); + + p_reg->CONFIG.CFGSTATIC = + ((p_cfg->outdrive << AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Pos) + & AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Msk) + | ((p_cfg->current_tune << AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Pos) + & AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Msk) + | ((p_cfg->sdm_off << AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Pos) + & AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Msk) + | ((p_cfg->dither_off << AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Pos) + & AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Msk) + | ((p_cfg->range << AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Pos) + & AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Msk); +} + +NRF_STATIC_INLINE void nrf_auxpll_trim_ctune_set(NRF_AUXPLL_Type * p_reg, + uint8_t value) +{ + p_reg->TRIM.CTUNE = value; +} + +NRF_STATIC_INLINE uint8_t nrf_auxpll_trim_ctune_get(NRF_AUXPLL_Type const * p_reg) +{ + return (uint8_t)p_reg->TRIM.CTUNE; +} + +NRF_STATIC_INLINE void nrf_auxpll_ctrl_frequency_set(NRF_AUXPLL_Type * p_reg, + uint16_t value) +{ + p_reg->AUXPLLCTRL.FREQUENCY = value; +} + +NRF_STATIC_INLINE uint16_t nrf_auxpll_ctrl_frequency_get(NRF_AUXPLL_Type const * p_reg) +{ + return (uint16_t)p_reg->AUXPLLCTRL.FREQUENCY; +} + +NRF_STATIC_INLINE void nrf_auxpll_ctrl_freqinc_set(NRF_AUXPLL_Type * p_reg, + int8_t value) +{ + p_reg->AUXPLLCTRL.FREQINC = (uint8_t)value; +} + +NRF_STATIC_INLINE int8_t nrf_auxpll_ctrl_freqinc_get(NRF_AUXPLL_Type const * p_reg) +{ + return (int8_t)p_reg->AUXPLLCTRL.FREQINC; +} + +NRF_STATIC_INLINE void nrf_auxpll_ctrl_freqinc_period_set(NRF_AUXPLL_Type * p_reg, + uint16_t value) +{ + p_reg->AUXPLLCTRL.FREQINCPERIOD = value; +} + +NRF_STATIC_INLINE uint16_t nrf_auxpll_ctrl_freqinc_period_get(NRF_AUXPLL_Type const * p_reg) +{ + return (uint16_t)p_reg->AUXPLLCTRL.FREQINCPERIOD; +} + +NRF_STATIC_INLINE void nrf_auxpll_ctrl_outsel_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_ctrl_outsel_t value) +{ + p_reg->AUXPLLCTRL.OUTSEL = (value << AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Pos); +} + +NRF_STATIC_INLINE nrf_auxpll_ctrl_outsel_t nrf_auxpll_ctrl_outsel_get(NRF_AUXPLL_Type const * p_reg) +{ + return (nrf_auxpll_ctrl_outsel_t)((p_reg->AUXPLLCTRL.OUTSEL & AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Msk) >> + AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Pos); +} + +NRF_STATIC_INLINE void nrf_auxpll_ctrl_mode_set(NRF_AUXPLL_Type * p_reg, + nrf_auxpll_ctrl_mode_t value) +{ + p_reg->AUXPLLCTRL.MODE = value << AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Pos; +} + +NRF_STATIC_INLINE nrf_auxpll_ctrl_mode_t nrf_auxpll_ctrl_mode_get(NRF_AUXPLL_Type const * p_reg) +{ + uint8_t val = (p_reg->AUXPLLCTRL.MODE & AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Msk) >> + AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Pos; + + return (nrf_auxpll_ctrl_mode_t)val; +} + +NRF_STATIC_INLINE void nrf_auxpll_lock(NRF_AUXPLL_Type * p_reg) +{ + p_reg->MIRROR = AUXPLL_MIRROR_LOCK_Enabled; +} + +NRF_STATIC_INLINE void nrf_auxpll_unlock(NRF_AUXPLL_Type * p_reg) +{ + p_reg->MIRROR = AUXPLL_MIRROR_LOCK_Disabled; +} + +NRF_STATIC_INLINE bool nrf_auxpll_lock_check(NRF_AUXPLL_Type const * p_reg) +{ + return ((p_reg->MIRROR) & AUXPLL_MIRROR_LOCK_Enabled); +} + +#endif // NRF_DECLARE_ONLY + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_AUXPLL_H__ diff --git a/hal/nrf_cache.h b/hal/nrf_cache.h index 64fb9e8a8..a6cef2974 100644 --- a/hal/nrf_cache.h +++ b/hal/nrf_cache.h @@ -523,6 +523,15 @@ NRF_STATIC_INLINE bool nrf_cache_is_data_unit_dirty_check(NRF_CACHEINFO_Type con */ NRF_STATIC_INLINE void nrf_cache_lineaddr_set(NRF_CACHE_Type * p_reg, uint32_t addr); +/** + * @brief Function to get the memory address covered by the line to be maintained. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Cache line adress. + */ +NRF_STATIC_INLINE uint32_t nrf_cache_lineaddr_get(NRF_CACHE_Type const * p_reg); + /** * @brief Function for triggering the specified CACHE task. * @@ -869,6 +878,11 @@ NRF_STATIC_INLINE void nrf_cache_lineaddr_set(NRF_CACHE_Type * p_reg, uint32_t a p_reg->LINEADDR = addr; } +NRF_STATIC_INLINE uint32_t nrf_cache_lineaddr_get(NRF_CACHE_Type const * p_reg) +{ + return p_reg->LINEADDR; +} + NRF_STATIC_INLINE void nrf_cache_task_trigger(NRF_CACHE_Type * p_reg, nrf_cache_task_t task) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; diff --git a/hal/nrf_common.h b/hal/nrf_common.h index 592bb4db7..e7075ce2e 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -47,7 +47,7 @@ extern "C" { #endif #ifndef NRFX_CONFIG_API_VER_MINOR -#define NRFX_CONFIG_API_VER_MINOR 2 +#define NRFX_CONFIG_API_VER_MINOR 3 #endif #ifndef NRFX_CONFIG_API_VER_MICRO @@ -129,8 +129,8 @@ extern "C" { #define NRF_PIN_PORT_TO_PIN_NUMBER(pin, port) (((pin) & 0x1F) | ((port) << 5)) #if defined(LUMOS_XXAA) -typedef NRF_DOMAINS_t nrf_domain_t; -typedef NRF_OWNERID_Type nrf_owner_t; +typedef NRF_DOMAINID_Type nrf_domain_t; +typedef NRF_OWNERID_Type nrf_owner_t; #endif #if defined(HALTIUM_XXAA) @@ -241,20 +241,17 @@ NRF_STATIC_INLINE bool nrf_dma_accessible_check(void const * p_reg, void const * #if defined(HALTIUM_XXAA) if (nrf_address_bus_get((uint32_t)p_reg, 0x10000) == 0x8E) { - /* Bitwise operation to unify secure/non-secure memory address */ - uint32_t addr = (uint32_t)p_object & 0xEFFFFFFFu; - /* When peripheral instance is high-speed check whether */ /* p_object is placed in GRAM2x or GRAM0x */ - bool gram0x = (addr >= 0x2F000000u) && (addr < 0x2F038000); - bool gram2x = (addr >= 0x2F880000u) && (addr < 0x2F886200); + bool gram0x = ((uint32_t)p_object & 0xEFF00000) == 0x2F000000; + bool gram2x = ((uint32_t)p_object & 0xEFF80000) == 0x2F880000; return gram0x || gram2x; } else { /* When peripheral instance is low-speed check whether */ /* p_object is placed in GRAM3x */ - return ((((uint32_t)p_object) & 0xEFFF8000u) == 0x2FC00000u); + return ((((uint32_t)p_object) & 0xEFFE0000u) == 0x2FC00000u); } #else (void)p_reg; diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index 0ffeba28c..41ed29987 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -856,8 +856,6 @@ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); */ NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin); -#ifndef NRF_DECLARE_ONLY - /** * @brief Function for extracting port and the relative pin number from the absolute pin number. * @@ -866,6 +864,10 @@ NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin); * * @return Pointer to port register set. */ +NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin); + +#ifndef NRF_DECLARE_ONLY + NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin)); diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index c47550ea2..4d7af8b2f 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -119,9 +119,18 @@ extern "C" { #define NRF_GPIOTE_HAS_LATENCY 0 #endif +#if defined(GPIOTE_IRQ_GROUP) || defined(GPIOTE130_IRQ_GROUP) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether GPIOTE interrupt groups are present. */ +#define NRF_GPIOTE_HAS_INT_GROUPS 1 +#else +#define NRF_GPIOTE_HAS_INT_GROUPS 0 +#endif + #if defined(GPIOTE_IRQ_GROUP) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating which interrupt group to use. Empty if there are no groups. */ #define NRF_GPIOTE_IRQ_GROUP GPIOTE_IRQ_GROUP +#elif defined(GPIOTE130_IRQ_GROUP) +#define NRF_GPIOTE_IRQ_GROUP GPIOTE130_IRQ_GROUP #else #define NRF_GPIOTE_IRQ_GROUP #endif @@ -353,6 +362,46 @@ NRF_STATIC_INLINE void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p_reg, uint32_t mask); +#if NRF_GPIOTE_HAS_INT_GROUPS +/** + * @brief Function for enabling interrupts in the specified group. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] group_idx Index of interrupt group to be enabled. + * @param[in] mask Mask of interrupts to be enabled. + * Use @ref nrf_gpiote_int_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_gpiote_int_group_enable(NRF_GPIOTE_Type * p_reg, + uint8_t group_idx, + uint32_t mask); + +/** + * @brief Function for disabling interrupts in the specified group. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] group_idx Index of interrupt group to be disabled. + * @param[in] mask Mask of interrupts to be disabled. + * Use @ref nrf_gpiote_int_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_gpiote_int_group_disable(NRF_GPIOTE_Type * p_reg, + uint8_t group_idx, + uint32_t mask); + +/** + * @brief Function for checking if the specified interrupts from a given group are enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] group_idx Index of interrupt group to be checked. + * @param[in] mask Mask of interrupts to be checked. + * Use @ref nrf_gpiote_int_t values for bit masking. + * + * @return Mask of enabled interrupts. + */ +NRF_STATIC_INLINE uint32_t nrf_gpiote_int_group_enable_check(NRF_GPIOTE_Type const * p_reg, + uint8_t group_idx, + uint32_t mask); +#endif + #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting the subscribe configuration for a given @@ -619,6 +668,130 @@ NRF_STATIC_INLINE uint32_t nrf_gpiote_int_enable_check(NRF_GPIOTE_Type const * p return p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) & mask; } +#if NRF_GPIOTE_HAS_INT_GROUPS +NRF_STATIC_INLINE void nrf_gpiote_int_group_enable(NRF_GPIOTE_Type * p_reg, + uint8_t group_idx, + uint32_t mask) +{ + switch (group_idx) + { + case 0: + p_reg->INTENSET0 = mask; + break; + case 1: + p_reg->INTENSET1 = mask; + break; +#if defined(GPIOTE_INTENSET2_IN0_Msk) + case 2: + p_reg->INTENSET2 = mask; + break; +#endif +#if defined(GPIOTE_INTENSET3_IN0_Msk) + case 3: + p_reg->INTENSET3 = mask; + break; +#endif +#if defined(GPIOTE_INTENSET4_IN0_Msk) + case 4: + p_reg->INTENSET4 = mask; + break; +#endif +#if defined(GPIOTE_INTENSET5_IN0_Msk) + case 5: + p_reg->INTENSET5 = mask; + break; +#endif +#if defined(GPIOTE_INTENSET6_IN0_Msk) + case 6: + p_reg->INTENSET6 = mask; + break; +#endif + default: + NRFX_ASSERT(false); + break; + } +} + +NRF_STATIC_INLINE void nrf_gpiote_int_group_disable(NRF_GPIOTE_Type * p_reg, + uint8_t group_idx, + uint32_t mask) +{ + switch (group_idx) + { + case 0: + p_reg->INTENCLR0 = mask; + break; + case 1: + p_reg->INTENCLR1 = mask; + break; +#if defined(GPIOTE_INTENCLR2_IN0_Msk) + case 2: + p_reg->INTENCLR2 = mask; + break; +#endif +#if defined(GPIOTE_INTENCLR3_IN0_Msk) + case 3: + p_reg->INTENCLR3 = mask; + break; +#endif +#if defined(GPIOTE_INTENCLR4_IN0_Msk) + case 4: + p_reg->INTENCLR4 = mask; + break; +#endif +#if defined(GPIOTE_INTENCLR5_IN0_Msk) + case 5: + p_reg->INTENCLR5 = mask; + break; +#endif +#if defined(GPIOTE_INTENCLR6_IN0_Msk) + case 6: + p_reg->INTENCLR6 = mask; + break; +#endif + default: + NRFX_ASSERT(false); + break; + } +} + +NRF_STATIC_INLINE uint32_t nrf_gpiote_int_group_enable_check(NRF_GPIOTE_Type const * p_reg, + uint8_t group_idx, + uint32_t mask) +{ + switch (group_idx) + { + case 0: + return p_reg->INTENSET0 & mask; + case 1: + return p_reg->INTENSET1 & mask; +#if defined(GPIOTE_INTENSET2_IN0_Msk) + case 2: + return p_reg->INTENSET2 & mask; +#endif +#if defined(GPIOTE_INTENSET3_IN0_Msk) + case 3: + return p_reg->INTENSET3 & mask; +#endif +#if defined(GPIOTE_INTENSET4_IN0_Msk) + case 4: + return p_reg->INTENSET4 & mask; +#endif +#if defined(GPIOTE_INTENSET5_IN0_Msk) + case 5: + return p_reg->INTENSET5 & mask; +#endif +#if defined(GPIOTE_INTENSET6_IN0_Msk) + case 6: + return p_reg->INTENSET6 & mask; +#endif + default: + NRFX_ASSERT(false); + return 0; + } +} +#endif + #if defined(DPPI_PRESENT) NRF_STATIC_INLINE void nrf_gpiote_subscribe_set(NRF_GPIOTE_Type * p_reg, nrf_gpiote_task_t task, diff --git a/hal/nrf_grtc.h b/hal/nrf_grtc.h index 448991c28..653b452ba 100644 --- a/hal/nrf_grtc.h +++ b/hal/nrf_grtc.h @@ -240,7 +240,11 @@ typedef enum #endif #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18 NRF_GRTC_TASK_CAPTURE_18 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[18]), /**< Capture the counter value on channel 18. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19 NRF_GRTC_TASK_CAPTURE_19 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[19]), /**< Capture the counter value on channel 19. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20 NRF_GRTC_TASK_CAPTURE_20 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[20]), /**< Capture the counter value on channel 20. */ NRF_GRTC_TASK_CAPTURE_21 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[21]), /**< Capture the counter value on channel 21. */ NRF_GRTC_TASK_CAPTURE_22 = offsetof(NRF_GRTC_Type, TASKS_CAPTURE[22]), /**< Capture the counter value on channel 22. */ @@ -275,7 +279,11 @@ typedef enum #endif #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18 NRF_GRTC_EVENT_COMPARE_18 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[18]), /**< Compare 18 event. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19 NRF_GRTC_EVENT_COMPARE_19 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[19]), /**< Compare 19 event. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20 NRF_GRTC_EVENT_COMPARE_20 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[20]), /**< Compare 20 event. */ NRF_GRTC_EVENT_COMPARE_21 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[21]), /**< Compare 21 event. */ NRF_GRTC_EVENT_COMPARE_22 = offsetof(NRF_GRTC_Type, EVENTS_COMPARE[22]), /**< Compare 22 event. */ @@ -333,7 +341,11 @@ typedef enum #endif #if NRF_GRTC_SYSCOUNTER_CC_COUNT > 18 NRF_GRTC_INT_COMPARE18_MASK = GRTC_INTENSET0_COMPARE18_Msk, /**< GRTC interrupt from compare event on channel 18. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 19 NRF_GRTC_INT_COMPARE19_MASK = GRTC_INTENSET0_COMPARE19_Msk, /**< GRTC interrupt from compare event on channel 19. */ +#endif +#if NRF_GRTC_SYSCOUNTER_CC_COUNT > 20 NRF_GRTC_INT_COMPARE20_MASK = GRTC_INTENSET0_COMPARE20_Msk, /**< GRTC interrupt from compare event on channel 20. */ NRF_GRTC_INT_COMPARE21_MASK = GRTC_INTENSET0_COMPARE21_Msk, /**< GRTC interrupt from compare event on channel 21. */ NRF_GRTC_INT_COMPARE22_MASK = GRTC_INTENSET0_COMPARE22_Msk, /**< GRTC interrupt from compare event on channel 22. */ diff --git a/hal/nrf_lrcconf.h b/hal/nrf_lrcconf.h index 9768f6e20..b63f888d8 100644 --- a/hal/nrf_lrcconf.h +++ b/hal/nrf_lrcconf.h @@ -52,6 +52,13 @@ extern "C" { /** @brief Size of AXI bridge waitstates array. */ #define NRF_LRCCONF_AXI_WAITSTATES_ARRAY_SIZE LRCCONF_AX2XWAITSTATES_MaxCount +#if defined(LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether HFXO requesting is present. */ +#define NRF_LRCCONF_HAS_HFXO 1 +#else +#define NRF_LRCCONF_HAS_HFXO 0 +#endif + /** @brief Tasks. */ typedef enum { @@ -75,6 +82,10 @@ typedef enum NRF_LRCCONF_TASK_CONSTLAT_DISABLE = offsetof(NRF_LRCCONF_Type, TASKS_CONSTLAT.DISABLE), /**< Disable constant latency mode. */ NRF_LRCCONF_TASK_SYSTEMOFFNOTREADY = offsetof(NRF_LRCCONF_Type, TASKS_SYSTEMOFF.NOTREADY), /**< Indicate being not ready to system off .*/ NRF_LRCCONF_TASK_SYSTEMOFFREADY = offsetof(NRF_LRCCONF_Type, TASKS_SYSTEMOFF.READY), /**< Indicate being ready to system off .*/ +#if NRF_LRCCONF_HAS_HFXO + NRF_LRCCONF_TASK_REQHFXO = offsetof(NRF_LRCCONF_Type, TASKS_REQHFXO), /**< Request HFXO. */ + NRF_LRCCONF_TASK_STOPREQHFXO = offsetof(NRF_LRCCONF_Type, TASKS_STOPREQHFXO), /**< Stop requesting HFXO. */ +#endif } nrf_lrcconf_task_t; /** @brief Events. */ @@ -88,6 +99,9 @@ typedef enum NRF_LRCCONF_EVENT_CLKSTARTED_5 = offsetof(NRF_LRCCONF_Type, EVENTS_CLKSRCSTARTED[5]), /**< Clock 5 started. */ NRF_LRCCONF_EVENT_CLKSTARTED_6 = offsetof(NRF_LRCCONF_Type, EVENTS_CLKSRCSTARTED[6]), /**< Clock 6 started. */ NRF_LRCCONF_EVENT_CLKSTARTED_7 = offsetof(NRF_LRCCONF_Type, EVENTS_CLKSRCSTARTED[7]), /**< Clock 7 started. */ +#if NRF_LRCCONF_HAS_HFXO + NRF_LRCCONF_EVENT_HFXOSTARTED = offsetof(NRF_LRCCONF_Type, EVENTS_HFXOSTARTED), /**< HFXO started. */ +#endif } nrf_lrcconf_event_t; /** @brief Clock sources. */ diff --git a/hal/nrf_ppib.h b/hal/nrf_ppib.h index 8e5db813a..cc977c2fd 100644 --- a/hal/nrf_ppib.h +++ b/hal/nrf_ppib.h @@ -127,6 +127,11 @@ typedef enum NRF_PPIB_EVENT_RECEIVE_31 = offsetof(NRF_PPIB_Type, EVENTS_RECEIVE[31]), /**< Receive 31 event. */ } nrf_ppib_event_t; +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + /** @brief Send task mask. */ typedef enum { @@ -164,6 +169,10 @@ typedef enum NRF_PPIB_SEND_31_MASK = PPIB_OVERFLOW_SEND_SEND31_Msk, /* Send task 31 mask. */ } nrf_ppib_send_mask_t; +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + /** * @brief Function for returning the specified PPIB SEND task. * diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index fb69577cb..ee90fcae3 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -54,7 +54,8 @@ extern "C" { #define NRF_PWM_HAS_DMA_REG 0 #endif -#if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__) +#if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || \ + defined(PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether shorting SEQSTART task with LOOPSDONE event is available. */ #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 1 #else @@ -143,13 +144,16 @@ typedef enum /** @brief PWM shortcuts. */ typedef enum { - NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task. - NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task. -#if NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART - NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task. - NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task. + NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task. + NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task. +#if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__) + NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task. +#else + NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[0].START task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[1].START task. #endif - NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task. + NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task. } nrf_pwm_short_mask_t; /** @brief PWM modes of operation. */ @@ -534,19 +538,17 @@ NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t const * p_values); -#if NRF_PWM_HAS_SEQ_CNT /** * @brief Function for modifying the total number of duty cycle values * in the specified sequence. * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] seq_id Identifier of the sequence (0 or 1). - * @param[in] length Number of duty cycle values. + * @param[in] length Number of duty cycle values (in 16-bit half words). */ NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t length); -#endif /** * @brief Function for modifying the additional number of PWM periods spent @@ -763,9 +765,7 @@ NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, NRFX_ASSERT(p_seq != NULL); nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw); -#if NRF_PWM_HAS_SEQ_CNT nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length); -#endif nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats); nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay); } @@ -783,17 +783,20 @@ NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, #endif } -#if NRF_PWM_HAS_SEQ_CNT NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t length) { NRFX_ASSERT(seq_id <= 1); NRFX_ASSERT(length != 0); +#if NRF_PWM_HAS_DMA_REG + NRFX_ASSERT(length * sizeof(uint16_t) <= PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk); + p_reg->DMA.SEQ[seq_id].MAXCNT = length * sizeof(uint16_t); +#else NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk); p_reg->SEQ[seq_id].CNT = length; -} #endif +} NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, uint8_t seq_id, diff --git a/hal/nrf_resetinfo.h b/hal/nrf_resetinfo.h index b7d6b3a74..9d3a56e0b 100644 --- a/hal/nrf_resetinfo.h +++ b/hal/nrf_resetinfo.h @@ -61,13 +61,20 @@ extern "C" { #define NRF_RESETINFO_HAS_MULTIPLE_SECWDT 0 #endif -#if defined(RESETINFO_MASKLOCKUP_MASK_Mask) || defined(__NRFX_DOXYGEN__) +#if defined(RESETINFO_MASKLOCKUP_MASK_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether CPU lockup signal masking is present. */ #define NRF_RESETINFO_HAS_MASKLOCKUP 1 #else #define NRF_RESETINFO_HAS_MASKLOCKUP 0 #endif +#if defined(RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether CROSSDOMAIN local reset reason is present. */ +#define NRF_RESETINFO_HAS_LOCAL_CROSSDOMAIN 1 +#else +#define NRF_RESETINFO_HAS_LOCAL_CROSSDOMAIN 0 +#endif + #if defined(RESETINFO_ERROR_STATUS_ERRORSTATUS_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Maximum value of error status. */ #define NRF_RESETINFO_ERROR_STATUS_MAX RESETINFO_ERROR_STATUS_ERRORSTATUS_Msk @@ -106,7 +113,9 @@ typedef enum NRF_RESETINFO_RESETREAS_LOCAL_DOGNS_MASK = RESETINFO_RESETREAS_LOCAL_DOGNS_Msk, /**< Reset from the local non-secure watchdog timer. */ NRF_RESETINFO_RESETREAS_LOCAL_SREQ_MASK = RESETINFO_RESETREAS_LOCAL_SREQ_Msk, /**< Reset from the local soft reset request. */ NRF_RESETINFO_RESETREAS_LOCAL_LOCKUP_MASK = RESETINFO_RESETREAS_LOCAL_LOCKUP_Msk, /**< Reset from local CPU lockup. */ +#if NRF_RESETINFO_HAS_LOCAL_CROSSDOMAIN NRF_RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_MASK = RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Msk, /**< Reset due to cross domain reset source. */ +#endif NRF_RESETINFO_RESETREAS_LOCAL_UNRETAINED_MASK = RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Msk, /**< Reset due to wake from unretained state. */ } nrf_resetinfo_resetreas_local_mask_t; diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index 8ca735475..1e79f163b 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -225,12 +225,24 @@ typedef enum #endif #if defined(SAADC_CH_CONFIG_GAIN_Gain1_4) || defined(__NRFX_DOXYGEN__) NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4. +#elif defined(SAADC_CH_CONFIG_GAIN_Gain2_8) || defined(__NRFX_DOXYGEN__) + NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain2_8, ///< Gain factor 1/4. +#endif +#if defined(SAADC_CH_CONFIG_GAIN_Gain2_7) || defined(__NRFX_DOXYGEN__) + NRF_SAADC_GAIN2_7 = SAADC_CH_CONFIG_GAIN_Gain2_7, ///< Gain factor 2/7. #endif #if defined(SAADC_CH_CONFIG_GAIN_Gain1_3) || defined(__NRFX_DOXYGEN__) NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3. +#elif defined(SAADC_CH_CONFIG_GAIN_Gain2_6) || defined(__NRFX_DOXYGEN__) + NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain2_6, ///< Gain factor 1/3. +#endif +#if defined(SAADC_CH_CONFIG_GAIN_Gain2_5) || defined(__NRFX_DOXYGEN__) + NRF_SAADC_GAIN2_5 = SAADC_CH_CONFIG_GAIN_Gain2_5, ///< Gain factor 2/5. #endif #if defined(SAADC_CH_CONFIG_GAIN_Gain1_2) || defined(__NRFX_DOXYGEN__) NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2. +#elif defined(SAADC_CH_CONFIG_GAIN_Gain2_4) || defined(__NRFX_DOXYGEN__) + NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain2_4, ///< Gain factor 1/2. #endif #if defined(SAADC_CH_CONFIG_GAIN_Gain2_3) || defined(__NRFX_DOXYGEN__) NRF_SAADC_GAIN2_3 = SAADC_CH_CONFIG_GAIN_Gain2_3, ///< Gain factor 2/3. diff --git a/hal/nrf_spu.h b/hal/nrf_spu.h index 7f71c29d8..ed0ef2f3d 100644 --- a/hal/nrf_spu.h +++ b/hal/nrf_spu.h @@ -54,6 +54,16 @@ extern "C" { #define NRF_SPU_HAS_PERIPHERAL_ACCESS 0 #endif +#if defined(SPU_PERIPHACCERR_INFO_OWNERID_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Symbol indicating whether register containing information about the transaction + * that caused peripheral access error is present. + */ +#define NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO 1 +#else +#define NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO 0 +#endif + #if defined(SPU_PERIPH_PERM_OWNERPROG_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Presence of ownership feature. */ #define NRF_SPU_HAS_OWNERSHIP 1 @@ -498,7 +508,7 @@ NRF_STATIC_INLINE void nrf_spu_extdomain_set(NRF_SPU_Type * p_reg, */ NRF_STATIC_INLINE uint32_t nrf_spu_periphaccerr_address_get(NRF_SPU_Type const * p_reg); -#if NRF_SPU_HAS_OWNERSHIP +#if NRF_SPU_HAS_OWNERSHIP && NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO /** * @brief Function for getting the owner ID of the security violation. * @@ -999,7 +1009,7 @@ NRF_STATIC_INLINE uint32_t nrf_spu_periphaccerr_address_get(NRF_SPU_Type const * return p_reg->PERIPHACCERR.ADDRESS; } -#if NRF_SPU_HAS_OWNERSHIP +#if NRF_SPU_HAS_OWNERSHIP && NRF_SPU_HAS_PERIPHERAL_ACCESS_ERROR_INFO NRF_STATIC_INLINE nrf_owner_t nrf_spu_periphaccerr_ownerid_get(NRF_SPU_Type const * p_reg) { return (nrf_owner_t)p_reg->PERIPHACCERR.INFO; diff --git a/hal/nrf_tampc.h b/hal/nrf_tampc.h index e8c6cd554..83a9e8c6e 100644 --- a/hal/nrf_tampc.h +++ b/hal/nrf_tampc.h @@ -84,6 +84,20 @@ extern "C" { #define NRF_TAMPC_HAS_ERASE_PROTECTOR 0 #endif +#if defined(TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether TAMPC external tamper switch protector is present. */ +#define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR 1 +#else +#define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR 0 +#endif + +#if defined(TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether AP secure priviliged invasive debug detector is present. */ +#define NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR 1 +#else +#define NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR 0 +#endif + #if defined(TAMPC_ENABLE_ACTIVESHIELD_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether the availability to enable the TAMPC detectors feature is present. */ #define NRF_TAMPC_HAS_DETECTORS_ENABLE 1 @@ -105,6 +119,13 @@ extern "C" { #define NRF_TAMPC_HAS_WARMBOOT 0 #endif +#if defined(TAMPC_STATUS_TAMPERSWITCH_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether TAMPC external tamper switch detector is present. */ +#define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR 1 +#else +#define NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR 0 +#endif + /** @brief TAMPC events. */ typedef enum { @@ -146,7 +167,9 @@ typedef enum typedef enum { NRF_TAMPC_DETECTOR_ACTIVE_SHIELD = TAMPC_STATUS_ACTIVESHIELD_Msk, ///< Active shield error detector. +#if NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_DETECTOR NRF_TAMPC_DETECTOR_TAMPER_SWITCH = TAMPC_STATUS_TAMPERSWITCH_Msk, ///< External tamper switch error detector. +#endif NRF_TAMPC_DETECTOR_PROTECTED_SIGNAL = TAMPC_STATUS_PROTECT_Msk, ///< Protected signals error detector. NRF_TAMPC_DETECTOR_CRACEN = TAMPC_STATUS_CRACENTAMP_Msk, ///< CRACEN error detector. NRF_TAMPC_DETECTOR_GLITCH_DOMAIN_SLOW = TAMPC_STATUS_GLITCHSLOWDOMAIN0_Msk, ///< Slow domain glitch error detector. @@ -161,7 +184,9 @@ typedef enum typedef enum { NRF_TAMPC_PROTECT_ACTIVE_SHIELD = offsetof(NRF_TAMPC_Type, PROTECT.ACTIVESHIELD), ///< Control register for active shield detector enable signal. +#if NRF_TAMPC_HAS_EXTERNAL_TAMPERSWITCH_PROTECTOR NRF_TAMPC_PROTECT_TAMPER_SWITCH = offsetof(NRF_TAMPC_Type, PROTECT.TAMPERSWITCH), ///< Control register for external tamper switch enable signal. +#endif NRF_TAMPC_PROTECT_CRACEN = offsetof(NRF_TAMPC_Type, PROTECT.CRACENTAMP), ///< Control register for CRACEN tamper detector enable signal. NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW = offsetof(NRF_TAMPC_Type, PROTECT.GLITCHSLOWDOMAIN), ///< Control register for slow domain glitch detectors enable signal. NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST = offsetof(NRF_TAMPC_Type, PROTECT.GLITCHFASTDOMAIN), ///< Control register for fast domain glitch detectors enable signal. @@ -1022,6 +1047,7 @@ NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_value_set(NRF_TAMPC_Type * p_reg, << TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos)) | NRF_TAMPC_KEY_MASK; break; +#if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR case NRF_TAMPC_DEBUG_TYPE_SPIDEN: #if NRF_TAMPC_KEY_MASK p_reg->PROTECT.AP[domain].SPIDEN.CTRL = @@ -1036,6 +1062,7 @@ NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_value_set(NRF_TAMPC_Type * p_reg, << TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos)) | NRF_TAMPC_KEY_MASK; break; +#endif default: NRFX_ASSERT(0); } @@ -1054,10 +1081,12 @@ NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_value_get(NRF_TAMPC_Type const * p_reg, return ((p_reg->PROTECT.AP[domain].DBGEN.CTRL & TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk) >> TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos); +#if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR case NRF_TAMPC_DEBUG_TYPE_SPIDEN: return ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL & TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk) >> TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos); +#endif default: NRFX_ASSERT(0); return false; @@ -1088,6 +1117,7 @@ NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_lock_set(NRF_TAMPC_Type * p_reg, << TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos)) | NRF_TAMPC_KEY_MASK; break; +#if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR case NRF_TAMPC_DEBUG_TYPE_SPIDEN: #if NRF_TAMPC_KEY_MASK p_reg->PROTECT.AP[domain].SPIDEN.CTRL = @@ -1102,6 +1132,7 @@ NRF_STATIC_INLINE void nrf_tampc_ap_ctrl_lock_set(NRF_TAMPC_Type * p_reg, << TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos)) | NRF_TAMPC_KEY_MASK; break; +#endif default: NRFX_ASSERT(0); } @@ -1120,10 +1151,12 @@ NRF_STATIC_INLINE bool nrf_tampc_ap_ctrl_lock_get(NRF_TAMPC_Type const * p_reg, return ((p_reg->PROTECT.AP[domain].DBGEN.CTRL & TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Msk) >> TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos); +#if NRF_TAMPC_HAS_AP_SPIDEN_PROTECTOR case NRF_TAMPC_DEBUG_TYPE_SPIDEN: return ((p_reg->PROTECT.AP[domain].SPIDEN.CTRL & TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Msk) >> TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos); +#endif default: NRFX_ASSERT(0); return false; diff --git a/hal/nrf_vpr.h b/hal/nrf_vpr.h index a9c93fb07..dcd4b0e71 100644 --- a/hal/nrf_vpr.h +++ b/hal/nrf_vpr.h @@ -53,14 +53,27 @@ extern "C" { /** @brief Macro for creating the interrupt bitmask for all event channels */ #define NRF_VPR_ALL_CHANNELS_INT_MASK \ ((uint32_t) (((1ULL << NRF_VPR_EVENTS_TRIGGERED_COUNT) - 1) \ - << VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos)) + << VPR_EVENTS_TRIGGERED_MinIndex)) /** @brief Macro used as an mask to clear all triggered interrupts within CSR */ #define NRF_VPR_TASK_TRIGGER_ALL_MASK UINT32_MAX +/** @brief Symbol specifying minimal index of TRIGGERED events array that is implemented. */ +#define NRF_VPR_EVENTS_TRIGGERED_MIN VPR_EVENTS_TRIGGERED_MinIndex + +/** @brief Symbol specifying maximal index of TRIGGERED events array that is implemented. */ +#define NRF_VPR_EVENTS_TRIGGERED_MAX VPR_EVENTS_TRIGGERED_MaxIndex + +/** @brief Symbol specifying minimal index of TRIGGER tasks array that is implemented. */ +#define NRF_VPR_TASKS_TRIGGER_MIN VPR_TASKS_TRIGGER_MinIndex + +/** @brief Symbol specifying maximal index of TRIGGER tasks array that is implemented. */ +#define NRF_VPR_TASKS_TRIGGER_MAX VPR_TASKS_TRIGGER_MaxIndex + /** @brief VPR events. */ typedef enum { +#if NRF_VPR_EVENTS_TRIGGERED_MIN < 16 NRF_VPR_EVENT_TRIGGERED_0 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[0]), /**< Triggered 0 event.*/ NRF_VPR_EVENT_TRIGGERED_1 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[1]), /**< Triggered 1 event.*/ NRF_VPR_EVENT_TRIGGERED_2 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[2]), /**< Triggered 2 event.*/ @@ -77,6 +90,7 @@ typedef enum NRF_VPR_EVENT_TRIGGERED_13 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[13]), /**< Triggered 13 event.*/ NRF_VPR_EVENT_TRIGGERED_14 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[14]), /**< Triggered 14 event.*/ NRF_VPR_EVENT_TRIGGERED_15 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[15]), /**< Triggered 15 event.*/ +#endif NRF_VPR_EVENT_TRIGGERED_16 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[16]), /**< Triggered 16 event.*/ NRF_VPR_EVENT_TRIGGERED_17 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[17]), /**< Triggered 17 event.*/ NRF_VPR_EVENT_TRIGGERED_18 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[18]), /**< Triggered 18 event.*/ @@ -84,6 +98,7 @@ typedef enum NRF_VPR_EVENT_TRIGGERED_20 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[20]), /**< Triggered 20 event.*/ NRF_VPR_EVENT_TRIGGERED_21 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[21]), /**< Triggered 21 event.*/ NRF_VPR_EVENT_TRIGGERED_22 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[22]), /**< Triggered 22 event.*/ +#if NRF_VPR_EVENTS_TRIGGERED_MAX > 22 NRF_VPR_EVENT_TRIGGERED_23 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[23]), /**< Triggered 23 event.*/ NRF_VPR_EVENT_TRIGGERED_24 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[24]), /**< Triggered 24 event.*/ NRF_VPR_EVENT_TRIGGERED_25 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[25]), /**< Triggered 25 event.*/ @@ -93,11 +108,13 @@ typedef enum NRF_VPR_EVENT_TRIGGERED_29 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[29]), /**< Triggered 29 event.*/ NRF_VPR_EVENT_TRIGGERED_30 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[30]), /**< Triggered 30 event.*/ NRF_VPR_EVENT_TRIGGERED_31 = offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[31]), /**< Triggered 31 event.*/ +#endif } nrf_vpr_event_t; /** @brief VPR interrupts. */ typedef enum { +#if NRF_VPR_EVENTS_TRIGGERED_MIN < 16 NRF_VPR_INT_TRIGGERED_0_MASK = VPR_INTENSET_TRIGGERED0_Msk, /**< Triggered 0 interrupt mask. */ NRF_VPR_INT_TRIGGERED_1_MASK = VPR_INTENSET_TRIGGERED1_Msk, /**< Triggered 1 interrupt mask. */ NRF_VPR_INT_TRIGGERED_2_MASK = VPR_INTENSET_TRIGGERED2_Msk, /**< Triggered 2 interrupt mask. */ @@ -114,6 +131,7 @@ typedef enum NRF_VPR_INT_TRIGGERED_13_MASK = VPR_INTENSET_TRIGGERED13_Msk, /**< Triggered 13 interrupt mask. */ NRF_VPR_INT_TRIGGERED_14_MASK = VPR_INTENSET_TRIGGERED14_Msk, /**< Triggered 14 interrupt mask. */ NRF_VPR_INT_TRIGGERED_15_MASK = VPR_INTENSET_TRIGGERED15_Msk, /**< Triggered 15 interrupt mask. */ +#endif NRF_VPR_INT_TRIGGERED_16_MASK = VPR_INTENSET_TRIGGERED16_Msk, /**< Triggered 16 interrupt mask. */ NRF_VPR_INT_TRIGGERED_17_MASK = VPR_INTENSET_TRIGGERED17_Msk, /**< Triggered 17 interrupt mask. */ NRF_VPR_INT_TRIGGERED_18_MASK = VPR_INTENSET_TRIGGERED18_Msk, /**< Triggered 18 interrupt mask. */ @@ -121,6 +139,7 @@ typedef enum NRF_VPR_INT_TRIGGERED_20_MASK = VPR_INTENSET_TRIGGERED20_Msk, /**< Triggered 20 interrupt mask. */ NRF_VPR_INT_TRIGGERED_21_MASK = VPR_INTENSET_TRIGGERED21_Msk, /**< Triggered 21 interrupt mask. */ NRF_VPR_INT_TRIGGERED_22_MASK = VPR_INTENSET_TRIGGERED22_Msk, /**< Triggered 22 interrupt mask. */ +#if NRF_VPR_EVENTS_TRIGGERED_MAX > 22 NRF_VPR_INT_TRIGGERED_23_MASK = VPR_INTENSET_TRIGGERED23_Msk, /**< Triggered 23 interrupt mask. */ NRF_VPR_INT_TRIGGERED_24_MASK = VPR_INTENSET_TRIGGERED24_Msk, /**< Triggered 24 interrupt mask. */ NRF_VPR_INT_TRIGGERED_25_MASK = VPR_INTENSET_TRIGGERED25_Msk, /**< Triggered 25 interrupt mask. */ @@ -130,11 +149,13 @@ typedef enum NRF_VPR_INT_TRIGGERED_29_MASK = VPR_INTENSET_TRIGGERED29_Msk, /**< Triggered 29 interrupt mask. */ NRF_VPR_INT_TRIGGERED_30_MASK = VPR_INTENSET_TRIGGERED30_Msk, /**< Triggered 30 interrupt mask. */ NRF_VPR_INT_TRIGGERED_31_MASK = VPR_INTENSET_TRIGGERED31_Msk, /**< Triggered 31 interrupt mask. */ +#endif } nrf_vpr_int_mask_t; /** @brief VPR tasks. */ typedef enum { +#if NRF_VPR_TASKS_TRIGGER_MIN < 16 NRF_VPR_TASK_TRIGGER_0 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[0]), /**< Trigger 0 task. */ NRF_VPR_TASK_TRIGGER_1 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[1]), /**< Trigger 1 task. */ NRF_VPR_TASK_TRIGGER_2 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[2]), /**< Trigger 2 task. */ @@ -151,6 +172,7 @@ typedef enum NRF_VPR_TASK_TRIGGER_13 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[13]), /**< Trigger 13 task. */ NRF_VPR_TASK_TRIGGER_14 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[14]), /**< Trigger 14 task. */ NRF_VPR_TASK_TRIGGER_15 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[15]), /**< Trigger 15 task. */ +#endif NRF_VPR_TASK_TRIGGER_16 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[16]), /**< Trigger 16 task. */ NRF_VPR_TASK_TRIGGER_17 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[17]), /**< Trigger 17 task. */ NRF_VPR_TASK_TRIGGER_18 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[18]), /**< Trigger 18 task. */ @@ -158,6 +180,7 @@ typedef enum NRF_VPR_TASK_TRIGGER_20 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[20]), /**< Trigger 20 task. */ NRF_VPR_TASK_TRIGGER_21 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[21]), /**< Trigger 21 task. */ NRF_VPR_TASK_TRIGGER_22 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[22]), /**< Trigger 22 task. */ +#if NRF_VPR_TASKS_TRIGGER_MAX > 22 NRF_VPR_TASK_TRIGGER_23 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[23]), /**< Trigger 23 task. */ NRF_VPR_TASK_TRIGGER_24 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[24]), /**< Trigger 24 task. */ NRF_VPR_TASK_TRIGGER_25 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[25]), /**< Trigger 25 task. */ @@ -167,6 +190,7 @@ typedef enum NRF_VPR_TASK_TRIGGER_29 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[29]), /**< Trigger 29 task. */ NRF_VPR_TASK_TRIGGER_30 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[30]), /**< Trigger 30 task. */ NRF_VPR_TASK_TRIGGER_31 = offsetof(NRF_VPR_Type, TASKS_TRIGGER[31]), /**< Trigger 31 task. */ +#endif } nrf_vpr_task_t; /** @brief Debug Mode Control signals. */ diff --git a/haly/nrfy_common.h b/haly/nrfy_common.h index bf089967e..8db18f60c 100644 --- a/haly/nrfy_common.h +++ b/haly/nrfy_common.h @@ -70,7 +70,7 @@ extern "C" { * * @return Interrupt bitmask. */ -#define NRFY_EVENT_TO_INT_BITMASK(event) (1 << NRFY_EVENT_TO_INT_BITPOS(event)) +#define NRFY_EVENT_TO_INT_BITMASK(event) (1U << NRFY_EVENT_TO_INT_BITPOS(event)) /** @sa NRFX_IRQ_PRIORITY_SET */ #define NRFY_IRQ_PRIORITY_SET(irq_number, priority) NRFX_IRQ_PRIORITY_SET(irq_number, priority) diff --git a/haly/nrfy_grtc.h b/haly/nrfy_grtc.h index a3c6cd0af..02f1a4b93 100644 --- a/haly/nrfy_grtc.h +++ b/haly/nrfy_grtc.h @@ -854,14 +854,14 @@ NRFY_STATIC_INLINE uint32_t nrfy_grtc_clkout_divider_get(NRF_GRTC_Type const * p #if NRFY_GRTC_HAS_CLKSEL /** @refhal{nrf_grtc_clksel_set} */ -NRF_STATIC_INLINE void nrfy_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel) +NRFY_STATIC_INLINE void nrfy_grtc_clksel_set(NRF_GRTC_Type * p_reg, nrf_grtc_clksel_t clksel) { nrf_grtc_clksel_set(p_reg, clksel); nrf_barrier_w(); } /** @refhal{nrf_grtc_clksel_get} */ -NRF_STATIC_INLINE nrf_grtc_clksel_t nrfy_grtc_clksel_get(NRF_GRTC_Type const * p_reg) +NRFY_STATIC_INLINE nrf_grtc_clksel_t nrfy_grtc_clksel_get(NRF_GRTC_Type const * p_reg) { nrf_barrier_rw(); nrf_grtc_clksel_t clksel = nrf_grtc_clksel_get(p_reg); diff --git a/haly/nrfy_rramc.h b/haly/nrfy_rramc.h index 4f7d14faa..876bca375 100644 --- a/haly/nrfy_rramc.h +++ b/haly/nrfy_rramc.h @@ -52,7 +52,11 @@ NRFY_STATIC_INLINE uint32_t __nrfy_internal_rramc_event_handle(NRF_RRAMC_Type * NRFY_STATIC_INLINE uint32_t __nrfy_internal_rramc_events_process(NRF_RRAMC_Type * p_reg, uint32_t mask); -NRFY_STATIC_INLINE void __nrfy_internal_rramc_write_enable_set(NRF_RRAMC_Type * p_reg, bool enable); +NRFY_STATIC_INLINE void __nrfy_internal_rramc_config_get(NRF_RRAMC_Type const * p_reg, + nrf_rramc_config_t * p_config); + +NRFY_STATIC_INLINE void __nrfy_internal_rramc_config_set(NRF_RRAMC_Type * p_reg, + nrf_rramc_config_t const * p_config); NRFY_STATIC_INLINE void __nrfy_internal_rramc_byte_write(NRF_RRAMC_Type * p_reg, uint32_t addr, @@ -189,9 +193,16 @@ NRFY_STATIC_INLINE void nrfy_rramc_byte_write(NRF_RRAMC_Type * p_reg, uint32_t address, uint8_t value) { - __nrfy_internal_rramc_write_enable_set(p_reg, true); + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); __nrfy_internal_rramc_byte_write(p_reg, address, value); - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); } /** @@ -211,12 +222,19 @@ NRFY_STATIC_INLINE void nrfy_rramc_bytes_write(NRF_RRAMC_Type * p_reg, void const * src, uint32_t num_bytes) { - __nrfy_internal_rramc_write_enable_set(p_reg, true); + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); for (uint32_t i = 0; i < num_bytes; i++) { __nrfy_internal_rramc_byte_write(p_reg, address + i, ((uint8_t const *)src)[i]); } - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); } /** @@ -249,9 +267,16 @@ NRFY_STATIC_INLINE void nrfy_rramc_word_write(NRF_RRAMC_Type * p_reg, uint32_t address, uint32_t value) { - __nrfy_internal_rramc_write_enable_set(p_reg, true); + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); __nrfy_internal_rramc_word_write(p_reg, address, value); - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); } /** @@ -271,14 +296,21 @@ NRFY_STATIC_INLINE void nrfy_rramc_words_write(NRF_RRAMC_Type * p_reg, void const * src, uint32_t num_words) { - __nrfy_internal_rramc_write_enable_set(p_reg, true); + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); for (uint32_t i = 0; i < num_words; i++) { __nrfy_internal_rramc_word_write(p_reg, address + (NRFY_RRAMC_BYTES_IN_WORD * i), ((uint32_t const *)src)[i]); } - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); } /** @@ -363,9 +395,17 @@ NRFY_STATIC_INLINE bool nrfy_rramc_otp_word_write(NRF_RRAMC_Type * p_reg, { return false; } - __nrfy_internal_rramc_write_enable_set(p_reg, true); + + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); NRF_UICR->OTP[index] = value; - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); return true; #else @@ -511,21 +551,14 @@ NRFY_STATIC_INLINE bool nrfy_rramc_empty_buffer_check(NRF_RRAMC_Type const * p_r NRFY_STATIC_INLINE void nrfy_rramc_config_get(NRF_RRAMC_Type const * p_reg, nrf_rramc_config_t * p_config) { - nrf_barrier_r(); - nrf_rramc_config_get(p_reg, p_config); - nrf_barrier_r(); + __nrfy_internal_rramc_config_get(p_reg, p_config); } /** @refhal{nrf_rramc_config_set} */ NRFY_STATIC_INLINE void nrfy_rramc_config_set(NRF_RRAMC_Type * p_reg, nrf_rramc_config_t const * p_config) { - nrf_rramc_config_set(p_reg, p_config); - nrf_barrier_w(); - nrf_barrier_r(); - while (!nrf_rramc_ready_check(p_reg)) - {} - nrf_barrier_r(); + __nrfy_internal_rramc_config_set(p_reg, p_config); } /** @refhal{nrf_rramc_ready_next_timeout_get} */ @@ -575,9 +608,16 @@ NRFY_STATIC_INLINE bool nrfy_rramc_erase_all_check(NRF_RRAMC_Type const * p_reg) /** @refhal{nrf_rramc_erase_all_set} */ NRFY_STATIC_INLINE void nrfy_rramc_erase_all_set(NRF_RRAMC_Type * p_reg) { - __nrfy_internal_rramc_write_enable_set(p_reg, true); + nrf_rramc_config_t rramc_config; + nrf_rramc_config_t prev_rramc_config; + + __nrfy_internal_rramc_config_get(p_reg, &rramc_config); + prev_rramc_config = rramc_config; + rramc_config.mode_write = true; + + __nrfy_internal_rramc_config_set(p_reg, &rramc_config); nrf_rramc_erase_all_set(p_reg); - __nrfy_internal_rramc_write_enable_set(p_reg, false); + __nrfy_internal_rramc_config_set(p_reg, &prev_rramc_config); } /** @} */ @@ -619,18 +659,21 @@ NRFY_STATIC_INLINE uint32_t __nrfy_internal_rramc_events_process(NRF_RRAMC_Type return evt_mask; } -NRFY_STATIC_INLINE void __nrfy_internal_rramc_write_enable_set(NRF_RRAMC_Type * p_reg, bool enable) +NRFY_STATIC_INLINE void __nrfy_internal_rramc_config_get(NRF_RRAMC_Type const * p_reg, + nrf_rramc_config_t * p_config) { - nrf_rramc_config_t rramc_config; - nrf_barrier_r(); - nrf_rramc_config_get(p_reg, &rramc_config); + nrf_rramc_config_get(p_reg, p_config); nrf_barrier_r(); - rramc_config.mode_write = enable; - nrf_rramc_config_set(p_reg, &rramc_config); +} + +NRFY_STATIC_INLINE void __nrfy_internal_rramc_config_set(NRF_RRAMC_Type * p_reg, + nrf_rramc_config_t const * p_config) +{ + nrf_rramc_config_set(p_reg, p_config); nrf_barrier_w(); nrf_barrier_r(); - while (!nrf_rramc_write_ready_check(p_reg)) + while (!nrf_rramc_ready_check(p_reg)) {} nrf_barrier_r(); } diff --git a/haly/nrfy_uarte.h b/haly/nrfy_uarte.h index 7cecbd47d..810f902db 100644 --- a/haly/nrfy_uarte.h +++ b/haly/nrfy_uarte.h @@ -454,6 +454,15 @@ NRFY_STATIC_INLINE void nrfy_uarte_disable(NRF_UARTE_Type * p_reg) nrf_barrier_w(); } +/** @refhal{nrf_uarte_enable_check} */ +NRFY_STATIC_INLINE bool nrfy_uarte_enable_check(NRF_UARTE_Type * p_reg) +{ + nrf_barrier_rw(); + bool ret = nrf_uarte_enable_check(p_reg); + nrf_barrier_r(); + return ret; +} + /** @refhal{nrf_uarte_txrx_pins_set} */ NRFY_STATIC_INLINE void nrfy_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, diff --git a/helpers/nrfx_ids.h b/helpers/nrfx_ids.h index 942309362..5a351648a 100644 --- a/helpers/nrfx_ids.h +++ b/helpers/nrfx_ids.h @@ -53,10 +53,12 @@ extern "C" { /** * @defgroup nrfx_ids Generic inter-domain signalling layer. * @{ - * @ingroup nrfx_ipc - * @ingroup nrfx_vevif - * @ingroup nrfx_bellboard - * @brief Helper layer that provides the common functionality for the inter-domain signalling (IDS) mechanisms. + * @ingroup nrfx + * @ingroup nrf_ipc + * @ingroup nrf_vevif + * @ingroup nrf_bellboard + * + * @brief Helper layer that provides the common functionality for the inter-domain signalling (IDS) mechanisms. */ /** diff --git a/mdk/arm_startup_nrf9230_enga_application.s b/mdk/arm_startup_nrf9230_enga_application.s new file mode 100644 index 000000000..3e6bb3d6f --- /dev/null +++ b/mdk/arm_startup_nrf9230_enga_application.s @@ -0,0 +1,828 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 2048 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align +Stack_Mem SPACE Stack_Size +__initial_sp + + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 2048 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPU000_IRQHandler + DCD MPC_IRQHandler + DCD 0 ; Reserved + DCD MVDMA_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU010_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT010_IRQHandler + DCD WDT011_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT_0_IRQHandler + DCD IPCT_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD SWI6_IRQHandler + DCD SWI7_IRQHandler + DCD BELLBOARD_0_IRQHandler + DCD BELLBOARD_1_IRQHandler + DCD BELLBOARD_2_IRQHandler + DCD BELLBOARD_3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SecureFault_Handler\ + PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SPU000_IRQHandler [WEAK] + EXPORT MPC_IRQHandler [WEAK] + EXPORT MVDMA_IRQHandler [WEAK] + EXPORT SPU010_IRQHandler [WEAK] + EXPORT WDT010_IRQHandler [WEAK] + EXPORT WDT011_IRQHandler [WEAK] + EXPORT IPCT_0_IRQHandler [WEAK] + EXPORT IPCT_1_IRQHandler [WEAK] + EXPORT SWI0_IRQHandler [WEAK] + EXPORT SWI1_IRQHandler [WEAK] + EXPORT SWI2_IRQHandler [WEAK] + EXPORT SWI3_IRQHandler [WEAK] + EXPORT SWI4_IRQHandler [WEAK] + EXPORT SWI5_IRQHandler [WEAK] + EXPORT SWI6_IRQHandler [WEAK] + EXPORT SWI7_IRQHandler [WEAK] + EXPORT BELLBOARD_0_IRQHandler [WEAK] + EXPORT BELLBOARD_1_IRQHandler [WEAK] + EXPORT BELLBOARD_2_IRQHandler [WEAK] + EXPORT BELLBOARD_3_IRQHandler [WEAK] + EXPORT GPIOTE130_0_IRQHandler [WEAK] + EXPORT GPIOTE130_1_IRQHandler [WEAK] + EXPORT GPIOTE131_0_IRQHandler [WEAK] + EXPORT GPIOTE131_1_IRQHandler [WEAK] + EXPORT GRTC_0_IRQHandler [WEAK] + EXPORT GRTC_1_IRQHandler [WEAK] + EXPORT GRTC_2_IRQHandler [WEAK] + EXPORT TBM_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT EXMIF_IRQHandler [WEAK] + EXPORT IPCT120_0_IRQHandler [WEAK] + EXPORT I3C120_IRQHandler [WEAK] + EXPORT VPR121_IRQHandler [WEAK] + EXPORT CAN120_IRQHandler [WEAK] + EXPORT MVDMA120_IRQHandler [WEAK] + EXPORT CAN121_IRQHandler [WEAK] + EXPORT MVDMA121_IRQHandler [WEAK] + EXPORT I3C121_IRQHandler [WEAK] + EXPORT TIMER120_IRQHandler [WEAK] + EXPORT TIMER121_IRQHandler [WEAK] + EXPORT PWM120_IRQHandler [WEAK] + EXPORT SPIS120_IRQHandler [WEAK] + EXPORT SPIM120_UARTE120_IRQHandler [WEAK] + EXPORT SPIM121_IRQHandler [WEAK] + EXPORT VPR130_IRQHandler [WEAK] + EXPORT IPCT130_0_IRQHandler [WEAK] + EXPORT RTC130_IRQHandler [WEAK] + EXPORT RTC131_IRQHandler [WEAK] + EXPORT WDT131_IRQHandler [WEAK] + EXPORT WDT132_IRQHandler [WEAK] + EXPORT EGU130_IRQHandler [WEAK] + EXPORT SAADC_IRQHandler [WEAK] + EXPORT COMP_LPCOMP_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler [WEAK] + EXPORT I2S130_IRQHandler [WEAK] + EXPORT PDM_IRQHandler [WEAK] + EXPORT QDEC130_IRQHandler [WEAK] + EXPORT QDEC131_IRQHandler [WEAK] + EXPORT I2S131_IRQHandler [WEAK] + EXPORT TIMER130_IRQHandler [WEAK] + EXPORT TIMER131_IRQHandler [WEAK] + EXPORT PWM130_IRQHandler [WEAK] + EXPORT SERIAL0_IRQHandler [WEAK] + EXPORT SERIAL1_IRQHandler [WEAK] + EXPORT TIMER132_IRQHandler [WEAK] + EXPORT TIMER133_IRQHandler [WEAK] + EXPORT PWM131_IRQHandler [WEAK] + EXPORT SERIAL2_IRQHandler [WEAK] + EXPORT SERIAL3_IRQHandler [WEAK] + EXPORT TIMER134_IRQHandler [WEAK] + EXPORT TIMER135_IRQHandler [WEAK] + EXPORT PWM132_IRQHandler [WEAK] + EXPORT SERIAL4_IRQHandler [WEAK] + EXPORT SERIAL5_IRQHandler [WEAK] + EXPORT TIMER136_IRQHandler [WEAK] + EXPORT TIMER137_IRQHandler [WEAK] + EXPORT PWM133_IRQHandler [WEAK] + EXPORT SERIAL6_IRQHandler [WEAK] + EXPORT SERIAL7_IRQHandler [WEAK] +SPU000_IRQHandler +MPC_IRQHandler +MVDMA_IRQHandler +SPU010_IRQHandler +WDT010_IRQHandler +WDT011_IRQHandler +IPCT_0_IRQHandler +IPCT_1_IRQHandler +SWI0_IRQHandler +SWI1_IRQHandler +SWI2_IRQHandler +SWI3_IRQHandler +SWI4_IRQHandler +SWI5_IRQHandler +SWI6_IRQHandler +SWI7_IRQHandler +BELLBOARD_0_IRQHandler +BELLBOARD_1_IRQHandler +BELLBOARD_2_IRQHandler +BELLBOARD_3_IRQHandler +GPIOTE130_0_IRQHandler +GPIOTE130_1_IRQHandler +GPIOTE131_0_IRQHandler +GPIOTE131_1_IRQHandler +GRTC_0_IRQHandler +GRTC_1_IRQHandler +GRTC_2_IRQHandler +TBM_IRQHandler +USBHS_IRQHandler +EXMIF_IRQHandler +IPCT120_0_IRQHandler +I3C120_IRQHandler +VPR121_IRQHandler +CAN120_IRQHandler +MVDMA120_IRQHandler +CAN121_IRQHandler +MVDMA121_IRQHandler +I3C121_IRQHandler +TIMER120_IRQHandler +TIMER121_IRQHandler +PWM120_IRQHandler +SPIS120_IRQHandler +SPIM120_UARTE120_IRQHandler +SPIM121_IRQHandler +VPR130_IRQHandler +IPCT130_0_IRQHandler +RTC130_IRQHandler +RTC131_IRQHandler +WDT131_IRQHandler +WDT132_IRQHandler +EGU130_IRQHandler +SAADC_IRQHandler +COMP_LPCOMP_IRQHandler +TEMP_IRQHandler +I2S130_IRQHandler +PDM_IRQHandler +QDEC130_IRQHandler +QDEC131_IRQHandler +I2S131_IRQHandler +TIMER130_IRQHandler +TIMER131_IRQHandler +PWM130_IRQHandler +SERIAL0_IRQHandler +SERIAL1_IRQHandler +TIMER132_IRQHandler +TIMER133_IRQHandler +PWM131_IRQHandler +SERIAL2_IRQHandler +SERIAL3_IRQHandler +TIMER134_IRQHandler +TIMER135_IRQHandler +PWM132_IRQHandler +SERIAL4_IRQHandler +SERIAL5_IRQHandler +TIMER136_IRQHandler +TIMER137_IRQHandler +PWM133_IRQHandler +SERIAL6_IRQHandler +SERIAL7_IRQHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/mdk/arm_startup_nrf9230_enga_radiocore.s b/mdk/arm_startup_nrf9230_enga_radiocore.s new file mode 100644 index 000000000..7c0811a57 --- /dev/null +++ b/mdk/arm_startup_nrf9230_enga_radiocore.s @@ -0,0 +1,856 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 4096 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align +Stack_Mem SPACE Stack_Size +__initial_sp + + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 4096 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPU000_IRQHandler + DCD MPC_IRQHandler + DCD 0 ; Reserved + DCD MVDMA_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU010_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT010_IRQHandler + DCD WDT011_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU020_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EGU020_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER020_IRQHandler + DCD TIMER021_IRQHandler + DCD TIMER022_IRQHandler + DCD RTC_IRQHandler + DCD RADIO_0_IRQHandler + DCD RADIO_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU030_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD AAR030_CCM030_IRQHandler + DCD ECB030_IRQHandler + DCD AAR031_CCM031_IRQHandler + DCD ECB031_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT_0_IRQHandler + DCD IPCT_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD SWI6_IRQHandler + DCD SWI7_IRQHandler + DCD BELLBOARD_0_IRQHandler + DCD BELLBOARD_1_IRQHandler + DCD BELLBOARD_2_IRQHandler + DCD BELLBOARD_3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SecureFault_Handler\ + PROC + EXPORT SecureFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SPU000_IRQHandler [WEAK] + EXPORT MPC_IRQHandler [WEAK] + EXPORT MVDMA_IRQHandler [WEAK] + EXPORT SPU010_IRQHandler [WEAK] + EXPORT WDT010_IRQHandler [WEAK] + EXPORT WDT011_IRQHandler [WEAK] + EXPORT SPU020_IRQHandler [WEAK] + EXPORT EGU020_IRQHandler [WEAK] + EXPORT TIMER020_IRQHandler [WEAK] + EXPORT TIMER021_IRQHandler [WEAK] + EXPORT TIMER022_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RADIO_0_IRQHandler [WEAK] + EXPORT RADIO_1_IRQHandler [WEAK] + EXPORT SPU030_IRQHandler [WEAK] + EXPORT VPR_IRQHandler [WEAK] + EXPORT AAR030_CCM030_IRQHandler [WEAK] + EXPORT ECB030_IRQHandler [WEAK] + EXPORT AAR031_CCM031_IRQHandler [WEAK] + EXPORT ECB031_IRQHandler [WEAK] + EXPORT IPCT_0_IRQHandler [WEAK] + EXPORT IPCT_1_IRQHandler [WEAK] + EXPORT SWI0_IRQHandler [WEAK] + EXPORT SWI1_IRQHandler [WEAK] + EXPORT SWI2_IRQHandler [WEAK] + EXPORT SWI3_IRQHandler [WEAK] + EXPORT SWI4_IRQHandler [WEAK] + EXPORT SWI5_IRQHandler [WEAK] + EXPORT SWI6_IRQHandler [WEAK] + EXPORT SWI7_IRQHandler [WEAK] + EXPORT BELLBOARD_0_IRQHandler [WEAK] + EXPORT BELLBOARD_1_IRQHandler [WEAK] + EXPORT BELLBOARD_2_IRQHandler [WEAK] + EXPORT BELLBOARD_3_IRQHandler [WEAK] + EXPORT GPIOTE130_0_IRQHandler [WEAK] + EXPORT GPIOTE130_1_IRQHandler [WEAK] + EXPORT GPIOTE131_0_IRQHandler [WEAK] + EXPORT GPIOTE131_1_IRQHandler [WEAK] + EXPORT GRTC_0_IRQHandler [WEAK] + EXPORT GRTC_1_IRQHandler [WEAK] + EXPORT GRTC_2_IRQHandler [WEAK] + EXPORT TBM_IRQHandler [WEAK] + EXPORT USBHS_IRQHandler [WEAK] + EXPORT EXMIF_IRQHandler [WEAK] + EXPORT IPCT120_0_IRQHandler [WEAK] + EXPORT I3C120_IRQHandler [WEAK] + EXPORT VPR121_IRQHandler [WEAK] + EXPORT CAN120_IRQHandler [WEAK] + EXPORT MVDMA120_IRQHandler [WEAK] + EXPORT CAN121_IRQHandler [WEAK] + EXPORT MVDMA121_IRQHandler [WEAK] + EXPORT I3C121_IRQHandler [WEAK] + EXPORT TIMER120_IRQHandler [WEAK] + EXPORT TIMER121_IRQHandler [WEAK] + EXPORT PWM120_IRQHandler [WEAK] + EXPORT SPIS120_IRQHandler [WEAK] + EXPORT SPIM120_UARTE120_IRQHandler [WEAK] + EXPORT SPIM121_IRQHandler [WEAK] + EXPORT VPR130_IRQHandler [WEAK] + EXPORT IPCT130_0_IRQHandler [WEAK] + EXPORT RTC130_IRQHandler [WEAK] + EXPORT RTC131_IRQHandler [WEAK] + EXPORT WDT131_IRQHandler [WEAK] + EXPORT WDT132_IRQHandler [WEAK] + EXPORT EGU130_IRQHandler [WEAK] + EXPORT SAADC_IRQHandler [WEAK] + EXPORT COMP_LPCOMP_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler [WEAK] + EXPORT I2S130_IRQHandler [WEAK] + EXPORT PDM_IRQHandler [WEAK] + EXPORT QDEC130_IRQHandler [WEAK] + EXPORT QDEC131_IRQHandler [WEAK] + EXPORT I2S131_IRQHandler [WEAK] + EXPORT TIMER130_IRQHandler [WEAK] + EXPORT TIMER131_IRQHandler [WEAK] + EXPORT PWM130_IRQHandler [WEAK] + EXPORT SERIAL0_IRQHandler [WEAK] + EXPORT SERIAL1_IRQHandler [WEAK] + EXPORT TIMER132_IRQHandler [WEAK] + EXPORT TIMER133_IRQHandler [WEAK] + EXPORT PWM131_IRQHandler [WEAK] + EXPORT SERIAL2_IRQHandler [WEAK] + EXPORT SERIAL3_IRQHandler [WEAK] + EXPORT TIMER134_IRQHandler [WEAK] + EXPORT TIMER135_IRQHandler [WEAK] + EXPORT PWM132_IRQHandler [WEAK] + EXPORT SERIAL4_IRQHandler [WEAK] + EXPORT SERIAL5_IRQHandler [WEAK] + EXPORT TIMER136_IRQHandler [WEAK] + EXPORT TIMER137_IRQHandler [WEAK] + EXPORT PWM133_IRQHandler [WEAK] + EXPORT SERIAL6_IRQHandler [WEAK] + EXPORT SERIAL7_IRQHandler [WEAK] +SPU000_IRQHandler +MPC_IRQHandler +MVDMA_IRQHandler +SPU010_IRQHandler +WDT010_IRQHandler +WDT011_IRQHandler +SPU020_IRQHandler +EGU020_IRQHandler +TIMER020_IRQHandler +TIMER021_IRQHandler +TIMER022_IRQHandler +RTC_IRQHandler +RADIO_0_IRQHandler +RADIO_1_IRQHandler +SPU030_IRQHandler +VPR_IRQHandler +AAR030_CCM030_IRQHandler +ECB030_IRQHandler +AAR031_CCM031_IRQHandler +ECB031_IRQHandler +IPCT_0_IRQHandler +IPCT_1_IRQHandler +SWI0_IRQHandler +SWI1_IRQHandler +SWI2_IRQHandler +SWI3_IRQHandler +SWI4_IRQHandler +SWI5_IRQHandler +SWI6_IRQHandler +SWI7_IRQHandler +BELLBOARD_0_IRQHandler +BELLBOARD_1_IRQHandler +BELLBOARD_2_IRQHandler +BELLBOARD_3_IRQHandler +GPIOTE130_0_IRQHandler +GPIOTE130_1_IRQHandler +GPIOTE131_0_IRQHandler +GPIOTE131_1_IRQHandler +GRTC_0_IRQHandler +GRTC_1_IRQHandler +GRTC_2_IRQHandler +TBM_IRQHandler +USBHS_IRQHandler +EXMIF_IRQHandler +IPCT120_0_IRQHandler +I3C120_IRQHandler +VPR121_IRQHandler +CAN120_IRQHandler +MVDMA120_IRQHandler +CAN121_IRQHandler +MVDMA121_IRQHandler +I3C121_IRQHandler +TIMER120_IRQHandler +TIMER121_IRQHandler +PWM120_IRQHandler +SPIS120_IRQHandler +SPIM120_UARTE120_IRQHandler +SPIM121_IRQHandler +VPR130_IRQHandler +IPCT130_0_IRQHandler +RTC130_IRQHandler +RTC131_IRQHandler +WDT131_IRQHandler +WDT132_IRQHandler +EGU130_IRQHandler +SAADC_IRQHandler +COMP_LPCOMP_IRQHandler +TEMP_IRQHandler +I2S130_IRQHandler +PDM_IRQHandler +QDEC130_IRQHandler +QDEC131_IRQHandler +I2S131_IRQHandler +TIMER130_IRQHandler +TIMER131_IRQHandler +PWM130_IRQHandler +SERIAL0_IRQHandler +SERIAL1_IRQHandler +TIMER132_IRQHandler +TIMER133_IRQHandler +PWM131_IRQHandler +SERIAL2_IRQHandler +SERIAL3_IRQHandler +TIMER134_IRQHandler +TIMER135_IRQHandler +PWM132_IRQHandler +SERIAL4_IRQHandler +SERIAL5_IRQHandler +TIMER136_IRQHandler +TIMER137_IRQHandler +PWM133_IRQHandler +SERIAL6_IRQHandler +SERIAL7_IRQHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/mdk/core_vpr.h b/mdk/core_vpr.h index 9973449b0..29d1fa08b 100644 --- a/mdk/core_vpr.h +++ b/mdk/core_vpr.h @@ -46,45 +46,39 @@ POSSIBILITY OF SUCH DAMAGE. /* =========================================================================================================================== */ /* ================ CSR declaration ================ */ /* =========================================================================================================================== */ -#define CSR_MCYCLE 0xB00 -#define CSR_MINSTRET 0xB02 -#define CSR_MCYCLEH 0xB80 -#define CSR_MINSTRETH 0xB82 -#define CSR_MVENDORID 0xF11 -#define CSR_MARCHID 0xF12 -#define CSR_MIMPID 0xF13 -#define CSR_MHARTID 0xF14 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MTVT 0x307 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MTVAL 0x343 -#define CSR_MIP 0x344 -#define CSR_MNXTI 0x345 -#define CSR_MINTSTATUS 0x346 -#define CSR_MSCRATCHCSW 0x348 -#define CSR_MSCRATCHCSWL 0x349 -#define CSR_MCLICBASE 0x350 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_UCYCLE 0xc00 -#define CSR_UINSTRET 0xc02 -#define CSR_UCYCLEH 0xc80 -#define CSR_UINSTRETH 0xc82 - -// Nordic custom CSRs + +#define CSR_MCYCLE 0xB00 +#define CSR_MINSTRET 0xB02 +#define CSR_MCYCLEH 0xB80 +#define CSR_MINSTRETH 0xB82 +#define CSR_MVENDORID 0xF11 +#define CSR_MARCHID 0xF12 +#define CSR_MIMPID 0xF13 +#define CSR_MHARTID 0xF14 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MTVEC 0x305 +#define CSR_MTVT 0x307 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MINTSTATUS 0x346 +#define CSR_MCLICBASE 0x350 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_UCYCLE 0xc00 +#define CSR_UINSTRET 0xc02 +#define CSR_UCYCLEH 0xc80 +#define CSR_UINSTRETH 0xc82 + + #define CSR_NORDIC_CTRL 0x7c0 #define CSR_NORDIC_SLEEP 0x7c1 #define CSR_NORDIC_DISFTR 0x7c2 #define CSR_NORDIC_VIOPINS 0x7c3 + #define VTIM_CNTMODE0 0x7d0 #define VTIM_CNTMODE1 0x7d1 #define VTIM_CNT 0x7d2 @@ -95,30 +89,14 @@ POSSIBILITY OF SUCH DAMAGE. #define VTIM_CNT1 0x7d7 #define VTIM_CNTADD1 0x7d8 -#define VIO_OUT 0x7e0 -#define VIO_DIR 0x7e1 -#define VIO_IN 0x7e2 -#define VIO_INMODE 0x7e3 -#define VIO_OUTB 0x7e4 -#define VIO_DIRB 0x7e5 -#define VIO_DIROUT 0x7e6 -#define VIO_DIROUTB 0x7e7 -#define VIO_OUTTGL 0x7e8 -#define VIO_DIRTGL 0x7e9 -#define VIO_OUTBTGL 0x7ea -#define VIO_DIRBTGL 0x7eb -#define VIO_DIROUTTGL 0x7ec -#define VIO_DIROUTBTGL 0x7ed -#define VIO_OUTBS 0x7ee -#define VIO_DIRBS 0x7ef -#define VIO_DIROUTBS 0x7f0 - -#define VEVIF_VTASKS 0x7f1 -#define VEVIF_VSUBSCRIBE 0x7f2 -#define VEVIF_VEVENTS 0x7f3 -#define VEVIF_VPUBLISH 0x7f4 -#define VEVIF_VINTEN 0x7f5 -#define VEVIF_VEVENTSB 0x7f6 -#define VEVIF_VEVENTSBS 0x7f7 + +#define CSR_NORDIC_TASKS 0x7e0 +#define CSR_NORDIC_SUBSCRIBE 0x7e1 +#define CSR_NORDIC_EVENTS 0x7e2 +#define CSR_NORDIC_PUBLISH 0x7e3 +#define CSR_NORDIC_INTEN 0x7e4 +#define CSR_NORDIC_EVENTSB 0x7e5 +#define CSR_NORDIC_EVENTSBS 0x7e6 + #endif /* _CORE_VPR_H */ \ No newline at end of file diff --git a/mdk/gcc_startup_nrf9230_enga_application.S b/mdk/gcc_startup_nrf9230_enga_application.S new file mode 100644 index 000000000..1088554a1 --- /dev/null +++ b/mdk/gcc_startup_nrf9230_enga_application.S @@ -0,0 +1,871 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + + .syntax unified + .arch armv8-m.main + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 2048 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 2048 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector, "ax" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long SecureFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMon_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long SPU000_IRQHandler + .long MPC_IRQHandler + .long 0 /*Reserved */ + .long MVDMA_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPU010_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long WDT010_IRQHandler + .long WDT011_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT_0_IRQHandler + .long IPCT_1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SWI0_IRQHandler + .long SWI1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + .long SWI6_IRQHandler + .long SWI7_IRQHandler + .long BELLBOARD_0_IRQHandler + .long BELLBOARD_1_IRQHandler + .long BELLBOARD_2_IRQHandler + .long BELLBOARD_3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long GPIOTE130_0_IRQHandler + .long GPIOTE130_1_IRQHandler + .long GPIOTE131_0_IRQHandler + .long GPIOTE131_1_IRQHandler + .long GRTC_0_IRQHandler + .long GRTC_1_IRQHandler + .long GRTC_2_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TBM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long USBHS_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EXMIF_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT120_0_IRQHandler + .long 0 /*Reserved */ + .long I3C120_IRQHandler + .long VPR121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long CAN120_IRQHandler + .long MVDMA120_IRQHandler + .long 0 /*Reserved */ + .long CAN121_IRQHandler + .long MVDMA121_IRQHandler + .long 0 /*Reserved */ + .long I3C121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER120_IRQHandler + .long TIMER121_IRQHandler + .long PWM120_IRQHandler + .long SPIS120_IRQHandler + .long SPIM120_UARTE120_IRQHandler + .long SPIM121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long VPR130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT130_0_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long RTC130_IRQHandler + .long RTC131_IRQHandler + .long 0 /*Reserved */ + .long WDT131_IRQHandler + .long WDT132_IRQHandler + .long EGU130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SAADC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long TEMP_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long I2S130_IRQHandler + .long PDM_IRQHandler + .long QDEC130_IRQHandler + .long QDEC131_IRQHandler + .long 0 /*Reserved */ + .long I2S131_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER130_IRQHandler + .long TIMER131_IRQHandler + .long PWM130_IRQHandler + .long SERIAL0_IRQHandler + .long SERIAL1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER132_IRQHandler + .long TIMER133_IRQHandler + .long PWM131_IRQHandler + .long SERIAL2_IRQHandler + .long SERIAL3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER134_IRQHandler + .long TIMER135_IRQHandler + .long PWM132_IRQHandler + .long SERIAL4_IRQHandler + .long SERIAL5_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER136_IRQHandler + .long TIMER137_IRQHandler + .long PWM133_IRQHandler + .long SERIAL6_IRQHandler + .long SERIAL7_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: + + +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + bl clear_region + + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: + movs r0, 0 + + subs r2, r2, r1 + ble .L_clear_region_done + +.L_clear_region: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: + +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SecureFault_Handler + .type SecureFault_Handler, %function +SecureFault_Handler: + b . + .size SecureFault_Handler, . - SecureFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ SPU000_IRQHandler + IRQ MPC_IRQHandler + IRQ MVDMA_IRQHandler + IRQ SPU010_IRQHandler + IRQ WDT010_IRQHandler + IRQ WDT011_IRQHandler + IRQ IPCT_0_IRQHandler + IRQ IPCT_1_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + IRQ SWI6_IRQHandler + IRQ SWI7_IRQHandler + IRQ BELLBOARD_0_IRQHandler + IRQ BELLBOARD_1_IRQHandler + IRQ BELLBOARD_2_IRQHandler + IRQ BELLBOARD_3_IRQHandler + IRQ GPIOTE130_0_IRQHandler + IRQ GPIOTE130_1_IRQHandler + IRQ GPIOTE131_0_IRQHandler + IRQ GPIOTE131_1_IRQHandler + IRQ GRTC_0_IRQHandler + IRQ GRTC_1_IRQHandler + IRQ GRTC_2_IRQHandler + IRQ TBM_IRQHandler + IRQ USBHS_IRQHandler + IRQ EXMIF_IRQHandler + IRQ IPCT120_0_IRQHandler + IRQ I3C120_IRQHandler + IRQ VPR121_IRQHandler + IRQ CAN120_IRQHandler + IRQ MVDMA120_IRQHandler + IRQ CAN121_IRQHandler + IRQ MVDMA121_IRQHandler + IRQ I3C121_IRQHandler + IRQ TIMER120_IRQHandler + IRQ TIMER121_IRQHandler + IRQ PWM120_IRQHandler + IRQ SPIS120_IRQHandler + IRQ SPIM120_UARTE120_IRQHandler + IRQ SPIM121_IRQHandler + IRQ VPR130_IRQHandler + IRQ IPCT130_0_IRQHandler + IRQ RTC130_IRQHandler + IRQ RTC131_IRQHandler + IRQ WDT131_IRQHandler + IRQ WDT132_IRQHandler + IRQ EGU130_IRQHandler + IRQ SAADC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ TEMP_IRQHandler + IRQ I2S130_IRQHandler + IRQ PDM_IRQHandler + IRQ QDEC130_IRQHandler + IRQ QDEC131_IRQHandler + IRQ I2S131_IRQHandler + IRQ TIMER130_IRQHandler + IRQ TIMER131_IRQHandler + IRQ PWM130_IRQHandler + IRQ SERIAL0_IRQHandler + IRQ SERIAL1_IRQHandler + IRQ TIMER132_IRQHandler + IRQ TIMER133_IRQHandler + IRQ PWM131_IRQHandler + IRQ SERIAL2_IRQHandler + IRQ SERIAL3_IRQHandler + IRQ TIMER134_IRQHandler + IRQ TIMER135_IRQHandler + IRQ PWM132_IRQHandler + IRQ SERIAL4_IRQHandler + IRQ SERIAL5_IRQHandler + IRQ TIMER136_IRQHandler + IRQ TIMER137_IRQHandler + IRQ PWM133_IRQHandler + IRQ SERIAL6_IRQHandler + IRQ SERIAL7_IRQHandler + + .end diff --git a/mdk/gcc_startup_nrf9230_enga_flpr.S b/mdk/gcc_startup_nrf9230_enga_flpr.S new file mode 100644 index 000000000..2cef94a66 --- /dev/null +++ b/mdk/gcc_startup_nrf9230_enga_flpr.S @@ -0,0 +1,941 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* + +This file was modified by Nordic Semiconductor to support RISC-V devices. + +*/ + +/* ============================ * + * Stack configuration * + * ============================ */ + +#ifndef __ASSEMBLY__ + #define __ASSEMBLY__ +#endif +#include "core_vpr.h" + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 2048 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* ============================ * + * Heap configuration * + * ============================ */ + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 2048 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + +/* ============================ * + * Startup code * + * ============================ */ +/* Reset Handler */ + + + .section .startup, "ax" + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifndef NO_STACK_INIT + /* Initialise main stack */ + la sp, __StackTop + add s0, sp, zero +#endif + + +#if !defined(NO_MTVT_CONFIG) && defined(__MTVT_PRESENT) && __MTVT_PRESENT + /* Configure machine trap vector table register */ + la t0, __isr_vector + csrw CSR_MTVT, t0 + + /* Setup machine trap vector in CSR and clear cause register (hardfault exceptions) */ + .weak Trap_Handler + la t0, Trap_Handler + csrw CSR_MTVEC, t0 + csrw CSR_MCAUSE, x0 +#endif + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __data_load_start: LMA of start of the section to copy from. Usually end of text + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + +/* Load .data */ + la t0, __data_start + la t1, __data_end + la t2, __data_load_start + jal copy_region + +/* Load .sdata */ + la t0, __sdata_start + la t1, __sdata_end + la t2, __sdata_load_start + jal copy_region + +/* Load .tdata */ + la t0, __tdata_start + la t1, __tdata_end + la t2, __tdata_load_start + jal copy_region + +/* Load .fast */ + la t0, __fast_start + la t1, __fast_end + la t2, __fast_load_start + jal copy_region + + j copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + beq t0, t1, L_copy_region_done + +L_copy_region: + lw a0,0(t2) + sw a0,0(t0) + addi t0, t0, 4 + addi t2, t2, 4 + bne t0, t1, L_copy_region + +L_copy_region_done: + + ret + +copy_etext_done: + +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start: start of the BSS section. + * __bss_end: + * __sbss_start + * __sbss_end + * __tbss_start + * __tbss_end : end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + la t0, __bss_start + la t1, __bss_end + jal zero_region + + la t0, __sbss_start + la t1, __sbss_end + jal zero_region + + la t0, __tbss_start + la t1, __tbss_end + jal zero_region + + j clear_bss_done + +/* Method that clears ram region */ +zero_region: + beq t0, t1, L_zero_region_done + +L_zero_region: + sw zero, 0(t0) + addi t0, t0, 4 + bne t0, t1, L_zero_region + +L_zero_region_done: + + ret + +clear_bss_done: + +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + jal SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + jal __START + + .size Reset_Handler,.-Reset_Handler + +/* ============================ * + * VPR interrupt return block * + * ============================ */ + .section .isr_return, "ax" + .globl __isr_return +__isr_return: + mret + +/* ============================ * + * HardFault trap * + * ============================ */ +.globl Trap_Handler +.type Trap_Handler, %function +.balign 8 +Trap_Handler: + j Trap_Handler + +/* ============================ * + * Vector table * + * ============================ */ + .section .isr_vector, "ax" + .balign 64 + .globl __isr_vector +__isr_vector: + .long UserSoftware_Handler + .long SuperVisorSoftware_Handler + .long MachineSoftware_Handler + .long 0 /*Reserved */ + .long UserTimer_Handler + .long SuperVisorTimer_Handler + .long 0 /*Reserved */ + .long MachineTimer_Handler + .long UserExternal_Handler + .long SuperVisorExternal_Handler + .long 0 /*Reserved */ + .long MachineExternal_Handler + .long CLICSoftware_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + /* External Interrupts */ + .long VPRCLIC_0_IRQHandler + .long VPRCLIC_1_IRQHandler + .long VPRCLIC_2_IRQHandler + .long VPRCLIC_3_IRQHandler + .long VPRCLIC_4_IRQHandler + .long VPRCLIC_5_IRQHandler + .long VPRCLIC_6_IRQHandler + .long VPRCLIC_7_IRQHandler + .long VPRCLIC_8_IRQHandler + .long VPRCLIC_9_IRQHandler + .long VPRCLIC_10_IRQHandler + .long VPRCLIC_11_IRQHandler + .long VPRCLIC_12_IRQHandler + .long VPRCLIC_13_IRQHandler + .long VPRCLIC_14_IRQHandler + .long VPRCLIC_15_IRQHandler + .long VPRCLIC_16_IRQHandler + .long VPRCLIC_17_IRQHandler + .long VPRCLIC_18_IRQHandler + .long VPRCLIC_19_IRQHandler + .long VPRCLIC_20_IRQHandler + .long VPRCLIC_21_IRQHandler + .long VPRCLIC_22_IRQHandler + .long VPRCLIC_23_IRQHandler + .long VPRCLIC_24_IRQHandler + .long VPRCLIC_25_IRQHandler + .long VPRCLIC_26_IRQHandler + .long VPRCLIC_27_IRQHandler + .long VPRCLIC_28_IRQHandler + .long VPRCLIC_29_IRQHandler + .long VPRCLIC_30_IRQHandler + .long VPRCLIC_31_IRQHandler + .long VPRTIM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long GPIOTE130_0_IRQHandler + .long GPIOTE130_1_IRQHandler + .long GPIOTE131_0_IRQHandler + .long GPIOTE131_1_IRQHandler + .long GRTC_0_IRQHandler + .long GRTC_1_IRQHandler + .long GRTC_2_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TBM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long USBHS_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EXMIF_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT120_0_IRQHandler + .long 0 /*Reserved */ + .long I3C120_IRQHandler + .long VPR121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long CAN120_IRQHandler + .long MVDMA120_IRQHandler + .long 0 /*Reserved */ + .long CAN121_IRQHandler + .long MVDMA121_IRQHandler + .long 0 /*Reserved */ + .long I3C121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER120_IRQHandler + .long TIMER121_IRQHandler + .long PWM120_IRQHandler + .long SPIS120_IRQHandler + .long SPIM120_UARTE120_IRQHandler + .long SPIM121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long VPR130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT130_0_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long RTC130_IRQHandler + .long RTC131_IRQHandler + .long 0 /*Reserved */ + .long WDT131_IRQHandler + .long WDT132_IRQHandler + .long EGU130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SAADC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long TEMP_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long I2S130_IRQHandler + .long PDM_IRQHandler + .long QDEC130_IRQHandler + .long QDEC131_IRQHandler + .long 0 /*Reserved */ + .long I2S131_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER130_IRQHandler + .long TIMER131_IRQHandler + .long PWM130_IRQHandler + .long SERIAL0_IRQHandler + .long SERIAL1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER132_IRQHandler + .long TIMER133_IRQHandler + .long PWM131_IRQHandler + .long SERIAL2_IRQHandler + .long SERIAL3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER134_IRQHandler + .long TIMER135_IRQHandler + .long PWM132_IRQHandler + .long SERIAL4_IRQHandler + .long SERIAL5_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER136_IRQHandler + .long TIMER137_IRQHandler + .long PWM133_IRQHandler + .long SERIAL6_IRQHandler + .long SERIAL7_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +.section .text + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak UserSoftware_Handler + .type UserSoftware_Handler, %function +UserSoftware_Handler: + j . + .size UserSoftware_Handler, . - UserSoftware_Handler + + + .weak SuperVisorSoftware_Handler + .type SuperVisorSoftware_Handler, %function +SuperVisorSoftware_Handler: + j . + .size SuperVisorSoftware_Handler, . - SuperVisorSoftware_Handler + + + .weak MachineSoftware_Handler + .type MachineSoftware_Handler, %function +MachineSoftware_Handler: + j . + .size MachineSoftware_Handler, . - MachineSoftware_Handler + + + .weak UserTimer_Handler + .type UserTimer_Handler, %function +UserTimer_Handler: + j . + .size UserTimer_Handler, . - UserTimer_Handler + + + .weak SuperVisorTimer_Handler + .type SuperVisorTimer_Handler, %function +SuperVisorTimer_Handler: + j . + .size SuperVisorTimer_Handler, . - SuperVisorTimer_Handler + + + .weak MachineTimer_Handler + .type MachineTimer_Handler, %function +MachineTimer_Handler: + j . + .size MachineTimer_Handler, . - MachineTimer_Handler + + + .weak UserExternal_Handler + .type UserExternal_Handler, %function +UserExternal_Handler: + j . + .size UserExternal_Handler, . - UserExternal_Handler + + + .weak SuperVisorExternal_Handler + .type SuperVisorExternal_Handler, %function +SuperVisorExternal_Handler: + j . + .size SuperVisorExternal_Handler, . - SuperVisorExternal_Handler + + + .weak MachineExternal_Handler + .type MachineExternal_Handler, %function +MachineExternal_Handler: + j . + .size MachineExternal_Handler, . - MachineExternal_Handler + + + .weak CLICSoftware_Handler + .type CLICSoftware_Handler, %function +CLICSoftware_Handler: + j . + .size CLICSoftware_Handler, . - CLICSoftware_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + j . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ VPRCLIC_0_IRQHandler + IRQ VPRCLIC_1_IRQHandler + IRQ VPRCLIC_2_IRQHandler + IRQ VPRCLIC_3_IRQHandler + IRQ VPRCLIC_4_IRQHandler + IRQ VPRCLIC_5_IRQHandler + IRQ VPRCLIC_6_IRQHandler + IRQ VPRCLIC_7_IRQHandler + IRQ VPRCLIC_8_IRQHandler + IRQ VPRCLIC_9_IRQHandler + IRQ VPRCLIC_10_IRQHandler + IRQ VPRCLIC_11_IRQHandler + IRQ VPRCLIC_12_IRQHandler + IRQ VPRCLIC_13_IRQHandler + IRQ VPRCLIC_14_IRQHandler + IRQ VPRCLIC_15_IRQHandler + IRQ VPRCLIC_16_IRQHandler + IRQ VPRCLIC_17_IRQHandler + IRQ VPRCLIC_18_IRQHandler + IRQ VPRCLIC_19_IRQHandler + IRQ VPRCLIC_20_IRQHandler + IRQ VPRCLIC_21_IRQHandler + IRQ VPRCLIC_22_IRQHandler + IRQ VPRCLIC_23_IRQHandler + IRQ VPRCLIC_24_IRQHandler + IRQ VPRCLIC_25_IRQHandler + IRQ VPRCLIC_26_IRQHandler + IRQ VPRCLIC_27_IRQHandler + IRQ VPRCLIC_28_IRQHandler + IRQ VPRCLIC_29_IRQHandler + IRQ VPRCLIC_30_IRQHandler + IRQ VPRCLIC_31_IRQHandler + IRQ VPRTIM_IRQHandler + IRQ GPIOTE130_0_IRQHandler + IRQ GPIOTE130_1_IRQHandler + IRQ GPIOTE131_0_IRQHandler + IRQ GPIOTE131_1_IRQHandler + IRQ GRTC_0_IRQHandler + IRQ GRTC_1_IRQHandler + IRQ GRTC_2_IRQHandler + IRQ TBM_IRQHandler + IRQ USBHS_IRQHandler + IRQ EXMIF_IRQHandler + IRQ IPCT120_0_IRQHandler + IRQ I3C120_IRQHandler + IRQ VPR121_IRQHandler + IRQ CAN120_IRQHandler + IRQ MVDMA120_IRQHandler + IRQ CAN121_IRQHandler + IRQ MVDMA121_IRQHandler + IRQ I3C121_IRQHandler + IRQ TIMER120_IRQHandler + IRQ TIMER121_IRQHandler + IRQ PWM120_IRQHandler + IRQ SPIS120_IRQHandler + IRQ SPIM120_UARTE120_IRQHandler + IRQ SPIM121_IRQHandler + IRQ VPR130_IRQHandler + IRQ IPCT130_0_IRQHandler + IRQ RTC130_IRQHandler + IRQ RTC131_IRQHandler + IRQ WDT131_IRQHandler + IRQ WDT132_IRQHandler + IRQ EGU130_IRQHandler + IRQ SAADC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ TEMP_IRQHandler + IRQ I2S130_IRQHandler + IRQ PDM_IRQHandler + IRQ QDEC130_IRQHandler + IRQ QDEC131_IRQHandler + IRQ I2S131_IRQHandler + IRQ TIMER130_IRQHandler + IRQ TIMER131_IRQHandler + IRQ PWM130_IRQHandler + IRQ SERIAL0_IRQHandler + IRQ SERIAL1_IRQHandler + IRQ TIMER132_IRQHandler + IRQ TIMER133_IRQHandler + IRQ PWM131_IRQHandler + IRQ SERIAL2_IRQHandler + IRQ SERIAL3_IRQHandler + IRQ TIMER134_IRQHandler + IRQ TIMER135_IRQHandler + IRQ PWM132_IRQHandler + IRQ SERIAL4_IRQHandler + IRQ SERIAL5_IRQHandler + IRQ TIMER136_IRQHandler + IRQ TIMER137_IRQHandler + IRQ PWM133_IRQHandler + IRQ SERIAL6_IRQHandler + IRQ SERIAL7_IRQHandler + + .end diff --git a/mdk/gcc_startup_nrf9230_enga_ppr.S b/mdk/gcc_startup_nrf9230_enga_ppr.S new file mode 100644 index 000000000..5b389f15b --- /dev/null +++ b/mdk/gcc_startup_nrf9230_enga_ppr.S @@ -0,0 +1,925 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* + +This file was modified by Nordic Semiconductor to support RISC-V devices. + +*/ + +/* ============================ * + * Stack configuration * + * ============================ */ + +#ifndef __ASSEMBLY__ + #define __ASSEMBLY__ +#endif +#include "core_vpr.h" + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 2048 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* ============================ * + * Heap configuration * + * ============================ */ + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 2048 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + +/* ============================ * + * Startup code * + * ============================ */ +/* Reset Handler */ + + + .section .startup, "ax" + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifndef NO_STACK_INIT + /* Initialise main stack */ + la sp, __StackTop + add s0, sp, zero +#endif + + +#if !defined(NO_MTVT_CONFIG) && defined(__MTVT_PRESENT) && __MTVT_PRESENT + /* Configure machine trap vector table register */ + la t0, __isr_vector + csrw CSR_MTVT, t0 + + /* Setup machine trap vector in CSR and clear cause register (hardfault exceptions) */ + .weak Trap_Handler + la t0, Trap_Handler + csrw CSR_MTVEC, t0 + csrw CSR_MCAUSE, x0 +#endif + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __data_load_start: LMA of start of the section to copy from. Usually end of text + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + +/* Load .data */ + la t0, __data_start + la t1, __data_end + la t2, __data_load_start + jal copy_region + +/* Load .sdata */ + la t0, __sdata_start + la t1, __sdata_end + la t2, __sdata_load_start + jal copy_region + +/* Load .tdata */ + la t0, __tdata_start + la t1, __tdata_end + la t2, __tdata_load_start + jal copy_region + +/* Load .fast */ + la t0, __fast_start + la t1, __fast_end + la t2, __fast_load_start + jal copy_region + + j copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + beq t0, t1, L_copy_region_done + +L_copy_region: + lw a0,0(t2) + sw a0,0(t0) + addi t0, t0, 4 + addi t2, t2, 4 + bne t0, t1, L_copy_region + +L_copy_region_done: + + ret + +copy_etext_done: + +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start: start of the BSS section. + * __bss_end: + * __sbss_start + * __sbss_end + * __tbss_start + * __tbss_end : end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + la t0, __bss_start + la t1, __bss_end + jal zero_region + + la t0, __sbss_start + la t1, __sbss_end + jal zero_region + + la t0, __tbss_start + la t1, __tbss_end + jal zero_region + + j clear_bss_done + +/* Method that clears ram region */ +zero_region: + beq t0, t1, L_zero_region_done + +L_zero_region: + sw zero, 0(t0) + addi t0, t0, 4 + bne t0, t1, L_zero_region + +L_zero_region_done: + + ret + +clear_bss_done: + +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + jal SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + jal __START + + .size Reset_Handler,.-Reset_Handler + +/* ============================ * + * VPR interrupt return block * + * ============================ */ + .section .isr_return, "ax" + .globl __isr_return +__isr_return: + mret + +/* ============================ * + * HardFault trap * + * ============================ */ +.globl Trap_Handler +.type Trap_Handler, %function +.balign 8 +Trap_Handler: + j Trap_Handler + +/* ============================ * + * Vector table * + * ============================ */ + .section .isr_vector, "ax" + .balign 64 + .globl __isr_vector +__isr_vector: + .long UserSoftware_Handler + .long SuperVisorSoftware_Handler + .long MachineSoftware_Handler + .long 0 /*Reserved */ + .long UserTimer_Handler + .long SuperVisorTimer_Handler + .long 0 /*Reserved */ + .long MachineTimer_Handler + .long UserExternal_Handler + .long SuperVisorExternal_Handler + .long 0 /*Reserved */ + .long MachineExternal_Handler + .long CLICSoftware_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + /* External Interrupts */ + .long VPRCLIC_0_IRQHandler + .long VPRCLIC_1_IRQHandler + .long VPRCLIC_2_IRQHandler + .long VPRCLIC_3_IRQHandler + .long VPRCLIC_4_IRQHandler + .long VPRCLIC_5_IRQHandler + .long VPRCLIC_6_IRQHandler + .long VPRCLIC_7_IRQHandler + .long VPRCLIC_8_IRQHandler + .long VPRCLIC_9_IRQHandler + .long VPRCLIC_10_IRQHandler + .long VPRCLIC_11_IRQHandler + .long VPRCLIC_12_IRQHandler + .long VPRCLIC_13_IRQHandler + .long VPRCLIC_14_IRQHandler + .long VPRCLIC_15_IRQHandler + .long VPRTIM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long GPIOTE130_0_IRQHandler + .long GPIOTE130_1_IRQHandler + .long GPIOTE131_0_IRQHandler + .long GPIOTE131_1_IRQHandler + .long GRTC_0_IRQHandler + .long GRTC_1_IRQHandler + .long GRTC_2_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TBM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long USBHS_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EXMIF_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT120_0_IRQHandler + .long 0 /*Reserved */ + .long I3C120_IRQHandler + .long VPR121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long CAN120_IRQHandler + .long MVDMA120_IRQHandler + .long 0 /*Reserved */ + .long CAN121_IRQHandler + .long MVDMA121_IRQHandler + .long 0 /*Reserved */ + .long I3C121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER120_IRQHandler + .long TIMER121_IRQHandler + .long PWM120_IRQHandler + .long SPIS120_IRQHandler + .long SPIM120_UARTE120_IRQHandler + .long SPIM121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long VPR130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT130_0_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long RTC130_IRQHandler + .long RTC131_IRQHandler + .long 0 /*Reserved */ + .long WDT131_IRQHandler + .long WDT132_IRQHandler + .long EGU130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SAADC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long TEMP_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long I2S130_IRQHandler + .long PDM_IRQHandler + .long QDEC130_IRQHandler + .long QDEC131_IRQHandler + .long 0 /*Reserved */ + .long I2S131_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER130_IRQHandler + .long TIMER131_IRQHandler + .long PWM130_IRQHandler + .long SERIAL0_IRQHandler + .long SERIAL1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER132_IRQHandler + .long TIMER133_IRQHandler + .long PWM131_IRQHandler + .long SERIAL2_IRQHandler + .long SERIAL3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER134_IRQHandler + .long TIMER135_IRQHandler + .long PWM132_IRQHandler + .long SERIAL4_IRQHandler + .long SERIAL5_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER136_IRQHandler + .long TIMER137_IRQHandler + .long PWM133_IRQHandler + .long SERIAL6_IRQHandler + .long SERIAL7_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +.section .text + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak UserSoftware_Handler + .type UserSoftware_Handler, %function +UserSoftware_Handler: + j . + .size UserSoftware_Handler, . - UserSoftware_Handler + + + .weak SuperVisorSoftware_Handler + .type SuperVisorSoftware_Handler, %function +SuperVisorSoftware_Handler: + j . + .size SuperVisorSoftware_Handler, . - SuperVisorSoftware_Handler + + + .weak MachineSoftware_Handler + .type MachineSoftware_Handler, %function +MachineSoftware_Handler: + j . + .size MachineSoftware_Handler, . - MachineSoftware_Handler + + + .weak UserTimer_Handler + .type UserTimer_Handler, %function +UserTimer_Handler: + j . + .size UserTimer_Handler, . - UserTimer_Handler + + + .weak SuperVisorTimer_Handler + .type SuperVisorTimer_Handler, %function +SuperVisorTimer_Handler: + j . + .size SuperVisorTimer_Handler, . - SuperVisorTimer_Handler + + + .weak MachineTimer_Handler + .type MachineTimer_Handler, %function +MachineTimer_Handler: + j . + .size MachineTimer_Handler, . - MachineTimer_Handler + + + .weak UserExternal_Handler + .type UserExternal_Handler, %function +UserExternal_Handler: + j . + .size UserExternal_Handler, . - UserExternal_Handler + + + .weak SuperVisorExternal_Handler + .type SuperVisorExternal_Handler, %function +SuperVisorExternal_Handler: + j . + .size SuperVisorExternal_Handler, . - SuperVisorExternal_Handler + + + .weak MachineExternal_Handler + .type MachineExternal_Handler, %function +MachineExternal_Handler: + j . + .size MachineExternal_Handler, . - MachineExternal_Handler + + + .weak CLICSoftware_Handler + .type CLICSoftware_Handler, %function +CLICSoftware_Handler: + j . + .size CLICSoftware_Handler, . - CLICSoftware_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + j . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ VPRCLIC_0_IRQHandler + IRQ VPRCLIC_1_IRQHandler + IRQ VPRCLIC_2_IRQHandler + IRQ VPRCLIC_3_IRQHandler + IRQ VPRCLIC_4_IRQHandler + IRQ VPRCLIC_5_IRQHandler + IRQ VPRCLIC_6_IRQHandler + IRQ VPRCLIC_7_IRQHandler + IRQ VPRCLIC_8_IRQHandler + IRQ VPRCLIC_9_IRQHandler + IRQ VPRCLIC_10_IRQHandler + IRQ VPRCLIC_11_IRQHandler + IRQ VPRCLIC_12_IRQHandler + IRQ VPRCLIC_13_IRQHandler + IRQ VPRCLIC_14_IRQHandler + IRQ VPRCLIC_15_IRQHandler + IRQ VPRTIM_IRQHandler + IRQ GPIOTE130_0_IRQHandler + IRQ GPIOTE130_1_IRQHandler + IRQ GPIOTE131_0_IRQHandler + IRQ GPIOTE131_1_IRQHandler + IRQ GRTC_0_IRQHandler + IRQ GRTC_1_IRQHandler + IRQ GRTC_2_IRQHandler + IRQ TBM_IRQHandler + IRQ USBHS_IRQHandler + IRQ EXMIF_IRQHandler + IRQ IPCT120_0_IRQHandler + IRQ I3C120_IRQHandler + IRQ VPR121_IRQHandler + IRQ CAN120_IRQHandler + IRQ MVDMA120_IRQHandler + IRQ CAN121_IRQHandler + IRQ MVDMA121_IRQHandler + IRQ I3C121_IRQHandler + IRQ TIMER120_IRQHandler + IRQ TIMER121_IRQHandler + IRQ PWM120_IRQHandler + IRQ SPIS120_IRQHandler + IRQ SPIM120_UARTE120_IRQHandler + IRQ SPIM121_IRQHandler + IRQ VPR130_IRQHandler + IRQ IPCT130_0_IRQHandler + IRQ RTC130_IRQHandler + IRQ RTC131_IRQHandler + IRQ WDT131_IRQHandler + IRQ WDT132_IRQHandler + IRQ EGU130_IRQHandler + IRQ SAADC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ TEMP_IRQHandler + IRQ I2S130_IRQHandler + IRQ PDM_IRQHandler + IRQ QDEC130_IRQHandler + IRQ QDEC131_IRQHandler + IRQ I2S131_IRQHandler + IRQ TIMER130_IRQHandler + IRQ TIMER131_IRQHandler + IRQ PWM130_IRQHandler + IRQ SERIAL0_IRQHandler + IRQ SERIAL1_IRQHandler + IRQ TIMER132_IRQHandler + IRQ TIMER133_IRQHandler + IRQ PWM131_IRQHandler + IRQ SERIAL2_IRQHandler + IRQ SERIAL3_IRQHandler + IRQ TIMER134_IRQHandler + IRQ TIMER135_IRQHandler + IRQ PWM132_IRQHandler + IRQ SERIAL4_IRQHandler + IRQ SERIAL5_IRQHandler + IRQ TIMER136_IRQHandler + IRQ TIMER137_IRQHandler + IRQ PWM133_IRQHandler + IRQ SERIAL6_IRQHandler + IRQ SERIAL7_IRQHandler + + .end diff --git a/mdk/gcc_startup_nrf9230_enga_radiocore.S b/mdk/gcc_startup_nrf9230_enga_radiocore.S new file mode 100644 index 000000000..ea714db66 --- /dev/null +++ b/mdk/gcc_startup_nrf9230_enga_radiocore.S @@ -0,0 +1,885 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + + .syntax unified + .arch armv8-m.main + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 4096 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 4096 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector, "ax" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long SecureFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMon_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long SPU000_IRQHandler + .long MPC_IRQHandler + .long 0 /*Reserved */ + .long MVDMA_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPU010_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long WDT010_IRQHandler + .long WDT011_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPU020_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EGU020_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER020_IRQHandler + .long TIMER021_IRQHandler + .long TIMER022_IRQHandler + .long RTC_IRQHandler + .long RADIO_0_IRQHandler + .long RADIO_1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SPU030_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long VPR_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long AAR030_CCM030_IRQHandler + .long ECB030_IRQHandler + .long AAR031_CCM031_IRQHandler + .long ECB031_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT_0_IRQHandler + .long IPCT_1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SWI0_IRQHandler + .long SWI1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + .long SWI6_IRQHandler + .long SWI7_IRQHandler + .long BELLBOARD_0_IRQHandler + .long BELLBOARD_1_IRQHandler + .long BELLBOARD_2_IRQHandler + .long BELLBOARD_3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long GPIOTE130_0_IRQHandler + .long GPIOTE130_1_IRQHandler + .long GPIOTE131_0_IRQHandler + .long GPIOTE131_1_IRQHandler + .long GRTC_0_IRQHandler + .long GRTC_1_IRQHandler + .long GRTC_2_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TBM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long USBHS_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long EXMIF_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT120_0_IRQHandler + .long 0 /*Reserved */ + .long I3C120_IRQHandler + .long VPR121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long CAN120_IRQHandler + .long MVDMA120_IRQHandler + .long 0 /*Reserved */ + .long CAN121_IRQHandler + .long MVDMA121_IRQHandler + .long 0 /*Reserved */ + .long I3C121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER120_IRQHandler + .long TIMER121_IRQHandler + .long PWM120_IRQHandler + .long SPIS120_IRQHandler + .long SPIM120_UARTE120_IRQHandler + .long SPIM121_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long VPR130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long IPCT130_0_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long RTC130_IRQHandler + .long RTC131_IRQHandler + .long 0 /*Reserved */ + .long WDT131_IRQHandler + .long WDT132_IRQHandler + .long EGU130_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SAADC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long TEMP_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long I2S130_IRQHandler + .long PDM_IRQHandler + .long QDEC130_IRQHandler + .long QDEC131_IRQHandler + .long 0 /*Reserved */ + .long I2S131_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER130_IRQHandler + .long TIMER131_IRQHandler + .long PWM130_IRQHandler + .long SERIAL0_IRQHandler + .long SERIAL1_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER132_IRQHandler + .long TIMER133_IRQHandler + .long PWM131_IRQHandler + .long SERIAL2_IRQHandler + .long SERIAL3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER134_IRQHandler + .long TIMER135_IRQHandler + .long PWM132_IRQHandler + .long SERIAL4_IRQHandler + .long SERIAL5_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long TIMER136_IRQHandler + .long TIMER137_IRQHandler + .long PWM133_IRQHandler + .long SERIAL6_IRQHandler + .long SERIAL7_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start: VMA of start of the section to copy to. + * __data_end: VMA of end of the section to copy to. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifndef __STARTUP_SKIP_ETEXT + +/* Load .data */ + ldr r1, =__data_start + ldr r2, =__data_end + ldr r3, =__data_load_start + bl copy_region + +/* Load .sdata */ + ldr r1, =__sdata_start + ldr r2, =__sdata_end + ldr r3, =__sdata_load_start + bl copy_region + +/* Load .tdata */ + ldr r1, =__tdata_start + ldr r2, =__tdata_end + ldr r3, =__tdata_load_start + bl copy_region + +/* Load .fast */ + ldr r1, =__fast_start + ldr r2, =__fast_end + ldr r3, =__fast_load_start + bl copy_region + + b copy_etext_done + +/* Method that loads data from nvm to ram */ +copy_region: + subs r2, r2, r1 + ble L_copy_region_done + +L_copy_region: + subs r2, r2, #4 + ldr r0, [r3,r2] + str r0, [r1,r2] + bgt L_copy_region + +L_copy_region_done: + + bx lr + +copy_etext_done: + + +#endif + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + bl clear_region + + ldr r1, =__tbss_start__ + ldr r2, =__tbss_end__ + bl clear_region + + ldr r1, =__sbss_start__ + ldr r2, =__sbss_end__ + bl clear_region + + b clear_bss_done + +/* Method that clears default-0 registers */ +clear_region: + movs r0, 0 + + subs r2, r2, r1 + ble .L_clear_region_done + +.L_clear_region: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_clear_region + +.L_clear_region_done: + + bx lr + +clear_bss_done: + +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SecureFault_Handler + .type SecureFault_Handler, %function +SecureFault_Handler: + b . + .size SecureFault_Handler, . - SecureFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ SPU000_IRQHandler + IRQ MPC_IRQHandler + IRQ MVDMA_IRQHandler + IRQ SPU010_IRQHandler + IRQ WDT010_IRQHandler + IRQ WDT011_IRQHandler + IRQ SPU020_IRQHandler + IRQ EGU020_IRQHandler + IRQ TIMER020_IRQHandler + IRQ TIMER021_IRQHandler + IRQ TIMER022_IRQHandler + IRQ RTC_IRQHandler + IRQ RADIO_0_IRQHandler + IRQ RADIO_1_IRQHandler + IRQ SPU030_IRQHandler + IRQ VPR_IRQHandler + IRQ AAR030_CCM030_IRQHandler + IRQ ECB030_IRQHandler + IRQ AAR031_CCM031_IRQHandler + IRQ ECB031_IRQHandler + IRQ IPCT_0_IRQHandler + IRQ IPCT_1_IRQHandler + IRQ SWI0_IRQHandler + IRQ SWI1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + IRQ SWI6_IRQHandler + IRQ SWI7_IRQHandler + IRQ BELLBOARD_0_IRQHandler + IRQ BELLBOARD_1_IRQHandler + IRQ BELLBOARD_2_IRQHandler + IRQ BELLBOARD_3_IRQHandler + IRQ GPIOTE130_0_IRQHandler + IRQ GPIOTE130_1_IRQHandler + IRQ GPIOTE131_0_IRQHandler + IRQ GPIOTE131_1_IRQHandler + IRQ GRTC_0_IRQHandler + IRQ GRTC_1_IRQHandler + IRQ GRTC_2_IRQHandler + IRQ TBM_IRQHandler + IRQ USBHS_IRQHandler + IRQ EXMIF_IRQHandler + IRQ IPCT120_0_IRQHandler + IRQ I3C120_IRQHandler + IRQ VPR121_IRQHandler + IRQ CAN120_IRQHandler + IRQ MVDMA120_IRQHandler + IRQ CAN121_IRQHandler + IRQ MVDMA121_IRQHandler + IRQ I3C121_IRQHandler + IRQ TIMER120_IRQHandler + IRQ TIMER121_IRQHandler + IRQ PWM120_IRQHandler + IRQ SPIS120_IRQHandler + IRQ SPIM120_UARTE120_IRQHandler + IRQ SPIM121_IRQHandler + IRQ VPR130_IRQHandler + IRQ IPCT130_0_IRQHandler + IRQ RTC130_IRQHandler + IRQ RTC131_IRQHandler + IRQ WDT131_IRQHandler + IRQ WDT132_IRQHandler + IRQ EGU130_IRQHandler + IRQ SAADC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ TEMP_IRQHandler + IRQ I2S130_IRQHandler + IRQ PDM_IRQHandler + IRQ QDEC130_IRQHandler + IRQ QDEC131_IRQHandler + IRQ I2S131_IRQHandler + IRQ TIMER130_IRQHandler + IRQ TIMER131_IRQHandler + IRQ PWM130_IRQHandler + IRQ SERIAL0_IRQHandler + IRQ SERIAL1_IRQHandler + IRQ TIMER132_IRQHandler + IRQ TIMER133_IRQHandler + IRQ PWM131_IRQHandler + IRQ SERIAL2_IRQHandler + IRQ SERIAL3_IRQHandler + IRQ TIMER134_IRQHandler + IRQ TIMER135_IRQHandler + IRQ PWM132_IRQHandler + IRQ SERIAL4_IRQHandler + IRQ SERIAL5_IRQHandler + IRQ TIMER136_IRQHandler + IRQ TIMER137_IRQHandler + IRQ PWM133_IRQHandler + IRQ SERIAL6_IRQHandler + IRQ SERIAL7_IRQHandler + + .end diff --git a/mdk/haltium_interim.h b/mdk/haltium_interim.h index e7a4849ce..8205991dd 100644 --- a/mdk/haltium_interim.h +++ b/mdk/haltium_interim.h @@ -37,65 +37,10 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(HALTIUM_XXAA) - typedef enum { - NRF_DOMAIN_APPLICATION = 2, /* Application Core */ - NRF_DOMAIN_RADIOCORE = 3, /* Radio Core */ - NRF_DOMAIN_GLOBALFAST = 12, /* Global Domain - Fast clock domain */ - NRF_DOMAIN_GLOBALSLOW = 13, /* Global Domain - Slow clock domain */ - NRF_DOMAIN_GLOBAL = 15, /* Global Domain */ - } NRF_DOMAINID_Type; - - #define NRF_DOMAINS_t NRF_DOMAINID_Type - - - typedef enum { - NRF_OWNER_NONE = 0, /* Used to denote that ownership is not enforced */ - NRF_OWNER_APPLICATION = 2, /* Application Core */ - NRF_OWNER_RADIOCORE = 3, /* Radio Core */ - NRF_OWNER_DBG_APPLICATION = 10, /* AHB-AP for Application Core CPU */ - NRF_OWNER_DBG_RADIOCORE = 11, /* AHB-AP for Radio core CPU */ - } NRF_OWNERID_Type; - - typedef enum { - NRF_PROCESSOR_APPLICATION = 2, /* Application Core Processor */ - NRF_PROCESSOR_RADIOCORE = 3, /* Radio Core Processor */ - NRF_PROCESSOR_PPR = 13, /* Peripheral Processor */ - NRF_PROCESSOR_FLPR = 14, /* Fast Lightweight Processor */ - } NRF_PROCESSORID_Type; - #define NRF_DOMAIN_COUNT NRF_DOMAIN_GLOBAL + 1 #define NRF_PROCESSOR_COUNT NRF_PROCESSOR_FLPR + 1 - #if defined(NRF_APPLICATION) - #define NRF_DOMAIN NRF_DOMAIN_APPLICATION - #elif defined(NRF_RADIOCORE) - #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE - #elif defined(NRF_FLPR) - #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST - #elif defined(NRF_PPR) - #define NRF_DOMAIN NRF_DOMAIN_GLOBALSLOW - #endif - - #if defined(NRF_APPLICATION) - #define NRF_PROCESSOR NRF_PROCESSOR_APPLICATION - #elif defined(NRF_RADIOCORE) - #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE - #elif defined(NRF_FLPR) - #define NRF_PROCESSOR NRF_PROCESSOR_FLPR - #elif defined(NRF_PPR) - #define NRF_PROCESSOR NRF_PROCESSOR_PPR - #endif - - #if defined(NRF_APPLICATION) - #define NRF_OWNER NRF_OWNER_APPLICATION - #elif defined(NRF_RADIOCORE) - #define NRF_OWNER NRF_OWNER_RADIOCORE - #elif defined(NRF_FLPR) && !defined(NRF_OWNER) - #define NRF_OWNER NRF_OWNER_APPLICATION - #elif defined(NRF_PPR) && !defined(NRF_OWNER) - #define NRF_OWNER NRF_OWNER_APPLICATION - #endif #define ADDRESS_REGION_Pos (29UL) #define ADDRESS_REGION_Msk (0x7UL << ADDRESS_REGION_Pos) diff --git a/mdk/iar_startup_nrf9230_enga_application.s b/mdk/iar_startup_nrf9230_enga_application.s new file mode 100644 index 000000000..d330f25ca --- /dev/null +++ b/mdk/iar_startup_nrf9230_enga_application.s @@ -0,0 +1,1039 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPU000_IRQHandler + DCD MPC_IRQHandler + DCD 0 ; Reserved + DCD MVDMA_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU010_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT010_IRQHandler + DCD WDT011_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT_0_IRQHandler + DCD IPCT_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD SWI6_IRQHandler + DCD SWI7_IRQHandler + DCD BELLBOARD_0_IRQHandler + DCD BELLBOARD_1_IRQHandler + DCD BELLBOARD_2_IRQHandler + DCD BELLBOARD_3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK SPU000_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU000_IRQHandler + B . + + PUBWEAK MPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPC_IRQHandler + B . + + PUBWEAK MVDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA_IRQHandler + B . + + PUBWEAK SPU010_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU010_IRQHandler + B . + + PUBWEAK WDT010_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT010_IRQHandler + B . + + PUBWEAK WDT011_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT011_IRQHandler + B . + + PUBWEAK IPCT_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT_0_IRQHandler + B . + + PUBWEAK IPCT_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT_1_IRQHandler + B . + + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + PUBWEAK SWI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI6_IRQHandler + B . + + PUBWEAK SWI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI7_IRQHandler + B . + + PUBWEAK BELLBOARD_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_0_IRQHandler + B . + + PUBWEAK BELLBOARD_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_1_IRQHandler + B . + + PUBWEAK BELLBOARD_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_2_IRQHandler + B . + + PUBWEAK BELLBOARD_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_3_IRQHandler + B . + + PUBWEAK GPIOTE130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_0_IRQHandler + B . + + PUBWEAK GPIOTE130_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_1_IRQHandler + B . + + PUBWEAK GPIOTE131_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_0_IRQHandler + B . + + PUBWEAK GPIOTE131_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_1_IRQHandler + B . + + PUBWEAK GRTC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_0_IRQHandler + B . + + PUBWEAK GRTC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_1_IRQHandler + B . + + PUBWEAK GRTC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_2_IRQHandler + B . + + PUBWEAK TBM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TBM_IRQHandler + B . + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBHS_IRQHandler + B . + + PUBWEAK EXMIF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXMIF_IRQHandler + B . + + PUBWEAK IPCT120_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT120_0_IRQHandler + B . + + PUBWEAK I3C120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C120_IRQHandler + B . + + PUBWEAK VPR121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR121_IRQHandler + B . + + PUBWEAK CAN120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN120_IRQHandler + B . + + PUBWEAK MVDMA120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA120_IRQHandler + B . + + PUBWEAK CAN121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN121_IRQHandler + B . + + PUBWEAK MVDMA121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA121_IRQHandler + B . + + PUBWEAK I3C121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C121_IRQHandler + B . + + PUBWEAK TIMER120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER120_IRQHandler + B . + + PUBWEAK TIMER121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER121_IRQHandler + B . + + PUBWEAK PWM120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM120_IRQHandler + B . + + PUBWEAK SPIS120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS120_IRQHandler + B . + + PUBWEAK SPIM120_UARTE120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM120_UARTE120_IRQHandler + B . + + PUBWEAK SPIM121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM121_IRQHandler + B . + + PUBWEAK VPR130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR130_IRQHandler + B . + + PUBWEAK IPCT130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT130_0_IRQHandler + B . + + PUBWEAK RTC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC130_IRQHandler + B . + + PUBWEAK RTC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC131_IRQHandler + B . + + PUBWEAK WDT131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT131_IRQHandler + B . + + PUBWEAK WDT132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT132_IRQHandler + B . + + PUBWEAK EGU130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU130_IRQHandler + B . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + B . + + PUBWEAK COMP_LPCOMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_LPCOMP_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + + PUBWEAK I2S130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S130_IRQHandler + B . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + B . + + PUBWEAK QDEC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC130_IRQHandler + B . + + PUBWEAK QDEC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC131_IRQHandler + B . + + PUBWEAK I2S131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S131_IRQHandler + B . + + PUBWEAK TIMER130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER130_IRQHandler + B . + + PUBWEAK TIMER131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER131_IRQHandler + B . + + PUBWEAK PWM130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM130_IRQHandler + B . + + PUBWEAK SERIAL0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL0_IRQHandler + B . + + PUBWEAK SERIAL1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL1_IRQHandler + B . + + PUBWEAK TIMER132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER132_IRQHandler + B . + + PUBWEAK TIMER133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER133_IRQHandler + B . + + PUBWEAK PWM131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM131_IRQHandler + B . + + PUBWEAK SERIAL2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL2_IRQHandler + B . + + PUBWEAK SERIAL3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL3_IRQHandler + B . + + PUBWEAK TIMER134_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER134_IRQHandler + B . + + PUBWEAK TIMER135_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER135_IRQHandler + B . + + PUBWEAK PWM132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM132_IRQHandler + B . + + PUBWEAK SERIAL4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL4_IRQHandler + B . + + PUBWEAK SERIAL5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL5_IRQHandler + B . + + PUBWEAK TIMER136_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER136_IRQHandler + B . + + PUBWEAK TIMER137_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER137_IRQHandler + B . + + PUBWEAK PWM133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM133_IRQHandler + B . + + PUBWEAK SERIAL6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL6_IRQHandler + B . + + PUBWEAK SERIAL7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL7_IRQHandler + B . + + END + + diff --git a/mdk/iar_startup_nrf9230_enga_flpr.s b/mdk/iar_startup_nrf9230_enga_flpr.s new file mode 100644 index 000000000..60f521d50 --- /dev/null +++ b/mdk/iar_startup_nrf9230_enga_flpr.s @@ -0,0 +1,1102 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + + ALIGN 6 ;; Align to 64 byte boundary. +__vector_table + DCD sfe(CSTACK) + DCD UserSoftware_Handler + DCD SuperVisorSoftware_Handler + DCD MachineSoftware_Handler + DCD 0 ; Reserved + DCD UserTimer_Handler + DCD SuperVisorTimer_Handler + DCD 0 ; Reserved + DCD MachineTimer_Handler + DCD UserExternal_Handler + DCD SuperVisorExternal_Handler + DCD 0 ; Reserved + DCD MachineExternal_Handler + DCD CLICSoftware_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + + ; External Interrupts + DCD VPRCLIC_0_IRQHandler + DCD VPRCLIC_1_IRQHandler + DCD VPRCLIC_2_IRQHandler + DCD VPRCLIC_3_IRQHandler + DCD VPRCLIC_4_IRQHandler + DCD VPRCLIC_5_IRQHandler + DCD VPRCLIC_6_IRQHandler + DCD VPRCLIC_7_IRQHandler + DCD VPRCLIC_8_IRQHandler + DCD VPRCLIC_9_IRQHandler + DCD VPRCLIC_10_IRQHandler + DCD VPRCLIC_11_IRQHandler + DCD VPRCLIC_12_IRQHandler + DCD VPRCLIC_13_IRQHandler + DCD VPRCLIC_14_IRQHandler + DCD VPRCLIC_15_IRQHandler + DCD VPRCLIC_16_IRQHandler + DCD VPRCLIC_17_IRQHandler + DCD VPRCLIC_18_IRQHandler + DCD VPRCLIC_19_IRQHandler + DCD VPRCLIC_20_IRQHandler + DCD VPRCLIC_21_IRQHandler + DCD VPRCLIC_22_IRQHandler + DCD VPRCLIC_23_IRQHandler + DCD VPRCLIC_24_IRQHandler + DCD VPRCLIC_25_IRQHandler + DCD VPRCLIC_26_IRQHandler + DCD VPRCLIC_27_IRQHandler + DCD VPRCLIC_28_IRQHandler + DCD VPRCLIC_29_IRQHandler + DCD VPRCLIC_30_IRQHandler + DCD VPRCLIC_31_IRQHandler + DCD VPRTIM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + jal ra, SystemInit + j __iar_program_start + + ; Dummy exception handlers + + + PUBWEAK UserSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserSoftware_Handler + j . + + PUBWEAK SuperVisorSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorSoftware_Handler + j . + + PUBWEAK MachineSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineSoftware_Handler + j . + + PUBWEAK UserTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserTimer_Handler + j . + + PUBWEAK SuperVisorTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorTimer_Handler + j . + + PUBWEAK MachineTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineTimer_Handler + j . + + PUBWEAK UserExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserExternal_Handler + j . + + PUBWEAK SuperVisorExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorExternal_Handler + j . + + PUBWEAK MachineExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineExternal_Handler + j . + + PUBWEAK CLICSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CLICSoftware_Handler + j . + + + ; Dummy interrupt handlers + + PUBWEAK VPRCLIC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_0_IRQHandler + j . + + PUBWEAK VPRCLIC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_1_IRQHandler + j . + + PUBWEAK VPRCLIC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_2_IRQHandler + j . + + PUBWEAK VPRCLIC_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_3_IRQHandler + j . + + PUBWEAK VPRCLIC_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_4_IRQHandler + j . + + PUBWEAK VPRCLIC_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_5_IRQHandler + j . + + PUBWEAK VPRCLIC_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_6_IRQHandler + j . + + PUBWEAK VPRCLIC_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_7_IRQHandler + j . + + PUBWEAK VPRCLIC_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_8_IRQHandler + j . + + PUBWEAK VPRCLIC_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_9_IRQHandler + j . + + PUBWEAK VPRCLIC_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_10_IRQHandler + j . + + PUBWEAK VPRCLIC_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_11_IRQHandler + j . + + PUBWEAK VPRCLIC_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_12_IRQHandler + j . + + PUBWEAK VPRCLIC_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_13_IRQHandler + j . + + PUBWEAK VPRCLIC_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_14_IRQHandler + j . + + PUBWEAK VPRCLIC_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_15_IRQHandler + j . + + PUBWEAK VPRCLIC_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_16_IRQHandler + j . + + PUBWEAK VPRCLIC_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_17_IRQHandler + j . + + PUBWEAK VPRCLIC_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_18_IRQHandler + j . + + PUBWEAK VPRCLIC_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_19_IRQHandler + j . + + PUBWEAK VPRCLIC_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_20_IRQHandler + j . + + PUBWEAK VPRCLIC_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_21_IRQHandler + j . + + PUBWEAK VPRCLIC_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_22_IRQHandler + j . + + PUBWEAK VPRCLIC_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_23_IRQHandler + j . + + PUBWEAK VPRCLIC_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_24_IRQHandler + j . + + PUBWEAK VPRCLIC_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_25_IRQHandler + j . + + PUBWEAK VPRCLIC_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_26_IRQHandler + j . + + PUBWEAK VPRCLIC_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_27_IRQHandler + j . + + PUBWEAK VPRCLIC_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_28_IRQHandler + j . + + PUBWEAK VPRCLIC_29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_29_IRQHandler + j . + + PUBWEAK VPRCLIC_30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_30_IRQHandler + j . + + PUBWEAK VPRCLIC_31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_31_IRQHandler + j . + + PUBWEAK VPRTIM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRTIM_IRQHandler + j . + + PUBWEAK GPIOTE130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_0_IRQHandler + j . + + PUBWEAK GPIOTE130_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_1_IRQHandler + j . + + PUBWEAK GPIOTE131_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_0_IRQHandler + j . + + PUBWEAK GPIOTE131_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_1_IRQHandler + j . + + PUBWEAK GRTC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_0_IRQHandler + j . + + PUBWEAK GRTC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_1_IRQHandler + j . + + PUBWEAK GRTC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_2_IRQHandler + j . + + PUBWEAK TBM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TBM_IRQHandler + j . + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBHS_IRQHandler + j . + + PUBWEAK EXMIF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXMIF_IRQHandler + j . + + PUBWEAK IPCT120_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT120_0_IRQHandler + j . + + PUBWEAK I3C120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C120_IRQHandler + j . + + PUBWEAK VPR121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR121_IRQHandler + j . + + PUBWEAK CAN120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN120_IRQHandler + j . + + PUBWEAK MVDMA120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA120_IRQHandler + j . + + PUBWEAK CAN121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN121_IRQHandler + j . + + PUBWEAK MVDMA121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA121_IRQHandler + j . + + PUBWEAK I3C121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C121_IRQHandler + j . + + PUBWEAK TIMER120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER120_IRQHandler + j . + + PUBWEAK TIMER121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER121_IRQHandler + j . + + PUBWEAK PWM120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM120_IRQHandler + j . + + PUBWEAK SPIS120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS120_IRQHandler + j . + + PUBWEAK SPIM120_UARTE120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM120_UARTE120_IRQHandler + j . + + PUBWEAK SPIM121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM121_IRQHandler + j . + + PUBWEAK VPR130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR130_IRQHandler + j . + + PUBWEAK IPCT130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT130_0_IRQHandler + j . + + PUBWEAK RTC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC130_IRQHandler + j . + + PUBWEAK RTC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC131_IRQHandler + j . + + PUBWEAK WDT131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT131_IRQHandler + j . + + PUBWEAK WDT132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT132_IRQHandler + j . + + PUBWEAK EGU130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU130_IRQHandler + j . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + j . + + PUBWEAK COMP_LPCOMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_LPCOMP_IRQHandler + j . + + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + j . + + PUBWEAK I2S130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S130_IRQHandler + j . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + j . + + PUBWEAK QDEC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC130_IRQHandler + j . + + PUBWEAK QDEC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC131_IRQHandler + j . + + PUBWEAK I2S131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S131_IRQHandler + j . + + PUBWEAK TIMER130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER130_IRQHandler + j . + + PUBWEAK TIMER131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER131_IRQHandler + j . + + PUBWEAK PWM130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM130_IRQHandler + j . + + PUBWEAK SERIAL0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL0_IRQHandler + j . + + PUBWEAK SERIAL1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL1_IRQHandler + j . + + PUBWEAK TIMER132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER132_IRQHandler + j . + + PUBWEAK TIMER133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER133_IRQHandler + j . + + PUBWEAK PWM131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM131_IRQHandler + j . + + PUBWEAK SERIAL2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL2_IRQHandler + j . + + PUBWEAK SERIAL3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL3_IRQHandler + j . + + PUBWEAK TIMER134_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER134_IRQHandler + j . + + PUBWEAK TIMER135_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER135_IRQHandler + j . + + PUBWEAK PWM132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM132_IRQHandler + j . + + PUBWEAK SERIAL4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL4_IRQHandler + j . + + PUBWEAK SERIAL5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL5_IRQHandler + j . + + PUBWEAK TIMER136_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER136_IRQHandler + j . + + PUBWEAK TIMER137_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER137_IRQHandler + j . + + PUBWEAK PWM133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM133_IRQHandler + j . + + PUBWEAK SERIAL6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL6_IRQHandler + j . + + PUBWEAK SERIAL7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL7_IRQHandler + j . + + END + + diff --git a/mdk/iar_startup_nrf9230_enga_ppr.s b/mdk/iar_startup_nrf9230_enga_ppr.s new file mode 100644 index 000000000..f2a3bfac9 --- /dev/null +++ b/mdk/iar_startup_nrf9230_enga_ppr.s @@ -0,0 +1,1022 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + + ALIGN 6 ;; Align to 64 byte boundary. +__vector_table + DCD sfe(CSTACK) + DCD UserSoftware_Handler + DCD SuperVisorSoftware_Handler + DCD MachineSoftware_Handler + DCD 0 ; Reserved + DCD UserTimer_Handler + DCD SuperVisorTimer_Handler + DCD 0 ; Reserved + DCD MachineTimer_Handler + DCD UserExternal_Handler + DCD SuperVisorExternal_Handler + DCD 0 ; Reserved + DCD MachineExternal_Handler + DCD CLICSoftware_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + + ; External Interrupts + DCD VPRCLIC_0_IRQHandler + DCD VPRCLIC_1_IRQHandler + DCD VPRCLIC_2_IRQHandler + DCD VPRCLIC_3_IRQHandler + DCD VPRCLIC_4_IRQHandler + DCD VPRCLIC_5_IRQHandler + DCD VPRCLIC_6_IRQHandler + DCD VPRCLIC_7_IRQHandler + DCD VPRCLIC_8_IRQHandler + DCD VPRCLIC_9_IRQHandler + DCD VPRCLIC_10_IRQHandler + DCD VPRCLIC_11_IRQHandler + DCD VPRCLIC_12_IRQHandler + DCD VPRCLIC_13_IRQHandler + DCD VPRCLIC_14_IRQHandler + DCD VPRCLIC_15_IRQHandler + DCD VPRTIM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + jal ra, SystemInit + j __iar_program_start + + ; Dummy exception handlers + + + PUBWEAK UserSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserSoftware_Handler + j . + + PUBWEAK SuperVisorSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorSoftware_Handler + j . + + PUBWEAK MachineSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineSoftware_Handler + j . + + PUBWEAK UserTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserTimer_Handler + j . + + PUBWEAK SuperVisorTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorTimer_Handler + j . + + PUBWEAK MachineTimer_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineTimer_Handler + j . + + PUBWEAK UserExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UserExternal_Handler + j . + + PUBWEAK SuperVisorExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SuperVisorExternal_Handler + j . + + PUBWEAK MachineExternal_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MachineExternal_Handler + j . + + PUBWEAK CLICSoftware_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CLICSoftware_Handler + j . + + + ; Dummy interrupt handlers + + PUBWEAK VPRCLIC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_0_IRQHandler + j . + + PUBWEAK VPRCLIC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_1_IRQHandler + j . + + PUBWEAK VPRCLIC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_2_IRQHandler + j . + + PUBWEAK VPRCLIC_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_3_IRQHandler + j . + + PUBWEAK VPRCLIC_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_4_IRQHandler + j . + + PUBWEAK VPRCLIC_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_5_IRQHandler + j . + + PUBWEAK VPRCLIC_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_6_IRQHandler + j . + + PUBWEAK VPRCLIC_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_7_IRQHandler + j . + + PUBWEAK VPRCLIC_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_8_IRQHandler + j . + + PUBWEAK VPRCLIC_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_9_IRQHandler + j . + + PUBWEAK VPRCLIC_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_10_IRQHandler + j . + + PUBWEAK VPRCLIC_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_11_IRQHandler + j . + + PUBWEAK VPRCLIC_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_12_IRQHandler + j . + + PUBWEAK VPRCLIC_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_13_IRQHandler + j . + + PUBWEAK VPRCLIC_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_14_IRQHandler + j . + + PUBWEAK VPRCLIC_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRCLIC_15_IRQHandler + j . + + PUBWEAK VPRTIM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPRTIM_IRQHandler + j . + + PUBWEAK GPIOTE130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_0_IRQHandler + j . + + PUBWEAK GPIOTE130_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_1_IRQHandler + j . + + PUBWEAK GPIOTE131_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_0_IRQHandler + j . + + PUBWEAK GPIOTE131_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_1_IRQHandler + j . + + PUBWEAK GRTC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_0_IRQHandler + j . + + PUBWEAK GRTC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_1_IRQHandler + j . + + PUBWEAK GRTC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_2_IRQHandler + j . + + PUBWEAK TBM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TBM_IRQHandler + j . + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBHS_IRQHandler + j . + + PUBWEAK EXMIF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXMIF_IRQHandler + j . + + PUBWEAK IPCT120_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT120_0_IRQHandler + j . + + PUBWEAK I3C120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C120_IRQHandler + j . + + PUBWEAK VPR121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR121_IRQHandler + j . + + PUBWEAK CAN120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN120_IRQHandler + j . + + PUBWEAK MVDMA120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA120_IRQHandler + j . + + PUBWEAK CAN121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN121_IRQHandler + j . + + PUBWEAK MVDMA121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA121_IRQHandler + j . + + PUBWEAK I3C121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C121_IRQHandler + j . + + PUBWEAK TIMER120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER120_IRQHandler + j . + + PUBWEAK TIMER121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER121_IRQHandler + j . + + PUBWEAK PWM120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM120_IRQHandler + j . + + PUBWEAK SPIS120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS120_IRQHandler + j . + + PUBWEAK SPIM120_UARTE120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM120_UARTE120_IRQHandler + j . + + PUBWEAK SPIM121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM121_IRQHandler + j . + + PUBWEAK VPR130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR130_IRQHandler + j . + + PUBWEAK IPCT130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT130_0_IRQHandler + j . + + PUBWEAK RTC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC130_IRQHandler + j . + + PUBWEAK RTC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC131_IRQHandler + j . + + PUBWEAK WDT131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT131_IRQHandler + j . + + PUBWEAK WDT132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT132_IRQHandler + j . + + PUBWEAK EGU130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU130_IRQHandler + j . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + j . + + PUBWEAK COMP_LPCOMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_LPCOMP_IRQHandler + j . + + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + j . + + PUBWEAK I2S130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S130_IRQHandler + j . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + j . + + PUBWEAK QDEC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC130_IRQHandler + j . + + PUBWEAK QDEC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC131_IRQHandler + j . + + PUBWEAK I2S131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S131_IRQHandler + j . + + PUBWEAK TIMER130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER130_IRQHandler + j . + + PUBWEAK TIMER131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER131_IRQHandler + j . + + PUBWEAK PWM130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM130_IRQHandler + j . + + PUBWEAK SERIAL0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL0_IRQHandler + j . + + PUBWEAK SERIAL1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL1_IRQHandler + j . + + PUBWEAK TIMER132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER132_IRQHandler + j . + + PUBWEAK TIMER133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER133_IRQHandler + j . + + PUBWEAK PWM131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM131_IRQHandler + j . + + PUBWEAK SERIAL2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL2_IRQHandler + j . + + PUBWEAK SERIAL3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL3_IRQHandler + j . + + PUBWEAK TIMER134_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER134_IRQHandler + j . + + PUBWEAK TIMER135_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER135_IRQHandler + j . + + PUBWEAK PWM132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM132_IRQHandler + j . + + PUBWEAK SERIAL4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL4_IRQHandler + j . + + PUBWEAK SERIAL5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL5_IRQHandler + j . + + PUBWEAK TIMER136_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER136_IRQHandler + j . + + PUBWEAK TIMER137_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER137_IRQHandler + j . + + PUBWEAK PWM133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM133_IRQHandler + j . + + PUBWEAK SERIAL6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL6_IRQHandler + j . + + PUBWEAK SERIAL7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL7_IRQHandler + j . + + END + + diff --git a/mdk/iar_startup_nrf9230_enga_radiocore.s b/mdk/iar_startup_nrf9230_enga_radiocore.s new file mode 100644 index 000000000..9bdb43da2 --- /dev/null +++ b/mdk/iar_startup_nrf9230_enga_radiocore.s @@ -0,0 +1,1109 @@ +; Copyright (c) 2009-2024 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD SecureFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD SPU000_IRQHandler + DCD MPC_IRQHandler + DCD 0 ; Reserved + DCD MVDMA_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU010_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WDT010_IRQHandler + DCD WDT011_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU020_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EGU020_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER020_IRQHandler + DCD TIMER021_IRQHandler + DCD TIMER022_IRQHandler + DCD RTC_IRQHandler + DCD RADIO_0_IRQHandler + DCD RADIO_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPU030_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD AAR030_CCM030_IRQHandler + DCD ECB030_IRQHandler + DCD AAR031_CCM031_IRQHandler + DCD ECB031_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT_0_IRQHandler + DCD IPCT_1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SWI0_IRQHandler + DCD SWI1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD SWI6_IRQHandler + DCD SWI7_IRQHandler + DCD BELLBOARD_0_IRQHandler + DCD BELLBOARD_1_IRQHandler + DCD BELLBOARD_2_IRQHandler + DCD BELLBOARD_3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD GPIOTE130_0_IRQHandler + DCD GPIOTE130_1_IRQHandler + DCD GPIOTE131_0_IRQHandler + DCD GPIOTE131_1_IRQHandler + DCD GRTC_0_IRQHandler + DCD GRTC_1_IRQHandler + DCD GRTC_2_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TBM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBHS_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXMIF_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT120_0_IRQHandler + DCD 0 ; Reserved + DCD I3C120_IRQHandler + DCD VPR121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN120_IRQHandler + DCD MVDMA120_IRQHandler + DCD 0 ; Reserved + DCD CAN121_IRQHandler + DCD MVDMA121_IRQHandler + DCD 0 ; Reserved + DCD I3C121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER120_IRQHandler + DCD TIMER121_IRQHandler + DCD PWM120_IRQHandler + DCD SPIS120_IRQHandler + DCD SPIM120_UARTE120_IRQHandler + DCD SPIM121_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD VPR130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD IPCT130_0_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RTC130_IRQHandler + DCD RTC131_IRQHandler + DCD 0 ; Reserved + DCD WDT131_IRQHandler + DCD WDT132_IRQHandler + DCD EGU130_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAADC_IRQHandler + DCD COMP_LPCOMP_IRQHandler + DCD TEMP_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2S130_IRQHandler + DCD PDM_IRQHandler + DCD QDEC130_IRQHandler + DCD QDEC131_IRQHandler + DCD 0 ; Reserved + DCD I2S131_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER130_IRQHandler + DCD TIMER131_IRQHandler + DCD PWM130_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER132_IRQHandler + DCD TIMER133_IRQHandler + DCD PWM131_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER134_IRQHandler + DCD TIMER135_IRQHandler + DCD PWM132_IRQHandler + DCD SERIAL4_IRQHandler + DCD SERIAL5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIMER136_IRQHandler + DCD TIMER137_IRQHandler + DCD PWM133_IRQHandler + DCD SERIAL6_IRQHandler + DCD SERIAL7_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK SPU000_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU000_IRQHandler + B . + + PUBWEAK MPC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPC_IRQHandler + B . + + PUBWEAK MVDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA_IRQHandler + B . + + PUBWEAK SPU010_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU010_IRQHandler + B . + + PUBWEAK WDT010_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT010_IRQHandler + B . + + PUBWEAK WDT011_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT011_IRQHandler + B . + + PUBWEAK SPU020_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU020_IRQHandler + B . + + PUBWEAK EGU020_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU020_IRQHandler + B . + + PUBWEAK TIMER020_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER020_IRQHandler + B . + + PUBWEAK TIMER021_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER021_IRQHandler + B . + + PUBWEAK TIMER022_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER022_IRQHandler + B . + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B . + + PUBWEAK RADIO_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_0_IRQHandler + B . + + PUBWEAK RADIO_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_1_IRQHandler + B . + + PUBWEAK SPU030_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPU030_IRQHandler + B . + + PUBWEAK VPR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR_IRQHandler + B . + + PUBWEAK AAR030_CCM030_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AAR030_CCM030_IRQHandler + B . + + PUBWEAK ECB030_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB030_IRQHandler + B . + + PUBWEAK AAR031_CCM031_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AAR031_CCM031_IRQHandler + B . + + PUBWEAK ECB031_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB031_IRQHandler + B . + + PUBWEAK IPCT_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT_0_IRQHandler + B . + + PUBWEAK IPCT_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT_1_IRQHandler + B . + + PUBWEAK SWI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_IRQHandler + B . + + PUBWEAK SWI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_IRQHandler + B . + + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + PUBWEAK SWI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI6_IRQHandler + B . + + PUBWEAK SWI7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI7_IRQHandler + B . + + PUBWEAK BELLBOARD_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_0_IRQHandler + B . + + PUBWEAK BELLBOARD_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_1_IRQHandler + B . + + PUBWEAK BELLBOARD_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_2_IRQHandler + B . + + PUBWEAK BELLBOARD_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BELLBOARD_3_IRQHandler + B . + + PUBWEAK GPIOTE130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_0_IRQHandler + B . + + PUBWEAK GPIOTE130_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE130_1_IRQHandler + B . + + PUBWEAK GPIOTE131_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_0_IRQHandler + B . + + PUBWEAK GPIOTE131_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE131_1_IRQHandler + B . + + PUBWEAK GRTC_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_0_IRQHandler + B . + + PUBWEAK GRTC_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_1_IRQHandler + B . + + PUBWEAK GRTC_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GRTC_2_IRQHandler + B . + + PUBWEAK TBM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TBM_IRQHandler + B . + + PUBWEAK USBHS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USBHS_IRQHandler + B . + + PUBWEAK EXMIF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXMIF_IRQHandler + B . + + PUBWEAK IPCT120_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT120_0_IRQHandler + B . + + PUBWEAK I3C120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C120_IRQHandler + B . + + PUBWEAK VPR121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR121_IRQHandler + B . + + PUBWEAK CAN120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN120_IRQHandler + B . + + PUBWEAK MVDMA120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA120_IRQHandler + B . + + PUBWEAK CAN121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN121_IRQHandler + B . + + PUBWEAK MVDMA121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MVDMA121_IRQHandler + B . + + PUBWEAK I3C121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I3C121_IRQHandler + B . + + PUBWEAK TIMER120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER120_IRQHandler + B . + + PUBWEAK TIMER121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER121_IRQHandler + B . + + PUBWEAK PWM120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM120_IRQHandler + B . + + PUBWEAK SPIS120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS120_IRQHandler + B . + + PUBWEAK SPIM120_UARTE120_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM120_UARTE120_IRQHandler + B . + + PUBWEAK SPIM121_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM121_IRQHandler + B . + + PUBWEAK VPR130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VPR130_IRQHandler + B . + + PUBWEAK IPCT130_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IPCT130_0_IRQHandler + B . + + PUBWEAK RTC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC130_IRQHandler + B . + + PUBWEAK RTC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC131_IRQHandler + B . + + PUBWEAK WDT131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT131_IRQHandler + B . + + PUBWEAK WDT132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT132_IRQHandler + B . + + PUBWEAK EGU130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EGU130_IRQHandler + B . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + B . + + PUBWEAK COMP_LPCOMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_LPCOMP_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + + PUBWEAK I2S130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S130_IRQHandler + B . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + B . + + PUBWEAK QDEC130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC130_IRQHandler + B . + + PUBWEAK QDEC131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC131_IRQHandler + B . + + PUBWEAK I2S131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S131_IRQHandler + B . + + PUBWEAK TIMER130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER130_IRQHandler + B . + + PUBWEAK TIMER131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER131_IRQHandler + B . + + PUBWEAK PWM130_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM130_IRQHandler + B . + + PUBWEAK SERIAL0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL0_IRQHandler + B . + + PUBWEAK SERIAL1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL1_IRQHandler + B . + + PUBWEAK TIMER132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER132_IRQHandler + B . + + PUBWEAK TIMER133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER133_IRQHandler + B . + + PUBWEAK PWM131_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM131_IRQHandler + B . + + PUBWEAK SERIAL2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL2_IRQHandler + B . + + PUBWEAK SERIAL3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL3_IRQHandler + B . + + PUBWEAK TIMER134_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER134_IRQHandler + B . + + PUBWEAK TIMER135_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER135_IRQHandler + B . + + PUBWEAK PWM132_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM132_IRQHandler + B . + + PUBWEAK SERIAL4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL4_IRQHandler + B . + + PUBWEAK SERIAL5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL5_IRQHandler + B . + + PUBWEAK TIMER136_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER136_IRQHandler + B . + + PUBWEAK TIMER137_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER137_IRQHandler + B . + + PUBWEAK PWM133_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM133_IRQHandler + B . + + PUBWEAK SERIAL6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL6_IRQHandler + B . + + PUBWEAK SERIAL7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SERIAL7_IRQHandler + B . + + END + + diff --git a/mdk/nrf.h b/mdk/nrf.h index df318e42b..f608cda10 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -37,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 63 -#define MDK_MICRO_VERSION 2 +#define MDK_MINOR_VERSION 64 +#define MDK_MICRO_VERSION 0 /* Define coprocessor domains */ @@ -139,6 +139,16 @@ POSSIBILITY OF SUCH DAMAGE. #endif #endif +/* Define NRF92_SERIES for common use in nRF92 series devices. */ +#if defined(NRF9230_ENGA_XXAA) + #ifndef NRF92_SERIES + #define NRF92_SERIES + #endif + #ifndef HALTIUM_XXAA + #define HALTIUM_XXAA + #endif +#endif + /* Device selection for device includes. */ #if defined (NRF51) #include "nrf51.h" @@ -244,6 +254,11 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) #endif +#elif defined (NRF9230_ENGA_XXAA) + #include "nrf9230_enga.h" + #include "nrf9230_enga_interim.h" + #include "nrf9230_enga_name_change.h" + #else #error "Device must be defined. See nrf.h." #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 8309c000c..b0018a4af 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:51 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:01 * from File 'nrf51.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52.h b/mdk/nrf52.h index e520d686b..fb51e8131 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:55 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:04 * from File 'nrf52.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index d5cb3ec90..a4cc5f58d 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:52 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:01 * from File 'nrf52805.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 5f747325e..07e26a95d 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:52 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:02 * from File 'nrf52810.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index a1b0a2212..1cef481cb 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:53 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:03 * from File 'nrf52811.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 2281196e8..cfaeaa428 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:54 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:03 * from File 'nrf52820.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index 3f052cc93..a1dcabbb0 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:56 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:06 * from File 'nrf52833.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 19d17decd..aa5d337c1 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:57 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:07 * from File 'nrf52840.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index 0407a981c..2de23ba10 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -14606,7 +14606,7 @@ static bool nrf52_errata_272(void) case 0x00ul: return false; case 0x01ul: - return false; + return true; case 0x02ul: return true; case 0x03ul: @@ -14621,7 +14621,8 @@ static bool nrf52_errata_272(void) } /* ========= Errata 273 ========= */ -#if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) #define NRF52_ERRATA_273_PRESENT 1 #else #define NRF52_ERRATA_273_PRESENT 0 @@ -14636,17 +14637,34 @@ static bool nrf52_errata_273(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) if (var1 == 0x0E) { switch(var2) { case 0x00ul: - return false; + return true; case 0x01ul: return true; default: diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index a68e748fb..e0ea97e4d 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:17:59 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:09 * from File 'nrf5340_application.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index 4dad18872..9ea44ff7b 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:18:06 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:16 * from File 'nrf5340_network.svd', - * last modified on Wednesday, 28.02.2024 14:17:06 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index 52f919ad0..370b22e10 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -154,6 +154,7 @@ static bool nrf53_errata_165(void) __UNUSED; static bool nrf53_errata_166(void) __UNUSED; static bool nrf53_errata_167(void) __UNUSED; static bool nrf53_errata_168(void) __UNUSED; +static bool nrf53_errata_169(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -6427,4 +6428,64 @@ static bool nrf53_errata_168(void) #endif } +/* ========= Errata 169 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_169_PRESENT 1 + #else + #define NRF53_ERRATA_169_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_169_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_169_ENABLE_WORKAROUND + #define NRF53_ERRATA_169_ENABLE_WORKAROUND NRF53_ERRATA_169_PRESENT +#endif + +static bool nrf53_errata_169(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + #endif /* NRF53_ERRATAS_H */ diff --git a/mdk/nrf54h20_application.h b/mdk/nrf54h20_application.h index 175e3348c..62d651f11 100644 --- a/mdk/nrf54h20_application.h +++ b/mdk/nrf54h20_application.h @@ -256,6 +256,15 @@ typedef enum { #endif /*!< NRF_APPLICATION */ +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_APPLICATION + #define NRF_PROCESSOR NRF_PROCESSOR_APPLICATION + #define NRF_OWNER NRF_OWNER_APPLICATION + +#endif /*!< NRF_APPLICATION */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_application.svd b/mdk/nrf54h20_application.svd index e64a3e114..ff46595f5 100644 --- a/mdk/nrf54h20_application.svd +++ b/mdk/nrf54h20_application.svd @@ -12950,6 +12950,660 @@ POSSIBILITY OF SUCH DAMAGE. + + TAMPER + Unspecified + UICR_TAMPER + read-write + 0x760 + + DETECTION + Tamper policy configuration for detected security events. + UICR_TAMPER_DETECTION + read-write + 0x000 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + GlobalEnable + Enable tamper detection. When disabled all tamper enable and policy switches are ignored. + 0 + 0 + + + Enable + Enable tamper detection. + 0x0 + + + Disable + Disable tamper detection. + 0x1 + + + + + VoltageLevel + Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when voltage on the corresponding supply line is too low. + 1 + 1 + + + Enable + Enable voltage level detectors. + 0x0 + + + Disable + Disable voltage level detectors. + 0x1 + + + + + ExternalActiveShield + Enable external active shield detector. + 4 + 4 + + + Enable + Enable external active shield detector. + 0x0 + + + Disable + Disable external active shield detector. + 0x1 + + + + + HardFault + Configure if tamper prevention should react on hard faults. + 7 + 7 + + + Enable + Enable hard fault detector. + 0x0 + + + Disable + Disable hard fault detector. + 0x1 + + + + + ApiFault + Configure if tamper prevention should react on invalid API usage. + 8 + 8 + + + Enable + Enable API fault detector. + 0x0 + + + Disable + Disable API fault detector. + 0x1 + + + + + AdacFault + Configure if tamper prevention should react on invalid ADAC usage. + 9 + 9 + + + Enable + Enable invalid ADAC usage detector. + 0x0 + + + Disable + Disable invalid ADAC usage detector. + 0x1 + + + + + StateFault + Configure if tamper prevention should react on invalid firmware execution state. + 10 + 10 + + + Enable + Enable invalid firmware execution state detector. + 0x0 + + + Disable + Disable invalid firmware execution state detector. + 0x1 + + + + + TemperatureFault + Configure if tamper prevention should react when on-die temperature exceeds a valid range. + 11 + 11 + + + Enable + Enable invalid out-of-range temperature detector. + 0x0 + + + Disable + Disable invalid out-of-range temperature detector. + 0x1 + + + + + + + RESPONSE0 + Unspecified + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + VoltageLevel + Configure tamper policy for invalid voltage level on supply lines. + 0 + 3 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + Watchdog + Configure tamper policy for watchdog timer. + 4 + 7 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ExternalActiveShield + Configure tamper policy for external active shield. BICR is used to specify which channels (GPIOs) are enabled. + 12 + 15 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + InternalDetectors + Configure tamper policy for internal detectors including glitch detector, signal protector and CRACEN detector. See for more information. An automatic reset is issued upon detection. + 20 + 23 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + HardFault + Configure tamper policy for hard fault. + 24 + 27 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ApiFault + Configure tamper policy for invalid API usage. + 28 + 31 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + RESPONSE1 + Unspecified + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + AdacFault + Configure tamper policy for invalid ADAC usage. + 0 + 3 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + StateFault + Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure domain before secure services are permitted again. + 4 + 7 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + TemperatureFault + Configure out-of-range on-die temperature tamper policy. A reset is required to continue providing secure services once the on-temperature is within valid operating conditions again. This reset is automatically triggered by the secure domain. + 8 + 11 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + TEMPDETECTORCONFIG + Unspecified + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TemperatureDetectionStrategy + Configure when on-die temperature sensor should check the temperature. + 0 + 1 + + + Periodically + On-die temperature sensor is read periodically with selected interval. + 0x1 + + + OnServiceCallAndPeriodically + On-die temperature sensor is read before each secure service call and periodically with selected interval. + 0x2 + + + OnServiceCallOnly + On-die temperature sensor is read before each secure service call. + 0x3 + + + + + TemperatureDetectionInterval + Configure interval for on-die temperature reading if periodic reading is enabled. + 2 + 3 + + + 1Minute + On-die temperature sensor is read with one minute intervals. + 0x0 + + + 15Minutes + On-die temperature sensor is read with 15 minutes intervals. + 0x2 + + + 1Hour + On-die temperature sensor is read with one hour intervals. + 0x3 + + + + + LowTemperatureThresholdShift + Low temperature detection threshold shift in degrees Celsius. The low temperature threshold is calculated by adding the threshold shift to the minimum operating temperature of the SoC. + 4 + 11 + + + HighTemperatureThresholdShift + High temperature detection threshold shift in degrees Celsius. The high temperature threshold is calculated by subtracting the threshold shift from the maximum operating temperature of the SoC. + 12 + 19 + + + + + + COUNTERMEASURES + Configuration of countermeasures. + UICR_TAMPER_COUNTERMEASURES + read-write + 0x010 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + DPAAES + Configure Differential Power Analysis countermeasure for CRACEN AES. + 0 + 0 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + DPAPK + Configure Differential Power Analysis countermeasure for CRACEN PK. + 1 + 1 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + ClockDithering + Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on TRNG. + 9 + 9 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + + + INITSVTOR Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. @@ -13197,7 +13851,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x004 POWER0 - Power configuration for P0 to P7 IO ports. + Power configuration for P0 to P7 IO ports. Note: P0 is not included in the fields of this register because it is always internally supplied and therefore considered 'Shorted'. 0x000 read-write 0xFFFFFFFF @@ -13545,6 +14199,11 @@ POSSIBILITY OF SUCH DAMAGE. LFXO in external square wave mode. 0x3 + + Disabled + LFXO is not to be used. + 0x6 + @@ -13685,11 +14344,6 @@ POSSIBILITY OF SUCH DAMAGE. HFXO in external square wave mode. 0x3 - - Auto - Either Pierce or PIXO automatically handled by the system based on system requests. - 0x6 - @@ -67839,7 +68493,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x040 GPIOTE[%s] Unspecified - GPIOTE + FEATURE_STRUCT0_GPIOTE read-write 0x100 @@ -77218,7 +77872,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: AX2X bridge waitstates for the domain [n], where n is the Domain ID. 0x500 read-write - 0x00000007 + 0x00000000 0x20 @@ -80952,29 +81606,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - CROSSDOMAIN - Reset due to cross domain reset source. - 4 - 4 - - - NotDetected - Not detected - 0x0 - - - Detected - Detected - 0x1 - - - UNRETAINEDWAKE Reset due to wake from unretained state. - 5 - 5 + 4 + 4 @@ -146679,6 +147315,42 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -170882,7 +171554,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0x004 write-only 0x00000000 @@ -170890,7 +171562,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0 0 @@ -173300,13 +173972,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -173340,7 +174012,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -173400,10 +174072,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x2 - Gain4 + Gain3 4 0x3 + + Gain1_2 + 1/2 + 0x4 + @@ -173703,6 +174380,44 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + NOISESHAPE + Enable noise shaping + 0x654 + read-write + 0x00000000 + 0x20 + + + NOISESHAPE + Enable noise shaping + 0 + 1 + + + Disable + Disable noiseshaping. Oversampling based on accumulate and average. + 0x0 + + + Audio + Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x the oversampling ratio. See design description for more information + 0x1 + + + Accuracy + Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bits. Provides a 10kS/s cut off frequency, 32x the oversampling ratio. See design description for more information + 0x2 + + + Stage1 + Result from common 1st stage filter. For debugging only + 0x3 + + + + + @@ -185225,7 +185940,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PSEL Unspecified - PSEL + QDEC_PSEL read-write 0x51C diff --git a/mdk/nrf54h20_application_peripherals.h b/mdk/nrf54h20_application_peripherals.h index b333dcfb0..7e71df63c 100644 --- a/mdk/nrf54h20_application_peripherals.h +++ b/mdk/nrf54h20_application_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*Extended UICR.*/ #define UICREXTENDED_PRESENT 1 #define UICREXTENDED_COUNT 1 @@ -73,6 +72,7 @@ POSSIBILITY OF SUCH DAMAGE. #define BICR_PRESENT 1 #define BICR_COUNT 1 +#define BICR_P0_INTERNAL 1 /*!< (unspecified) */ #define BICR_P0_POWER 0 /*!< (unspecified) */ #define BICR_P1_POWER 1 /*!< (unspecified) */ #define BICR_P2_POWER 1 /*!< (unspecified) */ @@ -121,6 +121,22 @@ POSSIBILITY OF SUCH DAMAGE. #define BICR_P13_DRIVECTRL 0 /*!< (unspecified) */ #define BICR_P14_DRIVECTRL 0 /*!< (unspecified) */ #define BICR_P15_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P0_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P1_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P2_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P3_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P4_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P5_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P6_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P7_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P8_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P9_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P10_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P11_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P12_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P13_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P14_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P15_BIASCTRL 0 /*!< (unspecified) */ #define BICR_PMICLDO 0 /*!< (unspecified) */ /*CACHEDATA*/ @@ -335,6 +351,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RESETINFO_COUNT 1 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ +#define RESETINFO_CROSSDOMAINRESET 0 /*!< (unspecified) */ /*IPCT APB registers*/ #define IPCT_PRESENT 1 @@ -1403,7 +1420,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ -/* =============================================== APPLICATION_SPU010_FEATURES =============================================== */ +/* ============================================= SPU010 Split Security Features ============================================== */ /** * @brief Indexes in SPU010.FEATURES controlling access permissions of features with split security */ diff --git a/mdk/nrf54h20_enga_application.h b/mdk/nrf54h20_enga_application.h index f4960deef..67a223e4c 100644 --- a/mdk/nrf54h20_enga_application.h +++ b/mdk/nrf54h20_enga_application.h @@ -243,6 +243,15 @@ typedef enum { #endif /*!< NRF_APPLICATION */ +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_APPLICATION + #define NRF_PROCESSOR NRF_PROCESSOR_APPLICATION + #define NRF_OWNER NRF_OWNER_APPLICATION + +#endif /*!< NRF_APPLICATION */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_enga_application.svd b/mdk/nrf54h20_enga_application.svd index 07481505f..35991b643 100644 --- a/mdk/nrf54h20_enga_application.svd +++ b/mdk/nrf54h20_enga_application.svd @@ -6,7 +6,7 @@ nrf54h20_enga_application nRF54h 1 - LiliumSOC1 reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + nRF54H20_EngA reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. @@ -52306,7 +52306,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x2000000 DOMAIN[%s] Unspecified - DOMAIN + STMDATA_DOMAIN read-write 0x000 @@ -99741,9 +99741,9 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - STRUCT1 + STRUCT0 Unspecified - STRUCT1 + STRUCT0 EXTCONF1 read-write 0x400 diff --git a/mdk/nrf54h20_enga_application_peripherals.h b/mdk/nrf54h20_enga_application_peripherals.h index d0d913272..0feacce7a 100644 --- a/mdk/nrf54h20_enga_application_peripherals.h +++ b/mdk/nrf54h20_enga_application_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*User information configuration registers*/ #define UICR_PRESENT 1 #define UICR_COUNT 1 diff --git a/mdk/nrf54h20_enga_flpr.h b/mdk/nrf54h20_enga_flpr.h index 39dc60ca6..8341ff159 100644 --- a/mdk/nrf54h20_enga_flpr.h +++ b/mdk/nrf54h20_enga_flpr.h @@ -234,6 +234,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 0.7 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 0 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 7 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -242,12 +245,24 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR121 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54h20_enga_flpr System Library */ #endif /*!< NRF_FLPR */ +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST + #define NRF_PROCESSOR NRF_PROCESSOR_FLPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_FLPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_enga_flpr.svd b/mdk/nrf54h20_enga_flpr.svd index cb837ec4c..dc0413f4c 100644 --- a/mdk/nrf54h20_enga_flpr.svd +++ b/mdk/nrf54h20_enga_flpr.svd @@ -6,7 +6,7 @@ nrf54h20_enga_flpr nRF54h 1 - LiliumSOC1 reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + nRF54H20_EngA reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. @@ -38965,7 +38965,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x2000000 DOMAIN[%s] Unspecified - DOMAIN + STMDATA_DOMAIN read-write 0x000 @@ -55788,9 +55788,9 @@ A write outputs the value to atbytesm. - STRUCT1 + STRUCT0 Unspecified - STRUCT1 + STRUCT0 EXTCONF1 read-write 0x400 diff --git a/mdk/nrf54h20_enga_flpr_peripherals.h b/mdk/nrf54h20_enga_flpr_peripherals.h index 319e3a967..456056cae 100644 --- a/mdk/nrf54h20_enga_flpr_peripherals.h +++ b/mdk/nrf54h20_enga_flpr_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 diff --git a/mdk/nrf54h20_enga_interim.h b/mdk/nrf54h20_enga_interim.h index b47c21b3a..7d14d2389 100644 --- a/mdk/nrf54h20_enga_interim.h +++ b/mdk/nrf54h20_enga_interim.h @@ -391,7 +391,6 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER137_CC_NUM TIMER137_CC_NUM_SIZE #define DPPIC020_CH_NUM DPPIC020_CH_NUM_SIZE - #define DPPIC030_CH_NUM DPPIC030_CH_NUM_SIZE #define DPPIC120_CH_NUM DPPIC120_CH_NUM_SIZE #define DPPIC130_CH_NUM DPPIC130_CH_NUM_SIZE #define DPPIC131_CH_NUM DPPIC131_CH_NUM_SIZE @@ -402,7 +401,6 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC136_CH_NUM DPPIC136_CH_NUM_SIZE #define DPPIC020_GROUP_NUM DPPIC020_GROUP_NUM_SIZE - #define DPPIC030_GROUP_NUM DPPIC030_GROUP_NUM_SIZE #define DPPIC120_GROUP_NUM DPPIC120_GROUP_NUM_SIZE #define DPPIC130_GROUP_NUM DPPIC130_GROUP_NUM_SIZE #define DPPIC131_GROUP_NUM DPPIC131_GROUP_NUM_SIZE diff --git a/mdk/nrf54h20_enga_peripherals.h b/mdk/nrf54h20_enga_peripherals.h index 561939131..81f93f25a 100644 --- a/mdk/nrf54h20_enga_peripherals.h +++ b/mdk/nrf54h20_enga_peripherals.h @@ -39,8 +39,6 @@ POSSIBILITY OF SUCH DAMAGE. extern "C" { #endif - - #if defined(NRF_APPLICATION) #include "nrf54h20_enga_application_peripherals.h" #elif defined(NRF_FLPR) diff --git a/mdk/nrf54h20_enga_ppr.h b/mdk/nrf54h20_enga_ppr.h index 4e5d81f8e..f5ff6fcbe 100644 --- a/mdk/nrf54h20_enga_ppr.h +++ b/mdk/nrf54h20_enga_ppr.h @@ -218,6 +218,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 0.7 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 0 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 7 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -226,12 +229,24 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR130 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54h20_enga_ppr System Library */ #endif /*!< NRF_PPR */ +#ifdef NRF_PPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALSLOW + #define NRF_PROCESSOR NRF_PROCESSOR_PPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_PPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_enga_ppr.svd b/mdk/nrf54h20_enga_ppr.svd index 0dbdc30f8..7edeabc89 100644 --- a/mdk/nrf54h20_enga_ppr.svd +++ b/mdk/nrf54h20_enga_ppr.svd @@ -6,7 +6,7 @@ nrf54h20_enga_ppr nRF54h 1 - LiliumSOC1 reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + nRF54H20_EngA reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. @@ -38965,7 +38965,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x2000000 DOMAIN[%s] Unspecified - DOMAIN + STMDATA_DOMAIN read-write 0x000 @@ -55660,9 +55660,9 @@ A write outputs the value to atbytesm. - STRUCT1 + STRUCT0 Unspecified - STRUCT1 + STRUCT0 EXTCONF1 read-write 0x400 diff --git a/mdk/nrf54h20_enga_ppr_peripherals.h b/mdk/nrf54h20_enga_ppr_peripherals.h index b72a773fd..4a6157cd9 100644 --- a/mdk/nrf54h20_enga_ppr_peripherals.h +++ b/mdk/nrf54h20_enga_ppr_peripherals.h @@ -40,8 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 diff --git a/mdk/nrf54h20_enga_radiocore.h b/mdk/nrf54h20_enga_radiocore.h index 4f22d8be1..1dd6eca17 100644 --- a/mdk/nrf54h20_enga_radiocore.h +++ b/mdk/nrf54h20_enga_radiocore.h @@ -265,6 +265,15 @@ typedef enum { #endif /*!< NRF_RADIOCORE */ +#ifdef NRF_RADIOCORE + + #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE + #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE + #define NRF_OWNER NRF_OWNER_RADIOCORE + +#endif /*!< NRF_RADIOCORE */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_enga_radiocore.svd b/mdk/nrf54h20_enga_radiocore.svd index 7714b7a97..f62f2f907 100644 --- a/mdk/nrf54h20_enga_radiocore.svd +++ b/mdk/nrf54h20_enga_radiocore.svd @@ -6,7 +6,7 @@ nrf54h20_enga_radiocore nRF54h 1 - LiliumSOC1 reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + nRF54H20_EngA reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. @@ -51336,7 +51336,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x2000000 DOMAIN[%s] Unspecified - DOMAIN + STMDATA_DOMAIN read-write 0x000 @@ -89643,14 +89643,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -90282,14 +90274,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -90921,14 +90905,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -91560,14 +91536,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -121400,9 +121368,9 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - STRUCT1 + STRUCT0 Unspecified - STRUCT1 + STRUCT0 EXTCONF1 read-write 0x400 diff --git a/mdk/nrf54h20_enga_radiocore_peripherals.h b/mdk/nrf54h20_enga_radiocore_peripherals.h index 1293938ca..d1d185b7b 100644 --- a/mdk/nrf54h20_enga_radiocore_peripherals.h +++ b/mdk/nrf54h20_enga_radiocore_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*User information configuration registers*/ #define UICR_PRESENT 1 #define UICR_COUNT 1 diff --git a/mdk/nrf54h20_enga_types.h b/mdk/nrf54h20_enga_types.h index 417a5ca91..d39b2d254 100644 --- a/mdk/nrf54h20_enga_types.h +++ b/mdk/nrf54h20_enga_types.h @@ -70,6 +70,40 @@ POSSIBILITY OF SUCH DAMAGE. #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ #endif +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_APPLICATION = 2, /*!< Application Core */ + NRF_DOMAIN_RADIOCORE = 3, /*!< Radio Core */ + NRF_DOMAIN_GLOBALFAST = 12, /*!< Global Domain - Fast clock domain */ + NRF_DOMAIN_GLOBALSLOW = 13, /*!< Global Domain - Slow clock domain */ + NRF_DOMAIN_GLOBAL = 15, /*!< Global Domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_APPLICATION = 2, /*!< Application Core Processor */ + NRF_PROCESSOR_RADIOCORE = 3, /*!< Radio Core Processor */ + NRF_PROCESSOR_PPR = 13, /*!< Peripheral Processor */ + NRF_PROCESSOR_FLPR = 14, /*!< Fast Lightweight Processor */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_GLOBAL = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 2, /*!< Application Core */ + NRF_OWNER_RADIOCORE = 3, /*!< Radio Core */ +} NRF_OWNERID_Type; + /* ========================================= Start of section using anonymous unions ========================================= */ @@ -13079,16 +13113,7 @@ typedef struct { __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ __IM uint32_t RESERVED7[2]; - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM uint32_t CONFIGVOLTLVL; /*!< (@ 0x00000518) Configure voltage level for analog input */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t CONFIGVOLTLVL; /*!< (@ 0x00000518) Configure voltage level for analog input */ __IM uint32_t RESERVED8[5]; __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ @@ -22984,21 +23009,8 @@ typedef struct { * @brief PORTCNF [GPIO_PORTCNF] (unspecified) */ typedef struct { - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - struct { - __IOM uint32_t DRIVECTRL; /*!< (@ 0x00000000) Drive control for impedance matching of the pins in + __IOM uint32_t DRIVECTRL; /*!< (@ 0x00000000) Drive control for impedance matching of the pins in this port*/ - }; - struct { - }; - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif } NRF_GPIO_PORTCNF_Type; /*!< Size = 4 (0x004) */ /* GPIO_PORTCNF_DRIVECTRL: Drive control for impedance matching of the pins in this port */ @@ -65294,51 +65306,49 @@ typedef struct { __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ __IM uint32_t RESERVED6[33]; __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ - __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ + __IM uint32_t RESERVED7; __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ - __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ - __IM uint32_t RESERVED7[4]; + __IM uint32_t RESERVED8[5]; __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ - __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ + __IM uint32_t RESERVED9; __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ - __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ - __IM uint32_t RESERVED8[18]; + __IM uint32_t RESERVED10[19]; __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ - __IM uint32_t RESERVED9[7]; + __IM uint32_t RESERVED11[7]; __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ - __IM uint32_t RESERVED10[3]; + __IM uint32_t RESERVED12[3]; __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED11; + __IM uint32_t RESERVED13; __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000540) Data whitening initial value */ - __IM uint32_t RESERVED12[112]; + __IM uint32_t RESERVED14[112]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED15; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED14[377]; + __IM uint32_t RESERVED16[377]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED15[2]; + __IM uint32_t RESERVED17[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED16[4]; + __IM uint32_t RESERVED18[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED17[43]; + __IM uint32_t RESERVED19[43]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED18; + __IM uint32_t RESERVED20; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -65353,14 +65363,14 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED19[3]; + __IM uint32_t RESERVED21[3]; __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ - __IM uint32_t RESERVED20[3]; + __IM uint32_t RESERVED22[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED21[3]; + __IM uint32_t RESERVED23[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 3796 (0xED4) */ @@ -74020,16 +74030,7 @@ typedef struct { * @brief System Trace Macrocell data buffer */ typedef struct { /*!< STMDATA Structure */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_STMDATA_DOMAIN_Type DOMAIN[16]; /*!< (@ 0x00000000) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_STMDATA_DOMAIN_Type DOMAIN[16]; /*!< (@ 0x00000000) (unspecified) */ } NRF_STMDATA_Type; /*!< Size = 536870912 (0x20000000) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ diff --git a/mdk/nrf54h20_enga_version.h b/mdk/nrf54h20_enga_version.h index 5cccba968..8c5f4c751 100644 --- a/mdk/nrf54h20_enga_version.h +++ b/mdk/nrf54h20_enga_version.h @@ -42,9 +42,8 @@ POSSIBILITY OF SUCH DAMAGE. #define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of product specification. */ #define MDK_SOURCE_VERSION_MINOR 2 /*!< Minor version of product specification. */ -#define MDK_SOURCE_VERSION_MICRO 25 /*!< Micro version of product specification. */ +#define MDK_SOURCE_VERSION_MICRO 26 /*!< Micro version of product specification. */ -#define MDK_SOURCE_HASH Lilium_SOC1_IPS_v0.2.24-6-gf9b2e05c /*!< Git hash of product specification source. */ #ifdef __cplusplus diff --git a/mdk/nrf54h20_flpr.h b/mdk/nrf54h20_flpr.h index a330f75ae..9ba63ba86 100644 --- a/mdk/nrf54h20_flpr.h +++ b/mdk/nrf54h20_flpr.h @@ -238,6 +238,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 1.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -246,12 +249,24 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR121 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54h20_flpr System Library */ #endif /*!< NRF_FLPR */ +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST + #define NRF_PROCESSOR NRF_PROCESSOR_FLPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_FLPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" @@ -296,11 +311,7 @@ typedef enum { /* =========================================================================================================================== */ #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ - #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ - #define NRF_VPRCLIC NRF_FLPR_VPRCLIC - #else /*!< Remap all instances. */ - #define NRF_VPRCLIC NRF_FLPR_VPRCLIC - #endif /*!< NRF_TRUSTZONE_NONSECURE */ + #define NRF_VPRCLIC NRF_FLPR_VPRCLIC #endif /*!< NRF_FLPR */ /* ========================================== End of section using anonymous unions ========================================== */ diff --git a/mdk/nrf54h20_flpr.svd b/mdk/nrf54h20_flpr.svd index 90d2e6ccc..c0b07c5e9 100644 --- a/mdk/nrf54h20_flpr.svd +++ b/mdk/nrf54h20_flpr.svd @@ -99421,6 +99421,42 @@ A write outputs the value to atbytesm. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -124481,7 +124517,7 @@ A write outputs the value to atbytesm. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0x004 write-only 0x00000000 @@ -124489,7 +124525,7 @@ A write outputs the value to atbytesm. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0 0 @@ -126899,13 +126935,13 @@ A write outputs the value to atbytesm. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -126939,7 +126975,7 @@ A write outputs the value to atbytesm. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -126999,10 +127035,15 @@ A write outputs the value to atbytesm. 0x2 - Gain4 + Gain3 4 0x3 + + Gain1_2 + 1/2 + 0x4 + @@ -127302,6 +127343,44 @@ A write outputs the value to atbytesm. + + NOISESHAPE + Enable noise shaping + 0x654 + read-write + 0x00000000 + 0x20 + + + NOISESHAPE + Enable noise shaping + 0 + 1 + + + Disable + Disable noiseshaping. Oversampling based on accumulate and average. + 0x0 + + + Audio + Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x the oversampling ratio. See design description for more information + 0x1 + + + Accuracy + Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bits. Provides a 10kS/s cut off frequency, 32x the oversampling ratio. See design description for more information + 0x2 + + + Stage1 + Result from common 1st stage filter. For debugging only + 0x3 + + + + + @@ -138733,7 +138812,7 @@ A write outputs the value to atbytesm. PSEL Unspecified - PSEL + QDEC_PSEL read-write 0x51C diff --git a/mdk/nrf54h20_flpr_peripherals.h b/mdk/nrf54h20_flpr_peripherals.h index ab4b6e15e..d172361bd 100644 --- a/mdk/nrf54h20_flpr_peripherals.h +++ b/mdk/nrf54h20_flpr_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 diff --git a/mdk/nrf54h20_global.h b/mdk/nrf54h20_global.h index 3fcc5bbe8..1f68469ad 100644 --- a/mdk/nrf54h20_global.h +++ b/mdk/nrf54h20_global.h @@ -106,6 +106,8 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_EXMIF_S_BASE 0x5F095000UL #define NRF_SECDOMBELLBOARD_NS_BASE 0x4F099000UL #define NRF_SECDOMBELLBOARD_S_BASE 0x5F099000UL +#define NRF_CANPLL_NS_BASE 0x4F8C2000UL +#define NRF_CANPLL_S_BASE 0x5F8C2000UL #define NRF_VPR120_NS_BASE 0x4F8C8000UL #define NRF_VPR120_S_BASE 0x5F8C8000UL #define NRF_IPCT120_NS_BASE 0x4F8D1000UL @@ -346,6 +348,8 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_EXMIF_S ((NRF_EXMIF_Type*) NRF_EXMIF_S_BASE) #define NRF_SECDOMBELLBOARD_NS ((NRF_BELLBOARDPUBLIC_Type*) NRF_SECDOMBELLBOARD_NS_BASE) #define NRF_SECDOMBELLBOARD_S ((NRF_BELLBOARDPUBLIC_Type*) NRF_SECDOMBELLBOARD_S_BASE) +#define NRF_CANPLL_NS ((NRF_AUXPLL_Type*) NRF_CANPLL_NS_BASE) +#define NRF_CANPLL_S ((NRF_AUXPLL_Type*) NRF_CANPLL_S_BASE) #define NRF_VPR120_NS ((NRF_VPRPUBLIC_Type*) NRF_VPR120_NS_BASE) #define NRF_VPR120_S ((NRF_VPRPUBLIC_Type*) NRF_VPR120_S_BASE) #define NRF_IPCT120_NS ((NRF_IPCT_Type*) NRF_IPCT120_NS_BASE) @@ -578,6 +582,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_USBHS NRF_USBHS_NS #define NRF_EXMIF NRF_EXMIF_NS #define NRF_SECDOMBELLBOARD NRF_SECDOMBELLBOARD_NS + #define NRF_CANPLL NRF_CANPLL_NS #define NRF_VPR120 NRF_VPR120_NS #define NRF_IPCT120 NRF_IPCT120_NS #define NRF_MUTEX120 NRF_MUTEX120_NS @@ -706,6 +711,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NRF_USBHS NRF_USBHS_S #define NRF_EXMIF NRF_EXMIF_S #define NRF_SECDOMBELLBOARD NRF_SECDOMBELLBOARD_S + #define NRF_CANPLL NRF_CANPLL_S #define NRF_VPR120 NRF_VPR120_S #define NRF_IPCT120 NRF_IPCT120_S #define NRF_MUTEX120 NRF_MUTEX120_NS diff --git a/mdk/nrf54h20_interim.h b/mdk/nrf54h20_interim.h index ed4e89868..b75c13115 100644 --- a/mdk/nrf54h20_interim.h +++ b/mdk/nrf54h20_interim.h @@ -117,7 +117,6 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER137_CC_NUM TIMER137_CC_NUM_SIZE #define DPPIC020_CH_NUM DPPIC020_CH_NUM_SIZE - #define DPPIC030_CH_NUM DPPIC030_CH_NUM_SIZE #define DPPIC120_CH_NUM DPPIC120_CH_NUM_SIZE #define DPPIC130_CH_NUM DPPIC130_CH_NUM_SIZE #define DPPIC131_CH_NUM DPPIC131_CH_NUM_SIZE @@ -128,7 +127,6 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC136_CH_NUM DPPIC136_CH_NUM_SIZE #define DPPIC020_GROUP_NUM DPPIC020_GROUP_NUM_SIZE - #define DPPIC030_GROUP_NUM DPPIC030_GROUP_NUM_SIZE #define DPPIC120_GROUP_NUM DPPIC120_GROUP_NUM_SIZE #define DPPIC130_GROUP_NUM DPPIC130_GROUP_NUM_SIZE #define DPPIC131_GROUP_NUM DPPIC131_GROUP_NUM_SIZE diff --git a/mdk/nrf54h20_name_change.h b/mdk/nrf54h20_name_change.h index fd8920bfa..2da3891fc 100644 --- a/mdk/nrf54h20_name_change.h +++ b/mdk/nrf54h20_name_change.h @@ -73,6 +73,8 @@ POSSIBILITY OF SUCH DAMAGE. #define BICR_P14_3V BICR_P14_POWER_3V #define BICR_P15_3V BICR_P15_POWER_3V +#define SAADC_CH_CONFIG_GAIN_Gain4 SAADC_CH_CONFIG_GAIN_Gain3 + #ifdef __cplusplus } diff --git a/mdk/nrf54h20_peripherals.h b/mdk/nrf54h20_peripherals.h index 5fd811b18..0e1e1b018 100644 --- a/mdk/nrf54h20_peripherals.h +++ b/mdk/nrf54h20_peripherals.h @@ -39,8 +39,6 @@ POSSIBILITY OF SUCH DAMAGE. extern "C" { #endif - - #if defined(NRF_APPLICATION) #include "nrf54h20_application_peripherals.h" #elif defined(NRF_FLPR) diff --git a/mdk/nrf54h20_ppr.h b/mdk/nrf54h20_ppr.h index 149a2795c..d1234d249 100644 --- a/mdk/nrf54h20_ppr.h +++ b/mdk/nrf54h20_ppr.h @@ -222,6 +222,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 1.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -230,12 +233,24 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR130 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54h20_ppr System Library */ #endif /*!< NRF_PPR */ +#ifdef NRF_PPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALSLOW + #define NRF_PROCESSOR NRF_PROCESSOR_PPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_PPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" @@ -280,11 +295,7 @@ typedef enum { /* =========================================================================================================================== */ #ifdef NRF_PPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ - #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ - #define NRF_VPRCLIC NRF_PPR_VPRCLIC - #else /*!< Remap all instances. */ - #define NRF_VPRCLIC NRF_PPR_VPRCLIC - #endif /*!< NRF_TRUSTZONE_NONSECURE */ + #define NRF_VPRCLIC NRF_PPR_VPRCLIC #endif /*!< NRF_PPR */ /* ========================================== End of section using anonymous unions ========================================== */ diff --git a/mdk/nrf54h20_ppr.svd b/mdk/nrf54h20_ppr.svd index b586f4b1d..8a3880b48 100644 --- a/mdk/nrf54h20_ppr.svd +++ b/mdk/nrf54h20_ppr.svd @@ -99357,6 +99357,42 @@ A write outputs the value to atbytesm. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -124417,7 +124453,7 @@ A write outputs the value to atbytesm. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0x004 write-only 0x00000000 @@ -124425,7 +124461,7 @@ A write outputs the value to atbytesm. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0 0 @@ -126835,13 +126871,13 @@ A write outputs the value to atbytesm. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -126875,7 +126911,7 @@ A write outputs the value to atbytesm. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -126935,10 +126971,15 @@ A write outputs the value to atbytesm. 0x2 - Gain4 + Gain3 4 0x3 + + Gain1_2 + 1/2 + 0x4 + @@ -127238,6 +127279,44 @@ A write outputs the value to atbytesm. + + NOISESHAPE + Enable noise shaping + 0x654 + read-write + 0x00000000 + 0x20 + + + NOISESHAPE + Enable noise shaping + 0 + 1 + + + Disable + Disable noiseshaping. Oversampling based on accumulate and average. + 0x0 + + + Audio + Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x the oversampling ratio. See design description for more information + 0x1 + + + Accuracy + Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bits. Provides a 10kS/s cut off frequency, 32x the oversampling ratio. See design description for more information + 0x2 + + + Stage1 + Result from common 1st stage filter. For debugging only + 0x3 + + + + + @@ -138669,7 +138748,7 @@ A write outputs the value to atbytesm. PSEL Unspecified - PSEL + QDEC_PSEL read-write 0x51C diff --git a/mdk/nrf54h20_ppr_peripherals.h b/mdk/nrf54h20_ppr_peripherals.h index 9b504b17c..20f8968d4 100644 --- a/mdk/nrf54h20_ppr_peripherals.h +++ b/mdk/nrf54h20_ppr_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 diff --git a/mdk/nrf54h20_radiocore.h b/mdk/nrf54h20_radiocore.h index 63e6da9b9..682ce8a1e 100644 --- a/mdk/nrf54h20_radiocore.h +++ b/mdk/nrf54h20_radiocore.h @@ -279,6 +279,15 @@ typedef enum { #endif /*!< NRF_RADIOCORE */ +#ifdef NRF_RADIOCORE + + #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE + #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE + #define NRF_OWNER NRF_OWNER_RADIOCORE + +#endif /*!< NRF_RADIOCORE */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54h20_radiocore.svd b/mdk/nrf54h20_radiocore.svd index 6a58fcf86..dd7dc4793 100644 --- a/mdk/nrf54h20_radiocore.svd +++ b/mdk/nrf54h20_radiocore.svd @@ -12363,6 +12363,660 @@ POSSIBILITY OF SUCH DAMAGE. + + TAMPER + Unspecified + UICR_TAMPER + read-write + 0x760 + + DETECTION + Tamper policy configuration for detected security events. + UICR_TAMPER_DETECTION + read-write + 0x000 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + GlobalEnable + Enable tamper detection. When disabled all tamper enable and policy switches are ignored. + 0 + 0 + + + Enable + Enable tamper detection. + 0x0 + + + Disable + Disable tamper detection. + 0x1 + + + + + VoltageLevel + Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when voltage on the corresponding supply line is too low. + 1 + 1 + + + Enable + Enable voltage level detectors. + 0x0 + + + Disable + Disable voltage level detectors. + 0x1 + + + + + ExternalActiveShield + Enable external active shield detector. + 4 + 4 + + + Enable + Enable external active shield detector. + 0x0 + + + Disable + Disable external active shield detector. + 0x1 + + + + + HardFault + Configure if tamper prevention should react on hard faults. + 7 + 7 + + + Enable + Enable hard fault detector. + 0x0 + + + Disable + Disable hard fault detector. + 0x1 + + + + + ApiFault + Configure if tamper prevention should react on invalid API usage. + 8 + 8 + + + Enable + Enable API fault detector. + 0x0 + + + Disable + Disable API fault detector. + 0x1 + + + + + AdacFault + Configure if tamper prevention should react on invalid ADAC usage. + 9 + 9 + + + Enable + Enable invalid ADAC usage detector. + 0x0 + + + Disable + Disable invalid ADAC usage detector. + 0x1 + + + + + StateFault + Configure if tamper prevention should react on invalid firmware execution state. + 10 + 10 + + + Enable + Enable invalid firmware execution state detector. + 0x0 + + + Disable + Disable invalid firmware execution state detector. + 0x1 + + + + + TemperatureFault + Configure if tamper prevention should react when on-die temperature exceeds a valid range. + 11 + 11 + + + Enable + Enable invalid out-of-range temperature detector. + 0x0 + + + Disable + Disable invalid out-of-range temperature detector. + 0x1 + + + + + + + RESPONSE0 + Unspecified + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + VoltageLevel + Configure tamper policy for invalid voltage level on supply lines. + 0 + 3 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + Watchdog + Configure tamper policy for watchdog timer. + 4 + 7 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ExternalActiveShield + Configure tamper policy for external active shield. BICR is used to specify which channels (GPIOs) are enabled. + 12 + 15 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + InternalDetectors + Configure tamper policy for internal detectors including glitch detector, signal protector and CRACEN detector. See for more information. An automatic reset is issued upon detection. + 20 + 23 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + HardFault + Configure tamper policy for hard fault. + 24 + 27 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ApiFault + Configure tamper policy for invalid API usage. + 28 + 31 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + RESPONSE1 + Unspecified + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + AdacFault + Configure tamper policy for invalid ADAC usage. + 0 + 3 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + StateFault + Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure domain before secure services are permitted again. + 4 + 7 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + TemperatureFault + Configure out-of-range on-die temperature tamper policy. A reset is required to continue providing secure services once the on-temperature is within valid operating conditions again. This reset is automatically triggered by the secure domain. + 8 + 11 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + TEMPDETECTORCONFIG + Unspecified + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TemperatureDetectionStrategy + Configure when on-die temperature sensor should check the temperature. + 0 + 1 + + + Periodically + On-die temperature sensor is read periodically with selected interval. + 0x1 + + + OnServiceCallAndPeriodically + On-die temperature sensor is read before each secure service call and periodically with selected interval. + 0x2 + + + OnServiceCallOnly + On-die temperature sensor is read before each secure service call. + 0x3 + + + + + TemperatureDetectionInterval + Configure interval for on-die temperature reading if periodic reading is enabled. + 2 + 3 + + + 1Minute + On-die temperature sensor is read with one minute intervals. + 0x0 + + + 15Minutes + On-die temperature sensor is read with 15 minutes intervals. + 0x2 + + + 1Hour + On-die temperature sensor is read with one hour intervals. + 0x3 + + + + + LowTemperatureThresholdShift + Low temperature detection threshold shift in degrees Celsius. The low temperature threshold is calculated by adding the threshold shift to the minimum operating temperature of the SoC. + 4 + 11 + + + HighTemperatureThresholdShift + High temperature detection threshold shift in degrees Celsius. The high temperature threshold is calculated by subtracting the threshold shift from the maximum operating temperature of the SoC. + 12 + 19 + + + + + + COUNTERMEASURES + Configuration of countermeasures. + UICR_TAMPER_COUNTERMEASURES + read-write + 0x010 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + DPAAES + Configure Differential Power Analysis countermeasure for CRACEN AES. + 0 + 0 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + DPAPK + Configure Differential Power Analysis countermeasure for CRACEN PK. + 1 + 1 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + ClockDithering + Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on TRNG. + 9 + 9 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + + + INITSVTOR Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. @@ -66397,7 +67051,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x040 GPIOTE[%s] Unspecified - GPIOTE + FEATURE_STRUCT0_GPIOTE read-write 0x100 @@ -75776,7 +76430,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: AX2X bridge waitstates for the domain [n], where n is the Domain ID. 0x500 read-write - 0x00000007 + 0x00000000 0x20 @@ -79352,29 +80006,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - CROSSDOMAIN - Reset due to cross domain reset source. - 4 - 4 - - - NotDetected - Not detected - 0x0 - - - Detected - Detected - 0x1 - - - UNRETAINEDWAKE Reset due to wake from unretained state. - 5 - 5 + 4 + 4 @@ -98296,14 +98932,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -98935,14 +99563,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -99574,14 +100194,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -100213,14 +100825,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -108167,7 +108771,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. EVENTS_END - Encrypt/decrypt complete + Encrypt/decrypt complete or ended because of an error 0x104 read-write 0x00000000 @@ -108175,7 +108779,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. EVENTS_END - Encrypt/decrypt complete + Encrypt/decrypt complete or ended because of an error 0 0 @@ -167615,6 +168219,42 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -190187,7 +190827,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0x004 write-only 0x00000000 @@ -190195,7 +190835,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. 0 0 @@ -192605,13 +193245,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -192645,7 +193285,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -192705,10 +193345,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x2 - Gain4 + Gain3 4 0x3 + + Gain1_2 + 1/2 + 0x4 + @@ -193008,6 +193653,44 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + NOISESHAPE + Enable noise shaping + 0x654 + read-write + 0x00000000 + 0x20 + + + NOISESHAPE + Enable noise shaping + 0 + 1 + + + Disable + Disable noiseshaping. Oversampling based on accumulate and average. + 0x0 + + + Audio + Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut off frequency, 8x the oversampling ratio. See design description for more information + 0x1 + + + Accuracy + Noiseshaping and decimating. Smaller passband. Recommended resolution setting is 14 bits. Provides a 10kS/s cut off frequency, 32x the oversampling ratio. See design description for more information + 0x2 + + + Stage1 + Result from common 1st stage filter. For debugging only + 0x3 + + + + + @@ -204530,7 +205213,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PSEL Unspecified - PSEL + QDEC_PSEL read-write 0x51C diff --git a/mdk/nrf54h20_radiocore_peripherals.h b/mdk/nrf54h20_radiocore_peripherals.h index ecc6a6b0a..30b51add3 100644 --- a/mdk/nrf54h20_radiocore_peripherals.h +++ b/mdk/nrf54h20_radiocore_peripherals.h @@ -40,7 +40,6 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include - /*CACHEDATA*/ #define ICACHEDATA_PRESENT 1 #define ICACHEDATA_COUNT 1 @@ -327,6 +326,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RESETINFO_COUNT 1 #define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ +#define RESETINFO_CROSSDOMAINRESET 0 /*!< (unspecified) */ /*Distributed programmable peripheral interconnect controller*/ #define DPPIC_PRESENT 1 @@ -1516,7 +1516,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS137_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ -/* ================================================ RADIOCORE_SPU020_FEATURES ================================================ */ +/* ============================================= SPU020 Split Security Features ============================================== */ /** * @brief Indexes in SPU020.FEATURES controlling access permissions of features with split security */ @@ -1569,7 +1569,7 @@ typedef enum { NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_3 = 67, /*!< Index of access permissions for channel group 3 of DPPIC020 */ } NRF_RADIOCORE_SPU020_FEATURES_ENUM_t; -/* ================================================ RADIOCORE_SPU030_FEATURES ================================================ */ +/* ============================================= SPU030 Split Security Features ============================================== */ /** * @brief Indexes in SPU030.FEATURES controlling access permissions of features with split security */ diff --git a/mdk/nrf54h20_types.h b/mdk/nrf54h20_types.h index 78be8dac9..b1cd4d360 100644 --- a/mdk/nrf54h20_types.h +++ b/mdk/nrf54h20_types.h @@ -70,6 +70,40 @@ POSSIBILITY OF SUCH DAMAGE. #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ #endif +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_APPLICATION = 2, /*!< Application Core */ + NRF_DOMAIN_RADIOCORE = 3, /*!< Radio Core */ + NRF_DOMAIN_GLOBALFAST = 12, /*!< Global Domain - Fast clock domain */ + NRF_DOMAIN_GLOBALSLOW = 13, /*!< Global Domain - Slow clock domain */ + NRF_DOMAIN_GLOBAL = 15, /*!< Global Domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_APPLICATION = 2, /*!< Application Core Processor */ + NRF_PROCESSOR_RADIOCORE = 3, /*!< Radio Core Processor */ + NRF_PROCESSOR_PPR = 13, /*!< Peripheral Processor */ + NRF_PROCESSOR_FLPR = 14, /*!< Fast Lightweight Processor */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_GLOBAL = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 2, /*!< Application Core */ + NRF_OWNER_RADIOCORE = 3, /*!< Radio Core */ +} NRF_OWNERID_Type; + /* ========================================= Start of section using anonymous unions ========================================= */ @@ -1710,6 +1744,466 @@ typedef struct { to multiple targets.*/ +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ AUXPLL ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct AUXPLL_CONFIG =================================================== */ +/** + * @brief CONFIG [AUXPLL_CONFIG] (unspecified) + */ +typedef struct { + __IOM uint32_t CFGSTATIC; /*!< (@ 0x00000000) AUXPLL configuration */ +} NRF_AUXPLL_CONFIG_Type; /*!< Size = 4 (0x004) */ + +/* AUXPLL_CONFIG_CFGSTATIC: AUXPLL configuration */ + #define AUXPLL_CONFIG_CFGSTATIC_ResetValue (0x00000224UL) /*!< Reset value of CFGSTATIC register. */ + +/* OUTDRIVE @Bits 0..1 : Output buffer drive strength selection */ + #define AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Pos (0UL) /*!< Position of OUTDRIVE field. */ + #define AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Msk (0x3UL << AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Pos) /*!< Bit mask of OUTDRIVE field.*/ + #define AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Min (0x0UL) /*!< Lowest drive strength */ + #define AUXPLL_CONFIG_CFGSTATIC_OUTDRIVE_Max (0x3UL) /*!< Highest drive strength */ + +/* SELCONSTANTI @Bits 2..6 : Constant current tune for ring oscillator */ + #define AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Pos (2UL) /*!< Position of SELCONSTANTI field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Msk (0x1FUL << AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Pos) /*!< Bit mask of + SELCONSTANTI field.*/ + #define AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Min (0x00UL) /*!< Minimum current */ + #define AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Default (0x09UL) /*!< Default current for audio and USB */ + #define AUXPLL_CONFIG_CFGSTATIC_SELCONSTANTI_Max (0x0FUL) /*!< Maximum current */ + +/* SDMOFF @Bit 7 : Turn off sigma delta modulation */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Pos (7UL) /*!< Position of SDMOFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Msk (0x1UL << AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Pos) /*!< Bit mask of SDMOFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Min (0x0UL) /*!< Min enumerator value of SDMOFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_Max (0x1UL) /*!< Max enumerator value of SDMOFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_SDMOn (0x0UL) /*!< Sigma Delta Modulator enabled */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMOFF_SDMOff (0x1UL) /*!< Sigma Delta Modulator disabled */ + +/* SDMDITHEROFF @Bit 8 : Turn off dither in sigma delta modulator */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Pos (8UL) /*!< Position of SDMDITHEROFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Msk (0x1UL << AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Pos) /*!< Bit mask of + SDMDITHEROFF field.*/ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Min (0x0UL) /*!< Min enumerator value of SDMDITHEROFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_Max (0x1UL) /*!< Max enumerator value of SDMDITHEROFF field. */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_DitherOn (0x0UL) /*!< Dither enabled */ + #define AUXPLL_CONFIG_CFGSTATIC_SDMDITHEROFF_DitherOff (0x1UL) /*!< Dither disabled */ + +/* AUXPLLRANGE @Bits 9..10 : Loop divider base settings */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Pos (9UL) /*!< Position of AUXPLLRANGE field. */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Msk (0x3UL << AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Pos) /*!< Bit mask of + AUXPLLRANGE field.*/ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Min (0x0UL) /*!< Min enumerator value of AUXPLLRANGE field. */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Max (0x3UL) /*!< Max enumerator value of AUXPLLRANGE field. */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Low (0x0UL) /*!< Low range divider setting */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_Mid (0x1UL) /*!< Mid range divider setting */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_High (0x2UL) /*!< High range divider setting */ + #define AUXPLL_CONFIG_CFGSTATIC_AUXPLLRANGE_StaticHigh (0x3UL) /*!< Maximum static divider setting */ + + + +/* =================================================== Struct AUXPLL_TRIM ==================================================== */ +/** + * @brief TRIM [AUXPLL_TRIM] (unspecified) + */ +typedef struct { + __IOM uint32_t CTUNE; /*!< (@ 0x00000000) Ring oscillator core process corner tuning */ +} NRF_AUXPLL_TRIM_Type; /*!< Size = 4 (0x004) */ + +/* AUXPLL_TRIM_CTUNE: Ring oscillator core process corner tuning */ + #define AUXPLL_TRIM_CTUNE_ResetValue (0x0000000DUL) /*!< Reset value of CTUNE register. */ + +/* VAL @Bits 0..4 : Tuning value */ + #define AUXPLL_TRIM_CTUNE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define AUXPLL_TRIM_CTUNE_VAL_Msk (0x1FUL << AUXPLL_TRIM_CTUNE_VAL_Pos) /*!< Bit mask of VAL field. */ + #define AUXPLL_TRIM_CTUNE_VAL_Max (0x00UL) /*!< Highest frequency */ + #define AUXPLL_TRIM_CTUNE_VAL_Default (0x0DUL) /*!< Default center frequency for audio and USB */ + #define AUXPLL_TRIM_CTUNE_VAL_Min (0x1FUL) /*!< Lowest frequency */ + + + +/* ================================================ Struct AUXPLL_AUXPLLCTRL ================================================= */ +/** + * @brief AUXPLLCTRL [AUXPLL_AUXPLLCTRL] (unspecified) + */ +typedef struct { + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) AUXPLL frequency selection */ + __IOM uint32_t FREQINC; /*!< (@ 0x00000004) Frequency increment */ + __IOM uint32_t FREQINCPERIOD; /*!< (@ 0x00000008) Frequency increment period in 1 us steps */ + __IOM uint32_t OUTSEL; /*!< (@ 0x0000000C) AUXPLL output prescaler */ + __IOM uint32_t MODE; /*!< (@ 0x00000010) Freerunning mode control */ +} NRF_AUXPLL_AUXPLLCTRL_Type; /*!< Size = 20 (0x014) */ + +/* AUXPLL_AUXPLLCTRL_FREQUENCY: AUXPLL frequency selection */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_ResetValue (0x00008000UL) /*!< Reset value of FREQUENCY register. */ + +/* FREQUENCY @Bits 0..15 : Set fractional PLL divider ratio */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of + FREQUENCY field.*/ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Min (0x0UL) /*!< Min enumerator value of FREQUENCY field. */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Max (0xFFFFUL) /*!< Max enumerator value of FREQUENCY field. */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_MinimumDiv (0x0000UL) /*!< Division ratio of 4 */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Audio44k1 (0x3BCDUL) /*!< Division ratio for audio 44.1kHz frequency family */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_USB24M (0x8000UL) /*!< Division ratio for USB PHY 24MHz clock */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_Audio48k (0x9BA5UL) /*!< Division ratio for audio 48kHz frequency family */ + #define AUXPLL_AUXPLLCTRL_FREQUENCY_FREQUENCY_MaximumDiv (0xFFFFUL) /*!< Division ratio of 5 */ + + +/* AUXPLL_AUXPLLCTRL_FREQINC: Frequency increment */ + #define AUXPLL_AUXPLLCTRL_FREQINC_ResetValue (0x00000000UL) /*!< Reset value of FREQINC register. */ + +/* FREQINC @Bits 0..7 : Signed 8-bit frequency increment, applied to FREQUENCY */ + #define AUXPLL_AUXPLLCTRL_FREQINC_FREQINC_Pos (0UL) /*!< Position of FREQINC field. */ + #define AUXPLL_AUXPLLCTRL_FREQINC_FREQINC_Msk (0xFFUL << AUXPLL_AUXPLLCTRL_FREQINC_FREQINC_Pos) /*!< Bit mask of FREQINC + field.*/ + + +/* AUXPLL_AUXPLLCTRL_FREQINCPERIOD: Frequency increment period in 1 us steps */ + #define AUXPLL_AUXPLLCTRL_FREQINCPERIOD_ResetValue (0x00000000UL) /*!< Reset value of FREQINCPERIOD register. */ + +/* FREQINCPERIOD @Bits 0..15 : Frequency increment period */ + #define AUXPLL_AUXPLLCTRL_FREQINCPERIOD_FREQINCPERIOD_Pos (0UL) /*!< Position of FREQINCPERIOD field. */ + #define AUXPLL_AUXPLLCTRL_FREQINCPERIOD_FREQINCPERIOD_Msk (0xFFFFUL << AUXPLL_AUXPLLCTRL_FREQINCPERIOD_FREQINCPERIOD_Pos) /*!< + Bit mask of FREQINCPERIOD field.*/ + #define AUXPLL_AUXPLLCTRL_FREQINCPERIOD_FREQINCPERIOD_Min (0x0001UL) /*!< Min value of FREQINCPERIOD field. */ + #define AUXPLL_AUXPLLCTRL_FREQINCPERIOD_FREQINCPERIOD_Max (0xFFFFUL) /*!< Max size of FREQINCPERIOD field. */ + + +/* AUXPLL_AUXPLLCTRL_OUTSEL: AUXPLL output prescaler */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_ResetValue (0x00000007UL) /*!< Reset value of OUTSEL register. */ + +/* OUTSEL @Bits 0..3 : Prescaler ratio */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Pos (0UL) /*!< Position of OUTSEL field. */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Msk (0xFUL << AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Pos) /*!< Bit mask of OUTSEL field. */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Min (0x0UL) /*!< Min enumerator value of OUTSEL field. */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Max (0x8UL) /*!< Max enumerator value of OUTSEL field. */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_DivDisabled (0x0UL) /*!< Divider disabled. Bypassed external clock still supported */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div1 (0x1UL) /*!< Divide by 1 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div2 (0x2UL) /*!< Divide by 2 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div3 (0x3UL) /*!< Divide by 3 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div4 (0x4UL) /*!< Divide by 4 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div6 (0x5UL) /*!< Divide by 6 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div8 (0x6UL) /*!< Divide by 8 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div12 (0x7UL) /*!< Divide by 12 */ + #define AUXPLL_AUXPLLCTRL_OUTSEL_OUTSEL_Div16 (0x8UL) /*!< Divide by 16 */ + + +/* AUXPLL_AUXPLLCTRL_MODE: Freerunning mode control */ + #define AUXPLL_AUXPLLCTRL_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODECTRL @Bits 0..1 : Freerunning mode control */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Pos (0UL) /*!< Position of MODECTRL field. */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Msk (0x3UL << AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Pos) /*!< Bit mask of MODECTRL field. */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Min (0x0UL) /*!< Min enumerator value of MODECTRL field. */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Max (0x2UL) /*!< Max enumerator value of MODECTRL field. */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Auto (0x0UL) /*!< Automatically handled by the AUXPLL peripheral */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Freerun (0x1UL) /*!< Keep AUXPLL in freerunning mode */ + #define AUXPLL_AUXPLLCTRL_MODE_MODECTRL_Locked (0x2UL) /*!< Keep AUXPLL in locked mode */ + + + +/* ====================================================== Struct AUXPLL ====================================================== */ +/** + * @brief AUXPLL + */ + typedef struct { /*!< AUXPLL Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the AUXPLL */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the AUXPLL */ + __OM uint32_t TASKS_NEWFINEFREQ; /*!< (@ 0x00000008) Change fine frequency */ + __OM uint32_t TASKS_NEWBASEFREQ; /*!< (@ 0x0000000C) Change base frequency */ + __OM uint32_t TASKS_FREQINCSTART; /*!< (@ 0x00000010) Start automated frequency increment */ + __OM uint32_t TASKS_FREQINCSTOP; /*!< (@ 0x00000014) Stop automated frequency increment */ + __IM uint32_t RESERVED[58]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) AUXPLL started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) AUXPLL stopped */ + __IOM uint32_t EVENTS_LOCKED; /*!< (@ 0x00000108) AUXPLL locked */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status of AUXPLL */ + __IM uint32_t RESERVED3[3]; + __IOM NRF_AUXPLL_CONFIG_Type CONFIG; /*!< (@ 0x00000410) (unspecified) */ + __IM uint32_t RESERVED4[11]; + __IOM NRF_AUXPLL_TRIM_Type TRIM; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t RESERVED5[7]; + __IOM NRF_AUXPLL_AUXPLLCTRL_Type AUXPLLCTRL; /*!< (@ 0x00000460) (unspecified) */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t MIRROR; /*!< (@ 0x00000480) Enable LOCK for mirrored registers */ + } NRF_AUXPLL_Type; /*!< Size = 1156 (0x634) */ + +/* AUXPLL_TASKS_START: Start the AUXPLL */ + #define AUXPLL_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the AUXPLL */ + #define AUXPLL_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define AUXPLL_TASKS_START_TASKS_START_Msk (0x1UL << AUXPLL_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define AUXPLL_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define AUXPLL_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define AUXPLL_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_TASKS_STOP: Stop the AUXPLL */ + #define AUXPLL_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the AUXPLL */ + #define AUXPLL_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define AUXPLL_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AUXPLL_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define AUXPLL_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define AUXPLL_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define AUXPLL_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_TASKS_NEWFINEFREQ: Change fine frequency */ + #define AUXPLL_TASKS_NEWFINEFREQ_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEWFINEFREQ register. */ + +/* TASKS_NEWFINEFREQ @Bit 0 : Change fine frequency */ + #define AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Pos (0UL) /*!< Position of TASKS_NEWFINEFREQ field. */ + #define AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Msk (0x1UL << AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Pos) /*!< Bit mask + of TASKS_NEWFINEFREQ field.*/ + #define AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Min (0x1UL) /*!< Min enumerator value of TASKS_NEWFINEFREQ field. */ + #define AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Max (0x1UL) /*!< Max enumerator value of TASKS_NEWFINEFREQ field. */ + #define AUXPLL_TASKS_NEWFINEFREQ_TASKS_NEWFINEFREQ_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_TASKS_NEWBASEFREQ: Change base frequency */ + #define AUXPLL_TASKS_NEWBASEFREQ_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEWBASEFREQ register. */ + +/* TASKS_NEWBASEFREQ @Bit 0 : Change base frequency */ + #define AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Pos (0UL) /*!< Position of TASKS_NEWBASEFREQ field. */ + #define AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Msk (0x1UL << AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Pos) /*!< Bit mask + of TASKS_NEWBASEFREQ field.*/ + #define AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Min (0x1UL) /*!< Min enumerator value of TASKS_NEWBASEFREQ field. */ + #define AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Max (0x1UL) /*!< Max enumerator value of TASKS_NEWBASEFREQ field. */ + #define AUXPLL_TASKS_NEWBASEFREQ_TASKS_NEWBASEFREQ_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_TASKS_FREQINCSTART: Start automated frequency increment */ + #define AUXPLL_TASKS_FREQINCSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQINCSTART register. */ + +/* TASKS_FREQINCSTART @Bit 0 : Start automated frequency increment */ + #define AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Pos (0UL) /*!< Position of TASKS_FREQINCSTART field. */ + #define AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Msk (0x1UL << AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Pos) /*!< Bit + mask of TASKS_FREQINCSTART field.*/ + #define AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQINCSTART field. */ + #define AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQINCSTART field. */ + #define AUXPLL_TASKS_FREQINCSTART_TASKS_FREQINCSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_TASKS_FREQINCSTOP: Stop automated frequency increment */ + #define AUXPLL_TASKS_FREQINCSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQINCSTOP register. */ + +/* TASKS_FREQINCSTOP @Bit 0 : Stop automated frequency increment */ + #define AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Pos (0UL) /*!< Position of TASKS_FREQINCSTOP field. */ + #define AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Msk (0x1UL << AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Pos) /*!< Bit mask + of TASKS_FREQINCSTOP field.*/ + #define AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQINCSTOP field. */ + #define AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQINCSTOP field. */ + #define AUXPLL_TASKS_FREQINCSTOP_TASKS_FREQINCSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* AUXPLL_EVENTS_STARTED: AUXPLL started */ + #define AUXPLL_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : AUXPLL started */ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AUXPLL_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* AUXPLL_EVENTS_STOPPED: AUXPLL stopped */ + #define AUXPLL_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : AUXPLL stopped */ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AUXPLL_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* AUXPLL_EVENTS_LOCKED: AUXPLL locked */ + #define AUXPLL_EVENTS_LOCKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LOCKED register. */ + +/* EVENTS_LOCKED @Bit 0 : AUXPLL locked */ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Pos (0UL) /*!< Position of EVENTS_LOCKED field. */ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Msk (0x1UL << AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Pos) /*!< Bit mask of + EVENTS_LOCKED field.*/ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_LOCKED field. */ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_LOCKED field. */ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AUXPLL_EVENTS_LOCKED_EVENTS_LOCKED_Generated (0x1UL) /*!< Event generated */ + + +/* AUXPLL_INTEN: Enable or disable interrupt */ + #define AUXPLL_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */ + #define AUXPLL_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define AUXPLL_INTEN_STARTED_Msk (0x1UL << AUXPLL_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define AUXPLL_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define AUXPLL_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define AUXPLL_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define AUXPLL_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define AUXPLL_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define AUXPLL_INTEN_STOPPED_Msk (0x1UL << AUXPLL_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define AUXPLL_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define AUXPLL_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define AUXPLL_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define AUXPLL_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* LOCKED @Bit 2 : Enable or disable interrupt for event LOCKED */ + #define AUXPLL_INTEN_LOCKED_Pos (2UL) /*!< Position of LOCKED field. */ + #define AUXPLL_INTEN_LOCKED_Msk (0x1UL << AUXPLL_INTEN_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define AUXPLL_INTEN_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define AUXPLL_INTEN_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define AUXPLL_INTEN_LOCKED_Disabled (0x0UL) /*!< Disable */ + #define AUXPLL_INTEN_LOCKED_Enabled (0x1UL) /*!< Enable */ + + +/* AUXPLL_INTENSET: Enable interrupt */ + #define AUXPLL_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define AUXPLL_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define AUXPLL_INTENSET_STARTED_Msk (0x1UL << AUXPLL_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define AUXPLL_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define AUXPLL_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define AUXPLL_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define AUXPLL_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define AUXPLL_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define AUXPLL_INTENSET_STOPPED_Msk (0x1UL << AUXPLL_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define AUXPLL_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define AUXPLL_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define AUXPLL_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define AUXPLL_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOCKED @Bit 2 : Write '1' to enable interrupt for event LOCKED */ + #define AUXPLL_INTENSET_LOCKED_Pos (2UL) /*!< Position of LOCKED field. */ + #define AUXPLL_INTENSET_LOCKED_Msk (0x1UL << AUXPLL_INTENSET_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define AUXPLL_INTENSET_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define AUXPLL_INTENSET_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define AUXPLL_INTENSET_LOCKED_Set (0x1UL) /*!< Enable */ + #define AUXPLL_INTENSET_LOCKED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENSET_LOCKED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AUXPLL_INTENCLR: Disable interrupt */ + #define AUXPLL_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define AUXPLL_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define AUXPLL_INTENCLR_STARTED_Msk (0x1UL << AUXPLL_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define AUXPLL_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define AUXPLL_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define AUXPLL_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define AUXPLL_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define AUXPLL_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define AUXPLL_INTENCLR_STOPPED_Msk (0x1UL << AUXPLL_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define AUXPLL_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define AUXPLL_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define AUXPLL_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define AUXPLL_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOCKED @Bit 2 : Write '1' to disable interrupt for event LOCKED */ + #define AUXPLL_INTENCLR_LOCKED_Pos (2UL) /*!< Position of LOCKED field. */ + #define AUXPLL_INTENCLR_LOCKED_Msk (0x1UL << AUXPLL_INTENCLR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define AUXPLL_INTENCLR_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define AUXPLL_INTENCLR_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define AUXPLL_INTENCLR_LOCKED_Clear (0x1UL) /*!< Disable */ + #define AUXPLL_INTENCLR_LOCKED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AUXPLL_INTENCLR_LOCKED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AUXPLL_INTPEND: Pending interrupts */ + #define AUXPLL_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* STARTED @Bit 0 : Read pending status of interrupt for event STARTED */ + #define AUXPLL_INTPEND_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define AUXPLL_INTPEND_STARTED_Msk (0x1UL << AUXPLL_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define AUXPLL_INTPEND_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define AUXPLL_INTPEND_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define AUXPLL_INTPEND_STARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define AUXPLL_INTPEND_STARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */ + #define AUXPLL_INTPEND_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define AUXPLL_INTPEND_STOPPED_Msk (0x1UL << AUXPLL_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define AUXPLL_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define AUXPLL_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define AUXPLL_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define AUXPLL_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* LOCKED @Bit 2 : Read pending status of interrupt for event LOCKED */ + #define AUXPLL_INTPEND_LOCKED_Pos (2UL) /*!< Position of LOCKED field. */ + #define AUXPLL_INTPEND_LOCKED_Msk (0x1UL << AUXPLL_INTPEND_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define AUXPLL_INTPEND_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define AUXPLL_INTPEND_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define AUXPLL_INTPEND_LOCKED_NotPending (0x0UL) /*!< Read: Not pending */ + #define AUXPLL_INTPEND_LOCKED_Pending (0x1UL) /*!< Read: Pending */ + + +/* AUXPLL_STATUS: Status of AUXPLL */ + #define AUXPLL_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* MODE @Bit 0 : AUXPLL mode */ + #define AUXPLL_STATUS_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define AUXPLL_STATUS_MODE_Msk (0x1UL << AUXPLL_STATUS_MODE_Pos) /*!< Bit mask of MODE field. */ + #define AUXPLL_STATUS_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define AUXPLL_STATUS_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define AUXPLL_STATUS_MODE_Freerunning (0x0UL) /*!< Freerunning mode */ + #define AUXPLL_STATUS_MODE_Locked (0x1UL) /*!< Locked mode */ + +/* PLLRUNNING @Bit 1 : AUXPLL running status */ + #define AUXPLL_STATUS_PLLRUNNING_Pos (1UL) /*!< Position of PLLRUNNING field. */ + #define AUXPLL_STATUS_PLLRUNNING_Msk (0x1UL << AUXPLL_STATUS_PLLRUNNING_Pos) /*!< Bit mask of PLLRUNNING field. */ + #define AUXPLL_STATUS_PLLRUNNING_Min (0x0UL) /*!< Min enumerator value of PLLRUNNING field. */ + #define AUXPLL_STATUS_PLLRUNNING_Max (0x1UL) /*!< Max enumerator value of PLLRUNNING field. */ + #define AUXPLL_STATUS_PLLRUNNING_Off (0x0UL) /*!< PLL not running */ + #define AUXPLL_STATUS_PLLRUNNING_Running (0x1UL) /*!< PLL running */ + +/* FREQUENCYACTUAL @Bits 16..31 : Actual fractional PLL divider ratio */ + #define AUXPLL_STATUS_FREQUENCYACTUAL_Pos (16UL) /*!< Position of FREQUENCYACTUAL field. */ + #define AUXPLL_STATUS_FREQUENCYACTUAL_Msk (0xFFFFUL << AUXPLL_STATUS_FREQUENCYACTUAL_Pos) /*!< Bit mask of FREQUENCYACTUAL + field.*/ + + +/* AUXPLL_MIRROR: Enable LOCK for mirrored registers */ + #define AUXPLL_MIRROR_ResetValue (0x00000000UL) /*!< Reset value of MIRROR register. */ + +/* LOCK @Bit 0 : Lock for mirrored registers */ + #define AUXPLL_MIRROR_LOCK_Pos (0UL) /*!< Position of LOCK field. */ + #define AUXPLL_MIRROR_LOCK_Msk (0x1UL << AUXPLL_MIRROR_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define AUXPLL_MIRROR_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define AUXPLL_MIRROR_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define AUXPLL_MIRROR_LOCK_Disabled (0x0UL) /*!< Lock disabled */ + #define AUXPLL_MIRROR_LOCK_Enabled (0x1UL) /*!< Lock enabled */ + + #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ /* =========================================================================================================================== */ @@ -6486,12 +6980,17 @@ typedef struct { * @brief IOPORT [BICR_IOPORT] (unspecified) */ typedef struct { - __IOM uint32_t POWER0; /*!< (@ 0x00000000) Power configuration for P0 to P7 IO ports. */ + __IOM uint32_t POWER0; /*!< (@ 0x00000000) Power configuration for P0 to P7 IO ports. Note: P0 is + not included in the fields of this register because it + is always internally supplied and therefore considered + 'Shorted'.*/ __IOM uint32_t POWER1; /*!< (@ 0x00000004) Power configuration for P8 to P15 IO ports. */ __IOM uint32_t DRIVECTRL0; /*!< (@ 0x00000008) Drive control configuration for P0 to P7 IO ports. */ } NRF_BICR_IOPORT_Type; /*!< Size = 12 (0x00C) */ -/* BICR_IOPORT_POWER0: Power configuration for P0 to P7 IO ports. */ +/* BICR_IOPORT_POWER0: Power configuration for P0 to P7 IO ports. Note: P0 is not included in the fields of this register + because it is always internally supplied and therefore considered 'Shorted'. */ + #define BICR_IOPORT_POWER0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of POWER0 register. */ /* P1 @Bits 4..7 : P1 power configuration. */ @@ -6624,6 +7123,7 @@ typedef struct { #define BICR_LFOSC_LFXOCONFIG_MODE_Crystal (0x0UL) /*!< LFXO in external crystal oscillator mode. */ #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSine (0x2UL) /*!< LFXO in external sine wave mode. */ #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSquare (0x3UL) /*!< LFXO in external square wave mode. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Disabled (0x6UL) /*!< LFXO is not to be used. */ /* LOADCAP @Bits 8..15 : Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. */ #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Pos (8UL) /*!< Position of LOADCAP field. */ @@ -6711,8 +7211,6 @@ typedef struct { #define BICR_HFXO_CONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured. */ #define BICR_HFXO_CONFIG_MODE_Crystal (0x0UL) /*!< HFXO in external crystal oscillator mode. */ #define BICR_HFXO_CONFIG_MODE_ExtSquare (0x3UL) /*!< HFXO in external square wave mode. */ - #define BICR_HFXO_CONFIG_MODE_Auto (0x6UL) /*!< Either Pierce or PIXO automatically handled by the system based on - system requests.*/ /* LOADCAP @Bits 12..19 : Built-in load capacitors selection in 0.25 pF steps. Max. value 25.75 pF. */ #define BICR_HFXO_CONFIG_LOADCAP_Pos (12UL) /*!< Position of LOADCAP field. */ @@ -7647,7 +8145,7 @@ typedef struct { __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x00000088) Subscribe configuration for task RATEOVERRIDE */ __IM uint32_t RESERVED1[30]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Encrypt/decrypt complete or ended because of an error */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ __IM uint32_t RESERVED2[30]; __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ @@ -7764,10 +8262,10 @@ typedef struct { #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (0x1UL) /*!< Enable subscription */ -/* CCM_EVENTS_END: Encrypt/decrypt complete */ +/* CCM_EVENTS_END: Encrypt/decrypt complete or ended because of an error */ #define CCM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ -/* EVENTS_END @Bit 0 : Encrypt/decrypt complete */ +/* EVENTS_END @Bit 0 : Encrypt/decrypt complete or ended because of an error */ #define CCM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define CCM_EVENTS_END_EVENTS_END_Msk (0x1UL << CCM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ #define CCM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ @@ -18905,19 +19403,8 @@ typedef struct { * @brief PORTCNF [GPIO_PORTCNF] (unspecified) */ typedef struct { - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - struct { - __IOM uint32_t DRIVECTRL; /*!< (@ 0x00000000) Drive control for impedance matching of the pins in + __IOM uint32_t DRIVECTRL; /*!< (@ 0x00000000) Drive control for impedance matching of the pins in this port*/ - }; - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif __IM uint32_t RESERVED; } NRF_GPIO_PORTCNF_Type; /*!< Size = 8 (0x008) */ @@ -25077,16 +25564,7 @@ typedef struct { typedef struct { __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __OM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __OM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ } NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ #define GRTC_CC_MaxCount (16UL) /*!< Size of CC[16] array. */ @@ -52895,7 +53373,7 @@ typedef struct { #define LRCCONF_AX2XWAITSTATES_MaxCount (16UL) /*!< Max size of AX2XWAITSTATES[16] array. */ #define LRCCONF_AX2XWAITSTATES_MaxIndex (15UL) /*!< Max index of AX2XWAITSTATES[16] array. */ #define LRCCONF_AX2XWAITSTATES_MinIndex (0UL) /*!< Min index of AX2XWAITSTATES[16] array. */ - #define LRCCONF_AX2XWAITSTATES_ResetValue (0x00000007UL) /*!< Reset value of AX2XWAITSTATES[16] register. */ + #define LRCCONF_AX2XWAITSTATES_ResetValue (0x00000000UL) /*!< Reset value of AX2XWAITSTATES[16] register. */ /* WAITSTATES @Bits 0..2 : Number of waitstates */ #define LRCCONF_AX2XWAITSTATES_WAITSTATES_Pos (0UL) /*!< Position of WAITSTATES field. */ @@ -62386,6 +62864,24 @@ typedef struct { #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ +/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ0_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ1_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut */ + /* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ @@ -63293,16 +63789,7 @@ typedef struct { __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task*/ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) (unspecified) */ __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ __IM uint32_t RESERVED6[5]; __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ @@ -64426,53 +64913,51 @@ typedef struct { __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[33]; __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ - __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ + __IM uint32_t RESERVED9; __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ - __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ - __IM uint32_t RESERVED9[4]; + __IM uint32_t RESERVED10[5]; __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ - __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ + __IM uint32_t RESERVED11; __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ - __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ - __IM uint32_t RESERVED10[18]; + __IM uint32_t RESERVED12[19]; __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ - __IM uint32_t RESERVED11[7]; + __IM uint32_t RESERVED13[7]; __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED14[3]; __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED15; __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000540) Data whitening initial value */ - __IM uint32_t RESERVED14[112]; + __IM uint32_t RESERVED16[112]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED17; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED16[123]; + __IM uint32_t RESERVED18[123]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED17[253]; + __IM uint32_t RESERVED19[253]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED18[2]; + __IM uint32_t RESERVED20[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED19[4]; + __IM uint32_t RESERVED21[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED20[41]; + __IM uint32_t RESERVED22[41]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED21; + __IM uint32_t RESERVED23; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -64487,16 +64972,16 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED22[3]; + __IM uint32_t RESERVED24[3]; __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED25[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED24[3]; + __IM uint32_t RESERVED26[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) (unspecified) */ - __IM uint32_t RESERVED25[75]; + __IM uint32_t RESERVED27[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -67768,17 +68253,8 @@ typedef struct { #define RESETINFO_RESETREAS_LOCAL_LOCKUP_NotDetected (0x0UL) /*!< Not detected */ #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Detected (0x1UL) /*!< Detected */ -/* CROSSDOMAIN @Bit 4 : Reset due to cross domain reset source. */ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos (4UL) /*!< Position of CROSSDOMAIN field. */ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos) /*!< Bit mask of - CROSSDOMAIN field.*/ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Min (0x0UL) /*!< Min enumerator value of CROSSDOMAIN field. */ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Max (0x1UL) /*!< Max enumerator value of CROSSDOMAIN field. */ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_NotDetected (0x0UL) /*!< Not detected */ - #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Detected (0x1UL) /*!< Detected */ - -/* UNRETAINEDWAKE @Bit 5 : Reset due to wake from unretained state. */ - #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos (5UL) /*!< Position of UNRETAINEDWAKE field. */ +/* UNRETAINEDWAKE @Bit 4 : Reset due to wake from unretained state. */ + #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos (4UL) /*!< Position of UNRETAINEDWAKE field. */ #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos) /*!< Bit mask of UNRETAINEDWAKE field.*/ @@ -68815,19 +69291,8 @@ typedef struct { * @brief CH [SAADC_CH] (unspecified) */ typedef struct { - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ - }; - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ } NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ @@ -68838,11 +69303,11 @@ typedef struct { /* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ -/* PIN @Bits 0..4 : Analog positive input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELP_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field. */ -/* PORT @Bits 8..11 : GPIO Port selection */ +/* PORT @Bits 8..11 : GPIO port selection */ #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ @@ -68858,7 +69323,7 @@ typedef struct { /* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ -/* PIN @Bits 0..4 : Analog negative input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELN_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -68882,11 +69347,12 @@ typedef struct { #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ #define SAADC_CH_CONFIG_GAIN_Msk (0x3UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ #define SAADC_CH_CONFIG_GAIN_Min (0x0UL) /*!< Min enumerator value of GAIN field. */ - #define SAADC_CH_CONFIG_GAIN_Max (0x3UL) /*!< Max enumerator value of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Max (0x4UL) /*!< Max enumerator value of GAIN field. */ #define SAADC_CH_CONFIG_GAIN_Gain2_3 (0x0UL) /*!< 2/3 */ #define SAADC_CH_CONFIG_GAIN_Gain1 (0x1UL) /*!< 1 */ #define SAADC_CH_CONFIG_GAIN_Gain2 (0x2UL) /*!< 2 */ - #define SAADC_CH_CONFIG_GAIN_Gain4 (0x3UL) /*!< 4 */ + #define SAADC_CH_CONFIG_GAIN_Gain3 (0x3UL) /*!< 4 */ + #define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */ /* BURST @Bit 11 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (11UL) /*!< Position of BURST field. */ @@ -68995,7 +69461,9 @@ typedef struct { typedef struct { /*!< SAADC Structure */ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in RAM */ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels - are sampled*/ + are sampled. This task requires that SAADC has started, + i.e. EVENTS_STARTED was set and EVENTS_STOPPED was + not.*/ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ __IM uint32_t RESERVED[28]; @@ -69042,7 +69510,9 @@ typedef struct { __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ __IM uint32_t RESERVED9[12]; __IOM NRF_SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ - } NRF_SAADC_Type; /*!< Size = 1596 (0x63C) */ + __IM uint32_t RESERVED10[6]; + __IOM uint32_t NOISESHAPE; /*!< (@ 0x00000654) Enable noise shaping */ + } NRF_SAADC_Type; /*!< Size = 1624 (0x658) */ /* SAADC_TASKS_START: Start the ADC and prepare the result buffer in RAM */ #define SAADC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ @@ -69055,10 +69525,14 @@ typedef struct { #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ -/* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled */ +/* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has + started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */ + #define SAADC_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ -/* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ +/* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has + started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field.*/ @@ -70014,6 +70488,25 @@ typedef struct { #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ +/* SAADC_NOISESHAPE: Enable noise shaping */ + #define SAADC_NOISESHAPE_ResetValue (0x00000000UL) /*!< Reset value of NOISESHAPE register. */ + +/* NOISESHAPE @Bits 0..1 : Enable noise shaping */ + #define SAADC_NOISESHAPE_NOISESHAPE_Pos (0UL) /*!< Position of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Msk (0x3UL << SAADC_NOISESHAPE_NOISESHAPE_Pos) /*!< Bit mask of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Min (0x0UL) /*!< Min enumerator value of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Max (0x3UL) /*!< Max enumerator value of NOISESHAPE field. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Disable (0x0UL) /*!< Disable noiseshaping. Oversampling based on accumulate and average. */ + #define SAADC_NOISESHAPE_NOISESHAPE_Audio (0x1UL) /*!< Noiseshaping and decimating. Larger passband. Provides a 100kS/s cut + off frequency, 8x the oversampling ratio. See design description for + more information*/ + #define SAADC_NOISESHAPE_NOISESHAPE_Accuracy (0x2UL) /*!< Noiseshaping and decimating. Smaller passband. Recommended + resolution setting is 14 bits. Provides a 10kS/s cut off frequency, + 32x the oversampling ratio. See design description for more + information*/ + #define SAADC_NOISESHAPE_NOISESHAPE_Stage1 (0x3UL) /*!< Result from common 1st stage filter. For debugging only */ + + #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ /* =========================================================================================================================== */ @@ -75751,16 +76244,7 @@ typedef union { struct { __IOM NRF_SPU_FEATURE_IPCT_Type IPCT; /*!< (@ 0x00000000) (unspecified) */ __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC; /*!< (@ 0x00000080) (unspecified) */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[1]; /*!< (@ 0x00000100) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[1]; /*!< (@ 0x00000100) (unspecified) */ __IM uint32_t RESERVED[48]; #if defined(_GNUC_) #pragma GCC diagnostic push @@ -92489,6 +92973,397 @@ typedef struct { #define UICR_TRACE_PORTCONFIG_PORTCONFIG_EightSpeed (0x0UL) /*!< One eigth speed */ + +/* ============================================== Struct UICR_TAMPER_DETECTION =============================================== */ +/** + * @brief DETECTION [UICR_TAMPER_DETECTION] Tamper policy configuration for detected security events. + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) (unspecified) */ + __IOM uint32_t RESPONSE0; /*!< (@ 0x00000004) (unspecified) */ + __IOM uint32_t RESPONSE1; /*!< (@ 0x00000008) (unspecified) */ + __IOM uint32_t TEMPDETECTORCONFIG; /*!< (@ 0x0000000C) (unspecified) */ +} NRF_UICR_TAMPER_DETECTION_Type; /*!< Size = 16 (0x010) */ + +/* UICR_TAMPER_DETECTION_ENABLE: (unspecified) */ + #define UICR_TAMPER_DETECTION_ENABLE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ENABLE register. */ + +/* GlobalEnable @Bit 0 : Enable tamper detection. When disabled all tamper enable and policy switches are ignored. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Pos (0UL) /*!< Position of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Pos) /*!< Bit mask + of GlobalEnable field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Min (0x0UL) /*!< Min enumerator value of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Max (0x1UL) /*!< Max enumerator value of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Enable (0x0UL) /*!< Enable tamper detection. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Disable (0x1UL) /*!< Disable tamper detection. */ + +/* VoltageLevel @Bit 1 : Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when + voltage on the corresponding supply line is too low. */ + + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Pos (1UL) /*!< Position of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Pos) /*!< Bit mask + of VoltageLevel field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Min (0x0UL) /*!< Min enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Max (0x1UL) /*!< Max enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Enable (0x0UL) /*!< Enable voltage level detectors. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Disable (0x1UL) /*!< Disable voltage level detectors. */ + +/* ExternalActiveShield @Bit 4 : Enable external active shield detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Pos (4UL) /*!< Position of ExternalActiveShield field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Pos) + /*!< Bit mask of ExternalActiveShield field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Min (0x0UL) /*!< Min enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Max (0x1UL) /*!< Max enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Enable (0x0UL) /*!< Enable external active shield detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Disable (0x1UL) /*!< Disable external active shield detector. */ + +/* HardFault @Bit 7 : Configure if tamper prevention should react on hard faults. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Pos (7UL) /*!< Position of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_HardFault_Pos) /*!< Bit mask of + HardFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Min (0x0UL) /*!< Min enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Max (0x1UL) /*!< Max enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Enable (0x0UL) /*!< Enable hard fault detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Disable (0x1UL) /*!< Disable hard fault detector. */ + +/* ApiFault @Bit 8 : Configure if tamper prevention should react on invalid API usage. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Pos (8UL) /*!< Position of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_ApiFault_Pos) /*!< Bit mask of + ApiFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Min (0x0UL) /*!< Min enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Max (0x1UL) /*!< Max enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Enable (0x0UL) /*!< Enable API fault detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Disable (0x1UL) /*!< Disable API fault detector. */ + +/* AdacFault @Bit 9 : Configure if tamper prevention should react on invalid ADAC usage. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Pos (9UL) /*!< Position of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_AdacFault_Pos) /*!< Bit mask of + AdacFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Min (0x0UL) /*!< Min enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Max (0x1UL) /*!< Max enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Enable (0x0UL) /*!< Enable invalid ADAC usage detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Disable (0x1UL) /*!< Disable invalid ADAC usage detector. */ + +/* StateFault @Bit 10 : Configure if tamper prevention should react on invalid firmware execution state. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Pos (10UL) /*!< Position of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_StateFault_Pos) /*!< Bit mask of + StateFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Min (0x0UL) /*!< Min enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Max (0x1UL) /*!< Max enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Enable (0x0UL) /*!< Enable invalid firmware execution state detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Disable (0x1UL) /*!< Disable invalid firmware execution state detector. */ + +/* TemperatureFault @Bit 11 : Configure if tamper prevention should react when on-die temperature exceeds a valid range. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Pos (11UL) /*!< Position of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Pos) /*!< + Bit mask of TemperatureFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Min (0x0UL) /*!< Min enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Max (0x1UL) /*!< Max enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Enable (0x0UL) /*!< Enable invalid out-of-range temperature detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Disable (0x1UL) /*!< Disable invalid out-of-range temperature detector.*/ + + +/* UICR_TAMPER_DETECTION_RESPONSE0: (unspecified) */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RESPONSE0 register. */ + +/* VoltageLevel @Bits 0..3 : Configure tamper policy for invalid voltage level on supply lines. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Pos (0UL) /*!< Position of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Pos) /*!< Bit + mask of VoltageLevel field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Min (0x2UL) /*!< Min enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Max (0xFUL) /*!< Max enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_1Hour (0x4UL) /*!< Block secure services until device has been powered + and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* Watchdog @Bits 4..7 : Configure tamper policy for watchdog timer. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Pos (4UL) /*!< Position of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Pos) /*!< Bit mask of + Watchdog field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Min (0x2UL) /*!< Min enumerator value of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Max (0xFUL) /*!< Max enumerator value of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* ExternalActiveShield @Bits 12..15 : Configure tamper policy for external active shield. BICR is used to specify which + channels (GPIOs) are enabled. */ + + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Pos (12UL) /*!< Position of ExternalActiveShield field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Pos) + /*!< Bit mask of ExternalActiveShield field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Min (0x1UL) /*!< Min enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Max (0xFUL) /*!< Max enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Manual (0x1UL) /*!< Block secure services until requested to + unblock secure services. Allows user application to + take required actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_PowerCycle (0x2UL) /*!< Block secure services until power cycling + the device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_15Minutes (0x3UL) /*!< Block secure services until device has + been powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, + this bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + +/* InternalDetectors @Bits 20..23 : Configure tamper policy for internal detectors including glitch detector, signal protector + and CRACEN detector. See for more information. An automatic reset is issued upon detection. + */ + + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Pos (20UL) /*!< Position of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Pos) + /*!< Bit mask of InternalDetectors field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Min (0x2UL) /*!< Min enumerator value of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Max (0xFUL) /*!< Max enumerator value of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_PowerCycle (0x2UL) /*!< Block secure services until power cycling + the device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + +/* HardFault @Bits 24..27 : Configure tamper policy for hard fault. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Pos (24UL) /*!< Position of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Pos) /*!< Bit mask + of HardFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Min (0x1UL) /*!< Min enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Max (0xFUL) /*!< Max enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* ApiFault @Bits 28..31 : Configure tamper policy for invalid API usage. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Pos (28UL) /*!< Position of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Pos) /*!< Bit mask of + ApiFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Min (0x1UL) /*!< Min enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Max (0xFUL) /*!< Max enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + + +/* UICR_TAMPER_DETECTION_RESPONSE1: (unspecified) */ + #define UICR_TAMPER_DETECTION_RESPONSE1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RESPONSE1 register. */ + +/* AdacFault @Bits 0..3 : Configure tamper policy for invalid ADAC usage. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Pos (0UL) /*!< Position of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Pos) /*!< Bit mask + of AdacFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Min (0x1UL) /*!< Min enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Max (0xFUL) /*!< Max enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* StateFault @Bits 4..7 : Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure + domain before secure services are permitted again. */ + + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Pos (4UL) /*!< Position of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Pos) /*!< Bit mask + of StateFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Min (0x1UL) /*!< Min enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Max (0xFUL) /*!< Max enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* TemperatureFault @Bits 8..11 : Configure out-of-range on-die temperature tamper policy. A reset is required to continue + providing secure services once the on-temperature is within valid operating conditions again. + This reset is automatically triggered by the secure domain. */ + + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Pos (8UL) /*!< Position of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Pos) + /*!< Bit mask of TemperatureFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Min (0x1UL) /*!< Min enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Max (0xFUL) /*!< Max enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Manual (0x1UL) /*!< Block secure services until requested to unblock + secure services. Allows user application to take + required actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + + +/* UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG: (unspecified) */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TEMPDETECTORCONFIG register. */ + +/* TemperatureDetectionStrategy @Bits 0..1 : Configure when on-die temperature sensor should check the temperature. */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Pos (0UL) /*!< Position of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Msk (0x3UL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Pos) + /*!< Bit mask of TemperatureDetectionStrategy + field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Min (0x1UL) /*!< Min enumerator value of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Max (0x3UL) /*!< Max enumerator value of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Periodically (0x1UL) /*!< On-die temperature + sensor is read periodically with selected interval.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_OnServiceCallAndPeriodically (0x2UL) /*!< On-die + temperature sensor is read before each secure + service call and periodically with selected + interval.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_OnServiceCallOnly (0x3UL) /*!< On-die + temperature sensor is read before each secure + service call.*/ + +/* TemperatureDetectionInterval @Bits 2..3 : Configure interval for on-die temperature reading if periodic reading is enabled. */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Pos (2UL) /*!< Position of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Msk (0x3UL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Pos) + /*!< Bit mask of TemperatureDetectionInterval + field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Min (0x0UL) /*!< Min enumerator value of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Max (0x3UL) /*!< Max enumerator value of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_1Minute (0x0UL) /*!< On-die temperature sensor + is read with one minute intervals.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_15Minutes (0x2UL) /*!< On-die temperature sensor + is read with 15 minutes intervals.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_1Hour (0x3UL) /*!< On-die temperature sensor is + read with one hour intervals.*/ + +/* LowTemperatureThresholdShift @Bits 4..11 : Low temperature detection threshold shift in degrees Celsius. The low temperature + threshold is calculated by adding the threshold shift to the minimum operating + temperature of the SoC. */ + + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Pos (4UL) /*!< Position of + LowTemperatureThresholdShift field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Msk (0xFFUL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Pos) + /*!< Bit mask of LowTemperatureThresholdShift + field.*/ + +/* HighTemperatureThresholdShift @Bits 12..19 : High temperature detection threshold shift in degrees Celsius. The high + temperature threshold is calculated by subtracting the threshold shift from the + maximum operating temperature of the SoC. */ + + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Pos (12UL) /*!< Position of + HighTemperatureThresholdShift field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Msk (0xFFUL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Pos) + /*!< Bit mask of HighTemperatureThresholdShift + field.*/ + + + +/* =========================================== Struct UICR_TAMPER_COUNTERMEASURES ============================================ */ +/** + * @brief COUNTERMEASURES [UICR_TAMPER_COUNTERMEASURES] Configuration of countermeasures. + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_TAMPER_COUNTERMEASURES_Type; /*!< Size = 4 (0x004) */ + +/* UICR_TAMPER_COUNTERMEASURES_ENABLE: (unspecified) */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ENABLE register. */ + +/* DPAAES @Bit 0 : Configure Differential Power Analysis countermeasure for CRACEN AES. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Pos (0UL) /*!< Position of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Pos) /*!< Bit mask + of DPAAES field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Min (0x0UL) /*!< Min enumerator value of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Max (0x1UL) /*!< Max enumerator value of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Disable (0x1UL) /*!< Disable countermeasure. */ + +/* DPAPK @Bit 1 : Configure Differential Power Analysis countermeasure for CRACEN PK. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Pos (1UL) /*!< Position of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Pos) /*!< Bit mask of + DPAPK field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Min (0x0UL) /*!< Min enumerator value of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Max (0x1UL) /*!< Max enumerator value of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Disable (0x1UL) /*!< Disable countermeasure. */ + +/* ClockDithering @Bit 9 : Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on + TRNG. */ + + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Pos (9UL) /*!< Position of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Pos) + /*!< Bit mask of ClockDithering field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Min (0x0UL) /*!< Min enumerator value of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Max (0x1UL) /*!< Max enumerator value of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Disable (0x1UL) /*!< Disable countermeasure. */ + + + +/* =================================================== Struct UICR_TAMPER ==================================================== */ +/** + * @brief TAMPER [UICR_TAMPER] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_TAMPER_DETECTION_Type DETECTION; /*!< (@ 0x00000000) Tamper policy configuration for detected security + events.*/ + __IOM NRF_UICR_TAMPER_COUNTERMEASURES_Type COUNTERMEASURES; /*!< (@ 0x00000010) Configuration of countermeasures. */ +} NRF_UICR_TAMPER_Type; /*!< Size = 20 (0x014) */ + /* ======================================================= Struct UICR ======================================================= */ /** * @brief User information configuration registers @@ -92508,12 +93383,14 @@ typedef struct { __IM uint32_t RESERVED4[16]; __IOM NRF_UICR_MAILBOX_Type MAILBOX[8]; /*!< (@ 0x00000700) (unspecified) */ __IOM NRF_UICR_TRACE_Type TRACE; /*!< (@ 0x00000740) (unspecified) */ - __IM uint32_t RESERVED5[12]; + __IM uint32_t RESERVED5[4]; + __IOM NRF_UICR_TAMPER_Type TAMPER; /*!< (@ 0x00000760) (unspecified) */ + __IM uint32_t RESERVED6[3]; __IOM uint32_t INITSVTOR; /*!< (@ 0x00000780) Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset.*/ __IOM uint32_t INITNSVTOR; /*!< (@ 0x00000784) Initial value of the non-secure VTOR (Vector Table Offset Register).*/ - __IM uint32_t RESERVED6[29]; + __IM uint32_t RESERVED7[29]; __IOM uint32_t PTREXTUICR; /*!< (@ 0x000007FC) Pointer to extended UICR. */ } NRF_UICR_Type; /*!< Size = 2048 (0x800) */ diff --git a/mdk/nrf54h20_version.h b/mdk/nrf54h20_version.h index c3a45461c..b58f70810 100644 --- a/mdk/nrf54h20_version.h +++ b/mdk/nrf54h20_version.h @@ -42,9 +42,8 @@ POSSIBILITY OF SUCH DAMAGE. #define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of product specification. */ #define MDK_SOURCE_VERSION_MINOR 2 /*!< Minor version of product specification. */ -#define MDK_SOURCE_VERSION_MICRO 28 /*!< Micro version of product specification. */ +#define MDK_SOURCE_VERSION_MICRO 30 /*!< Micro version of product specification. */ -#define MDK_SOURCE_HASH Lilium_FP1_IPS_v0.2.28 /*!< Git hash of product specification source. */ #ifdef __cplusplus diff --git a/mdk/nrf54l15_application.h b/mdk/nrf54l15_application.h index d951e3a9a..59c643c0e 100644 --- a/mdk/nrf54l15_application.h +++ b/mdk/nrf54l15_application.h @@ -195,7 +195,7 @@ typedef enum { #define __MPU_PRESENT 1 /*!< MPU present */ #define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_DP 0 /*!< Double Precision FPU */ -#define __INTERRUPTS_MAX 176 /*!< Size of interrupt vector table */ +#define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ #define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ #define __SAUREGION_PRESENT 1 /*!< SAU present */ #define __NUM_SAUREGIONS 4 /*!< Number of regions */ @@ -206,6 +206,14 @@ typedef enum { #endif /*!< NRF_APPLICATION */ +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_CM33 + +#endif /*!< NRF_APPLICATION */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54l15_application.svd b/mdk/nrf54l15_application.svd index 4bd0bc53d..905ca7f10 100644 --- a/mdk/nrf54l15_application.svd +++ b/mdk/nrf54l15_application.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE. 1 3 0 - 176 + 270 4 system_nrf54l15_application @@ -613,9 +613,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -635,9 +635,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -666,9 +666,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -688,9 +688,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -719,9 +719,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.AP[0] DBGEN signal protector. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -741,9 +741,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.AP[0] DBGEN signal protector. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -772,9 +772,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Protected, the device cannot be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is locked. - 0x50FA50FA + Unprotected + The device can be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF @@ -794,9 +794,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Protected, the device cannot be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is locked. - 0x50FA50FA + Unprotected + The device canbe erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF @@ -1107,7 +1107,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 256 + 128 0x040 SET[%s] Unspecified @@ -1170,7 +1170,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 256 + 128 0x008 SET[%s] Unspecified @@ -12765,7 +12765,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel n of DPPIC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -12814,7 +12814,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel group n of DPPIC 0x060 read-write - 0x00000000 + 0x00100010 0x20 @@ -12862,7 +12862,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x040 GPIOTE[%s] Unspecified - GPIOTE + SPU_FEATURE_GPIOTE read-write 0x100 @@ -12872,7 +12872,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel o of GPIOTE[n] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -12921,7 +12921,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for interrupt o of GPIOTE[n] 0x020 read-write - 0x00000000 + 0x00100010 0x20 @@ -12979,7 +12979,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for GPIO[n] PIN[o] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -13034,7 +13034,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration for CRACEN SEED 0x180 read-write - 0x00000000 + 0x00020010 0x20 @@ -13090,7 +13090,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for CC n of GRTC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -13137,7 +13137,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of feature for PWMCONFIG of GRTC 0x074 read-write - 0x00000000 + 0x00100010 0x20 @@ -13184,7 +13184,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of features for CLKOUT/CLKCFG of GRTC 0x078 read-write - 0x00000000 + 0x00100010 0x20 @@ -13231,7 +13231,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC 0x07C read-write - 0x00000000 + 0x00100010 0x20 @@ -13280,7 +13280,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for interrupt n of GRTC 0x080 read-write - 0x00000000 + 0x00100010 0x20 @@ -29537,92 +29537,92 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Baud1200 - 1200 baud (actual rate: 1205) + 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency 0x0004F000 Baud2400 - 2400 baud (actual rate: 2396) + 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency 0x0009D000 Baud4800 - 4800 baud (actual rate: 4808) + 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency 0x0013B000 Baud9600 - 9600 baud (actual rate: 9598) + 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency 0x00275000 Baud14400 - 14400 baud (actual rate: 14401) + 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency 0x003AF000 Baud19200 - 19200 baud (actual rate: 19208) + 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency 0x004EA000 Baud28800 - 28800 baud (actual rate: 28777) + 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency 0x0075C000 Baud31250 - 31250 baud + 31250 baud when UARTE has 16 MHz peripheral clock frequency 0x00800000 Baud38400 - 38400 baud (actual rate: 38369) + 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency 0x009D0000 Baud56000 - 56000 baud (actual rate: 55944) + 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency 0x00E50000 Baud57600 - 57600 baud (actual rate: 57554) + 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency 0x00EB0000 Baud76800 - 76800 baud (actual rate: 76923) + 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency 0x013A9000 Baud115200 - 115200 baud (actual rate: 115108) + 115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency 0x01D60000 Baud230400 - 230400 baud (actual rate: 231884) + 230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency 0x03B00000 Baud250000 - 250000 baud + 250000 baud when UARTE has 16 MHz peripheral clock frequency 0x04000000 Baud460800 - 460800 baud (actual rate: 457143) + 460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency 0x07400000 Baud921600 - 921600 baud (actual rate: 941176) + 921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency 0x0F000000 Baud1M - 1 megabaud + 1 megabaud when UARTE has 16 MHz peripheral clock frequency 0x10000000 @@ -31511,6 +31511,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Owner ID 4 7 + + + NotEnforced + Owner ID protection is not enforced + 0x0 + + WRITEONCE @@ -31580,7 +31587,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x20 - 0x20 + 0x7 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register @@ -31605,7 +31612,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x4 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TASKS_TRIGGER[n] @@ -31635,7 +31642,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x7 0x4 EVENTS_TRIGGERED[%s] Description collection: VPR event [n] register @@ -31665,7 +31672,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x4 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event EVENTS_TRIGGERED[n] @@ -31702,294 +31709,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x00000000 0x20 - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - TRIGGERED16 Enable or disable interrupt for event TRIGGERED[16] @@ -32116,1487 +31835,19 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - TRIGGERED23 - Enable or disable interrupt for event TRIGGERED[23] - 23 - 23 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED24 - Enable or disable interrupt for event TRIGGERED[24] - 24 - 24 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED25 - Enable or disable interrupt for event TRIGGERED[25] - 25 - 25 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED26 - Enable or disable interrupt for event TRIGGERED[26] - 26 - 26 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED27 - Enable or disable interrupt for event TRIGGERED[27] - 27 - 27 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED28 - Enable or disable interrupt for event TRIGGERED[28] - 28 - 28 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED29 - Enable or disable interrupt for event TRIGGERED[29] - 29 - 29 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED30 - Enable or disable interrupt for event TRIGGERED[30] - 30 - 30 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED31 - Enable or disable interrupt for event TRIGGERED[31] - 31 - 31 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED16 - Write '1' to enable interrupt for event TRIGGERED[16] - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED17 - Write '1' to enable interrupt for event TRIGGERED[17] - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED18 - Write '1' to enable interrupt for event TRIGGERED[18] - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED19 - Write '1' to enable interrupt for event TRIGGERED[19] - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED20 - Write '1' to enable interrupt for event TRIGGERED[20] - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED21 - Write '1' to enable interrupt for event TRIGGERED[21] - 21 - 21 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED22 - Write '1' to enable interrupt for event TRIGGERED[22] - 22 - 22 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED23 - Write '1' to enable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED24 - Write '1' to enable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED25 - Write '1' to enable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED26 - Write '1' to enable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED27 - Write '1' to enable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED28 - Write '1' to enable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED29 - Write '1' to enable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED30 - Write '1' to enable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED31 - Write '1' to enable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + TRIGGERED16 - Write '1' to disable interrupt for event TRIGGERED[16] + Write '1' to enable interrupt for event TRIGGERED[16] 16 16 @@ -33615,15 +31866,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED17 - Write '1' to disable interrupt for event TRIGGERED[17] + Write '1' to enable interrupt for event TRIGGERED[17] 17 17 @@ -33642,15 +31893,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED18 - Write '1' to disable interrupt for event TRIGGERED[18] + Write '1' to enable interrupt for event TRIGGERED[18] 18 18 @@ -33669,15 +31920,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED19 - Write '1' to disable interrupt for event TRIGGERED[19] + Write '1' to enable interrupt for event TRIGGERED[19] 19 19 @@ -33696,15 +31947,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED20 - Write '1' to disable interrupt for event TRIGGERED[20] + Write '1' to enable interrupt for event TRIGGERED[20] 20 20 @@ -33723,15 +31974,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED21 - Write '1' to disable interrupt for event TRIGGERED[21] + Write '1' to enable interrupt for event TRIGGERED[21] 21 21 @@ -33750,15 +32001,15 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable + Set + Enable 0x1 TRIGGERED22 - Write '1' to disable interrupt for event TRIGGERED[22] + Write '1' to enable interrupt for event TRIGGERED[22] 22 22 @@ -33777,71 +32028,27 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Clear - Disable - 0x1 - - - - - TRIGGERED23 - Write '1' to disable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED24 - Write '1' to disable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable + Set + Enable 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - TRIGGERED25 - Write '1' to disable interrupt for event TRIGGERED[25] - 25 - 25 + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -33865,10 +32072,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED26 - Write '1' to disable interrupt for event TRIGGERED[26] - 26 - 26 + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -33892,10 +32099,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED27 - Write '1' to disable interrupt for event TRIGGERED[27] - 27 - 27 + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -33919,10 +32126,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED28 - Write '1' to disable interrupt for event TRIGGERED[28] - 28 - 28 + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -33946,10 +32153,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED29 - Write '1' to disable interrupt for event TRIGGERED[29] - 29 - 29 + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -33973,10 +32180,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED30 - Write '1' to disable interrupt for event TRIGGERED[30] - 30 - 30 + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -34000,10 +32207,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED31 - Write '1' to disable interrupt for event TRIGGERED[31] - 31 - 31 + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -34036,310 +32243,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x00000000 0x20 - - TRIGGERED0 - Read pending status of interrupt for event TRIGGERED[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED1 - Read pending status of interrupt for event TRIGGERED[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED2 - Read pending status of interrupt for event TRIGGERED[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED3 - Read pending status of interrupt for event TRIGGERED[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED4 - Read pending status of interrupt for event TRIGGERED[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED5 - Read pending status of interrupt for event TRIGGERED[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED6 - Read pending status of interrupt for event TRIGGERED[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED7 - Read pending status of interrupt for event TRIGGERED[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED8 - Read pending status of interrupt for event TRIGGERED[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED9 - Read pending status of interrupt for event TRIGGERED[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED10 - Read pending status of interrupt for event TRIGGERED[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED11 - Read pending status of interrupt for event TRIGGERED[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED12 - Read pending status of interrupt for event TRIGGERED[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED13 - Read pending status of interrupt for event TRIGGERED[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED14 - Read pending status of interrupt for event TRIGGERED[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED15 - Read pending status of interrupt for event TRIGGERED[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - TRIGGERED16 Read pending status of interrupt for event TRIGGERED[16] @@ -34473,177 +32376,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - TRIGGERED23 - Read pending status of interrupt for event TRIGGERED[23] - 23 - 23 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED24 - Read pending status of interrupt for event TRIGGERED[24] - 24 - 24 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED25 - Read pending status of interrupt for event TRIGGERED[25] - 25 - 25 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED26 - Read pending status of interrupt for event TRIGGERED[26] - 26 - 26 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED27 - Read pending status of interrupt for event TRIGGERED[27] - 27 - 27 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED28 - Read pending status of interrupt for event TRIGGERED[28] - 28 - 28 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED29 - Read pending status of interrupt for event TRIGGERED[29] - 29 - 29 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED30 - Read pending status of interrupt for event TRIGGERED[30] - 30 - 30 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED31 - Read pending status of interrupt for event TRIGGERED[31] - 31 - 31 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - @@ -50227,14 +47959,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -50866,14 +48590,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -51505,14 +49221,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -52144,14 +49852,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -52231,7 +49931,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Disabled - RADIO is in the Disabled state + RADIO is in the DISABLED state 0x0 @@ -52251,7 +49951,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. RxDisable - RADIO is in the RXDISABLED state + RADIO is in the RXDISABLE state 0x4 @@ -52271,7 +49971,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. TxDisable - RADIO is in the TXDISABLED state + RADIO is in the TXDISABLE state 0xC @@ -52455,7 +50155,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.TXPOWER RADIO output power 0 - 8 + 10 Pos8dBm @@ -53038,15 +50738,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x20 - OFFSET + PTR Data pointer 0 - 15 - - - BASE - 29 - 29 + 31 @@ -54287,21 +51982,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PACKETPTR - Unspecified + Packet pointer 0xED0 read-write 0x00000000 0x20 - OFFSET + PTR + Data pointer 0 - 15 - - - BASE - 29 - 29 + 31 @@ -57814,11 +55505,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.400 kbps 0x06400000 - - K1000 - 1000 kbps - 0x0FF00000 - @@ -64887,7 +62573,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x010 2 - 0x004 + 0x008 SEQ[%s] Peripheral tasks. PWM_TASKS_DMA_SEQ @@ -64916,6 +62602,29 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + @@ -64992,7 +62701,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x090 2 - 0x004 + 0x008 SEQ[%s] Subscribe configuration for tasks PWM_SUBSCRIBE_DMA_SEQ @@ -65031,6 +62740,39 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + @@ -65731,6 +63473,42 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -67871,7 +65649,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. AMOUNT - Description cluster: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. 0x00C read-only 0x00000000 @@ -70464,13 +68242,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -70504,7 +68282,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -74707,7 +72485,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 1st piece wise linear function 0x520 read-write - 0x000002C4 + 0x000002D6 0x20 @@ -74723,7 +72501,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 2nd piece wise linear function 0x524 read-write - 0x000002FB + 0x0000032D 0x20 @@ -74739,7 +72517,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 3rd piece wise linear function 0x528 read-write - 0x00000328 + 0x00000384 0x20 @@ -74755,7 +72533,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 4th piece wise linear function 0x52C read-write - 0x00000377 + 0x000003E9 0x20 @@ -74771,7 +72549,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 5th piece wise linear function 0x530 read-write - 0x000003DD + 0x0000046F 0x20 @@ -74787,7 +72565,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 6th piece wise linear function 0x534 read-write - 0x0000046F + 0x00000522 0x20 @@ -74803,7 +72581,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Slope of 7th piece wise linear function 0x538 read-write - 0x0000055A + 0x000005B7 0x20 @@ -74819,7 +72597,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 1st piece wise linear function 0x540 read-write - 0x00000072 + 0x00000FD6 0x20 @@ -74835,7 +72613,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 2nd piece wise linear function 0x544 read-write - 0x0000000E + 0x00000F76 0x20 @@ -74851,7 +72629,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 3rd piece wise linear function 0x548 read-write - 0x00000FEA + 0x00000F8A 0x20 @@ -74867,7 +72645,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 4th piece wise linear function 0x54C read-write - 0x00000FEA + 0x00000FF8 0x20 @@ -74883,7 +72661,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 5th piece wise linear function 0x550 read-write - 0x0000004A + 0x000000CC 0x20 @@ -74899,7 +72677,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 6th piece wise linear function 0x554 read-write - 0x00000134 + 0x00000207 0x20 @@ -74915,7 +72693,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.y-intercept of 7th piece wise linear function 0x558 read-write - 0x000002C0 + 0x00000558 0x20 @@ -74931,7 +72709,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 1st piece wise linear function 0x560 read-write - 0x000000D8 + 0x000000E2 0x20 @@ -74947,7 +72725,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 2nd piece wise linear function 0x564 read-write - 0x000000EC + 0x00000002 0x20 @@ -74963,7 +72741,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 3rd piece wise linear function 0x568 read-write - 0x000000FF + 0x0000001F 0x20 @@ -74979,7 +72757,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 4th piece wise linear function 0x56C read-write - 0x0000001C + 0x00000038 0x20 @@ -74995,7 +72773,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 5th piece wise linear function 0x570 read-write - 0x0000003C + 0x0000004F 0x20 @@ -75011,7 +72789,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.End point of 6th piece wise linear function 0x574 read-write - 0x00000052 + 0x00000066 0x20 @@ -77019,24 +74797,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - TAMPERSWITCH - External tamper switch detector detected an error. - 1 - 1 - - - NotDetected - Not detected. - 0x0 - - - Detected - Detected. - 0x1 - - - PROTECT Error detected for the protected signals. @@ -77261,764 +75021,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.read-write 0x500 - STRUCT0 + 1 + 0x020 + DOMAIN[%s] Unspecified - TAMPC_PROTECT_STRUCT0 + TAMPC_PROTECT_DOMAIN read-write 0x000 - 1 - 0x020 - DOMAIN[%s] + DBGEN Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN + TAMPC_PROTECT_DOMAIN_DBGEN read-write 0x000 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - NIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_NIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of niden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPIDEN - read-write - 0x010 - - CTRL - Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPNIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPNIDEN - read-write - 0x018 - - CTRL - Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spniden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - 1 - 0x010 - AP[%s] - Unspecified - TAMPC_PROTECT_STRUCT0_AP - read-write - 0x200 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_SPIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register to enable secure priviliged invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - ACTIVESHIELD - Enable active shield detector. - TAMPC_PROTECT_STRUCT0_ACTIVESHIELD - read-write - 0x400 CTRL - Control register for active shield detector enable signal. + Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -78026,7 +75044,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. VALUE - Set value of active shield enable signal. + Set value of dbgen signal. 0 0 @@ -78103,7 +75121,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for active shield detector enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -78132,14 +75150,14 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TAMPERSWITCH - Enable tamper switch detector. - TAMPC_PROTECT_STRUCT0_TAMPERSWITCH + NIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_NIDEN read-write - 0x408 + 0x008 CTRL - Control register for external tamper switch enable signal. + Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -78147,7 +75165,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. VALUE - Set value of tamper switch enable signal. + Set value of niden signal. 0 0 @@ -78224,7 +75242,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for external tamper switch detector enable signal. + Description cluster: Status register for non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -78253,22 +75271,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CRACENTAMP - Enable tamper detector from CRACEN. - TAMPC_PROTECT_STRUCT0_CRACENTAMP + SPIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPIDEN read-write - 0x438 + 0x010 CTRL - Control register for CRACEN tamper detector enable signal. + Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of CRACEN tamper detector enable signal. + Set value of spiden signal. 0 0 @@ -78345,7 +75363,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for CRACEN tamper detector enable signal. + Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -78374,22 +75392,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - GLITCHSLOWDOMAIN - Enable slow domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHSLOWDOMAIN + SPNIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPNIDEN read-write - 0x440 + 0x018 CTRL - Control register for slow domain glitch detectors enable signal. + Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of slow domain glitch detectors enable signal. + Set value of spniden signal. 0 0 @@ -78466,7 +75484,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for slow domain glitch detectors enable signal. + Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -78494,23 +75512,32 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + + 1 + 0x010 + AP[%s] + Unspecified + TAMPC_PROTECT_AP + read-write + 0x200 - GLITCHFASTDOMAIN - Enable fast domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHFASTDOMAIN + DBGEN + Unspecified + TAMPC_PROTECT_AP_DBGEN read-write - 0x448 + 0x000 CTRL - Control register for fast domain glitch detectors enable signal. + Description cluster: Control register to enable invasive (halting) debug in domain n's access port. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of fast domain glitch detector's enable signal. + Set value of dbgen signal. 0 0 @@ -78587,7 +75614,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for fast domain glitch detectors enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n's access port. 0x004 read-write 0x00000000 @@ -78615,369 +75642,853 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - EXTRESETEN - Trigger a reset when tamper is detected by the active shield or tamper switch detector. - TAMPC_PROTECT_STRUCT0_EXTRESETEN + + + ACTIVESHIELD + Enable active shield detector. + TAMPC_PROTECT_ACTIVESHIELD + read-write + 0x400 + + CTRL + Control register for active shield detector enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of active shield enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for active shield detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + CRACENTAMP + Enable tamper detector from CRACEN. + TAMPC_PROTECT_CRACENTAMP + read-write + 0x438 + + CTRL + Control register for CRACEN tamper detector enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of CRACEN tamper detector enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for CRACEN tamper detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHSLOWDOMAIN + Enable slow domain glitch detectors. + TAMPC_PROTECT_GLITCHSLOWDOMAIN + read-write + 0x440 + + CTRL + Control register for slow domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of slow domain glitch detectors enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for slow domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHFASTDOMAIN + Enable fast domain glitch detectors. + TAMPC_PROTECT_GLITCHFASTDOMAIN + read-write + 0x448 + + CTRL + Control register for fast domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of fast domain glitch detector's enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for fast domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + EXTRESETEN + Trigger a reset when tamper is detected by the external tamper detectors. + TAMPC_PROTECT_EXTRESETEN + read-write + 0x470 + + CTRL + Control register for external tamper reset enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of external tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for external tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + INTRESETEN + Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. + TAMPC_PROTECT_INTRESETEN + read-write + 0x478 + + CTRL + Control register for internal tamper reset enable signal. + 0x000 read-write - 0x470 - - CTRL - Control register for external tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of external tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for external tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - INTRESETEN - Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. - TAMPC_PROTECT_STRUCT0_INTRESETEN + 0x00000010 + 0x20 + + + VALUE + Set value of internal tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for internal tamper reset enable signal. + 0x004 read-write - 0x478 - - CTRL - Control register for internal tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of internal tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for internal tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - ERASEPROTECT - Device erase protection. - TAMPC_PROTECT_STRUCT0_ERASEPROTECT + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + ERASEPROTECT + Device erase protection. + TAMPC_PROTECT_ERASEPROTECT + read-write + 0x480 + + CTRL + Control register for erase protection. + 0x000 read-write - 0x480 - - CTRL - Control register for erase protection. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of eraseprotect signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for eraseprotect. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - + 0x00000010 + 0x20 + + + VALUE + Set value of eraseprotect signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for eraseprotect. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + @@ -88472,6 +85983,11 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.GRTC LFCLK clock source is system LFCLK 0x1 + + LFLPRC + GRTC LFCLK clock source is LFLPRC + 0x2 + @@ -95265,7 +92781,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Programmable capacitance of XL1 and XL2 0x004 read-write - 0x00000000 + 0x00000017 0x20 diff --git a/mdk/nrf54l15_application_peripherals.h b/mdk/nrf54l15_application_peripherals.h index b509efe93..c12e4d5ef 100644 --- a/mdk/nrf54l15_application_peripherals.h +++ b/mdk/nrf54l15_application_peripherals.h @@ -40,16 +40,13 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include -/* Domain definition */ -#define NRF_DOMAIN NRF_DOMAIN_APPLICATION - /*CACHEDATA*/ #define CACHEDATA_PRESENT 1 #define CACHEDATA_COUNT 1 -#define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..255 */ -#define ICACHEDATA_NUMSETS_MAX 255 /*!< Number of sets : 0..255 */ -#define ICACHEDATA_NUMSETS_SIZE 256 /*!< Number of sets : 0..255 */ +#define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ #define ICACHEDATA_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ #define ICACHEDATA_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ #define ICACHEDATA_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ @@ -64,9 +61,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHEINFO_PRESENT 1 #define CACHEINFO_COUNT 1 -#define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..255 */ -#define ICACHEINFO_NUMSETS_MAX 255 /*!< Number of sets : 0..255 */ -#define ICACHEINFO_NUMSETS_SIZE 256 /*!< Number of sets : 0..255 */ +#define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ #define ICACHEINFO_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ #define ICACHEINFO_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ #define ICACHEINFO_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ @@ -284,8 +281,8 @@ POSSIBILITY OF SUCH DAMAGE. #define KMU_PRESENT 1 #define KMU_COUNT 1 -#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots */ -#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot */ +#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ +#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ /*Accelerated Address Resolver*/ #define AAR_PRESENT 1 @@ -332,12 +329,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PKEDATA 0x51808000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ -#define CRACEN_PKECODE 0x5180C000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ +#define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ +#define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ /*Serial Peripheral Interface Master with EasyDMA*/ #define SPIM_PRESENT 1 @@ -507,8 +506,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_COUNT 5 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ @@ -517,8 +516,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -527,8 +526,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -537,8 +536,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -547,8 +546,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -659,22 +658,27 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ -#define VPR00_RAM_BASE_ADDR 0x00000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x00000000 */ -#define VPR00_RAM_SZ 0 /*!< VPR RAM size (RAM_SZ): 0 (Value in bytes is computed as 2^(RAM size))*/ +#define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ +#define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM + size))*/ +#define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ +#define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ -#define VPR00_VPRSAVEADDR 0x00000000 /*!< VPR context save address: 0x00000000 */ +#define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ -#define VPR00_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ +#define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ +#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ +#define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ /*GPIO Port*/ @@ -942,7 +946,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_COUNT 1 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ -#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ @@ -996,7 +1000,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ +#define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ /*Inter-IC Sound*/ #define I2S_PRESENT 1 @@ -1037,7 +1043,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GRTC_PWMREGS 1 /*!< (unspecified) */ #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ #define GRTC_CLKSELREG 1 /*!< (unspecified) */ -#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ /*Comparator*/ @@ -1053,8 +1059,10 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_COUNT 2 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT30_HAS_INTEN 0 /*!< (unspecified) */ #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT31_HAS_INTEN 0 /*!< (unspecified) */ /*Clock management*/ #define CLOCK_PRESENT 1 @@ -1080,6 +1088,257 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 + MHz core frequency*/ +} NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; + #ifdef __cplusplus } diff --git a/mdk/nrf54l15_enga_application.h b/mdk/nrf54l15_enga_application.h index ff953f158..acdeed020 100644 --- a/mdk/nrf54l15_enga_application.h +++ b/mdk/nrf54l15_enga_application.h @@ -193,7 +193,7 @@ typedef enum { #define __MPU_PRESENT 1 /*!< MPU present */ #define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_DP 0 /*!< Double Precision FPU */ -#define __INTERRUPTS_MAX 176 /*!< Size of interrupt vector table */ +#define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ #define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ #define __SAUREGION_PRESENT 1 /*!< SAU present */ #define __NUM_SAUREGIONS 4 /*!< Number of regions */ @@ -204,6 +204,14 @@ typedef enum { #endif /*!< NRF_APPLICATION */ +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_CM33 + +#endif /*!< NRF_APPLICATION */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54l15_enga_application.svd b/mdk/nrf54l15_enga_application.svd index 083b462b2..2f82bfc0d 100644 --- a/mdk/nrf54l15_enga_application.svd +++ b/mdk/nrf54l15_enga_application.svd @@ -52,7 +52,7 @@ POSSIBILITY OF SUCH DAMAGE. 1 3 0 - 176 + 270 4 system_nrf54l15_enga_application @@ -1001,7 +1001,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 256 + 128 0x040 SET[%s] Unspecified @@ -1064,7 +1064,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 256 + 128 0x008 SET[%s] Unspecified @@ -12659,7 +12659,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel n of DPPIC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -12708,7 +12708,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel group n of DPPIC 0x060 read-write - 0x00000000 + 0x00100010 0x20 @@ -12756,7 +12756,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x040 GPIOTE[%s] Unspecified - GPIOTE + SPU_FEATURE_GPIOTE read-write 0x100 @@ -12766,7 +12766,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for channel o of GPIOTE[n] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -12815,7 +12815,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for interrupt o of GPIOTE[n] 0x020 read-write - 0x00000000 + 0x00100010 0x20 @@ -12873,7 +12873,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for GPIO[n] PIN[o] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -12928,7 +12928,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration for CRACEN SEED 0x180 read-write - 0x00000000 + 0x00020010 0x20 @@ -12984,7 +12984,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for CC n of GRTC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -13031,7 +13031,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of feature for PWMCONFIG of GRTC 0x074 read-write - 0x00000000 + 0x00100010 0x20 @@ -13078,7 +13078,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of features for CLKOUT/CLKCFG of GRTC 0x078 read-write - 0x00000000 + 0x00100010 0x20 @@ -13125,7 +13125,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC 0x07C read-write - 0x00000000 + 0x00100010 0x20 @@ -13174,7 +13174,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Description collection: Configuration of features for interrupt n of GRTC 0x080 read-write - 0x00000000 + 0x00100010 0x20 @@ -29404,92 +29404,92 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. Baud1200 - 1200 baud (actual rate: 1205) + 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency 0x0004F000 Baud2400 - 2400 baud (actual rate: 2396) + 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency 0x0009D000 Baud4800 - 4800 baud (actual rate: 4808) + 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency 0x0013B000 Baud9600 - 9600 baud (actual rate: 9598) + 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency 0x00275000 Baud14400 - 14400 baud (actual rate: 14401) + 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency 0x003AF000 Baud19200 - 19200 baud (actual rate: 19208) + 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency 0x004EA000 Baud28800 - 28800 baud (actual rate: 28777) + 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency 0x0075C000 Baud31250 - 31250 baud + 31250 baud when UARTE has 16 MHz peripheral clock frequency 0x00800000 Baud38400 - 38400 baud (actual rate: 38369) + 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency 0x009D0000 Baud56000 - 56000 baud (actual rate: 55944) + 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency 0x00E50000 Baud57600 - 57600 baud (actual rate: 57554) + 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency 0x00EB0000 Baud76800 - 76800 baud (actual rate: 76923) + 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency 0x013A9000 Baud115200 - 115200 baud (actual rate: 115108) + 115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency 0x01D60000 Baud230400 - 230400 baud (actual rate: 231884) + 230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency 0x03B00000 Baud250000 - 250000 baud + 250000 baud when UARTE has 16 MHz peripheral clock frequency 0x04000000 Baud460800 - 460800 baud (actual rate: 457143) + 460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency 0x07400000 Baud921600 - 921600 baud (actual rate: 941176) + 921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency 0x0F000000 Baud1M - 1 megabaud + 1 megabaud when UARTE has 16 MHz peripheral clock frequency 0x10000000 @@ -31378,6 +31378,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.Owner ID 4 7 + + + NotEnforced + Owner ID protection is not enforced + 0x0 + + WRITEONCE @@ -31447,7 +31454,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x20 - 0x20 + 0x7 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register @@ -31472,7 +31479,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x4 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TASKS_TRIGGER[n] @@ -31502,7 +31509,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x7 0x4 EVENTS_TRIGGERED[%s] Description collection: VPR event [n] register @@ -31532,7 +31539,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - 0x20 + 0x4 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event EVENTS_TRIGGERED[n] @@ -31569,294 +31576,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x00000000 0x20 - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - TRIGGERED16 Enable or disable interrupt for event TRIGGERED[16] @@ -31983,168 +31702,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - TRIGGERED23 - Enable or disable interrupt for event TRIGGERED[23] - 23 - 23 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED24 - Enable or disable interrupt for event TRIGGERED[24] - 24 - 24 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED25 - Enable or disable interrupt for event TRIGGERED[25] - 25 - 25 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED26 - Enable or disable interrupt for event TRIGGERED[26] - 26 - 26 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED27 - Enable or disable interrupt for event TRIGGERED[27] - 27 - 27 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED28 - Enable or disable interrupt for event TRIGGERED[28] - 28 - 28 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED29 - Enable or disable interrupt for event TRIGGERED[29] - 29 - 29 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED30 - Enable or disable interrupt for event TRIGGERED[30] - 30 - 30 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED31 - Enable or disable interrupt for event TRIGGERED[31] - 31 - 31 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - @@ -32156,64 +31713,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x20 - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -32237,10 +31740,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -32264,10 +31767,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -32291,10 +31794,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -32318,10 +31821,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -32345,10 +31848,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -32372,10 +31875,10 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -32398,11 +31901,21 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -32419,17 +31932,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -32446,17 +31959,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -32473,17 +31986,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -32500,17 +32013,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -32527,17 +32040,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -32554,17 +32067,17 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -32581,1932 +32094,151 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. write - Set - Enable + Clear + Disable 0x1 + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + TRIGGERED16 - Write '1' to enable interrupt for event TRIGGERED[16] + Read pending status of interrupt for event TRIGGERED[16] 16 16 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED17 - Write '1' to enable interrupt for event TRIGGERED[17] + Read pending status of interrupt for event TRIGGERED[17] 17 17 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED18 - Write '1' to enable interrupt for event TRIGGERED[18] + Read pending status of interrupt for event TRIGGERED[18] 18 18 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED19 - Write '1' to enable interrupt for event TRIGGERED[19] + Read pending status of interrupt for event TRIGGERED[19] 19 19 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED20 - Write '1' to enable interrupt for event TRIGGERED[20] + Read pending status of interrupt for event TRIGGERED[20] 20 20 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED21 - Write '1' to enable interrupt for event TRIGGERED[21] + Read pending status of interrupt for event TRIGGERED[21] 21 21 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED22 - Write '1' to enable interrupt for event TRIGGERED[22] + Read pending status of interrupt for event TRIGGERED[22] 22 22 read - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED23 - Write '1' to enable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED24 - Write '1' to enable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED25 - Write '1' to enable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED26 - Write '1' to enable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED27 - Write '1' to enable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED28 - Write '1' to enable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED29 - Write '1' to enable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED30 - Write '1' to enable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED31 - Write '1' to enable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED16 - Write '1' to disable interrupt for event TRIGGERED[16] - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED17 - Write '1' to disable interrupt for event TRIGGERED[17] - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED18 - Write '1' to disable interrupt for event TRIGGERED[18] - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED19 - Write '1' to disable interrupt for event TRIGGERED[19] - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED20 - Write '1' to disable interrupt for event TRIGGERED[20] - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED21 - Write '1' to disable interrupt for event TRIGGERED[21] - 21 - 21 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED22 - Write '1' to disable interrupt for event TRIGGERED[22] - 22 - 22 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED23 - Write '1' to disable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED24 - Write '1' to disable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED25 - Write '1' to disable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED26 - Write '1' to disable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED27 - Write '1' to disable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED28 - Write '1' to disable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED29 - Write '1' to disable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED30 - Write '1' to disable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED31 - Write '1' to disable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - 0x00000000 - 0x20 - - - TRIGGERED0 - Read pending status of interrupt for event TRIGGERED[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED1 - Read pending status of interrupt for event TRIGGERED[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED2 - Read pending status of interrupt for event TRIGGERED[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED3 - Read pending status of interrupt for event TRIGGERED[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED4 - Read pending status of interrupt for event TRIGGERED[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED5 - Read pending status of interrupt for event TRIGGERED[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED6 - Read pending status of interrupt for event TRIGGERED[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED7 - Read pending status of interrupt for event TRIGGERED[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED8 - Read pending status of interrupt for event TRIGGERED[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED9 - Read pending status of interrupt for event TRIGGERED[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED10 - Read pending status of interrupt for event TRIGGERED[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED11 - Read pending status of interrupt for event TRIGGERED[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED12 - Read pending status of interrupt for event TRIGGERED[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED13 - Read pending status of interrupt for event TRIGGERED[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED14 - Read pending status of interrupt for event TRIGGERED[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED15 - Read pending status of interrupt for event TRIGGERED[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED16 - Read pending status of interrupt for event TRIGGERED[16] - 16 - 16 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED17 - Read pending status of interrupt for event TRIGGERED[17] - 17 - 17 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED18 - Read pending status of interrupt for event TRIGGERED[18] - 18 - 18 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED19 - Read pending status of interrupt for event TRIGGERED[19] - 19 - 19 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED20 - Read pending status of interrupt for event TRIGGERED[20] - 20 - 20 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED21 - Read pending status of interrupt for event TRIGGERED[21] - 21 - 21 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED22 - Read pending status of interrupt for event TRIGGERED[22] - 22 - 22 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED23 - Read pending status of interrupt for event TRIGGERED[23] - 23 - 23 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED24 - Read pending status of interrupt for event TRIGGERED[24] - 24 - 24 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED25 - Read pending status of interrupt for event TRIGGERED[25] - 25 - 25 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED26 - Read pending status of interrupt for event TRIGGERED[26] - 26 - 26 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED27 - Read pending status of interrupt for event TRIGGERED[27] - 27 - 27 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED28 - Read pending status of interrupt for event TRIGGERED[28] - 28 - 28 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED29 - Read pending status of interrupt for event TRIGGERED[29] - 29 - 29 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED30 - Read pending status of interrupt for event TRIGGERED[30] - 30 - 30 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED31 - Read pending status of interrupt for event TRIGGERED[31] - 31 - 31 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending + Pending + Read: Pending 0x1 @@ -50094,14 +47826,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -50733,14 +48457,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -51372,14 +49088,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -52011,14 +49719,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -57589,11 +55289,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.400 kbps 0x06400000 - - K1000 - 1000 kbps - 0x0FF00000 - @@ -63030,7 +60725,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x010 2 - 0x004 + 0x008 SEQ[%s] Peripheral tasks. PWM_TASKS_DMA_SEQ @@ -63059,6 +60754,29 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + @@ -63135,7 +60853,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.0x090 2 - 0x004 + 0x008 SEQ[%s] Subscribe configuration for tasks PWM_SUBSCRIBE_DMA_SEQ @@ -63174,6 +60892,39 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + @@ -63874,6 +61625,42 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -66014,7 +63801,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. AMOUNT - Description cluster: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. 0x00C read-only 0x00000000 @@ -68607,13 +66394,13 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -68647,7 +66434,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -75162,24 +72949,6 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - TAMPERSWITCH - External tamper switch detector detected an error. - 1 - 1 - - - NotDetected - Not detected. - 0x0 - - - Detected - Detected. - 0x1 - - - PROTECT Error detected for the protected signals. @@ -75404,764 +73173,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.read-write 0x500 - STRUCT0 + 1 + 0x020 + DOMAIN[%s] Unspecified - TAMPC_PROTECT_STRUCT0 + TAMPC_PROTECT_DOMAIN read-write 0x000 - 1 - 0x020 - DOMAIN[%s] + DBGEN Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN + TAMPC_PROTECT_DOMAIN_DBGEN read-write 0x000 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - NIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_NIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of niden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPIDEN - read-write - 0x010 - - CTRL - Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPNIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPNIDEN - read-write - 0x018 - - CTRL - Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spniden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - 1 - 0x010 - AP[%s] - Unspecified - TAMPC_PROTECT_STRUCT0_AP - read-write - 0x200 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_SPIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register to enable secure priviliged invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - ACTIVESHIELD - Enable active shield detector. - TAMPC_PROTECT_STRUCT0_ACTIVESHIELD - read-write - 0x400 CTRL - Control register for active shield detector enable signal. + Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -76169,7 +73196,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. VALUE - Set value of active shield enable signal. + Set value of dbgen signal. 0 0 @@ -76246,7 +73273,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for active shield detector enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -76275,14 +73302,14 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - TAMPERSWITCH - Enable tamper switch detector. - TAMPC_PROTECT_STRUCT0_TAMPERSWITCH + NIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_NIDEN read-write - 0x408 + 0x008 CTRL - Control register for external tamper switch enable signal. + Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -76290,7 +73317,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. VALUE - Set value of tamper switch enable signal. + Set value of niden signal. 0 0 @@ -76367,7 +73394,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for external tamper switch detector enable signal. + Description cluster: Status register for non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -76396,22 +73423,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - CRACENTAMP - Enable tamper detector from CRACEN. - TAMPC_PROTECT_STRUCT0_CRACENTAMP + SPIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPIDEN read-write - 0x438 + 0x010 CTRL - Control register for CRACEN tamper detector enable signal. + Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of CRACEN tamper detector enable signal. + Set value of spiden signal. 0 0 @@ -76488,7 +73515,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for CRACEN tamper detector enable signal. + Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -76517,22 +73544,22 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - GLITCHSLOWDOMAIN - Enable slow domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHSLOWDOMAIN + SPNIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPNIDEN read-write - 0x440 + 0x018 CTRL - Control register for slow domain glitch detectors enable signal. + Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of slow domain glitch detectors enable signal. + Set value of spniden signal. 0 0 @@ -76609,7 +73636,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for slow domain glitch detectors enable signal. + Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -76637,23 +73664,32 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + + + 1 + 0x010 + AP[%s] + Unspecified + TAMPC_PROTECT_AP + read-write + 0x200 - GLITCHFASTDOMAIN - Enable fast domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHFASTDOMAIN + DBGEN + Unspecified + TAMPC_PROTECT_AP_DBGEN read-write - 0x448 + 0x000 CTRL - Control register for fast domain glitch detectors enable signal. + Description cluster: Control register to enable invasive (halting) debug in domain n's access port. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of fast domain glitch detector's enable signal. + Set value of dbgen signal. 0 0 @@ -76730,7 +73766,7 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. STATUS - Status register for fast domain glitch detectors enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n's access port. 0x004 read-write 0x00000000 @@ -76758,369 +73794,853 @@ unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. - - EXTRESETEN - Trigger a reset when tamper is detected by the active shield or tamper switch detector. - TAMPC_PROTECT_STRUCT0_EXTRESETEN + + + ACTIVESHIELD + Enable active shield detector. + TAMPC_PROTECT_ACTIVESHIELD + read-write + 0x400 + + CTRL + Control register for active shield detector enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of active shield enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for active shield detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + CRACENTAMP + Enable tamper detector from CRACEN. + TAMPC_PROTECT_CRACENTAMP + read-write + 0x438 + + CTRL + Control register for CRACEN tamper detector enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of CRACEN tamper detector enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for CRACEN tamper detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHSLOWDOMAIN + Enable slow domain glitch detectors. + TAMPC_PROTECT_GLITCHSLOWDOMAIN + read-write + 0x440 + + CTRL + Control register for slow domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of slow domain glitch detectors enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for slow domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHFASTDOMAIN + Enable fast domain glitch detectors. + TAMPC_PROTECT_GLITCHFASTDOMAIN + read-write + 0x448 + + CTRL + Control register for fast domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of fast domain glitch detector's enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for fast domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + EXTRESETEN + Trigger a reset when tamper is detected by the external tamper detectors. + TAMPC_PROTECT_EXTRESETEN + read-write + 0x470 + + CTRL + Control register for external tamper reset enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of external tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for external tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + INTRESETEN + Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. + TAMPC_PROTECT_INTRESETEN + read-write + 0x478 + + CTRL + Control register for internal tamper reset enable signal. + 0x000 read-write - 0x470 - - CTRL - Control register for external tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of external tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for external tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - INTRESETEN - Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. - TAMPC_PROTECT_STRUCT0_INTRESETEN + 0x00000010 + 0x20 + + + VALUE + Set value of internal tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for internal tamper reset enable signal. + 0x004 read-write - 0x478 - - CTRL - Control register for internal tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of internal tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for internal tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - ERASEPROTECT - Device erase protection. - TAMPC_PROTECT_STRUCT0_ERASEPROTECT + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + ERASEPROTECT + Device erase protection. + TAMPC_PROTECT_ERASEPROTECT + read-write + 0x480 + + CTRL + Control register for erase protection. + 0x000 read-write - 0x480 - - CTRL - Control register for erase protection. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of eraseprotect signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for eraseprotect. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - + 0x00000010 + 0x20 + + + VALUE + Set value of eraseprotect signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for eraseprotect. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + diff --git a/mdk/nrf54l15_enga_application_peripherals.h b/mdk/nrf54l15_enga_application_peripherals.h index 1964c4eb8..65fc6742d 100644 --- a/mdk/nrf54l15_enga_application_peripherals.h +++ b/mdk/nrf54l15_enga_application_peripherals.h @@ -40,16 +40,13 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include -/* Domain definition */ -#define NRF_DOMAIN NRF_DOMAIN_APPLICATION - /*CACHEDATA*/ #define CACHEDATA_PRESENT 1 #define CACHEDATA_COUNT 1 -#define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..255 */ -#define ICACHEDATA_NUMSETS_MAX 255 /*!< Number of sets : 0..255 */ -#define ICACHEDATA_NUMSETS_SIZE 256 /*!< Number of sets : 0..255 */ +#define ICACHEDATA_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEDATA_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ #define ICACHEDATA_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ #define ICACHEDATA_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ #define ICACHEDATA_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ @@ -64,9 +61,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHEINFO_PRESENT 1 #define CACHEINFO_COUNT 1 -#define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..255 */ -#define ICACHEINFO_NUMSETS_MAX 255 /*!< Number of sets : 0..255 */ -#define ICACHEINFO_NUMSETS_SIZE 256 /*!< Number of sets : 0..255 */ +#define ICACHEINFO_NUMSETS_MIN 0 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_MAX 127 /*!< Number of sets : 0..127 */ +#define ICACHEINFO_NUMSETS_SIZE 128 /*!< Number of sets : 0..127 */ #define ICACHEINFO_NUMWAYS_MIN 0 /*!< Number of ways : 0..1 */ #define ICACHEINFO_NUMWAYS_MAX 1 /*!< Number of ways : 0..1 */ #define ICACHEINFO_NUMWAYS_SIZE 2 /*!< Number of ways : 0..1 */ @@ -284,8 +281,8 @@ POSSIBILITY OF SUCH DAMAGE. #define KMU_PRESENT 1 #define KMU_COUNT 1 -#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots */ -#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot */ +#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ +#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ /*Accelerated Address Resolver*/ #define AAR_PRESENT 1 @@ -332,12 +329,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PKEDATA 0x51808000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ -#define CRACEN_PKECODE 0x5180C000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ +#define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ +#define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ /*Serial Peripheral Interface Master with EasyDMA*/ #define SPIM_PRESENT 1 @@ -507,8 +506,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_COUNT 5 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ @@ -517,8 +516,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -527,8 +526,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -537,8 +536,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -547,8 +546,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -659,22 +658,27 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ -#define VPR00_RAM_BASE_ADDR 0x00000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x00000000 */ -#define VPR00_RAM_SZ 0 /*!< VPR RAM size (RAM_SZ): 0 (Value in bytes is computed as 2^(RAM size))*/ +#define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ +#define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM + size))*/ +#define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ +#define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ -#define VPR00_VPRSAVEADDR 0x00000000 /*!< VPR context save address: 0x00000000 */ +#define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ -#define VPR00_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ +#define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ +#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ +#define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ /*GPIO Port*/ @@ -925,7 +929,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_COUNT 1 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ -#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ @@ -979,7 +983,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ +#define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ /*Inter-IC Sound*/ #define I2S_PRESENT 1 @@ -1036,8 +1042,10 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_COUNT 2 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT30_HAS_INTEN 0 /*!< (unspecified) */ #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT31_HAS_INTEN 0 /*!< (unspecified) */ /*Clock management*/ #define CLOCK_PRESENT 1 @@ -1063,6 +1071,257 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 + MHz core frequency*/ +} NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; + #ifdef __cplusplus } diff --git a/mdk/nrf54l15_enga_flpr.h b/mdk/nrf54l15_enga_flpr.h index 6609596ce..9811a1931 100644 --- a/mdk/nrf54l15_enga_flpr.h +++ b/mdk/nrf54l15_enga_flpr.h @@ -201,6 +201,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -209,12 +212,21 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR00 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54l15_enga_flpr System Library */ #endif /*!< NRF_FLPR */ +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_VPR + +#endif /*!< NRF_FLPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54l15_enga_flpr.svd b/mdk/nrf54l15_enga_flpr.svd index 3cb5fada8..7e17d5ae0 100644 --- a/mdk/nrf54l15_enga_flpr.svd +++ b/mdk/nrf54l15_enga_flpr.svd @@ -3365,7 +3365,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x1E0 + 0x10F 0x4 CLICINT[%s] Description collection: Interrupt control register for IRQ number [n]. @@ -3865,7 +3865,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel n of DPPIC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -3914,7 +3914,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel group n of DPPIC 0x060 read-write - 0x00000000 + 0x00100010 0x20 @@ -3962,7 +3962,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x040 GPIOTE[%s] Unspecified - GPIOTE + SPU_FEATURE_GPIOTE read-write 0x100 @@ -3972,7 +3972,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel o of GPIOTE[n] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4021,7 +4021,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for interrupt o of GPIOTE[n] 0x020 read-write - 0x00000000 + 0x00100010 0x20 @@ -4079,7 +4079,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for GPIO[n] PIN[o] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4134,7 +4134,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration for CRACEN SEED 0x180 read-write - 0x00000000 + 0x00020010 0x20 @@ -4190,7 +4190,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for CC n of GRTC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4237,7 +4237,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of feature for PWMCONFIG of GRTC 0x074 read-write - 0x00000000 + 0x00100010 0x20 @@ -4284,7 +4284,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of features for CLKOUT/CLKCFG of GRTC 0x078 read-write - 0x00000000 + 0x00100010 0x20 @@ -4331,7 +4331,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC 0x07C read-write - 0x00000000 + 0x00100010 0x20 @@ -4380,7 +4380,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for interrupt n of GRTC 0x080 read-write - 0x00000000 + 0x00100010 0x20 @@ -20610,92 +20610,92 @@ POSSIBILITY OF SUCH DAMAGE. Baud1200 - 1200 baud (actual rate: 1205) + 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency 0x0004F000 Baud2400 - 2400 baud (actual rate: 2396) + 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency 0x0009D000 Baud4800 - 4800 baud (actual rate: 4808) + 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency 0x0013B000 Baud9600 - 9600 baud (actual rate: 9598) + 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency 0x00275000 Baud14400 - 14400 baud (actual rate: 14401) + 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency 0x003AF000 Baud19200 - 19200 baud (actual rate: 19208) + 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency 0x004EA000 Baud28800 - 28800 baud (actual rate: 28777) + 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency 0x0075C000 Baud31250 - 31250 baud + 31250 baud when UARTE has 16 MHz peripheral clock frequency 0x00800000 Baud38400 - 38400 baud (actual rate: 38369) + 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency 0x009D0000 Baud56000 - 56000 baud (actual rate: 55944) + 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency 0x00E50000 Baud57600 - 57600 baud (actual rate: 57554) + 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency 0x00EB0000 Baud76800 - 76800 baud (actual rate: 76923) + 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency 0x013A9000 Baud115200 - 115200 baud (actual rate: 115108) + 115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency 0x01D60000 Baud230400 - 230400 baud (actual rate: 231884) + 230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency 0x03B00000 Baud250000 - 250000 baud + 250000 baud when UARTE has 16 MHz peripheral clock frequency 0x04000000 Baud460800 - 460800 baud (actual rate: 457143) + 460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency 0x07400000 Baud921600 - 921600 baud (actual rate: 941176) + 921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency 0x0F000000 Baud1M - 1 megabaud + 1 megabaud when UARTE has 16 MHz peripheral clock frequency 0x10000000 @@ -22584,6 +22584,13 @@ POSSIBILITY OF SUCH DAMAGE. Owner ID 4 7 + + + NotEnforced + Owner ID protection is not enforced + 0x0 + + WRITEONCE @@ -22653,7 +22660,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 0x20 + 0x7 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register @@ -22678,7 +22685,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x4 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TASKS_TRIGGER[n] @@ -22708,7 +22715,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x7 0x4 EVENTS_TRIGGERED[%s] Description collection: VPR event [n] register @@ -22738,7 +22745,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x4 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event EVENTS_TRIGGERED[n] @@ -22775,294 +22782,6 @@ POSSIBILITY OF SUCH DAMAGE. 0x00000000 0x20 - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - TRIGGERED16 Enable or disable interrupt for event TRIGGERED[16] @@ -23189,168 +22908,6 @@ POSSIBILITY OF SUCH DAMAGE. - - TRIGGERED23 - Enable or disable interrupt for event TRIGGERED[23] - 23 - 23 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED24 - Enable or disable interrupt for event TRIGGERED[24] - 24 - 24 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED25 - Enable or disable interrupt for event TRIGGERED[25] - 25 - 25 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED26 - Enable or disable interrupt for event TRIGGERED[26] - 26 - 26 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED27 - Enable or disable interrupt for event TRIGGERED[27] - 27 - 27 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED28 - Enable or disable interrupt for event TRIGGERED[28] - 28 - 28 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED29 - Enable or disable interrupt for event TRIGGERED[29] - 29 - 29 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED30 - Enable or disable interrupt for event TRIGGERED[30] - 30 - 30 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED31 - Enable or disable interrupt for event TRIGGERED[31] - 31 - 31 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - @@ -23362,64 +22919,10 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -23443,10 +22946,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -23470,10 +22973,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -23497,10 +23000,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -23524,10 +23027,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -23551,10 +23054,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -23578,10 +23081,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -23604,11 +23107,21 @@ POSSIBILITY OF SUCH DAMAGE. + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -23625,17 +23138,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -23652,17 +23165,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -23679,17 +23192,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -23706,17 +23219,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -23733,17 +23246,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -23760,17 +23273,17 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -23787,1932 +23300,151 @@ POSSIBILITY OF SUCH DAMAGE. write - Set - Enable + Clear + Disable 0x1 + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + TRIGGERED16 - Write '1' to enable interrupt for event TRIGGERED[16] + Read pending status of interrupt for event TRIGGERED[16] 16 16 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED17 - Write '1' to enable interrupt for event TRIGGERED[17] + Read pending status of interrupt for event TRIGGERED[17] 17 17 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED18 - Write '1' to enable interrupt for event TRIGGERED[18] + Read pending status of interrupt for event TRIGGERED[18] 18 18 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED19 - Write '1' to enable interrupt for event TRIGGERED[19] + Read pending status of interrupt for event TRIGGERED[19] 19 19 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED20 - Write '1' to enable interrupt for event TRIGGERED[20] + Read pending status of interrupt for event TRIGGERED[20] 20 20 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED21 - Write '1' to enable interrupt for event TRIGGERED[21] + Read pending status of interrupt for event TRIGGERED[21] 21 21 read - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable + Pending + Read: Pending 0x1 TRIGGERED22 - Write '1' to enable interrupt for event TRIGGERED[22] + Read pending status of interrupt for event TRIGGERED[22] 22 22 read - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED23 - Write '1' to enable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled + NotPending + Read: Not pending 0x0 - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED24 - Write '1' to enable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED25 - Write '1' to enable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED26 - Write '1' to enable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED27 - Write '1' to enable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED28 - Write '1' to enable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED29 - Write '1' to enable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED30 - Write '1' to enable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED31 - Write '1' to enable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED16 - Write '1' to disable interrupt for event TRIGGERED[16] - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED17 - Write '1' to disable interrupt for event TRIGGERED[17] - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED18 - Write '1' to disable interrupt for event TRIGGERED[18] - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED19 - Write '1' to disable interrupt for event TRIGGERED[19] - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED20 - Write '1' to disable interrupt for event TRIGGERED[20] - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED21 - Write '1' to disable interrupt for event TRIGGERED[21] - 21 - 21 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED22 - Write '1' to disable interrupt for event TRIGGERED[22] - 22 - 22 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED23 - Write '1' to disable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED24 - Write '1' to disable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED25 - Write '1' to disable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED26 - Write '1' to disable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED27 - Write '1' to disable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED28 - Write '1' to disable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED29 - Write '1' to disable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED30 - Write '1' to disable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED31 - Write '1' to disable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - - - INTPEND - Pending interrupts - 0x30C - read-only - 0x00000000 - 0x20 - - - TRIGGERED0 - Read pending status of interrupt for event TRIGGERED[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED1 - Read pending status of interrupt for event TRIGGERED[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED2 - Read pending status of interrupt for event TRIGGERED[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED3 - Read pending status of interrupt for event TRIGGERED[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED4 - Read pending status of interrupt for event TRIGGERED[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED5 - Read pending status of interrupt for event TRIGGERED[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED6 - Read pending status of interrupt for event TRIGGERED[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED7 - Read pending status of interrupt for event TRIGGERED[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED8 - Read pending status of interrupt for event TRIGGERED[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED9 - Read pending status of interrupt for event TRIGGERED[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED10 - Read pending status of interrupt for event TRIGGERED[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED11 - Read pending status of interrupt for event TRIGGERED[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED12 - Read pending status of interrupt for event TRIGGERED[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED13 - Read pending status of interrupt for event TRIGGERED[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED14 - Read pending status of interrupt for event TRIGGERED[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED15 - Read pending status of interrupt for event TRIGGERED[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED16 - Read pending status of interrupt for event TRIGGERED[16] - 16 - 16 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED17 - Read pending status of interrupt for event TRIGGERED[17] - 17 - 17 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED18 - Read pending status of interrupt for event TRIGGERED[18] - 18 - 18 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED19 - Read pending status of interrupt for event TRIGGERED[19] - 19 - 19 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED20 - Read pending status of interrupt for event TRIGGERED[20] - 20 - 20 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED21 - Read pending status of interrupt for event TRIGGERED[21] - 21 - 21 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED22 - Read pending status of interrupt for event TRIGGERED[22] - 22 - 22 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED23 - Read pending status of interrupt for event TRIGGERED[23] - 23 - 23 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED24 - Read pending status of interrupt for event TRIGGERED[24] - 24 - 24 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED25 - Read pending status of interrupt for event TRIGGERED[25] - 25 - 25 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED26 - Read pending status of interrupt for event TRIGGERED[26] - 26 - 26 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED27 - Read pending status of interrupt for event TRIGGERED[27] - 27 - 27 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED28 - Read pending status of interrupt for event TRIGGERED[28] - 28 - 28 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED29 - Read pending status of interrupt for event TRIGGERED[29] - 29 - 29 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED30 - Read pending status of interrupt for event TRIGGERED[30] - 30 - 30 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED31 - Read pending status of interrupt for event TRIGGERED[31] - 31 - 31 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending + Pending + Read: Pending 0x1 @@ -41300,14 +39032,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -41939,14 +39663,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -42578,14 +40294,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -43217,14 +40925,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -48795,11 +46495,6 @@ POSSIBILITY OF SUCH DAMAGE. 400 kbps 0x06400000 - - K1000 - 1000 kbps - 0x0FF00000 - @@ -54236,7 +51931,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x010 2 - 0x004 + 0x008 SEQ[%s] Peripheral tasks. PWM_TASKS_DMA_SEQ @@ -54265,6 +51960,29 @@ POSSIBILITY OF SUCH DAMAGE. + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + @@ -54341,7 +52059,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x090 2 - 0x004 + 0x008 SEQ[%s] Subscribe configuration for tasks PWM_SUBSCRIBE_DMA_SEQ @@ -54380,6 +52098,39 @@ POSSIBILITY OF SUCH DAMAGE. + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + @@ -55080,6 +52831,42 @@ POSSIBILITY OF SUCH DAMAGE. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -57220,7 +55007,7 @@ POSSIBILITY OF SUCH DAMAGE. AMOUNT - Description cluster: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. 0x00C read-only 0x00000000 @@ -59813,13 +57600,13 @@ POSSIBILITY OF SUCH DAMAGE. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -59853,7 +57640,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -66368,24 +64155,6 @@ POSSIBILITY OF SUCH DAMAGE. - - TAMPERSWITCH - External tamper switch detector detected an error. - 1 - 1 - - - NotDetected - Not detected. - 0x0 - - - Detected - Detected. - 0x1 - - - PROTECT Error detected for the protected signals. @@ -66610,764 +64379,22 @@ POSSIBILITY OF SUCH DAMAGE. read-write 0x500 - STRUCT0 + 1 + 0x020 + DOMAIN[%s] Unspecified - TAMPC_PROTECT_STRUCT0 + TAMPC_PROTECT_DOMAIN read-write 0x000 - 1 - 0x020 - DOMAIN[%s] + DBGEN Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN + TAMPC_PROTECT_DOMAIN_DBGEN read-write 0x000 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - NIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_NIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of niden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPIDEN - read-write - 0x010 - - CTRL - Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPNIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPNIDEN - read-write - 0x018 - - CTRL - Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spniden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - 1 - 0x010 - AP[%s] - Unspecified - TAMPC_PROTECT_STRUCT0_AP - read-write - 0x200 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_SPIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register to enable secure priviliged invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - ACTIVESHIELD - Enable active shield detector. - TAMPC_PROTECT_STRUCT0_ACTIVESHIELD - read-write - 0x400 CTRL - Control register for active shield detector enable signal. + Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -67375,7 +64402,7 @@ POSSIBILITY OF SUCH DAMAGE. VALUE - Set value of active shield enable signal. + Set value of dbgen signal. 0 0 @@ -67452,7 +64479,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for active shield detector enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -67481,14 +64508,14 @@ POSSIBILITY OF SUCH DAMAGE. - TAMPERSWITCH - Enable tamper switch detector. - TAMPC_PROTECT_STRUCT0_TAMPERSWITCH + NIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_NIDEN read-write - 0x408 + 0x008 CTRL - Control register for external tamper switch enable signal. + Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -67496,7 +64523,7 @@ POSSIBILITY OF SUCH DAMAGE. VALUE - Set value of tamper switch enable signal. + Set value of niden signal. 0 0 @@ -67573,7 +64600,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for external tamper switch detector enable signal. + Description cluster: Status register for non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -67602,22 +64629,22 @@ POSSIBILITY OF SUCH DAMAGE. - CRACENTAMP - Enable tamper detector from CRACEN. - TAMPC_PROTECT_STRUCT0_CRACENTAMP + SPIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPIDEN read-write - 0x438 + 0x010 CTRL - Control register for CRACEN tamper detector enable signal. + Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of CRACEN tamper detector enable signal. + Set value of spiden signal. 0 0 @@ -67694,7 +64721,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for CRACEN tamper detector enable signal. + Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -67723,22 +64750,22 @@ POSSIBILITY OF SUCH DAMAGE. - GLITCHSLOWDOMAIN - Enable slow domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHSLOWDOMAIN + SPNIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPNIDEN read-write - 0x440 + 0x018 CTRL - Control register for slow domain glitch detectors enable signal. + Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of slow domain glitch detectors enable signal. + Set value of spniden signal. 0 0 @@ -67815,7 +64842,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for slow domain glitch detectors enable signal. + Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -67843,23 +64870,32 @@ POSSIBILITY OF SUCH DAMAGE. + + + 1 + 0x010 + AP[%s] + Unspecified + TAMPC_PROTECT_AP + read-write + 0x200 - GLITCHFASTDOMAIN - Enable fast domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHFASTDOMAIN + DBGEN + Unspecified + TAMPC_PROTECT_AP_DBGEN read-write - 0x448 + 0x000 CTRL - Control register for fast domain glitch detectors enable signal. + Description cluster: Control register to enable invasive (halting) debug in domain n's access port. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of fast domain glitch detector's enable signal. + Set value of dbgen signal. 0 0 @@ -67936,7 +64972,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for fast domain glitch detectors enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n's access port. 0x004 read-write 0x00000000 @@ -67964,369 +65000,853 @@ POSSIBILITY OF SUCH DAMAGE. - - EXTRESETEN - Trigger a reset when tamper is detected by the active shield or tamper switch detector. - TAMPC_PROTECT_STRUCT0_EXTRESETEN + + + ACTIVESHIELD + Enable active shield detector. + TAMPC_PROTECT_ACTIVESHIELD + read-write + 0x400 + + CTRL + Control register for active shield detector enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of active shield enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for active shield detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + CRACENTAMP + Enable tamper detector from CRACEN. + TAMPC_PROTECT_CRACENTAMP + read-write + 0x438 + + CTRL + Control register for CRACEN tamper detector enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of CRACEN tamper detector enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for CRACEN tamper detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHSLOWDOMAIN + Enable slow domain glitch detectors. + TAMPC_PROTECT_GLITCHSLOWDOMAIN + read-write + 0x440 + + CTRL + Control register for slow domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of slow domain glitch detectors enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for slow domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHFASTDOMAIN + Enable fast domain glitch detectors. + TAMPC_PROTECT_GLITCHFASTDOMAIN + read-write + 0x448 + + CTRL + Control register for fast domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of fast domain glitch detector's enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for fast domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + EXTRESETEN + Trigger a reset when tamper is detected by the external tamper detectors. + TAMPC_PROTECT_EXTRESETEN + read-write + 0x470 + + CTRL + Control register for external tamper reset enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of external tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for external tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + INTRESETEN + Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. + TAMPC_PROTECT_INTRESETEN + read-write + 0x478 + + CTRL + Control register for internal tamper reset enable signal. + 0x000 read-write - 0x470 - - CTRL - Control register for external tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of external tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for external tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - INTRESETEN - Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. - TAMPC_PROTECT_STRUCT0_INTRESETEN + 0x00000010 + 0x20 + + + VALUE + Set value of internal tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for internal tamper reset enable signal. + 0x004 read-write - 0x478 - - CTRL - Control register for internal tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of internal tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for internal tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - ERASEPROTECT - Device erase protection. - TAMPC_PROTECT_STRUCT0_ERASEPROTECT + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + ERASEPROTECT + Device erase protection. + TAMPC_PROTECT_ERASEPROTECT + read-write + 0x480 + + CTRL + Control register for erase protection. + 0x000 read-write - 0x480 - - CTRL - Control register for erase protection. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of eraseprotect signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for eraseprotect. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - + 0x00000010 + 0x20 + + + VALUE + Set value of eraseprotect signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for eraseprotect. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + diff --git a/mdk/nrf54l15_enga_flpr_peripherals.h b/mdk/nrf54l15_enga_flpr_peripherals.h index 06b2002bb..72e7b9af8 100644 --- a/mdk/nrf54l15_enga_flpr_peripherals.h +++ b/mdk/nrf54l15_enga_flpr_peripherals.h @@ -40,34 +40,33 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include -/* Domain definition */ -#define NRF_DOMAIN NRF_DOMAIN_FLPR - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 -#define VPRCSR_HARTNUM 0 /*!< HARTNUM: 0 */ -#define VPRCSR_MCLICBASERESET 0x00001000 /*!< MCLICBASE: 0x00001000 */ +#define VPRCSR_HARTNUM 14 /*!< HARTNUM: 14 */ +#define VPRCSR_MCLICBASERESET 0xF0000000 /*!< MCLICBASE: 0xF0000000 */ #define VPRCSR_MULDIV 2 /*!< MULDIV: 2 */ #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ #define VPRCSR_DBG 1 /*!< DBG: 1 */ -#define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ +#define VPRCSR_REMAP 1 /*!< Code patching (REMAP): 1 */ #define VPRCSR_BUSWIDTH 64 /*!< BUSWIDTH: 64 */ -#define VPRCSR_BKPT 2 /*!< BKPT: 2 */ -#define VPRCSR_VIOPINS 0x00000000 /*!< CSR VIOPINS value: 0x00000000 */ +#define VPRCSR_BKPT 1 /*!< BKPT: 1 */ +#define VPRCSR_RETAINED 1 /*!< (unspecified) */ +#define VPRCSR_VIOPINS 0x0000FFFF /*!< CSR VIOPINS value: 0x0000FFFF */ #define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPRCSR_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPRCSR_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ +#define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPRCSR_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPRCSR_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ #define VPRCSR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ -#define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ +#define VPRCSR_BEXT 1 /*!< Bit-Manipulation extension: 1 */ #define VPRCSR_CACHE_EN 1 /*!< (unspecified) */ +#define VPRCSR_CACHEEXTRATAGBUF 0 /*!< CACHEEXTRATAGBUF: 0 */ #define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ #define VPRCSR_VPR_BUS_PRIO 1 /*!< (unspecified) */ #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ @@ -77,9 +76,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLIC_COUNT 1 #define VPRCLIC_IRQ_COUNT 32 -#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ -#define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ -#define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..270 */ +#define VPRCLIC_IRQNUM_MAX 270 /*!< Supported interrupts (IRQNUM): 0..270 */ +#define VPRCLIC_IRQNUM_SIZE 271 /*!< Supported interrupts (IRQNUM): 0..270 */ #define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ #define VPRCLIC_CLIC_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ #define VPRCLIC_CLIC_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ @@ -262,8 +261,8 @@ POSSIBILITY OF SUCH DAMAGE. #define KMU_PRESENT 1 #define KMU_COUNT 1 -#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots */ -#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot */ +#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ +#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ /*Accelerated Address Resolver*/ #define AAR_PRESENT 1 @@ -310,12 +309,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PKEDATA 0x51808000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ -#define CRACEN_PKECODE 0x5180C000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ +#define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ +#define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ /*Serial Peripheral Interface Master with EasyDMA*/ #define SPIM_PRESENT 1 @@ -485,8 +486,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_COUNT 5 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ @@ -495,8 +496,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -505,8 +506,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -515,8 +516,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -525,8 +526,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -637,22 +638,27 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ -#define VPR00_RAM_BASE_ADDR 0x00000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x00000000 */ -#define VPR00_RAM_SZ 0 /*!< VPR RAM size (RAM_SZ): 0 (Value in bytes is computed as 2^(RAM size))*/ +#define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ +#define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM + size))*/ +#define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ +#define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ -#define VPR00_VPRSAVEADDR 0x00000000 /*!< VPR context save address: 0x00000000 */ +#define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ -#define VPR00_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ +#define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ +#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ +#define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ /*GPIO Port*/ @@ -903,7 +909,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_COUNT 1 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ -#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ @@ -957,7 +963,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ +#define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ /*Inter-IC Sound*/ #define I2S_PRESENT 1 @@ -1014,8 +1022,10 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_COUNT 2 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT30_HAS_INTEN 0 /*!< (unspecified) */ #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT31_HAS_INTEN 0 /*!< (unspecified) */ /*Clock management*/ #define CLOCK_PRESENT 1 @@ -1041,6 +1051,257 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 + MHz core frequency*/ +} NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; + #ifdef __cplusplus } diff --git a/mdk/nrf54l15_enga_interim.h b/mdk/nrf54l15_enga_interim.h index 952039287..cc9f9f7b6 100644 --- a/mdk/nrf54l15_enga_interim.h +++ b/mdk/nrf54l15_enga_interim.h @@ -38,18 +38,11 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(NRF54L15_ENGA_XXAA) - #define NRF_DOMAIN_COUNT NRF_DOMAIN_GLOBAL + 1 + #define NRF_DOMAIN_COUNT NRF_DOMAIN_NONE + 1 #define ADDRESS_BUS_Pos (18UL) #define ADDRESS_BUS_Msk (0x3FUL << ADDRESS_BUS_Pos) - typedef enum { - NRF_OWNER_NONE = 0, - NRF_OWNER_APPLICATION = 1, - NRF_OWNER_KMU = 2, - } NRF_OWNERID_Type; - - #define NRF_DOMAINS_t NRF_DOMAINID_Type #define PPIB00_CH_NUM 8 #define PPIB10_CH_NUM 8 diff --git a/mdk/nrf54l15_enga_peripherals.h b/mdk/nrf54l15_enga_peripherals.h index 2a7a4b3a8..fcff75cdb 100644 --- a/mdk/nrf54l15_enga_peripherals.h +++ b/mdk/nrf54l15_enga_peripherals.h @@ -39,20 +39,6 @@ POSSIBILITY OF SUCH DAMAGE. extern "C" { #endif -/* Domain IDs */ - typedef enum { - NRF_DOMAIN_APPLICATION = 1, - NRF_DOMAIN_FLPR = 2, - NRF_DOMAIN_GLOBAL = 3, -} NRF_DOMAINID_Type; - -/* Processor IDs */ - typedef enum { - NRF_PROCESSOR_APPLICATION = 1, - NRF_PROCESSOR_FLPR = 2, - NRF_PROCESSOR_GLOBAL = 3, -} NRF_PROCESSORID_Type; - #if defined(NRF_APPLICATION) #include "nrf54l15_enga_application_peripherals.h" #elif defined(NRF_FLPR) diff --git a/mdk/nrf54l15_enga_types.h b/mdk/nrf54l15_enga_types.h index af297e048..4813b6262 100644 --- a/mdk/nrf54l15_enga_types.h +++ b/mdk/nrf54l15_enga_types.h @@ -70,6 +70,33 @@ POSSIBILITY OF SUCH DAMAGE. #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ #endif +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_NONE = 0, /*!< No domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_CM33 = 1, /*!< (unspecified) */ + NRF_PROCESSOR_VPR = 2, /*!< (unspecified) */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 1, /*!< Application Core */ + NRF_OWNER_KMU = 2, /*!< KMU Accesses */ +} NRF_OWNERID_Type; + /* ========================================= Start of section using anonymous unions ========================================= */ @@ -758,17 +785,17 @@ typedef struct { typedef struct { __IOM NRF_CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ } NRF_CACHEDATA_SET_Type; /*!< Size = 64 (0x040) */ - #define CACHEDATA_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ - #define CACHEDATA_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ - #define CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + #define CACHEDATA_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEDATA_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ /* ==================================================== Struct CACHEDATA ===================================================== */ /** * @brief CACHEDATA */ typedef struct { /*!< CACHEDATA Structure */ - __IOM NRF_CACHEDATA_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CACHEDATA_Type; /*!< Size = 16384 (0x4000) */ + __IOM NRF_CACHEDATA_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEDATA_Type; /*!< Size = 8192 (0x2000) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -853,17 +880,17 @@ typedef struct { typedef struct { __IOM NRF_CACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ } NRF_CACHEINFO_SET_Type; /*!< Size = 8 (0x008) */ - #define CACHEINFO_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ - #define CACHEINFO_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ - #define CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + #define CACHEINFO_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEINFO_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ /* ==================================================== Struct CACHEINFO ===================================================== */ /** * @brief CACHEINFO */ typedef struct { /*!< CACHEINFO Structure */ - __IOM NRF_CACHEINFO_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CACHEINFO_Type; /*!< Size = 2048 (0x800) */ + __IOM NRF_CACHEINFO_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEINFO_Type; /*!< Size = 1024 (0x400) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -1323,8 +1350,8 @@ typedef struct { __IM uint32_t CLICCFG; /*!< (@ 0x00000000) CLIC configuration. */ __IM uint32_t CLICINFO; /*!< (@ 0x00000004) CLIC information. */ __IM uint32_t RESERVED[1022]; - __IOM uint32_t CLICINT[480]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ -} NRF_CLIC_CLIC_Type; /*!< Size = 6016 (0x1780) */ + __IOM uint32_t CLICINT[271]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ +} NRF_CLIC_CLIC_Type; /*!< Size = 5180 (0x143C) */ /* CLIC_CLIC_CLICCFG: CLIC configuration. */ #define CLIC_CLIC_CLICCFG_ResetValue (0x00000011UL) /*!< Reset value of CLICCFG register. */ @@ -1369,10 +1396,10 @@ typedef struct { /* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */ - #define CLIC_CLIC_CLICINT_MaxCount (480UL) /*!< Max size of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_MaxIndex (479UL) /*!< Max index of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[480] register. */ + #define CLIC_CLIC_CLICINT_MaxCount (271UL) /*!< Max size of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MaxIndex (270UL) /*!< Max index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[271] register. */ /* IP @Bit 0 : Interrupt Pending bit. */ #define CLIC_CLIC_CLICINT_IP_Pos (0UL) /*!< Position of IP field. */ @@ -1436,7 +1463,7 @@ typedef struct { */ typedef struct { /*!< CLIC Structure */ __IOM NRF_CLIC_CLIC_Type CLIC; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CLIC_Type; /*!< Size = 6016 (0x1780) */ + } NRF_CLIC_Type; /*!< Size = 5180 (0x143C) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -12784,16 +12811,7 @@ typedef struct { typedef struct { __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ } NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ #define GRTC_CC_MaxCount (12UL) /*!< Size of CC[12] array. */ @@ -21062,7 +21080,9 @@ typedef struct { typedef struct { __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.*/ -} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 4 (0x004) */ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ #define PWM_TASKS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ #define PWM_TASKS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ #define PWM_TASKS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ @@ -21080,6 +21100,17 @@ typedef struct { #define PWM_TASKS_DMA_SEQ_START_START_Trigger (0x1UL) /*!< Trigger task */ +/* PWM_TASKS_DMA_SEQ_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Msk (0x1UL << PWM_TASKS_DMA_SEQ_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + /* ================================================== Struct PWM_TASKS_DMA =================================================== */ /** @@ -21087,7 +21118,7 @@ typedef struct { */ typedef struct { __OM NRF_PWM_TASKS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral tasks. */ -} NRF_PWM_TASKS_DMA_Type; /*!< Size = 8 (0x008) */ +} NRF_PWM_TASKS_DMA_Type; /*!< Size = 16 (0x010) */ /* ============================================== Struct PWM_SUBSCRIBE_DMA_SEQ =============================================== */ @@ -21096,7 +21127,8 @@ typedef struct { */ typedef struct { __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ -} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 4 (0x004) */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ #define PWM_SUBSCRIBE_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ #define PWM_SUBSCRIBE_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ #define PWM_SUBSCRIBE_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ @@ -21119,6 +21151,24 @@ typedef struct { #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Enabled (0x1UL) /*!< Enable subscription */ +/* PWM_SUBSCRIBE_DMA_SEQ_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + /* ================================================ Struct PWM_SUBSCRIBE_DMA ================================================= */ /** @@ -21126,7 +21176,7 @@ typedef struct { */ typedef struct { __IOM NRF_PWM_SUBSCRIBE_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Subscribe configuration for tasks */ -} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 8 (0x008) */ +} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 16 (0x010) */ /* ================================================ Struct PWM_EVENTS_DMA_SEQ ================================================ */ @@ -21355,8 +21405,7 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, - updated after the END event. Also updated after each - MATCH event.*/ + updated after the END event.*/ __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ __IM uint32_t RESERVED1[2]; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is @@ -21386,9 +21435,7 @@ typedef struct { #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ -/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each - MATCH event. */ - +/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ #define PWM_DMA_SEQ_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ /* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ @@ -21453,12 +21500,12 @@ typedef struct { cause PWM generation to start if not running.*/ __IM uint32_t RESERVED1; __OM NRF_PWM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000010) Peripheral tasks. */ - __IM uint32_t RESERVED2[27]; + __IM uint32_t RESERVED2[25]; __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000088) Subscribe configuration for task NEXTSTEP */ __IM uint32_t RESERVED3; __IOM NRF_PWM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x00000090) Subscribe configuration for tasks */ - __IM uint32_t RESERVED4[27]; + __IM uint32_t RESERVED4[25]; __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no longer generated*/ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) First PWM period started on sequence n */ @@ -21823,6 +21870,24 @@ typedef struct { #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ +/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ0_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ1_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut */ + /* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ @@ -23854,53 +23919,51 @@ typedef struct { __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[33]; __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ - __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ + __IM uint32_t RESERVED9; __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ - __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ - __IM uint32_t RESERVED9[4]; + __IM uint32_t RESERVED10[5]; __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ - __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ + __IM uint32_t RESERVED11; __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ - __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ - __IM uint32_t RESERVED10[18]; + __IM uint32_t RESERVED12[19]; __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ - __IM uint32_t RESERVED11[7]; + __IM uint32_t RESERVED13[7]; __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED14[3]; __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED15; __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000540) Data whitening initial value */ - __IM uint32_t RESERVED14[112]; + __IM uint32_t RESERVED16[112]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED17; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED16[123]; + __IM uint32_t RESERVED18[123]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED17[253]; + __IM uint32_t RESERVED19[253]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED18[2]; + __IM uint32_t RESERVED20[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED19[4]; + __IM uint32_t RESERVED21[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED20[41]; + __IM uint32_t RESERVED22[41]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED21; + __IM uint32_t RESERVED23; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -23915,16 +23978,16 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED22[3]; + __IM uint32_t RESERVED24[3]; __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED25[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED24[3]; + __IM uint32_t RESERVED26[3]; __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) (unspecified) */ - __IM uint32_t RESERVED25[75]; + __IM uint32_t RESERVED27[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -27352,6 +27415,9 @@ typedef struct { /* OWNER @Bits 4..7 : Owner ID */ #define RRAMC_REGION_CONFIG_OWNER_Pos (4UL) /*!< Position of OWNER field. */ #define RRAMC_REGION_CONFIG_OWNER_Msk (0xFUL << RRAMC_REGION_CONFIG_OWNER_Pos) /*!< Bit mask of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Min (0x0UL) /*!< Min enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Max (0x0UL) /*!< Max enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_NotEnforced (0x0UL) /*!< Owner ID protection is not enforced */ /* WRITEONCE @Bit 12 : Write-once */ #define RRAMC_REGION_CONFIG_WRITEONCE_Pos (12UL) /*!< Position of WRITEONCE field. */ @@ -28540,19 +28606,8 @@ typedef struct { * @brief CH [SAADC_CH] (unspecified) */ typedef struct { - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ - }; - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ } NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ @@ -28563,11 +28618,11 @@ typedef struct { /* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ -/* PIN @Bits 0..4 : Analog positive input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELP_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field. */ -/* PORT @Bits 8..11 : GPIO Port selection */ +/* PORT @Bits 8..11 : GPIO port selection */ #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ @@ -28583,7 +28638,7 @@ typedef struct { /* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ -/* PIN @Bits 0..4 : Analog negative input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELN_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -29890,16 +29945,7 @@ typedef struct { __IM uint32_t RESERVED3[125]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ __IM uint32_t RESERVED4; - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) (unspecified) */ __IM uint32_t RESERVED5; __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ @@ -33117,7 +33163,7 @@ typedef struct { #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL) /*!< Max size of CH[24] array. */ #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL) /*!< Max index of CH[24] array. */ #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL) /*!< Min index of CH[24] array. */ - #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register. */ + #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[24] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33140,7 +33186,7 @@ typedef struct { #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL) /*!< Max size of CHG[8] array. */ #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL) /*!< Max index of CHG[8] array. */ #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[8] array. */ - #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[8] register. */ + #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00100010UL) /*!< Reset value of CHG[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33176,7 +33222,7 @@ typedef struct { #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL) /*!< Max size of CH[8] array. */ #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ - #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[8] register. */ + #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33199,7 +33245,7 @@ typedef struct { #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array. */ #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array. */ #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array. */ - #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33235,7 +33281,7 @@ typedef struct { #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL) /*!< Max size of PIN[32] array. */ #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL) /*!< Max index of PIN[32] array. */ #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL) /*!< Min index of PIN[32] array. */ - #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00000000UL) /*!< Reset value of PIN[32] register. */ + #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00100010UL) /*!< Reset value of PIN[32] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33264,7 +33310,7 @@ typedef struct { } NRF_SPU_FEATURE_CRACEN_Type; /*!< Size = 4 (0x004) */ /* SPU_FEATURE_CRACEN_SEED: Configuration for CRACEN SEED */ - #define SPU_FEATURE_CRACEN_SEED_ResetValue (0x00000000UL) /*!< Reset value of SEED register. */ + #define SPU_FEATURE_CRACEN_SEED_ResetValue (0x00020010UL) /*!< Reset value of SEED register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_CRACEN_SEED_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33302,7 +33348,7 @@ typedef struct { #define SPU_FEATURE_GRTC_CC_MaxCount (24UL) /*!< Max size of CC[24] array. */ #define SPU_FEATURE_GRTC_CC_MaxIndex (23UL) /*!< Max index of CC[24] array. */ #define SPU_FEATURE_GRTC_CC_MinIndex (0UL) /*!< Min index of CC[24] array. */ - #define SPU_FEATURE_GRTC_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[24] register. */ + #define SPU_FEATURE_GRTC_CC_ResetValue (0x00100010UL) /*!< Reset value of CC[24] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33322,7 +33368,7 @@ typedef struct { /* SPU_FEATURE_GRTC_PWMCONFIG: Configuration of feature for PWMCONFIG of GRTC */ - #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00000000UL) /*!< Reset value of PWMCONFIG register. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00100010UL) /*!< Reset value of PWMCONFIG register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33343,7 +33389,7 @@ typedef struct { /* SPU_FEATURE_GRTC_CLK: Configuration of features for CLKOUT/CLKCFG of GRTC */ - #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00000000UL) /*!< Reset value of CLK register. */ + #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00100010UL) /*!< Reset value of CLK register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_CLK_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33363,7 +33409,7 @@ typedef struct { /* SPU_FEATURE_GRTC_SYSCOUNTER: Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC */ - #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTER register. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00100010UL) /*!< Reset value of SYSCOUNTER register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33387,7 +33433,7 @@ typedef struct { #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (16UL) /*!< Max size of INTERRUPT[16] array. */ #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (15UL) /*!< Max index of INTERRUPT[16] array. */ #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[16] array. */ - #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[16] register. */ + #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[16] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -33416,16 +33462,7 @@ typedef union { struct { __IM uint32_t RESERVED[32]; __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC; /*!< (@ 0x00000080) (unspecified) */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ __IM uint32_t RESERVED1[32]; #if defined(_GNUC_) #pragma GCC diagnostic push @@ -34028,80 +34065,13 @@ typedef struct { -/* ============================================= Struct TAMPC_PROTECT_AP_SPIDEN ============================================== */ -/** - * @brief SPIDEN [TAMPC_PROTECT_AP_SPIDEN] (unspecified) - */ -typedef struct { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register to enable secure priviliged invasive - (halting) debug in domain n's access port.*/ - __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for secure priviliged invasive - (halting) debug enable for domain n's access port.*/ -} NRF_TAMPC_PROTECT_AP_SPIDEN_Type; /*!< Size = 8 (0x008) */ - -/* TAMPC_PROTECT_AP_SPIDEN_CTRL: Control register to enable secure priviliged invasive (halting) debug in domain n's access - port. */ - - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ - -/* VALUE @Bit 0 : Set value of spiden signal. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE - field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ - -/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ - -/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos) /*!< Bit - mask of WRITEPROTECTION field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ - -/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ - - -/* TAMPC_PROTECT_AP_SPIDEN_STATUS: Status register for secure priviliged invasive (halting) debug enable for domain n's access - port. */ - - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ - -/* ERROR @Bit 0 : Error detection status. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR - field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ - - - /* ================================================= Struct TAMPC_PROTECT_AP ================================================= */ /** * @brief AP [TAMPC_PROTECT_AP] (unspecified) */ typedef struct { __IOM NRF_TAMPC_PROTECT_AP_DBGEN_Type DBGEN; /*!< (@ 0x00000000) (unspecified) */ - __IOM NRF_TAMPC_PROTECT_AP_SPIDEN_Type SPIDEN; /*!< (@ 0x00000008) (unspecified) */ + __IM uint32_t RESERVED[2]; } NRF_TAMPC_PROTECT_AP_Type; /*!< Size = 16 (0x010) */ #define TAMPC_PROTECT_AP_MaxCount (1UL) /*!< Size of AP[1] array. */ #define TAMPC_PROTECT_AP_MaxIndex (0UL) /*!< Max index of AP[1] array. */ @@ -34173,71 +34143,6 @@ typedef struct { -/* ============================================ Struct TAMPC_PROTECT_TAMPERSWITCH ============================================ */ -/** - * @brief TAMPERSWITCH [TAMPC_PROTECT_TAMPERSWITCH] Enable tamper switch detector. - */ -typedef struct { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for external tamper switch enable - signal.*/ - __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for external tamper switch detector - enable signal.*/ -} NRF_TAMPC_PROTECT_TAMPERSWITCH_Type; /*!< Size = 8 (0x008) */ - -/* TAMPC_PROTECT_TAMPERSWITCH_CTRL: Control register for external tamper switch enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ - -/* VALUE @Bit 0 : Set value of tamper switch enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Pos) /*!< Bit mask of VALUE - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ - -/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Pos) /*!< Bit mask of LOCK - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ - -/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Pos) - /*!< Bit mask of WRITEPROTECTION field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ - -/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Pos) /*!< Bit mask of KEY - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ - - -/* TAMPC_PROTECT_TAMPERSWITCH_STATUS: Status register for external tamper switch detector enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ - -/* ERROR @Bit 0 : Error detection status. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Pos) /*!< Bit mask of - ERROR field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ - - - /* ============================================= Struct TAMPC_PROTECT_CRACENTAMP ============================================= */ /** * @brief CRACENTAMP [TAMPC_PROTECT_CRACENTAMP] Enable tamper detector from CRACEN. @@ -34433,9 +34338,7 @@ typedef struct { /* ============================================= Struct TAMPC_PROTECT_EXTRESETEN ============================================= */ /** - * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the active shield or tamper switch - detector. - + * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the external tamper detectors. */ typedef struct { __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for external tamper reset enable @@ -34635,14 +34538,13 @@ typedef union { __IOM NRF_TAMPC_PROTECT_AP_Type AP[1]; /*!< (@ 0x00000200) (unspecified) */ __IM uint32_t RESERVED1[124]; __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector. */ - __IOM NRF_TAMPC_PROTECT_TAMPERSWITCH_Type TAMPERSWITCH; /*!< (@ 0x00000408) Enable tamper switch detector. */ - __IM uint32_t RESERVED2[10]; + __IM uint32_t RESERVED2[12]; __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN. */ __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors. */ __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors. */ __IM uint32_t RESERVED3[8]; __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the - active shield or tamper switch detector.*/ + external tamper detectors.*/ __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector.*/ @@ -34792,14 +34694,6 @@ typedef union { #define TAMPC_STATUS_ACTIVESHIELD_NotDetected (0x0UL) /*!< Not detected. */ #define TAMPC_STATUS_ACTIVESHIELD_Detected (0x1UL) /*!< Detected. */ -/* TAMPERSWITCH @Bit 1 : External tamper switch detector detected an error. */ - #define TAMPC_STATUS_TAMPERSWITCH_Pos (1UL) /*!< Position of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Msk (0x1UL << TAMPC_STATUS_TAMPERSWITCH_Pos) /*!< Bit mask of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Min (0x0UL) /*!< Min enumerator value of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Max (0x1UL) /*!< Max enumerator value of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_NotDetected (0x0UL) /*!< Not detected. */ - #define TAMPC_STATUS_TAMPERSWITCH_Detected (0x1UL) /*!< Detected. */ - /* PROTECT @Bit 4 : Error detected for the protected signals. */ #define TAMPC_STATUS_PROTECT_Pos (4UL) /*!< Position of PROTECT field. */ #define TAMPC_STATUS_PROTECT_Msk (0x1UL << TAMPC_STATUS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ @@ -40012,11 +39906,10 @@ typedef struct { #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field. */ - #define TWIM_FREQUENCY_FREQUENCY_Max (0xFF00000UL) /*!< Max enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Max (0x6400000UL) /*!< Max enumerator value of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ - #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */ /* TWIM_ADDRESS: Address used in the TWI transfer */ @@ -43638,24 +43531,39 @@ typedef struct { #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Min (0x4F000UL) /*!< Min enumerator value of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field. */ - #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ - #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ - #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ + #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud when UARTE has 16 MHz peripheral clock frequency */ /* UARTE_CONFIG: Configuration of parity, hardware flow control, framesize, and packet timeout. */ @@ -44018,6 +43926,53 @@ typedef struct { #define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field. */ +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VDMADESCRIPTOR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct VDMADESCRIPTOR ================================================== */ +/** + * @brief Job descriptor for vector-based DMA. + */ + typedef struct { /*!< VDMADESCRIPTOR Structure */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Pointer to data buffer. */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Job configuration. Configuration of attributes and + buffer length.*/ + } NRF_VDMADESCRIPTOR_Type; /*!< Size = 8 (0x008) */ + +/* VDMADESCRIPTOR_PTR: Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */ + #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* ATTRIBUTE @Bits 24..29 : Job attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0xBUL) /*!< Min enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0xEUL) /*!< Max enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarHash (0x0BUL) /*!< Hash attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarPrand (0x0CUL) /*!< Prand attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarIrk (0x0DUL) /*!< Irk attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAlen (0x0BUL) /*!< Alen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMlen (0x0CUL) /*!< Mlen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAdata (0x0DUL) /*!< Adata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMdata (0x0EUL) /*!< Mdata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_EcbData (0x0BUL) /*!< EcbData attribute */ + + #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ /* =========================================================================================================================== */ @@ -44737,28 +44692,31 @@ typedef struct { * @brief VPR peripheral registers */ typedef struct { /*!< VPR Structure */ - __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) VPR task [n] register */ - __IOM uint32_t SUBSCRIBE_TRIGGER[32]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ - __IOM uint32_t EVENTS_TRIGGERED[32]; /*!< (@ 0x00000100) VPR event [n] register */ - __IOM uint32_t PUBLISH_TRIGGERED[32]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ - __IM uint32_t RESERVED[64]; + __OM uint32_t TASKS_TRIGGER[23]; /*!< (@ 0x00000000) VPR task [n] register */ + __IM uint32_t RESERVED[9]; + __IOM uint32_t SUBSCRIBE_TRIGGER[4]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_TRIGGERED[23]; /*!< (@ 0x00000100) VPR event [n] register */ + __IM uint32_t RESERVED2[9]; + __IOM uint32_t PUBLISH_TRIGGERED[4]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ + __IM uint32_t RESERVED3[92]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ - __IM uint32_t RESERVED1[60]; + __IM uint32_t RESERVED4[60]; __IOM NRF_VPR_DEBUGIF_Type DEBUGIF; /*!< (@ 0x00000400) (unspecified) */ - __IM uint32_t RESERVED2[191]; + __IM uint32_t RESERVED5[191]; __IOM uint32_t CPURUN; /*!< (@ 0x00000800) State of the CPU after a core reset */ - __IM uint32_t RESERVED3; + __IM uint32_t RESERVED6; __IOM uint32_t INITPC; /*!< (@ 0x00000808) Initial value of the PC at CPU start. */ } NRF_VPR_Type; /*!< Size = 2060 (0x80C) */ /* VPR_TASKS_TRIGGER: VPR task [n] register */ - #define VPR_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + #define VPR_TASKS_TRIGGER_MaxCount (7UL) /*!< Max size of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MaxIndex (22UL) /*!< Max index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MinIndex (16UL) /*!< Min index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[23] register. */ /* TASKS_TRIGGER @Bit 0 : VPR task [n] register */ #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ @@ -44770,10 +44728,10 @@ typedef struct { /* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */ - #define VPR_SUBSCRIBE_TRIGGER_MaxCount (32UL) /*!< Max size of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (31UL) /*!< Max index of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[32] register. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL) /*!< Max size of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (3UL) /*!< Max index of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[4] register. */ /* EN @Bit 31 : Subscription enable bit */ #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ @@ -44785,10 +44743,10 @@ typedef struct { /* VPR_EVENTS_TRIGGERED: VPR event [n] register */ - #define VPR_EVENTS_TRIGGERED_MaxCount (32UL) /*!< Max size of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_MaxIndex (31UL) /*!< Max index of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register. */ + #define VPR_EVENTS_TRIGGERED_MaxCount (7UL) /*!< Max size of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MaxIndex (22UL) /*!< Max index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MinIndex (16UL) /*!< Min index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[23] register. */ /* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */ #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ @@ -44801,10 +44759,10 @@ typedef struct { /* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */ - #define VPR_PUBLISH_TRIGGERED_MaxCount (32UL) /*!< Max size of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_MaxIndex (31UL) /*!< Max index of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[32] register. */ + #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL) /*!< Max size of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_MaxIndex (3UL) /*!< Max index of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[4] register. */ /* EN @Bit 31 : Publication enable bit */ #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ @@ -44818,134 +44776,6 @@ typedef struct { /* VPR_INTEN: Enable or disable interrupt */ #define VPR_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ -/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ - #define VPR_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Msk (0x1UL << VPR_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ - #define VPR_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Msk (0x1UL << VPR_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ - #define VPR_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Msk (0x1UL << VPR_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ - #define VPR_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Msk (0x1UL << VPR_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ - #define VPR_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Msk (0x1UL << VPR_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ - #define VPR_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Msk (0x1UL << VPR_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ - #define VPR_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Msk (0x1UL << VPR_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ - #define VPR_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Msk (0x1UL << VPR_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ - #define VPR_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Msk (0x1UL << VPR_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ - #define VPR_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Msk (0x1UL << VPR_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ - #define VPR_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Msk (0x1UL << VPR_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ - #define VPR_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Msk (0x1UL << VPR_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ - #define VPR_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Msk (0x1UL << VPR_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ - #define VPR_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Msk (0x1UL << VPR_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ - #define VPR_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Msk (0x1UL << VPR_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ - #define VPR_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Msk (0x1UL << VPR_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ - /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ #define VPR_INTEN_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -45002,226 +44832,10 @@ typedef struct { #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ -/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ - #define VPR_INTEN_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Msk (0x1UL << VPR_INTEN_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ - #define VPR_INTEN_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Msk (0x1UL << VPR_INTEN_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ - #define VPR_INTEN_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Msk (0x1UL << VPR_INTEN_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ - #define VPR_INTEN_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Msk (0x1UL << VPR_INTEN_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ - #define VPR_INTEN_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Msk (0x1UL << VPR_INTEN_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ - #define VPR_INTEN_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Msk (0x1UL << VPR_INTEN_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ - #define VPR_INTEN_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Msk (0x1UL << VPR_INTEN_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ - #define VPR_INTEN_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Msk (0x1UL << VPR_INTEN_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ - #define VPR_INTEN_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Msk (0x1UL << VPR_INTEN_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ - /* VPR_INTENSET: Enable interrupt */ #define VPR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ -/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ - #define VPR_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Msk (0x1UL << VPR_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ - #define VPR_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Msk (0x1UL << VPR_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ - #define VPR_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Msk (0x1UL << VPR_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ - #define VPR_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Msk (0x1UL << VPR_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ - #define VPR_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Msk (0x1UL << VPR_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ - #define VPR_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Msk (0x1UL << VPR_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ - #define VPR_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Msk (0x1UL << VPR_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ - #define VPR_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Msk (0x1UL << VPR_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ - #define VPR_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Msk (0x1UL << VPR_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ - #define VPR_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Msk (0x1UL << VPR_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ - #define VPR_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Msk (0x1UL << VPR_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ - #define VPR_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Msk (0x1UL << VPR_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ - #define VPR_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Msk (0x1UL << VPR_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ - #define VPR_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Msk (0x1UL << VPR_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ - #define VPR_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Msk (0x1UL << VPR_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ - #define VPR_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Msk (0x1UL << VPR_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ - /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ #define VPR_INTENSET_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -45285,235 +44899,10 @@ typedef struct { #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ -/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ - #define VPR_INTENSET_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Msk (0x1UL << VPR_INTENSET_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ - #define VPR_INTENSET_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Msk (0x1UL << VPR_INTENSET_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ - #define VPR_INTENSET_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Msk (0x1UL << VPR_INTENSET_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ - #define VPR_INTENSET_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Msk (0x1UL << VPR_INTENSET_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ - #define VPR_INTENSET_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Msk (0x1UL << VPR_INTENSET_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ - #define VPR_INTENSET_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Msk (0x1UL << VPR_INTENSET_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ - #define VPR_INTENSET_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Msk (0x1UL << VPR_INTENSET_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ - #define VPR_INTENSET_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Msk (0x1UL << VPR_INTENSET_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ - #define VPR_INTENSET_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Msk (0x1UL << VPR_INTENSET_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ - /* VPR_INTENCLR: Disable interrupt */ #define VPR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ -/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ - #define VPR_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Msk (0x1UL << VPR_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ - #define VPR_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Msk (0x1UL << VPR_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ - #define VPR_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Msk (0x1UL << VPR_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ - #define VPR_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Msk (0x1UL << VPR_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ - #define VPR_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Msk (0x1UL << VPR_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ - #define VPR_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Msk (0x1UL << VPR_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ - #define VPR_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Msk (0x1UL << VPR_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ - #define VPR_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Msk (0x1UL << VPR_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ - #define VPR_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Msk (0x1UL << VPR_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ - #define VPR_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Msk (0x1UL << VPR_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ - #define VPR_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Msk (0x1UL << VPR_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ - #define VPR_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Msk (0x1UL << VPR_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ - #define VPR_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Msk (0x1UL << VPR_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ - #define VPR_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Msk (0x1UL << VPR_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ - #define VPR_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Msk (0x1UL << VPR_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ - #define VPR_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Msk (0x1UL << VPR_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ - /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ #define VPR_INTENCLR_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -45577,219 +44966,10 @@ typedef struct { #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ -/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ - #define VPR_INTENCLR_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Msk (0x1UL << VPR_INTENCLR_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ - #define VPR_INTENCLR_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Msk (0x1UL << VPR_INTENCLR_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ - #define VPR_INTENCLR_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Msk (0x1UL << VPR_INTENCLR_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ - #define VPR_INTENCLR_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Msk (0x1UL << VPR_INTENCLR_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ - #define VPR_INTENCLR_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Msk (0x1UL << VPR_INTENCLR_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ - #define VPR_INTENCLR_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Msk (0x1UL << VPR_INTENCLR_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ - #define VPR_INTENCLR_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Msk (0x1UL << VPR_INTENCLR_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ - #define VPR_INTENCLR_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Msk (0x1UL << VPR_INTENCLR_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ - #define VPR_INTENCLR_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Msk (0x1UL << VPR_INTENCLR_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ - /* VPR_INTPEND: Pending interrupts */ #define VPR_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ -/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ - #define VPR_INTPEND_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Msk (0x1UL << VPR_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ - #define VPR_INTPEND_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Msk (0x1UL << VPR_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ - #define VPR_INTPEND_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Msk (0x1UL << VPR_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ - #define VPR_INTPEND_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Msk (0x1UL << VPR_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ - #define VPR_INTPEND_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Msk (0x1UL << VPR_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ - #define VPR_INTPEND_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Msk (0x1UL << VPR_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ - #define VPR_INTPEND_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Msk (0x1UL << VPR_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ - #define VPR_INTPEND_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Msk (0x1UL << VPR_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ - #define VPR_INTPEND_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Msk (0x1UL << VPR_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ - #define VPR_INTPEND_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Msk (0x1UL << VPR_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ - #define VPR_INTPEND_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Msk (0x1UL << VPR_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ - #define VPR_INTPEND_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Msk (0x1UL << VPR_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ - #define VPR_INTPEND_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Msk (0x1UL << VPR_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ - #define VPR_INTPEND_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Msk (0x1UL << VPR_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ - #define VPR_INTPEND_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Msk (0x1UL << VPR_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ - #define VPR_INTPEND_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Msk (0x1UL << VPR_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ - /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ #define VPR_INTPEND_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -45846,78 +45026,6 @@ typedef struct { #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ -/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ - #define VPR_INTPEND_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Msk (0x1UL << VPR_INTPEND_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ - #define VPR_INTPEND_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Msk (0x1UL << VPR_INTPEND_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ - #define VPR_INTPEND_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Msk (0x1UL << VPR_INTPEND_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ - #define VPR_INTPEND_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Msk (0x1UL << VPR_INTPEND_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ - #define VPR_INTPEND_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Msk (0x1UL << VPR_INTPEND_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ - #define VPR_INTPEND_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Msk (0x1UL << VPR_INTPEND_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ - #define VPR_INTPEND_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Msk (0x1UL << VPR_INTPEND_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ - #define VPR_INTPEND_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Msk (0x1UL << VPR_INTPEND_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ - #define VPR_INTPEND_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Msk (0x1UL << VPR_INTPEND_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ - /* VPR_CPURUN: State of the CPU after a core reset */ #define VPR_CPURUN_ResetValue (0x00000000UL) /*!< Reset value of CPURUN register. */ @@ -45991,7 +45099,7 @@ typedef struct { * @brief MISA [VPRCSR_MISA] Machine ISA */ #define VPRCSR_MISA (0x00000301ul) - #define VPRCSR_MISA_ResetValue (0x40001014UL) /*!< Reset value of MISA register. */ + #define VPRCSR_MISA_ResetValue (0x40001016UL) /*!< Reset value of MISA register. */ /* A @Bit 0 : Atomic extension */ #define VPRCSR_MISA_A_Pos (0UL) /*!< Position of A field. */ @@ -46231,7 +45339,7 @@ typedef struct { * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base */ #define VPRCSR_MCLICBASE (0x00000350ul) - #define VPRCSR_MCLICBASE_ResetValue (0x00001000UL) /*!< Reset value of MCLICBASE register. */ + #define VPRCSR_MCLICBASE_ResetValue (0xF0000000UL) /*!< Reset value of MCLICBASE register. */ /* VAL @Bits 0..31 : CLIC base address value */ #define VPRCSR_MCLICBASE_VAL_Pos (0UL) /*!< Position of VAL field. */ @@ -46275,8 +45383,8 @@ typedef struct { #define VPRCSR_TDATA1_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ #define VPRCSR_TDATA1_TYPE_Max (0xFUL) /*!< Max enumerator value of TYPE field. */ #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL) /*!< There is no trigger at this tselect */ - #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address/data match trigger. The remaining bits in - this register act as described in mcontrol*/ + #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address match trigger. The remaining bits in this + register act as described in mcontrol*/ #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL) /*!< This trigger is a remapping trigger. The remaining bits in this register behave as described in remapping functionality*/ @@ -46511,13 +45619,13 @@ typedef struct { * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID */ #define VPRCSR_MARCHID (0x00000F12ul) - #define VPRCSR_MARCHID_ResetValue (0x800000AEUL) /*!< Reset value of MARCHID register. */ + #define VPRCSR_MARCHID_ResetValue (0x8000007EUL) /*!< Reset value of MARCHID register. */ /* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */ #define VPRCSR_MARCHID_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ -/* HIBERNATE @Bit 2 : Indicates the HIBERNATE parameter option */ +/* HIBERNATE @Bit 2 : Indicates the POWEROFFSLEEP parameter option */ #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL) /*!< Position of HIBERNATE field. */ #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field. */ @@ -46533,9 +45641,22 @@ typedef struct { #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL) /*!< Position of BUSWIDTH field. */ #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field. */ -/* BKPT @Bits 6..8 : Indicates the BKPT parameter option */ +/* BKPT @Bits 6..9 : Indicates the BKPT parameter option */ #define VPRCSR_MARCHID_BKPT_Pos (6UL) /*!< Position of BKPT field. */ - #define VPRCSR_MARCHID_BKPT_Msk (0x7UL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + #define VPRCSR_MARCHID_BKPT_Msk (0xFUL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* CACHE @Bit 10 : Indicates that the CACHE is present */ + #define VPRCSR_MARCHID_CACHE_Pos (10UL) /*!< Position of CACHE field. */ + #define VPRCSR_MARCHID_CACHE_Msk (0x1UL << VPRCSR_MARCHID_CACHE_Pos) /*!< Bit mask of CACHE field. */ + +/* CACHEEXTRATAGBUF @Bits 11..13 : Indicates the number of extra TAG buffers in CACHE */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos (11UL) /*!< Position of CACHEEXTRATAGBUF field. */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Msk (0x7UL << VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos) /*!< Bit mask of CACHEEXTRATAGBUF + field.*/ + +/* RETAINED @Bit 16 : Indicates the RETAINED parameter option */ + #define VPRCSR_MARCHID_RETAINED_Pos (16UL) /*!< Position of RETAINED field. */ + #define VPRCSR_MARCHID_RETAINED_Msk (0x1UL << VPRCSR_MARCHID_RETAINED_Pos) /*!< Bit mask of RETAINED field. */ /* IMPLEM @Bit 31 : Indicates a non-open implementation */ #define VPRCSR_MARCHID_IMPLEM_Pos (31UL) /*!< Position of IMPLEM field. */ @@ -46565,7 +45686,7 @@ typedef struct { * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID */ #define VPRCSR_MHARTID (0x00000F14ul) - #define VPRCSR_MHARTID_ResetValue (0x00000000UL) /*!< Reset value of MHARTID register. */ + #define VPRCSR_MHARTID_ResetValue (0x0000000EUL) /*!< Reset value of MHARTID register. */ /* HARTNUM @Bits 0..31 : Machine Hart ID value */ #define VPRCSR_MHARTID_HARTNUM_Pos (0UL) /*!< Position of HARTNUM field. */ @@ -46709,7 +45830,7 @@ typedef struct { * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO */ #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul) - #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x00000000UL) /*!< Reset value of VIOPINS register. */ + #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x0000FFFFUL) /*!< Reset value of VIOPINS register. */ /* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */ #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL) /*!< Position of VAL field. */ @@ -46720,7 +45841,7 @@ typedef struct { * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters */ #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul) - #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x00000016UL) /*!< Reset value of EXTPARAMS register. */ + #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x0000008EUL) /*!< Reset value of EXTPARAMS register. */ /* MULDIV @Bits 0..1 : value of MULDIV */ #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ @@ -47392,258 +46513,6 @@ typedef struct { #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3] */ #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3] */ -/* SUBSCRIBE4 @Bit 4 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos (4UL) /*!< Position of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos) /*!< Bit mask of SUBSCRIBE4 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Disabled (0x0UL) /*!< Subscribe disabled for TASK[4] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Enabled (0x1UL) /*!< Subscribe enabled for TASK[4] */ - -/* SUBSCRIBE5 @Bit 5 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos (5UL) /*!< Position of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos) /*!< Bit mask of SUBSCRIBE5 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Disabled (0x0UL) /*!< Subscribe disabled for TASK[5] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Enabled (0x1UL) /*!< Subscribe enabled for TASK[5] */ - -/* SUBSCRIBE6 @Bit 6 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos (6UL) /*!< Position of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos) /*!< Bit mask of SUBSCRIBE6 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Disabled (0x0UL) /*!< Subscribe disabled for TASK[6] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Enabled (0x1UL) /*!< Subscribe enabled for TASK[6] */ - -/* SUBSCRIBE7 @Bit 7 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos (7UL) /*!< Position of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos) /*!< Bit mask of SUBSCRIBE7 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Disabled (0x0UL) /*!< Subscribe disabled for TASK[7] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Enabled (0x1UL) /*!< Subscribe enabled for TASK[7] */ - -/* SUBSCRIBE8 @Bit 8 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos (8UL) /*!< Position of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos) /*!< Bit mask of SUBSCRIBE8 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Disabled (0x0UL) /*!< Subscribe disabled for TASK[8] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Enabled (0x1UL) /*!< Subscribe enabled for TASK[8] */ - -/* SUBSCRIBE9 @Bit 9 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos (9UL) /*!< Position of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos) /*!< Bit mask of SUBSCRIBE9 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Disabled (0x0UL) /*!< Subscribe disabled for TASK[9] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Enabled (0x1UL) /*!< Subscribe enabled for TASK[9] */ - -/* SUBSCRIBE10 @Bit 10 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos (10UL) /*!< Position of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos) /*!< Bit mask of - SUBSCRIBE10 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Disabled (0x0UL) /*!< Subscribe disabled for TASK[10] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Enabled (0x1UL) /*!< Subscribe enabled for TASK[10] */ - -/* SUBSCRIBE11 @Bit 11 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos (11UL) /*!< Position of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos) /*!< Bit mask of - SUBSCRIBE11 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Disabled (0x0UL) /*!< Subscribe disabled for TASK[11] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Enabled (0x1UL) /*!< Subscribe enabled for TASK[11] */ - -/* SUBSCRIBE12 @Bit 12 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos (12UL) /*!< Position of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos) /*!< Bit mask of - SUBSCRIBE12 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Disabled (0x0UL) /*!< Subscribe disabled for TASK[12] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Enabled (0x1UL) /*!< Subscribe enabled for TASK[12] */ - -/* SUBSCRIBE13 @Bit 13 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos (13UL) /*!< Position of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos) /*!< Bit mask of - SUBSCRIBE13 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Disabled (0x0UL) /*!< Subscribe disabled for TASK[13] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Enabled (0x1UL) /*!< Subscribe enabled for TASK[13] */ - -/* SUBSCRIBE14 @Bit 14 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos (14UL) /*!< Position of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos) /*!< Bit mask of - SUBSCRIBE14 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Disabled (0x0UL) /*!< Subscribe disabled for TASK[14] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Enabled (0x1UL) /*!< Subscribe enabled for TASK[14] */ - -/* SUBSCRIBE15 @Bit 15 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos (15UL) /*!< Position of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos) /*!< Bit mask of - SUBSCRIBE15 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Disabled (0x0UL) /*!< Subscribe disabled for TASK[15] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Enabled (0x1UL) /*!< Subscribe enabled for TASK[15] */ - -/* SUBSCRIBE16 @Bit 16 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of - SUBSCRIBE16 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16] */ - -/* SUBSCRIBE17 @Bit 17 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of - SUBSCRIBE17 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17] */ - -/* SUBSCRIBE18 @Bit 18 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of - SUBSCRIBE18 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18] */ - -/* SUBSCRIBE19 @Bit 19 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of - SUBSCRIBE19 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19] */ - -/* SUBSCRIBE20 @Bit 20 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos (20UL) /*!< Position of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos) /*!< Bit mask of - SUBSCRIBE20 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Disabled (0x0UL) /*!< Subscribe disabled for TASK[20] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Enabled (0x1UL) /*!< Subscribe enabled for TASK[20] */ - -/* SUBSCRIBE21 @Bit 21 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos (21UL) /*!< Position of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos) /*!< Bit mask of - SUBSCRIBE21 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Disabled (0x0UL) /*!< Subscribe disabled for TASK[21] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Enabled (0x1UL) /*!< Subscribe enabled for TASK[21] */ - -/* SUBSCRIBE22 @Bit 22 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos (22UL) /*!< Position of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos) /*!< Bit mask of - SUBSCRIBE22 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Disabled (0x0UL) /*!< Subscribe disabled for TASK[22] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Enabled (0x1UL) /*!< Subscribe enabled for TASK[22] */ - -/* SUBSCRIBE23 @Bit 23 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos (23UL) /*!< Position of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos) /*!< Bit mask of - SUBSCRIBE23 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Disabled (0x0UL) /*!< Subscribe disabled for TASK[23] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Enabled (0x1UL) /*!< Subscribe enabled for TASK[23] */ - -/* SUBSCRIBE24 @Bit 24 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos (24UL) /*!< Position of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos) /*!< Bit mask of - SUBSCRIBE24 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Disabled (0x0UL) /*!< Subscribe disabled for TASK[24] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Enabled (0x1UL) /*!< Subscribe enabled for TASK[24] */ - -/* SUBSCRIBE25 @Bit 25 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos (25UL) /*!< Position of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos) /*!< Bit mask of - SUBSCRIBE25 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Disabled (0x0UL) /*!< Subscribe disabled for TASK[25] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Enabled (0x1UL) /*!< Subscribe enabled for TASK[25] */ - -/* SUBSCRIBE26 @Bit 26 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos (26UL) /*!< Position of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos) /*!< Bit mask of - SUBSCRIBE26 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Disabled (0x0UL) /*!< Subscribe disabled for TASK[26] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Enabled (0x1UL) /*!< Subscribe enabled for TASK[26] */ - -/* SUBSCRIBE27 @Bit 27 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos (27UL) /*!< Position of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos) /*!< Bit mask of - SUBSCRIBE27 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Disabled (0x0UL) /*!< Subscribe disabled for TASK[27] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Enabled (0x1UL) /*!< Subscribe enabled for TASK[27] */ - -/* SUBSCRIBE28 @Bit 28 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos (28UL) /*!< Position of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos) /*!< Bit mask of - SUBSCRIBE28 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Disabled (0x0UL) /*!< Subscribe disabled for TASK[28] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Enabled (0x1UL) /*!< Subscribe enabled for TASK[28] */ - -/* SUBSCRIBE29 @Bit 29 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos (29UL) /*!< Position of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos) /*!< Bit mask of - SUBSCRIBE29 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Disabled (0x0UL) /*!< Subscribe disabled for TASK[29] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Enabled (0x1UL) /*!< Subscribe enabled for TASK[29] */ - -/* SUBSCRIBE30 @Bit 30 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos (30UL) /*!< Position of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos) /*!< Bit mask of - SUBSCRIBE30 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Disabled (0x0UL) /*!< Subscribe disabled for TASK[30] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Enabled (0x1UL) /*!< Subscribe enabled for TASK[30] */ - -/* SUBSCRIBE31 @Bit 31 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos (31UL) /*!< Position of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos) /*!< Bit mask of - SUBSCRIBE31 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Disabled (0x0UL) /*!< Subscribe disabled for TASK[31] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Enabled (0x1UL) /*!< Subscribe enabled for TASK[31] */ - /** * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events @@ -47946,230 +46815,6 @@ typedef struct { #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3] */ #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3] */ -/* PUBLISH4 @Bit 4 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos (4UL) /*!< Position of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos) /*!< Bit mask of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Min (0x0UL) /*!< Min enumerator value of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Max (0x1UL) /*!< Max enumerator value of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Disabled (0x0UL) /*!< Publish disabled for EVENTS[4] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Enabled (0x1UL) /*!< Publish enabled for EVENTS[4] */ - -/* PUBLISH5 @Bit 5 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos (5UL) /*!< Position of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos) /*!< Bit mask of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Min (0x0UL) /*!< Min enumerator value of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Max (0x1UL) /*!< Max enumerator value of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Disabled (0x0UL) /*!< Publish disabled for EVENTS[5] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Enabled (0x1UL) /*!< Publish enabled for EVENTS[5] */ - -/* PUBLISH6 @Bit 6 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos (6UL) /*!< Position of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos) /*!< Bit mask of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Min (0x0UL) /*!< Min enumerator value of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Max (0x1UL) /*!< Max enumerator value of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Disabled (0x0UL) /*!< Publish disabled for EVENTS[6] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Enabled (0x1UL) /*!< Publish enabled for EVENTS[6] */ - -/* PUBLISH7 @Bit 7 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos (7UL) /*!< Position of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos) /*!< Bit mask of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Min (0x0UL) /*!< Min enumerator value of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Max (0x1UL) /*!< Max enumerator value of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Disabled (0x0UL) /*!< Publish disabled for EVENTS[7] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Enabled (0x1UL) /*!< Publish enabled for EVENTS[7] */ - -/* PUBLISH8 @Bit 8 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos (8UL) /*!< Position of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos) /*!< Bit mask of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Min (0x0UL) /*!< Min enumerator value of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Max (0x1UL) /*!< Max enumerator value of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Disabled (0x0UL) /*!< Publish disabled for EVENTS[8] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Enabled (0x1UL) /*!< Publish enabled for EVENTS[8] */ - -/* PUBLISH9 @Bit 9 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos (9UL) /*!< Position of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos) /*!< Bit mask of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Min (0x0UL) /*!< Min enumerator value of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Max (0x1UL) /*!< Max enumerator value of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Disabled (0x0UL) /*!< Publish disabled for EVENTS[9] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Enabled (0x1UL) /*!< Publish enabled for EVENTS[9] */ - -/* PUBLISH10 @Bit 10 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos (10UL) /*!< Position of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos) /*!< Bit mask of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Min (0x0UL) /*!< Min enumerator value of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Max (0x1UL) /*!< Max enumerator value of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Disabled (0x0UL) /*!< Publish disabled for EVENTS[10] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Enabled (0x1UL) /*!< Publish enabled for EVENTS[10] */ - -/* PUBLISH11 @Bit 11 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos (11UL) /*!< Position of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos) /*!< Bit mask of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Min (0x0UL) /*!< Min enumerator value of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Max (0x1UL) /*!< Max enumerator value of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Disabled (0x0UL) /*!< Publish disabled for EVENTS[11] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Enabled (0x1UL) /*!< Publish enabled for EVENTS[11] */ - -/* PUBLISH12 @Bit 12 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos (12UL) /*!< Position of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos) /*!< Bit mask of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Min (0x0UL) /*!< Min enumerator value of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Max (0x1UL) /*!< Max enumerator value of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Disabled (0x0UL) /*!< Publish disabled for EVENTS[12] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Enabled (0x1UL) /*!< Publish enabled for EVENTS[12] */ - -/* PUBLISH13 @Bit 13 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos (13UL) /*!< Position of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos) /*!< Bit mask of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Min (0x0UL) /*!< Min enumerator value of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Max (0x1UL) /*!< Max enumerator value of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Disabled (0x0UL) /*!< Publish disabled for EVENTS[13] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Enabled (0x1UL) /*!< Publish enabled for EVENTS[13] */ - -/* PUBLISH14 @Bit 14 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos (14UL) /*!< Position of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos) /*!< Bit mask of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Min (0x0UL) /*!< Min enumerator value of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Max (0x1UL) /*!< Max enumerator value of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Disabled (0x0UL) /*!< Publish disabled for EVENTS[14] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Enabled (0x1UL) /*!< Publish enabled for EVENTS[14] */ - -/* PUBLISH15 @Bit 15 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos (15UL) /*!< Position of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos) /*!< Bit mask of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Min (0x0UL) /*!< Min enumerator value of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Max (0x1UL) /*!< Max enumerator value of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Disabled (0x0UL) /*!< Publish disabled for EVENTS[15] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Enabled (0x1UL) /*!< Publish enabled for EVENTS[15] */ - -/* PUBLISH16 @Bit 16 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16] */ - -/* PUBLISH17 @Bit 17 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17] */ - -/* PUBLISH18 @Bit 18 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18] */ - -/* PUBLISH19 @Bit 19 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19] */ - -/* PUBLISH20 @Bit 20 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos (20UL) /*!< Position of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos) /*!< Bit mask of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Min (0x0UL) /*!< Min enumerator value of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Max (0x1UL) /*!< Max enumerator value of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Disabled (0x0UL) /*!< Publish disabled for EVENTS[20] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Enabled (0x1UL) /*!< Publish enabled for EVENTS[20] */ - -/* PUBLISH21 @Bit 21 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos (21UL) /*!< Position of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos) /*!< Bit mask of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Min (0x0UL) /*!< Min enumerator value of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Max (0x1UL) /*!< Max enumerator value of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Disabled (0x0UL) /*!< Publish disabled for EVENTS[21] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Enabled (0x1UL) /*!< Publish enabled for EVENTS[21] */ - -/* PUBLISH22 @Bit 22 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos (22UL) /*!< Position of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos) /*!< Bit mask of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Min (0x0UL) /*!< Min enumerator value of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Max (0x1UL) /*!< Max enumerator value of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Disabled (0x0UL) /*!< Publish disabled for EVENTS[22] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Enabled (0x1UL) /*!< Publish enabled for EVENTS[22] */ - -/* PUBLISH23 @Bit 23 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos (23UL) /*!< Position of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos) /*!< Bit mask of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Min (0x0UL) /*!< Min enumerator value of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Max (0x1UL) /*!< Max enumerator value of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Disabled (0x0UL) /*!< Publish disabled for EVENTS[23] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Enabled (0x1UL) /*!< Publish enabled for EVENTS[23] */ - -/* PUBLISH24 @Bit 24 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos (24UL) /*!< Position of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos) /*!< Bit mask of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Min (0x0UL) /*!< Min enumerator value of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Max (0x1UL) /*!< Max enumerator value of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Disabled (0x0UL) /*!< Publish disabled for EVENTS[24] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Enabled (0x1UL) /*!< Publish enabled for EVENTS[24] */ - -/* PUBLISH25 @Bit 25 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos (25UL) /*!< Position of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos) /*!< Bit mask of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Min (0x0UL) /*!< Min enumerator value of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Max (0x1UL) /*!< Max enumerator value of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Disabled (0x0UL) /*!< Publish disabled for EVENTS[25] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Enabled (0x1UL) /*!< Publish enabled for EVENTS[25] */ - -/* PUBLISH26 @Bit 26 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos (26UL) /*!< Position of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos) /*!< Bit mask of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Min (0x0UL) /*!< Min enumerator value of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Max (0x1UL) /*!< Max enumerator value of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Disabled (0x0UL) /*!< Publish disabled for EVENTS[26] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Enabled (0x1UL) /*!< Publish enabled for EVENTS[26] */ - -/* PUBLISH27 @Bit 27 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos (27UL) /*!< Position of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos) /*!< Bit mask of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Min (0x0UL) /*!< Min enumerator value of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Max (0x1UL) /*!< Max enumerator value of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Disabled (0x0UL) /*!< Publish disabled for EVENTS[27] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Enabled (0x1UL) /*!< Publish enabled for EVENTS[27] */ - -/* PUBLISH28 @Bit 28 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos (28UL) /*!< Position of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos) /*!< Bit mask of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Min (0x0UL) /*!< Min enumerator value of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Max (0x1UL) /*!< Max enumerator value of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Disabled (0x0UL) /*!< Publish disabled for EVENTS[28] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Enabled (0x1UL) /*!< Publish enabled for EVENTS[28] */ - -/* PUBLISH29 @Bit 29 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos (29UL) /*!< Position of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos) /*!< Bit mask of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Min (0x0UL) /*!< Min enumerator value of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Max (0x1UL) /*!< Max enumerator value of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Disabled (0x0UL) /*!< Publish disabled for EVENTS[29] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Enabled (0x1UL) /*!< Publish enabled for EVENTS[29] */ - -/* PUBLISH30 @Bit 30 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos (30UL) /*!< Position of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos) /*!< Bit mask of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Min (0x0UL) /*!< Min enumerator value of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Max (0x1UL) /*!< Max enumerator value of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Disabled (0x0UL) /*!< Publish disabled for EVENTS[30] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Enabled (0x1UL) /*!< Publish enabled for EVENTS[30] */ - -/* PUBLISH31 @Bit 31 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos (31UL) /*!< Position of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos) /*!< Bit mask of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Min (0x0UL) /*!< Min enumerator value of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Max (0x1UL) /*!< Max enumerator value of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Disabled (0x0UL) /*!< Publish disabled for EVENTS[31] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Enabled (0x1UL) /*!< Publish enabled for EVENTS[31] */ - /** * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable diff --git a/mdk/nrf54l15_enga_version.h b/mdk/nrf54l15_enga_version.h index 1ed8ea5a3..54230efa8 100644 --- a/mdk/nrf54l15_enga_version.h +++ b/mdk/nrf54l15_enga_version.h @@ -44,7 +44,6 @@ POSSIBILITY OF SUCH DAMAGE. #define MDK_SOURCE_VERSION_MINOR 5b /*!< Minor version of product specification. */ #define MDK_SOURCE_VERSION_MICRO /*!< Micro version of product specification. */ -#define MDK_SOURCE_HASH Moonlight_IPS_v0.5G /*!< Git hash of product specification source. */ #ifdef __cplusplus diff --git a/mdk/nrf54l15_flpr.h b/mdk/nrf54l15_flpr.h index bae82a664..e0ba76038 100644 --- a/mdk/nrf54l15_flpr.h +++ b/mdk/nrf54l15_flpr.h @@ -203,6 +203,9 @@ typedef enum { /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ #define __DSP_PRESENT 0 /*!< DSP present or not */ #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ @@ -211,12 +214,21 @@ typedef enum { #define __FPU_DP 0 /*!< Double Precision FPU */ #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ +#define NRF_VPR NRF_VPR00 /*!< VPR instance name */ #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ #include "system_nrf.h" /*!< nrf54l15_flpr System Library */ #endif /*!< NRF_FLPR */ +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_NONE + #define NRF_PROCESSOR NRF_PROCESSOR_VPR + +#endif /*!< NRF_FLPR */ + + /* ========================================= Start of section using anonymous unions ========================================= */ #include "compiler_abstraction.h" diff --git a/mdk/nrf54l15_flpr.svd b/mdk/nrf54l15_flpr.svd index 01eb9d5ba..292beee20 100644 --- a/mdk/nrf54l15_flpr.svd +++ b/mdk/nrf54l15_flpr.svd @@ -602,9 +602,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -624,9 +624,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -655,9 +655,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -677,9 +677,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -708,9 +708,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.AP[0] DBGEN signal protector. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -730,9 +730,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Blocks debugger read/write access to all CPU registers and memory mapped addresses, and locks TAMPC PROTECT.AP[0] DBGEN signal protector. - 0x50FA50FA + Unprotected + Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal protectors unlocked and under CPU control. + 0xFFFFFFFF @@ -761,9 +761,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Protected, the device cannot be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is locked. - 0x50FA50FA + Unprotected + The device can be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF @@ -783,9 +783,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - Protected - Protected, the device cannot be erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is locked. - 0x50FA50FA + Unprotected + The device canbe erased using the CTRL-AP Erase all function and TAMPC PROTECT.ERASEPROTECT signal protector is unlocked. + 0xFFFFFFFF @@ -3471,7 +3471,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x1E0 + 0x10F 0x4 CLICINT[%s] Description collection: Interrupt control register for IRQ number [n]. @@ -3971,7 +3971,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel n of DPPIC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4020,7 +4020,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel group n of DPPIC 0x060 read-write - 0x00000000 + 0x00100010 0x20 @@ -4068,7 +4068,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x040 GPIOTE[%s] Unspecified - GPIOTE + SPU_FEATURE_GPIOTE read-write 0x100 @@ -4078,7 +4078,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for channel o of GPIOTE[n] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4127,7 +4127,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for interrupt o of GPIOTE[n] 0x020 read-write - 0x00000000 + 0x00100010 0x20 @@ -4185,7 +4185,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for GPIO[n] PIN[o] 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4240,7 +4240,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration for CRACEN SEED 0x180 read-write - 0x00000000 + 0x00020010 0x20 @@ -4296,7 +4296,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for CC n of GRTC 0x000 read-write - 0x00000000 + 0x00100010 0x20 @@ -4343,7 +4343,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of feature for PWMCONFIG of GRTC 0x074 read-write - 0x00000000 + 0x00100010 0x20 @@ -4390,7 +4390,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of features for CLKOUT/CLKCFG of GRTC 0x078 read-write - 0x00000000 + 0x00100010 0x20 @@ -4437,7 +4437,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC 0x07C read-write - 0x00000000 + 0x00100010 0x20 @@ -4486,7 +4486,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration of features for interrupt n of GRTC 0x080 read-write - 0x00000000 + 0x00100010 0x20 @@ -20743,92 +20743,92 @@ POSSIBILITY OF SUCH DAMAGE. Baud1200 - 1200 baud (actual rate: 1205) + 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral clock frequency 0x0004F000 Baud2400 - 2400 baud (actual rate: 2396) + 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral clock frequency 0x0009D000 Baud4800 - 4800 baud (actual rate: 4808) + 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral clock frequency 0x0013B000 Baud9600 - 9600 baud (actual rate: 9598) + 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral clock frequency 0x00275000 Baud14400 - 14400 baud (actual rate: 14401) + 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral clock frequency 0x003AF000 Baud19200 - 19200 baud (actual rate: 19208) + 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral clock frequency 0x004EA000 Baud28800 - 28800 baud (actual rate: 28777) + 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral clock frequency 0x0075C000 Baud31250 - 31250 baud + 31250 baud when UARTE has 16 MHz peripheral clock frequency 0x00800000 Baud38400 - 38400 baud (actual rate: 38369) + 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral clock frequency 0x009D0000 Baud56000 - 56000 baud (actual rate: 55944) + 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral clock frequency 0x00E50000 Baud57600 - 57600 baud (actual rate: 57554) + 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral clock frequency 0x00EB0000 Baud76800 - 76800 baud (actual rate: 76923) + 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral clock frequency 0x013A9000 Baud115200 - 115200 baud (actual rate: 115108) + 115200 baud (actual rate: 115108) when UARTE has 16 MHz peripheral clock frequency 0x01D60000 Baud230400 - 230400 baud (actual rate: 231884) + 230400 baud (actual rate: 231884) when UARTE has 16 MHz peripheral clock frequency 0x03B00000 Baud250000 - 250000 baud + 250000 baud when UARTE has 16 MHz peripheral clock frequency 0x04000000 Baud460800 - 460800 baud (actual rate: 457143) + 460800 baud (actual rate: 457143) when UARTE has 16 MHz peripheral clock frequency 0x07400000 Baud921600 - 921600 baud (actual rate: 941176) + 921600 baud (actual rate: 941176) when UARTE has 16 MHz peripheral clock frequency 0x0F000000 Baud1M - 1 megabaud + 1 megabaud when UARTE has 16 MHz peripheral clock frequency 0x10000000 @@ -22717,6 +22717,13 @@ POSSIBILITY OF SUCH DAMAGE. Owner ID 4 7 + + + NotEnforced + Owner ID protection is not enforced + 0x0 + + WRITEONCE @@ -22786,7 +22793,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - 0x20 + 0x7 0x4 TASKS_TRIGGER[%s] Description collection: VPR task [n] register @@ -22811,7 +22818,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x4 0x4 SUBSCRIBE_TRIGGER[%s] Description collection: Subscribe configuration for task TASKS_TRIGGER[n] @@ -22841,7 +22848,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x7 0x4 EVENTS_TRIGGERED[%s] Description collection: VPR event [n] register @@ -22871,7 +22878,7 @@ POSSIBILITY OF SUCH DAMAGE. - 0x20 + 0x4 0x4 PUBLISH_TRIGGERED[%s] Description collection: Publish configuration for event EVENTS_TRIGGERED[n] @@ -22908,294 +22915,6 @@ POSSIBILITY OF SUCH DAMAGE. 0x00000000 0x20 - - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] - 0 - 0 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - TRIGGERED16 Enable or disable interrupt for event TRIGGERED[16] @@ -23322,1487 +23041,19 @@ POSSIBILITY OF SUCH DAMAGE. - - TRIGGERED23 - Enable or disable interrupt for event TRIGGERED[23] - 23 - 23 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED24 - Enable or disable interrupt for event TRIGGERED[24] - 24 - 24 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED25 - Enable or disable interrupt for event TRIGGERED[25] - 25 - 25 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED26 - Enable or disable interrupt for event TRIGGERED[26] - 26 - 26 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED27 - Enable or disable interrupt for event TRIGGERED[27] - 27 - 27 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED28 - Enable or disable interrupt for event TRIGGERED[28] - 28 - 28 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED29 - Enable or disable interrupt for event TRIGGERED[29] - 29 - 29 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED30 - Enable or disable interrupt for event TRIGGERED[30] - 30 - 30 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - TRIGGERED31 - Enable or disable interrupt for event TRIGGERED[31] - 31 - 31 - - - Disabled - Disable - 0x0 - - - Enabled - Enable - 0x1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED16 - Write '1' to enable interrupt for event TRIGGERED[16] - 16 - 16 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED17 - Write '1' to enable interrupt for event TRIGGERED[17] - 17 - 17 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED18 - Write '1' to enable interrupt for event TRIGGERED[18] - 18 - 18 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED19 - Write '1' to enable interrupt for event TRIGGERED[19] - 19 - 19 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED20 - Write '1' to enable interrupt for event TRIGGERED[20] - 20 - 20 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED21 - Write '1' to enable interrupt for event TRIGGERED[21] - 21 - 21 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED22 - Write '1' to enable interrupt for event TRIGGERED[22] - 22 - 22 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED23 - Write '1' to enable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED24 - Write '1' to enable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED25 - Write '1' to enable interrupt for event TRIGGERED[25] - 25 - 25 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED26 - Write '1' to enable interrupt for event TRIGGERED[26] - 26 - 26 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED27 - Write '1' to enable interrupt for event TRIGGERED[27] - 27 - 27 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED28 - Write '1' to enable interrupt for event TRIGGERED[28] - 28 - 28 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED29 - Write '1' to enable interrupt for event TRIGGERED[29] - 29 - 29 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED30 - Write '1' to enable interrupt for event TRIGGERED[30] - 30 - 30 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - TRIGGERED31 - Write '1' to enable interrupt for event TRIGGERED[31] - 31 - 31 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Set - Enable - 0x1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - 0x00000000 - 0x20 - - - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] - 0 - 0 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + TRIGGERED16 - Write '1' to disable interrupt for event TRIGGERED[16] + Write '1' to enable interrupt for event TRIGGERED[16] 16 16 @@ -24821,15 +23072,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED17 - Write '1' to disable interrupt for event TRIGGERED[17] + Write '1' to enable interrupt for event TRIGGERED[17] 17 17 @@ -24848,15 +23099,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED18 - Write '1' to disable interrupt for event TRIGGERED[18] + Write '1' to enable interrupt for event TRIGGERED[18] 18 18 @@ -24875,15 +23126,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED19 - Write '1' to disable interrupt for event TRIGGERED[19] + Write '1' to enable interrupt for event TRIGGERED[19] 19 19 @@ -24902,15 +23153,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED20 - Write '1' to disable interrupt for event TRIGGERED[20] + Write '1' to enable interrupt for event TRIGGERED[20] 20 20 @@ -24929,15 +23180,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED21 - Write '1' to disable interrupt for event TRIGGERED[21] + Write '1' to enable interrupt for event TRIGGERED[21] 21 21 @@ -24956,15 +23207,15 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable + Set + Enable 0x1 TRIGGERED22 - Write '1' to disable interrupt for event TRIGGERED[22] + Write '1' to enable interrupt for event TRIGGERED[22] 22 22 @@ -24983,71 +23234,27 @@ POSSIBILITY OF SUCH DAMAGE. write - Clear - Disable - 0x1 - - - - - TRIGGERED23 - Write '1' to disable interrupt for event TRIGGERED[23] - 23 - 23 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable - 0x1 - - - - - TRIGGERED24 - Write '1' to disable interrupt for event TRIGGERED[24] - 24 - 24 - - read - - Disabled - Read: Disabled - 0x0 - - - Enabled - Read: Enabled - 0x1 - - - - write - - Clear - Disable + Set + Enable 0x1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + - TRIGGERED25 - Write '1' to disable interrupt for event TRIGGERED[25] - 25 - 25 + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 read @@ -25071,10 +23278,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED26 - Write '1' to disable interrupt for event TRIGGERED[26] - 26 - 26 + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 read @@ -25098,10 +23305,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED27 - Write '1' to disable interrupt for event TRIGGERED[27] - 27 - 27 + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 read @@ -25125,10 +23332,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED28 - Write '1' to disable interrupt for event TRIGGERED[28] - 28 - 28 + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 read @@ -25152,10 +23359,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED29 - Write '1' to disable interrupt for event TRIGGERED[29] - 29 - 29 + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 read @@ -25179,10 +23386,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED30 - Write '1' to disable interrupt for event TRIGGERED[30] - 30 - 30 + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 read @@ -25206,10 +23413,10 @@ POSSIBILITY OF SUCH DAMAGE. - TRIGGERED31 - Write '1' to disable interrupt for event TRIGGERED[31] - 31 - 31 + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 read @@ -25242,310 +23449,6 @@ POSSIBILITY OF SUCH DAMAGE. 0x00000000 0x20 - - TRIGGERED0 - Read pending status of interrupt for event TRIGGERED[0] - 0 - 0 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED1 - Read pending status of interrupt for event TRIGGERED[1] - 1 - 1 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED2 - Read pending status of interrupt for event TRIGGERED[2] - 2 - 2 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED3 - Read pending status of interrupt for event TRIGGERED[3] - 3 - 3 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED4 - Read pending status of interrupt for event TRIGGERED[4] - 4 - 4 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED5 - Read pending status of interrupt for event TRIGGERED[5] - 5 - 5 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED6 - Read pending status of interrupt for event TRIGGERED[6] - 6 - 6 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED7 - Read pending status of interrupt for event TRIGGERED[7] - 7 - 7 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED8 - Read pending status of interrupt for event TRIGGERED[8] - 8 - 8 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED9 - Read pending status of interrupt for event TRIGGERED[9] - 9 - 9 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED10 - Read pending status of interrupt for event TRIGGERED[10] - 10 - 10 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED11 - Read pending status of interrupt for event TRIGGERED[11] - 11 - 11 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED12 - Read pending status of interrupt for event TRIGGERED[12] - 12 - 12 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED13 - Read pending status of interrupt for event TRIGGERED[13] - 13 - 13 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED14 - Read pending status of interrupt for event TRIGGERED[14] - 14 - 14 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED15 - Read pending status of interrupt for event TRIGGERED[15] - 15 - 15 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - TRIGGERED16 Read pending status of interrupt for event TRIGGERED[16] @@ -25679,177 +23582,6 @@ POSSIBILITY OF SUCH DAMAGE. - - TRIGGERED23 - Read pending status of interrupt for event TRIGGERED[23] - 23 - 23 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED24 - Read pending status of interrupt for event TRIGGERED[24] - 24 - 24 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED25 - Read pending status of interrupt for event TRIGGERED[25] - 25 - 25 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED26 - Read pending status of interrupt for event TRIGGERED[26] - 26 - 26 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED27 - Read pending status of interrupt for event TRIGGERED[27] - 27 - 27 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED28 - Read pending status of interrupt for event TRIGGERED[28] - 28 - 28 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED29 - Read pending status of interrupt for event TRIGGERED[29] - 29 - 29 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED30 - Read pending status of interrupt for event TRIGGERED[30] - 30 - 30 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - - - TRIGGERED31 - Read pending status of interrupt for event TRIGGERED[31] - 31 - 31 - - read - - NotPending - Read: Not pending - 0x0 - - - Pending - Read: Pending - 0x1 - - - @@ -41433,14 +39165,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENSET01 - Enable interrupt - 0x48C - read-write - 0x00000000 - 0x20 - INTENCLR00 Disable interrupt @@ -42072,14 +39796,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENCLR01 - Disable interrupt - 0x494 - read-write - 0x00000000 - 0x20 - INTENSET10 Enable interrupt @@ -42711,14 +40427,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENSET11 - Enable interrupt - 0x4AC - read-write - 0x00000000 - 0x20 - INTENCLR10 Disable interrupt @@ -43350,14 +41058,6 @@ POSSIBILITY OF SUCH DAMAGE. - - INTENCLR11 - Disable interrupt - 0x4B4 - read-write - 0x00000000 - 0x20 - MODE Data rate and modulation @@ -43437,7 +41137,7 @@ POSSIBILITY OF SUCH DAMAGE. Disabled - RADIO is in the Disabled state + RADIO is in the DISABLED state 0x0 @@ -43457,7 +41157,7 @@ POSSIBILITY OF SUCH DAMAGE. RxDisable - RADIO is in the RXDISABLED state + RADIO is in the RXDISABLE state 0x4 @@ -43477,7 +41177,7 @@ POSSIBILITY OF SUCH DAMAGE. TxDisable - RADIO is in the TXDISABLED state + RADIO is in the TXDISABLE state 0xC @@ -43661,7 +41361,7 @@ POSSIBILITY OF SUCH DAMAGE. TXPOWER RADIO output power 0 - 8 + 10 Pos8dBm @@ -44244,15 +41944,10 @@ POSSIBILITY OF SUCH DAMAGE. 0x20 - OFFSET + PTR Data pointer 0 - 15 - - - BASE - 29 - 29 + 31 @@ -45493,21 +43188,17 @@ POSSIBILITY OF SUCH DAMAGE. PACKETPTR - Unspecified + Packet pointer 0xED0 read-write 0x00000000 0x20 - OFFSET + PTR + Data pointer 0 - 15 - - - BASE - 29 - 29 + 31 @@ -49020,11 +46711,6 @@ POSSIBILITY OF SUCH DAMAGE. 400 kbps 0x06400000 - - K1000 - 1000 kbps - 0x0FF00000 - @@ -56093,7 +53779,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x010 2 - 0x004 + 0x008 SEQ[%s] Peripheral tasks. PWM_TASKS_DMA_SEQ @@ -56122,6 +53808,29 @@ POSSIBILITY OF SUCH DAMAGE. + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + @@ -56198,7 +53907,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x090 2 - 0x004 + 0x008 SEQ[%s] Subscribe configuration for tasks PWM_SUBSCRIBE_DMA_SEQ @@ -56237,6 +53946,39 @@ POSSIBILITY OF SUCH DAMAGE. + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + @@ -56937,6 +54679,42 @@ POSSIBILITY OF SUCH DAMAGE. + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP @@ -59077,7 +56855,7 @@ POSSIBILITY OF SUCH DAMAGE. AMOUNT - Description cluster: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. 0x00C read-only 0x00000000 @@ -61670,13 +59448,13 @@ POSSIBILITY OF SUCH DAMAGE. PIN - Analog positive input pin select + GPIO pin selection. 0 4 PORT - GPIO Port selection + GPIO port selection 8 11 @@ -61710,7 +59488,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN - Analog negative input pin select + GPIO pin selection. 0 4 @@ -65913,7 +63691,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 1st piece wise linear function 0x520 read-write - 0x000002C4 + 0x000002D6 0x20 @@ -65929,7 +63707,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 2nd piece wise linear function 0x524 read-write - 0x000002FB + 0x0000032D 0x20 @@ -65945,7 +63723,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 3rd piece wise linear function 0x528 read-write - 0x00000328 + 0x00000384 0x20 @@ -65961,7 +63739,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 4th piece wise linear function 0x52C read-write - 0x00000377 + 0x000003E9 0x20 @@ -65977,7 +63755,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 5th piece wise linear function 0x530 read-write - 0x000003DD + 0x0000046F 0x20 @@ -65993,7 +63771,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 6th piece wise linear function 0x534 read-write - 0x0000046F + 0x00000522 0x20 @@ -66009,7 +63787,7 @@ POSSIBILITY OF SUCH DAMAGE. Slope of 7th piece wise linear function 0x538 read-write - 0x0000055A + 0x000005B7 0x20 @@ -66025,7 +63803,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 1st piece wise linear function 0x540 read-write - 0x00000072 + 0x00000FD6 0x20 @@ -66041,7 +63819,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 2nd piece wise linear function 0x544 read-write - 0x0000000E + 0x00000F76 0x20 @@ -66057,7 +63835,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 3rd piece wise linear function 0x548 read-write - 0x00000FEA + 0x00000F8A 0x20 @@ -66073,7 +63851,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 4th piece wise linear function 0x54C read-write - 0x00000FEA + 0x00000FF8 0x20 @@ -66089,7 +63867,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 5th piece wise linear function 0x550 read-write - 0x0000004A + 0x000000CC 0x20 @@ -66105,7 +63883,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 6th piece wise linear function 0x554 read-write - 0x00000134 + 0x00000207 0x20 @@ -66121,7 +63899,7 @@ POSSIBILITY OF SUCH DAMAGE. y-intercept of 7th piece wise linear function 0x558 read-write - 0x000002C0 + 0x00000558 0x20 @@ -66137,7 +63915,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 1st piece wise linear function 0x560 read-write - 0x000000D8 + 0x000000E2 0x20 @@ -66153,7 +63931,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 2nd piece wise linear function 0x564 read-write - 0x000000EC + 0x00000002 0x20 @@ -66169,7 +63947,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 3rd piece wise linear function 0x568 read-write - 0x000000FF + 0x0000001F 0x20 @@ -66185,7 +63963,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 4th piece wise linear function 0x56C read-write - 0x0000001C + 0x00000038 0x20 @@ -66201,7 +63979,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 5th piece wise linear function 0x570 read-write - 0x0000003C + 0x0000004F 0x20 @@ -66217,7 +63995,7 @@ POSSIBILITY OF SUCH DAMAGE. End point of 6th piece wise linear function 0x574 read-write - 0x00000052 + 0x00000066 0x20 @@ -68225,24 +66003,6 @@ POSSIBILITY OF SUCH DAMAGE. - - TAMPERSWITCH - External tamper switch detector detected an error. - 1 - 1 - - - NotDetected - Not detected. - 0x0 - - - Detected - Detected. - 0x1 - - - PROTECT Error detected for the protected signals. @@ -68467,764 +66227,22 @@ POSSIBILITY OF SUCH DAMAGE. read-write 0x500 - STRUCT0 + 1 + 0x020 + DOMAIN[%s] Unspecified - TAMPC_PROTECT_STRUCT0 + TAMPC_PROTECT_DOMAIN read-write 0x000 - 1 - 0x020 - DOMAIN[%s] + DBGEN Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN + TAMPC_PROTECT_DOMAIN_DBGEN read-write 0x000 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - NIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_NIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of niden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPIDEN - read-write - 0x010 - - CTRL - Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPNIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_DOMAIN_SPNIDEN - read-write - 0x018 - - CTRL - Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spniden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - 1 - 0x010 - AP[%s] - Unspecified - TAMPC_PROTECT_STRUCT0_AP - read-write - 0x200 - - DBGEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_DBGEN - read-write - 0x000 - - CTRL - Description cluster: Control register to enable invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of dbgen signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - SPIDEN - Unspecified - TAMPC_PROTECT_STRUCT0_AP_SPIDEN - read-write - 0x008 - - CTRL - Description cluster: Control register to enable secure priviliged invasive (halting) debug in domain n's access port. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of spiden signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n's access port. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - - ACTIVESHIELD - Enable active shield detector. - TAMPC_PROTECT_STRUCT0_ACTIVESHIELD - read-write - 0x400 CTRL - Control register for active shield detector enable signal. + Description cluster: Control register for invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -69232,7 +66250,7 @@ POSSIBILITY OF SUCH DAMAGE. VALUE - Set value of active shield enable signal. + Set value of dbgen signal. 0 0 @@ -69309,7 +66327,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for active shield detector enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -69338,14 +66356,14 @@ POSSIBILITY OF SUCH DAMAGE. - TAMPERSWITCH - Enable tamper switch detector. - TAMPC_PROTECT_STRUCT0_TAMPERSWITCH + NIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_NIDEN read-write - 0x408 + 0x008 CTRL - Control register for external tamper switch enable signal. + Description cluster: Control register for non-invasive debug enable for the local debug components within domain n. 0x000 read-write 0x00000010 @@ -69353,7 +66371,7 @@ POSSIBILITY OF SUCH DAMAGE. VALUE - Set value of tamper switch enable signal. + Set value of niden signal. 0 0 @@ -69430,7 +66448,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for external tamper switch detector enable signal. + Description cluster: Status register for non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -69459,22 +66477,22 @@ POSSIBILITY OF SUCH DAMAGE. - CRACENTAMP - Enable tamper detector from CRACEN. - TAMPC_PROTECT_STRUCT0_CRACENTAMP + SPIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPIDEN read-write - 0x438 + 0x010 CTRL - Control register for CRACEN tamper detector enable signal. + Description cluster: Control register for secure priviliged invasive (halting) debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of CRACEN tamper detector enable signal. + Set value of spiden signal. 0 0 @@ -69551,7 +66569,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for CRACEN tamper detector enable signal. + Description cluster: Status register for secure priviliged invasive (halting) debug enable for domain n. 0x004 read-write 0x00000000 @@ -69580,22 +66598,22 @@ POSSIBILITY OF SUCH DAMAGE. - GLITCHSLOWDOMAIN - Enable slow domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHSLOWDOMAIN + SPNIDEN + Unspecified + TAMPC_PROTECT_DOMAIN_SPNIDEN read-write - 0x440 + 0x018 CTRL - Control register for slow domain glitch detectors enable signal. + Description cluster: Control register for secure priviliged non-invasive debug enable for the local debug components within domain n. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of slow domain glitch detectors enable signal. + Set value of spniden signal. 0 0 @@ -69672,7 +66690,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for slow domain glitch detectors enable signal. + Description cluster: Status register for secure priviliged non-invasive debug enable for domain n. 0x004 read-write 0x00000000 @@ -69700,23 +66718,32 @@ POSSIBILITY OF SUCH DAMAGE. + + + 1 + 0x010 + AP[%s] + Unspecified + TAMPC_PROTECT_AP + read-write + 0x200 - GLITCHFASTDOMAIN - Enable fast domain glitch detectors. - TAMPC_PROTECT_STRUCT0_GLITCHFASTDOMAIN + DBGEN + Unspecified + TAMPC_PROTECT_AP_DBGEN read-write - 0x448 + 0x000 CTRL - Control register for fast domain glitch detectors enable signal. + Description cluster: Control register to enable invasive (halting) debug in domain n's access port. 0x000 read-write - 0x00000011 + 0x00000010 0x20 VALUE - Set value of fast domain glitch detector's enable signal. + Set value of dbgen signal. 0 0 @@ -69793,7 +66820,7 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status register for fast domain glitch detectors enable signal. + Description cluster: Status register for invasive (halting) debug enable for domain n's access port. 0x004 read-write 0x00000000 @@ -69821,369 +66848,853 @@ POSSIBILITY OF SUCH DAMAGE. - - EXTRESETEN - Trigger a reset when tamper is detected by the active shield or tamper switch detector. - TAMPC_PROTECT_STRUCT0_EXTRESETEN + + + ACTIVESHIELD + Enable active shield detector. + TAMPC_PROTECT_ACTIVESHIELD + read-write + 0x400 + + CTRL + Control register for active shield detector enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of active shield enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for active shield detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + CRACENTAMP + Enable tamper detector from CRACEN. + TAMPC_PROTECT_CRACENTAMP + read-write + 0x438 + + CTRL + Control register for CRACEN tamper detector enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of CRACEN tamper detector enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for CRACEN tamper detector enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHSLOWDOMAIN + Enable slow domain glitch detectors. + TAMPC_PROTECT_GLITCHSLOWDOMAIN + read-write + 0x440 + + CTRL + Control register for slow domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of slow domain glitch detectors enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for slow domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + GLITCHFASTDOMAIN + Enable fast domain glitch detectors. + TAMPC_PROTECT_GLITCHFASTDOMAIN + read-write + 0x448 + + CTRL + Control register for fast domain glitch detectors enable signal. + 0x000 + read-write + 0x00000011 + 0x20 + + + VALUE + Set value of fast domain glitch detector's enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for fast domain glitch detectors enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + EXTRESETEN + Trigger a reset when tamper is detected by the external tamper detectors. + TAMPC_PROTECT_EXTRESETEN + read-write + 0x470 + + CTRL + Control register for external tamper reset enable signal. + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Set value of external tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for external tamper reset enable signal. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + INTRESETEN + Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. + TAMPC_PROTECT_INTRESETEN + read-write + 0x478 + + CTRL + Control register for internal tamper reset enable signal. + 0x000 read-write - 0x470 - - CTRL - Control register for external tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of external tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for external tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - INTRESETEN - Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector. - TAMPC_PROTECT_STRUCT0_INTRESETEN + 0x00000010 + 0x20 + + + VALUE + Set value of internal tamper reset enable signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for internal tamper reset enable signal. + 0x004 read-write - 0x478 - - CTRL - Control register for internal tamper reset enable signal. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of internal tamper reset enable signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for internal tamper reset enable signal. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - - - ERASEPROTECT - Device erase protection. - TAMPC_PROTECT_STRUCT0_ERASEPROTECT + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + + + + ERASEPROTECT + Device erase protection. + TAMPC_PROTECT_ERASEPROTECT + read-write + 0x480 + + CTRL + Control register for erase protection. + 0x000 read-write - 0x480 - - CTRL - Control register for erase protection. - 0x000 - read-write - 0x00000010 - 0x20 - - - VALUE - Set value of eraseprotect signal. - 0 - 0 - - - Low - Signal is logic 0. - 0x0 - - - High - Signal is logic 1. - 0x1 - - - - - LOCK - Lock this register to prevent changes to the VALUE field until next reset. - 1 - 1 - writeonce - oneToSet - - - Disabled - Lock disabled. - 0x0 - - - Enabled - Lock enabled. - 0x1 - - - - - WRITEPROTECTION - The write protection must be cleared to allow updates to the VALUE field. - 4 - 7 - - - Disabled - Read: Write protection is disabled. - 0x0 - - - Enabled - Read: Write protection is enabled. - 0x1 - - - Clear - Write: Value to clear write protection. - 0xF - - - - - KEY - Required write key for upper 16 bits. Must be included in all register write operations. - 16 - 31 - write-only - - - KEY - Write key value. - 0x50FA - - - - - - - STATUS - Status register for eraseprotect. - 0x004 - read-write - 0x00000000 - oneToClear - 0x20 - - - ERROR - Error detection status. - 0 - 0 - - - NoError - No error detected. - 0x0 - - - Error - Error detected. - 0x1 - - - - - - + 0x00000010 + 0x20 + + + VALUE + Set value of eraseprotect signal. + 0 + 0 + + + Low + Signal is logic 0. + 0x0 + + + High + Signal is logic 1. + 0x1 + + + + + LOCK + Lock this register to prevent changes to the VALUE field until next reset. + 1 + 1 + writeonce + oneToSet + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + WRITEPROTECTION + The write protection must be cleared to allow updates to the VALUE field. + 4 + 7 + + + Disabled + Read: Write protection is disabled. + 0x0 + + + Enabled + Read: Write protection is enabled. + 0x1 + + + Clear + Write: Value to clear write protection. + 0xF + + + + + KEY + Required write key for upper 16 bits. Must be included in all register write operations. + 16 + 31 + write-only + + + KEY + Write key value. + 0x50FA + + + + + + + STATUS + Status register for eraseprotect. + 0x004 + read-write + 0x00000000 + oneToClear + 0x20 + + + ERROR + Error detection status. + 0 + 0 + + + NoError + No error detected. + 0x0 + + + Error + Error detected. + 0x1 + + + + + @@ -79678,6 +77189,11 @@ POSSIBILITY OF SUCH DAMAGE. GRTC LFCLK clock source is system LFCLK 0x1 + + LFLPRC + GRTC LFCLK clock source is LFLPRC + 0x2 + @@ -86471,7 +83987,7 @@ POSSIBILITY OF SUCH DAMAGE. Programmable capacitance of XL1 and XL2 0x004 read-write - 0x00000000 + 0x00000017 0x20 diff --git a/mdk/nrf54l15_flpr_peripherals.h b/mdk/nrf54l15_flpr_peripherals.h index f1b004bfb..b137c4a48 100644 --- a/mdk/nrf54l15_flpr_peripherals.h +++ b/mdk/nrf54l15_flpr_peripherals.h @@ -40,34 +40,33 @@ POSSIBILITY OF SUCH DAMAGE. #endif #include -/* Domain definition */ -#define NRF_DOMAIN NRF_DOMAIN_FLPR - /*VPR CSR registers*/ #define VPRCSR_PRESENT 1 #define VPRCSR_COUNT 1 -#define VPRCSR_HARTNUM 0 /*!< HARTNUM: 0 */ -#define VPRCSR_MCLICBASERESET 0x00001000 /*!< MCLICBASE: 0x00001000 */ +#define VPRCSR_HARTNUM 14 /*!< HARTNUM: 14 */ +#define VPRCSR_MCLICBASERESET 0xF0000000 /*!< MCLICBASE: 0xF0000000 */ #define VPRCSR_MULDIV 2 /*!< MULDIV: 2 */ #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ #define VPRCSR_DBG 1 /*!< DBG: 1 */ -#define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ +#define VPRCSR_REMAP 1 /*!< Code patching (REMAP): 1 */ #define VPRCSR_BUSWIDTH 64 /*!< BUSWIDTH: 64 */ -#define VPRCSR_BKPT 2 /*!< BKPT: 2 */ -#define VPRCSR_VIOPINS 0x00000000 /*!< CSR VIOPINS value: 0x00000000 */ +#define VPRCSR_BKPT 1 /*!< BKPT: 1 */ +#define VPRCSR_RETAINED 1 /*!< (unspecified) */ +#define VPRCSR_VIOPINS 0x0000FFFF /*!< CSR VIOPINS value: 0x0000FFFF */ #define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ #define VPRCSR_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPRCSR_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPRCSR_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ +#define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPRCSR_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPRCSR_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ #define VPRCSR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ #define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ -#define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ +#define VPRCSR_BEXT 1 /*!< Bit-Manipulation extension: 1 */ #define VPRCSR_CACHE_EN 1 /*!< (unspecified) */ +#define VPRCSR_CACHEEXTRATAGBUF 0 /*!< CACHEEXTRATAGBUF: 0 */ #define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ #define VPRCSR_VPR_BUS_PRIO 1 /*!< (unspecified) */ #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ @@ -77,9 +76,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CLIC_COUNT 1 #define VPRCLIC_IRQ_COUNT 32 -#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ -#define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ -#define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..270 */ +#define VPRCLIC_IRQNUM_MAX 270 /*!< Supported interrupts (IRQNUM): 0..270 */ +#define VPRCLIC_IRQNUM_SIZE 271 /*!< Supported interrupts (IRQNUM): 0..270 */ #define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ #define VPRCLIC_CLIC_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ #define VPRCLIC_CLIC_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ @@ -262,8 +261,8 @@ POSSIBILITY OF SUCH DAMAGE. #define KMU_PRESENT 1 #define KMU_COUNT 1 -#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots */ -#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot */ +#define KMU_KEYSLOTNUM 256 /*!< Number of keyslots is 256 */ +#define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ /*Accelerated Address Resolver*/ #define AAR_PRESENT 1 @@ -310,12 +309,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ -#define CRACEN_PKEDATA 0x51808000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ -#define CRACEN_PKECODE 0x5180C000 /*!< Must be read and written using aligned access, i.e. using an operation - where a word-aligned address is used for a word, or a halfword-aligned - address is used for a halfword access.*/ +#define CRACEN_PKEDATA 0x51808000 /*!< PKE data (address 0x51808000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ +#define CRACEN_PKECODE 0x5180C000 /*!< PKE code (address 0x5180C000) must be read and written using aligned + access, i.e. using an operation where a word-aligned address is used + for a word, or a halfword-aligned address is used for a halfword + access.*/ /*Serial Peripheral Interface Master with EasyDMA*/ #define SPIM_PRESENT 1 @@ -485,8 +486,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_COUNT 5 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE00_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE00_CORE_FREQUENCY 128 /*!< Peripheral clock frequency is 128 MHz. */ @@ -495,8 +496,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE20_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -505,8 +506,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE21_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -515,8 +516,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE22_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -525,8 +526,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_MAX 7 /*!< (unspecified) */ -#define UARTE30_EASYDMA_MAXCNT_SIZE 8 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ +#define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ @@ -637,22 +638,27 @@ POSSIBILITY OF SUCH DAMAGE. #define VPR00_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ #define VPR00_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ -#define VPR00_RAM_BASE_ADDR 0x00000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x00000000 */ -#define VPR00_RAM_SZ 0 /*!< VPR RAM size (RAM_SZ): 0 (Value in bytes is computed as 2^(RAM size))*/ +#define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ +#define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM + size))*/ +#define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ +#define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ -#define VPR00_VPRSAVEADDR 0x00000000 /*!< VPR context save address: 0x00000000 */ +#define VPR00_VPRSAVEADDR 0x2003FE00 /*!< VPR context save address: 0x2003FE00 */ #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ -#define VPR00_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ -#define VPR00_VEVIF_TASKS_MASK 0xFFFFFFFF /*!< Mask of supported VEVIF tasks: 0xFFFFFFFF */ -#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_MAX 31 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NDPPI_SIZE 32 /*!< VEVIF DPPI channels: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ -#define VPR00_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ +#define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ +#define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ +#define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ +#define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ +#define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ +#define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ /*GPIO Port*/ @@ -920,7 +926,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_COUNT 1 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ -#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ @@ -974,7 +980,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TAMPC_PRESENT 1 #define TAMPC_COUNT 1 +#define TAMPC_APSPIDEN 0 /*!< (unspecified) */ #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 0 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 0 */ +#define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ /*Inter-IC Sound*/ #define I2S_PRESENT 1 @@ -1015,7 +1023,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GRTC_PWMREGS 1 /*!< (unspecified) */ #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ #define GRTC_CLKSELREG 1 /*!< (unspecified) */ -#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ /*Comparator*/ @@ -1031,8 +1039,10 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_COUNT 2 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT30_HAS_INTEN 0 /*!< (unspecified) */ #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ +#define WDT31_HAS_INTEN 0 /*!< (unspecified) */ /*Clock management*/ #define CLOCK_PRESENT 1 @@ -1058,6 +1068,257 @@ POSSIBILITY OF SUCH DAMAGE. #define REGULATORS_PRESENT 1 #define REGULATORS_COUNT 1 +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core + frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz + core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 + MHz core frequency*/ + NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 + MHz core frequency*/ +} NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; + +/* ==================================================== Baudrate settings ==================================================== */ +/** + * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency + */ +typedef enum { + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core + frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 + MHz core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz + core frequency*/ + NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 + MHz core frequency*/ +} NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; + #ifdef __cplusplus } diff --git a/mdk/nrf54l15_interim.h b/mdk/nrf54l15_interim.h index 678a1780d..75f397f4d 100644 --- a/mdk/nrf54l15_interim.h +++ b/mdk/nrf54l15_interim.h @@ -37,19 +37,12 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(NRF54L15_XXAA) - #define NRF_DOMAINS_t NRF_DOMAINID_Type - #define NRF_DOMAIN_COUNT NRF_DOMAIN_GLOBAL + 1 + #define NRF_DOMAIN_COUNT NRF_DOMAIN_NONE + 1 #define ADDRESS_BUS_Pos (18UL) #define ADDRESS_BUS_Msk (0x3FUL << ADDRESS_BUS_Pos) - typedef enum { - NRF_OWNER_NONE = 0, - NRF_OWNER_APPLICATION = 1, - NRF_OWNER_KMU = 2, - } NRF_OWNERID_Type; - #define PPIB00_CH_NUM 8 #define PPIB10_CH_NUM 8 diff --git a/mdk/nrf54l15_peripherals.h b/mdk/nrf54l15_peripherals.h index 59cc791b6..ce0f444a4 100644 --- a/mdk/nrf54l15_peripherals.h +++ b/mdk/nrf54l15_peripherals.h @@ -39,20 +39,6 @@ POSSIBILITY OF SUCH DAMAGE. extern "C" { #endif -/* Domain IDs */ - typedef enum { - NRF_DOMAIN_APPLICATION = 1, - NRF_DOMAIN_FLPR = 2, - NRF_DOMAIN_GLOBAL = 3, -} NRF_DOMAINID_Type; - -/* Processor IDs */ - typedef enum { - NRF_PROCESSOR_APPLICATION = 1, - NRF_PROCESSOR_FLPR = 2, - NRF_PROCESSOR_GLOBAL = 3, -} NRF_PROCESSORID_Type; - #if defined(NRF_APPLICATION) #include "nrf54l15_application_peripherals.h" #elif defined(NRF_FLPR) diff --git a/mdk/nrf54l15_types.h b/mdk/nrf54l15_types.h index 81f110160..0e4102d27 100644 --- a/mdk/nrf54l15_types.h +++ b/mdk/nrf54l15_types.h @@ -70,6 +70,33 @@ POSSIBILITY OF SUCH DAMAGE. #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ #endif +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_NONE = 0, /*!< No domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_CM33 = 1, /*!< (unspecified) */ + NRF_PROCESSOR_VPR = 2, /*!< (unspecified) */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 1, /*!< Application Core */ + NRF_OWNER_KMU = 2, /*!< KMU Accesses */ +} NRF_OWNERID_Type; + /* ========================================= Start of section using anonymous unions ========================================= */ @@ -758,17 +785,17 @@ typedef struct { typedef struct { __IOM NRF_CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ } NRF_CACHEDATA_SET_Type; /*!< Size = 64 (0x040) */ - #define CACHEDATA_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ - #define CACHEDATA_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ - #define CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + #define CACHEDATA_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEDATA_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ /* ==================================================== Struct CACHEDATA ===================================================== */ /** * @brief CACHEDATA */ typedef struct { /*!< CACHEDATA Structure */ - __IOM NRF_CACHEDATA_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CACHEDATA_Type; /*!< Size = 16384 (0x4000) */ + __IOM NRF_CACHEDATA_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEDATA_Type; /*!< Size = 8192 (0x2000) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -853,17 +880,17 @@ typedef struct { typedef struct { __IOM NRF_CACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ } NRF_CACHEINFO_SET_Type; /*!< Size = 8 (0x008) */ - #define CACHEINFO_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ - #define CACHEINFO_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ - #define CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + #define CACHEINFO_SET_MaxCount (128UL) /*!< Size of SET[128] array. */ + #define CACHEINFO_SET_MaxIndex (127UL) /*!< Max index of SET[128] array. */ + #define CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[128] array. */ /* ==================================================== Struct CACHEINFO ===================================================== */ /** * @brief CACHEINFO */ typedef struct { /*!< CACHEINFO Structure */ - __IOM NRF_CACHEINFO_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CACHEINFO_Type; /*!< Size = 2048 (0x800) */ + __IOM NRF_CACHEINFO_SET_Type SET[128]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CACHEINFO_Type; /*!< Size = 1024 (0x400) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -1323,8 +1350,8 @@ typedef struct { __IM uint32_t CLICCFG; /*!< (@ 0x00000000) CLIC configuration. */ __IM uint32_t CLICINFO; /*!< (@ 0x00000004) CLIC information. */ __IM uint32_t RESERVED[1022]; - __IOM uint32_t CLICINT[480]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ -} NRF_CLIC_CLIC_Type; /*!< Size = 6016 (0x1780) */ + __IOM uint32_t CLICINT[271]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ +} NRF_CLIC_CLIC_Type; /*!< Size = 5180 (0x143C) */ /* CLIC_CLIC_CLICCFG: CLIC configuration. */ #define CLIC_CLIC_CLICCFG_ResetValue (0x00000011UL) /*!< Reset value of CLICCFG register. */ @@ -1369,10 +1396,10 @@ typedef struct { /* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */ - #define CLIC_CLIC_CLICINT_MaxCount (480UL) /*!< Max size of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_MaxIndex (479UL) /*!< Max index of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[480] array. */ - #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[480] register. */ + #define CLIC_CLIC_CLICINT_MaxCount (271UL) /*!< Max size of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MaxIndex (270UL) /*!< Max index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[271] array. */ + #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[271] register. */ /* IP @Bit 0 : Interrupt Pending bit. */ #define CLIC_CLIC_CLICINT_IP_Pos (0UL) /*!< Position of IP field. */ @@ -1436,7 +1463,7 @@ typedef struct { */ typedef struct { /*!< CLIC Structure */ __IOM NRF_CLIC_CLIC_Type CLIC; /*!< (@ 0x00000000) (unspecified) */ - } NRF_CLIC_Type; /*!< Size = 6016 (0x1780) */ + } NRF_CLIC_Type; /*!< Size = 5180 (0x143C) */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -3333,16 +3360,7 @@ typedef struct { __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ __IM uint32_t RESERVED2[60]; __IOM uint32_t ENABLE; /*!< (@ 0x00000400) Enable CRACEN peripheral modules. */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM uint32_t SEEDVALID; /*!< (@ 0x00000404) Marks the SEED register as valid */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t SEEDVALID; /*!< (@ 0x00000404) Marks the SEED register as valid */ __IM uint32_t RESERVED3[2]; __OM uint32_t SEED[12]; /*!< (@ 0x00000410) Seed word [n] for symmetric and asymmetric key generation. This register is only writable from KMU.*/ @@ -13066,16 +13084,7 @@ typedef struct { typedef struct { __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ } NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ #define GRTC_CC_MaxCount (12UL) /*!< Size of CC[12] array. */ @@ -15714,9 +15723,10 @@ typedef struct { #define GRTC_CLKCFG_CLKSEL_Pos (16UL) /*!< Position of CLKSEL field. */ #define GRTC_CLKCFG_CLKSEL_Msk (0x3UL << GRTC_CLKCFG_CLKSEL_Pos) /*!< Bit mask of CLKSEL field. */ #define GRTC_CLKCFG_CLKSEL_Min (0x0UL) /*!< Min enumerator value of CLKSEL field. */ - #define GRTC_CLKCFG_CLKSEL_Max (0x1UL) /*!< Max enumerator value of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Max (0x2UL) /*!< Max enumerator value of CLKSEL field. */ #define GRTC_CLKCFG_CLKSEL_LFXO (0x0UL) /*!< GRTC LFCLK clock source is LFXO */ #define GRTC_CLKCFG_CLKSEL_SystemLFCLK (0x1UL) /*!< GRTC LFCLK clock source is system LFCLK */ + #define GRTC_CLKCFG_CLKSEL_LFLPRC (0x2UL) /*!< GRTC LFCLK clock source is LFLPRC */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -20748,7 +20758,7 @@ typedef struct { } NRF_OSCILLATORS_XOSC32KI_Type; /*!< Size = 56 (0x038) */ /* OSCILLATORS_XOSC32KI_INTCAP: Programmable capacitance of XL1 and XL2 */ - #define OSCILLATORS_XOSC32KI_INTCAP_ResetValue (0x00000000UL) /*!< Reset value of INTCAP register. */ + #define OSCILLATORS_XOSC32KI_INTCAP_ResetValue (0x00000017UL) /*!< Reset value of INTCAP register. */ /* VAL @Bits 0..5 : Crystal load capacitor as seen by the crystal across its terminals, including pin capacitance but excluding PCB stray capacitance. */ @@ -22079,7 +22089,9 @@ typedef struct { typedef struct { __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA.*/ -} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 4 (0x004) */ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ #define PWM_TASKS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ #define PWM_TASKS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ #define PWM_TASKS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ @@ -22097,6 +22109,17 @@ typedef struct { #define PWM_TASKS_DMA_SEQ_START_START_Trigger (0x1UL) /*!< Trigger task */ +/* PWM_TASKS_DMA_SEQ_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Msk (0x1UL << PWM_TASKS_DMA_SEQ_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + /* ================================================== Struct PWM_TASKS_DMA =================================================== */ /** @@ -22104,7 +22127,7 @@ typedef struct { */ typedef struct { __OM NRF_PWM_TASKS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral tasks. */ -} NRF_PWM_TASKS_DMA_Type; /*!< Size = 8 (0x008) */ +} NRF_PWM_TASKS_DMA_Type; /*!< Size = 16 (0x010) */ /* ============================================== Struct PWM_SUBSCRIBE_DMA_SEQ =============================================== */ @@ -22113,7 +22136,8 @@ typedef struct { */ typedef struct { __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ -} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 4 (0x004) */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ #define PWM_SUBSCRIBE_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ #define PWM_SUBSCRIBE_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ #define PWM_SUBSCRIBE_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ @@ -22136,6 +22160,24 @@ typedef struct { #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Enabled (0x1UL) /*!< Enable subscription */ +/* PWM_SUBSCRIBE_DMA_SEQ_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + /* ================================================ Struct PWM_SUBSCRIBE_DMA ================================================= */ /** @@ -22143,7 +22185,7 @@ typedef struct { */ typedef struct { __IOM NRF_PWM_SUBSCRIBE_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Subscribe configuration for tasks */ -} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 8 (0x008) */ +} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 16 (0x010) */ /* ================================================ Struct PWM_EVENTS_DMA_SEQ ================================================ */ @@ -22372,8 +22414,7 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, - updated after the END event. Also updated after each - MATCH event.*/ + updated after the END event.*/ __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ __IM uint32_t RESERVED1[2]; __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is @@ -22403,9 +22444,7 @@ typedef struct { #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Max (0xFFFFUL) /*!< Max size of MAXCNT field. */ -/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each - MATCH event. */ - +/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ #define PWM_DMA_SEQ_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ /* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ @@ -22470,12 +22509,12 @@ typedef struct { cause PWM generation to start if not running.*/ __IM uint32_t RESERVED1; __OM NRF_PWM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000010) Peripheral tasks. */ - __IM uint32_t RESERVED2[27]; + __IM uint32_t RESERVED2[25]; __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000088) Subscribe configuration for task NEXTSTEP */ __IM uint32_t RESERVED3; __IOM NRF_PWM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x00000090) Subscribe configuration for tasks */ - __IM uint32_t RESERVED4[27]; + __IM uint32_t RESERVED4[25]; __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no longer generated*/ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) First PWM period started on sequence n */ @@ -22840,6 +22879,24 @@ typedef struct { #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ +/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ0_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ1_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut */ + /* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ @@ -24419,13 +24476,9 @@ typedef struct { /* RADIO_DFEPACKET_PTR: Data pointer */ #define RADIO_DFEPACKET_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ -/* OFFSET @Bits 0..15 : Data pointer */ - #define RADIO_DFEPACKET_PTR_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ - #define RADIO_DFEPACKET_PTR_OFFSET_Msk (0xFFFFUL << RADIO_DFEPACKET_PTR_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ - -/* BASE @Bit 29 : (unspecified) */ - #define RADIO_DFEPACKET_PTR_BASE_Pos (29UL) /*!< Position of BASE field. */ - #define RADIO_DFEPACKET_PTR_BASE_Msk (0x1UL << RADIO_DFEPACKET_PTR_BASE_Pos) /*!< Bit mask of BASE field. */ +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* RADIO_DFEPACKET_MAXCNT: Maximum number of bytes to transfer */ @@ -24896,53 +24949,51 @@ typedef struct { __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[33]; __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ - __IOM uint32_t INTENSET01; /*!< (@ 0x0000048C) Enable interrupt */ + __IM uint32_t RESERVED9; __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ - __IOM uint32_t INTENCLR01; /*!< (@ 0x00000494) Disable interrupt */ - __IM uint32_t RESERVED9[4]; + __IM uint32_t RESERVED10[5]; __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ - __IOM uint32_t INTENSET11; /*!< (@ 0x000004AC) Enable interrupt */ + __IM uint32_t RESERVED11; __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ - __IOM uint32_t INTENCLR11; /*!< (@ 0x000004B4) Disable interrupt */ - __IM uint32_t RESERVED10[18]; + __IM uint32_t RESERVED12[19]; __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ - __IM uint32_t RESERVED11[7]; + __IM uint32_t RESERVED13[7]; __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ - __IM uint32_t RESERVED12[3]; + __IM uint32_t RESERVED14[3]; __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED15; __IOM uint32_t DATAWHITE; /*!< (@ 0x00000540) Data whitening configuration */ - __IM uint32_t RESERVED14[112]; + __IM uint32_t RESERVED16[112]; __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED17; __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ - __IM uint32_t RESERVED16[123]; + __IM uint32_t RESERVED18[123]; __IOM uint32_t FECONFIG; /*!< (@ 0x00000908) Config register */ - __IM uint32_t RESERVED17[253]; + __IM uint32_t RESERVED19[253]; __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)*/ __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ - __IM uint32_t RESERVED18[2]; + __IM uint32_t RESERVED20[2]; __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ - __IM uint32_t RESERVED19[4]; + __IM uint32_t RESERVED21[4]; __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ - __IM uint32_t RESERVED20[41]; + __IM uint32_t RESERVED22[41]; __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ - __IM uint32_t RESERVED21; + __IM uint32_t RESERVED23; __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ @@ -24957,16 +25008,16 @@ typedef struct { __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ - __IM uint32_t RESERVED22[3]; + __IM uint32_t RESERVED24[3]; __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ - __IM uint32_t RESERVED23[3]; + __IM uint32_t RESERVED25[3]; __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ - __IM uint32_t RESERVED24[3]; - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) (unspecified) */ - __IM uint32_t RESERVED25[75]; + __IM uint32_t RESERVED26[3]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) Packet pointer */ + __IM uint32_t RESERVED27[75]; __IOM NRF_RADIO_CSTONES_Type CSTONES; /*!< (@ 0x00001000) (unspecified) */ __IOM NRF_RADIO_RTT_Type RTT; /*!< (@ 0x00001050) (unspecified) */ } NRF_RADIO_Type; /*!< Size = 4196 (0x1064) */ @@ -27090,15 +27141,15 @@ typedef struct { #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ #define RADIO_STATE_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ #define RADIO_STATE_STATE_Max (0xCUL) /*!< Max enumerator value of STATE field. */ - #define RADIO_STATE_STATE_Disabled (0x0UL) /*!< RADIO is in the Disabled state */ + #define RADIO_STATE_STATE_Disabled (0x0UL) /*!< RADIO is in the DISABLED state */ #define RADIO_STATE_STATE_RxRu (0x1UL) /*!< RADIO is in the RXRU state */ #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ - #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLED state */ + #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLE state */ #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ - #define RADIO_STATE_STATE_TxDisable (0xCUL) /*!< RADIO is in the TXDISABLED state */ + #define RADIO_STATE_STATE_TxDisable (0xCUL) /*!< RADIO is in the TXDISABLE state */ /* RADIO_EDCTRL: IEEE 802.15.4 energy detect control */ @@ -27192,9 +27243,9 @@ typedef struct { /* RADIO_TXPOWER: Output power */ #define RADIO_TXPOWER_ResetValue (0x00000013UL) /*!< Reset value of TXPOWER register. */ -/* TXPOWER @Bits 0..8 : RADIO output power */ +/* TXPOWER @Bits 0..10 : RADIO output power */ #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ - #define RADIO_TXPOWER_TXPOWER_Msk (0x1FFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Msk (0x7FFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Min (0x0UL) /*!< Min enumerator value of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Max (0x130UL) /*!< Max enumerator value of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x033UL) /*!< +8 dBm */ @@ -27979,16 +28030,12 @@ typedef struct { #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ -/* RADIO_PACKETPTR: (unspecified) */ +/* RADIO_PACKETPTR: Packet pointer */ #define RADIO_PACKETPTR_ResetValue (0x00000000UL) /*!< Reset value of PACKETPTR register. */ -/* OFFSET @Bits 0..15 : (unspecified) */ - #define RADIO_PACKETPTR_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ - #define RADIO_PACKETPTR_OFFSET_Msk (0xFFFFUL << RADIO_PACKETPTR_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ - -/* BASE @Bit 29 : (unspecified) */ - #define RADIO_PACKETPTR_BASE_Pos (29UL) /*!< Position of BASE field. */ - #define RADIO_PACKETPTR_BASE_Msk (0x1UL << RADIO_PACKETPTR_BASE_Pos) /*!< Bit mask of BASE field. */ +/* PTR @Bits 0..31 : Data pointer */ + #define RADIO_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define RADIO_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ @@ -28408,6 +28455,9 @@ typedef struct { /* OWNER @Bits 4..7 : Owner ID */ #define RRAMC_REGION_CONFIG_OWNER_Pos (4UL) /*!< Position of OWNER field. */ #define RRAMC_REGION_CONFIG_OWNER_Msk (0xFUL << RRAMC_REGION_CONFIG_OWNER_Pos) /*!< Bit mask of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Min (0x0UL) /*!< Min enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_Max (0x0UL) /*!< Max enumerator value of OWNER field. */ + #define RRAMC_REGION_CONFIG_OWNER_NotEnforced (0x0UL) /*!< Owner ID protection is not enforced */ /* WRITEONCE @Bit 12 : Write-once */ #define RRAMC_REGION_CONFIG_WRITEONCE_Pos (12UL) /*!< Position of WRITEONCE field. */ @@ -29596,19 +29646,8 @@ typedef struct { * @brief CH [SAADC_CH] (unspecified) */ typedef struct { - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ - }; - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ } NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ @@ -29619,11 +29658,11 @@ typedef struct { /* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ -/* PIN @Bits 0..4 : Analog positive input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELP_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field. */ -/* PORT @Bits 8..11 : GPIO Port selection */ +/* PORT @Bits 8..11 : GPIO port selection */ #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ @@ -29639,7 +29678,7 @@ typedef struct { /* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ -/* PIN @Bits 0..4 : Analog negative input pin select */ +/* PIN @Bits 0..4 : GPIO pin selection. */ #define SAADC_CH_PSELN_PIN_Pos (0UL) /*!< Position of PIN field. */ #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -30946,16 +30985,7 @@ typedef struct { __IM uint32_t RESERVED3[125]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ __IM uint32_t RESERVED4; - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) (unspecified) */ __IM uint32_t RESERVED5; __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ @@ -34173,7 +34203,7 @@ typedef struct { #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL) /*!< Max size of CH[24] array. */ #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL) /*!< Max index of CH[24] array. */ #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL) /*!< Min index of CH[24] array. */ - #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register. */ + #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[24] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34196,7 +34226,7 @@ typedef struct { #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL) /*!< Max size of CHG[8] array. */ #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL) /*!< Max index of CHG[8] array. */ #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[8] array. */ - #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[8] register. */ + #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00100010UL) /*!< Reset value of CHG[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34232,7 +34262,7 @@ typedef struct { #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL) /*!< Max size of CH[8] array. */ #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ - #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[8] register. */ + #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34255,7 +34285,7 @@ typedef struct { #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array. */ #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array. */ #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array. */ - #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[8] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34291,7 +34321,7 @@ typedef struct { #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL) /*!< Max size of PIN[32] array. */ #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL) /*!< Max index of PIN[32] array. */ #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL) /*!< Min index of PIN[32] array. */ - #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00000000UL) /*!< Reset value of PIN[32] register. */ + #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00100010UL) /*!< Reset value of PIN[32] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34320,7 +34350,7 @@ typedef struct { } NRF_SPU_FEATURE_CRACEN_Type; /*!< Size = 4 (0x004) */ /* SPU_FEATURE_CRACEN_SEED: Configuration for CRACEN SEED */ - #define SPU_FEATURE_CRACEN_SEED_ResetValue (0x00000000UL) /*!< Reset value of SEED register. */ + #define SPU_FEATURE_CRACEN_SEED_ResetValue (0x00020010UL) /*!< Reset value of SEED register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_CRACEN_SEED_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34358,7 +34388,7 @@ typedef struct { #define SPU_FEATURE_GRTC_CC_MaxCount (24UL) /*!< Max size of CC[24] array. */ #define SPU_FEATURE_GRTC_CC_MaxIndex (23UL) /*!< Max index of CC[24] array. */ #define SPU_FEATURE_GRTC_CC_MinIndex (0UL) /*!< Min index of CC[24] array. */ - #define SPU_FEATURE_GRTC_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[24] register. */ + #define SPU_FEATURE_GRTC_CC_ResetValue (0x00100010UL) /*!< Reset value of CC[24] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34378,7 +34408,7 @@ typedef struct { /* SPU_FEATURE_GRTC_PWMCONFIG: Configuration of feature for PWMCONFIG of GRTC */ - #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00000000UL) /*!< Reset value of PWMCONFIG register. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00100010UL) /*!< Reset value of PWMCONFIG register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34399,7 +34429,7 @@ typedef struct { /* SPU_FEATURE_GRTC_CLK: Configuration of features for CLKOUT/CLKCFG of GRTC */ - #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00000000UL) /*!< Reset value of CLK register. */ + #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00100010UL) /*!< Reset value of CLK register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_CLK_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34419,7 +34449,7 @@ typedef struct { /* SPU_FEATURE_GRTC_SYSCOUNTER: Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC */ - #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTER register. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00100010UL) /*!< Reset value of SYSCOUNTER register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34443,7 +34473,7 @@ typedef struct { #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (16UL) /*!< Max size of INTERRUPT[16] array. */ #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (15UL) /*!< Max index of INTERRUPT[16] array. */ #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[16] array. */ - #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[16] register. */ + #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[16] register. */ /* SECATTR @Bit 4 : SECATTR feature */ #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ @@ -34472,16 +34502,7 @@ typedef union { struct { __IM uint32_t RESERVED[32]; __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC; /*!< (@ 0x00000080) (unspecified) */ - #if defined(_GNUC_) - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpedantic" - #endif - union { - __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ - }; - #if defined(_GNUC_) - #pragma GCC diagnostic pop - #endif + __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ __IM uint32_t RESERVED1[32]; #if defined(_GNUC_) #pragma GCC diagnostic push @@ -35084,80 +35105,13 @@ typedef struct { -/* ============================================= Struct TAMPC_PROTECT_AP_SPIDEN ============================================== */ -/** - * @brief SPIDEN [TAMPC_PROTECT_AP_SPIDEN] (unspecified) - */ -typedef struct { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register to enable secure priviliged invasive - (halting) debug in domain n's access port.*/ - __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for secure priviliged invasive - (halting) debug enable for domain n's access port.*/ -} NRF_TAMPC_PROTECT_AP_SPIDEN_Type; /*!< Size = 8 (0x008) */ - -/* TAMPC_PROTECT_AP_SPIDEN_CTRL: Control register to enable secure priviliged invasive (halting) debug in domain n's access - port. */ - - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ - -/* VALUE @Bit 0 : Set value of spiden signal. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE - field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ - -/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ - -/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Pos) /*!< Bit - mask of WRITEPROTECTION field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ - -/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ - #define TAMPC_PROTECT_AP_SPIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ - - -/* TAMPC_PROTECT_AP_SPIDEN_STATUS: Status register for secure priviliged invasive (halting) debug enable for domain n's access - port. */ - - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ - -/* ERROR @Bit 0 : Error detection status. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR - field.*/ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ - #define TAMPC_PROTECT_AP_SPIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ - - - /* ================================================= Struct TAMPC_PROTECT_AP ================================================= */ /** * @brief AP [TAMPC_PROTECT_AP] (unspecified) */ typedef struct { __IOM NRF_TAMPC_PROTECT_AP_DBGEN_Type DBGEN; /*!< (@ 0x00000000) (unspecified) */ - __IOM NRF_TAMPC_PROTECT_AP_SPIDEN_Type SPIDEN; /*!< (@ 0x00000008) (unspecified) */ + __IM uint32_t RESERVED[2]; } NRF_TAMPC_PROTECT_AP_Type; /*!< Size = 16 (0x010) */ #define TAMPC_PROTECT_AP_MaxCount (1UL) /*!< Size of AP[1] array. */ #define TAMPC_PROTECT_AP_MaxIndex (0UL) /*!< Max index of AP[1] array. */ @@ -35229,71 +35183,6 @@ typedef struct { -/* ============================================ Struct TAMPC_PROTECT_TAMPERSWITCH ============================================ */ -/** - * @brief TAMPERSWITCH [TAMPC_PROTECT_TAMPERSWITCH] Enable tamper switch detector. - */ -typedef struct { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for external tamper switch enable - signal.*/ - __IOM uint32_t STATUS; /*!< (@ 0x00000004) Status register for external tamper switch detector - enable signal.*/ -} NRF_TAMPC_PROTECT_TAMPERSWITCH_Type; /*!< Size = 8 (0x008) */ - -/* TAMPC_PROTECT_TAMPERSWITCH_CTRL: Control register for external tamper switch enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register. */ - -/* VALUE @Bit 0 : Set value of tamper switch enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Pos) /*!< Bit mask of VALUE - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1. */ - -/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Pos) /*!< Bit mask of LOCK - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ - -/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Pos) - /*!< Bit mask of WRITEPROTECTION field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection. */ - -/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Pos (16UL) /*!< Position of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Pos) /*!< Bit mask of KEY - field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value. */ - - -/* TAMPC_PROTECT_TAMPERSWITCH_STATUS: Status register for external tamper switch detector enable signal. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ - -/* ERROR @Bit 0 : Error detection status. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Pos) /*!< Bit mask of - ERROR field.*/ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_NoError (0x0UL) /*!< No error detected. */ - #define TAMPC_PROTECT_TAMPERSWITCH_STATUS_ERROR_Error (0x1UL) /*!< Error detected. */ - - - /* ============================================= Struct TAMPC_PROTECT_CRACENTAMP ============================================= */ /** * @brief CRACENTAMP [TAMPC_PROTECT_CRACENTAMP] Enable tamper detector from CRACEN. @@ -35489,9 +35378,7 @@ typedef struct { /* ============================================= Struct TAMPC_PROTECT_EXTRESETEN ============================================= */ /** - * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the active shield or tamper switch - detector. - + * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the external tamper detectors. */ typedef struct { __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control register for external tamper reset enable @@ -35691,14 +35578,13 @@ typedef union { __IOM NRF_TAMPC_PROTECT_AP_Type AP[1]; /*!< (@ 0x00000200) (unspecified) */ __IM uint32_t RESERVED1[124]; __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector. */ - __IOM NRF_TAMPC_PROTECT_TAMPERSWITCH_Type TAMPERSWITCH; /*!< (@ 0x00000408) Enable tamper switch detector. */ - __IM uint32_t RESERVED2[10]; + __IM uint32_t RESERVED2[12]; __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN. */ __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors. */ __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors. */ __IM uint32_t RESERVED3[8]; __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the - active shield or tamper switch detector.*/ + external tamper detectors.*/ __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the glitch detectors, signal protector or CRACEN tamper detector.*/ @@ -35848,14 +35734,6 @@ typedef union { #define TAMPC_STATUS_ACTIVESHIELD_NotDetected (0x0UL) /*!< Not detected. */ #define TAMPC_STATUS_ACTIVESHIELD_Detected (0x1UL) /*!< Detected. */ -/* TAMPERSWITCH @Bit 1 : External tamper switch detector detected an error. */ - #define TAMPC_STATUS_TAMPERSWITCH_Pos (1UL) /*!< Position of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Msk (0x1UL << TAMPC_STATUS_TAMPERSWITCH_Pos) /*!< Bit mask of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Min (0x0UL) /*!< Min enumerator value of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_Max (0x1UL) /*!< Max enumerator value of TAMPERSWITCH field. */ - #define TAMPC_STATUS_TAMPERSWITCH_NotDetected (0x0UL) /*!< Not detected. */ - #define TAMPC_STATUS_TAMPERSWITCH_Detected (0x1UL) /*!< Detected. */ - /* PROTECT @Bit 4 : Error detected for the protected signals. */ #define TAMPC_STATUS_PROTECT_Pos (4UL) /*!< Position of PROTECT field. */ #define TAMPC_STATUS_PROTECT_Msk (0x1UL << TAMPC_STATUS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ @@ -36093,7 +35971,7 @@ typedef union { /* TEMP_A0: Slope of 1st piece wise linear function */ - #define TEMP_A0_ResetValue (0x000002C4UL) /*!< Reset value of A0 register. */ + #define TEMP_A0_ResetValue (0x000002D6UL) /*!< Reset value of A0 register. */ /* A0 @Bits 0..11 : Slope of 1st piece wise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ @@ -36101,7 +35979,7 @@ typedef union { /* TEMP_A1: Slope of 2nd piece wise linear function */ - #define TEMP_A1_ResetValue (0x000002FBUL) /*!< Reset value of A1 register. */ + #define TEMP_A1_ResetValue (0x0000032DUL) /*!< Reset value of A1 register. */ /* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ @@ -36109,7 +35987,7 @@ typedef union { /* TEMP_A2: Slope of 3rd piece wise linear function */ - #define TEMP_A2_ResetValue (0x00000328UL) /*!< Reset value of A2 register. */ + #define TEMP_A2_ResetValue (0x00000384UL) /*!< Reset value of A2 register. */ /* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ @@ -36117,7 +35995,7 @@ typedef union { /* TEMP_A3: Slope of 4th piece wise linear function */ - #define TEMP_A3_ResetValue (0x00000377UL) /*!< Reset value of A3 register. */ + #define TEMP_A3_ResetValue (0x000003E9UL) /*!< Reset value of A3 register. */ /* A3 @Bits 0..11 : Slope of 4th piece wise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ @@ -36125,7 +36003,7 @@ typedef union { /* TEMP_A4: Slope of 5th piece wise linear function */ - #define TEMP_A4_ResetValue (0x000003DDUL) /*!< Reset value of A4 register. */ + #define TEMP_A4_ResetValue (0x0000046FUL) /*!< Reset value of A4 register. */ /* A4 @Bits 0..11 : Slope of 5th piece wise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ @@ -36133,7 +36011,7 @@ typedef union { /* TEMP_A5: Slope of 6th piece wise linear function */ - #define TEMP_A5_ResetValue (0x0000046FUL) /*!< Reset value of A5 register. */ + #define TEMP_A5_ResetValue (0x00000522UL) /*!< Reset value of A5 register. */ /* A5 @Bits 0..11 : Slope of 6th piece wise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ @@ -36141,7 +36019,7 @@ typedef union { /* TEMP_A6: Slope of 7th piece wise linear function */ - #define TEMP_A6_ResetValue (0x0000055AUL) /*!< Reset value of A6 register. */ + #define TEMP_A6_ResetValue (0x000005B7UL) /*!< Reset value of A6 register. */ /* A6 @Bits 0..11 : Slope of 7th piece wise linear function */ #define TEMP_A6_A6_Pos (0UL) /*!< Position of A6 field. */ @@ -36149,7 +36027,7 @@ typedef union { /* TEMP_B0: y-intercept of 1st piece wise linear function */ - #define TEMP_B0_ResetValue (0x00000072UL) /*!< Reset value of B0 register. */ + #define TEMP_B0_ResetValue (0x00000FD6UL) /*!< Reset value of B0 register. */ /* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ @@ -36157,7 +36035,7 @@ typedef union { /* TEMP_B1: y-intercept of 2nd piece wise linear function */ - #define TEMP_B1_ResetValue (0x0000000EUL) /*!< Reset value of B1 register. */ + #define TEMP_B1_ResetValue (0x00000F76UL) /*!< Reset value of B1 register. */ /* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ @@ -36165,7 +36043,7 @@ typedef union { /* TEMP_B2: y-intercept of 3rd piece wise linear function */ - #define TEMP_B2_ResetValue (0x00000FEAUL) /*!< Reset value of B2 register. */ + #define TEMP_B2_ResetValue (0x00000F8AUL) /*!< Reset value of B2 register. */ /* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ @@ -36173,7 +36051,7 @@ typedef union { /* TEMP_B3: y-intercept of 4th piece wise linear function */ - #define TEMP_B3_ResetValue (0x00000FEAUL) /*!< Reset value of B3 register. */ + #define TEMP_B3_ResetValue (0x00000FF8UL) /*!< Reset value of B3 register. */ /* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ @@ -36181,7 +36059,7 @@ typedef union { /* TEMP_B4: y-intercept of 5th piece wise linear function */ - #define TEMP_B4_ResetValue (0x0000004AUL) /*!< Reset value of B4 register. */ + #define TEMP_B4_ResetValue (0x000000CCUL) /*!< Reset value of B4 register. */ /* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ @@ -36189,7 +36067,7 @@ typedef union { /* TEMP_B5: y-intercept of 6th piece wise linear function */ - #define TEMP_B5_ResetValue (0x00000134UL) /*!< Reset value of B5 register. */ + #define TEMP_B5_ResetValue (0x00000207UL) /*!< Reset value of B5 register. */ /* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ @@ -36197,7 +36075,7 @@ typedef union { /* TEMP_B6: y-intercept of 7th piece wise linear function */ - #define TEMP_B6_ResetValue (0x000002C0UL) /*!< Reset value of B6 register. */ + #define TEMP_B6_ResetValue (0x00000558UL) /*!< Reset value of B6 register. */ /* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */ #define TEMP_B6_B6_Pos (0UL) /*!< Position of B6 field. */ @@ -36205,7 +36083,7 @@ typedef union { /* TEMP_T0: End point of 1st piece wise linear function */ - #define TEMP_T0_ResetValue (0x000000D8UL) /*!< Reset value of T0 register. */ + #define TEMP_T0_ResetValue (0x000000E2UL) /*!< Reset value of T0 register. */ /* T0 @Bits 0..7 : End point of 1st piece wise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ @@ -36213,7 +36091,7 @@ typedef union { /* TEMP_T1: End point of 2nd piece wise linear function */ - #define TEMP_T1_ResetValue (0x000000ECUL) /*!< Reset value of T1 register. */ + #define TEMP_T1_ResetValue (0x00000002UL) /*!< Reset value of T1 register. */ /* T1 @Bits 0..7 : End point of 2nd piece wise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ @@ -36221,7 +36099,7 @@ typedef union { /* TEMP_T2: End point of 3rd piece wise linear function */ - #define TEMP_T2_ResetValue (0x000000FFUL) /*!< Reset value of T2 register. */ + #define TEMP_T2_ResetValue (0x0000001FUL) /*!< Reset value of T2 register. */ /* T2 @Bits 0..7 : End point of 3rd piece wise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ @@ -36229,7 +36107,7 @@ typedef union { /* TEMP_T3: End point of 4th piece wise linear function */ - #define TEMP_T3_ResetValue (0x0000001CUL) /*!< Reset value of T3 register. */ + #define TEMP_T3_ResetValue (0x00000038UL) /*!< Reset value of T3 register. */ /* T3 @Bits 0..7 : End point of 4th piece wise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ @@ -36237,7 +36115,7 @@ typedef union { /* TEMP_T4: End point of 5th piece wise linear function */ - #define TEMP_T4_ResetValue (0x0000003CUL) /*!< Reset value of T4 register. */ + #define TEMP_T4_ResetValue (0x0000004FUL) /*!< Reset value of T4 register. */ /* T4 @Bits 0..7 : End point of 5th piece wise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ @@ -36245,7 +36123,7 @@ typedef union { /* TEMP_T5: End point of 6th piece wise linear function */ - #define TEMP_T5_ResetValue (0x00000052UL) /*!< Reset value of T5 register. */ + #define TEMP_T5_ResetValue (0x00000066UL) /*!< Reset value of T5 register. */ /* T5 @Bits 0..7 : End point of 6th piece wise linear function */ #define TEMP_T5_T5_Pos (0UL) /*!< Position of T5 field. */ @@ -41068,11 +40946,10 @@ typedef struct { #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field. */ - #define TWIM_FREQUENCY_FREQUENCY_Max (0xFF00000UL) /*!< Max enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Max (0x6400000UL) /*!< Max enumerator value of FREQUENCY field. */ #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ - #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */ /* TWIM_ADDRESS: Address used in the TWI transfer */ @@ -44694,24 +44571,39 @@ typedef struct { #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Min (0x4F000UL) /*!< Min enumerator value of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field. */ - #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ - #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ - #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ - #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ + #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral + clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud when UARTE has 16 MHz peripheral clock frequency */ + #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) when UARTE has 16 MHz + peripheral clock frequency*/ + #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud when UARTE has 16 MHz peripheral clock frequency */ /* UARTE_CONFIG: Configuration of parity, hardware flow control, framesize, and packet timeout. */ @@ -44821,11 +44713,10 @@ typedef struct { /* PALL @Bits 0..31 : (unspecified) */ #define UICR_APPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field. */ - #define UICR_APPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_APPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_APPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU registers and - memory mapped addresses, and locks TAMPC PROTECT.DOMAIN - DBGEN and NIDEN signal protectors.*/ + #define UICR_APPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal + protectors unlocked and under CPU control.*/ /* UICR_APPROTECT_PROTECT1: Access port protection */ @@ -44834,11 +44725,10 @@ typedef struct { /* PALL @Bits 0..31 : (unspecified) */ #define UICR_APPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field. */ - #define UICR_APPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_APPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_APPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU registers and - memory mapped addresses, and locks TAMPC PROTECT.DOMAIN - DBGEN and NIDEN signal protectors.*/ + #define UICR_APPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_APPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal + protectors unlocked and under CPU control.*/ @@ -44862,12 +44752,10 @@ typedef struct { #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU - registers and memory mapped addresses, and locks - TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal - protectors.*/ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN + signal protectors unlocked and under CPU control.*/ /* UICR_SECUREAPPROTECT_PROTECT1: Access port protection register */ @@ -44877,12 +44765,10 @@ typedef struct { #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU - registers and memory mapped addresses, and locks - TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN signal - protectors.*/ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN + signal protectors unlocked and under CPU control.*/ @@ -44906,11 +44792,10 @@ typedef struct { #define UICR_AUXAPPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_AUXAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_AUXAPPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_AUXAPPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_AUXAPPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU registers - and memory mapped addresses, and locks TAMPC - PROTECT.AP[0] DBGEN signal protector.*/ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal + protectors unlocked and under CPU control.*/ /* UICR_AUXAPPROTECT_PROTECT1: Access port protection register */ @@ -44920,11 +44805,10 @@ typedef struct { #define UICR_AUXAPPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_AUXAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_AUXAPPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_AUXAPPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_AUXAPPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Blocks debugger read/write access to all CPU registers - and memory mapped addresses, and locks TAMPC - PROTECT.AP[0] DBGEN signal protector.*/ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_AUXAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN and SPIDEN signal + protectors unlocked and under CPU control.*/ @@ -44948,11 +44832,11 @@ typedef struct { #define UICR_ERASEPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_ERASEPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_ERASEPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_ERASEPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_ERASEPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Protected, the device cannot be erased using the CTRL-AP - Erase all function and TAMPC PROTECT.ERASEPROTECT signal - protector is locked.*/ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< The device can be erased using the CTRL-AP Erase all + function and TAMPC PROTECT.ERASEPROTECT signal + protector is unlocked.*/ /* UICR_ERASEPROTECT_PROTECT1: Erase protection */ @@ -44962,11 +44846,11 @@ typedef struct { #define UICR_ERASEPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_ERASEPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field.*/ - #define UICR_ERASEPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field. */ - #define UICR_ERASEPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field. */ - #define UICR_ERASEPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Protected, the device cannot be erased using the CTRL-AP - Erase all function and TAMPC PROTECT.ERASEPROTECT signal - protector is locked.*/ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field. */ + #define UICR_ERASEPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< The device canbe erased using the CTRL-AP Erase all + function and TAMPC PROTECT.ERASEPROTECT signal + protector is unlocked.*/ @@ -45159,6 +45043,53 @@ typedef struct { #define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field. */ +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VDMADESCRIPTOR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct VDMADESCRIPTOR ================================================== */ +/** + * @brief Job descriptor for vector-based DMA. + */ + typedef struct { /*!< VDMADESCRIPTOR Structure */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Pointer to data buffer. */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Job configuration. Configuration of attributes and + buffer length.*/ + } NRF_VDMADESCRIPTOR_Type; /*!< Size = 8 (0x008) */ + +/* VDMADESCRIPTOR_PTR: Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */ + #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* ATTRIBUTE @Bits 24..29 : Job attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0xBUL) /*!< Min enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0xEUL) /*!< Max enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarHash (0x0BUL) /*!< Hash attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarPrand (0x0CUL) /*!< Prand attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarIrk (0x0DUL) /*!< Irk attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAlen (0x0BUL) /*!< Alen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMlen (0x0CUL) /*!< Mlen attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAdata (0x0DUL) /*!< Adata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMdata (0x0EUL) /*!< Mdata attribute */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_EcbData (0x0BUL) /*!< EcbData attribute */ + + #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ /* =========================================================================================================================== */ @@ -45878,28 +45809,31 @@ typedef struct { * @brief VPR peripheral registers */ typedef struct { /*!< VPR Structure */ - __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) VPR task [n] register */ - __IOM uint32_t SUBSCRIBE_TRIGGER[32]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ - __IOM uint32_t EVENTS_TRIGGERED[32]; /*!< (@ 0x00000100) VPR event [n] register */ - __IOM uint32_t PUBLISH_TRIGGERED[32]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ - __IM uint32_t RESERVED[64]; + __OM uint32_t TASKS_TRIGGER[23]; /*!< (@ 0x00000000) VPR task [n] register */ + __IM uint32_t RESERVED[9]; + __IOM uint32_t SUBSCRIBE_TRIGGER[4]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_TRIGGERED[23]; /*!< (@ 0x00000100) VPR event [n] register */ + __IM uint32_t RESERVED2[9]; + __IOM uint32_t PUBLISH_TRIGGERED[4]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ + __IM uint32_t RESERVED3[92]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ - __IM uint32_t RESERVED1[60]; + __IM uint32_t RESERVED4[60]; __IOM NRF_VPR_DEBUGIF_Type DEBUGIF; /*!< (@ 0x00000400) (unspecified) */ - __IM uint32_t RESERVED2[191]; + __IM uint32_t RESERVED5[191]; __IOM uint32_t CPURUN; /*!< (@ 0x00000800) State of the CPU after a core reset */ - __IM uint32_t RESERVED3; + __IM uint32_t RESERVED6; __IOM uint32_t INITPC; /*!< (@ 0x00000808) Initial value of the PC at CPU start. */ } NRF_VPR_Type; /*!< Size = 2060 (0x80C) */ /* VPR_TASKS_TRIGGER: VPR task [n] register */ - #define VPR_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ - #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + #define VPR_TASKS_TRIGGER_MaxCount (7UL) /*!< Max size of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MaxIndex (22UL) /*!< Max index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_MinIndex (16UL) /*!< Min index of TASKS_TRIGGER[23] array. */ + #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[23] register. */ /* TASKS_TRIGGER @Bit 0 : VPR task [n] register */ #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ @@ -45911,10 +45845,10 @@ typedef struct { /* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */ - #define VPR_SUBSCRIBE_TRIGGER_MaxCount (32UL) /*!< Max size of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (31UL) /*!< Max index of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[32] array. */ - #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[32] register. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL) /*!< Max size of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (3UL) /*!< Max index of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[4] array. */ + #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[4] register. */ /* EN @Bit 31 : Subscription enable bit */ #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ @@ -45926,10 +45860,10 @@ typedef struct { /* VPR_EVENTS_TRIGGERED: VPR event [n] register */ - #define VPR_EVENTS_TRIGGERED_MaxCount (32UL) /*!< Max size of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_MaxIndex (31UL) /*!< Max index of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[32] array. */ - #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register. */ + #define VPR_EVENTS_TRIGGERED_MaxCount (7UL) /*!< Max size of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MaxIndex (22UL) /*!< Max index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_MinIndex (16UL) /*!< Min index of EVENTS_TRIGGERED[23] array. */ + #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[23] register. */ /* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */ #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ @@ -45942,10 +45876,10 @@ typedef struct { /* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */ - #define VPR_PUBLISH_TRIGGERED_MaxCount (32UL) /*!< Max size of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_MaxIndex (31UL) /*!< Max index of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[32] array. */ - #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[32] register. */ + #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL) /*!< Max size of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_MaxIndex (3UL) /*!< Max index of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[4] array. */ + #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[4] register. */ /* EN @Bit 31 : Publication enable bit */ #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ @@ -45959,134 +45893,6 @@ typedef struct { /* VPR_INTEN: Enable or disable interrupt */ #define VPR_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ -/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ - #define VPR_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Msk (0x1UL << VPR_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ - #define VPR_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Msk (0x1UL << VPR_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ - #define VPR_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Msk (0x1UL << VPR_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ - #define VPR_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Msk (0x1UL << VPR_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ - #define VPR_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Msk (0x1UL << VPR_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ - #define VPR_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Msk (0x1UL << VPR_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ - #define VPR_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Msk (0x1UL << VPR_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ - #define VPR_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Msk (0x1UL << VPR_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ - #define VPR_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Msk (0x1UL << VPR_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ - #define VPR_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Msk (0x1UL << VPR_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ - #define VPR_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Msk (0x1UL << VPR_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ - #define VPR_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Msk (0x1UL << VPR_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ - #define VPR_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Msk (0x1UL << VPR_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ - #define VPR_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Msk (0x1UL << VPR_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ - #define VPR_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Msk (0x1UL << VPR_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ - #define VPR_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Msk (0x1UL << VPR_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ - /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ #define VPR_INTEN_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -46143,226 +45949,10 @@ typedef struct { #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ -/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ - #define VPR_INTEN_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Msk (0x1UL << VPR_INTEN_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTEN_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ - #define VPR_INTEN_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Msk (0x1UL << VPR_INTEN_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTEN_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ - #define VPR_INTEN_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Msk (0x1UL << VPR_INTEN_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTEN_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ - #define VPR_INTEN_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Msk (0x1UL << VPR_INTEN_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTEN_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ - #define VPR_INTEN_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Msk (0x1UL << VPR_INTEN_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTEN_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ - #define VPR_INTEN_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Msk (0x1UL << VPR_INTEN_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTEN_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ - #define VPR_INTEN_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Msk (0x1UL << VPR_INTEN_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTEN_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ - #define VPR_INTEN_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Msk (0x1UL << VPR_INTEN_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTEN_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ - -/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ - #define VPR_INTEN_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Msk (0x1UL << VPR_INTEN_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTEN_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ - #define VPR_INTEN_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ - /* VPR_INTENSET: Enable interrupt */ #define VPR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ -/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ - #define VPR_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Msk (0x1UL << VPR_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ - #define VPR_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Msk (0x1UL << VPR_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ - #define VPR_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Msk (0x1UL << VPR_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ - #define VPR_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Msk (0x1UL << VPR_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ - #define VPR_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Msk (0x1UL << VPR_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ - #define VPR_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Msk (0x1UL << VPR_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ - #define VPR_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Msk (0x1UL << VPR_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ - #define VPR_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Msk (0x1UL << VPR_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ - #define VPR_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Msk (0x1UL << VPR_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ - #define VPR_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Msk (0x1UL << VPR_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ - #define VPR_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Msk (0x1UL << VPR_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ - #define VPR_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Msk (0x1UL << VPR_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ - #define VPR_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Msk (0x1UL << VPR_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ - #define VPR_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Msk (0x1UL << VPR_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ - #define VPR_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Msk (0x1UL << VPR_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ - #define VPR_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Msk (0x1UL << VPR_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ - /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ #define VPR_INTENSET_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -46426,235 +46016,10 @@ typedef struct { #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ -/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ - #define VPR_INTENSET_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Msk (0x1UL << VPR_INTENSET_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTENSET_TRIGGERED23_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ - #define VPR_INTENSET_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Msk (0x1UL << VPR_INTENSET_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTENSET_TRIGGERED24_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ - #define VPR_INTENSET_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Msk (0x1UL << VPR_INTENSET_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTENSET_TRIGGERED25_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ - #define VPR_INTENSET_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Msk (0x1UL << VPR_INTENSET_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTENSET_TRIGGERED26_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ - #define VPR_INTENSET_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Msk (0x1UL << VPR_INTENSET_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTENSET_TRIGGERED27_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ - #define VPR_INTENSET_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Msk (0x1UL << VPR_INTENSET_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTENSET_TRIGGERED28_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ - #define VPR_INTENSET_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Msk (0x1UL << VPR_INTENSET_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTENSET_TRIGGERED29_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ - #define VPR_INTENSET_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Msk (0x1UL << VPR_INTENSET_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTENSET_TRIGGERED30_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ - #define VPR_INTENSET_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Msk (0x1UL << VPR_INTENSET_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTENSET_TRIGGERED31_Set (0x1UL) /*!< Enable */ - #define VPR_INTENSET_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENSET_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ - /* VPR_INTENCLR: Disable interrupt */ #define VPR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ -/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ - #define VPR_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Msk (0x1UL << VPR_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ - #define VPR_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Msk (0x1UL << VPR_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ - #define VPR_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Msk (0x1UL << VPR_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ - #define VPR_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Msk (0x1UL << VPR_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ - #define VPR_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Msk (0x1UL << VPR_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ - #define VPR_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Msk (0x1UL << VPR_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ - #define VPR_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Msk (0x1UL << VPR_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ - #define VPR_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Msk (0x1UL << VPR_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ - #define VPR_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Msk (0x1UL << VPR_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ - #define VPR_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Msk (0x1UL << VPR_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ - #define VPR_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Msk (0x1UL << VPR_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ - #define VPR_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Msk (0x1UL << VPR_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ - #define VPR_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Msk (0x1UL << VPR_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ - #define VPR_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Msk (0x1UL << VPR_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ - #define VPR_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Msk (0x1UL << VPR_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ - #define VPR_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Msk (0x1UL << VPR_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ - /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ #define VPR_INTENCLR_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -46718,219 +46083,10 @@ typedef struct { #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ -/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ - #define VPR_INTENCLR_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Msk (0x1UL << VPR_INTENCLR_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTENCLR_TRIGGERED23_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ - #define VPR_INTENCLR_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Msk (0x1UL << VPR_INTENCLR_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTENCLR_TRIGGERED24_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ - #define VPR_INTENCLR_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Msk (0x1UL << VPR_INTENCLR_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTENCLR_TRIGGERED25_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ - #define VPR_INTENCLR_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Msk (0x1UL << VPR_INTENCLR_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTENCLR_TRIGGERED26_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ - #define VPR_INTENCLR_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Msk (0x1UL << VPR_INTENCLR_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTENCLR_TRIGGERED27_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ - #define VPR_INTENCLR_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Msk (0x1UL << VPR_INTENCLR_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTENCLR_TRIGGERED28_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ - #define VPR_INTENCLR_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Msk (0x1UL << VPR_INTENCLR_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTENCLR_TRIGGERED29_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ - #define VPR_INTENCLR_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Msk (0x1UL << VPR_INTENCLR_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTENCLR_TRIGGERED30_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ - -/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ - #define VPR_INTENCLR_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Msk (0x1UL << VPR_INTENCLR_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTENCLR_TRIGGERED31_Clear (0x1UL) /*!< Disable */ - #define VPR_INTENCLR_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ - #define VPR_INTENCLR_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ - /* VPR_INTPEND: Pending interrupts */ #define VPR_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ -/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ - #define VPR_INTPEND_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Msk (0x1UL << VPR_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ - #define VPR_INTPEND_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ - #define VPR_INTPEND_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Msk (0x1UL << VPR_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ - #define VPR_INTPEND_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ - #define VPR_INTPEND_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Msk (0x1UL << VPR_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ - #define VPR_INTPEND_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ - #define VPR_INTPEND_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Msk (0x1UL << VPR_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ - #define VPR_INTPEND_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ - #define VPR_INTPEND_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Msk (0x1UL << VPR_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ - #define VPR_INTPEND_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ - #define VPR_INTPEND_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Msk (0x1UL << VPR_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ - #define VPR_INTPEND_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ - #define VPR_INTPEND_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Msk (0x1UL << VPR_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ - #define VPR_INTPEND_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ - #define VPR_INTPEND_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Msk (0x1UL << VPR_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ - #define VPR_INTPEND_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ - #define VPR_INTPEND_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Msk (0x1UL << VPR_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ - #define VPR_INTPEND_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ - #define VPR_INTPEND_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Msk (0x1UL << VPR_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ - #define VPR_INTPEND_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ - #define VPR_INTPEND_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Msk (0x1UL << VPR_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ - #define VPR_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ - #define VPR_INTPEND_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Msk (0x1UL << VPR_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ - #define VPR_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ - #define VPR_INTPEND_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Msk (0x1UL << VPR_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ - #define VPR_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ - #define VPR_INTPEND_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Msk (0x1UL << VPR_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ - #define VPR_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ - #define VPR_INTPEND_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Msk (0x1UL << VPR_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ - #define VPR_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ - #define VPR_INTPEND_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Msk (0x1UL << VPR_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ - #define VPR_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ - /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ #define VPR_INTPEND_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ @@ -46987,78 +46143,6 @@ typedef struct { #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ -/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ - #define VPR_INTPEND_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Msk (0x1UL << VPR_INTPEND_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ - #define VPR_INTPEND_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ - #define VPR_INTPEND_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Msk (0x1UL << VPR_INTPEND_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ - #define VPR_INTPEND_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ - #define VPR_INTPEND_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Msk (0x1UL << VPR_INTPEND_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ - #define VPR_INTPEND_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ - #define VPR_INTPEND_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Msk (0x1UL << VPR_INTPEND_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ - #define VPR_INTPEND_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ - #define VPR_INTPEND_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Msk (0x1UL << VPR_INTPEND_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ - #define VPR_INTPEND_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ - #define VPR_INTPEND_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Msk (0x1UL << VPR_INTPEND_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ - #define VPR_INTPEND_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ - #define VPR_INTPEND_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Msk (0x1UL << VPR_INTPEND_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ - #define VPR_INTPEND_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ - #define VPR_INTPEND_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Msk (0x1UL << VPR_INTPEND_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ - #define VPR_INTPEND_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ - -/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ - #define VPR_INTPEND_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Msk (0x1UL << VPR_INTPEND_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ - #define VPR_INTPEND_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ - #define VPR_INTPEND_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ - /* VPR_CPURUN: State of the CPU after a core reset */ #define VPR_CPURUN_ResetValue (0x00000000UL) /*!< Reset value of CPURUN register. */ @@ -47132,7 +46216,7 @@ typedef struct { * @brief MISA [VPRCSR_MISA] Machine ISA */ #define VPRCSR_MISA (0x00000301ul) - #define VPRCSR_MISA_ResetValue (0x40001014UL) /*!< Reset value of MISA register. */ + #define VPRCSR_MISA_ResetValue (0x40001016UL) /*!< Reset value of MISA register. */ /* A @Bit 0 : Atomic extension */ #define VPRCSR_MISA_A_Pos (0UL) /*!< Position of A field. */ @@ -47372,7 +46456,7 @@ typedef struct { * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base */ #define VPRCSR_MCLICBASE (0x00000350ul) - #define VPRCSR_MCLICBASE_ResetValue (0x00001000UL) /*!< Reset value of MCLICBASE register. */ + #define VPRCSR_MCLICBASE_ResetValue (0xF0000000UL) /*!< Reset value of MCLICBASE register. */ /* VAL @Bits 0..31 : CLIC base address value */ #define VPRCSR_MCLICBASE_VAL_Pos (0UL) /*!< Position of VAL field. */ @@ -47416,8 +46500,8 @@ typedef struct { #define VPRCSR_TDATA1_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ #define VPRCSR_TDATA1_TYPE_Max (0xFUL) /*!< Max enumerator value of TYPE field. */ #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL) /*!< There is no trigger at this tselect */ - #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address/data match trigger. The remaining bits in - this register act as described in mcontrol*/ + #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address match trigger. The remaining bits in this + register act as described in mcontrol*/ #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL) /*!< This trigger is a remapping trigger. The remaining bits in this register behave as described in remapping functionality*/ @@ -47652,13 +46736,13 @@ typedef struct { * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID */ #define VPRCSR_MARCHID (0x00000F12ul) - #define VPRCSR_MARCHID_ResetValue (0x800000AEUL) /*!< Reset value of MARCHID register. */ + #define VPRCSR_MARCHID_ResetValue (0x8000007EUL) /*!< Reset value of MARCHID register. */ /* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */ #define VPRCSR_MARCHID_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ -/* HIBERNATE @Bit 2 : Indicates the HIBERNATE parameter option */ +/* HIBERNATE @Bit 2 : Indicates the POWEROFFSLEEP parameter option */ #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL) /*!< Position of HIBERNATE field. */ #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field. */ @@ -47674,9 +46758,22 @@ typedef struct { #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL) /*!< Position of BUSWIDTH field. */ #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field. */ -/* BKPT @Bits 6..8 : Indicates the BKPT parameter option */ +/* BKPT @Bits 6..9 : Indicates the BKPT parameter option */ #define VPRCSR_MARCHID_BKPT_Pos (6UL) /*!< Position of BKPT field. */ - #define VPRCSR_MARCHID_BKPT_Msk (0x7UL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + #define VPRCSR_MARCHID_BKPT_Msk (0xFUL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* CACHE @Bit 10 : Indicates that the CACHE is present */ + #define VPRCSR_MARCHID_CACHE_Pos (10UL) /*!< Position of CACHE field. */ + #define VPRCSR_MARCHID_CACHE_Msk (0x1UL << VPRCSR_MARCHID_CACHE_Pos) /*!< Bit mask of CACHE field. */ + +/* CACHEEXTRATAGBUF @Bits 11..13 : Indicates the number of extra TAG buffers in CACHE */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos (11UL) /*!< Position of CACHEEXTRATAGBUF field. */ + #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Msk (0x7UL << VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos) /*!< Bit mask of CACHEEXTRATAGBUF + field.*/ + +/* RETAINED @Bit 16 : Indicates the RETAINED parameter option */ + #define VPRCSR_MARCHID_RETAINED_Pos (16UL) /*!< Position of RETAINED field. */ + #define VPRCSR_MARCHID_RETAINED_Msk (0x1UL << VPRCSR_MARCHID_RETAINED_Pos) /*!< Bit mask of RETAINED field. */ /* IMPLEM @Bit 31 : Indicates a non-open implementation */ #define VPRCSR_MARCHID_IMPLEM_Pos (31UL) /*!< Position of IMPLEM field. */ @@ -47706,7 +46803,7 @@ typedef struct { * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID */ #define VPRCSR_MHARTID (0x00000F14ul) - #define VPRCSR_MHARTID_ResetValue (0x00000000UL) /*!< Reset value of MHARTID register. */ + #define VPRCSR_MHARTID_ResetValue (0x0000000EUL) /*!< Reset value of MHARTID register. */ /* HARTNUM @Bits 0..31 : Machine Hart ID value */ #define VPRCSR_MHARTID_HARTNUM_Pos (0UL) /*!< Position of HARTNUM field. */ @@ -47850,7 +46947,7 @@ typedef struct { * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO */ #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul) - #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x00000000UL) /*!< Reset value of VIOPINS register. */ + #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x0000FFFFUL) /*!< Reset value of VIOPINS register. */ /* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */ #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL) /*!< Position of VAL field. */ @@ -47861,7 +46958,7 @@ typedef struct { * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters */ #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul) - #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x00000016UL) /*!< Reset value of EXTPARAMS register. */ + #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x0000008EUL) /*!< Reset value of EXTPARAMS register. */ /* MULDIV @Bits 0..1 : value of MULDIV */ #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ @@ -48533,258 +47630,6 @@ typedef struct { #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3] */ #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3] */ -/* SUBSCRIBE4 @Bit 4 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos (4UL) /*!< Position of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos) /*!< Bit mask of SUBSCRIBE4 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE4 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Disabled (0x0UL) /*!< Subscribe disabled for TASK[4] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Enabled (0x1UL) /*!< Subscribe enabled for TASK[4] */ - -/* SUBSCRIBE5 @Bit 5 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos (5UL) /*!< Position of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos) /*!< Bit mask of SUBSCRIBE5 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE5 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Disabled (0x0UL) /*!< Subscribe disabled for TASK[5] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Enabled (0x1UL) /*!< Subscribe enabled for TASK[5] */ - -/* SUBSCRIBE6 @Bit 6 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos (6UL) /*!< Position of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos) /*!< Bit mask of SUBSCRIBE6 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE6 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Disabled (0x0UL) /*!< Subscribe disabled for TASK[6] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Enabled (0x1UL) /*!< Subscribe enabled for TASK[6] */ - -/* SUBSCRIBE7 @Bit 7 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos (7UL) /*!< Position of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos) /*!< Bit mask of SUBSCRIBE7 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE7 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Disabled (0x0UL) /*!< Subscribe disabled for TASK[7] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Enabled (0x1UL) /*!< Subscribe enabled for TASK[7] */ - -/* SUBSCRIBE8 @Bit 8 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos (8UL) /*!< Position of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos) /*!< Bit mask of SUBSCRIBE8 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE8 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Disabled (0x0UL) /*!< Subscribe disabled for TASK[8] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Enabled (0x1UL) /*!< Subscribe enabled for TASK[8] */ - -/* SUBSCRIBE9 @Bit 9 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos (9UL) /*!< Position of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos) /*!< Bit mask of SUBSCRIBE9 - field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE9 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Disabled (0x0UL) /*!< Subscribe disabled for TASK[9] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Enabled (0x1UL) /*!< Subscribe enabled for TASK[9] */ - -/* SUBSCRIBE10 @Bit 10 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos (10UL) /*!< Position of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos) /*!< Bit mask of - SUBSCRIBE10 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE10 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Disabled (0x0UL) /*!< Subscribe disabled for TASK[10] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Enabled (0x1UL) /*!< Subscribe enabled for TASK[10] */ - -/* SUBSCRIBE11 @Bit 11 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos (11UL) /*!< Position of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos) /*!< Bit mask of - SUBSCRIBE11 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE11 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Disabled (0x0UL) /*!< Subscribe disabled for TASK[11] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Enabled (0x1UL) /*!< Subscribe enabled for TASK[11] */ - -/* SUBSCRIBE12 @Bit 12 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos (12UL) /*!< Position of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos) /*!< Bit mask of - SUBSCRIBE12 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE12 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Disabled (0x0UL) /*!< Subscribe disabled for TASK[12] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Enabled (0x1UL) /*!< Subscribe enabled for TASK[12] */ - -/* SUBSCRIBE13 @Bit 13 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos (13UL) /*!< Position of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos) /*!< Bit mask of - SUBSCRIBE13 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE13 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Disabled (0x0UL) /*!< Subscribe disabled for TASK[13] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Enabled (0x1UL) /*!< Subscribe enabled for TASK[13] */ - -/* SUBSCRIBE14 @Bit 14 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos (14UL) /*!< Position of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos) /*!< Bit mask of - SUBSCRIBE14 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE14 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Disabled (0x0UL) /*!< Subscribe disabled for TASK[14] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Enabled (0x1UL) /*!< Subscribe enabled for TASK[14] */ - -/* SUBSCRIBE15 @Bit 15 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos (15UL) /*!< Position of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos) /*!< Bit mask of - SUBSCRIBE15 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE15 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Disabled (0x0UL) /*!< Subscribe disabled for TASK[15] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Enabled (0x1UL) /*!< Subscribe enabled for TASK[15] */ - -/* SUBSCRIBE16 @Bit 16 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of - SUBSCRIBE16 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16] */ - -/* SUBSCRIBE17 @Bit 17 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of - SUBSCRIBE17 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17] */ - -/* SUBSCRIBE18 @Bit 18 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of - SUBSCRIBE18 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18] */ - -/* SUBSCRIBE19 @Bit 19 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of - SUBSCRIBE19 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19] */ - -/* SUBSCRIBE20 @Bit 20 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos (20UL) /*!< Position of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos) /*!< Bit mask of - SUBSCRIBE20 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE20 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Disabled (0x0UL) /*!< Subscribe disabled for TASK[20] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Enabled (0x1UL) /*!< Subscribe enabled for TASK[20] */ - -/* SUBSCRIBE21 @Bit 21 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos (21UL) /*!< Position of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos) /*!< Bit mask of - SUBSCRIBE21 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE21 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Disabled (0x0UL) /*!< Subscribe disabled for TASK[21] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Enabled (0x1UL) /*!< Subscribe enabled for TASK[21] */ - -/* SUBSCRIBE22 @Bit 22 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos (22UL) /*!< Position of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos) /*!< Bit mask of - SUBSCRIBE22 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE22 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Disabled (0x0UL) /*!< Subscribe disabled for TASK[22] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Enabled (0x1UL) /*!< Subscribe enabled for TASK[22] */ - -/* SUBSCRIBE23 @Bit 23 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos (23UL) /*!< Position of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos) /*!< Bit mask of - SUBSCRIBE23 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE23 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Disabled (0x0UL) /*!< Subscribe disabled for TASK[23] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Enabled (0x1UL) /*!< Subscribe enabled for TASK[23] */ - -/* SUBSCRIBE24 @Bit 24 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos (24UL) /*!< Position of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos) /*!< Bit mask of - SUBSCRIBE24 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE24 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Disabled (0x0UL) /*!< Subscribe disabled for TASK[24] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Enabled (0x1UL) /*!< Subscribe enabled for TASK[24] */ - -/* SUBSCRIBE25 @Bit 25 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos (25UL) /*!< Position of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos) /*!< Bit mask of - SUBSCRIBE25 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE25 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Disabled (0x0UL) /*!< Subscribe disabled for TASK[25] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Enabled (0x1UL) /*!< Subscribe enabled for TASK[25] */ - -/* SUBSCRIBE26 @Bit 26 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos (26UL) /*!< Position of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos) /*!< Bit mask of - SUBSCRIBE26 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE26 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Disabled (0x0UL) /*!< Subscribe disabled for TASK[26] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Enabled (0x1UL) /*!< Subscribe enabled for TASK[26] */ - -/* SUBSCRIBE27 @Bit 27 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos (27UL) /*!< Position of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos) /*!< Bit mask of - SUBSCRIBE27 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE27 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Disabled (0x0UL) /*!< Subscribe disabled for TASK[27] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Enabled (0x1UL) /*!< Subscribe enabled for TASK[27] */ - -/* SUBSCRIBE28 @Bit 28 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos (28UL) /*!< Position of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos) /*!< Bit mask of - SUBSCRIBE28 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE28 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Disabled (0x0UL) /*!< Subscribe disabled for TASK[28] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Enabled (0x1UL) /*!< Subscribe enabled for TASK[28] */ - -/* SUBSCRIBE29 @Bit 29 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos (29UL) /*!< Position of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos) /*!< Bit mask of - SUBSCRIBE29 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE29 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Disabled (0x0UL) /*!< Subscribe disabled for TASK[29] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Enabled (0x1UL) /*!< Subscribe enabled for TASK[29] */ - -/* SUBSCRIBE30 @Bit 30 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos (30UL) /*!< Position of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos) /*!< Bit mask of - SUBSCRIBE30 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE30 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Disabled (0x0UL) /*!< Subscribe disabled for TASK[30] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Enabled (0x1UL) /*!< Subscribe enabled for TASK[30] */ - -/* SUBSCRIBE31 @Bit 31 : (unspecified) */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos (31UL) /*!< Position of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos) /*!< Bit mask of - SUBSCRIBE31 field.*/ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE31 field. */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Disabled (0x0UL) /*!< Subscribe disabled for TASK[31] */ - #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Enabled (0x1UL) /*!< Subscribe enabled for TASK[31] */ - /** * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events @@ -49087,230 +47932,6 @@ typedef struct { #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3] */ #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3] */ -/* PUBLISH4 @Bit 4 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos (4UL) /*!< Position of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos) /*!< Bit mask of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Min (0x0UL) /*!< Min enumerator value of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Max (0x1UL) /*!< Max enumerator value of PUBLISH4 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Disabled (0x0UL) /*!< Publish disabled for EVENTS[4] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Enabled (0x1UL) /*!< Publish enabled for EVENTS[4] */ - -/* PUBLISH5 @Bit 5 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos (5UL) /*!< Position of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos) /*!< Bit mask of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Min (0x0UL) /*!< Min enumerator value of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Max (0x1UL) /*!< Max enumerator value of PUBLISH5 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Disabled (0x0UL) /*!< Publish disabled for EVENTS[5] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Enabled (0x1UL) /*!< Publish enabled for EVENTS[5] */ - -/* PUBLISH6 @Bit 6 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos (6UL) /*!< Position of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos) /*!< Bit mask of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Min (0x0UL) /*!< Min enumerator value of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Max (0x1UL) /*!< Max enumerator value of PUBLISH6 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Disabled (0x0UL) /*!< Publish disabled for EVENTS[6] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Enabled (0x1UL) /*!< Publish enabled for EVENTS[6] */ - -/* PUBLISH7 @Bit 7 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos (7UL) /*!< Position of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos) /*!< Bit mask of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Min (0x0UL) /*!< Min enumerator value of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Max (0x1UL) /*!< Max enumerator value of PUBLISH7 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Disabled (0x0UL) /*!< Publish disabled for EVENTS[7] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Enabled (0x1UL) /*!< Publish enabled for EVENTS[7] */ - -/* PUBLISH8 @Bit 8 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos (8UL) /*!< Position of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos) /*!< Bit mask of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Min (0x0UL) /*!< Min enumerator value of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Max (0x1UL) /*!< Max enumerator value of PUBLISH8 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Disabled (0x0UL) /*!< Publish disabled for EVENTS[8] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Enabled (0x1UL) /*!< Publish enabled for EVENTS[8] */ - -/* PUBLISH9 @Bit 9 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos (9UL) /*!< Position of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos) /*!< Bit mask of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Min (0x0UL) /*!< Min enumerator value of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Max (0x1UL) /*!< Max enumerator value of PUBLISH9 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Disabled (0x0UL) /*!< Publish disabled for EVENTS[9] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Enabled (0x1UL) /*!< Publish enabled for EVENTS[9] */ - -/* PUBLISH10 @Bit 10 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos (10UL) /*!< Position of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos) /*!< Bit mask of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Min (0x0UL) /*!< Min enumerator value of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Max (0x1UL) /*!< Max enumerator value of PUBLISH10 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Disabled (0x0UL) /*!< Publish disabled for EVENTS[10] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Enabled (0x1UL) /*!< Publish enabled for EVENTS[10] */ - -/* PUBLISH11 @Bit 11 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos (11UL) /*!< Position of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos) /*!< Bit mask of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Min (0x0UL) /*!< Min enumerator value of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Max (0x1UL) /*!< Max enumerator value of PUBLISH11 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Disabled (0x0UL) /*!< Publish disabled for EVENTS[11] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Enabled (0x1UL) /*!< Publish enabled for EVENTS[11] */ - -/* PUBLISH12 @Bit 12 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos (12UL) /*!< Position of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos) /*!< Bit mask of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Min (0x0UL) /*!< Min enumerator value of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Max (0x1UL) /*!< Max enumerator value of PUBLISH12 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Disabled (0x0UL) /*!< Publish disabled for EVENTS[12] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Enabled (0x1UL) /*!< Publish enabled for EVENTS[12] */ - -/* PUBLISH13 @Bit 13 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos (13UL) /*!< Position of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos) /*!< Bit mask of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Min (0x0UL) /*!< Min enumerator value of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Max (0x1UL) /*!< Max enumerator value of PUBLISH13 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Disabled (0x0UL) /*!< Publish disabled for EVENTS[13] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Enabled (0x1UL) /*!< Publish enabled for EVENTS[13] */ - -/* PUBLISH14 @Bit 14 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos (14UL) /*!< Position of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos) /*!< Bit mask of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Min (0x0UL) /*!< Min enumerator value of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Max (0x1UL) /*!< Max enumerator value of PUBLISH14 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Disabled (0x0UL) /*!< Publish disabled for EVENTS[14] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Enabled (0x1UL) /*!< Publish enabled for EVENTS[14] */ - -/* PUBLISH15 @Bit 15 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos (15UL) /*!< Position of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos) /*!< Bit mask of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Min (0x0UL) /*!< Min enumerator value of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Max (0x1UL) /*!< Max enumerator value of PUBLISH15 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Disabled (0x0UL) /*!< Publish disabled for EVENTS[15] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Enabled (0x1UL) /*!< Publish enabled for EVENTS[15] */ - -/* PUBLISH16 @Bit 16 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16] */ - -/* PUBLISH17 @Bit 17 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17] */ - -/* PUBLISH18 @Bit 18 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18] */ - -/* PUBLISH19 @Bit 19 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19] */ - -/* PUBLISH20 @Bit 20 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos (20UL) /*!< Position of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos) /*!< Bit mask of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Min (0x0UL) /*!< Min enumerator value of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Max (0x1UL) /*!< Max enumerator value of PUBLISH20 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Disabled (0x0UL) /*!< Publish disabled for EVENTS[20] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Enabled (0x1UL) /*!< Publish enabled for EVENTS[20] */ - -/* PUBLISH21 @Bit 21 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos (21UL) /*!< Position of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos) /*!< Bit mask of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Min (0x0UL) /*!< Min enumerator value of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Max (0x1UL) /*!< Max enumerator value of PUBLISH21 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Disabled (0x0UL) /*!< Publish disabled for EVENTS[21] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Enabled (0x1UL) /*!< Publish enabled for EVENTS[21] */ - -/* PUBLISH22 @Bit 22 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos (22UL) /*!< Position of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos) /*!< Bit mask of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Min (0x0UL) /*!< Min enumerator value of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Max (0x1UL) /*!< Max enumerator value of PUBLISH22 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Disabled (0x0UL) /*!< Publish disabled for EVENTS[22] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Enabled (0x1UL) /*!< Publish enabled for EVENTS[22] */ - -/* PUBLISH23 @Bit 23 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos (23UL) /*!< Position of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos) /*!< Bit mask of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Min (0x0UL) /*!< Min enumerator value of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Max (0x1UL) /*!< Max enumerator value of PUBLISH23 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Disabled (0x0UL) /*!< Publish disabled for EVENTS[23] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Enabled (0x1UL) /*!< Publish enabled for EVENTS[23] */ - -/* PUBLISH24 @Bit 24 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos (24UL) /*!< Position of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos) /*!< Bit mask of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Min (0x0UL) /*!< Min enumerator value of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Max (0x1UL) /*!< Max enumerator value of PUBLISH24 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Disabled (0x0UL) /*!< Publish disabled for EVENTS[24] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Enabled (0x1UL) /*!< Publish enabled for EVENTS[24] */ - -/* PUBLISH25 @Bit 25 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos (25UL) /*!< Position of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos) /*!< Bit mask of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Min (0x0UL) /*!< Min enumerator value of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Max (0x1UL) /*!< Max enumerator value of PUBLISH25 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Disabled (0x0UL) /*!< Publish disabled for EVENTS[25] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Enabled (0x1UL) /*!< Publish enabled for EVENTS[25] */ - -/* PUBLISH26 @Bit 26 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos (26UL) /*!< Position of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos) /*!< Bit mask of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Min (0x0UL) /*!< Min enumerator value of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Max (0x1UL) /*!< Max enumerator value of PUBLISH26 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Disabled (0x0UL) /*!< Publish disabled for EVENTS[26] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Enabled (0x1UL) /*!< Publish enabled for EVENTS[26] */ - -/* PUBLISH27 @Bit 27 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos (27UL) /*!< Position of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos) /*!< Bit mask of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Min (0x0UL) /*!< Min enumerator value of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Max (0x1UL) /*!< Max enumerator value of PUBLISH27 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Disabled (0x0UL) /*!< Publish disabled for EVENTS[27] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Enabled (0x1UL) /*!< Publish enabled for EVENTS[27] */ - -/* PUBLISH28 @Bit 28 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos (28UL) /*!< Position of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos) /*!< Bit mask of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Min (0x0UL) /*!< Min enumerator value of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Max (0x1UL) /*!< Max enumerator value of PUBLISH28 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Disabled (0x0UL) /*!< Publish disabled for EVENTS[28] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Enabled (0x1UL) /*!< Publish enabled for EVENTS[28] */ - -/* PUBLISH29 @Bit 29 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos (29UL) /*!< Position of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos) /*!< Bit mask of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Min (0x0UL) /*!< Min enumerator value of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Max (0x1UL) /*!< Max enumerator value of PUBLISH29 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Disabled (0x0UL) /*!< Publish disabled for EVENTS[29] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Enabled (0x1UL) /*!< Publish enabled for EVENTS[29] */ - -/* PUBLISH30 @Bit 30 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos (30UL) /*!< Position of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos) /*!< Bit mask of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Min (0x0UL) /*!< Min enumerator value of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Max (0x1UL) /*!< Max enumerator value of PUBLISH30 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Disabled (0x0UL) /*!< Publish disabled for EVENTS[30] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Enabled (0x1UL) /*!< Publish enabled for EVENTS[30] */ - -/* PUBLISH31 @Bit 31 : (unspecified) */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos (31UL) /*!< Position of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos) /*!< Bit mask of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Min (0x0UL) /*!< Min enumerator value of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Max (0x1UL) /*!< Max enumerator value of PUBLISH31 field. */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Disabled (0x0UL) /*!< Publish disabled for EVENTS[31] */ - #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Enabled (0x1UL) /*!< Publish enabled for EVENTS[31] */ - /** * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable diff --git a/mdk/nrf54l15_version.h b/mdk/nrf54l15_version.h index 1ddde1173..75b4db391 100644 --- a/mdk/nrf54l15_version.h +++ b/mdk/nrf54l15_version.h @@ -41,10 +41,9 @@ POSSIBILITY OF SUCH DAMAGE. #define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of product specification. */ -#define MDK_SOURCE_VERSION_MINOR 5e /*!< Minor version of product specification. */ +#define MDK_SOURCE_VERSION_MINOR 5g /*!< Minor version of product specification. */ #define MDK_SOURCE_VERSION_MICRO /*!< Micro version of product specification. */ -#define MDK_SOURCE_HASH Moonlight_OPS_v0.5E /*!< Git hash of product specification source. */ #ifdef __cplusplus diff --git a/mdk/nrf9120.h b/mdk/nrf9120.h index f00fb71e8..080d6684c 100644 --- a/mdk/nrf9120.h +++ b/mdk/nrf9120.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf9120.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:18:08 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:17 * from File 'nrf9120.svd', - * last modified on Wednesday, 28.02.2024 14:17:07 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 6fed62d20..9139f6f37 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 28. February 2024 - * @note Generated by SVDConv V3.3.35 on Wednesday, 28.02.2024 15:18:11 + * @date 22. April 2024 + * @note Generated by SVDConv V3.3.35 on Monday, 22.04.2024 15:21:21 * from File 'nrf9160.svd', - * last modified on Wednesday, 28.02.2024 14:17:07 + * last modified on Monday, 22.04.2024 13:20:06 */ diff --git a/mdk/nrf9230_enga.h b/mdk/nrf9230_enga.h new file mode 100644 index 000000000..1d96d98f7 --- /dev/null +++ b/mdk/nrf9230_enga.h @@ -0,0 +1,54 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_H +#define NRF9230_ENGA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "nrf9230_enga_types.h" + +#include "nrf9230_enga_global.h" +#include "nrf9230_enga_application.h" +#include "nrf9230_enga_flpr.h" +#include "nrf9230_enga_ppr.h" +#include "nrf9230_enga_radiocore.h" + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_H */ + diff --git a/mdk/nrf9230_enga_application.h b/mdk/nrf9230_enga_application.h new file mode 100644 index 000000000..c211532cc --- /dev/null +++ b/mdk/nrf9230_enga_application.h @@ -0,0 +1,539 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_APPLICATION_H +#define NRF9230_ENGA_APPLICATION_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_APPLICATION /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No + Match*/ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault*/ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ============================================== Processor Specific Interrupts ============================================== */ + SPU000_IRQn = 0, /*!< 0 SPU000 */ + MPC_IRQn = 1, /*!< 1 MPC */ + MVDMA_IRQn = 3, /*!< 3 MVDMA */ + SPU010_IRQn = 16, /*!< 16 SPU010 */ + WDT010_IRQn = 20, /*!< 20 WDT010 */ + WDT011_IRQn = 21, /*!< 21 WDT011 */ + IPCT_0_IRQn = 64, /*!< 64 IPCT_0 */ + IPCT_1_IRQn = 65, /*!< 65 IPCT_1 */ + SWI0_IRQn = 88, /*!< 88 SWI0 */ + SWI1_IRQn = 89, /*!< 89 SWI1 */ + SWI2_IRQn = 90, /*!< 90 SWI2 */ + SWI3_IRQn = 91, /*!< 91 SWI3 */ + SWI4_IRQn = 92, /*!< 92 SWI4 */ + SWI5_IRQn = 93, /*!< 93 SWI5 */ + SWI6_IRQn = 94, /*!< 94 SWI6 */ + SWI7_IRQn = 95, /*!< 95 SWI7 */ + BELLBOARD_0_IRQn = 96, /*!< 96 BELLBOARD_0 */ + BELLBOARD_1_IRQn = 97, /*!< 97 BELLBOARD_1 */ + BELLBOARD_2_IRQn = 98, /*!< 98 BELLBOARD_2 */ + BELLBOARD_3_IRQn = 99, /*!< 99 BELLBOARD_3 */ + GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ + GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ + GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ + GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ + GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ + GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ + GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ + TBM_IRQn = 127, /*!< 127 TBM */ + USBHS_IRQn = 134, /*!< 134 USBHS */ + EXMIF_IRQn = 149, /*!< 149 EXMIF */ + IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ + I3C120_IRQn = 211, /*!< 211 I3C120 */ + VPR121_IRQn = 212, /*!< 212 VPR121 */ + CAN120_IRQn = 216, /*!< 216 CAN120 */ + MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ + CAN121_IRQn = 219, /*!< 219 CAN121 */ + MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ + I3C121_IRQn = 222, /*!< 222 I3C121 */ + TIMER120_IRQn = 226, /*!< 226 TIMER120 */ + TIMER121_IRQn = 227, /*!< 227 TIMER121 */ + PWM120_IRQn = 228, /*!< 228 PWM120 */ + SPIS120_IRQn = 229, /*!< 229 SPIS120 */ + SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ + SPIM121_IRQn = 231, /*!< 231 SPIM121 */ + VPR130_IRQn = 264, /*!< 264 VPR130 */ + IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ + RTC130_IRQn = 296, /*!< 296 RTC130 */ + RTC131_IRQn = 297, /*!< 297 RTC131 */ + WDT131_IRQn = 299, /*!< 299 WDT131 */ + WDT132_IRQn = 300, /*!< 300 WDT132 */ + EGU130_IRQn = 301, /*!< 301 EGU130 */ + SAADC_IRQn = 386, /*!< 386 SAADC */ + COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ + TEMP_IRQn = 388, /*!< 388 TEMP */ + I2S130_IRQn = 402, /*!< 402 I2S130 */ + PDM_IRQn = 403, /*!< 403 PDM */ + QDEC130_IRQn = 404, /*!< 404 QDEC130 */ + QDEC131_IRQn = 405, /*!< 405 QDEC131 */ + I2S131_IRQn = 407, /*!< 407 I2S131 */ + TIMER130_IRQn = 418, /*!< 418 TIMER130 */ + TIMER131_IRQn = 419, /*!< 419 TIMER131 */ + PWM130_IRQn = 420, /*!< 420 PWM130 */ + SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ + SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ + TIMER132_IRQn = 434, /*!< 434 TIMER132 */ + TIMER133_IRQn = 435, /*!< 435 TIMER133 */ + PWM131_IRQn = 436, /*!< 436 PWM131 */ + SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ + SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ + TIMER134_IRQn = 450, /*!< 450 TIMER134 */ + TIMER135_IRQn = 451, /*!< 451 TIMER135 */ + PWM132_IRQn = 452, /*!< 452 PWM132 */ + SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ + SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ + TIMER136_IRQn = 466, /*!< 466 TIMER136 */ + TIMER137_IRQn = 467, /*!< 467 TIMER137 */ + PWM133_IRQn = 468, /*!< 468 PWM133 */ + SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ + SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define SPIM120_IRQn SPIM120_UARTE120_IRQn +#define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler +#define UARTE120_IRQn SPIM120_UARTE120_IRQn +#define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SPIM130_IRQn SERIAL0_IRQn +#define SPIM130_IRQHandler SERIAL0_IRQHandler +#define SPIS130_IRQn SERIAL0_IRQn +#define SPIS130_IRQHandler SERIAL0_IRQHandler +#define TWIM130_IRQn SERIAL0_IRQn +#define TWIM130_IRQHandler SERIAL0_IRQHandler +#define TWIS130_IRQn SERIAL0_IRQn +#define TWIS130_IRQHandler SERIAL0_IRQHandler +#define UARTE130_IRQn SERIAL0_IRQn +#define UARTE130_IRQHandler SERIAL0_IRQHandler +#define SPIM131_IRQn SERIAL1_IRQn +#define SPIM131_IRQHandler SERIAL1_IRQHandler +#define SPIS131_IRQn SERIAL1_IRQn +#define SPIS131_IRQHandler SERIAL1_IRQHandler +#define TWIM131_IRQn SERIAL1_IRQn +#define TWIM131_IRQHandler SERIAL1_IRQHandler +#define TWIS131_IRQn SERIAL1_IRQn +#define TWIS131_IRQHandler SERIAL1_IRQHandler +#define UARTE131_IRQn SERIAL1_IRQn +#define UARTE131_IRQHandler SERIAL1_IRQHandler +#define SPIM132_IRQn SERIAL2_IRQn +#define SPIM132_IRQHandler SERIAL2_IRQHandler +#define SPIS132_IRQn SERIAL2_IRQn +#define SPIS132_IRQHandler SERIAL2_IRQHandler +#define TWIM132_IRQn SERIAL2_IRQn +#define TWIM132_IRQHandler SERIAL2_IRQHandler +#define TWIS132_IRQn SERIAL2_IRQn +#define TWIS132_IRQHandler SERIAL2_IRQHandler +#define UARTE132_IRQn SERIAL2_IRQn +#define UARTE132_IRQHandler SERIAL2_IRQHandler +#define SPIM133_IRQn SERIAL3_IRQn +#define SPIM133_IRQHandler SERIAL3_IRQHandler +#define SPIS133_IRQn SERIAL3_IRQn +#define SPIS133_IRQHandler SERIAL3_IRQHandler +#define TWIM133_IRQn SERIAL3_IRQn +#define TWIM133_IRQHandler SERIAL3_IRQHandler +#define TWIS133_IRQn SERIAL3_IRQn +#define TWIS133_IRQHandler SERIAL3_IRQHandler +#define UARTE133_IRQn SERIAL3_IRQn +#define UARTE133_IRQHandler SERIAL3_IRQHandler +#define SPIM134_IRQn SERIAL4_IRQn +#define SPIM134_IRQHandler SERIAL4_IRQHandler +#define SPIS134_IRQn SERIAL4_IRQn +#define SPIS134_IRQHandler SERIAL4_IRQHandler +#define TWIM134_IRQn SERIAL4_IRQn +#define TWIM134_IRQHandler SERIAL4_IRQHandler +#define TWIS134_IRQn SERIAL4_IRQn +#define TWIS134_IRQHandler SERIAL4_IRQHandler +#define UARTE134_IRQn SERIAL4_IRQn +#define UARTE134_IRQHandler SERIAL4_IRQHandler +#define SPIM135_IRQn SERIAL5_IRQn +#define SPIM135_IRQHandler SERIAL5_IRQHandler +#define SPIS135_IRQn SERIAL5_IRQn +#define SPIS135_IRQHandler SERIAL5_IRQHandler +#define TWIM135_IRQn SERIAL5_IRQn +#define TWIM135_IRQHandler SERIAL5_IRQHandler +#define TWIS135_IRQn SERIAL5_IRQn +#define TWIS135_IRQHandler SERIAL5_IRQHandler +#define UARTE135_IRQn SERIAL5_IRQn +#define UARTE135_IRQHandler SERIAL5_IRQHandler +#define SPIM136_IRQn SERIAL6_IRQn +#define SPIM136_IRQHandler SERIAL6_IRQHandler +#define SPIS136_IRQn SERIAL6_IRQn +#define SPIS136_IRQHandler SERIAL6_IRQHandler +#define TWIM136_IRQn SERIAL6_IRQn +#define TWIM136_IRQHandler SERIAL6_IRQHandler +#define TWIS136_IRQn SERIAL6_IRQn +#define TWIS136_IRQHandler SERIAL6_IRQHandler +#define UARTE136_IRQn SERIAL6_IRQn +#define UARTE136_IRQHandler SERIAL6_IRQHandler +#define SPIM137_IRQn SERIAL7_IRQn +#define SPIM137_IRQHandler SERIAL7_IRQHandler +#define SPIS137_IRQn SERIAL7_IRQn +#define SPIS137_IRQHandler SERIAL7_IRQHandler +#define TWIM137_IRQn SERIAL7_IRQn +#define TWIM137_IRQHandler SERIAL7_IRQHandler +#define TWIS137_IRQn SERIAL7_IRQn +#define TWIS137_IRQHandler SERIAL7_IRQHandler +#define UARTE137_IRQn SERIAL7_IRQn +#define UARTE137_IRQHandler SERIAL7_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ +#define __CM33_REV r0p4 /*!< CM33 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ +#define __SAUREGION_PRESENT 1 /*!< SAU present */ +#define __NUM_SAUREGIONS 4 /*!< Number of regions */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_nrf.h" /*!< nrf9230_enga_application System Library */ + +#endif /*!< NRF_APPLICATION */ + + +#ifdef NRF_APPLICATION + + #define NRF_DOMAIN NRF_DOMAIN_APPLICATION + #define NRF_PROCESSOR NRF_PROCESSOR_APPLICATION + #define NRF_OWNER NRF_OWNER_APPLICATION + +#endif /*!< NRF_APPLICATION */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_APPLICATION_UICREXTENDED_NS_BASE 0x00000000UL +#define NRF_APPLICATION_ICACHEDATA_S_BASE 0x02F00000UL +#define NRF_APPLICATION_ICACHEINFO_S_BASE 0x02F10000UL +#define NRF_APPLICATION_UICR_NS_BASE 0x0FFF8000UL +#define NRF_APPLICATION_BICR_NS_BASE 0x0FFF8800UL +#define NRF_APPLICATION_DCACHEDATA_S_BASE 0x22F00000UL +#define NRF_APPLICATION_DCACHEINFO_S_BASE 0x22F10000UL +#define NRF_APPLICATION_ETM_NS_BASE 0xE0041000UL +#define NRF_APPLICATION_CTI_S_BASE 0xE0042000UL +#define NRF_APPLICATION_CPUC_S_BASE 0xE0080000UL +#define NRF_APPLICATION_ICACHE_S_BASE 0xE0082000UL +#define NRF_APPLICATION_DCACHE_S_BASE 0xE0083000UL +#define NRF_APPLICATION_SPU000_S_BASE 0x52000000UL +#define NRF_APPLICATION_MPC_S_BASE 0x52001000UL +#define NRF_APPLICATION_MVDMA_NS_BASE 0x42003000UL +#define NRF_APPLICATION_MVDMA_S_BASE 0x52003000UL +#define NRF_APPLICATION_RAMC_NS_BASE 0x42004000UL +#define NRF_APPLICATION_RAMC_S_BASE 0x52004000UL +#define NRF_APPLICATION_HSFLL_S_BASE 0x5200D000UL +#define NRF_APPLICATION_LRCCONF000_S_BASE 0x5200E000UL +#define NRF_APPLICATION_SPU010_S_BASE 0x52010000UL +#define NRF_APPLICATION_MEMCONF_NS_BASE 0x42012000UL +#define NRF_APPLICATION_MEMCONF_S_BASE 0x52012000UL +#define NRF_APPLICATION_WDT010_NS_BASE 0x42014000UL +#define NRF_APPLICATION_WDT010_S_BASE 0x52014000UL +#define NRF_APPLICATION_WDT011_NS_BASE 0x42015000UL +#define NRF_APPLICATION_WDT011_S_BASE 0x52015000UL +#define NRF_APPLICATION_ABB_S_BASE 0x5201C000UL +#define NRF_APPLICATION_LRCCONF010_S_BASE 0x5201E000UL +#define NRF_APPLICATION_RESETINFO_S_BASE 0x5201E000UL +#define NRF_APPLICATION_IPCT_NS_BASE 0x42013000UL +#define NRF_APPLICATION_IPCT_S_BASE 0x52013000UL +#define NRF_APPLICATION_SWI0_NS_BASE 0x42058000UL +#define NRF_APPLICATION_SWI1_NS_BASE 0x42059000UL +#define NRF_APPLICATION_SWI2_NS_BASE 0x4205A000UL +#define NRF_APPLICATION_SWI3_NS_BASE 0x4205B000UL +#define NRF_APPLICATION_SWI4_NS_BASE 0x4205C000UL +#define NRF_APPLICATION_SWI5_NS_BASE 0x4205D000UL +#define NRF_APPLICATION_SWI6_NS_BASE 0x4205E000UL +#define NRF_APPLICATION_SWI7_NS_BASE 0x4205F000UL +#define NRF_APPLICATION_BELLBOARD_NS_BASE 0x4F09A000UL +#define NRF_APPLICATION_BELLBOARD_S_BASE 0x5F09A000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_APPLICATION_UICREXTENDED_NS ((NRF_UICREXTENDED_Type*) NRF_APPLICATION_UICREXTENDED_NS_BASE) +#define NRF_APPLICATION_ICACHEDATA_S ((NRF_ICACHEDATA_Type*) NRF_APPLICATION_ICACHEDATA_S_BASE) +#define NRF_APPLICATION_ICACHEINFO_S ((NRF_ICACHEINFO_Type*) NRF_APPLICATION_ICACHEINFO_S_BASE) +#define NRF_APPLICATION_UICR_NS ((NRF_UICR_Type*) NRF_APPLICATION_UICR_NS_BASE) +#define NRF_APPLICATION_BICR_NS ((NRF_BICR_Type*) NRF_APPLICATION_BICR_NS_BASE) +#define NRF_APPLICATION_DCACHEDATA_S ((NRF_DCACHEDATA_Type*) NRF_APPLICATION_DCACHEDATA_S_BASE) +#define NRF_APPLICATION_DCACHEINFO_S ((NRF_DCACHEINFO_Type*) NRF_APPLICATION_DCACHEINFO_S_BASE) +#define NRF_APPLICATION_ETM_NS ((NRF_ETM_Type*) NRF_APPLICATION_ETM_NS_BASE) +#define NRF_APPLICATION_CTI_S ((NRF_CTI_Type*) NRF_APPLICATION_CTI_S_BASE) +#define NRF_APPLICATION_CPUC_S ((NRF_CM33SS_Type*) NRF_APPLICATION_CPUC_S_BASE) +#define NRF_APPLICATION_ICACHE_S ((NRF_CACHE_Type*) NRF_APPLICATION_ICACHE_S_BASE) +#define NRF_APPLICATION_DCACHE_S ((NRF_CACHE_Type*) NRF_APPLICATION_DCACHE_S_BASE) +#define NRF_APPLICATION_SPU000_S ((NRF_SPU_Type*) NRF_APPLICATION_SPU000_S_BASE) +#define NRF_APPLICATION_MPC_S ((NRF_MPC_Type*) NRF_APPLICATION_MPC_S_BASE) +#define NRF_APPLICATION_MVDMA_NS ((NRF_MVDMA_Type*) NRF_APPLICATION_MVDMA_NS_BASE) +#define NRF_APPLICATION_MVDMA_S ((NRF_MVDMA_Type*) NRF_APPLICATION_MVDMA_S_BASE) +#define NRF_APPLICATION_RAMC_NS ((NRF_RAMC_Type*) NRF_APPLICATION_RAMC_NS_BASE) +#define NRF_APPLICATION_RAMC_S ((NRF_RAMC_Type*) NRF_APPLICATION_RAMC_S_BASE) +#define NRF_APPLICATION_HSFLL_S ((NRF_HSFLL_Type*) NRF_APPLICATION_HSFLL_S_BASE) +#define NRF_APPLICATION_LRCCONF000_S ((NRF_LRCCONF_Type*) NRF_APPLICATION_LRCCONF000_S_BASE) +#define NRF_APPLICATION_SPU010_S ((NRF_SPU_Type*) NRF_APPLICATION_SPU010_S_BASE) +#define NRF_APPLICATION_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_APPLICATION_MEMCONF_NS_BASE) +#define NRF_APPLICATION_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_APPLICATION_MEMCONF_S_BASE) +#define NRF_APPLICATION_WDT010_NS ((NRF_WDT_Type*) NRF_APPLICATION_WDT010_NS_BASE) +#define NRF_APPLICATION_WDT010_S ((NRF_WDT_Type*) NRF_APPLICATION_WDT010_S_BASE) +#define NRF_APPLICATION_WDT011_NS ((NRF_WDT_Type*) NRF_APPLICATION_WDT011_NS_BASE) +#define NRF_APPLICATION_WDT011_S ((NRF_WDT_Type*) NRF_APPLICATION_WDT011_S_BASE) +#define NRF_APPLICATION_ABB_S ((NRF_ABB_Type*) NRF_APPLICATION_ABB_S_BASE) +#define NRF_APPLICATION_LRCCONF010_S ((NRF_LRCCONF_Type*) NRF_APPLICATION_LRCCONF010_S_BASE) +#define NRF_APPLICATION_RESETINFO_S ((NRF_RESETINFO_Type*) NRF_APPLICATION_RESETINFO_S_BASE) +#define NRF_APPLICATION_IPCT_NS ((NRF_IPCT_Type*) NRF_APPLICATION_IPCT_NS_BASE) +#define NRF_APPLICATION_IPCT_S ((NRF_IPCT_Type*) NRF_APPLICATION_IPCT_S_BASE) +#define NRF_APPLICATION_SWI0_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI0_NS_BASE) +#define NRF_APPLICATION_SWI1_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI1_NS_BASE) +#define NRF_APPLICATION_SWI2_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI2_NS_BASE) +#define NRF_APPLICATION_SWI3_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI3_NS_BASE) +#define NRF_APPLICATION_SWI4_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI4_NS_BASE) +#define NRF_APPLICATION_SWI5_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI5_NS_BASE) +#define NRF_APPLICATION_SWI6_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI6_NS_BASE) +#define NRF_APPLICATION_SWI7_NS ((NRF_SWI_Type*) NRF_APPLICATION_SWI7_NS_BASE) +#define NRF_APPLICATION_BELLBOARD_NS ((NRF_BELLBOARD_Type*) NRF_APPLICATION_BELLBOARD_NS_BASE) +#define NRF_APPLICATION_BELLBOARD_S ((NRF_BELLBOARD_Type*) NRF_APPLICATION_BELLBOARD_S_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_APPLICATION_UICREXTENDED NRF_APPLICATION_UICREXTENDED_NS + #define NRF_APPLICATION_UICR NRF_APPLICATION_UICR_NS + #define NRF_APPLICATION_BICR NRF_APPLICATION_BICR_NS + #define NRF_APPLICATION_ETM NRF_APPLICATION_ETM_NS + #define NRF_APPLICATION_MVDMA NRF_APPLICATION_MVDMA_NS + #define NRF_APPLICATION_RAMC NRF_APPLICATION_RAMC_NS + #define NRF_APPLICATION_MEMCONF NRF_APPLICATION_MEMCONF_NS + #define NRF_APPLICATION_WDT010 NRF_APPLICATION_WDT010_NS + #define NRF_APPLICATION_WDT011 NRF_APPLICATION_WDT011_NS + #define NRF_APPLICATION_IPCT NRF_APPLICATION_IPCT_NS + #define NRF_APPLICATION_SWI0 NRF_APPLICATION_SWI0_NS + #define NRF_APPLICATION_SWI1 NRF_APPLICATION_SWI1_NS + #define NRF_APPLICATION_SWI2 NRF_APPLICATION_SWI2_NS + #define NRF_APPLICATION_SWI3 NRF_APPLICATION_SWI3_NS + #define NRF_APPLICATION_SWI4 NRF_APPLICATION_SWI4_NS + #define NRF_APPLICATION_SWI5 NRF_APPLICATION_SWI5_NS + #define NRF_APPLICATION_SWI6 NRF_APPLICATION_SWI6_NS + #define NRF_APPLICATION_SWI7 NRF_APPLICATION_SWI7_NS + #define NRF_APPLICATION_BELLBOARD NRF_APPLICATION_BELLBOARD_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_APPLICATION_UICREXTENDED NRF_APPLICATION_UICREXTENDED_NS + #define NRF_APPLICATION_ICACHEDATA NRF_APPLICATION_ICACHEDATA_S + #define NRF_APPLICATION_ICACHEINFO NRF_APPLICATION_ICACHEINFO_S + #define NRF_APPLICATION_UICR NRF_APPLICATION_UICR_NS + #define NRF_APPLICATION_BICR NRF_APPLICATION_BICR_NS + #define NRF_APPLICATION_DCACHEDATA NRF_APPLICATION_DCACHEDATA_S + #define NRF_APPLICATION_DCACHEINFO NRF_APPLICATION_DCACHEINFO_S + #define NRF_APPLICATION_ETM NRF_APPLICATION_ETM_NS + #define NRF_APPLICATION_CTI NRF_APPLICATION_CTI_S + #define NRF_APPLICATION_CPUC NRF_APPLICATION_CPUC_S + #define NRF_APPLICATION_ICACHE NRF_APPLICATION_ICACHE_S + #define NRF_APPLICATION_DCACHE NRF_APPLICATION_DCACHE_S + #define NRF_APPLICATION_SPU000 NRF_APPLICATION_SPU000_S + #define NRF_APPLICATION_MPC NRF_APPLICATION_MPC_S + #define NRF_APPLICATION_MVDMA NRF_APPLICATION_MVDMA_S + #define NRF_APPLICATION_RAMC NRF_APPLICATION_RAMC_S + #define NRF_APPLICATION_HSFLL NRF_APPLICATION_HSFLL_S + #define NRF_APPLICATION_LRCCONF000 NRF_APPLICATION_LRCCONF000_S + #define NRF_APPLICATION_SPU010 NRF_APPLICATION_SPU010_S + #define NRF_APPLICATION_MEMCONF NRF_APPLICATION_MEMCONF_S + #define NRF_APPLICATION_WDT010 NRF_APPLICATION_WDT010_S + #define NRF_APPLICATION_WDT011 NRF_APPLICATION_WDT011_S + #define NRF_APPLICATION_ABB NRF_APPLICATION_ABB_S + #define NRF_APPLICATION_LRCCONF010 NRF_APPLICATION_LRCCONF010_S + #define NRF_APPLICATION_RESETINFO NRF_APPLICATION_RESETINFO_S + #define NRF_APPLICATION_IPCT NRF_APPLICATION_IPCT_S + #define NRF_APPLICATION_SWI0 NRF_APPLICATION_SWI0_NS + #define NRF_APPLICATION_SWI1 NRF_APPLICATION_SWI1_NS + #define NRF_APPLICATION_SWI2 NRF_APPLICATION_SWI2_NS + #define NRF_APPLICATION_SWI3 NRF_APPLICATION_SWI3_NS + #define NRF_APPLICATION_SWI4 NRF_APPLICATION_SWI4_NS + #define NRF_APPLICATION_SWI5 NRF_APPLICATION_SWI5_NS + #define NRF_APPLICATION_SWI6 NRF_APPLICATION_SWI6_NS + #define NRF_APPLICATION_SWI7 NRF_APPLICATION_SWI7_NS + #define NRF_APPLICATION_BELLBOARD NRF_APPLICATION_BELLBOARD_S +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_APPLICATION /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ + #define NRF_UICREXTENDED NRF_APPLICATION_UICREXTENDED + #define NRF_UICR NRF_APPLICATION_UICR + #define NRF_BICR NRF_APPLICATION_BICR + #define NRF_ETM NRF_APPLICATION_ETM + #define NRF_MVDMA NRF_APPLICATION_MVDMA + #define NRF_RAMC NRF_APPLICATION_RAMC + #define NRF_MEMCONF NRF_APPLICATION_MEMCONF + #define NRF_WDT010 NRF_APPLICATION_WDT010 + #define NRF_WDT011 NRF_APPLICATION_WDT011 + #define NRF_IPCT NRF_APPLICATION_IPCT + #define NRF_SWI0 NRF_APPLICATION_SWI0 + #define NRF_SWI1 NRF_APPLICATION_SWI1 + #define NRF_SWI2 NRF_APPLICATION_SWI2 + #define NRF_SWI3 NRF_APPLICATION_SWI3 + #define NRF_SWI4 NRF_APPLICATION_SWI4 + #define NRF_SWI5 NRF_APPLICATION_SWI5 + #define NRF_SWI6 NRF_APPLICATION_SWI6 + #define NRF_SWI7 NRF_APPLICATION_SWI7 + #define NRF_BELLBOARD NRF_APPLICATION_BELLBOARD + #else /*!< Remap all instances. */ + #define NRF_UICREXTENDED NRF_APPLICATION_UICREXTENDED + #define NRF_ICACHEDATA NRF_APPLICATION_ICACHEDATA + #define NRF_ICACHEINFO NRF_APPLICATION_ICACHEINFO + #define NRF_UICR NRF_APPLICATION_UICR + #define NRF_BICR NRF_APPLICATION_BICR + #define NRF_DCACHEDATA NRF_APPLICATION_DCACHEDATA + #define NRF_DCACHEINFO NRF_APPLICATION_DCACHEINFO + #define NRF_ETM NRF_APPLICATION_ETM + #define NRF_CTI NRF_APPLICATION_CTI + #define NRF_CPUC NRF_APPLICATION_CPUC + #define NRF_ICACHE NRF_APPLICATION_ICACHE + #define NRF_DCACHE NRF_APPLICATION_DCACHE + #define NRF_SPU000 NRF_APPLICATION_SPU000 + #define NRF_MPC NRF_APPLICATION_MPC + #define NRF_MVDMA NRF_APPLICATION_MVDMA + #define NRF_RAMC NRF_APPLICATION_RAMC + #define NRF_HSFLL NRF_APPLICATION_HSFLL + #define NRF_LRCCONF000 NRF_APPLICATION_LRCCONF000 + #define NRF_SPU010 NRF_APPLICATION_SPU010 + #define NRF_MEMCONF NRF_APPLICATION_MEMCONF + #define NRF_WDT010 NRF_APPLICATION_WDT010 + #define NRF_WDT011 NRF_APPLICATION_WDT011 + #define NRF_ABB NRF_APPLICATION_ABB + #define NRF_LRCCONF010 NRF_APPLICATION_LRCCONF010 + #define NRF_RESETINFO NRF_APPLICATION_RESETINFO + #define NRF_IPCT NRF_APPLICATION_IPCT + #define NRF_SWI0 NRF_APPLICATION_SWI0 + #define NRF_SWI1 NRF_APPLICATION_SWI1 + #define NRF_SWI2 NRF_APPLICATION_SWI2 + #define NRF_SWI3 NRF_APPLICATION_SWI3 + #define NRF_SWI4 NRF_APPLICATION_SWI4 + #define NRF_SWI5 NRF_APPLICATION_SWI5 + #define NRF_SWI6 NRF_APPLICATION_SWI6 + #define NRF_SWI7 NRF_APPLICATION_SWI7 + #define NRF_BELLBOARD NRF_APPLICATION_BELLBOARD + #endif /*!< NRF_TRUSTZONE_NONSECURE */ +#endif /*!< NRF_APPLICATION */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_APPLICATION_H */ + diff --git a/mdk/nrf9230_enga_application.svd b/mdk/nrf9230_enga_application.svd new file mode 100644 index 000000000..3eee350ea --- /dev/null +++ b/mdk/nrf9230_enga_application.svd @@ -0,0 +1,186420 @@ + + + + Nordic Semiconductor + Nordic + nrf9230_enga_application + nRF92 + 1 + nRF9230_enga reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 480 + 4 + + system_nrf9230_enga_application + + 480 + + + + UICREXTENDED_NS + Extended UICR. + 0x00000000 + UICREXTENDED + + + + 0 + 0x1000 + registers + + UICREXTENDED + 0x20 + + + 14 + 0x044 + GPIO[%s] + Unspecified + UICREXTENDED_GPIO + read-write + 0x000 + + INSTANCE + Description cluster: Address of the GPIO instance associated with GPIO[n] + 0x000 + read-write + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + OWN + Description cluster: Request ownership of the pins at GPIO port P[n] + 0x004 + read-write + 0x20 + + + PIN_0 + Pin number + 0 + 0 + + + NotOwn + Do not own the pin 0 + 0x1 + + + Own + Own the pin 0 + 0x0 + + + + + PIN_1 + Pin number + 1 + 1 + + + NotOwn + Do not own the pin 1 + 0x1 + + + Own + Own the pin 1 + 0x0 + + + + + PIN_2 + Pin number + 2 + 2 + + + NotOwn + Do not own the pin 2 + 0x1 + + + Own + Own the pin 2 + 0x0 + + + + + PIN_3 + Pin number + 3 + 3 + + + NotOwn + Do not own the pin 3 + 0x1 + + + Own + Own the pin 3 + 0x0 + + + + + PIN_4 + Pin number + 4 + 4 + + + NotOwn + Do not own the pin 4 + 0x1 + + + Own + Own the pin 4 + 0x0 + + + + + PIN_5 + Pin number + 5 + 5 + + + NotOwn + Do not own the pin 5 + 0x1 + + + Own + Own the pin 5 + 0x0 + + + + + PIN_6 + Pin number + 6 + 6 + + + NotOwn + Do not own the pin 6 + 0x1 + + + Own + Own the pin 6 + 0x0 + + + + + PIN_7 + Pin number + 7 + 7 + + + NotOwn + Do not own the pin 7 + 0x1 + + + Own + Own the pin 7 + 0x0 + + + + + PIN_8 + Pin number + 8 + 8 + + + NotOwn + Do not own the pin 8 + 0x1 + + + Own + Own the pin 8 + 0x0 + + + + + PIN_9 + Pin number + 9 + 9 + + + NotOwn + Do not own the pin 9 + 0x1 + + + Own + Own the pin 9 + 0x0 + + + + + PIN_10 + Pin number + 10 + 10 + + + NotOwn + Do not own the pin 10 + 0x1 + + + Own + Own the pin 10 + 0x0 + + + + + PIN_11 + Pin number + 11 + 11 + + + NotOwn + Do not own the pin 11 + 0x1 + + + Own + Own the pin 11 + 0x0 + + + + + PIN_12 + Pin number + 12 + 12 + + + NotOwn + Do not own the pin 12 + 0x1 + + + Own + Own the pin 12 + 0x0 + + + + + PIN_13 + Pin number + 13 + 13 + + + NotOwn + Do not own the pin 13 + 0x1 + + + Own + Own the pin 13 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the pins at GPIO port P[n] + 0x008 + read-write + 0x20 + + + PIN_0 + Pin number + 0 + 0 + + + Secure + The pin 0 is secure + 0x1 + + + NonSecure + The pin 0 is non-secure + 0x0 + + + + + PIN_1 + Pin number + 1 + 1 + + + Secure + The pin 1 is secure + 0x1 + + + NonSecure + The pin 1 is non-secure + 0x0 + + + + + PIN_2 + Pin number + 2 + 2 + + + Secure + The pin 2 is secure + 0x1 + + + NonSecure + The pin 2 is non-secure + 0x0 + + + + + PIN_3 + Pin number + 3 + 3 + + + Secure + The pin 3 is secure + 0x1 + + + NonSecure + The pin 3 is non-secure + 0x0 + + + + + PIN_4 + Pin number + 4 + 4 + + + Secure + The pin 4 is secure + 0x1 + + + NonSecure + The pin 4 is non-secure + 0x0 + + + + + PIN_5 + Pin number + 5 + 5 + + + Secure + The pin 5 is secure + 0x1 + + + NonSecure + The pin 5 is non-secure + 0x0 + + + + + PIN_6 + Pin number + 6 + 6 + + + Secure + The pin 6 is secure + 0x1 + + + NonSecure + The pin 6 is non-secure + 0x0 + + + + + PIN_7 + Pin number + 7 + 7 + + + Secure + The pin 7 is secure + 0x1 + + + NonSecure + The pin 7 is non-secure + 0x0 + + + + + PIN_8 + Pin number + 8 + 8 + + + Secure + The pin 8 is secure + 0x1 + + + NonSecure + The pin 8 is non-secure + 0x0 + + + + + PIN_9 + Pin number + 9 + 9 + + + Secure + The pin 9 is secure + 0x1 + + + NonSecure + The pin 9 is non-secure + 0x0 + + + + + PIN_10 + Pin number + 10 + 10 + + + Secure + The pin 10 is secure + 0x1 + + + NonSecure + The pin 10 is non-secure + 0x0 + + + + + PIN_11 + Pin number + 11 + 11 + + + Secure + The pin 11 is secure + 0x1 + + + NonSecure + The pin 11 is non-secure + 0x0 + + + + + PIN_12 + Pin number + 12 + 12 + + + Secure + The pin 12 is secure + 0x1 + + + NonSecure + The pin 12 is non-secure + 0x0 + + + + + PIN_13 + Pin number + 13 + 13 + + + Secure + The pin 13 is secure + 0x1 + + + NonSecure + The pin 13 is non-secure + 0x0 + + + + + + + 14 + 0x004 + PIN[%s] + Unspecified + UICREXTENDED_GPIO_PIN + read-write + 0x00C + + CTRLSEL + Description cluster: CTRLSEL values for PIN[o] of GPIO port P[n] + 0x000 + read-write + 0x20 + + + CTRLSEL + CTRLSEL value + 0 + 2 + + + + + + + + + ICACHEDATA_S + CACHEDATA + 0x02F00000 + ICACHEDATA + + + + 0 + 0x1000 + registers + + ICACHEDATA + 0x20 + + + 1024 + 0x040 + SET[%s] + Unspecified + ICACHEDATA_SET + read-write + 0x0 + + 2 + 0x020 + WAY[%s] + Unspecified + ICACHEDATA_SET_WAY + read-write + 0x0 + + 4 + 0x008 + DU[%s] + Unspecified + ICACHEDATA_SET_WAY_DU + read-write + 0x0 + + 0x2 + 0x4 + DATA[%s] + Description collection: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + Data + Data + 0 + 31 + read-only + + + + + + + + + + ICACHEINFO_S + CACHEINFO + 0x02F10000 + ICACHEINFO + + + + 0 + 0x1000 + registers + + ICACHEINFO + 0x20 + + + 1024 + 0x008 + SET[%s] + Unspecified + ICACHEINFO_SET + read-write + 0x0 + + 2 + 0x004 + WAY[%s] + Unspecified + ICACHEINFO_SET_WAY + read-write + 0x0 + + INFO + Description cluster: Cache information for SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + TAG + Cache tag. + 0 + 19 + read-only + + + DUV_0 + Data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_1 + Data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_2 + Data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_3 + Data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + D0 + Dirty status of combined data unit 0 and 1. + 28 + 28 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D1 + Dirty status of combined data unit 2 and 3. + 29 + 29 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + V + Line valid bit. + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0x0 + + + Valid + Valid cache line + 0x1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0x0 + + + Way1 + Way1 was most recently used + 0x1 + + + + + + + + + + + UICR_NS + User information configuration registers + 0x0FFF8000 + UICR + + + + 0 + 0x800 + registers + + UICR + 0x20 + + + 16 + 0x008 + MEM[%s] + Unspecified + UICR_MEM + read-write + 0x000 + + CONFIG + Description cluster: Memory configuration of the memory region + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + READ + 0 + 0 + + + NotAllowed + Read access to MEM[n] is not allowed + 0x1 + + + Allowed + Read access to MEM[n] is allowed + 0x0 + + + + + WRITE + 1 + 1 + + + NotAllowed + Write access to MEM[n] is not allowed + 0x1 + + + Allowed + Write access to MEM[n] is allowed + 0x0 + + + + + EXECUTE + 2 + 2 + + + NotAllowed + SW execution from MEM[n] is not allowed + 0x1 + + + Allowed + SW execution from MEM[n] is allowed + 0x0 + + + + + SECURE + 3 + 3 + + + Secure + Non-secure access to MEM[n] is not allowed + 0x1 + + + NonSecure + Non-secure access to MEM[n] is allowed + 0x0 + + + + + NSC + 4 + 4 + + + Disabled + Memory region is not non-secure callable + 0x1 + + + Enabled + Memory region is non-secure callable + 0x0 + + + + + OWNERID + Memory owner identification + 8 + 11 + + + ADDRESS + Memory region start address, bits [31:12] + 12 + 31 + + + + + SIZE + Description cluster: Size of the memory region + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + SIZE + Memory size in bytes + 0 + 31 + + + + + + 192 + 0x004 + PERIPH[%s] + Unspecified + UICR_PERIPH + read-write + 0x100 + + CONFIG + Description cluster: Peripheral configuration + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SECURE + Peripheral security mapping + 3 + 3 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + Peripheral is mapped in non-secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + PROCESSOR + Processor ID of the processor that will receive the peripheral IRQ + 8 + 11 + + + ADDRESS + Peripheral address, bits [31:12] + 12 + 31 + + + + + + 4 + 0x00C + GPIOTE[%s] + Unspecified + UICR_GPIOTE + read-write + 0x480 + + INSTANCE + Description cluster: Address of the GPIOTE instance associated with GPIOTE[n] + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_GPIOTE_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of GPIOTE[n] + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of GPIOTE[n] + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + + IPCT + Unspecified + UICR_IPCT + read-write + 0x4B0 + + LOCAL + Unspecified + UICR_IPCT_LOCAL + read-write + 0x000 + + CH + Unspecified + UICR_IPCT_LOCAL_CH + read-write + 0x000 + + SECURE + Request permission for the channels of IPCT in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + INTERRUPT + Unspecified + UICR_IPCT_LOCAL_INTERRUPT + read-write + 0x004 + + SECURE + Request permission for the interrupts of IPCT in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + Secure + The interrupt 0 is secure + 0x1 + + + NonSecure + The interrupt 0 is non-secure + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + Secure + The interrupt 1 is secure + 0x1 + + + NonSecure + The interrupt 1 is non-secure + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + Secure + The interrupt 2 is secure + 0x1 + + + NonSecure + The interrupt 2 is non-secure + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + Secure + The interrupt 3 is secure + 0x1 + + + NonSecure + The interrupt 3 is non-secure + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + Secure + The interrupt 4 is secure + 0x1 + + + NonSecure + The interrupt 4 is non-secure + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + Secure + The interrupt 5 is secure + 0x1 + + + NonSecure + The interrupt 5 is non-secure + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + Secure + The interrupt 6 is secure + 0x1 + + + NonSecure + The interrupt 6 is non-secure + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + Secure + The interrupt 7 is secure + 0x1 + + + NonSecure + The interrupt 7 is non-secure + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + Secure + The interrupt 8 is secure + 0x1 + + + NonSecure + The interrupt 8 is non-secure + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + Secure + The interrupt 9 is secure + 0x1 + + + NonSecure + The interrupt 9 is non-secure + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + Secure + The interrupt 10 is secure + 0x1 + + + NonSecure + The interrupt 10 is non-secure + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + Secure + The interrupt 11 is secure + 0x1 + + + NonSecure + The interrupt 11 is non-secure + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + Secure + The interrupt 12 is secure + 0x1 + + + NonSecure + The interrupt 12 is non-secure + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + Secure + The interrupt 13 is secure + 0x1 + + + NonSecure + The interrupt 13 is non-secure + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + Secure + The interrupt 14 is secure + 0x1 + + + NonSecure + The interrupt 14 is non-secure + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + Secure + The interrupt 15 is secure + 0x1 + + + NonSecure + The interrupt 15 is non-secure + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + Secure + The interrupt 16 is secure + 0x1 + + + NonSecure + The interrupt 16 is non-secure + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + Secure + The interrupt 17 is secure + 0x1 + + + NonSecure + The interrupt 17 is non-secure + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + Secure + The interrupt 18 is secure + 0x1 + + + NonSecure + The interrupt 18 is non-secure + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + Secure + The interrupt 19 is secure + 0x1 + + + NonSecure + The interrupt 19 is non-secure + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + Secure + The interrupt 20 is secure + 0x1 + + + NonSecure + The interrupt 20 is non-secure + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + Secure + The interrupt 21 is secure + 0x1 + + + NonSecure + The interrupt 21 is non-secure + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + Secure + The interrupt 22 is secure + 0x1 + + + NonSecure + The interrupt 22 is non-secure + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + Secure + The interrupt 23 is secure + 0x1 + + + NonSecure + The interrupt 23 is non-secure + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + Secure + The interrupt 24 is secure + 0x1 + + + NonSecure + The interrupt 24 is non-secure + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + Secure + The interrupt 25 is secure + 0x1 + + + NonSecure + The interrupt 25 is non-secure + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + Secure + The interrupt 26 is secure + 0x1 + + + NonSecure + The interrupt 26 is non-secure + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + Secure + The interrupt 27 is secure + 0x1 + + + NonSecure + The interrupt 27 is non-secure + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + Secure + The interrupt 28 is secure + 0x1 + + + NonSecure + The interrupt 28 is non-secure + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + Secure + The interrupt 29 is secure + 0x1 + + + NonSecure + The interrupt 29 is non-secure + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + Secure + The interrupt 30 is secure + 0x1 + + + NonSecure + The interrupt 30 is non-secure + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + Secure + The interrupt 31 is secure + 0x1 + + + NonSecure + The interrupt 31 is non-secure + 0x0 + + + + + + + + + 2 + 0x014 + GLOBAL[%s] + Unspecified + UICR_IPCT_GLOBAL + read-write + 0x008 + + INSTANCE + Description cluster: Address of the IPCT instance associated with IPCT[n].GLOBAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_IPCT_GLOBAL_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of IPCT[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of IPCT[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + INTERRUPT + Unspecified + UICR_IPCT_GLOBAL_INTERRUPT + read-write + 0x00C + + OWN + Description cluster: Request ownership of the interrupts of IPCT[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + NotOwn + Do not own the interrupt 0 + 0x1 + + + Own + Own the interrupt 0 + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + NotOwn + Do not own the interrupt 1 + 0x1 + + + Own + Own the interrupt 1 + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + NotOwn + Do not own the interrupt 2 + 0x1 + + + Own + Own the interrupt 2 + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + NotOwn + Do not own the interrupt 3 + 0x1 + + + Own + Own the interrupt 3 + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + NotOwn + Do not own the interrupt 4 + 0x1 + + + Own + Own the interrupt 4 + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + NotOwn + Do not own the interrupt 5 + 0x1 + + + Own + Own the interrupt 5 + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + NotOwn + Do not own the interrupt 6 + 0x1 + + + Own + Own the interrupt 6 + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + NotOwn + Do not own the interrupt 7 + 0x1 + + + Own + Own the interrupt 7 + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + NotOwn + Do not own the interrupt 8 + 0x1 + + + Own + Own the interrupt 8 + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + NotOwn + Do not own the interrupt 9 + 0x1 + + + Own + Own the interrupt 9 + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + NotOwn + Do not own the interrupt 10 + 0x1 + + + Own + Own the interrupt 10 + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + NotOwn + Do not own the interrupt 11 + 0x1 + + + Own + Own the interrupt 11 + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + NotOwn + Do not own the interrupt 12 + 0x1 + + + Own + Own the interrupt 12 + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + NotOwn + Do not own the interrupt 13 + 0x1 + + + Own + Own the interrupt 13 + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + NotOwn + Do not own the interrupt 14 + 0x1 + + + Own + Own the interrupt 14 + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + NotOwn + Do not own the interrupt 15 + 0x1 + + + Own + Own the interrupt 15 + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + NotOwn + Do not own the interrupt 16 + 0x1 + + + Own + Own the interrupt 16 + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + NotOwn + Do not own the interrupt 17 + 0x1 + + + Own + Own the interrupt 17 + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + NotOwn + Do not own the interrupt 18 + 0x1 + + + Own + Own the interrupt 18 + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + NotOwn + Do not own the interrupt 19 + 0x1 + + + Own + Own the interrupt 19 + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + NotOwn + Do not own the interrupt 20 + 0x1 + + + Own + Own the interrupt 20 + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + NotOwn + Do not own the interrupt 21 + 0x1 + + + Own + Own the interrupt 21 + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + NotOwn + Do not own the interrupt 22 + 0x1 + + + Own + Own the interrupt 22 + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + NotOwn + Do not own the interrupt 23 + 0x1 + + + Own + Own the interrupt 23 + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + NotOwn + Do not own the interrupt 24 + 0x1 + + + Own + Own the interrupt 24 + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + NotOwn + Do not own the interrupt 25 + 0x1 + + + Own + Own the interrupt 25 + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + NotOwn + Do not own the interrupt 26 + 0x1 + + + Own + Own the interrupt 26 + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + NotOwn + Do not own the interrupt 27 + 0x1 + + + Own + Own the interrupt 27 + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + NotOwn + Do not own the interrupt 28 + 0x1 + + + Own + Own the interrupt 28 + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + NotOwn + Do not own the interrupt 29 + 0x1 + + + Own + Own the interrupt 29 + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + NotOwn + Do not own the interrupt 30 + 0x1 + + + Own + Own the interrupt 30 + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + NotOwn + Do not own the interrupt 31 + 0x1 + + + Own + Own the interrupt 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the interrupts of IPCT[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + Secure + The interrupt 0 is secure + 0x1 + + + NonSecure + The interrupt 0 is non-secure + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + Secure + The interrupt 1 is secure + 0x1 + + + NonSecure + The interrupt 1 is non-secure + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + Secure + The interrupt 2 is secure + 0x1 + + + NonSecure + The interrupt 2 is non-secure + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + Secure + The interrupt 3 is secure + 0x1 + + + NonSecure + The interrupt 3 is non-secure + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + Secure + The interrupt 4 is secure + 0x1 + + + NonSecure + The interrupt 4 is non-secure + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + Secure + The interrupt 5 is secure + 0x1 + + + NonSecure + The interrupt 5 is non-secure + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + Secure + The interrupt 6 is secure + 0x1 + + + NonSecure + The interrupt 6 is non-secure + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + Secure + The interrupt 7 is secure + 0x1 + + + NonSecure + The interrupt 7 is non-secure + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + Secure + The interrupt 8 is secure + 0x1 + + + NonSecure + The interrupt 8 is non-secure + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + Secure + The interrupt 9 is secure + 0x1 + + + NonSecure + The interrupt 9 is non-secure + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + Secure + The interrupt 10 is secure + 0x1 + + + NonSecure + The interrupt 10 is non-secure + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + Secure + The interrupt 11 is secure + 0x1 + + + NonSecure + The interrupt 11 is non-secure + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + Secure + The interrupt 12 is secure + 0x1 + + + NonSecure + The interrupt 12 is non-secure + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + Secure + The interrupt 13 is secure + 0x1 + + + NonSecure + The interrupt 13 is non-secure + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + Secure + The interrupt 14 is secure + 0x1 + + + NonSecure + The interrupt 14 is non-secure + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + Secure + The interrupt 15 is secure + 0x1 + + + NonSecure + The interrupt 15 is non-secure + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + Secure + The interrupt 16 is secure + 0x1 + + + NonSecure + The interrupt 16 is non-secure + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + Secure + The interrupt 17 is secure + 0x1 + + + NonSecure + The interrupt 17 is non-secure + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + Secure + The interrupt 18 is secure + 0x1 + + + NonSecure + The interrupt 18 is non-secure + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + Secure + The interrupt 19 is secure + 0x1 + + + NonSecure + The interrupt 19 is non-secure + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + Secure + The interrupt 20 is secure + 0x1 + + + NonSecure + The interrupt 20 is non-secure + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + Secure + The interrupt 21 is secure + 0x1 + + + NonSecure + The interrupt 21 is non-secure + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + Secure + The interrupt 22 is secure + 0x1 + + + NonSecure + The interrupt 22 is non-secure + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + Secure + The interrupt 23 is secure + 0x1 + + + NonSecure + The interrupt 23 is non-secure + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + Secure + The interrupt 24 is secure + 0x1 + + + NonSecure + The interrupt 24 is non-secure + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + Secure + The interrupt 25 is secure + 0x1 + + + NonSecure + The interrupt 25 is non-secure + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + Secure + The interrupt 26 is secure + 0x1 + + + NonSecure + The interrupt 26 is non-secure + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + Secure + The interrupt 27 is secure + 0x1 + + + NonSecure + The interrupt 27 is non-secure + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + Secure + The interrupt 28 is secure + 0x1 + + + NonSecure + The interrupt 28 is non-secure + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + Secure + The interrupt 29 is secure + 0x1 + + + NonSecure + The interrupt 29 is non-secure + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + Secure + The interrupt 30 is secure + 0x1 + + + NonSecure + The interrupt 30 is non-secure + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + Secure + The interrupt 31 is secure + 0x1 + + + NonSecure + The interrupt 31 is non-secure + 0x0 + + + + + + + + + + DPPI + Unspecified + UICR_DPPI + read-write + 0x4E0 + + 2 + 0x014 + LOCAL[%s] + Unspecified + UICR_DPPI_LOCAL + read-write + 0x000 + + INSTANCE + Description cluster: Address of the DPPI instance associated with DPPI[n].LOCAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_DPPI_LOCAL_CH + read-write + 0x004 + + SECURE + Description cluster: Request permission for the channels of DPPI[n] in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + LINK + Unspecified + UICR_DPPI_LOCAL_CH_LINK + read-write + 0x004 + + DIR + Description cluster: Request linking the channels of DPPI[n] in local domain as source or sink + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link direction + 0 + 0 + + + Source + The channel 0 is linked as source + 0x1 + + + Sink + The channel 0 is linked as sink + 0x0 + + + + + CH_1 + Link direction + 1 + 1 + + + Source + The channel 1 is linked as source + 0x1 + + + Sink + The channel 1 is linked as sink + 0x0 + + + + + CH_2 + Link direction + 2 + 2 + + + Source + The channel 2 is linked as source + 0x1 + + + Sink + The channel 2 is linked as sink + 0x0 + + + + + CH_3 + Link direction + 3 + 3 + + + Source + The channel 3 is linked as source + 0x1 + + + Sink + The channel 3 is linked as sink + 0x0 + + + + + CH_4 + Link direction + 4 + 4 + + + Source + The channel 4 is linked as source + 0x1 + + + Sink + The channel 4 is linked as sink + 0x0 + + + + + CH_5 + Link direction + 5 + 5 + + + Source + The channel 5 is linked as source + 0x1 + + + Sink + The channel 5 is linked as sink + 0x0 + + + + + CH_6 + Link direction + 6 + 6 + + + Source + The channel 6 is linked as source + 0x1 + + + Sink + The channel 6 is linked as sink + 0x0 + + + + + CH_7 + Link direction + 7 + 7 + + + Source + The channel 7 is linked as source + 0x1 + + + Sink + The channel 7 is linked as sink + 0x0 + + + + + CH_8 + Link direction + 8 + 8 + + + Source + The channel 8 is linked as source + 0x1 + + + Sink + The channel 8 is linked as sink + 0x0 + + + + + CH_9 + Link direction + 9 + 9 + + + Source + The channel 9 is linked as source + 0x1 + + + Sink + The channel 9 is linked as sink + 0x0 + + + + + CH_10 + Link direction + 10 + 10 + + + Source + The channel 10 is linked as source + 0x1 + + + Sink + The channel 10 is linked as sink + 0x0 + + + + + CH_11 + Link direction + 11 + 11 + + + Source + The channel 11 is linked as source + 0x1 + + + Sink + The channel 11 is linked as sink + 0x0 + + + + + CH_12 + Link direction + 12 + 12 + + + Source + The channel 12 is linked as source + 0x1 + + + Sink + The channel 12 is linked as sink + 0x0 + + + + + CH_13 + Link direction + 13 + 13 + + + Source + The channel 13 is linked as source + 0x1 + + + Sink + The channel 13 is linked as sink + 0x0 + + + + + CH_14 + Link direction + 14 + 14 + + + Source + The channel 14 is linked as source + 0x1 + + + Sink + The channel 14 is linked as sink + 0x0 + + + + + CH_15 + Link direction + 15 + 15 + + + Source + The channel 15 is linked as source + 0x1 + + + Sink + The channel 15 is linked as sink + 0x0 + + + + + CH_16 + Link direction + 16 + 16 + + + Source + The channel 16 is linked as source + 0x1 + + + Sink + The channel 16 is linked as sink + 0x0 + + + + + CH_17 + Link direction + 17 + 17 + + + Source + The channel 17 is linked as source + 0x1 + + + Sink + The channel 17 is linked as sink + 0x0 + + + + + CH_18 + Link direction + 18 + 18 + + + Source + The channel 18 is linked as source + 0x1 + + + Sink + The channel 18 is linked as sink + 0x0 + + + + + CH_19 + Link direction + 19 + 19 + + + Source + The channel 19 is linked as source + 0x1 + + + Sink + The channel 19 is linked as sink + 0x0 + + + + + CH_20 + Link direction + 20 + 20 + + + Source + The channel 20 is linked as source + 0x1 + + + Sink + The channel 20 is linked as sink + 0x0 + + + + + CH_21 + Link direction + 21 + 21 + + + Source + The channel 21 is linked as source + 0x1 + + + Sink + The channel 21 is linked as sink + 0x0 + + + + + CH_22 + Link direction + 22 + 22 + + + Source + The channel 22 is linked as source + 0x1 + + + Sink + The channel 22 is linked as sink + 0x0 + + + + + CH_23 + Link direction + 23 + 23 + + + Source + The channel 23 is linked as source + 0x1 + + + Sink + The channel 23 is linked as sink + 0x0 + + + + + CH_24 + Link direction + 24 + 24 + + + Source + The channel 24 is linked as source + 0x1 + + + Sink + The channel 24 is linked as sink + 0x0 + + + + + CH_25 + Link direction + 25 + 25 + + + Source + The channel 25 is linked as source + 0x1 + + + Sink + The channel 25 is linked as sink + 0x0 + + + + + CH_26 + Link direction + 26 + 26 + + + Source + The channel 26 is linked as source + 0x1 + + + Sink + The channel 26 is linked as sink + 0x0 + + + + + CH_27 + Link direction + 27 + 27 + + + Source + The channel 27 is linked as source + 0x1 + + + Sink + The channel 27 is linked as sink + 0x0 + + + + + CH_28 + Link direction + 28 + 28 + + + Source + The channel 28 is linked as source + 0x1 + + + Sink + The channel 28 is linked as sink + 0x0 + + + + + CH_29 + Link direction + 29 + 29 + + + Source + The channel 29 is linked as source + 0x1 + + + Sink + The channel 29 is linked as sink + 0x0 + + + + + CH_30 + Link direction + 30 + 30 + + + Source + The channel 30 is linked as source + 0x1 + + + Sink + The channel 30 is linked as sink + 0x0 + + + + + CH_31 + Link direction + 31 + 31 + + + Source + The channel 31 is linked as source + 0x1 + + + Sink + The channel 31 is linked as sink + 0x0 + + + + + + + EN + Description cluster: Request linking of the channels of DPPI[n] in the local domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link enable + 0 + 0 + + + Disabled + The channel 0 is disabled + 0x1 + + + Enabled + The channel 0 is enabled + 0x0 + + + + + CH_1 + Link enable + 1 + 1 + + + Disabled + The channel 1 is disabled + 0x1 + + + Enabled + The channel 1 is enabled + 0x0 + + + + + CH_2 + Link enable + 2 + 2 + + + Disabled + The channel 2 is disabled + 0x1 + + + Enabled + The channel 2 is enabled + 0x0 + + + + + CH_3 + Link enable + 3 + 3 + + + Disabled + The channel 3 is disabled + 0x1 + + + Enabled + The channel 3 is enabled + 0x0 + + + + + CH_4 + Link enable + 4 + 4 + + + Disabled + The channel 4 is disabled + 0x1 + + + Enabled + The channel 4 is enabled + 0x0 + + + + + CH_5 + Link enable + 5 + 5 + + + Disabled + The channel 5 is disabled + 0x1 + + + Enabled + The channel 5 is enabled + 0x0 + + + + + CH_6 + Link enable + 6 + 6 + + + Disabled + The channel 6 is disabled + 0x1 + + + Enabled + The channel 6 is enabled + 0x0 + + + + + CH_7 + Link enable + 7 + 7 + + + Disabled + The channel 7 is disabled + 0x1 + + + Enabled + The channel 7 is enabled + 0x0 + + + + + CH_8 + Link enable + 8 + 8 + + + Disabled + The channel 8 is disabled + 0x1 + + + Enabled + The channel 8 is enabled + 0x0 + + + + + CH_9 + Link enable + 9 + 9 + + + Disabled + The channel 9 is disabled + 0x1 + + + Enabled + The channel 9 is enabled + 0x0 + + + + + CH_10 + Link enable + 10 + 10 + + + Disabled + The channel 10 is disabled + 0x1 + + + Enabled + The channel 10 is enabled + 0x0 + + + + + CH_11 + Link enable + 11 + 11 + + + Disabled + The channel 11 is disabled + 0x1 + + + Enabled + The channel 11 is enabled + 0x0 + + + + + CH_12 + Link enable + 12 + 12 + + + Disabled + The channel 12 is disabled + 0x1 + + + Enabled + The channel 12 is enabled + 0x0 + + + + + CH_13 + Link enable + 13 + 13 + + + Disabled + The channel 13 is disabled + 0x1 + + + Enabled + The channel 13 is enabled + 0x0 + + + + + CH_14 + Link enable + 14 + 14 + + + Disabled + The channel 14 is disabled + 0x1 + + + Enabled + The channel 14 is enabled + 0x0 + + + + + CH_15 + Link enable + 15 + 15 + + + Disabled + The channel 15 is disabled + 0x1 + + + Enabled + The channel 15 is enabled + 0x0 + + + + + CH_16 + Link enable + 16 + 16 + + + Disabled + The channel 16 is disabled + 0x1 + + + Enabled + The channel 16 is enabled + 0x0 + + + + + CH_17 + Link enable + 17 + 17 + + + Disabled + The channel 17 is disabled + 0x1 + + + Enabled + The channel 17 is enabled + 0x0 + + + + + CH_18 + Link enable + 18 + 18 + + + Disabled + The channel 18 is disabled + 0x1 + + + Enabled + The channel 18 is enabled + 0x0 + + + + + CH_19 + Link enable + 19 + 19 + + + Disabled + The channel 19 is disabled + 0x1 + + + Enabled + The channel 19 is enabled + 0x0 + + + + + CH_20 + Link enable + 20 + 20 + + + Disabled + The channel 20 is disabled + 0x1 + + + Enabled + The channel 20 is enabled + 0x0 + + + + + CH_21 + Link enable + 21 + 21 + + + Disabled + The channel 21 is disabled + 0x1 + + + Enabled + The channel 21 is enabled + 0x0 + + + + + CH_22 + Link enable + 22 + 22 + + + Disabled + The channel 22 is disabled + 0x1 + + + Enabled + The channel 22 is enabled + 0x0 + + + + + CH_23 + Link enable + 23 + 23 + + + Disabled + The channel 23 is disabled + 0x1 + + + Enabled + The channel 23 is enabled + 0x0 + + + + + CH_24 + Link enable + 24 + 24 + + + Disabled + The channel 24 is disabled + 0x1 + + + Enabled + The channel 24 is enabled + 0x0 + + + + + CH_25 + Link enable + 25 + 25 + + + Disabled + The channel 25 is disabled + 0x1 + + + Enabled + The channel 25 is enabled + 0x0 + + + + + CH_26 + Link enable + 26 + 26 + + + Disabled + The channel 26 is disabled + 0x1 + + + Enabled + The channel 26 is enabled + 0x0 + + + + + CH_27 + Link enable + 27 + 27 + + + Disabled + The channel 27 is disabled + 0x1 + + + Enabled + The channel 27 is enabled + 0x0 + + + + + CH_28 + Link enable + 28 + 28 + + + Disabled + The channel 28 is disabled + 0x1 + + + Enabled + The channel 28 is enabled + 0x0 + + + + + CH_29 + Link enable + 29 + 29 + + + Disabled + The channel 29 is disabled + 0x1 + + + Enabled + The channel 29 is enabled + 0x0 + + + + + CH_30 + Link enable + 30 + 30 + + + Disabled + The channel 30 is disabled + 0x1 + + + Enabled + The channel 30 is enabled + 0x0 + + + + + CH_31 + Link enable + 31 + 31 + + + Disabled + The channel 31 is disabled + 0x1 + + + Enabled + The channel 31 is enabled + 0x0 + + + + + + + + + CHG + Unspecified + UICR_DPPI_LOCAL_CHG + read-write + 0x010 + + SECURE + Description cluster: Request permission for the channel groups of DPPI[n] in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + Secure + The channel group 0 is secure + 0x1 + + + NonSecure + The channel group 0 is non-secure + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + Secure + The channel group 1 is secure + 0x1 + + + NonSecure + The channel group 1 is non-secure + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + Secure + The channel group 2 is secure + 0x1 + + + NonSecure + The channel group 2 is non-secure + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + Secure + The channel group 3 is secure + 0x1 + + + NonSecure + The channel group 3 is non-secure + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + Secure + The channel group 4 is secure + 0x1 + + + NonSecure + The channel group 4 is non-secure + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + Secure + The channel group 5 is secure + 0x1 + + + NonSecure + The channel group 5 is non-secure + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + Secure + The channel group 6 is secure + 0x1 + + + NonSecure + The channel group 6 is non-secure + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + Secure + The channel group 7 is secure + 0x1 + + + NonSecure + The channel group 7 is non-secure + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + Secure + The channel group 8 is secure + 0x1 + + + NonSecure + The channel group 8 is non-secure + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + Secure + The channel group 9 is secure + 0x1 + + + NonSecure + The channel group 9 is non-secure + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + Secure + The channel group 10 is secure + 0x1 + + + NonSecure + The channel group 10 is non-secure + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + Secure + The channel group 11 is secure + 0x1 + + + NonSecure + The channel group 11 is non-secure + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + Secure + The channel group 12 is secure + 0x1 + + + NonSecure + The channel group 12 is non-secure + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + Secure + The channel group 13 is secure + 0x1 + + + NonSecure + The channel group 13 is non-secure + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + Secure + The channel group 14 is secure + 0x1 + + + NonSecure + The channel group 14 is non-secure + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + Secure + The channel group 15 is secure + 0x1 + + + NonSecure + The channel group 15 is non-secure + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + Secure + The channel group 16 is secure + 0x1 + + + NonSecure + The channel group 16 is non-secure + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + Secure + The channel group 17 is secure + 0x1 + + + NonSecure + The channel group 17 is non-secure + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + Secure + The channel group 18 is secure + 0x1 + + + NonSecure + The channel group 18 is non-secure + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + Secure + The channel group 19 is secure + 0x1 + + + NonSecure + The channel group 19 is non-secure + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + Secure + The channel group 20 is secure + 0x1 + + + NonSecure + The channel group 20 is non-secure + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + Secure + The channel group 21 is secure + 0x1 + + + NonSecure + The channel group 21 is non-secure + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + Secure + The channel group 22 is secure + 0x1 + + + NonSecure + The channel group 22 is non-secure + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + Secure + The channel group 23 is secure + 0x1 + + + NonSecure + The channel group 23 is non-secure + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + Secure + The channel group 24 is secure + 0x1 + + + NonSecure + The channel group 24 is non-secure + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + Secure + The channel group 25 is secure + 0x1 + + + NonSecure + The channel group 25 is non-secure + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + Secure + The channel group 26 is secure + 0x1 + + + NonSecure + The channel group 26 is non-secure + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + Secure + The channel group 27 is secure + 0x1 + + + NonSecure + The channel group 27 is non-secure + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + Secure + The channel group 28 is secure + 0x1 + + + NonSecure + The channel group 28 is non-secure + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + Secure + The channel group 29 is secure + 0x1 + + + NonSecure + The channel group 29 is non-secure + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + Secure + The channel group 30 is secure + 0x1 + + + NonSecure + The channel group 30 is non-secure + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + Secure + The channel group 31 is secure + 0x1 + + + NonSecure + The channel group 31 is non-secure + 0x0 + + + + + + + + + 12 + 0x01C + GLOBAL[%s] + Unspecified + UICR_DPPI_GLOBAL + read-write + 0x028 + + INSTANCE + Description cluster: Address of the DPPI instance associated with DPPI[n].GLOBAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_DPPI_GLOBAL_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of DPPI[n] in Global Domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of DPPI[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + LINK + Unspecified + UICR_DPPI_GLOBAL_CH_LINK + read-write + 0x008 + + DIR + Description cluster: Request linking the channels of DPPI[n] in Global domain as source or sink + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link direction + 0 + 0 + + + Source + The channel 0 is linked as source + 0x1 + + + Sink + The channel 0 is linked as sink + 0x0 + + + + + CH_1 + Link direction + 1 + 1 + + + Source + The channel 1 is linked as source + 0x1 + + + Sink + The channel 1 is linked as sink + 0x0 + + + + + CH_2 + Link direction + 2 + 2 + + + Source + The channel 2 is linked as source + 0x1 + + + Sink + The channel 2 is linked as sink + 0x0 + + + + + CH_3 + Link direction + 3 + 3 + + + Source + The channel 3 is linked as source + 0x1 + + + Sink + The channel 3 is linked as sink + 0x0 + + + + + CH_4 + Link direction + 4 + 4 + + + Source + The channel 4 is linked as source + 0x1 + + + Sink + The channel 4 is linked as sink + 0x0 + + + + + CH_5 + Link direction + 5 + 5 + + + Source + The channel 5 is linked as source + 0x1 + + + Sink + The channel 5 is linked as sink + 0x0 + + + + + CH_6 + Link direction + 6 + 6 + + + Source + The channel 6 is linked as source + 0x1 + + + Sink + The channel 6 is linked as sink + 0x0 + + + + + CH_7 + Link direction + 7 + 7 + + + Source + The channel 7 is linked as source + 0x1 + + + Sink + The channel 7 is linked as sink + 0x0 + + + + + CH_8 + Link direction + 8 + 8 + + + Source + The channel 8 is linked as source + 0x1 + + + Sink + The channel 8 is linked as sink + 0x0 + + + + + CH_9 + Link direction + 9 + 9 + + + Source + The channel 9 is linked as source + 0x1 + + + Sink + The channel 9 is linked as sink + 0x0 + + + + + CH_10 + Link direction + 10 + 10 + + + Source + The channel 10 is linked as source + 0x1 + + + Sink + The channel 10 is linked as sink + 0x0 + + + + + CH_11 + Link direction + 11 + 11 + + + Source + The channel 11 is linked as source + 0x1 + + + Sink + The channel 11 is linked as sink + 0x0 + + + + + CH_12 + Link direction + 12 + 12 + + + Source + The channel 12 is linked as source + 0x1 + + + Sink + The channel 12 is linked as sink + 0x0 + + + + + CH_13 + Link direction + 13 + 13 + + + Source + The channel 13 is linked as source + 0x1 + + + Sink + The channel 13 is linked as sink + 0x0 + + + + + CH_14 + Link direction + 14 + 14 + + + Source + The channel 14 is linked as source + 0x1 + + + Sink + The channel 14 is linked as sink + 0x0 + + + + + CH_15 + Link direction + 15 + 15 + + + Source + The channel 15 is linked as source + 0x1 + + + Sink + The channel 15 is linked as sink + 0x0 + + + + + CH_16 + Link direction + 16 + 16 + + + Source + The channel 16 is linked as source + 0x1 + + + Sink + The channel 16 is linked as sink + 0x0 + + + + + CH_17 + Link direction + 17 + 17 + + + Source + The channel 17 is linked as source + 0x1 + + + Sink + The channel 17 is linked as sink + 0x0 + + + + + CH_18 + Link direction + 18 + 18 + + + Source + The channel 18 is linked as source + 0x1 + + + Sink + The channel 18 is linked as sink + 0x0 + + + + + CH_19 + Link direction + 19 + 19 + + + Source + The channel 19 is linked as source + 0x1 + + + Sink + The channel 19 is linked as sink + 0x0 + + + + + CH_20 + Link direction + 20 + 20 + + + Source + The channel 20 is linked as source + 0x1 + + + Sink + The channel 20 is linked as sink + 0x0 + + + + + CH_21 + Link direction + 21 + 21 + + + Source + The channel 21 is linked as source + 0x1 + + + Sink + The channel 21 is linked as sink + 0x0 + + + + + CH_22 + Link direction + 22 + 22 + + + Source + The channel 22 is linked as source + 0x1 + + + Sink + The channel 22 is linked as sink + 0x0 + + + + + CH_23 + Link direction + 23 + 23 + + + Source + The channel 23 is linked as source + 0x1 + + + Sink + The channel 23 is linked as sink + 0x0 + + + + + CH_24 + Link direction + 24 + 24 + + + Source + The channel 24 is linked as source + 0x1 + + + Sink + The channel 24 is linked as sink + 0x0 + + + + + CH_25 + Link direction + 25 + 25 + + + Source + The channel 25 is linked as source + 0x1 + + + Sink + The channel 25 is linked as sink + 0x0 + + + + + CH_26 + Link direction + 26 + 26 + + + Source + The channel 26 is linked as source + 0x1 + + + Sink + The channel 26 is linked as sink + 0x0 + + + + + CH_27 + Link direction + 27 + 27 + + + Source + The channel 27 is linked as source + 0x1 + + + Sink + The channel 27 is linked as sink + 0x0 + + + + + CH_28 + Link direction + 28 + 28 + + + Source + The channel 28 is linked as source + 0x1 + + + Sink + The channel 28 is linked as sink + 0x0 + + + + + CH_29 + Link direction + 29 + 29 + + + Source + The channel 29 is linked as source + 0x1 + + + Sink + The channel 29 is linked as sink + 0x0 + + + + + CH_30 + Link direction + 30 + 30 + + + Source + The channel 30 is linked as source + 0x1 + + + Sink + The channel 30 is linked as sink + 0x0 + + + + + CH_31 + Link direction + 31 + 31 + + + Source + The channel 31 is linked as source + 0x1 + + + Sink + The channel 31 is linked as sink + 0x0 + + + + + + + EN + Description cluster: Request linking of the channels of DPPI[n] in the Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link enable + 0 + 0 + + + Disabled + The channel 0 is disabled + 0x1 + + + Enabled + The channel 0 is enabled + 0x0 + + + + + CH_1 + Link enable + 1 + 1 + + + Disabled + The channel 1 is disabled + 0x1 + + + Enabled + The channel 1 is enabled + 0x0 + + + + + CH_2 + Link enable + 2 + 2 + + + Disabled + The channel 2 is disabled + 0x1 + + + Enabled + The channel 2 is enabled + 0x0 + + + + + CH_3 + Link enable + 3 + 3 + + + Disabled + The channel 3 is disabled + 0x1 + + + Enabled + The channel 3 is enabled + 0x0 + + + + + CH_4 + Link enable + 4 + 4 + + + Disabled + The channel 4 is disabled + 0x1 + + + Enabled + The channel 4 is enabled + 0x0 + + + + + CH_5 + Link enable + 5 + 5 + + + Disabled + The channel 5 is disabled + 0x1 + + + Enabled + The channel 5 is enabled + 0x0 + + + + + CH_6 + Link enable + 6 + 6 + + + Disabled + The channel 6 is disabled + 0x1 + + + Enabled + The channel 6 is enabled + 0x0 + + + + + CH_7 + Link enable + 7 + 7 + + + Disabled + The channel 7 is disabled + 0x1 + + + Enabled + The channel 7 is enabled + 0x0 + + + + + CH_8 + Link enable + 8 + 8 + + + Disabled + The channel 8 is disabled + 0x1 + + + Enabled + The channel 8 is enabled + 0x0 + + + + + CH_9 + Link enable + 9 + 9 + + + Disabled + The channel 9 is disabled + 0x1 + + + Enabled + The channel 9 is enabled + 0x0 + + + + + CH_10 + Link enable + 10 + 10 + + + Disabled + The channel 10 is disabled + 0x1 + + + Enabled + The channel 10 is enabled + 0x0 + + + + + CH_11 + Link enable + 11 + 11 + + + Disabled + The channel 11 is disabled + 0x1 + + + Enabled + The channel 11 is enabled + 0x0 + + + + + CH_12 + Link enable + 12 + 12 + + + Disabled + The channel 12 is disabled + 0x1 + + + Enabled + The channel 12 is enabled + 0x0 + + + + + CH_13 + Link enable + 13 + 13 + + + Disabled + The channel 13 is disabled + 0x1 + + + Enabled + The channel 13 is enabled + 0x0 + + + + + CH_14 + Link enable + 14 + 14 + + + Disabled + The channel 14 is disabled + 0x1 + + + Enabled + The channel 14 is enabled + 0x0 + + + + + CH_15 + Link enable + 15 + 15 + + + Disabled + The channel 15 is disabled + 0x1 + + + Enabled + The channel 15 is enabled + 0x0 + + + + + CH_16 + Link enable + 16 + 16 + + + Disabled + The channel 16 is disabled + 0x1 + + + Enabled + The channel 16 is enabled + 0x0 + + + + + CH_17 + Link enable + 17 + 17 + + + Disabled + The channel 17 is disabled + 0x1 + + + Enabled + The channel 17 is enabled + 0x0 + + + + + CH_18 + Link enable + 18 + 18 + + + Disabled + The channel 18 is disabled + 0x1 + + + Enabled + The channel 18 is enabled + 0x0 + + + + + CH_19 + Link enable + 19 + 19 + + + Disabled + The channel 19 is disabled + 0x1 + + + Enabled + The channel 19 is enabled + 0x0 + + + + + CH_20 + Link enable + 20 + 20 + + + Disabled + The channel 20 is disabled + 0x1 + + + Enabled + The channel 20 is enabled + 0x0 + + + + + CH_21 + Link enable + 21 + 21 + + + Disabled + The channel 21 is disabled + 0x1 + + + Enabled + The channel 21 is enabled + 0x0 + + + + + CH_22 + Link enable + 22 + 22 + + + Disabled + The channel 22 is disabled + 0x1 + + + Enabled + The channel 22 is enabled + 0x0 + + + + + CH_23 + Link enable + 23 + 23 + + + Disabled + The channel 23 is disabled + 0x1 + + + Enabled + The channel 23 is enabled + 0x0 + + + + + CH_24 + Link enable + 24 + 24 + + + Disabled + The channel 24 is disabled + 0x1 + + + Enabled + The channel 24 is enabled + 0x0 + + + + + CH_25 + Link enable + 25 + 25 + + + Disabled + The channel 25 is disabled + 0x1 + + + Enabled + The channel 25 is enabled + 0x0 + + + + + CH_26 + Link enable + 26 + 26 + + + Disabled + The channel 26 is disabled + 0x1 + + + Enabled + The channel 26 is enabled + 0x0 + + + + + CH_27 + Link enable + 27 + 27 + + + Disabled + The channel 27 is disabled + 0x1 + + + Enabled + The channel 27 is enabled + 0x0 + + + + + CH_28 + Link enable + 28 + 28 + + + Disabled + The channel 28 is disabled + 0x1 + + + Enabled + The channel 28 is enabled + 0x0 + + + + + CH_29 + Link enable + 29 + 29 + + + Disabled + The channel 29 is disabled + 0x1 + + + Enabled + The channel 29 is enabled + 0x0 + + + + + CH_30 + Link enable + 30 + 30 + + + Disabled + The channel 30 is disabled + 0x1 + + + Enabled + The channel 30 is enabled + 0x0 + + + + + CH_31 + Link enable + 31 + 31 + + + Disabled + The channel 31 is disabled + 0x1 + + + Enabled + The channel 31 is enabled + 0x0 + + + + + + + + + CHG + Unspecified + UICR_DPPI_GLOBAL_CHG + read-write + 0x014 + + OWN + Description cluster: Request ownership of the channel groups of DPPI[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + NotOwn + Do not own the channel group 0 + 0x1 + + + Own + Own the channel group 0 + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + NotOwn + Do not own the channel group 1 + 0x1 + + + Own + Own the channel group 1 + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + NotOwn + Do not own the channel group 2 + 0x1 + + + Own + Own the channel group 2 + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + NotOwn + Do not own the channel group 3 + 0x1 + + + Own + Own the channel group 3 + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + NotOwn + Do not own the channel group 4 + 0x1 + + + Own + Own the channel group 4 + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + NotOwn + Do not own the channel group 5 + 0x1 + + + Own + Own the channel group 5 + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + NotOwn + Do not own the channel group 6 + 0x1 + + + Own + Own the channel group 6 + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + NotOwn + Do not own the channel group 7 + 0x1 + + + Own + Own the channel group 7 + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + NotOwn + Do not own the channel group 8 + 0x1 + + + Own + Own the channel group 8 + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + NotOwn + Do not own the channel group 9 + 0x1 + + + Own + Own the channel group 9 + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + NotOwn + Do not own the channel group 10 + 0x1 + + + Own + Own the channel group 10 + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + NotOwn + Do not own the channel group 11 + 0x1 + + + Own + Own the channel group 11 + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + NotOwn + Do not own the channel group 12 + 0x1 + + + Own + Own the channel group 12 + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + NotOwn + Do not own the channel group 13 + 0x1 + + + Own + Own the channel group 13 + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + NotOwn + Do not own the channel group 14 + 0x1 + + + Own + Own the channel group 14 + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + NotOwn + Do not own the channel group 15 + 0x1 + + + Own + Own the channel group 15 + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + NotOwn + Do not own the channel group 16 + 0x1 + + + Own + Own the channel group 16 + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + NotOwn + Do not own the channel group 17 + 0x1 + + + Own + Own the channel group 17 + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + NotOwn + Do not own the channel group 18 + 0x1 + + + Own + Own the channel group 18 + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + NotOwn + Do not own the channel group 19 + 0x1 + + + Own + Own the channel group 19 + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + NotOwn + Do not own the channel group 20 + 0x1 + + + Own + Own the channel group 20 + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + NotOwn + Do not own the channel group 21 + 0x1 + + + Own + Own the channel group 21 + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + NotOwn + Do not own the channel group 22 + 0x1 + + + Own + Own the channel group 22 + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + NotOwn + Do not own the channel group 23 + 0x1 + + + Own + Own the channel group 23 + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + NotOwn + Do not own the channel group 24 + 0x1 + + + Own + Own the channel group 24 + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + NotOwn + Do not own the channel group 25 + 0x1 + + + Own + Own the channel group 25 + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + NotOwn + Do not own the channel group 26 + 0x1 + + + Own + Own the channel group 26 + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + NotOwn + Do not own the channel group 27 + 0x1 + + + Own + Own the channel group 27 + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + NotOwn + Do not own the channel group 28 + 0x1 + + + Own + Own the channel group 28 + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + NotOwn + Do not own the channel group 29 + 0x1 + + + Own + Own the channel group 29 + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + NotOwn + Do not own the channel group 30 + 0x1 + + + Own + Own the channel group 30 + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + NotOwn + Do not own the channel group 31 + 0x1 + + + Own + Own the channel group 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channel groups of DPPI[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + Secure + The channel group 0 is secure + 0x1 + + + NonSecure + The channel group 0 is non-secure + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + Secure + The channel group 1 is secure + 0x1 + + + NonSecure + The channel group 1 is non-secure + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + Secure + The channel group 2 is secure + 0x1 + + + NonSecure + The channel group 2 is non-secure + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + Secure + The channel group 3 is secure + 0x1 + + + NonSecure + The channel group 3 is non-secure + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + Secure + The channel group 4 is secure + 0x1 + + + NonSecure + The channel group 4 is non-secure + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + Secure + The channel group 5 is secure + 0x1 + + + NonSecure + The channel group 5 is non-secure + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + Secure + The channel group 6 is secure + 0x1 + + + NonSecure + The channel group 6 is non-secure + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + Secure + The channel group 7 is secure + 0x1 + + + NonSecure + The channel group 7 is non-secure + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + Secure + The channel group 8 is secure + 0x1 + + + NonSecure + The channel group 8 is non-secure + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + Secure + The channel group 9 is secure + 0x1 + + + NonSecure + The channel group 9 is non-secure + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + Secure + The channel group 10 is secure + 0x1 + + + NonSecure + The channel group 10 is non-secure + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + Secure + The channel group 11 is secure + 0x1 + + + NonSecure + The channel group 11 is non-secure + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + Secure + The channel group 12 is secure + 0x1 + + + NonSecure + The channel group 12 is non-secure + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + Secure + The channel group 13 is secure + 0x1 + + + NonSecure + The channel group 13 is non-secure + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + Secure + The channel group 14 is secure + 0x1 + + + NonSecure + The channel group 14 is non-secure + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + Secure + The channel group 15 is secure + 0x1 + + + NonSecure + The channel group 15 is non-secure + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + Secure + The channel group 16 is secure + 0x1 + + + NonSecure + The channel group 16 is non-secure + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + Secure + The channel group 17 is secure + 0x1 + + + NonSecure + The channel group 17 is non-secure + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + Secure + The channel group 18 is secure + 0x1 + + + NonSecure + The channel group 18 is non-secure + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + Secure + The channel group 19 is secure + 0x1 + + + NonSecure + The channel group 19 is non-secure + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + Secure + The channel group 20 is secure + 0x1 + + + NonSecure + The channel group 20 is non-secure + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + Secure + The channel group 21 is secure + 0x1 + + + NonSecure + The channel group 21 is non-secure + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + Secure + The channel group 22 is secure + 0x1 + + + NonSecure + The channel group 22 is non-secure + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + Secure + The channel group 23 is secure + 0x1 + + + NonSecure + The channel group 23 is non-secure + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + Secure + The channel group 24 is secure + 0x1 + + + NonSecure + The channel group 24 is non-secure + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + Secure + The channel group 25 is secure + 0x1 + + + NonSecure + The channel group 25 is non-secure + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + Secure + The channel group 26 is secure + 0x1 + + + NonSecure + The channel group 26 is non-secure + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + Secure + The channel group 27 is secure + 0x1 + + + NonSecure + The channel group 27 is non-secure + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + Secure + The channel group 28 is secure + 0x1 + + + NonSecure + The channel group 28 is non-secure + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + Secure + The channel group 29 is secure + 0x1 + + + NonSecure + The channel group 29 is non-secure + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + Secure + The channel group 30 is secure + 0x1 + + + NonSecure + The channel group 30 is non-secure + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + Secure + The channel group 31 is secure + 0x1 + + + NonSecure + The channel group 31 is non-secure + 0x0 + + + + + + + + + + GRTC + Unspecified + UICR_GRTC + read-write + 0x660 + + CC + Unspecified + UICR_GRTC_CC + read-write + 0x000 + + OWN + Request ownership of the CCs of GRTCGRTC + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CC_0 + Capture/compare register number + 0 + 0 + + + NotOwn + Do not own the CC register 0 + 0x1 + + + Own + Own the CC register 0 + 0x0 + + + + + CC_1 + Capture/compare register number + 1 + 1 + + + NotOwn + Do not own the CC register 1 + 0x1 + + + Own + Own the CC register 1 + 0x0 + + + + + CC_2 + Capture/compare register number + 2 + 2 + + + NotOwn + Do not own the CC register 2 + 0x1 + + + Own + Own the CC register 2 + 0x0 + + + + + CC_3 + Capture/compare register number + 3 + 3 + + + NotOwn + Do not own the CC register 3 + 0x1 + + + Own + Own the CC register 3 + 0x0 + + + + + CC_4 + Capture/compare register number + 4 + 4 + + + NotOwn + Do not own the CC register 4 + 0x1 + + + Own + Own the CC register 4 + 0x0 + + + + + CC_5 + Capture/compare register number + 5 + 5 + + + NotOwn + Do not own the CC register 5 + 0x1 + + + Own + Own the CC register 5 + 0x0 + + + + + CC_6 + Capture/compare register number + 6 + 6 + + + NotOwn + Do not own the CC register 6 + 0x1 + + + Own + Own the CC register 6 + 0x0 + + + + + CC_7 + Capture/compare register number + 7 + 7 + + + NotOwn + Do not own the CC register 7 + 0x1 + + + Own + Own the CC register 7 + 0x0 + + + + + CC_8 + Capture/compare register number + 8 + 8 + + + NotOwn + Do not own the CC register 8 + 0x1 + + + Own + Own the CC register 8 + 0x0 + + + + + CC_9 + Capture/compare register number + 9 + 9 + + + NotOwn + Do not own the CC register 9 + 0x1 + + + Own + Own the CC register 9 + 0x0 + + + + + CC_10 + Capture/compare register number + 10 + 10 + + + NotOwn + Do not own the CC register 10 + 0x1 + + + Own + Own the CC register 10 + 0x0 + + + + + CC_11 + Capture/compare register number + 11 + 11 + + + NotOwn + Do not own the CC register 11 + 0x1 + + + Own + Own the CC register 11 + 0x0 + + + + + CC_12 + Capture/compare register number + 12 + 12 + + + NotOwn + Do not own the CC register 12 + 0x1 + + + Own + Own the CC register 12 + 0x0 + + + + + CC_13 + Capture/compare register number + 13 + 13 + + + NotOwn + Do not own the CC register 13 + 0x1 + + + Own + Own the CC register 13 + 0x0 + + + + + CC_14 + Capture/compare register number + 14 + 14 + + + NotOwn + Do not own the CC register 14 + 0x1 + + + Own + Own the CC register 14 + 0x0 + + + + + CC_15 + Capture/compare register number + 15 + 15 + + + NotOwn + Do not own the CC register 15 + 0x1 + + + Own + Own the CC register 15 + 0x0 + + + + + + + SECURE + Request permission for the CCs of GRTC + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CC_0 + Capture/compare register number + 0 + 0 + + + Secure + The CC register 0 is secure + 0x1 + + + NonSecure + The CC register 0 is non-secure + 0x0 + + + + + CC_1 + Capture/compare register number + 1 + 1 + + + Secure + The CC register 1 is secure + 0x1 + + + NonSecure + The CC register 1 is non-secure + 0x0 + + + + + CC_2 + Capture/compare register number + 2 + 2 + + + Secure + The CC register 2 is secure + 0x1 + + + NonSecure + The CC register 2 is non-secure + 0x0 + + + + + CC_3 + Capture/compare register number + 3 + 3 + + + Secure + The CC register 3 is secure + 0x1 + + + NonSecure + The CC register 3 is non-secure + 0x0 + + + + + CC_4 + Capture/compare register number + 4 + 4 + + + Secure + The CC register 4 is secure + 0x1 + + + NonSecure + The CC register 4 is non-secure + 0x0 + + + + + CC_5 + Capture/compare register number + 5 + 5 + + + Secure + The CC register 5 is secure + 0x1 + + + NonSecure + The CC register 5 is non-secure + 0x0 + + + + + CC_6 + Capture/compare register number + 6 + 6 + + + Secure + The CC register 6 is secure + 0x1 + + + NonSecure + The CC register 6 is non-secure + 0x0 + + + + + CC_7 + Capture/compare register number + 7 + 7 + + + Secure + The CC register 7 is secure + 0x1 + + + NonSecure + The CC register 7 is non-secure + 0x0 + + + + + CC_8 + Capture/compare register number + 8 + 8 + + + Secure + The CC register 8 is secure + 0x1 + + + NonSecure + The CC register 8 is non-secure + 0x0 + + + + + CC_9 + Capture/compare register number + 9 + 9 + + + Secure + The CC register 9 is secure + 0x1 + + + NonSecure + The CC register 9 is non-secure + 0x0 + + + + + CC_10 + Capture/compare register number + 10 + 10 + + + Secure + The CC register 10 is secure + 0x1 + + + NonSecure + The CC register 10 is non-secure + 0x0 + + + + + CC_11 + Capture/compare register number + 11 + 11 + + + Secure + The CC register 11 is secure + 0x1 + + + NonSecure + The CC register 11 is non-secure + 0x0 + + + + + CC_12 + Capture/compare register number + 12 + 12 + + + Secure + The CC register 12 is secure + 0x1 + + + NonSecure + The CC register 12 is non-secure + 0x0 + + + + + CC_13 + Capture/compare register number + 13 + 13 + + + Secure + The CC register 13 is secure + 0x1 + + + NonSecure + The CC register 13 is non-secure + 0x0 + + + + + CC_14 + Capture/compare register number + 14 + 14 + + + Secure + The CC register 14 is secure + 0x1 + + + NonSecure + The CC register 14 is non-secure + 0x0 + + + + + CC_15 + Capture/compare register number + 15 + 15 + + + Secure + The CC register 15 is secure + 0x1 + + + NonSecure + The CC register 15 is non-secure + 0x0 + + + + + + + + + 0x10 + 0x4 + IPCMAP[%s] + Description collection: Request configuration for the channel n of IPCMAP + 0x680 + read-write + 0xFFFFFFFF + 0x20 + + + IPCTCHSINK + IPCT channel number (sink side) + 0 + 7 + + + DOMAINIDSINK + Domain ID (sink side) + 8 + 11 + + + IPCTCHSOURCE + IPCT channel number (source side) + 16 + 23 + + + DOMAINIDSOURCE + Domain ID (source side) + 24 + 27 + + + + + 8 + 0x008 + MAILBOX[%s] + Unspecified + UICR_MAILBOX + read-write + 0x700 + + ADDRESS + Description cluster: Memory start address of mailbox n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Memory address + 0 + 31 + + + + + CONFIG + Description cluster: Configuration of mailbox n + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + SECURE + Permission + 3 + 3 + + + Secure + The mailbox memory is secure + 0x1 + + + NonSecure + The mailbox memory is non-secure + 0x0 + + + + + OWNERID + Remote owner identification + 8 + 11 + + + SIZE + Memory size + 16 + 31 + + + + + + TRACE + Unspecified + UICR_TRACE + read-write + 0x740 + + ETBSINK + Unspecified + UICR_TRACE_ETBSINK + read-write + 0x000 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + TPIUSINK + Unspecified + UICR_TRACE_TPIUSINK + read-write + 0x004 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + ETRSINK + Unspecified + UICR_TRACE_ETRSINK + read-write + 0x008 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + PORTCONFIG + Trace port speed configuration + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PORTCONFIG + 0 + 1 + + + FullSpeed + Full speed + 0x3 + + + HalfSpeed + Half speed + 0x2 + + + QuarterSpeed + One quarter speed + 0x1 + + + EightSpeed + One eigth speed + 0x0 + + + + + + + + TAMPER + Unspecified + UICR_TAMPER + read-write + 0x760 + + DETECTION + Tamper policy configuration for detected security events. + UICR_TAMPER_DETECTION + read-write + 0x000 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + GlobalEnable + Enable tamper detection. When disabled all tamper enable and policy switches are ignored. + 0 + 0 + + + Enable + Enable tamper detection. + 0x0 + + + Disable + Disable tamper detection. + 0x1 + + + + + VoltageLevel + Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when voltage on the corresponding supply line is too low. + 1 + 1 + + + Enable + Enable voltage level detectors. + 0x0 + + + Disable + Disable voltage level detectors. + 0x1 + + + + + ExternalActiveShield + Enable external active shield detector. + 4 + 4 + + + Enable + Enable external active shield detector. + 0x0 + + + Disable + Disable external active shield detector. + 0x1 + + + + + HardFault + Configure if tamper prevention should react on hard faults. + 7 + 7 + + + Enable + Enable hard fault detector. + 0x0 + + + Disable + Disable hard fault detector. + 0x1 + + + + + ApiFault + Configure if tamper prevention should react on invalid API usage. + 8 + 8 + + + Enable + Enable API fault detector. + 0x0 + + + Disable + Disable API fault detector. + 0x1 + + + + + AdacFault + Configure if tamper prevention should react on invalid ADAC usage. + 9 + 9 + + + Enable + Enable invalid ADAC usage detector. + 0x0 + + + Disable + Disable invalid ADAC usage detector. + 0x1 + + + + + StateFault + Configure if tamper prevention should react on invalid firmware execution state. + 10 + 10 + + + Enable + Enable invalid firmware execution state detector. + 0x0 + + + Disable + Disable invalid firmware execution state detector. + 0x1 + + + + + TemperatureFault + Configure if tamper prevention should react when on-die temperature exceeds a valid range. + 11 + 11 + + + Enable + Enable invalid out-of-range temperature detector. + 0x0 + + + Disable + Disable invalid out-of-range temperature detector. + 0x1 + + + + + + + RESPONSE0 + Unspecified + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + VoltageLevel + Configure tamper policy for invalid voltage level on supply lines. + 0 + 3 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + Watchdog + Configure tamper policy for watchdog timer. + 4 + 7 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ExternalActiveShield + Configure tamper policy for external active shield. BICR is used to specify which channels (GPIOs) are enabled. + 12 + 15 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + InternalDetectors + Configure tamper policy for internal detectors including glitch detector, signal protector and CRACEN detector. See for more information. An automatic reset is issued upon detection. + 20 + 23 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + HardFault + Configure tamper policy for hard fault. + 24 + 27 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ApiFault + Configure tamper policy for invalid API usage. + 28 + 31 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + RESPONSE1 + Unspecified + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + AdacFault + Configure tamper policy for invalid ADAC usage. + 0 + 3 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + StateFault + Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure domain before secure services are permitted again. + 4 + 7 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + TemperatureFault + Configure out-of-range on-die temperature tamper policy. A reset is required to continue providing secure services once the on-temperature is within valid operating conditions again. This reset is automatically triggered by the secure domain. + 8 + 11 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + TEMPDETECTORCONFIG + Unspecified + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TemperatureDetectionStrategy + Configure when on-die temperature sensor should check the temperature. + 0 + 1 + + + Periodically + On-die temperature sensor is read periodically with selected interval. + 0x1 + + + OnServiceCallAndPeriodically + On-die temperature sensor is read before each secure service call and periodically with selected interval. + 0x2 + + + OnServiceCallOnly + On-die temperature sensor is read before each secure service call. + 0x3 + + + + + TemperatureDetectionInterval + Configure interval for on-die temperature reading if periodic reading is enabled. + 2 + 3 + + + 1Minute + On-die temperature sensor is read with one minute intervals. + 0x0 + + + 15Minutes + On-die temperature sensor is read with 15 minutes intervals. + 0x2 + + + 1Hour + On-die temperature sensor is read with one hour intervals. + 0x3 + + + + + LowTemperatureThresholdShift + Low temperature detection threshold shift in degrees Celsius. The low temperature threshold is calculated by adding the threshold shift to the minimum operating temperature of the SoC. + 4 + 11 + + + HighTemperatureThresholdShift + High temperature detection threshold shift in degrees Celsius. The high temperature threshold is calculated by subtracting the threshold shift from the maximum operating temperature of the SoC. + 12 + 19 + + + + + + COUNTERMEASURES + Configuration of countermeasures. + UICR_TAMPER_COUNTERMEASURES + read-write + 0x010 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + DPAAES + Configure Differential Power Analysis countermeasure for CRACEN AES. + 0 + 0 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + DPAPK + Configure Differential Power Analysis countermeasure for CRACEN PK. + 1 + 1 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + ClockDithering + Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on TRNG. + 9 + 9 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + + + + + INITSVTOR + Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. + 0x780 + read-write + 0xFFFFFFFF + 0x20 + + + INITSVTOR + Initial value of the VTOR. + 0 + 31 + + + + + INITNSVTOR + Initial value of the non-secure VTOR (Vector Table Offset Register). + 0x784 + read-write + 0xFFFFFFFF + 0x20 + + + INITNSVTOR + Initial value of the VTOR. + 0 + 31 + + + + + PTREXTUICR + Pointer to extended UICR. + 0x7FC + read-write + 0xFFFFFFFF + 0x20 + + + PTREXTUICR + Pointer to extended UICR. + 0 + 31 + + + + + + + BICR_NS + Board information configuration registers + 0x0FFF8800 + BICR + + + + 0 + 0x80 + registers + + BICR + 0x20 + + + IOPORT + Unspecified + BICR_IOPORT + read-write + 0x004 + + POWER0 + Power configuration for P0 to P7 IO ports. Note: P0 is not included in the fields of this register because it is always internally supplied and therefore considered 'Shorted'. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + P1 + P1 power configuration. + 4 + 7 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P2 + P2 power configuration. + 8 + 11 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P6 + P6 power configuration. + 24 + 27 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + + + POWER1 + Power configuration for P8 to P15 IO ports. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + P8 + P8 power configuration. + 0 + 3 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P9 + P9 power configuration. + 4 + 7 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + External3V + Port supply is provided externally at 3 V. + 0x3 + + + ExternalFull + Port supply is provided externally with a full range of values, from 3 V to 1.8 V. + 0x4 + + + + + P10 + P10 power configuration. + 8 + 11 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P11 + P11 power configuration. + 12 + 15 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P12 + P12 power configuration. + 16 + 19 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + P13 + P13 power configuration. + 20 + 23 + + + Unconfigured + Port supply is unconfigured. + 0xF + + + Disconnected + Port supply rail is not connected. Port cannot be used. + 0x0 + + + Shorted + Port supply is shorted to VDD_AO_1V8. + 0x1 + + + External1V8 + Port supply is provided externally at 1.8 V. + 0x2 + + + + + + + DRIVECTRL0 + Drive control configuration for P0 to P7 IO ports. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + P6 + P6 drive control configuration. + 24 + 27 + + + Unconfigured + Port supply is unconfigured. PORTCNF.DRIVECTRL will not be adjusted. + 0xF + + + Ohms33 + PORTCNF.DRIVECTRL will be adjusted for 33 Ohms. + 0x0 + + + Ohms40 + PORTCNF.DRIVECTRL will be adjusted for 40 Ohms. + 0x1 + + + Ohms50 + PORTCNF.DRIVECTRL will be adjusted for 50 Ohms. + 0x2 + + + Ohms66 + PORTCNF.DRIVECTRL will be adjusted for 66 Ohms. + 0x3 + + + Ohms100 + PORTCNF.DRIVECTRL will be adjusted for 100 Ohms. + 0x4 + + + + + + + DRIVECTRL1 + Drive control configuration for P8 to P15 IO ports. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + P8 + P8 drive control configuration. + 0 + 3 + + + Unconfigured + Port supply is unconfigured. PORTCNF.DRIVECTRL will not be adjusted. + 0xF + + + Ohms33 + PORTCNF.DRIVECTRL will be adjusted for 33 Ohms. + 0x0 + + + Ohms40 + PORTCNF.DRIVECTRL will be adjusted for 40 Ohms. + 0x1 + + + Ohms50 + PORTCNF.DRIVECTRL will be adjusted for 50 Ohms. + 0x2 + + + Ohms66 + PORTCNF.DRIVECTRL will be adjusted for 66 Ohms. + 0x3 + + + Ohms100 + PORTCNF.DRIVECTRL will be adjusted for 100 Ohms. + 0x4 + + + + + + + + LFOSC + Unspecified + BICR_LFOSC + read-write + 0x018 + + LFXOCONFIG + LFXO configuration. Note. This configuration might be overridden by FICR configuration. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ACCURACY + LFXO crystal or external signal accuracy. + 0 + 3 + + + Unconfigured + The accuracy is unconfigured. + 0xF + + + 500ppm + LFXO crystal or external signal has an accuracy of 500 ppm. + 0x0 + + + 250ppm + LFXO crystal or external signal has an accuracy of 250 ppm. + 0x1 + + + 150ppm + LFXO crystal or external signal has an accuracy of 150 ppm. + 0x2 + + + 100ppm + LFXO crystal or external signal has an accuracy of 100 ppm. + 0x3 + + + 75ppm + LFXO crystal or external signal has an accuracy of 75 ppm. + 0x4 + + + 50ppm + LFXO crystal or external signal has an accuracy of 50 ppm. + 0x5 + + + 30ppm + LFXO crystal or external signal has an accuracy of 30 ppm. + 0x6 + + + 20ppm + LFXO crystal or external signal has an accuracy of 20 ppm. + 0x7 + + + + + MODE + LFXO mode. LFXO will not start unless MODE is configured. Setting this field to anyting but Unconfigured will be used as the indication that the selected source is available as input to the LFXO. + 4 + 6 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Crystal + LFXO in external crystal oscillator mode. + 0x0 + + + ExtSine + LFXO in external sine wave mode. + 0x2 + + + ExtSquare + LFXO in external square wave mode. + 0x3 + + + Disabled + LFXO is not to be used. + 0x6 + + + + + LOADCAP + Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. + 8 + 15 + + + Unconfigured + The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is configured. + 0xFF + + + External + Do not use the built-in load capacitors, only external capacitors will be used. + 0x00 + + + + + TIME + LFXO startup time in ms. + 16 + 27 + + + Unconfigured + Startup time has not been configured. + 0xFFF + + + + + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0 + 31 + + + Calibrate + Calibrate the LFXO at startup. + 0xFFFFFFFF + + + + + + + LFRCAUTOCALCONFIG + LFRC autocalibration configuration. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + TEMPINTERVAL + Temperature measurement interval in 0.25 s steps. + 0 + 6 + + + TEMPDELTA + Temperature delta that should trigger a calibration in 0.25 degrees steps. + 8 + 13 + + + INTERVALMAXNO + Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature changes. + 16 + 20 + + + ENABLE + LFRC.AUTOCALCONFIG register enable. + 31 + 31 + + + Enabled + LFRC.AUTOCALCONFIG register has been configured and can be used. + 0x0 + + + Disabled + LFRC.AUTOCALCONFIG register has not been configured and cannot be used. + 0x1 + + + + + + + + HFXO64M + Unspecified + BICR_HFXO64M + read-write + 0x02C + + CONFIG + HFXO64M configuration. Note. This configuration might be overridden by FICR configuration. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MODE + HFXO64M mode. + 0 + 2 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Normal + Normal operating mode. + 0x0 + + + TCXO + TCXO/bypass mode + 0x1 + + + Crystal2 + Reserved value + 0x2 + + + Crystal3 + Reserved value + 0x3 + + + Crystal4 + Reserved value + 0x4 + + + Crystal5 + Reserved value + 0x5 + + + Crystal6 + Reserved value + 0x6 + + + + + + + STARTUPTIME + HFXO64M startup time in us. Note. This configuration might be overridden by FICR configuration. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + TIME + HFXO64M startup time in us. + 0 + 31 + + + Unconfigured + Startup time has not been configured. + 0xFFFFFFFF + + + + + + + + TAMPC + Unspecified + BICR_TAMPC + read-write + 0x034 + + TAMPERSWITCH + Configuration for external tamper switch detector. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + TAMPERSWITCH + Tamper switch enable. + 0 + 3 + + + Disabled + Tamper switch is disabled. + 0xF + + + Enabled + Tamper switch is enabled. + 0x0 + + + + + + + ACTIVESHIELD + Configuration for active shield channels. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CHEN_0 + Active shield enable for channel 0. + 0 + 3 + + + Disabled + Active shield channel 0 is disabled. + 0xF + + + Enabled + Active shield channel 0 is enabled. + 0x0 + + + + + CHEN_1 + Active shield enable for channel 1. + 4 + 7 + + + Disabled + Active shield channel 1 is disabled. + 0xF + + + Enabled + Active shield channel 1 is enabled. + 0x0 + + + + + CHEN_2 + Active shield enable for channel 2. + 8 + 11 + + + Disabled + Active shield channel 2 is disabled. + 0xF + + + Enabled + Active shield channel 2 is enabled. + 0x0 + + + + + CHEN_3 + Active shield enable for channel 3. + 12 + 15 + + + Disabled + Active shield channel 3 is disabled. + 0xF + + + Enabled + Active shield channel 3 is enabled. + 0x0 + + + + + + + + PMIC + Unspecified + BICR_PMIC + read-write + 0xC8 + + LDOIO1V8 + Configuration for PMIC LDO_IO1V8. + 0x00 + read-write + 0xFFFFFFFF + 0x20 + + + LEVEL + PMIC LDO_IO1V8 output voltage in 100mV steps. All values above 0x0F are invalid. + 0 + 4 + + + 1v8 + PMIC LDO_IO1V8 output voltage configured for 1v8 operation. + 0x00 + + + 2v6 + PMIC LDO_IO1V8 output voltage configured for 2v6 operation. + 0x08 + + + 3v3 + PMIC LDO_IO1V8 output voltage configured for 3v3 operation. + 0x0F + + + Unconfigured + PMIC LDO_IO1V8 output voltage is unconfigured. + 0x1F + + + + + ONMODE + PMIC LDO_IO1V8 operation mode during system ON. + 5 + 6 + + + Normal + PMIC LDO_IO1V8 is configured for normal operation during system ON. + 0x0 + + + ULP + PMIC LDO_IO1V8 is configured for ULP operation during system ON. + 0x1 + + + Off + PMIC LDO_IO1V8 is not used. + 0x2 + + + Unconfigured + PMIC LDO_IO1V8 mode during system ON is unconfigured. + 0x3 + + + + + IDLEMODE + PMIC LDO_IO1V8 operation mode during system ON IDLE. + 7 + 8 + + + Normal + PMIC LDO_IO1V8 is configured for normal operation during system ON IDLE. + 0x0 + + + ULP + PMIC LDO_IO1V8 is configured for ULP operation during system ON IDLE. + 0x1 + + + Off + PMIC LDO_IO1V8 is forced off during system ON IDLE. + 0x2 + + + Unconfigured + PMIC LDO_IO1V8 mode during system ON IDLE is unconfigured. + 0x3 + + + + + OFFMODE + PMIC LDO_IO1V8 operation mode during system OFF. + 9 + 10 + + + Normal + PMIC LDO_IO1V8 is configured for normal operation during system OFF. + 0x0 + + + ULP + PMIC LDO_IO1V8 is configured for ULP operation during system OFF. + 0x1 + + + Off + PMIC LDO_IO1V8 is forced off during system OFF. + 0x2 + + + Unconfigured + PMIC LDO_IO1V8 mode for system OFF is unconfigured. + 0x3 + + + + + + + LDOIO3V3 + Configuration for PMIC LDO_IO3V3. + 0x04 + read-write + 0xFFFFFFFF + 0x20 + + + LEVEL + PMIC LDO_IO3V3 output voltage in 100mV steps. All values above 0x0F are invalid. + 0 + 4 + + + 1v8 + PMIC LDO_IO3V3 output voltage configured for 1v8 operation. + 0x00 + + + 2v6 + PMIC LDO_IO3V3 output voltage configured for 2v6 operation. + 0x08 + + + 3v3 + PMIC LDO_IO3V3 output voltage configured for 3v3 operation. + 0x0F + + + Unconfigured + PMIC LDO_IO3V3 output voltage is unconfigured. + 0x1F + + + + + ONMODE + PMIC LDO_IO3V3 operation mode during system ON. + 5 + 6 + + + Normal + PMIC LDO_IO3V3 is configured for normal operation during system ON. + 0x0 + + + ULP + PMIC LDO_IO3V3 is configured for ULP operation during system ON + 0x1 + + + Off + PMIC LDO_IO3V3 is not used. + 0x2 + + + Unconfigured + PMIC LDO_IO3V3 mode during system ON is unconfigured. + 0x3 + + + + + IDLEMODE + PMIC LDO_IO3V3 operation mode during system ON IDLE. + 7 + 8 + + + Normal + PMIC LDO_IO3V3 is configured for normal operation during system ON IDLE. + 0x0 + + + ULP + PMIC LDO_IO3V3 is configured for ULP operation during system ON IDLE. + 0x1 + + + Off + PMIC LDO_IO3V3 is forced off during system ON IDLE. + 0x2 + + + Unconfigured + PMIC LDO_IO3V3 mode during system ON IDLE is unconfigured. + 0x3 + + + + + OFFMODE + PMIC LDO_IO3V3 operation mode during system OFF. + 9 + 10 + + + Normal + PMIC LDO_IO3V3 is configured for normal operation during system OFF. + 0x0 + + + ULP + PMIC LDO_IO3V3 is configured for ULP operation during system OFF + 0x1 + + + Off + PMIC LDO_IO3V3 is forced off during system OFF. + 0x2 + + + Unconfigured + PMIC LDO_IO3V3 mode for system OFF is unconfigured. + 0x3 + + + + + + + + + + GLOBAL_FICR_NS + Factory Information Configuration Registers + 0x0FFFE000 + FICR + + + + 0 + 0xC00 + registers + + FICR + 0x20 + + + BLE + Unspecified + FICR_BLE + read-write + 0x00C + + ADDRTYPE + Device address type. + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + TYPE + Device address type. + 0 + 0 + + + Public + Public address. + 0x0 + + + Random + Random address. + 0x1 + + + + + + + 0x2 + 0x4 + ADDR[%s] + Description collection: 48 bit device address. + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + ADDR + Device address [n]. + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root. + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + ER + Encryption root word [n]. + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root. + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + IR + Identity root word [n]. + 0 + 31 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x050 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + HWID + Identification number for the HW + 0 + 15 + + + + + PART + Part code + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + PART + Part code + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x008 + read-only + 0xFFFFFFFF + 0x20 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + PACKAGE + Package option + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x010 + read-only + 0xFFFFFFFF + 0x20 + + + RAM + RAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + MRAM + MRAM variant + 0x014 + read-only + 0xFFFFFFFF + 0x20 + + + MRAM + MRAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x018 + read-only + 0x00001000 + 0x20 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODESIZE + Code memory size + 0x01C + read-only + 0x00000100 + 0x20 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + DEVICETYPE + Device type + 0x020 + read-only + 0x00000000 + 0x20 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x00000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x080 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + PARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0xFF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0xFF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + PMICVERSION + PMIC version + 0x00C + read-only + 0x00000000 + 0x20 + + + PMICVERSION + PMIC version, incremental code + 0 + 31 + + + + + 0x4 + 0x1 + TESTSITE[%s] + Description collection: Test site, in ascii + 0x010 + read-only + 0x00 + uint8_t + 0x8 + + + LOT + Lot number + test index in hex format (number digits 0-9). + 0x014 + read-only + 0x00000000 + 0x20 + + + LOTID + Lot number in hex format + 0 + 23 + + + TESTID + Test ID in hex format + 24 + 31 + + + + + 0x4 + 0x1 + TESTPROGRAMID[%s] + Description collection: Test program id, in ascii + 0x018 + read-only + 0x00 + uint8_t + 0x8 + + + OSATPARTNO + OSAT part number + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + OSATPARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWBUILDVERSION[%s] + Description collection: OSAT production build version + 0x020 + read-only + 0xFF + uint8_t + 0x8 + + + OVERRIDE + Unspecified + FICR_SIPINFO_OVERRIDE + read-write + 0x024 + + LFOSC + Unspecified + FICR_SIPINFO_OVERRIDE_LFOSC + read-write + 0x000 + + CONFIG + LF oscillator configuration. Note. This configuration overrides corresponding LF oscillator configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SRC + LF oscillator source. + 0 + 3 + + + Unconfigured + LF oscillator source is unconfigured. Default will be used. + 0xF + + + LFXO + Use LFXO as source for the LF oscillator. + 0x0 + + + LFRC + Use LFRC as source for the LF oscillator. + 0x1 + + + LFLPRC + Use LFLPRC as source for the LF oscillator. + 0x2 + + + Synth + Use LF Synth as source for the LF oscillator. + 0x3 + + + + + + + LFXOCONFIG + LFXO configuration. Note. This configuration overrides corresponding LFXO configuration in BICR when set. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + ACCURACY + LFXO crystal or external signal accuracy. + 0 + 3 + + + Unconfigured + The accuracy is unconfigured. + 0xF + + + 500ppm + LFXO crystal or external signal has an accuracy of 500 ppm. + 0x0 + + + 250ppm + LFXO crystal or external signal has an accuracy of 250 ppm. + 0x1 + + + 150ppm + LFXO crystal or external signal has an accuracy of 150 ppm. + 0x2 + + + 100ppm + LFXO crystal or external signal has an accuracy of 100 ppm. + 0x3 + + + 75ppm + LFXO crystal or external signal has an accuracy of 75 ppm. + 0x4 + + + 50ppm + LFXO crystal or external signal has an accuracy of 50 ppm. + 0x5 + + + 30ppm + LFXO crystal or external signal has an accuracy of 30 ppm. + 0x6 + + + 20ppm + LFXO crystal or external signal has an accuracy of 20 ppm. + 0x7 + + + + + MODE + LFXO mode. LFXO will not start unless MODE is configured. + 4 + 6 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Pierce + LFXO Pierce mode. + 0x0 + + + PIXO + LFXO PIXO mode. + 0x1 + + + ExtSine + LFXO in external sine wave mode. + 0x2 + + + ExtSquare + LFXO in external square wave mode. + 0x3 + + + + + LOADCAP + Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. + 8 + 15 + + + Unconfigured + The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is configured. + 0xFF + + + External + Do not use the built-in load capacitors, only external capacitors will be used. + 0x00 + + + + + TIME + LFXO startup time in ms. + 16 + 27 + + + Unconfigured + Startup time has not been configured. + 0xFFF + + + + + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. Note. This configuration overrides corresponding LFXO calibration in BICR when set. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0 + 31 + + + Calibrate + Calibrate the LFXO at startup. + 0xFFFFFFFF + + + + + + + LFRCAUTOCALCONFIG + LFRC autocalibration configuration. Note. This configuration overrides corresponding LFRC autocalibration configuration in BICR when set. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TEMPINTERVAL + Temperature measurement interval in 0.25 s steps. + 0 + 6 + + + TEMPDELTA + Temperature delta that should trigger a calibration in 0.25 degrees steps. + 8 + 13 + + + INTERVALMAXNO + Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature changes. + 16 + 20 + + + ENABLE + LFRC.AUTOCALCONFIG register enable. + 31 + 31 + + + Enabled + LFRC.AUTOCALCONFIG register has been configured and can be used. + 0x0 + + + Disabled + LFRC.AUTOCALCONFIG register has not been configured and cannot be used. + 0x1 + + + + + + + + HFXO64M + Unspecified + FICR_SIPINFO_OVERRIDE_HFXO64M + read-write + 0x010 + + CONFIG + HFXO64M configuration. Note. This configuration overrides corresponding XO configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MODE + HFXO64M mode. + 0 + 2 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Normal + Normal operating mode. + 0x0 + + + TCXO + TCXO/bypass mode + 0x1 + + + Crystal2 + Reserved value + 0x2 + + + Crystal3 + Reserved value + 0x3 + + + Crystal4 + Reserved value + 0x4 + + + Crystal5 + Reserved value + 0x5 + + + Crystal6 + Reserved value + 0x6 + + + + + + + + + + TRIM + Unspecified + FICR_TRIM + read-write + 0x100 + + GLOBAL + Unspecified + FICR_TRIM_GLOBAL + read-write + 0x244 + + SAADC + Unspecified + FICR_TRIM_GLOBAL_SAADC + read-write + 0x0 + + CALVREF + Trim value for GLOBAL.SAADC.CALVREF + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x3 + 0x4 + CALGAIN[%s] + Description collection: Trim value for GLOBAL.SAADC.CALGAIN + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALOFFSET + Trim value for GLOBAL.SAADC.CALOFFSET + 0x10 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF + 0x14 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALIREF + Trim value for GLOBAL.SAADC.CALIREF + 0x2C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALVREFTC + Trim value for GLOBAL.SAADC.CALVREFTC + 0x30 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + CANPLL + Unspecified + FICR_TRIM_GLOBAL_CANPLL + read-write + 0x3C + + TRIM + Unspecified + FICR_TRIM_GLOBAL_CANPLL_TRIM + read-write + 0x0 + + CTUNE + Trim value for GLOBAL.CANPLL.TRIM.CTUNE + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + COMP + Unspecified + FICR_TRIM_GLOBAL_COMP + read-write + 0x4C + + REFTRIM + Trim value for GLOBAL.COMP.REFTRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + APPLICATION + Unspecified + FICR_TRIM_APPLICATION + read-write + 0x298 + + HSFLL + Unspecified + FICR_TRIM_APPLICATION_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_APPLICATION_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for APPLICATION.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_APPLICATION_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + RADIOCORE + Unspecified + FICR_TRIM_RADIOCORE + read-write + 0x2DC + + HSFLL + Unspecified + FICR_TRIM_RADIOCORE_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_RADIOCORE_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for RADIOCORE.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + + + + DCACHEDATA_S + CACHEDATA + 0x22F00000 + DCACHEDATA + + + + 0 + 0x1000 + registers + + DCACHEDATA + 0x20 + + + 256 + 0x040 + SET[%s] + Unspecified + DCACHEDATA_SET + read-write + 0x0 + + 2 + 0x020 + WAY[%s] + Unspecified + DCACHEDATA_SET_WAY + read-write + 0x0 + + 8 + 0x004 + DU[%s] + Unspecified + DCACHEDATA_SET_WAY_DU + read-write + 0x0 + + 0x1 + 0x4 + DATA[%s] + Description collection: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + Data + Data + 0 + 31 + read-only + + + + + + + + + + DCACHEINFO_S + CACHEINFO + 0x22F10000 + DCACHEINFO + + + + 0 + 0x1000 + registers + + DCACHEINFO + 0x20 + + + 256 + 0x010 + SET[%s] + Unspecified + DCACHEINFO_SET + read-write + 0x0 + + 2 + 0x008 + WAY[%s] + Unspecified + DCACHEINFO_SET_WAY + read-write + 0x0 + + INFO + Description cluster: Cache information for SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + TAG + Cache tag. + 0 + 19 + read-only + + + DUV_0 + Data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_1 + Data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_2 + Data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_3 + Data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + D0 + Dirty status of combined data unit 0 and 1. + 28 + 28 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D1 + Dirty status of combined data unit 2 and 3. + 29 + 29 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + V + Line valid bit. + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0x0 + + + Valid + Valid cache line + 0x1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0x0 + + + Way1 + Way1 was most recently used + 0x1 + + + + + + + INFOEXT + Description cluster: Extended cache information for SET[n], WAY[o]. + 0x4 + read-write + 0x00000000 + 0x20 + + + D_0 + Dirty status. + 16 + 16 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_1 + Dirty status. + 17 + 17 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_2 + Dirty status. + 18 + 18 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_3 + Dirty status. + 19 + 19 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_4 + Dirty status. + 20 + 20 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_5 + Dirty status. + 21 + 21 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_6 + Dirty status. + 22 + 22 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_7 + Dirty status. + 23 + 23 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + DUVEXT_0 + Extended data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_1 + Extended data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_2 + Extended data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_3 + Extended data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + + + + + + + GLOBAL_USBHSCORE0_NS + USBHSCORE 0 + 0x2F700000 + USBHSCORE + + + + 0 + 0x24000 + registers + + USBHSCORE + 0x20 + + + GOTGCTL + Control and Status Register + 0x000 + read-write + 0x000D0000 + 0x20 + + + VBVALIDOVEN + Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) + 2 + 2 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller + 0x0 + + + ENABLED + The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal + 0x1 + + + + + VBVALIDOVVAL + Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) + 3 + 3 + + + SET0 + vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + 0x0 + + + SET1 + vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + 0x1 + + + + + AVALIDOVEN + Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) + 4 + 4 + + + DISABLED + Derive AValid from PHY + 0x0 + + + ENABLED + Derive Avalid from GOTGCTL.AvalidOvVal + 0x1 + + + + + AVALIDOVVAL + Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) + 5 + 5 + + + VALUE0 + Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + 0x0 + + + VALUE1 + Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + 0x1 + + + + + BVALIDOVEN + Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) + 6 + 6 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + ENABLED + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal + 0x1 + + + + + BVALIDOVVAL + Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) + 7 + 7 + + + VALUE0 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x0 + + + VALUE1 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x1 + + + + + DBNCEFLTRBYPASS + Mode: Host and Device. Debounce Filter Bypass + 15 + 15 + + + DISABLED + Debounce Filter Bypass is disabled. + 0x0 + + + ENABLED + Debounce Filter Bypass is enabled. + 0x1 + + + + + CONIDSTS + Mode: Host and Device. Connector ID Status (ConIDSts) + 16 + 16 + read-only + + + MODEA + The core is in A-Device mode. + 0x0 + + + MODEB + The core is in B-Device mode. + 0x1 + + + + + DBNCTIME + Mode: Host only. Long/Short Debounce Time (DbncTime) + 17 + 17 + read-only + + + LONG + Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + 0x0 + + + SHORT + Short debounce time, used for soft connections (2.5 micro-sec) + 0x1 + + + + + ASESVLD + Mode: Host only. A-Session Valid (ASesVld) + 18 + 18 + read-only + + + NOTVALID + A-session is not valid. + 0x0 + + + VALID + A-session is valid. + 0x1 + + + + + BSESVLD + Mode: Device only. B-Session Valid (BSesVld) + 19 + 19 + read-only + + + NOTVALID + B-session is not valid. + 0x0 + + + VALID + B-session is valid. + 0x1 + + + + + OTGVER + OTG Version (OTGVer) + 20 + 20 + + + VER13 + Supports OTG Version 1.3 + 0x0 + + + VER20 + Supports OTG Version 2.0 + 0x1 + + + + + CURMOD + Current Mode of Operation (CurMod) + 21 + 21 + read-only + + + DEVICEMODE + Current mode is device mode. + 0x0 + + + HOSTMODE + Current mode is host mode. + 0x1 + + + + + MULTVALIDBC + Mode: Host and Device. Multi Valued ID pin (MultValIdBC) + 22 + 26 + read-only + + + RID_C + B-Device connected to ACA. VBUS is on. + 0x01 + + + RID_B + B-Device connected to ACA. VBUS is off. + 0x02 + + + RID_A + A-Device connected to ACA + 0x04 + + + RID_GND + A-Device not connected to ACA + 0x08 + + + RID_FLOAT + B-Device not connected to ACA + 0x10 + + + + + CHIRPEN + Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used + 27 + 27 + + + CHIRP_DISABLE + The controller does not assert chirp_on before sending an actual Chirp 'K' signal on USB. + 0x0 + + + CHIRP_ENABLE + The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB. + 0x1 + + + + + + + GOTGINT + Interrupt Register + 0x004 + read-write + 0x00000000 + 0x20 + + + SESENDDET + Mode: Host and Device. Session End Detected (SesEndDet) + 2 + 2 + + + INACTIVE + Session is Active + 0x0 + + + ACTIVE + SessionEnd utmiotg_bvalid signal is deasserted + 0x1 + + + + + SESREQSUCSTSCHNG + Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) + 8 + 8 + + + INACTIVE + No Change in Session Request Status + 0x0 + + + ACTIVE + Session Request Status has changed + 0x1 + + + + + HSTNEGSUCSTSCHNG + Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) + 9 + 9 + + + INACTIVE + No Change + 0x0 + + + ACTIVE + Host Negotiation Status Change + 0x1 + + + + + HSTNEGDET + Mode:Host and Device. Host Negotiation Detected (HstNegDet) + 17 + 17 + + + INACTIVE + No Active HNP Request + 0x0 + + + ACTIVE + Active HNP request detected + 0x1 + + + + + ADEVTOUTCHG + Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) + 18 + 18 + + + INACTIVE + No A-Device Timeout + 0x0 + + + ACTIVE + A-Device Timeout + 0x1 + + + + + DBNCEDONE + Mode: Host only. Debounce Done (DbnceDone) + 19 + 19 + + + INACTIVE + After Connect waiting for Debounce to complete + 0x0 + + + ACTIVE + Debounce completed + 0x1 + + + + + MULTVALIPCHNG + This bit when set indicates that there is a change in the value of at least one ACA pin value. + 20 + 20 + + + NO_ACA_PIN_CHANGE + Indicates there is no change in ACA pin value + 0x0 + + + ACA_PIN_CHANGE + Indicates there is a change in ACA pin value + 0x1 + + + + + + + GAHBCFG + AHB Configuration Register + 0x008 + read-write + 0x00000000 + 0x20 + + + GLBLINTRMSK + Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) + 0 + 0 + + + MASK + Mask the interrupt assertion to the application + 0x0 + + + NOMASK + Unmask the interrupt assertion to the application. + 0x1 + + + + + HBSTLEN + Mode: Host and device. Burst Length/Type (HBstLen) + 1 + 4 + + + WORD1ORSINGLE + 1 word or single + 0x0 + + + WORD4ORINCR + 4 words or INCR + 0x1 + + + WORD8 + 8 words + 0x2 + + + WORD16ORINCR4 + 16 words or INCR4 + 0x3 + + + WORD32 + 32 words + 0x4 + + + WORD64ORINCR8 + 64 words or INCR8 + 0x5 + + + WORD128 + 128 words + 0x6 + + + WORD256ORINCR16 + 256 words or INCR16 + 0x7 + + + WORDX + Others reserved + 0x8 + + + + + DMAEN + Mode: Host and device. DMA Enable (DMAEn) + 5 + 5 + + + SLAVEMODE + Core operates in Slave mode + 0x0 + + + DMAMODE + Core operates in a DMA mode + 0x1 + + + + + NPTXFEMPLVL + Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + 7 + 7 + + + HALFEMPTY + DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or that the IN Endpoint TxFIFO is half empty. + 0x0 + + + EMPTY + GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty or that the IN Endpoint TxFIFO is completely empty. + 0x1 + + + + + REMMEMSUPP + Mode: Host and Device. Remote Memory Support (RemMemSupp) + 21 + 21 + + + DISABLED + Remote Memory Support Feature disabled + 0x0 + + + ENABLED + Remote Memory Support Feature enabled + 0x1 + + + + + NOTIALLDMAWRIT + Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) + 22 + 22 + + + LASTTRANS + Unspecified + 0x0 + + + ALLTRANS + The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint + 0x1 + + + + + AHBSINGLE + Mode: Host and Device. AHB Single Support (AHBSingle) + 23 + 23 + + + INCRBURST + The remaining data in the transfer is sent using INCR burst size + 0x0 + + + SINGLEBURST + The remaining data in the transfer is sent using Single burst size + 0x1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + read-write + 0x10001400 + 0x20 + + + TOUTCAL + Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) + 0 + 2 + + + ZERO + Add 0 PHY clocks + 0x0 + + + ONE + Add 1 PHY clocks + 0x1 + + + TWO + Add 2 PHY clocks + 0x2 + + + THREE + Add 3 PHY clocks + 0x3 + + + FOUR + Add 4 PHY clocks + 0x4 + + + FIVE + Add 5 PHY clocks + 0x5 + + + SIX + Add 6 PHY clocks + 0x6 + + + SEVEN + Add 7 PHY clocks + 0x7 + + + + + PHYIF + Mode: Host and Device. PHY Interface (PHYIf) + 3 + 3 + + + BITS8 + PHY 8bit Mode + 0x0 + + + BITS16 + PHY 16bit Mode + 0x1 + + + + + ULPIUTMISEL + Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) + 4 + 4 + read-only + + + UTMI + UTMI+ Interface + 0x0 + + + ULPI + ULPI Interface + 0x1 + + + + + FSINTF + Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) + 5 + 5 + read-only + + + FS6PIN + 6-pin unidirectional full-speed serial interface + 0x0 + + + FS3PIN + 3-pin bidirectional full-speed serial interface + 0x1 + + + + + PHYSEL + PHYSel + 6 + 6 + read-only + + + USB20 + USB 2.0 high-speed UTMI+ or ULPI PHY is selected + 0x0 + + + USB11 + USB 1.1 full-speed serial transceiver is selected + 0x1 + + + + + USBTRDTIM + Mode: Device only. USB Turnaround Time (USBTrdTim) + 10 + 13 + + + TURNTIME16BIT + MAC interface is 16-bit UTMI+. + 0x5 + + + TURNTIME8BIT + MAC interface is 8-bit UTMI+. + 0x9 + + + + + PHYLPWRCLKSEL + PHY Low-Power Clock Select (PhyLPwrClkSel) + 15 + 15 + + + INTPLLCLK + 480-MHz Internal PLL clock + 0x0 + + + EXTCLK + 48-MHz External Clock + 0x1 + + + + + TERMSELDLPULSE + Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) + 22 + 22 + + + TXVALID + Data line pulsing using utmi_txvalid + 0x0 + + + TERMSEL + Data line pulsing using utmi_termsel + 0x1 + + + + + ICUSBCAP + Mode: Host and Device. IC_USB-Capable (IC_USBCap) + 26 + 26 + read-only + + + NOTSELECTED + IC_USB PHY Interface is not selected + 0x0 + + + SELECTED + IC_USB PHY Interface is selected + 0x1 + + + + + TXENDDELAY + Mode: Device only. Tx End Delay (TxEndDelay) + 28 + 28 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Tx End delay + 0x1 + + + + + FORCEHSTMODE + Mode: Host and device. Force Host Mode (ForceHstMode) + 29 + 29 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Host Mode + 0x1 + + + + + FORCEDEVMODE + Mode:Host and device. Force Device Mode (ForceDevMode) + 30 + 30 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Device Mode + 0x1 + + + + + CORRUPTTXPKT + Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) + 31 + 31 + write-only + + + Disabled + Normal Mode + 0x0 + + + Enabled + Debug Mode + 0x1 + + + + + + + GRSTCTL + Reset Register + 0x010 + read-write + 0x80000000 + 0x20 + + + CSFTRST + Mode: Host and Device. Core Soft Reset (CSftRst) + 0 + 0 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Resets hclk and phy_clock domains + 0x1 + + + + + PIUFSSFTRST + Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + 1 + 1 + + + RESET_INACTIVE + No Reset + 0x0 + + + RESET_ACTIVE + PIU FS Dedicated Controller Soft Reset + 0x1 + + + + + FRMCNTRRST + Mode: Host only. Host Frame Counter Reset (FrmCntrRst) + 2 + 2 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Host Frame Counter Reset + 0x1 + + + + + RXFFLSH + Mode: Host and Device. RxFIFO Flush (RxFFlsh) + 4 + 4 + + + INACTIVE + Does not flush the entire RxFIFO + 0x0 + + + ACTIVE + Flushes the entire RxFIFO + 0x1 + + + + + TXFFLSH + Mode: Host and Device. TxFIFO Flush (TxFFlsh) + 5 + 5 + + + INACTIVE + No Flush + 0x0 + + + ACTIVE + Selectively flushes a single or all transmit FIFOs + 0x1 + + + + + TXFNUM + Mode: Host and Device. TxFIFO Number (TxFNum) + 6 + 10 + + + TXF0 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in shared FIFO operation -TXFIFO 0 flush in device mode when in dedicated FIFO mode + 0x00 + + + TXF1 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in shared FIFO operation -TXFIFO 1 flush in device mode when in dedicated FIFO mode + 0x01 + + + TXF2 + -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush in device mode when in dedicated FIFO mode + 0x02 + + + TXF3 + -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush in device mode when in dedicated FIFO mode + 0x03 + + + TXF4 + -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush in device mode when in dedicated FIFO mode + 0x04 + + + TXF5 + -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush in device mode when in dedicated FIFO mode + 0x05 + + + TXF6 + -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush in device mode when in dedicated FIFO mode + 0x06 + + + TXF7 + -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush in device mode when in dedicated FIFO mode + 0x07 + + + TXF8 + -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush in device mode when in dedicated FIFO mode + 0x08 + + + TXF9 + -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush in device mode when in dedicated FIFO mode + 0x09 + + + TXF10 + -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flush in device mode when in dedicated FIFO mode + 0x0A + + + TXF11 + -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flush in device mode when in dedicated FIFO mode + 0x0B + + + TXF12 + -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flush in device mode when in dedicated FIFO mode + 0x0C + + + TXF13 + -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flush in device mode when in dedicated FIFO mode + 0x0D + + + TXF14 + -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flush in device mode when in dedicated FIFO mode + 0x0E + + + TXF15 + -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flush in device mode when in dedicated FIFO mode + 0x0F + + + TXF16 + Flush all the transmit FIFOs in device or host mode + 0x10 + + + + + CSFTRSTDONE + Mode: Host and Device. Core Soft Reset Done (CSftRstDone) + 29 + 29 + + + INACTIVE + No reset + 0x0 + + + ACTIVE + Core Soft Reset is done + 0x1 + + + + + DMAREQ + Mode: Host and Device. DMA Request Signal (DMAReq) + 30 + 30 + read-only + + + INACTIVE + No DMA request + 0x0 + + + ACTIVE + DMA request is in progress + 0x1 + + + + + AHBIDLE + Mode: Host and Device. AHB Master Idle (AHBIdle) + 31 + 31 + read-only + + + INACTIVE + Not Idle + 0x0 + + + ACTIVE + AHB Master Idle + 0x1 + + + + + + + GINTSTS + Interrupt Register + 0x014 + read-write + 0x00000020 + 0x20 + + + CURMOD + Mode: Host and Device. Current Mode of Operation (CurMod) + 0 + 0 + read-only + + + DEVICE + Device mode + 0x0 + + + HOST + Host mode + 0x1 + + + + + MODEMIS + Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) + 1 + 1 + + + INACTIVE + No Mode Mismatch Interrupt + 0x0 + + + ACTIVE + Mode Mismatch Interrupt + 0x1 + + + + + OTGINT + Mode: Host and Device. OTG Interrupt (OTGInt) + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + OTG Interrupt + 0x1 + + + + + SOF + Mode: Host and Device. Start of (micro)Frame (Sof) + 3 + 3 + + + INTACTIVE + No Start of Frame + 0x0 + + + ACTIVE + Start of Frame + 0x1 + + + + + RXFLVL + Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) + 4 + 4 + read-only + + + INACTIVE + Rx Fifo is empty + 0x0 + + + ACTIVE + Rx Fifo is not empty + 0x1 + + + + + NPTXFEMP + Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) + 5 + 5 + read-only + + + INACTIVE + Non-periodic TxFIFO is not empty + 0x0 + + + ACTIVE + Non-periodic TxFIFO is empty + 0x1 + + + + + GINNAKEFF + Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) + 6 + 6 + read-only + + + INACTIVE + Global Non-periodic IN NAK not active + 0x0 + + + ACTIVE + Set Global Non-periodic IN NAK bit + 0x1 + + + + + GOUTNAKEFF + Mode: Device only. Global OUT NAK Effective (GOUTNakEff) + 7 + 7 + read-only + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Global OUT NAK Effective + 0x1 + + + + + ERLYSUSP + Mode: Device only. Early Suspend (ErlySusp) + 10 + 10 + + + INACTIVE + No Idle state detected + 0x0 + + + ACTIVE + 3ms of Idle state detected + 0x1 + + + + + USBSUSP + Mode: Device only. USB Suspend (USBSusp) + 11 + 11 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + USB Suspend + 0x1 + + + + + USBRST + Mode: Device only. USB Reset (USBRst) + 12 + 12 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + USB Reset + 0x1 + + + + + ENUMDONE + Mode: Device only. Enumeration Done (EnumDone) + 13 + 13 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Enumeration Done + 0x1 + + + + + ISOOUTDROP + Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + 14 + 14 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Isochronous OUT Packet Dropped Interrupt + 0x1 + + + + + EOPF + Mode: Device only. End of Periodic Frame Interrupt (EOPF) + 15 + 15 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + End of Periodic Frame Interrupt + 0x1 + + + + + RSTRDONEINT + Mode: Device only. Restore Done Interrupt (RstrDoneInt) + 16 + 16 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Restore Done Interrupt + 0x1 + + + + + EPMIS + Mode: Device only. Endpoint Mismatch Interrupt (EPMis) + 17 + 17 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Endpoint Mismatch Interrupt + 0x1 + + + + + IEPINT + Mode: Device only. IN Endpoints Interrupt (IEPInt) + 18 + 18 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + IN Endpoints Interrupt + 0x1 + + + + + OEPINT + Mode: Device only. OUT Endpoints Interrupt (OEPInt) + 19 + 19 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + OUT Endpoints Interrupt + 0x1 + + + + + INCOMPISOIN + Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) + 20 + 20 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Isochronous IN Transfer + 0x1 + + + + + INCOMPLP + Incomplete Periodic Transfer (incomplP) + 21 + 21 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Periodic Transfer + 0x1 + + + + + FETSUSP + Mode: Device only. Data Fetch Suspended (FetSusp) + 22 + 22 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Data Fetch Suspended + 0x1 + + + + + RESETDET + Mode: Device only. Reset detected Interrupt (ResetDet) + 23 + 23 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Reset detected Interrupt + 0x1 + + + + + PRTINT + Mode: Host only. Host Port Interrupt (PrtInt) + 24 + 24 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Port Interrupt + 0x1 + + + + + HCHINT + Mode: Host only. Host Channels Interrupt (HChInt) + 25 + 25 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Channels Interrupt + 0x1 + + + + + LPMINT + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). + 27 + 27 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + LPM Transaction Received Interrupt + 0x1 + + + + + CONIDSTSCHNG + Mode: Host and Device. Connector ID Status Change (ConIDStsChng) + 28 + 28 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Connector ID Status Change + 0x1 + + + + + DISCONNINT + Mode: Host only. Disconnect Detected Interrupt (DisconnInt) + 29 + 29 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Disconnect Detected Interrupt + 0x1 + + + + + SESSREQINT + Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) + 30 + 30 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Session Request New Session Detected Interrupt + 0x1 + + + + + WKUPINT + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) + 31 + 31 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Resume or Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GINTMSK + Interrupt Mask Register + 0x018 + read-write + 0x00000000 + 0x20 + + + MODEMISMSK + Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) + 1 + 1 + + + MASK + Mode Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Mode Mismatch Interrupt Mask + 0x1 + + + + + OTGINTMSK + Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) + 2 + 2 + + + MASK + OTG Interrupt Mask + 0x0 + + + NOMASK + No OTG Interrupt Mask + 0x1 + + + + + SOFMSK + Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) + 3 + 3 + + + MASK + Start of Frame Mask + 0x0 + + + NOMASK + No Start of Frame Mask + 0x1 + + + + + RXFLVLMSK + Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) + 4 + 4 + + + MASK + Receive FIFO Non-Empty Mask + 0x0 + + + NOMASK + No Receive FIFO Non-Empty Mask + 0x1 + + + + + NPTXFEMPMSK + Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + 5 + 5 + + + MASK + Non-periodic TxFIFO Empty Mask + 0x0 + + + NOMASK + No Non-periodic TxFIFO Empty Mask + 0x1 + + + + + GINNAKEFFMSK + Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + 6 + 6 + + + MASK + Global Non-periodic IN NAK Effective Mask + 0x0 + + + NOMASK + No Global Non-periodic IN NAK Effective Mask + 0x1 + + + + + GOUTNAKEFFMSK + Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) + 7 + 7 + + + MASK + Global OUT NAK Effective Mask + 0x0 + + + NOMASK + No Global OUT NAK Effective Mask + 0x1 + + + + + ERLYSUSPMSK + Mode: Device only. Early Suspend Mask (ErlySuspMsk) + 10 + 10 + + + MASK + Early Suspend Mask + 0x0 + + + NOMASK + No Early Suspend Mask + 0x1 + + + + + USBSUSPMSK + Mode: Device only. USB Suspend Mask (USBSuspMsk) + 11 + 11 + + + MASK + USB Suspend Mask + 0x0 + + + NOMASK + No USB Suspend Mask + 0x1 + + + + + USBRSTMSK + Mode: Device only. USB Reset Mask (USBRstMsk) + 12 + 12 + + + MASK + USB Reset Mask + 0x0 + + + NOMASK + No USB Reset Mask + 0x1 + + + + + ENUMDONEMSK + Mode: Device only. Enumeration Done Mask (EnumDoneMsk) + 13 + 13 + + + MASK + Enumeration Done Mask + 0x0 + + + NOMASK + No Enumeration Done Mask + 0x1 + + + + + ISOOUTDROPMSK + Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + 14 + 14 + + + MASK + Isochronous OUT Packet Dropped Interrupt Mask + 0x0 + + + NOMASK + No Isochronous OUT Packet Dropped Interrupt Mask + 0x1 + + + + + EOPFMSK + Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) + 15 + 15 + + + MASK + End of Periodic Frame Interrupt Mask + 0x0 + + + NOMASK + No End of Periodic Frame Interrupt Mask + 0x1 + + + + + RSTRDONEINTMSK + Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) + 16 + 16 + + + MASK + Restore Done Interrupt Mask + 0x0 + + + NOMASK + No Restore Done Interrupt Mask + 0x1 + + + + + EPMISMSK + Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) + 17 + 17 + + + MASK + Endpoint Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Endpoint Mismatch Interrupt Mask + 0x1 + + + + + IEPINTMSK + Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) + 18 + 18 + + + MASK + IN Endpoints Interrupt Mask + 0x0 + + + NOMASK + No IN Endpoints Interrupt Mask + 0x1 + + + + + OEPINTMSK + Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) + 19 + 19 + + + MASK + OUT Endpoints Interrupt Mask + 0x0 + + + NOMASK + No OUT Endpoints Interrupt Mask + 0x1 + + + + + INCOMPLPMSK + Incomplete Periodic Transfer Mask (incomplPMsk) + 21 + 21 + + + MASK + Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT Transfer Mask + 0x0 + + + NOMASK + Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous OUT Transfer Mask + 0x1 + + + + + FETSUSPMSK + Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) + 22 + 22 + + + MASK + Data Fetch Suspended Mask + 0x0 + + + NOMASK + No Data Fetch Suspended Mask + 0x1 + + + + + RESETDETMSK + Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) + 23 + 23 + + + MASK + Reset detected Interrupt Mask + 0x0 + + + NOMASK + No Reset detected Interrupt Mask + 0x1 + + + + + PRTINTMSK + Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) + 24 + 24 + + + MASK + Host Port Interrupt Mask + 0x0 + + + NOMASK + No Host Port Interrupt Mask + 0x1 + + + + + HCHINTMSK + Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) + 25 + 25 + + + MASK + Host Channels Interrupt Mask + 0x0 + + + NOMASK + No Host Channels Interrupt Mask + 0x1 + + + + + LPMINTMSK + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) + 27 + 27 + + + MASK + LPM Transaction received interrupt Mask + 0x0 + + + NOMASK + No LPM Transaction received interrupt Mask + 0x1 + + + + + CONIDSTSCHNGMSK + Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) + 28 + 28 + + + MASK + Connector ID Status Change Mask + 0x0 + + + NOMASK + No Connector ID Status Change Mask + 0x1 + + + + + DISCONNINTMSK + Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) + 29 + 29 + + + MASK + Disconnect Detected Interrupt Mask + 0x0 + + + NOMASK + No Disconnect Detected Interrupt Mask + 0x1 + + + + + SESSREQINTMSK + Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + 30 + 30 + + + MASK + Session Request or New Session Detected Interrupt Mask + 0x0 + + + NOMASK + No Session Request or New Session Detected Interrupt Mask + 0x1 + + + + + WKUPINTMSK + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + 31 + 31 + + + MASK + Resume or Remote Wakeup Detected Interrupt Mask + 0x0 + + + NOMASK + Unmask Resume Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GRXSTSR + Receive Status Debug Read Register + 0x01C + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + DSETUPRX + SETUP data packet received in device mode + 0x6 + + + CHHALT + Channel halted in host mode (triggers an interrupt) + 0x7 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXSTSP + Receive Status Read/Pop Register + 0x020 + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + read-write + 0x00000224 + 0x20 + + + RXFDEP + Mode: Host and Device. RxFIFO Depth (RxFDep) + 0 + 9 + + + + + GNPTXFSIZ + Non-periodic Transmit FIFO Size Register + 0x028 + read-write + 0x02000224 + 0x20 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start Address (NPTxFStAddr) + 0 + 9 + + + NPTXFDEP + Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) + 16 + 25 + + + + + GNPTXSTS + Non-periodic Transmit FIFO/Queue Status Register + 0x02C + read-write + 0x00080200 + 0x20 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + 0 + 15 + read-only + + + NPTXQSPCAVAIL + Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + 16 + 23 + read-only + + + FULL + Non-periodic Transmit Request Queue is full + 0x00 + + + QUE1 + 1 location available + 0x01 + + + QUE2 + 2 locations available + 0x02 + + + QUE3 + 3 locations available + 0x03 + + + QUE4 + 4 locations available + 0x04 + + + QUE5 + 5 locations available + 0x05 + + + QUE6 + 6 locations available + 0x06 + + + QUE7 + 7 locations available + 0x07 + + + QUE8 + 8 locations available + 0x08 + + + + + NPTXQTOP + Top of the Non-periodic Transmit Request Queue (NPTxQTop) + 24 + 30 + read-only + + + INOUTTK + IN/OUT token + 0x00 + + + ZEROTX + Zero-length transmit packet (device IN/host OUT) + 0x01 + + + PINGCSPLIT + PING/CSPLIT token + 0x02 + + + CHNHALT + Channel halt command + 0x03 + + + + + + + GGPIO + General Purpose Input/Output Register + 0x038 + read-write + 0x00000000 + 0x20 + + + GPI + 0 + 15 + read-only + + + GPO + 16 + 31 + + + + + GUID + User ID Register + 0x03C + read-write + 0x00000000 + 0x20 + + + GUID + User ID (UserID) Application-programmable ID field. + 0 + 31 + + + + + GSNPSID + Synopsys ID Register + 0x040 + read-write + 0x4F54430A + 0x20 + + + SYNOPSYSID + Release number of the controller being used currently. + 0 + 31 + read-only + + + + + GHWCFG1 + User Hardware Configuration 1 Register + 0x044 + read-write + 0xAA555000 + 0x20 + + + EPDIR + This 32-bit field uses two bits per + 0 + 31 + read-only + + + + + GHWCFG2 + User Hardware Configuration 2 Register + 0x048 + read-write + 0x228BFC72 + 0x20 + + + OTGMODE + Mode of Operation (OtgMode) + 0 + 2 + read-only + + + HNPSRP + HNP- and SRP-Capable OTG (Host and Device) + 0x0 + + + SRPOTG + SRP-Capable OTG (Host and Device) + 0x1 + + + NHNPNSRP + Non-HNP and Non-SRP Capable OTG (Host and Device) + 0x2 + + + SRPCAPD + SRP-Capable Device + 0x3 + + + NONOTGD + Non-OTG Device + 0x4 + + + SRPCAPH + SRP-Capable Host + 0x5 + + + NONOTGH + Non-OTG Host + 0x6 + + + + + OTGARCH + Architecture (OtgArch) + 3 + 4 + read-only + + + SLAVEMODE + Slave Mode + 0x0 + + + EXTERNALDMA + External DMA Mode + 0x1 + + + INTERNALDMA + Internal DMA Mode + 0x2 + + + + + SINGPNT + Point-to-Point (SingPnt) + 5 + 5 + read-only + + + MULTIPOINT + Multi-point application (hub and split support) + 0x0 + + + SINGLEPOINT + Single-point application (no hub and split support) + 0x1 + + + + + HSPHYTYPE + High-Speed PHY Interface Type (HSPhyType) + 6 + 7 + read-only + + + NOHS + High-Speed interface not supported + 0x0 + + + UTMIPLUS + High Speed Interface UTMI+ is supported + 0x1 + + + ULPI + High Speed Interface ULPI is supported + 0x2 + + + UTMIPUSULPI + High Speed Interfaces UTMI+ and ULPI is supported + 0x3 + + + + + FSPHYTYPE + Full-Speed PHY Interface Type (FSPhyType) + 8 + 9 + read-only + + + NO_FS + Full-speed interface not supported + 0x0 + + + FS + Dedicated full-speed interface is supported + 0x1 + + + FSPLUSUTMI + FS pins shared with UTMI+ pins is supported + 0x2 + + + FSPLUSULPI + FS pins shared with ULPI pins is supported + 0x3 + + + + + NUMDEVEPS + Number of Device Endpoints (NumDevEps) + 10 + 13 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + NUMHSTCHNL + Number of Host Channels (NumHstChnl) + 14 + 17 + read-only + + + HOSTCH0 + Host Channel 1 + 0x0 + + + HOSTCH1 + Host Channel 2 + 0x1 + + + HOSTCH2 + Host Channel 3 + 0x2 + + + HOSTCH3 + Host Channel 4 + 0x3 + + + HOSTCH4 + Host Channel 5 + 0x4 + + + HOSTCH5 + Host Channel 6 + 0x5 + + + HOSTCH6 + Host Channel 7 + 0x6 + + + HOSTCH7 + Host Channel 8 + 0x7 + + + HOSTCH8 + Host Channel 9 + 0x8 + + + HOSTCH9 + Host Channel 10 + 0x9 + + + HOSTCH10 + Host Channel 11 + 0xA + + + HOSTCH11 + Host Channel 12 + 0xB + + + HOSTCH12 + Host Channel 13 + 0xC + + + HOSTCH13 + Host Channel 14 + 0xD + + + HOSTCH14 + Host Channel 15 + 0xE + + + HOSTCH15 + Host Channel 16 + 0xF + + + + + PERIOSUPPORT + Periodic OUT Channels Supported in Host Mode (PerioSupport) + 18 + 18 + read-only + + + DISABLED + Periodic OUT Channels is not supported in Host Mode + 0x0 + + + ENABLED + Periodic OUT Channels Supported in Host Mode Supported + 0x1 + + + + + DYNFIFOSIZING + Dynamic FIFO Sizing Enabled (DynFifoSizing) + 19 + 19 + read-only + + + DISABLED + Dynamic FIFO Sizing Disabled + 0x0 + + + ENABLED + Dynamic FIFO Sizing Enabled + 0x1 + + + + + MULTIPROCINTRPT + Multi Processor Interrupt Enabled (MultiProcIntrpt) + 20 + 20 + read-only + + + DISABLED + No Multi Processor Interrupt Enabled + 0x0 + + + ENABLED + Multi Processor Interrupt Enabled + 0x1 + + + + + NPTXQDEPTH + Non-periodic Request Queue Depth (NPTxQDepth) + 22 + 23 + read-only + + + TWO + Queue size 2 + 0x0 + + + FOUR + Queue size 4 + 0x1 + + + EIGHT + Queue size 8 + 0x2 + + + + + PTXQDEPTH + Host Mode Periodic Request Queue Depth (PTxQDepth) + 24 + 25 + read-only + + + QUE2 + Queue Depth 2 + 0x0 + + + QUE4 + Queue Depth 4 + 0x1 + + + QUE8 + Queue Depth 8 + 0x2 + + + QUE16 + Queue Depth 16 + 0x3 + + + + + TKNQDEPTH + Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + 26 + 30 + read-only + + + + + GHWCFG3 + User Hardware Configuration 3 Register + 0x04C + read-write + 0x0BEAC0E8 + 0x20 + + + XFERSIZEWIDTH + Width of Transfer Size Counters (XferSizeWidth) + 0 + 3 + read-only + + + WIDTH11 + Width of Transfer Size Counter 11 bits + 0x0 + + + WIDTH12 + Width of Transfer Size Counter 12 bits + 0x1 + + + WIDTH13 + Width of Transfer Size Counter 13 bits + 0x2 + + + WIDTH14 + Width of Transfer Size Counter 14 bits + 0x3 + + + WIDTH15 + Width of Transfer Size Counter 15 bits + 0x4 + + + WIDTH16 + Width of Transfer Size Counter 16 bits + 0x5 + + + WIDTH17 + Width of Transfer Size Counter 17 bits + 0x6 + + + WIDTH18 + Width of Transfer Size Counter 18 bits + 0x7 + + + WIDTH19 + Width of Transfer Size Counter 19 bits + 0x8 + + + + + PKTSIZEWIDTH + Width of Packet Size Counters (PktSizeWidth) + 4 + 6 + read-only + + + BITS4 + Width of Packet Size Counter 4 + 0x0 + + + BITS5 + Width of Packet Size Counter 5 + 0x1 + + + BITS6 + Width of Packet Size Counter 6 + 0x2 + + + BITS7 + Width of Packet Size Counter 7 + 0x3 + + + BITS8 + Width of Packet Size Counter 8 + 0x4 + + + BITS9 + Width of Packet Size Counter 9 + 0x5 + + + BITS10 + Width of Packet Size Counter 10 + 0x6 + + + + + OTGEN + OTG Function Enabled (OtgEn) + 7 + 7 + read-only + + + DISABLED + Not OTG Capable + 0x0 + + + ENABLED + OTG Capable + 0x1 + + + + + I2CINTSEL + I2C Selection (I2CIntSel) + 8 + 8 + read-only + + + DISABLED + I2C Interface is not available + 0x0 + + + ENABLED + I2C Interface is available + 0x1 + + + + + VNDCTLSUPT + Vendor Control Interface Support (VndctlSupt) + 9 + 9 + read-only + + + DISABLED + Vendor Control Interface is not available. + 0x0 + + + ENABLED + Vendor Control Interface is available. + 0x1 + + + + + OPTFEATURE + Optional Features Removed (OptFeature) + 10 + 10 + read-only + + + DISABLED + Optional features were not Removed + 0x0 + + + ENABLED + Optional Features have been Removed + 0x1 + + + + + RSTTYPE + Reset Style for Clocked always Blocks in RTL (RstType) + 11 + 11 + read-only + + + ASYNCRST + Asynchronous reset is used in the core + 0x0 + + + SYNCRST + Synchronous reset is used in the core + 0x1 + + + + + ADPSUPPORT + This bit indicates whether ADP logic is present within or external to the controller + 12 + 12 + read-only + + + DISABLED + ADP logic is not present along with the controller + 0x0 + + + ENABLED + ADP logic is present along with the controller + 0x1 + + + + + HSICMODE + HSIC mode specified for Mode of Operation + 13 + 13 + read-only + + + DISABLED + No HSIC capability + 0x0 + + + ENABLED + HSIC-capable with shared UTMI PHY interface + 0x1 + + + + + BCSUPPORT + This bit indicates the controller support for Battery Charger. + 14 + 14 + read-only + + + DISABLED + No Battery Charger Support + 0x0 + + + ENABLED + Battery Charger Support present + 0x1 + + + + + LPMMODE + LPM mode specified for Mode of Operation. + 15 + 15 + read-only + + + DISABLED + LPM disabled + 0x0 + + + ENABLED + LPM enabled + 0x1 + + + + + DFIFODEPTH + DFIFO Depth (DfifoDepth - EP_LOC_CNT) + 16 + 31 + read-only + + + + + GHWCFG4 + User Hardware Configuration 4 Register + 0x050 + read-write + 0x1E10AA60 + 0x20 + + + NUMDEVPERIOEPS + Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + 0 + 3 + read-only + + + Value0 + Number of Periodic IN EPs is 0 + 0x0 + + + Value1 + Number of Periodic IN EPs is 1 + 0x1 + + + Value2 + Number of Periodic IN EPs is 2 + 0x2 + + + Value3 + Number of Periodic IN EPs is 3 + 0x3 + + + Value4 + Number of Periodic IN EPs is 4 + 0x4 + + + Value5 + Number of Periodic IN EPs is 5 + 0x5 + + + Value6 + Number of Periodic IN EPs is 6 + 0x6 + + + Value7 + Number of Periodic IN EPs is 7 + 0x7 + + + Value8 + Number of Periodic IN EPs is 8 + 0x8 + + + Value9 + Number of Periodic IN EPs is 9 + 0x9 + + + Value10 + Number of Periodic IN EPs is 10 + 0xA + + + Value11 + Number of Periodic IN EPs is 11 + 0xB + + + Value12 + Number of Periodic IN EPs is 12 + 0xC + + + Value13 + Number of Periodic IN EPs is 13 + 0xD + + + Value14 + Number of Periodic IN EPs is 14 + 0xE + + + Value15 + Number of Periodic IN EPs is 15 + 0xF + + + + + PARTIALPWRDN + Enable Partial Power Down (PartialPwrDn) + 4 + 4 + read-only + + + DISABLED + Partial Power Down disabled + 0x0 + + + ENABLED + Partial Power Down enabled + 0x1 + + + + + AHBFREQ + Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + 5 + 5 + read-only + + + DISABLED + Minimum AHB Frequency More Than 60 MHz + 0x0 + + + ENABLED + Minimum AHB Frequency Less Than 60 MHz + 0x1 + + + + + HIBERNATION + Enable Hibernation (Hibernation) + 6 + 6 + read-only + + + DISABLED + Hibernation feature disabled + 0x0 + + + ENABLED + Hibernation feature enabled + 0x1 + + + + + EXTENDEDHIBERNATION + Enable Hibernation + 7 + 7 + read-only + + + DISABLED + Extended Hibernation feature not enabled + 0x0 + + + ENABLED + Extended Hibernation feature enabled + 0x1 + + + + + ENHANCEDLPMSUPT1 + Enhanced LPM Support1 (EnhancedLPMSupt1) + 9 + 9 + read-only + + + DISABLED + Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty. + 0x0 + + + ENABLED + Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty + 0x1 + + + + + SERVINTFLOW + Service Interval Flow + 10 + 10 + read-only + + + DISABLED + Service Interval Flow not supported + 0x0 + + + ENABLED + Service Interval Flow supported + 0x1 + + + + + IPGISOCSUPT + Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) + 11 + 11 + read-only + + + DISABLED + Interpacket Gap ISOC OUT Worst-case Support is Disabled + 0x0 + + + ENABLED + Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) + 0x1 + + + + + ACGSUPT + Active Clock Gating Support + 12 + 12 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Active Clock Gating Support + 0x1 + + + + + ENHANCEDLPMSUPT + Enhanced LPM Support (EnhancedLPMSupt) + 13 + 13 + read-only + + + ENABLED + Enhanced LPM Support is enabled + 0x1 + + + + + PHYDATAWIDTH + UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + 14 + 15 + read-only + + + WIDTH1 + 8 bits + 0x0 + + + WIDTH2 + 16 bits + 0x1 + + + WIDTH3 + 8/16 bits, software selectable + 0x2 + + + + + NUMCTLEPS + Number of Device Mode Control Endpoints in Addition to + 16 + 19 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + IDDGFLTR + IDDIG Filter Enable (IddgFltr) + 20 + 20 + read-only + + + DISABLED + Iddig Filter Disabled + 0x0 + + + ENABLED + Iddig Filter Enabled + 0x1 + + + + + VBUSVALIDFLTR + VBUS Valid Filter Enabled (VBusValidFltr) + 21 + 21 + read-only + + + DISABLED + Vbus Valid Filter Disabled + 0x0 + + + ENABLED + Vbus Valid Filter Enabled + 0x1 + + + + + AVALIDFLTR + a_valid Filter Enabled (AValidFltr) + 22 + 22 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + BVALIDFLTR + b_valid Filter Enabled (BValidFltr) + 23 + 23 + read-only + + + DISABLED + No Filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + SESSENDFLTR + session_end Filter Enabled (SessEndFltr) + 24 + 24 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + DEDFIFOMODE + Enable Dedicated Transmit FIFO for device IN Endpoints + 25 + 25 + read-only + + + DISABLED + Dedicated Transmit FIFO Operation not enabled + 0x0 + + + ENABLED + Dedicated Transmit FIFO Operation enabled + 0x1 + + + + + INEPS + Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + 26 + 29 + read-only + + + ENDPT1 + 1 IN Endpoint + 0x0 + + + ENDPT2 + 2 IN Endpoints + 0x1 + + + ENDPT3 + 3 IN Endpoints + 0x2 + + + ENDPT4 + 4 IN Endpoints + 0x3 + + + ENDPT5 + 5 IN Endpoints + 0x4 + + + ENDPT6 + 6 IN Endpoints + 0x5 + + + ENDPT7 + 7 IN Endpoints + 0x6 + + + ENDPT8 + 8 IN Endpoints + 0x7 + + + ENDPT9 + 9 IN Endpoints + 0x8 + + + ENDPT10 + 10 IN Endpoints + 0x9 + + + ENDPT11 + 11 IN Endpoints + 0xA + + + ENDPT12 + 12 IN Endpoints + 0xB + + + ENDPT13 + 13 IN Endpoints + 0xC + + + ENDPT14 + 14 IN Endpoints + 0xD + + + ENDPT15 + 15 IN Endpoints + 0xE + + + ENDPT16 + 16 IN Endpoints + 0xF + + + + + DESCDMAENABLED + Scatter/Gather DMA configuration + 30 + 30 + read-only + + + DISABLE + Non-Scatter/Gather DMA configuration + 0x0 + + + ENABLE + Scatter/Gather DMA configuration + 0x1 + + + + + DESCDMA + Scatter/Gather DMA configuration + 31 + 31 + read-only + + + CONFIG1 + Non Dynamic configuration + 0x0 + + + CONFIG2 + Dynamic configuration + 0x1 + + + + + + + GLPMCFG + LPM Config Register + 0x054 + read-write + 0x00000000 + 0x20 + + + LPMCAP + LPM-Capable (LPMCap) + 0 + 0 + + + DISABLED + LPM capability is not enabled + 0x0 + + + ENABLED + LPM capability is enabled + 0x1 + + + + + APPL1RES + Mode: Device only. LPM response programmed by application (AppL1Res) + 1 + 1 + + + NYET_RESP + The core responds with a NYET when an error is detected in either of the LPM token packets due to corruption + 0x0 + + + ACK_RESP + The core responds with an ACK only on a successful LPM transaction + 0x1 + + + + + HIRD + Host-Initiated Resume Duration (HIRD) + 2 + 5 + + + BREMOTEWAKE + RemoteWakeEnable (bRemoteWake) + 6 + 6 + + + DISABLED + Remote Wakeup is disabled + 0x0 + + + ENABLED + In Host or device mode, this field takes the value of remote wake up + 0x1 + + + + + ENBLSLPM + Enable utmi_sleep_n (EnblSlpM) + 7 + 7 + + + DISABLED + utmi_sleep_n assertion from the core is not transferred to the external PHY + 0x0 + + + ENABLED + utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted + 0x1 + + + + + HIRDTHRES + BESL/HIRD Threshold (HIRD_Thres) + 8 + 12 + + + COREL1RES + LPM Response (CoreL1Res) + 13 + 14 + read-only + + + LPMRESP1 + ERROR : No handshake response + 0x0 + + + LPMRESP2 + STALL response + 0x1 + + + LPMRESP3 + NYET response + 0x2 + + + LPMRESP4 + ACK response + 0x3 + + + + + SLPSTS + Port Sleep Status (SlpSts) + 15 + 15 + read-only + + + CORE_NOT_IN_L1 + In Host or Device mode, this bit indicates core is not in L1 + 0x0 + + + CORE_IN_L1 + In Host mode, this bit indicates the core transitions to Sleep state as a successful LPM transaction. In Device mode, the core enters the Sleep state when an ACK response is sent to an LPM transaction + 0x1 + + + + + L1RESUMEOK + Sleep State Resume OK (L1ResumeOK) + 16 + 16 + read-only + + + NOTOK + The application/core cannot start Resume from Sleep state + 0x0 + + + OK + The application/core can start Resume from Sleep state + 0x1 + + + + + LPMCHNLINDX + LPM Channel Index + 17 + 20 + + + CH0 + Channel 0 + 0x0 + + + CH1 + Channel 1 + 0x1 + + + CH2 + Channel 2 + 0x2 + + + CH3 + Channel 3 + 0x3 + + + CH4 + Channel 4 + 0x4 + + + CH5 + Channel 5 + 0x5 + + + CH6 + Channel 6 + 0x6 + + + CH7 + Channel 7 + 0x7 + + + CH8 + Channel 8 + 0x8 + + + CH9 + Channel 9 + 0x9 + + + CH10 + Channel 10 + 0xA + + + CH11 + Channel 11 + 0xB + + + CH12 + Channel 12 + 0xC + + + CH13 + Channel 13 + 0xD + + + CH14 + Channel 14 + 0xE + + + CH15 + Channel15 + 0xF + + + + + LPMRETRYCNT + LPM Retry Count (LPM_Retry_Cnt) + 21 + 23 + + + RETRY0 + Zero LPM retries + 0x0 + + + RETRY1 + One LPM retry + 0x1 + + + RETRY2 + Two LPM retries + 0x2 + + + RETRY3 + Three LPM retries + 0x3 + + + RETRY4 + Four LPM retries + 0x4 + + + RETRY5 + Five LPM retries + 0x5 + + + RETRY6 + Six LPM retries + 0x6 + + + RETRY7 + Seven LPM retries + 0x7 + + + + + SNDLPM + Send LPM Transaction (SndLPM) + 24 + 24 + + + DISABLED + In host-only mode: Received the response from the device for the LPM transaction + 0x0 + + + ENABLED + In host-only mode: Sending LPM transaction containing EXT and LPM tokens + 0x1 + + + + + LPMRETRYCNTSTS + LPM Retry Count Status (LPM_RetryCnt_Sts) + 25 + 27 + read-only + + + RETRY_REM0 + Zero LPM retries remaining + 0x0 + + + RETRY_REM1 + One LPM retry remaining + 0x1 + + + RETRY_REM2 + Two LPM retries remaining + 0x2 + + + RETRY_REM3 + Three LPM retries remaining + 0x3 + + + RETRY_REM4 + Four LPM retries remaining + 0x4 + + + RETRY_REM5 + Five LPM retries remaining + 0x5 + + + RETRY_REM6 + Six LPM retries remaining + 0x6 + + + RETRY_REM7 + Seven LPM retries remaining + 0x7 + + + + + LPMENBESL + LPM Enable BESL (LPM_EnBESL) + 28 + 28 + + + DISABLED + BESL is disabled + 0x0 + + + ENABLED + BESL is enabled as defined in LPM Errata + 0x1 + + + + + LPMRESTORESLPSTS + LPM Restore Sleep Status (LPM_RestoreSlpSts) + 29 + 29 + + + DISABLED + Puts the core in Shallow Sleep mode based on the BESL value from the Host + 0x0 + + + ENABLED + Puts the core in Deep Sleep mode based on the BESL value from the Host + 0x1 + + + + + + + GPWRDN + Global Power Down Register + 0x058 + read-write + 0x00000010 + 0x20 + + + PMUINTSEL + PMU Interrupt Select (PMUIntSel) + 0 + 0 + + + DISABLE + Internal DWC_otg_core interrupt is selected + 0x0 + + + ENABLE + External DWC_otg_pmu interrupt is selected + 0x1 + + + + + PMUACTV + PMU Active (PMUActv) + 1 + 1 + + + DISABLE + Disable PMU module + 0x0 + + + ENABLE + Enable PMU module + 0x1 + + + + + RESTORE + Restore + 2 + 2 + + + DISABLE + The controller in normal mode of operation + 0x0 + + + ENABLE + The controller in Restore mode + 0x1 + + + + + PWRDNCLMP + Power Down Clamp (PwrDnClmp) + 3 + 3 + + + DISABLE + Disable PMU power clamp + 0x0 + + + ENABLE + Enable PMU power clamp + 0x1 + + + + + PWRDNRSTN + Power Down ResetN (PwrDnRst_n) + 4 + 4 + + + DISABLE + Reset the controller + 0x0 + + + ENABLE + The controller is in normal operation + 0x1 + + + + + PWRDNSWTCH + Power Down Switch (PwrDnSwtch) + 5 + 5 + + + ON + The controller is in ON state + 0x0 + + + OFF + The controller is in OFF state + 0x1 + + + + + DISABLEVBUS + DisableVBUS + 6 + 6 + + + DISABLED + Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid + 0x0 + + + ENABLED + Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End + 0x1 + + + + + LNSTSCHNG + Line State Change (LnStsChng) + 7 + 7 + + + DISABLED + No LineState change on USB + 0x0 + + + ENABLED + LineState change on USB + 0x1 + + + + + LINESTAGECHANGEMSK + LineStageChangeMsk + 8 + 8 + + + NOMASK + No LineStateChange Interrupt Mask + 0x0 + + + MASK + Mask for LineStateChange Interrupt + 0x1 + + + + + RESETDETECTED + ResetDetected + 9 + 9 + + + DISABLED + Reset not detected + 0x0 + + + ENABLED + Reset detected + 0x1 + + + + + RESETDETMSK + ResetDetMsk + 10 + 10 + + + NOMASK + No ResetDetect Interrupt Mask + 0x0 + + + MASK + Mask for ResetDetect Interrupt + 0x1 + + + + + DISCONNECTDETECT + DisconnectDetect + 11 + 11 + + + DISABLED + Disconnect not detected + 0x0 + + + ENABLED + Disconnect detected + 0x1 + + + + + DISCONNECTDETECTMSK + DisconnectDetectMsk + 12 + 12 + + + NOMASK + No DisconnectDetect Interrupt Mask + 0x0 + + + MASK + Mask for DisconnectDetect Interrupt + 0x1 + + + + + CONNECTDET + ConnectDet + 13 + 13 + + + DISABLED + Connect not detected + 0x0 + + + ENABLED + Connect detected + 0x1 + + + + + CONNDETMSK + ConnDetMsk + 14 + 14 + + + NOMASK + No ConnectDet Interrupt Mask + 0x0 + + + MASK + Mask for ConnectDet Interrupt + 0x1 + + + + + SRPDETECT + SRPDetect + 15 + 15 + + + DISABLED + SRP not detected + 0x0 + + + ENABLED + SRP detected + 0x1 + + + + + SRPDETECTMSK + SRPDetectMsk + 16 + 16 + + + NOMASK + No SRPDetect Interrupt Mask + 0x0 + + + MASK + Mask for SRPDetect Interrupt + 0x1 + + + + + STSCHNGINT + Status Change Interrupt (StsChngInt) + 17 + 17 + + + DISABLED + No Status change + 0x0 + + + ENABLED + Status change detected + 0x1 + + + + + STSCHNGINTMSK + StsChngIntMsk + 18 + 18 + + + NOMASK + No Status Change Interrupt Mask + 0x0 + + + MASK + Mask for Status Change Interrupt + 0x1 + + + + + LINESTATE + LineState + 19 + 20 + read-only + + + LS1 + Linestate on USB: DM = 0, DP = 0 + 0x0 + + + LS2 + Linestate on USB: DM = 0, DP = 1 + 0x1 + + + LS3 + Linestate on USB: DM = 1, DP = 0 + 0x2 + + + LS4 + Linestate on USB: Not-defined + 0x3 + + + + + IDDIG + This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application. + 21 + 21 + read-only + + + DISABLED + Host Mode + 0x0 + + + ENABLED + Device Mode + 0x1 + + + + + BSESSVLD + B Session Valid (BSessVld) + 22 + 22 + read-only + + + NOTVALID + B_Valid is 0 + 0x0 + + + VALID + B_Valid is 1 + 0x1 + + + + + MULTVALIDBC + MultValIdBC + 24 + 28 + read-only + + + RID_0 + OTG device as B-device + 0x00 + + + RID_C + OTG device as B-device, can connect + 0x01 + + + RID_B + OTG device as B-device, cannot connect + 0x02 + + + RID_A + OTG device as A-device + 0x04 + + + RID_GND + ID_OTG pin is grounded + 0x08 + + + RID_A_RID_GND + OTG device as A-device, RID_A=1 and RID_GND=1 + 0x0C + + + RID_FLOAT + ID pull down when ID_OTG is floating + 0x10 + + + RID_C_RID_FLOAT + OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1 + 0x11 + + + RID_B_RID_FLOAT + OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1 + 0x12 + + + RID_1 + OTG device as A-device + 0x1F + + + + + + + GDFIFOCFG + Global DFIFO Configuration Register + 0x05C + read-write + 0x0BEA0C00 + 0x20 + + + GDFIFOCFG + GDFIFOCfg + 0 + 15 + + + EPINFOBASEADDR + This field provides the start address of the EP info controller. + 16 + 31 + + + + + GINTMSK2 + Interrupt Mask Register 2 + 0x068 + read-write + 0x00000000 + 0x20 + + + GINTMSK2 + 0 + 31 + + + + + GINTSTS2 + Interrupt Register 2 + 0x06C + read-write + 0x00000000 + 0x20 + + + GINTSTS2 + 0 + 31 + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + read-write + 0x04000424 + 0x20 + + + PTXFSTADDR + Host Periodic TxFIFO Start Address (PTxFStAddr) + 0 + 10 + + + PTXFSIZE + Host Periodic TxFIFO Depth (PTxFSize) + 16 + 26 + + + + + 0x7 + 0x4 + DIEPTXF[%s] + Description collection: Device IN Endpoint Transmit FIFO Size Register + 0x104 + read-write + 0x02000424 + 0x20 + + + INEPNTXFSTADDR + IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + 0 + 10 + + + INEPNTXFDEP + IN Endpoint TxFIFO Depth (INEPnTxFDep) + 16 + 25 + + + + + HCFG + Host Configuration Register + 0x400 + read-write + 0x00000200 + 0x20 + + + FSLSPCLKSEL + FS/LS PHY Clock Select (FSLSPclkSel) + 0 + 1 + + + CLK3060 + PHY clock is running at 30/60 MHz + 0x0 + + + CLK48 + PHY clock is running at 48 MHz + 0x1 + + + CLK6 + PHY clock is running at 6 MHz + 0x2 + + + + + FSLSSUPP + FS- and LS-Only Support (FSLSSupp) + 2 + 2 + + + HSFSLS + HS/FS/LS, based on the maximum speed supported by the connected device + 0x0 + + + FSLS + FS/LS-only, even if the connected device can support HS + 0x1 + + + + + ENA32KHZS + Enable 32 KHz Suspend mode (Ena32KHzS) + 7 + 7 + + + DISABLED + 32 KHz Suspend mode disabled + 0x0 + + + ENABLED + 32 KHz Suspend mode enabled + 0x1 + + + + + RESVALID + Resume Validation Period (ResValid) + 8 + 15 + + + MODECHTIMEN + Mode Change Ready Timer Enable (ModeChTimEn) + 31 + 31 + + + ENABLED + The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x0 + + + DISABLED + The Host core waits only for a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x1 + + + + + + + HFIR + Host Frame Interval Register + 0x404 + read-write + 0x0000EA60 + 0x20 + + + FRINT + Frame Interval (FrInt) + 0 + 15 + + + HFIRRLDCTRL + Reload Control (HFIRRldCtrl) + 16 + 16 + + + DISABLED + The HFIR cannot be reloaded dynamically + 0x0 + + + ENABLED + The HFIR can be dynamically reloaded during runtime + 0x1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + read-write + 0x00003FFF + 0x20 + + + FRNUM + Frame Number (FrNum) + 0 + 15 + read-only + + + INACTIVE + No SOF is transmitted + 0x0000 + + + ACTIVE + SOF is transmitted + 0x0001 + + + + + FRREM + Frame Time Remaining (FrRem) + 16 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + read-write + 0x00000000 + 0x20 + + + HAINT + 0 + 15 + read-only + + + INACTIVE + Not active + 0x0000 + + + ACTIVE + Host Channel Interrupt + 0x0001 + + + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + read-write + 0x00000000 + 0x20 + + + HAINTMSK + Channel Interrupt Mask (HAINTMsk) + 0 + 15 + + + UNMASK + Unmask Channel interrupt + 0x0000 + + + MASK + Mask Channel interrupt + 0x0001 + + + + + + + HPRT + Host Port Control and Status Register + 0x440 + read-write + 0x00000000 + 0x20 + + + PRTCONNSTS + Port Connect Status (PrtConnSts) + 0 + 0 + read-only + + + NOTATTACHED + No device is attached to the port + 0x0 + + + ATTACHED + A device is attached to the port + 0x1 + + + + + PRTCONNDET + Port Connect Detected (PrtConnDet) + 1 + 1 + + + INACTIVE + No device connection detected + 0x0 + + + ACTIVE + Device connection detected + 0x1 + + + + + PRTENA + Port Enable (PrtEna) + 2 + 2 + + + DISABLED + Port disabled + 0x0 + + + ENABLED + Port enabled + 0x1 + + + + + PRTENCHNG + Port Enable/Disable Change (PrtEnChng) + 3 + 3 + + + INACTIVE + Port Enable bit 2 has not changed + 0x0 + + + ACTIVE + Port Enable bit 2 changed + 0x1 + + + + + PRTOVRCURRACT + Port Overcurrent Active (PrtOvrCurrAct) + 4 + 4 + read-only + + + INACTIVE + No overcurrent condition + 0x0 + + + ACTIVE + Overcurrent condition + 0x1 + + + + + PRTOVRCURRCHNG + Port Overcurrent Change (PrtOvrCurrChng) + 5 + 5 + + + INACTIVE + Status of port overcurrent status is not changed + 0x0 + + + ACTIVE + Status of port overcurrent changed + 0x1 + + + + + PRTRES + Port Resume (PrtRes) + 6 + 6 + + + NORESUME + No resume driven + 0x0 + + + RESUME + Resume driven + 0x1 + + + + + PRTSUSP + Port Suspend (PrtSusp) + 7 + 7 + + + INACTIVE + Port not in Suspend mode + 0x0 + + + ACTIVE + Port in Suspend mode + 0x1 + + + + + PRTRST + Port Reset (PrtRst) + 8 + 8 + + + DISABLED + Port not in reset + 0x0 + + + ENABLED + Port in reset + 0x1 + + + + + PRTLNSTS + Port Line Status (PrtLnSts) + 10 + 11 + read-only + + + PLUSD + Logic level of D+ + 0x1 + + + MINUSD + Logic level of D- + 0x2 + + + + + PRTPWR + Port Power (PrtPwr) + 12 + 12 + + + OFF + Power off + 0x0 + + + ON + Power on + 0x1 + + + + + PRTTSTCTL + Port Test Control (PrtTstCtl) + 13 + 16 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFENB + Test_force_Enable + 0x5 + + + + + PRTSPD + Port Speed (PrtSpd) + 17 + 18 + read-only + + + HIGHSPD + High speed + 0x0 + + + FULLSPD + Full speed + 0x1 + + + LOWSPD + Low speed + 0x2 + + + + + + + 16 + 0x018 + HC[%s] + Unspecified + USBHSCORE_HC + read-write + 0x500 + + CHAR + Description cluster: Host Channel Characteristics Register + 0x000 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + EPNUM + Endpoint Number (EPNum) + 11 + 14 + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + EPDIR + Endpoint Direction (EPDir) + 15 + 15 + + + OUT + OUT Direction + 0x0 + + + IN + IN Direction + 0x1 + + + + + LSPDDEV + Low-Speed Device (LSpdDev) + 17 + 17 + + + DISABLED + Not Communicating with low speed device + 0x0 + + + ENABLED + Communicating with low speed device + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CTRL + Control + 0x0 + + + ISOC + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERR + Interrupt + 0x3 + + + + + EC + Multi Count (MC) / Error Count (EC) + 20 + 21 + + + TRANSONE + 1 transaction + 0x1 + + + TRANSTWO + 2 transactions to be issued for this endpoint per microframe + 0x2 + + + TRANSTHREE + 3 transactions to be issued for this endpoint per microframe + 0x3 + + + + + DEVADDR + Device Address (DevAddr) + 22 + 28 + + + ODDFRM + Odd Frame (OddFrm) + 29 + 29 + + + EFRAME + Even Frame Transfer + 0x0 + + + OFRAME + Odd Frame Transfer + 0x1 + + + + + CHDIS + Channel Disable (ChDis) + 30 + 30 + + + INACTIVE + Transmit/Recieve normal + 0x0 + + + ACTIVE + Stop transmitting/receiving data on channel + 0x1 + + + + + CHENA + Channel Enable (ChEna) + 31 + 31 + + + DISABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is disabled. + 0x0 + + + ENABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure and data buffer with data is set up and this channel can access the descriptor. If Scatter/Gather mode is disabled, indicates that the channel is enabled. + 0x1 + + + + + + + INT + Description cluster: Host Channel Interrupt Register + 0x008 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed (XferCompl) + 0 + 0 + + + INACTIVE + Transfer in progress or No Active Transfer + 0x0 + + + ACTIVE + Transfer completed normally without any errors + 0x1 + + + + + CHHLTD + Channel Halted (ChHltd) + 1 + 1 + + + INACTIVE + Channel not halted + 0x0 + + + ACTIVE + Channel Halted + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB error + 0x0 + + + ACTIVE + AHB error during AHB read/write + 0x1 + + + + + STALL + STALL Response Received Interrupt (STALL) + 3 + 3 + + + INACTIVE + No Stall Response Received Interrupt + 0x0 + + + ACTIVE + Stall Response Received Interrupt + 0x1 + + + + + NAK + NAK Response Received Interrupt (NAK) + 4 + 4 + + + INACTIVE + No NAK Response Received Interrupt + 0x0 + + + ACTIVE + NAK Response Received Interrupt + 0x1 + + + + + ACK + ACK Response Received/Transmitted Interrupt (ACK) + 5 + 5 + + + INACTIVE + No ACK Response Received or Transmitted Interrupt + 0x0 + + + ACTIVE + ACK Response Received or Transmitted Interrup + 0x1 + + + + + NYET + NYET Response Received Interrupt (NYET) + 6 + 6 + + + INACTIVE + No NYET Response Received Interrupt + 0x0 + + + ACTIVE + NYET Response Received Interrupt + 0x1 + + + + + XACTERR + Transaction Error (XactErr) + 7 + 7 + + + INACTIVE + No Transaction Error + 0x0 + + + ACTIVE + Transaction Error + 0x1 + + + + + BBLERR + Babble Error (BblErr) + 8 + 8 + + + INACTIVE + No Babble Error + 0x0 + + + ACTIVE + Babble Error + 0x1 + + + + + FRMOVRUN + Frame Overrun (FrmOvrun). + 9 + 9 + + + INACTIVE + No Frame Overrun + 0x0 + + + ACTIVE + Frame Overrun + 0x1 + + + + + DATATGLERR + 10 + 10 + + + INACTIVE + No Data Toggle Error + 0x0 + + + ACTIVE + Data Toggle Error + 0x1 + + + + + + + INTMSK + Description cluster: Host Channel Interrupt Mask Register + 0x00C + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + 0 + 0 + + + MASK + Transfer Completed Mask + 0x0 + + + NOMASK + No Transfer Completed Mask + 0x1 + + + + + CHHLTDMSK + 1 + 1 + + + MASK + Channel Halted Mask + 0x0 + + + NOMASK + No Channel Halted Mask + 0x1 + + + + + AHBERRMSK + 2 + 2 + + + MASK + AHB Error Mask + 0x0 + + + NOMASK + No AHB Error Mask + 0x1 + + + + + STALLMSK + 3 + 3 + + + MASK + Mask STALL Response Received Interrupt + 0x0 + + + NOMASK + No STALL Response Received Interrupt Mask + 0x1 + + + + + NAKMSK + 4 + 4 + + + MASK + Mask NAK Response Received Interrupt + 0x0 + + + NOMASK + No NAK Response Received Interrupt Mask + 0x1 + + + + + ACKMSK + 5 + 5 + + + MASK + Mask ACK Response Received/Transmitted Interrupt + 0x0 + + + NOMASK + No ACK Response Received/Transmitted Interrupt Mask + 0x1 + + + + + NYETMSK + 6 + 6 + + + MASK + Mask NYET Response Received Interrupt + 0x0 + + + NOMASK + No NYET Response Received Interrupt Mask + 0x1 + + + + + XACTERRMSK + 7 + 7 + + + MASK + Mask Transaction Error + 0x0 + + + NOMASK + No Transaction Error Mask + 0x1 + + + + + BBLERRMSK + 8 + 8 + + + MASK + Mask Babble Error + 0x0 + + + NOMASK + No Babble Error Mask + 0x1 + + + + + FRMOVRUNMSK + 9 + 9 + + + MASK + Mask Overrun Mask + 0x0 + + + NOMASK + No Frame Overrun Mask + 0x1 + + + + + DATATGLERRMSK + 10 + 10 + + + MASK + Mask Data Toggle Error + 0x0 + + + NOMASK + No Data Toggle Error Mask + 0x1 + + + + + + + TSIZ + Description cluster: Host Channel Transfer Size Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Non-Scatter/Gather DMA Mode: + 0 + 18 + + + PKTCNT + Non-Scatter/Gather DMA Mode: + 19 + 28 + + + PID + PID (Pid) + 29 + 30 + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA (non-control)/SETUP (control) + 0x3 + + + + + DOPNG + Do Ping (DoPng) + 31 + 31 + + + NOPING + No ping protocol + 0x0 + + + PING + Ping protocol + 0x1 + + + + + + + DMA + Description cluster: Host Channel DMA Address Register + 0x014 + read-write + 0x00000000 + 0x20 + + + DMAADDR + In Buffer DMA Mode: + 0 + 31 + + + + + + DCFG + Device Configuration Register + 0x800 + read-write + 0x08020000 + 0x20 + + + DEVSPD + Device Speed (DevSpd) + 0 + 1 + + + USBHS20 + High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x0 + + + USBFS20 + Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x1 + + + USBLS116 + Low speed USB 1.1 transceiver clock is 6 MHz + 0x2 + + + USBFS1148 + Full speed USB 1.1 transceiver clock is 48 MHz + 0x3 + + + + + NZSTSOUTHSHK + Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + 2 + 2 + + + SENDOUT + Send the received OUT packet to the application (zero-length or non-zero length) and send a handshake based on NAK and STALL bits for the endpoint in the Devce Endpoint Control Register + 0x0 + + + SENDSTALL + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application + 0x1 + + + + + ENA32KHZSUSP + Enable 32 KHz Suspend mode (Ena32KHzSusp) + 3 + 3 + + + DISABLED + USB 1.1 Full-Speed Serial Transceiver not selected + 0x0 + + + ENABLED + USB 1.1 Full-Speed Serial Transceiver Interface selected + 0x1 + + + + + DEVADDR + Device Address (DevAddr) + 4 + 10 + + + PERFRINT + Periodic Frame Interval (PerFrInt) + 11 + 12 + + + EOPF80 + 80 percent of the (micro)Frame interval + 0x0 + + + EOPF85 + 85 percent of the (micro)Frame interval + 0x1 + + + EOPF90 + 90 percent of the (micro)Frame interval + 0x2 + + + EOPF95 + 95 percent of the (micro)Frame interval + 0x3 + + + + + XCVRDLY + XCVRDLY + 14 + 14 + + + DISABLE + No delay between xcvr_sel and txvalid during Device chirp + 0x0 + + + ENABLE + Enable delay between xcvr_sel and txvalid during Device chirp + 0x1 + + + + + ERRATICINTMSK + Erratic Error Interrupt Mask + 15 + 15 + + + NOMASK + Early suspend interrupt is generated on erratic error + 0x0 + + + MASK + Mask early suspend interrupt on erratic error + 0x1 + + + + + IPGISOCSUPT + Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) + 17 + 17 + + + DISABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is disabled + 0x0 + + + ENABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is enabled + 0x1 + + + + + PERSCHINTVL + Periodic Scheduling Interval (PerSchIntvl) + 24 + 25 + + + MF25 + 25 percent of (micro)Frame + 0x0 + + + MF50 + 50 percent of (micro)Frame + 0x1 + + + MF75 + 75 percent of (micro)Frame + 0x2 + + + + + RESVALID + Resume Validation Period (ResValid) + 26 + 31 + + + + + DCTL + Device Control Register + 0x804 + read-write + 0x00000002 + 0x20 + + + RMTWKUPSIG + Remote Wakeup Signaling (RmtWkUpSig) + 0 + 0 + + + DISABLEDRMWKUP + Core does not send Remote Wakeup Signaling + 0x0 + + + ENABLERMWKUP + Core sends Remote Wakeup Signaling + 0x1 + + + + + SFTDISCON + Soft Disconnect (SftDiscon) + 1 + 1 + + + NODISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + 0x0 + + + DISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host + 0x1 + + + + + GNPINNAKSTS + Global Non-periodic IN NAK Status (GNPINNakSts) + 2 + 2 + read-only + + + INACTIVE + A handshake is sent out based on the data availability in the transmit FIFO + 0x0 + + + ACTIVE + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + 0x1 + + + + + GOUTNAKSTS + Global OUT NAK Status (GOUTNakSts) + 3 + 3 + read-only + + + INACTIVE + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + 0x0 + + + ACTIVE + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + 0x1 + + + + + TSTCTL + Test Control (TstCtl) + 4 + 6 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFE + Test_force_Enable + 0x5 + + + + + SGNPINNAK + Set Global Non-periodic IN NAK (SGNPInNak) + 7 + 7 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Set Global Non-periodic IN NAK + 0x1 + + + + + CGNPINNAK + Clear Global Non-periodic IN NAK (CGNPInNak) + 8 + 8 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Clear Global Non-periodic IN NAK + 0x1 + + + + + SGOUTNAK + Set Global OUT NAK (SGOUTNak) + 9 + 9 + write-only + + + DISABLED + Disable Global OUT NAK + 0x0 + + + ENABLED + Set Global OUT NAK + 0x1 + + + + + CGOUTNAK + Clear Global OUT NAK (CGOUTNak) + 10 + 10 + write-only + + + DISABLED + Disable Clear Global OUT NAK + 0x0 + + + ENABLED + Clear Global OUT NAK + 0x1 + + + + + PWRONPRGDONE + Power-On Programming Done (PWROnPrgDone) + 11 + 11 + + + NOTDONE + Power-On Programming not done + 0x0 + + + DONE + Power-On Programming Done + 0x1 + + + + + IGNRFRMNUM + Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + 15 + 15 + + + DISABLED + Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in which they are intended to be transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is disabled. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediately as the packets are ready.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is enabled. + 0x1 + + + + + NAKONBBLE + NAK on Babble Error (NakOnBble) + 16 + 16 + + + DISABLED + Disable NAK on Babble Error + 0x0 + + + ENABLED + NAK on Babble Error + 0x1 + + + + + DEEPSLEEPBESLREJECT + DeepSleepBESLReject + 18 + 18 + + + DISABLED + Deep Sleep BESL Reject feature is disabled + 0x0 + + + ENABLED + Deep Sleep BESL Reject feature is enabled + 0x1 + + + + + SERVINT + Service Interval based scheduling for Isochronous IN Endpoints + 19 + 19 + + + DISABLED + The controller behavior depends on DCTL.IgnrFrmNum field. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the service interval. + 0x1 + + + + + UTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface. + 30 + 30 + + + DISABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW (1'b0)on soft disconnect. + 0x0 + + + ENABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft disconnect. + 0x1 + + + + + UTMITERMSELCORRDIS + Disable the correction of TermSel on UTMI Interface. + 31 + 31 + + + DISABLED + Valid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x0 + + + ENABLED + Invalid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x1 + + + + + + + DSTS + Device Status Register + 0x808 + read-write + 0x00000002 + 0x20 + + + SUSPSTS + Suspend Status (SuspSts) + 0 + 0 + read-only + + + INACTIVE + No suspend state + 0x0 + + + ACTIVE + Suspend state + 0x1 + + + + + ENUMSPD + Enumerated Speed (EnumSpd) + 1 + 2 + read-only + + + HS3060 + High speed (PHY clock is running at 30 or 60 MHz) + 0x0 + + + FS3060 + Full speed (PHY clock is running at 30 or 60 MHz) + 0x1 + + + LS6 + Low speed (PHY clock is running at 6 MHz) + 0x2 + + + FS48 + Full speed (PHY clock is running at 48 MHz) + 0x3 + + + + + ERRTICERR + Erratic Error (ErrticErr) + 3 + 3 + read-only + + + INACTIVE + No Erratic Error + 0x0 + + + ACTIVE + Erratic Error + 0x1 + + + + + SOFFN + Frame or Microframe Number of the Received SOF (SOFFN) + 8 + 21 + read-only + + + DEVLNSTS + Device Line Status (DevLnSts) + 22 + 23 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error Mask (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + TIMEOUTMSK + Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + 3 + 3 + + + MASK + Mask Timeout Condition Interrupt + 0x0 + + + NOMASK + No Timeout Condition Interrupt Mask + 0x1 + + + + + INTKNTXFEMPMSK + IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + 4 + 4 + + + MASK + Mask IN Token Received When TxFIFO Empty Interrupt + 0x0 + + + NOMASK + No IN Token Received When TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMISMSK + IN Token received with EP Mismatch Mask (INTknEPMisMsk) + 5 + 5 + + + MASK + Mask IN Token received with EP Mismatch Interrupt + 0x0 + + + NOMASK + No Mask IN Token received with EP Mismatch Interrupt + 0x1 + + + + + INEPNAKEFFMSK + IN Endpoint NAK Effective Mask (INEPNakEffMsk) + 6 + 6 + + + MASK + Mask IN Endpoint NAK Effective Interrupt + 0x0 + + + NOMASK + No IN Endpoint NAK Effective Interrupt Mask + 0x1 + + + + + TXFIFOUNDRNMSK + Fifo Underrun Mask (TxfifoUndrnMsk) + 8 + 8 + + + MASK + Mask Fifo Underrun Interrupt + 0x0 + + + NOMASK + No Fifo Underrun Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No Mask NAK Interrupt + 0x1 + + + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + SETUPMSK + SETUP Phase Done Mask (SetUPMsk) + 3 + 3 + + + MASK + Mask SETUP Phase Done Interrupt + 0x0 + + + NOMASK + No SETUP Phase Done Interrupt Mask + 0x1 + + + + + OUTTKNEPDISMSK + OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + 4 + 4 + + + MASK + Mask OUT Token Received when Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No OUT Token Received when Endpoint Disabled Interrupt Mask + 0x1 + + + + + STSPHSERCVDMSK + Status Phase Received Mask (StsPhseRcvdMsk) + 5 + 5 + + + MASK + Status Phase Received Mask + 0x0 + + + NOMASK + No Status Phase Received Mask + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + 6 + 6 + + + MASK + Mask Back-to-Back SETUP Packets Received Interrupt + 0x0 + + + NOMASK + No Back-to-Back SETUP Packets Received Interrupt Mask + 0x1 + + + + + OUTPKTERRMSK + OUT Packet Error Mask (OutPktErrMsk) + 8 + 8 + + + MASK + Mask OUT Packet Error Interrupt + 0x0 + + + NOMASK + No OUT Packet Error Interrupt Mask + 0x1 + + + + + BBLEERRMSK + Babble Error interrupt Mask (BbleErrMsk) + 12 + 12 + + + MASK + Mask Babble Error Interrupt + 0x0 + + + NOMASK + No Babble Error Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No NAK Interrupt Mask + 0x1 + + + + + NYETMSK + NYET interrupt Mask (NYETMsk) + 14 + 14 + + + MASK + Mask NYET Interrupt + 0x0 + + + NOMASK + No NYET Interrupt Mask + 0x1 + + + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + read-write + 0x00000000 + 0x20 + + + INEPINT0 + IN Endpoint 0 Interrupt Bit + 0 + 0 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for IN EP0 + 0x1 + + + + + INEPINT1 + IN Endpoint 1 Interrupt Bit + 1 + 1 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT2 + IN Endpoint 2 Interrupt Bit + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT3 + IN Endpoint 3 Interrupt Bit + 3 + 3 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT4 + IN Endpoint 4 Interrupt Bit + 4 + 4 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT5 + IN Endpoint 5 Interrupt Bit + 5 + 5 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT6 + IN Endpoint 6 Interrupt Bit + 6 + 6 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT7 + IN Endpoint 7 Interrupt Bit + 7 + 7 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT8 + IN Endpoint 8 Interrupt Bit + 8 + 8 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT9 + IN Endpoint 9 Interrupt Bit + 9 + 9 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT10 + IN Endpoint 10 Interrupt Bit + 10 + 10 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT11 + IN Endpoint 11 Interrupt Bit + 11 + 11 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + OUTEPINT0 + OUT Endpoint 0 Interrupt Bit + 16 + 16 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for OUT EP0 + 0x1 + + + + + OUTEPINT1 + OUT Endpoint 1 Interrupt Bit + 17 + 17 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT2 + OUT Endpoint 2 Interrupt Bit + 18 + 18 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT3 + OUT Endpoint 3 Interrupt Bit + 19 + 19 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT4 + OUT Endpoint 4 Interrupt Bit + 20 + 20 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT5 + OUT Endpoint 5 Interrupt Bit + 21 + 21 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT12 + OUT Endpoint 12 Interrupt Bit + 28 + 28 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT13 + OUT Endpoint 13 Interrupt Bit + 29 + 29 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT14 + OUT Endpoint 14 Interrupt Bit + 30 + 30 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT15 + OUT Endpoint 15 Interrupt Bit + 31 + 31 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + read-write + 0x00000000 + 0x20 + + + INEPMSK0 + IN Endpoint 0 Interrupt mask Bit + 0 + 0 + + + MASK + Mask IN Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK1 + IN Endpoint 1 Interrupt mask Bit + 1 + 1 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK2 + IN Endpoint 2 Interrupt mask Bit + 2 + 2 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK3 + IN Endpoint 3 Interrupt mask Bit + 3 + 3 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK4 + IN Endpoint 4 Interrupt mask Bit + 4 + 4 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK5 + IN Endpoint 5 Interrupt mask Bit + 5 + 5 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK6 + IN Endpoint 6 Interrupt mask Bit + 6 + 6 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK7 + IN Endpoint 7 Interrupt mask Bit + 7 + 7 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK8 + IN Endpoint 8 Interrupt mask Bit + 8 + 8 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK9 + IN Endpoint 9 Interrupt mask Bit + 9 + 9 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK10 + IN Endpoint 10 Interrupt mask Bit + 10 + 10 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK11 + IN Endpoint 11 Interrupt mask Bit + 11 + 11 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK0 + OUT Endpoint 0 Interrupt mask Bit + 16 + 16 + + + MASK + Mask OUT Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK1 + OUT Endpoint 1 Interrupt mask Bit + 17 + 17 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK2 + OUT Endpoint 2 Interrupt mask Bit + 18 + 18 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK3 + OUT Endpoint 3 Interrupt mask Bit + 19 + 19 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK4 + OUT Endpoint 4 Interrupt mask Bit + 20 + 20 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK5 + OUT Endpoint 5 Interrupt mask Bit + 21 + 21 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK12 + OUT Endpoint 12 Interrupt mask Bit + 28 + 28 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK13 + OUT Endpoint 13 Interrupt mask Bit + 29 + 29 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK14 + OUT Endpoint 14 Interrupt mask Bit + 30 + 30 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK15 + OUT Endpoint 15 Interrupt mask Bit + 31 + 31 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + read-write + 0x000017D7 + 0x20 + + + DVBUSDIS + Device VBUS Discharge Time (DVBUSDis) + 0 + 15 + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + read-write + 0x000005B8 + 0x20 + + + DVBUSPULSE + Device VBUS Pulsing Time (DVBUSPulse) + 0 + 11 + + + + + DTHRCTL + Device Threshold Control Register + 0x830 + read-write + 0x08100020 + 0x20 + + + NONISOTHREN + Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + 0 + 0 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enable thresholding for non-isochronous IN endpoints + 0x1 + + + + + ISOTHREN + 1 + 1 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enables thresholding for isochronous IN endpoints + 0x1 + + + + + TXTHRLEN + Transmit Threshold Length (TxThrLen) + 2 + 10 + + + AHBTHRRATIO + AHB Threshold Ratio (AHBThrRatio) + 11 + 12 + + + THRESZERO + AHB threshold = MAC threshold + 0x0 + + + THRESONE + AHB threshold = MAC threshold /2 + 0x1 + + + THRESTWO + AHB threshold = MAC threshold /4 + 0x2 + + + THRESTHREE + AHB threshold = MAC threshold /8 + 0x3 + + + + + RXTHREN + Receive Threshold Enable (RxThrEn) + 16 + 16 + + + DISABLED + Disable thresholding + 0x0 + + + ENABLED + Enable thresholding in the receive direction + 0x1 + + + + + RXTHRLEN + Receive Threshold Length (RxThrLen) + 17 + 25 + + + ARBPRKEN + Arbiter Parking Enable (ArbPrkEn) + 27 + 27 + + + DISABLED + Disable DMA arbiter parking + 0x0 + + + ENABLED + Enable DMA arbiter parking for IN endpoints + 0x1 + + + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + read-write + 0x00000000 + 0x20 + + + INEPTXFEMPMSK + IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + 0 + 15 + + + EP0_MASK + Mask IN EP0 Tx FIFO Empty Interrupt + 0x0001 + + + EP1_MASK + Mask IN EP1 Tx FIFO Empty Interrupt + 0x0002 + + + EP2_MASK + Mask IN EP2 Tx FIFO Empty Interrupt + 0x0004 + + + EP3_MASK + Mask IN EP3 Tx FIFO Empty Interrupt + 0x0008 + + + EP4_MASK + Mask IN EP4 Tx FIFO Empty Interrupt + 0x0010 + + + EP5_MASK + Mask IN EP5 Tx FIFO Empty Interrupt + 0x0020 + + + EP6_MASK + Mask IN EP6 Tx FIFO Empty Interrupt + 0x0040 + + + EP7_MASK + Mask IN EP7 Tx FIFO Empty Interrupt + 0x0080 + + + EP8_MASK + Mask IN EP8 Tx FIFO Empty Interrupt + 0x0100 + + + EP9_MASK + Mask IN EP9 Tx FIFO Empty Interrupt + 0x0200 + + + EP10_MASK + Mask IN EP10 Tx FIFO Empty Interrupt + 0x0400 + + + EP11_MASK + Mask IN EP11 Tx FIFO Empty Interrupt + 0x0800 + + + EP12_MASK + Mask IN EP12 Tx FIFO Empty Interrupt + 0x1000 + + + EP13_MASK + Mask IN EP13 Tx FIFO Empty Interrupt + 0x2000 + + + EP14_MASK + Mask IN EP14 Tx FIFO Empty Interrupt + 0x4000 + + + EP15_MASK + Mask IN EP15 Tx FIFO Empty Interrupt + 0x8000 + + + + + + + DIEPCTL0 + Device Control IN Endpoint 0 Control Register + 0x900 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + + + BYTES64 + 64 bytes + 0x0 + + + BYTES32 + 32 bytes + 0x1 + + + BYTES16 + 16 bytes + 0x2 + + + BYTES8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE0 + Control endpoint is always active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Disabled Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT0 + Device IN Endpoint 0 Interrupt Register + 0x908 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Completed Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received when TxFIFO Empty interrupt + 0x0 + + + ACTIVE + IN Token Received when TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No IN Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Fifo Underrun interrupt + 0x0 + + + ACTIVE + Fifo Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ0 + Device IN Endpoint 0 Transfer Size Register + 0x910 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 20 + + + + + DIEPDMA0 + Device IN Endpoint 0 DMA Address Register + 0x914 + read-write + 0x00000000 + 0x20 + + + DMAADDR + DMAAddr + 0 + 31 + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register 0 + 0x918 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL1 + Device Control IN Endpoint Control Register + 0x920 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT1 + Device IN Endpoint Interrupt Register + 0x928 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ1 + Device IN Endpoint Transfer Size Register + 0x930 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA1 + Device IN Endpoint DMA Address Register + 0x934 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS1 + Device IN Endpoint Transmit FIFO Status Register + 0x938 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL2 + Device Control IN Endpoint Control Register + 0x940 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT2 + Device IN Endpoint Interrupt Register + 0x948 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ2 + Device IN Endpoint Transfer Size Register + 0x950 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA2 + Device IN Endpoint DMA Address Register + 0x954 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS2 + Device IN Endpoint Transmit FIFO Status Register + 0x958 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL3 + Device Control IN Endpoint Control Register + 0x960 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT3 + Device IN Endpoint Interrupt Register + 0x968 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ3 + Device IN Endpoint Transfer Size Register + 0x970 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA3 + Device IN Endpoint DMA Address Register + 0x974 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS3 + Device IN Endpoint Transmit FIFO Status Register + 0x978 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL4 + Device Control IN Endpoint Control Register + 0x980 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT4 + Device IN Endpoint Interrupt Register + 0x988 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ4 + Device IN Endpoint Transfer Size Register + 0x990 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA4 + Device IN Endpoint DMA Address Register + 0x994 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS4 + Device IN Endpoint Transmit FIFO Status Register + 0x998 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL5 + Device Control IN Endpoint Control Register + 0x9A0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT5 + Device IN Endpoint Interrupt Register + 0x9A8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ5 + Device IN Endpoint Transfer Size Register + 0x9B0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA5 + Device IN Endpoint DMA Address Register + 0x9B4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS5 + Device IN Endpoint Transmit FIFO Status Register + 0x9B8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL6 + Device Control IN Endpoint Control Register + 0x9C0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT6 + Device IN Endpoint Interrupt Register + 0x9C8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ6 + Device IN Endpoint Transfer Size Register + 0x9D0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA6 + Device IN Endpoint DMA Address Register + 0x9D4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS6 + Device IN Endpoint Transmit FIFO Status Register + 0x9D8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL7 + Device Control IN Endpoint Control Register + 0x9E0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT7 + Device IN Endpoint Interrupt Register + 0x9E8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ7 + Device IN Endpoint Transfer Size Register + 0x9F0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA7 + Device IN Endpoint DMA Address Register + 0x9F4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS7 + Device IN Endpoint Transmit FIFO Status Register + 0x9F8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL8 + Device Control IN Endpoint Control Register + 0xA00 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT8 + Device IN Endpoint Interrupt Register + 0xA08 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ8 + Device IN Endpoint Transfer Size Register + 0xA10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA8 + Device IN Endpoint DMA Address Register + 0xA14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS8 + Device IN Endpoint Transmit FIFO Status Register + 0xA18 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL9 + Device Control IN Endpoint Control Register + 0xA20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT9 + Device IN Endpoint Interrupt Register + 0xA28 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ9 + Device IN Endpoint Transfer Size Register + 0xA30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA9 + Device IN Endpoint DMA Address Register + 0xA34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS9 + Device IN Endpoint Transmit FIFO Status Register + 0xA38 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL10 + Device Control IN Endpoint Control Register + 0xA40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT10 + Device IN Endpoint Interrupt Register + 0xA48 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ10 + Device IN Endpoint Transfer Size Register + 0xA50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA10 + Device IN Endpoint DMA Address Register + 0xA54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS10 + Device IN Endpoint Transmit FIFO Status Register + 0xA58 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL11 + Device Control IN Endpoint Control Register + 0xA60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT11 + Device IN Endpoint Interrupt Register + 0xA68 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ11 + Device IN Endpoint Transfer Size Register + 0xA70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA11 + Device IN Endpoint DMA Address Register + 0xA74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS11 + Device IN Endpoint Transmit FIFO Status Register + 0xA78 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint 0 Control Register + 0xB00 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + read-only + + + BYTE64 + 64 bytes + 0x0 + + + BYTE32 + 32 bytes + 0x1 + + + BYTE16 + 16 bytes + 0x2 + + + BYTE8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE + USB Active Endpoint 0 + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + read-only + + + INACTIVE + No Endpoint disable + 0x0 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT0 + Device OUT Endpoint 0 Interrupt Register + 0xB08 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ0 + Device OUT Endpoint 0 Transfer Size Register + 0xB10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 19 + + + SUPCNT + SETUP Packet Count (SUPCnt) + 29 + 30 + + + ONEPACKET + 1 packet + 0x1 + + + TWOPACKET + 2 packets + 0x2 + + + THREEPACKET + 3 packets + 0x3 + + + + + + + DOEPDMA0 + Device OUT Endpoint 0 DMA Address Register + 0xB14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL1 + Device Control OUT Endpoint Control Register + 0xB20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT1 + Device OUT Endpoint Interrupt Register + 0xB28 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ1 + Device OUT Endpoint Transfer Size Register + 0xB30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA1 + Device OUT Endpoint DMA Address Register + 0xB34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL2 + Device Control OUT Endpoint Control Register + 0xB40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT2 + Device OUT Endpoint Interrupt Register + 0xB48 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ2 + Device OUT Endpoint Transfer Size Register + 0xB50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA2 + Device OUT Endpoint DMA Address Register + 0xB54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL3 + Device Control OUT Endpoint Control Register + 0xB60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT3 + Device OUT Endpoint Interrupt Register + 0xB68 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ3 + Device OUT Endpoint Transfer Size Register + 0xB70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA3 + Device OUT Endpoint DMA Address Register + 0xB74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL4 + Device Control OUT Endpoint Control Register + 0xB80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT4 + Device OUT Endpoint Interrupt Register + 0xB88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ4 + Device OUT Endpoint Transfer Size Register + 0xB90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA4 + Device OUT Endpoint DMA Address Register + 0xB94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL5 + Device Control OUT Endpoint Control Register + 0xBA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT5 + Device OUT Endpoint Interrupt Register + 0xBA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ5 + Device OUT Endpoint Transfer Size Register + 0xBB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA5 + Device OUT Endpoint DMA Address Register + 0xBB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL12 + Device Control OUT Endpoint Control Register + 0xC80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT12 + Device OUT Endpoint Interrupt Register + 0xC88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ12 + Device OUT Endpoint Transfer Size Register + 0xC90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA12 + Device OUT Endpoint DMA Address Register + 0xC94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL13 + Device Control OUT Endpoint Control Register + 0xCA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT13 + Device OUT Endpoint Interrupt Register + 0xCA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ13 + Device OUT Endpoint Transfer Size Register + 0xCB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA13 + Device OUT Endpoint DMA Address Register + 0xCB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL14 + Device Control OUT Endpoint Control Register + 0xCC0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT14 + Device OUT Endpoint Interrupt Register + 0xCC8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ14 + Device OUT Endpoint Transfer Size Register + 0xCD0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA14 + Device OUT Endpoint DMA Address Register + 0xCD4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL15 + Device Control OUT Endpoint Control Register + 0xCE0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT15 + Device OUT Endpoint Interrupt Register + 0xCE8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ15 + Device OUT Endpoint Transfer Size Register + 0xCF0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA15 + Device OUT Endpoint DMA Address Register + 0xCF4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + read-write + 0x880A0000 + 0x20 + + + STOPPCLK + Stop Pclk (StopPclk) + 0 + 0 + + + DISABLED + Disable Stop Pclk + 0x0 + + + ENABLED + Enable Stop Pclk + 0x1 + + + + + GATEHCLK + Gate Hclk (GateHclk) + 1 + 1 + + + DISABLED + Clears this bit when the USB is resumed or a new session starts + 0x0 + + + ENABLED + Sets this bit to gate hclk to modules when the USB is suspended or the session is not valid + 0x1 + + + + + RSTPDWNMODULE + Reset Power-Down Modules (RstPdwnModule) + 3 + 3 + + + ON + Power is turned on + 0x0 + + + OFF + Power is turned off + 0x1 + + + + + ENBLL1GATING + Enable Sleep Clock Gating + 5 + 5 + + + DISABLED + The PHY clock is not gated in Sleep state + 0x0 + + + ENABLED + The Core internal clock gating is enabled in Sleep state + 0x1 + + + + + PHYSLEEP + PHY In Sleep + 6 + 6 + read-only + + + INACTIVE + Phy not in Sleep state + 0x0 + + + ACTIVE + Phy in Sleep state + 0x1 + + + + + L1SUSPENDED + L1 Deep Sleep + 7 + 7 + read-only + + + INACTIVE + Non Deep Sleep + 0x0 + + + ACTIVE + Deep Sleep + 0x1 + + + + + RESTOREMODE + Restore Mode (RestoreMode) + 9 + 9 + + + DISABLED + In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this bit indicates Device-initiated Remote Wakeup + 0x0 + + + ENABLED + In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this bit indicates Host-initiated Resume and Reset + 0x1 + + + + + ESSREGRESTORED + Essential Register Values Restored (EssRegRestored) + 13 + 13 + write-only + + + NOT_RESTORED + Register values of essential registers are not restored + 0x0 + + + RESTORED + Register values of essential registers have been restored + 0x1 + + + + + RESTOREVALUE + Restore Value (RestoreValue) + 14 + 31 + + + + + GSTARFXDIS + Global STAR Fix Disable Register + 0xF00 + read-write + 0x00002200 + 0x20 + + + HOSTIGNORESRMTWKUPDIS + Disable the STAR fix added for Device controller to go back to low power mode when Host ignores Remote wakeup + 0 + 0 + + + ENABLE_FIX + Device controller goes back into SUSPENDED state when host ignores Remote Wakeup + 0x0 + + + DISABLE_FIX + Device controller waits indefinitely without entering SUSPENDED state when host ignores the Remote Wakeup + 0x1 + + + + + RESUMEFRMCHKBUSDIS + Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after the 50us pull-up delay ends + 1 + 1 + + + ENABLE_FIX + Device controller detects line K and resumes + 0x0 + + + DISABLE_FIX + Device controller does not detect line K and resume + 0x1 + + + + + IGNORECTLOUTDATA0DIS + Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data Phase and Control Status OUT Phase + 2 + 2 + + + ENABLE_FIX + Transaction Error reported when host sends DATA0 PID + 0x0 + + + DISABLE_FIX + Transaction Error not reported when host sends DATA0 PID + 0x1 + + + + + SSPLITSTALLNYETERRDIS + Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET + 3 + 3 + + + ENABLE_FIX + Transaction Error reported when device sends STALL/NYET for SSPLIT + 0x0 + + + DISABLE_FIX + Transaction Error not reported when device sends STALL/NYET for SSPLIT + 0x1 + + + + + ACCEPTISOCSPLITDATA1DIS + Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC Split transfers + 4 + 4 + + + ENABLE_FIX + Transaction Error not reported when device sends DATA1 PID for ISOC Split + 0x0 + + + DISABLE_FIX + Transaction Error reported when device sends DATA1 PID for ISOC Split + 0x1 + + + + + HANDLEFAULTYCABLEDIS + Disable the STAR fix added for Host controller to handle Faulty cable scenarios + 5 + 5 + + + ENABLE_FIX + Fix for handling faulty cable enabled + 0x0 + + + DISABLE_FIX + Fix for handling faulty cable disabled + 0x1 + + + + + LSIPGINCRDIS + Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit times + 6 + 6 + + + ENABLE_FIX + Host LS mode IPG is 3 LS bit times + 0x0 + + + DISABLE_FIX + Host LS mode IPG is 2 LS bit times + 0x1 + + + + + FSDISCIDLEDIS + Disable the STAR fix added for Device controller to transition to IDLE state during FS device disconnect + 7 + 7 + + + ENABLE_FIX + Device controller transitions to IDLE state during FS device disconnect + 0x0 + + + DISABLE_FIX + Device controller does not transition to IDLE state during FS device disconnect + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEDIS + Disable the STAR fix added for Device controller to not start Remote Wakeup signalling when USB resume has already started + 8 + 8 + + + ENABLE_FIX + Device controller does not start remote wakeup signalling when host resume has already started + 0x0 + + + DISABLE_FIX + Device controller is allowed to start remote wakeup signalling when host resume has already started + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEHIBDIS + Disable the STAR fix added for Device controller to not hang when Remote Wakeup signalling clashes with Host resume + 9 + 9 + + + ENABLE_FIX + Device controller does not hang when remote wakeup signalling clashes with host resume during Hibernation exit + 0x0 + + + DISABLE_FIX + Device controller hangs when remote wakeup signalling clashes with host resume during Hibernation exit + 0x1 + + + + + LSIPGCHKAFTERNAKSTALLFORINDIS + Disable the STAR fix added for Host controller to wait for IPG duration to send next token after receiving NAK/STALL for previous IN token with FS/LS device + 10 + 10 + + + ENABLE_FIX + Host controller checks IPG after NAK/STALL for IN token + 0x0 + + + DISABLE_FIX + Host controller does not check IPG after NAK/STALL for IN token + 0x1 + + + + + PHYIOPXCVRSELTXVLDCORRDIS + Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode + 11 + 11 + + + ENABLE_FIX + Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect switching + 0x0 + + + DISABLE_FIX + Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect switching + 0x1 + + + + + ULPIXCVRSELSWITCHCORRDIS + Disable the STAR fix added for Host controller to increase the preamble transceiver select switch delay to accommodate time taken for ULPI function control write + 12 + 12 + + + ENABLE_FIX + Host controller waits for previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x0 + + + DISABLE_FIX + Host controller does not wait for the previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x1 + + + + + XACTERRDATA0CTRLSTSINDIS + Disable the STAR fix added for Host controller to report transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 13 + 13 + + + ENABLE_FIX + Host controller reports transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x0 + + + DISABLE_FIX + Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x1 + + + + + HOSTUTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. + 16 + 16 + + + ENABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1'b0) + 0x0 + + + DISABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxValid to go LOW (1'b0) during SOF transmission + 0x1 + + + + + OPMODEXCVRSELCHIRPENCORRDIS + Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when reset is detected in suspend state. + 17 + 17 + + + ENABLE_FIX + Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x0 + + + DISABLE_FIX + Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x1 + + + + + TXVALIDDEASSERTIONCORRDIS + Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft disconnect is done. + 18 + 18 + + + ENABLE_FIX + Txvalid is deasserted during soft disconnect after receiving Txready from the PHY + 0x0 + + + DISABLE_FIX + Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY + 0x1 + + + + + HOSTNOXFERAFTERPRTDISFIXDIS + Disable the STAR fix added for correcting Host behavior when port is disabled. + 19 + 19 + + + ENABLE_FIX + Txvalid is not asserted when port is disabled + 0x0 + + + DISABLE_FIX + Txvalid can be asserted when port is disabled + 0x1 + + + + + + + 16 + 0x1000 + DWCOTGDFIFO[%s] + Unspecified + USBHSCORE_DWCOTGDFIFO + read-write + 0x1000 + + 0x400 + 0x4 + DATA[%s] + Description collection: Data FIFO Access Register Map 0 + 0x0000 + read-write + 0x00000000 + 0x20 + + + + DWCOTGDFIFODIRECTACCESS + Unspecified + USBHSCORE_DWCOTGDFIFODIRECTACCESS + read-write + 0x20000 + + 0x8000 + 0x4 + DATA[%s] + Description collection: Data FIFO Direct Access Register Map + 0x00000 + read-write + 0x00000000 + 0x20 + + + + + + GLOBAL_USBHSCORE0_S + USBHSCORE 1 + 0x2F700000 + GLOBAL_USBHSCORE0_NS + + + + + GLOBAL_I3CCORE120_NS + I3CCORE 0 + 0x2FBE0000 + I3CCORE + + + + 0 + 0x1000 + registers + + I3CCORE + 0x20 + + + CORE + Unspecified + I3CCORE_CORE + read-write + 0x000 + + DEVICECTRL + DWC_mipi_i3c control Register + 0x000 + read-write + 0x00000000 + 0x20 + + + IBAINCLUDE + I3C Broadcast Address include + 0 + 0 + + + NOT_INCLUDED + Unspecified + 0x0 + + + INCLUDED + Unspecified + 0x1 + + + + + I2CSLAVEPRESENT + I2C Slave Present + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + HOTJOINCTRL + Hot-Join ACK/NACK Control + 8 + 8 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + IDLECNTMULTPLIER + Idle Count Multiplier + 24 + 25 + + + MultiplyBy1 + Unspecified + 0x0 + + + MultiplyBy2 + Unspecified + 0x1 + + + MultiplyBy4 + Unspecified + 0x2 + + + MultiplyBy8 + Unspecified + 0x3 + + + + + ADAPTIVEI2CI3C + This field is used in Slave mode of operation. + 27 + 27 + + + DMAENABLE + DMA Handshake Interface Enable + 28 + 28 + + + DISABLE + The DMA handshake control has no significance. + 0x0 + + + ENABLE + Enables the DMA handshake control to interact with external DMA. + 0x1 + + + + + ABORT + DWC_mipi_i3c Abort + 29 + 29 + + + RESUME + DWC_mipi_i3c Resume + 30 + 30 + + + ENABLE + Controls whether or not DWC_mipi_i3c is enabled. + 31 + 31 + + + DISABLE + Disables the DWC_mipi_i3c controller + 0x0 + + + ENABLE + Enables the DWC_mipi_i3c controller. + 0x1 + + + + + + + DEVICEADDR + In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit. + 0x004 + read-write + 0x80000000 + 0x20 + + + STATICADDR + Device Static Address. + 0 + 6 + + + STATICADDRVALID + Static Address Valid. + 15 + 15 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + DYNAMICADDR + Device Dynamic Address. + 16 + 22 + + + DYNAMICADDRVALID + Dynamic Address Valid + 31 + 31 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + + + HWCAPABILITY + Hardware Capability register + 0x008 + read-write + 0x000E187B + 0x20 + + + DEVICEROLECONFIG + Reflects the IC_DEVICE_ROLE Configurable Parameter. + 0 + 2 + read-only + + + MASTER + Master Only + 0x1 + + + PMASTERSLAVE + Programmable Master-Slave + 0x2 + + + SECONDARYMASTER + Secondary Master + 0x3 + + + SLAVE + Slave Only + 0x4 + + + + + HDRDDREN + Reflects the IC_SPEED_HDR_DDR Configurable Parameter. + 3 + 3 + read-only + + + NOTSUPPORTED + HDR-DDR not supported + 0x0 + + + SUPPORTED + HDR-DDR supported + 0x1 + + + + + HDRTSEN + Reflects the IC_SPEED_HDR_TS Configurable Parameter. + 4 + 4 + read-only + + + NOTSUPPORTED + HDR-TS not supported + 0x0 + + + SUPPORTED + HDR-TS supported + 0x1 + + + + + CLOCKPERIOD + Reflects the IC_CLK_PERIOD Configurable Parameter + 5 + 10 + read-only + + + HDRTXCLOCKPERIOD + Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. + 11 + 16 + read-only + + + DMAEN + Reflects the IC_HAS_DMA Configurable Parameter. + 17 + 17 + read-only + + + SLVHJCAP + Reflects the IC_SLV_HJ Configurable Parameter. + 18 + 18 + read-only + + + SLVIBICAP + Reflects the IC_SLV_IBI Configurable Parameter. + 19 + 19 + read-only + + + + + COMMANDQUEUEPORT + Command Queue Port. + 0x00C + read-write + 0x00000000 + 0x20 + + + COMMAND + 32 bit command + 0 + 31 + write-only + + + + + RESPONSEQUEUEPORT + Response Queue Port + 0x010 + read-write + 0x00000000 + 0x20 + + + RESPONSE + 32 bit Response + 0 + 31 + read-only + + + + + RXDATAPORT + Receive Data Port Register + 0x014 + read-write + 0x00000000 + 0x20 + + + RXDATAPORT + Receive Data Port. + 0 + 31 + read-only + + + + + TXDATAPORT + Transmit Data Port Register + 0x014 + read-write + 0x00000000 + RXDATAPORT + 0x20 + + + TXDATAPORT + Transmit Data Port + 0 + 31 + write-only + + + + + IBIQUEUEDATA + In-Band Interrupt Queue Data Register + 0x018 + read-write + 0x00000000 + 0x20 + + + IBIDATA + In-Band Interrupt Data + 0 + 31 + read-only + + + + + IBIQUEUESTATUS + In-Band Interrupt Queue Status Register + 0x018 + read-write + 0x00000000 + IBIQUEUEDATA + 0x20 + + + DATALENGTH + In-Band Interrupt data length. + 0 + 7 + read-only + + + IBIID + IBI Identifier. + 8 + 15 + read-only + + + IBIACK + The acknowledge bit of the IBI Received Status (IBISTS) bitfield. + 31 + 31 + read-only + + + ACK + Responded with ACK + 0x0 + + + NACK + Responded with NACK + 0x1 + + + + + + + QUEUETHLDCTRL + Queue Threshold Control Register + 0x01C + read-write + 0x01000101 + 0x20 + + + CMDEMPTYBUFTHLD + Command Buffer Empty Threshold Value. + 0 + 7 + + + RESPBUFTHLD + Response Buffer Threshold Value. + 8 + 15 + + + IBISTATUSTHLD + In-Band Interrupt Status Threshold Value. + 24 + 31 + + + + + DATABUFFERTHLDCTRL + Data Buffer Threshold Control Register + 0x020 + read-write + 0x01010101 + 0x20 + + + TXEMPTYBUFTHLD + Transmit Buffer Threshold Value + 0 + 2 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD14 + Unspecified + 0x1 + + + THRESHOLD18 + Unspecified + 0x2 + + + THRESHOLD116 + Unspecified + 0x3 + + + THRESHOLD132 + Unspecified + 0x4 + + + THRESHOLD164 + Unspecified + 0x5 + + + + + RXBUFTHLD + Receive Buffer Threshold Value + 8 + 10 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + TXSTARTTHLD + Transfer Start Threshold Value + 16 + 18 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + RXSTARTTHLD + Receive Start Threshold Value + 24 + 26 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + + + IBIQUEUECTRL + This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked). + 0x024 + read-write + 0x00000000 + 0x20 + + + NOTIFYHJREJECTED + Notify Rejected Hot-Join Control. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + NOTIFYMRREJECTED + Notify Rejected Master Request Control. + 1 + 1 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x1 + + + + + NOTIFYSIRREJECTED + Notify Rejected Slave Interrupt Request Control. + 3 + 3 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x1 + + + + + + + IBIMRREQREJECT + IBI Master Request Rejection Control Register. + 0x02C + read-write + 0x00000000 + 0x20 + + + MRREQREJECT + In-band Master Request Reject. + 0 + 31 + + + ACK + ACK Master Request. + 0x00000000 + + + NACK + NACK and send Directed DISEC CCC to disable the interrupting slave. + 0x00000001 + + + + + + + IBISIRREQREJECT + IBI SIR Request Rejection Control + 0x030 + read-write + 0x00000000 + 0x20 + + + SIRREQREJECT + In-band Slave Interrupt Request Reject + 0 + 31 + + + ACK + ACK the SIR Request. + 0x00000000 + + + NACK + NACK and send directed auto disable CCC. + 0x00000001 + + + + + + + RESETCTRL + This Register is used for general software reset and for individual buffer reset. + 0x034 + read-write + 0x00000000 + 0x20 + + + SOFTRST + Core Software Reset. + 0 + 0 + + + CMDQUEUERST + Command Queue Software Reset + 1 + 1 + + + RESPQUEUERST + Response Queue Software Reset + 2 + 2 + + + TXFIFORST + Transmit Buffer Software Reset + 3 + 3 + + + RXFIFORST + Receive Buffer Software Reset. + 4 + 4 + + + IBIQUEUERST + IBI Queue Software Reset. + 5 + 5 + + + BUSRESETTYPE + Bus Reset type + 29 + 30 + + + EXIT + Exit Pattern. + 0x0 + + + SCL_LOW_RESET + SCL_LOW_RESET Pattern. + 0x3 + + + + + BUSRESET + Bus Reset. + 31 + 31 + + + + + SLVEVENTSTATUS + This register indicates the status/values of some events/controls that are relavant to slave mode of operation. + 0x038 + read-write + 0x0000000B + 0x20 + + + SIREN + Slave Interrupt Request Enable. + 0 + 0 + read-only + + + MREN + Master Request Enable. + 1 + 1 + read-only + + + HJEN + Hot-Join Interrupt Enable + 3 + 3 + + + ACTIVITYSTATE + Activity State Status. + 4 + 5 + read-only + + + ENTAS0 + Unspecified + 0x0 + + + ENTAS1 + Unspecified + 0x1 + + + ENTAS2 + Unspecified + 0x2 + + + ENTAS3 + Unspecified + 0x3 + + + + + MRLUPDATED + MRL Updated Status. + 6 + 6 + + + MWLUPDATED + MWL Updated Status. + 7 + 7 + + + + + INTRSTATUS + Interrupt Status Register + 0x03C + read-write + 0x00000000 + 0x20 + + + TXTHLDSTS + Transmit Buffer Threshold Status + 0 + 0 + read-only + + + RXTHLDSTS + Receive Buffer Threshold Status. + 1 + 1 + read-only + + + IBITHLDSTS + IBI Buffer Threshold Status. + 2 + 2 + read-only + + + CMDQUEUEREADYSTS + Command Queue Ready. + 3 + 3 + read-only + + + RESPREADYSTS + Response Queue Ready Status. + 4 + 4 + read-only + + + TRANSFERABORTSTS + Transfer Abort Status. + 5 + 5 + + + CCCUPDATEDSTS + CCC Table Updated Status. + 6 + 6 + + + DYNADDRASSGNSTS + Dynamic Address Assigned Status. + 8 + 8 + + + TRANSFERERRSTS + Transfer Error Status. + 9 + 9 + + + DEFSLVSTS + Define Slave CCC Received Status. + 10 + 10 + + + READREQRECVSTS + Read Request Received. + 11 + 11 + + + IBIUPDATEDSTS + IBI status is updated. + 12 + 12 + + + BUSOWNERUPDATEDSTS + This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa. + 13 + 13 + + + BUSRESETDONESTS + Bus Reset Pattern Generation Done Status. + 15 + 15 + + + + + INTRSTATUSEN + Interrupt Status Enable Register. + 0x040 + read-write + 0x00000000 + 0x20 + + + TXTHLDSTSEN + Transmit Buffer Threshold Status Enable. + 0 + 0 + + + RXTHLDSTSEN + Receive Buffer Threshold Status Enable + 1 + 1 + + + IBITHLDSTSEN + IBI Buffer Threshold Status Enable. + 2 + 2 + + + CMDQUEUEREADYSTSEN + Command Queue Ready Status Enable + 3 + 3 + + + RESPREADYSTSEN + Response Queue Ready Status Enable + 4 + 4 + + + TRANSFERABORTSTSEN + Transfer Abort Status Enable. + 5 + 5 + + + CCCUPDATEDSTSEN + CCC Table Updated Status Enable. + 6 + 6 + + + DYNADDRASSGNSTSEN + Dynamic Address Assigned Status Enable + 8 + 8 + + + TRANSFERERRSTSEN + Transfer Error Status Enable + 9 + 9 + + + DEFSLVSTSEN + Define Slave CCC Received Status Enable + 10 + 10 + + + READREQRECVSTSEN + Read Request Received Status Enable + 11 + 11 + + + IBIUPDATEDSTSEN + IBI Updated Status Enable + 12 + 12 + + + BUSOWNERUPDATEDSTSEN + Bus owner Updated Status Enable + 13 + 13 + + + BUSRESETDONESTSEN + Bus Reset Pattern Generation Done Status Enable. + 15 + 15 + + + + + INTRSIGNALEN + Interrupt Signal Enable Register + 0x044 + read-write + 0x00000000 + 0x20 + + + TXTHLDSIGNALEN + Transmit Buffer Threshold Signal Enable + 0 + 0 + + + RXTHLDSIGNALEN + Receive Buffer Threshold Signal Enable + 1 + 1 + + + IBITHLDSIGNALEN + IBI Buffer Threshold Signal Enable + 2 + 2 + + + CMDQUEUEREADYSIGNALEN + Command Queue Ready Signal Enable + 3 + 3 + + + RESPREADYSIGNALEN + Response Queue Ready Signal Enable + 4 + 4 + + + TRANSFERABORTSIGNALEN + Transfer Abort Signal Enable + 5 + 5 + + + CCCUPDATEDSIGNALEN + CCC Table Updated Signal Enable + 6 + 6 + + + DYNADDRASSGNSIGNALEN + Dynamic Address Assigned Signal Enable + 8 + 8 + + + TRANSFERERRSIGNALEN + Transfer Error Signal Enable + 9 + 9 + + + DEFSLVSIGNALEN + Define Slave CCC Received Signal Enable + 10 + 10 + + + READREQRECVSIGNALEN + Read Request Received Signal Enable + 11 + 11 + + + IBIUPDATEDSIGNALEN + IBI Updated Signal Enable + 12 + 12 + + + BUSOWNERUPDATEDSIGNALEN + Bus owner Updated Signal Enable + 13 + 13 + + + BUSRESETDONESIGNALEN + Bus Reset Pattern Generation Done Signal Enable. + 15 + 15 + + + + + INTRFORCE + Interrupt Force Enable Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TXTHLDFORCEEN + Transmit Buffer Threshold Force Enable + 0 + 0 + write-only + + + RXTHLDFORCEEN + Receive Buffer Threshold Force Enable + 1 + 1 + write-only + + + IBITHLDFORCEEN + IBI Buffer Threshold Force Enable + 2 + 2 + write-only + + + CMDQUEUEREADYFORCEEN + Command Queue Ready Force Enable + 3 + 3 + write-only + + + RESPREADYFORCEEN + Response Queue Ready Force Enable + 4 + 4 + write-only + + + TRANSFERABORTFORCEEN + Transfer Abort Force Enable + 5 + 5 + write-only + + + CCCUPDATEDFORCEEN + CCC Table Updated Force Enable + 6 + 6 + write-only + + + DYNADDRASSGNFORCEEN + Dynamic Address Assigned Force Enable + 8 + 8 + write-only + + + TRANSFERERRFORCEEN + Transfer Error Force Enable + 9 + 9 + write-only + + + DEFSLVFORCEEN + Define Slave CCC Received Force Enable + 10 + 10 + write-only + + + READREQFORCEEN + Read Request Received Force Enable + 11 + 11 + write-only + + + IBIUPDATEDFORCEEN + IBI Updated Force Enable + 12 + 12 + write-only + + + BUSOWNERUPDATEDFORCEEN + Bus owner Updated Force Enable + 13 + 13 + write-only + + + BUSRESETDONEFORCEEN + Bus Reset Pattern Generation Done Force Enable. + 15 + 15 + write-only + + + + + QUEUESTATUSLEVEL + Queue Status Level Register. + 0x04C + read-write + 0x00000010 + 0x20 + + + CMDQUEUEEMPTYLOC + Command Queue Empty Locations. + 0 + 7 + read-only + + + RESPBUFBLR + Response Buffer Level Value. + 8 + 15 + read-only + + + IBIBUFBLR + IBI Buffer Level Value. + 16 + 23 + read-only + + + IBISTSCNT + IBI Buffer Status Count. + 24 + 28 + read-only + + + + + DATABUFFERSTATUSLEVEL + Data Buffer Status Level Register. + 0x050 + read-write + 0x00000040 + 0x20 + + + TXBUFEMPTYLOC + Transmit Buffer Empty Level Value. + 0 + 7 + read-only + + + RXBUFBLR + Receive Buffer Level Value. + 16 + 23 + read-only + + + + + PRESENTSTATEM + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Master). + 0x054 + read-write + 0x10000003 + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + IDLE + Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + BCCCWTRANSFER + Broadcast CCC Write Transfer. + 0x01 + + + DCCCWTRANSFER + Directed CCC Write Transfer. + 0x02 + + + DCCCRTRANSFER + Directed CCC Read Transfer. + 0x03 + + + ENTDAATRANSFER + ENTDAA Address Assignment Transfer. + 0x04 + + + SETDASATRANSFER + SETDASA Address Assignment Transfer. + 0x05 + + + SDRWTRANSFER + Private I3C SDR Write Transfer. + 0x06 + + + SDRRTRANSFER + Private I3C SDR Read Transfer. + 0x07 + + + SDRWTRANSFERI2C + Private I2C SDR Write Transfer. + 0x08 + + + SDRRTRANSFERI2C + Private I2C SDR Read Transfer. + 0x09 + + + TSWTRANSFER + Private HDR Ternary Symbol(TS) Write Transfer. + 0x0A + + + TSRTRANSFER + Private HDR Ternary Symbol(TS) Read Transfer. + 0x0B + + + DDRWTRANSFER + Private HDR Double-Data Rate(DDR) Write Transfer. + 0x0C + + + DDRRTRANSFER + Private HDR Double-Data Rate(DDR) Read Transfer. + 0x0D + + + IBITRANSFER + Servicing In-Band Interrupt Transfer. + 0x0E + + + HALT + Halt state. Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register. + 0x0F + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + IDLE + Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + START + START Generation State. + 0x01 + + + RESTART + RESTART Generation State. + 0x02 + + + STOP + STOP Genration State. + 0x03 + + + STARTH + START Hold Generation for the Slave Initiated START State. + 0x04 + + + BWADDRGEN + Broadcast Write Address Header(7h7E,W) Generation State. + 0x05 + + + BRADDRGEN + Broadcast Read Address Header(7h7E,R) Generation State. + 0x06 + + + DAA + Dynamic Address Assignment State. + 0x07 + + + ADDRGEN + Slave Address Generation State. + 0x08 + + + CCCBYTEGEN + CCC Byte Generation State. + 0x0B + + + HDRCMDGEN + HDR Command Generation State. + 0x0C + + + WTRANSFER + Write Data Transfer State. + 0x0D + + + RTRANSFER + Read Data Transfer State. + 0x0E + + + RIBI + In-Band Interrupt(SIR) Read Data State. + 0x0F + + + IBIAUTODISABLE + In-Band Interrupt Auto-Disable State + 0x10 + + + DDRCRCGEN + HDR-DDR CRC Data Generation/Receive State. + 0x11 + + + CLKEXTEND + Clock Extension State. + 0x12 + + + HALT + Halt State. + 0x13 + + + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + PRESENTSTATES + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Slave). + 0x054 + read-write + 0x10000003 + PRESENTSTATEM + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + SLAVEIDLE + Controller is in Idle state. + 0x00 + + + SLAVEHOTJOIN + Hot-Join transfer state. + 0x01 + + + SLAVEIBITRANSFER + IBI transfer state. + 0x02 + + + SLAVEWTRANSFER + Master write transfer ongoing. + 0x03 + + + SLAVERPREFETCH + Read data prefetch state. + 0x04 + + + SLAVERTRANSFER + Master read transfer ongoing. + 0x05 + + + SLAVEHALT + Slave controller in Halt State waiting for resume from application. + 0x06 + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + CCCDEVICESTATUS + Device Operating Status Register. + 0x058 + read-write + 0x00000000 + 0x20 + + + PENDINGINTR + Pending Interrupt + 0 + 3 + read-only + + + PROTOCOLERR + Protocol Error + 5 + 5 + read-only + + + ACTIVITYMODE + Activity Mode + 6 + 7 + read-only + + + UNDERFLOWERR + Underflow error + 8 + 8 + read-only + + + SLAVEBUSY + Slave Busy + 9 + 9 + read-only + + + OVERFLOWERR + Overflow Error + 10 + 10 + read-only + + + DATANOTREADY + Data not ready + 11 + 11 + read-only + + + BUFFERNOTAVAIL + Buffer not available + 12 + 12 + read-only + + + FRAMEERROR + Frame Error + 13 + 13 + read-only + + + + + DEVICEADDRTABLEPOINTER + Pointer for Device Address Table + 0x05C + read-write + 0x000A02C0 + 0x20 + + + PDEVADDRTABLESTARTADDR + Start Address of Device Address Table. + 0 + 15 + read-only + + + DEVADDRTABLEDEPTH + Depth of Device Address Table + 16 + 31 + read-only + + + + + DEVCHARTABLEPOINTER + Pointer for Device Characteristics Table + 0x060 + read-write + 0x00028200 + 0x20 + + + PDEVCHARTABLESTARTADDR + Start Address of Device Characteristics Table. + 0 + 11 + read-only + + + DEVCHARTABLEDEPTH + Depth of Device Characteristics Table + 12 + 18 + read-only + + + PRESENTDEVCHARTABLEINDX + Current index of Device Characteristics Table. + 19 + 22 + + + + + VENDORSPECIFICREGPOINTER + Pointer for Vendor Specific Registers. + 0x06C + read-write + 0x000000B0 + 0x20 + + + PVENDORREGSTARTADDR + Start Address of Vendor specific registers. + 0 + 15 + read-only + + + + + SLVMIPIIDVALUE + I3C MIPI Manufacturer ID Register. + 0x070 + read-write + 0x00000000 + 0x20 + + + SLVPROVIDSEL + Specifies the Provisional ID Type Selector (PID[32]). + 0 + 0 + + + SLVMIPIMFGID + Specifies the MIPI Manufacturer ID. + 1 + 15 + + + + + SLVPIDVALUE + I3C Normal Provisional ID Register. + 0x074 + read-write + 0x00000000 + 0x20 + + + SLVPIDDCR + Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). + 0 + 11 + + + SLVINSTID + This field is used to program the instance ID of the Slave. + 12 + 15 + + + SLVPARTID + Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) + 16 + 31 + + + + + SLVCHARCTRL + I3C Slave Characteristic Register. + 0x078 + read-write + 0x00070062 + 0x20 + + + MAXDATASPEEDLIMIT + Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). + 0 + 0 + + + IBIREQUESTCAPABLE + IBI Request Capable field in Bus Characteristic Register (BCR[1]). + 1 + 1 + read-only + + + IBIPAYLOAD + IBI Payload field in Bus Characteristic Register (BCR[2]). + 2 + 2 + read-only + + + OFFLINECAPABLE + Offline Capable field in Bus Characteristic Register (BCR[3]). + 3 + 3 + read-only + + + BRIDGEIDENTIFIER + Bridge Identifier field in Bus Characteristic Register (BCR[4]). + 4 + 4 + read-only + + + HDRCAPABLE + SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). + 5 + 5 + + + DEVICEROLE + Device Role field in Bus Characteristic Register (BCR[7:6]). + 6 + 7 + + + DCR + I3C Device Characteristic Value. + 8 + 15 + + + HDRCAP + I3C Device HDR Capability Register Value. + 16 + 23 + read-only + + + + + SLVMAXLEN + I3C Max Write/Read Length Register. + 0x07C + read-write + 0x00FF00FF + 0x20 + + + MWL + I3C Device Max Write Length + 0 + 15 + read-only + + + MRL + I3C Device Max Read Length. + 16 + 31 + read-only + + + + + MAXREADTURNAROUND + MXDS Maximum Read Turnaround Time. + 0x080 + read-write + 0x00000000 + 0x20 + + + MXDSMAXRDTURN + Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. + 0 + 23 + read-only + + + + + MAXDATASPEED + The values in this register are returned by the slave as GETACCMST CCC data. + 0x084 + read-write + 0x00000000 + 0x20 + + + MXDSMAXWRSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device + 0 + 2 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSMAXRDSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device + 8 + 10 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSCLKDATATURN + Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device + 16 + 18 + + + 8NS + 8ns + 0x0 + + + 9NS + 9ns + 0x1 + + + 10NS + 10ns + 0x2 + + + 11NS + 11ns + 0x3 + + + 12NS + 12ns + 0x4 + + + + + + + SLVINTRREQ + This register is used in slave mode of operation. + 0x08C + read-write + 0x00000000 + 0x20 + + + SIR + Slave Interrupt Request + 0 + 0 + + + SIRCTRL + Slave Interrupt Request Control + 1 + 2 + + + SEND + Send the Assigned Dynamic Address + 0x0 + + + + + MR + Master Request + 3 + 3 + + + IBISTS + IBI Completion Status + 8 + 9 + read-only + + + ACCEPTED + IBI accepted by the Master (ACK response received) + 0x1 + + + NOATTEMPT + IBI Not Attempted + 0x3 + + + + + + + SLVTSXSYMBLTIMING + TSP/TSL Symbol Timing Register + 0x090 + read-write + 0x0000003F + 0x20 + + + SLVTSXSYMBLCNT + TSP/TSL Symbol Count Value. + 0 + 5 + + + + + DEVICECTRLEXTENDED + Device Control Extended register. + 0x0B0 + read-write + 0x00000000 + 0x20 + + + DEVOPERATIONMODE + This bit is used to select the Device Operation Mode before the controller is enabled. + 0 + 1 + + + MASTER + Unspecified + 0x0 + + + SLAVE + Unspecified + 0x1 + + + + + REQMSTACKCTRL + In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current master. + 3 + 3 + + + ACK + ACK GETACCMST CCC + 0x0 + + + NACK + NACK GETACCMST CCC + 0x1 + + + + + + + SCLI3CODTIMING + SCL I3C Open Drain Timing Register + 0x0B4 + read-write + 0x000A0010 + 0x20 + + + I3CODLCNT + I3C Open Drain Low Count. + 0 + 7 + + + I3CODHCNT + I3C Open Drain High Count. + 16 + 23 + + + + + SCLI3CPPTIMING + SCL I3C Push Pull Timing Register + 0x0B8 + read-write + 0x000A000A + 0x20 + + + I3CPPLCNT + I3C Push Pull Low Count. + 0 + 7 + + + I3CPPHCNT + I3C Push Pull High Count. + 16 + 23 + + + + + SCLI2CFMTIMING + SCL I2C Fast Mode Timing Register + 0x0BC + read-write + 0x00100010 + 0x20 + + + I2CFMLCNT + I2C Fast Mode Low Count + 0 + 15 + + + I2CFMHCNT + I2C Fast Mode High Count + 16 + 31 + + + + + SCLI2CFMPTIMING + SCL I2C Fast Mode Plus Timing Register + 0x0C0 + read-write + 0x00100010 + 0x20 + + + I2CFMPLCNT + I2C Fast Mode Plus Low Count + 0 + 15 + + + I2CFMPHCNT + I2C Fast Mode Plus High Count + 16 + 23 + + + + + SCLEXTLCNTTIMING + SCL Extended Low Count Timing Register. + 0x0C8 + read-write + 0x20202020 + 0x20 + + + I3CEXTLCNT1 + I3C Extended Low Count Register 1 + 0 + 7 + + + I3CEXTLCNT2 + I3C Extended Low Count Register 2 + 8 + 15 + + + I3CEXTLCNT3 + I3C Extended Low Count Register 3 + 16 + 23 + + + I3CEXTLCNT4 + I3C Extended Low Count Register 4 + 24 + 31 + + + + + SCLEXTTERMNLCNTTIMING + SCL Termination Bit Low Count Timing Register + 0x0CC + read-write + 0x00030000 + 0x20 + + + I3CEXTTERMNLCNT + I3C Read Termination Bit Low count. + 0 + 3 + + + I3CTSSKEWCNT + I3C HDR Ternary Skew Count. + 16 + 19 + + + + + SDAHOLDSWITCHDLYTIMING + SDA Hold and Mode Switch Delay Timing Register + 0x0D0 + read-write + 0x00010000 + 0x20 + + + SDATXHOLD + This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with + 16 + 18 + + + + + BUSFREEAVAILTIMING + Bus Free and Available Timing Register + 0x0D4 + read-write + 0x00200020 + 0x20 + + + BUSFREETIME + This register field is used only in Master mode of operation + 0 + 15 + + + BUSAVAILABLETIME + This register field is used only in Slave mode of operation + 16 + 31 + + + + + BUSIDLETIMING + Bus Idle Timing Register + 0x0D8 + read-write + 0x00000020 + 0x20 + + + BUSIDLETIME + Bus Idle Count Value. + 0 + 19 + + + + + SCLLOWMSTEXTTIMEOUT + The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low Bus Reset Pattern. + 0x0DC + read-write + 0x003567E0 + 0x20 + + + SCLLOWMSTTIMEOUTCOUNT + This count defines the number of core clock periods to count for generation of the SCL Low Bus Reset Pattern. + 0 + 25 + + + + + I3CVERID + This register reflects the current release number of DWC_mipi_i3c + 0x0E0 + read-write + 0x3130302A + 0x20 + + + I3CVERID + Current release number + 0 + 31 + read-only + + + + + I3CVERTYPE + This register reflects the current release type of DWC_mipi_i3c. + 0x0E4 + read-write + 0x6C633033 + 0x20 + + + I3CVERTYPE + Current release type + 0 + 31 + read-only + + + + + QUEUESIZECAPABILITY + This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. + 0x0E8 + read-write + 0x00022355 + 0x20 + + + TXBUFSIZE + Transmit Data Buffer Size + 0 + 3 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + RXBUFSIZE + Receive Data Buffer Size + 4 + 7 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + CMDBUFSIZE + Command Queue Size + 8 + 11 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + RESPBUFSIZE + Response Queue Size + 12 + 15 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + IBIBUFSIZE + IBI Queue Size + 16 + 19 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + + + 10 + 0x010 + DEVCHARTABLE[%s] + Unspecified + DEVCHARTABLE + read-write + 0x200 + + LOC1 + Description cluster: Device Characteristic Table Location-1 of Device [n] + 0x0 + read-write + 0x00000000 + 0x20 + + + LSBPROVISIONALID + The LSB 32-bit value of Provisional-ID + 0 + 31 + read-only + + + + + LOC2 + Description cluster: Device Characteristic Table Location-2 of Device [n] + 0x4 + read-write + 0x00000000 + 0x20 + + + MSBPROVISIONALID + The MSB 16-bit value of Provisional-ID + 0 + 15 + read-only + + + + + LOC3 + Description cluster: Device Characteristic Table Location-3 of Device [n] + 0x8 + read-write + 0x00000000 + 0x20 + + + DCR + Device Characteristic Value + 0 + 7 + read-only + + + BCR + Bus Characteristic Value + 8 + 15 + read-only + + + + + LOC4 + Description cluster: Device Characteristic Table Location-4 of Device [n] + 0xC + read-write + 0x00000000 + 0x20 + + + DEVDYNAMICADDR + Device Dynamic Address assigned. + 0 + 7 + read-only + + + + + + 0x20 + 0x4 + SECDEVCHARTABLE[%s] + Description collection: Secondary Master Device Characteristic Table Location of Device [n] + 0x200 + read-write + 0x00000000 + 0x20 + + + DYNAMICADDR + The Dynamic Addr of Device [n] + 0 + 7 + read-only + + + DCRTYPE + The DCR TYPE of Device [n] + 8 + 15 + read-only + + + BCRTYPE + The BCR TYPE of Device [n] + 16 + 23 + read-only + + + STATICADDR + The Static Addr of Device [n] + 24 + 31 + read-only + + + + + 0xA + 0x4 + DEVADDRTABLELOC[%s] + Description collection: Device Address Table of Device [n] + 0x2C0 + read-write + 0x00000000 + 0x20 + + + DEVSTATICADDR + Device Static Address. + 0 + 6 + + + DEVDYNAMICADDR + Device Dynamic Address with parity. + 16 + 23 + + + DEVNACKRETRYCNT + This field is used to set the Device NACK Retry count for the particular device. + 29 + 30 + + + LEGACYI2CDEVICE + Legacy I2C device or not. + 31 + 31 + + + + + + DMA + Unspecified + I3CCORE_DMA + read-write + 0x900 + + CH0 + Unspecified + I3CCORE_DMA_CH0 + read-write + 0x000 + + SAR0 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR0 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL00 + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x02504821 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + DSTTRWIDTH + Destination Transfer Width. + 1 + 3 + + + DST_TR_WIDTH_0 + Unspecified + 0x0 + + + DST_TR_WIDTH_1 + Unspecified + 0x1 + + + DST_TR_WIDTH_2 + Unspecified + 0x2 + + + DST_TR_WIDTH_3 + Unspecified + 0x3 + + + DST_TR_WIDTH_4 + Unspecified + 0x4 + + + DST_TR_WIDTH_5 + Unspecified + 0x5 + + + DST_TR_WIDTH_6 + Unspecified + 0x6 + + + DST_TR_WIDTH_7 + Unspecified + 0x7 + + + + + RSVDSRCTRWIDTH + Reserved field - read-only + 4 + 6 + read-only + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + RSVDSRCGATHEREN + Reserved field - read-only + 17 + 17 + read-only + + + DSTSCATTEREN + Destination scatter enable. + 18 + 18 + + + DST_SCATTER_DISABLE + Unspecified + 0x0 + + + DST_SCATTER_ENABLE + Unspecified + 0x1 + + + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL01 + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG0L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E00 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG0H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + RSVD2CFG + Reserved field - read-only + 12 + 14 + read-only + + + RSVD3CFG + Reserved field - read-only + 15 + 31 + read-only + + + + + DSR0 + Destination Scatter register. + 0x050 + read-write + 0x00000000 + 0x20 + + + DSI + Destination Scatter Interval. + 0 + 19 + + + DSC + Destination Scatter Count. + 20 + 24 + + + + + + CH1 + Unspecified + I3CCORE_DMA_CH1 + read-write + 0x058 + + SAR1 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR1 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL1L + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x00F04805 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTTRWIDTH + Reserved field - read-only + 1 + 3 + read-only + + + SRCTRWIDTH + Source Transfer Width. + 4 + 6 + + + SRC_TR_WIDTH_0 + Unspecified + 0x0 + + + SRC_TR_WIDTH_1 + Unspecified + 0x1 + + + SRC_TR_WIDTH_2 + Unspecified + 0x2 + + + SRC_TR_WIDTH_3 + Unspecified + 0x3 + + + SRC_TR_WIDTH_4 + Unspecified + 0x4 + + + SRC_TR_WIDTH_5 + Unspecified + 0x5 + + + SRC_TR_WIDTH_6 + Unspecified + 0x6 + + + SRC_TR_WIDTH_7 + Unspecified + 0x7 + + + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + SRCGATHEREN + Source gather enable. + 17 + 17 + + + SRC_GATHER_DISABLE + Unspecified + 0x0 + + + SRC_GATHER_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTSCATTEREN + Reserved field - read-only + 18 + 18 + read-only + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL1H + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG1L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E20 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG1H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + + + SGR1 + Source Gather register + 0x048 + read-write + 0x00000000 + 0x20 + + + SGI + Source Gather Interval. + 0 + 19 + + + SGC + Source Gather Count. + 20 + 24 + + + + + + INT + Unspecified + I3CCORE_DMA_INT + read-write + 0x2C0 + + RAWTFR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x000 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntTfr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWBLOCK + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x008 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntBlock Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWSRCTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x010 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntSrcTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWDSTTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x018 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntDstTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWERR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x020 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntErr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSTFR + Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x028 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntTfr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSBLOCK + Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x030 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntBlock Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSSRCTRAN + Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x038 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntSrcTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSDSTTRAN + Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x040 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntDstTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSERR + Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x048 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntErr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + MASKTFR + The contents of the Raw Status register RawTfr is masked with the contents of the Mask register MaskTfr. + 0x050 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntTfr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKTFR + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKBLOCK + The contents of the Raw Status register RawBlock is masked with the contents of the Mask register MaskBlock. + 0x058 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntBlock Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKBLOCK + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKSRCTRAN + The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask register MaskSrcTran. + 0x060 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntSrcTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKSRCTRAN + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKDSTTRAN + The contents of the Raw Status register RawDstTran is masked with the contents of the Mask register MaskDstTran. + 0x068 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntDstTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKDSTTRAN + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKERR + The contents of the Raw Status register RawErr is masked with the contents of the Mask register MaskErr. + 0x070 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntErr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKERR + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CLEARTFR + Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x078 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntTfr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARBLOCK + Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x080 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntBlock Interrupt + 0 + 1 + write-only + + + + + CLEARSRCTRAN + Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x088 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntSrcTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARDSTTRAN + Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x090 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntDstTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARERR + Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x098 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntErr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + STATUSINT + The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TFR + OR of the contents of StatusTfr register + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + BLOCK + OR of the contents of StatusBlock register + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + SRCT + OR of the contents of StatusSrcTran + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DSTT + OR of the contents of StatusDstTran + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + ERR + OR of the contents of StatusErr + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + + SWHANDSHAKE + Unspecified + I3CCORE_DMA_SWHANDSHAKE + read-write + 0x368 + + REQSRCREG + A bit is assigned for each channel in this register. + 0x000 + read-write + 0x00000000 + 0x20 + + + SRCREQ + Source Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCREQWE + Source Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + REQDSTREG + A bit is assigned for each channel in this register. + 0x008 + read-write + 0x00000000 + 0x20 + + + DSTREQ + Destination Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTREQWE + Destination Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQSRCREG + A bit is assigned for each channel in this register. + 0x010 + read-write + 0x00000000 + 0x20 + + + SRCSGLREQ + Source Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCSGLREQWE + Source Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQDSTREG + A bit is assigned for each channel in this register. + 0x018 + read-write + 0x00000000 + 0x20 + + + DSTSGLREQ + Destination Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTSGLREQWE + Destination Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTSRCREG + A bit is assigned for each channel in this register. + 0x020 + read-write + 0x00000000 + 0x20 + + + LSTSRC + Source Last Transaction Request register + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTSRCREG + Reserved field- read-only + 2 + 7 + read-only + + + LSTSRCWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTDSTREG + A bit is assigned for each channel in this register. + 0x028 + read-write + 0x00000000 + 0x20 + + + LSTDST + Destination Last Transaction Request + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + LSTDSTWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + + MISC + Unspecified + I3CCORE_DMA_MISC + read-write + 0x398 + + DMACFGREG + This register is used to enable the DW_ahb_dmac, which must be done before any channel activity can begin. + 0x000 + read-write + 0x00000000 + 0x20 + + + DMAEN + DW_ahb_dmac Enable bit. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CHENREG + This is the DW_ahb_dmac Channel Enable Register. + 0x008 + read-write + 0x00000000 + 0x20 + + + CHEN + Channel Enable. + 0 + 1 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + RSVDCHENREG + Reserved field - read-only + 2 + 7 + read-only + + + CHENWE + Channel enable register + 8 + 9 + write-only + + + + + DMAIDREG + This is the DW_ahb_dmac ID register, which is a read-only register that reads back the coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. + 0x010 + read-write + 0x00000000 + 0x20 + + + DMAID + Hardcoded DW_ahb_dmac peripheral ID. + 0 + 31 + read-only + + + + + DMATESTREG + This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written, assuming the DW_ahb_dmac configuration has not optimized the same registers. + 0x018 + read-write + 0x00000000 + 0x20 + + + TESTSLVIF + DMA Test register + 0 + 0 + + + NORMAL_MODE + Unspecified + 0x0 + + + TEST_MODE + Unspecified + 0x1 + + + + + + + DMALPTIMEOUTREG + This register holds the timeout value of Low Power Counter. + 0x020 + read-write + 0x00000008 + 0x20 + + + DMALPTIMEOUT + This field holds timeout value of low power counter register. + 0 + 3 + + + + + DMACOMPPARAMS6L + DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about the component parameter settings for Channel 7. + 0x034 + read-write + 0x00000000 + 0x20 + + + CH7DTW + The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. + 0 + 2 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + DTW_8 + Unspecified + 0x1 + + + DTW_16 + Unspecified + 0x2 + + + DTW_32 + Unspecified + 0x3 + + + DTW_64 + Unspecified + 0x4 + + + DTW_128 + Unspecified + 0x5 + + + DTW_256 + Unspecified + 0x6 + + + + + CH7STW + The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. + 3 + 5 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + STW_8 + Unspecified + 0x1 + + + STW_16 + Unspecified + 0x2 + + + STW_32 + Unspecified + 0x3 + + + STW_64 + Unspecified + 0x4 + + + STW_128 + Unspecified + 0x5 + + + STW_256 + Unspecified + 0x6 + + + + + CH7STATDST + The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7STATSRC + The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7DSTSCAEN + The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7SRCGATEN + The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7LOCKEN + The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7MULTIBLKEN + The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7CTLWBEN + The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7HCLLP + The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH7FC + The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH7MAXMULTSIZE + The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH7DMS + The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7LMS + The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7SMS + The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7FIFODEPTH + The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5L + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x038 + read-write + 0x00000000 + 0x20 + + + CH6DTW + The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STW + The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STATDST + The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6STATSRC + The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6DSTSCAEN + The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6SRCGATEN + The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6LOCKEN + The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6MULTIBLKEN + The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6CTLWBEN + The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6HCLLP + The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH6FC + The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH6MAXMULTSIZE + The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH6DMS + The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6LMS + The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6SMS + The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6FIFODEPTH + The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + IFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5H + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x03C + read-write + 0x00000000 + 0x20 + + + CH5DTW + The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STW + The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STATDST + The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5STATSRC + The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5DSTSCAEN + The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5SRCGATEN + The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5LOCKEN + The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5MULTIBLKEN + The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5CTLWBEN + The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5HCLLP + The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH5FC + The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH5MAXMULTSIZE + The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH5DMS + The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5LMS + The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5SMS + The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5FIFODEPTH + The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4L + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x040 + read-write + 0x00000000 + 0x20 + + + CH4DTW + The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STW + The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STATDST + The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4STATSRC + The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4DSTSCAEN + The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4SRCGATEN + The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4LOCKEN + The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4MULTIBLKEN + The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4CTLWBEN + The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4HCLLP + The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH4FC + The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH4MAXMULTSIZE + The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH4DMS + The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4LMS + The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4SMS + The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4FIFODEPTH + The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4H + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x044 + read-write + 0x00000000 + 0x20 + + + CH3DTW + The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STW + The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STATDST + The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3STATSRC + The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3DSTSCAEN + The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3SRCGATEN + The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3LOCKEN + The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3MULTIBLKEN + The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3CTLWBEN + The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3HCLLP + The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH3FC + The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH3MAXMULTSIZE + The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH3DMS + The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3LMS + The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3SMS + The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3FIFODEPTH + The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3L + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x048 + read-write + 0x00000000 + 0x20 + + + CH2DTW + The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STW + The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STATDST + The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2STATSRC + The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2DSTSCAEN + The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2SRCGATEN + The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2LOCKEN + The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2MULTIBLKEN + The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2CTLWBEN + The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2HCLLP + The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH2FC + The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH2MAXMULTSIZE + The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH2DMS + The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH2LMS + The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2SMS + The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2FIFODEPTH + The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3H + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x04C + read-write + 0x1109A203 + 0x20 + + + CH1DTW + The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STW + The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STATDST + The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1STATSRC + The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1DSTSCAEN + The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1SRCGATEN + The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1LOCKEN + The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1MULTIBLKEN + The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1CTLWBEN + The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1HCLLP + The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH1FC + The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH1MAXMULTSIZE + The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH1DMS + The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1LMS + The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1SMS + The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1FIFODEPTH + The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2L + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x050 + read-write + 0x13016118 + 0x20 + + + CH0DTW + The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STW + The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STATDST + The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0STATSRC + The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0DSTSCAEN + The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0SRCGATEN + The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0LOCKEN + The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0MULTIBLKEN + The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0CTLWBEN + The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0HCLLP + The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH0FC + The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH0MAXMULTSIZE + The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH0DMS + The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0LMS + The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0SMS + The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0FIFODEPTH + The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2H + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x054 + read-write + 0x00000000 + 0x20 + + + CHOMULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant parameter. + 0 + 3 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH1MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant parameter. + 4 + 7 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH2MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant parameter. + 8 + 11 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH3MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant parameter. + 12 + 15 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH4MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant parameter. + 16 + 19 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH5MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant parameter. + 20 + 23 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH6MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant parameter. + 24 + 27 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH7MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant parameter. + 28 + 31 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + + + DMACOMPPARAMS1L + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x058 + read-write + 0x33333333 + 0x20 + + + CHOMAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant parameter. + 0 + 3 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH1MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant parameter. + 4 + 7 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH2MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant parameter. + 8 + 11 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH3MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant parameter. + 12 + 15 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH4MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant parameter. + 16 + 19 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH5MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant parameter. + 20 + 23 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH6MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant parameter. + 24 + 27 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH7MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant parameter. + 28 + 31 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + + + DMACOMPPARAMS1H + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x05C + read-write + 0x3120090C + 0x20 + + + BIGENDIAN + The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. + 0 + 0 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + INTRIO + The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. + 1 + 2 + read-only + + + ALL_INT + Unspecified + 0x0 + + + TYPE_INT + Unspecified + 0x1 + + + COMBINED_INT + Unspecified + 0x2 + + + + + MAXABRST + The value of this register is derived from the DMAH_MABRST coreConsultant parameter. + 3 + 3 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + RSVDDMACOMPPARAMS1 + Reserved field- read-only + 4 + 7 + read-only + + + NUMCHANNELS + The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. + 8 + 10 + read-only + + + NUM_CHANNEL_1 + Unspecified + 0x0 + + + NUM_CHANNEL_2 + Unspecified + 0x1 + + + NUM_CHANNEL_3 + Unspecified + 0x2 + + + NUM_CHANNEL_4 + Unspecified + 0x3 + + + NUM_CHANNEL_5 + Unspecified + 0x4 + + + NUM_CHANNEL_6 + Unspecified + 0x5 + + + NUM_CHANNEL_7 + Unspecified + 0x6 + + + NUM_CHANNEL_8 + Unspecified + 0x7 + + + + + NUMMASTERINT + The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. + 11 + 12 + read-only + + + NUM_MST_INTERFACE_1 + Unspecified + 0x0 + + + NUM_MST_INTERFACE_2 + Unspecified + 0x1 + + + NUM_MST_INTERFACE_3 + Unspecified + 0x2 + + + NUM_MST_INTERFACE_4 + Unspecified + 0x3 + + + + + SHDATAWIDTH + The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. + 13 + 14 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M4HDATAWIDTH + The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. + 15 + 16 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M3HDATAWIDTH + The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. + 17 + 18 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M2HDATAWIDTH + The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. + 19 + 20 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M1HDATAWIDTH + The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. + 21 + 22 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + NUMHSINT + The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. + 23 + 27 + read-only + + + HS_INTERFACE_0 + Unspecified + 0x00 + + + HS_INTERFACE_1 + Unspecified + 0x01 + + + HS_INTERFACE_2 + Unspecified + 0x02 + + + HS_INTERFACE_3 + Unspecified + 0x03 + + + HS_INTERFACE_4 + Unspecified + 0x04 + + + HS_INTERFACE_5 + Unspecified + 0x05 + + + HS_INTERFACE_6 + Unspecified + 0x06 + + + HS_INTERFACE_7 + Unspecified + 0x07 + + + HS_INTERFACE_8 + Unspecified + 0x08 + + + HS_INTERFACE_9 + Unspecified + 0x09 + + + HS_INTERFACE_a + Unspecified + 0x0A + + + HS_INTERFACE_b + Unspecified + 0x0B + + + HS_INTERFACE_c + Unspecified + 0x0C + + + HS_INTERFACE_d + Unspecified + 0x0D + + + HS_INTERFACE_e + Unspecified + 0x0E + + + HS_INTERFACE_f + Unspecified + 0x0F + + + HS_INTERFACE_10 + Unspecified + 0x10 + + + + + ADDENCODEDPARAMS + The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. + 28 + 28 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + STATICENDIANSELECT + The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant parameter. + 29 + 29 + read-only + + + + + DMACOMPSID0 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the component type. + 0x060 + read-write + 0x44571110 + 0x20 + + + DMACOMPTYPE + DMA Component Type Number = `h44571110. + 0 + 31 + read-only + + + + + DMACOMPSID1 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the version of the packaged component. + 0x064 + read-write + 0x3232322A + 0x20 + + + DMACOMPVERSION + DMA Component Version. + 0 + 31 + read-only + + + + + + + + + GLOBAL_I3CCORE121_NS + I3CCORE 1 + 0x2FBE1000 + + + + + GLOBAL_DMU120_NS + DMU 0 + 0x2FBEF800 + DMU + + + + 0 + 0x1000 + registers + + DMU + 0x20 + + + DMUCR + DMU Core Release + 0x3C0 + read-only + 0x00000000 + 0x20 + + + REL + Core Release + 1 + 1 + + + STEP + Step of Core Release + 2 + 2 + + + SUBSTEP + Sub-step of Core Release + 3 + 3 + + + YEAR + Time Stamp Year + 4 + 4 + + + MON + Time Stamp Month + 6 + 6 + + + DAY + Time Stamp Day + 8 + 8 + + + + + DMUI + DMU Internals + 0x3C4 + read-write + 0x00070000 + 0x20 + + + TXR + TX Service Request line of DMU + 0 + 0 + + + NotRequested + No TX DMA service requested + 0x0 + + + Requested + TX DMA Service requested + 0x1 + + + + + RX0R + RX0 Service Request line of DMU + 1 + 1 + + + NotRequested + No RX0 DMA service requested + 0x0 + + + Requested + RX0 DMA Service requested + 0x1 + + + + + RX1R + RX1 Service Request line of DMU + 2 + 2 + + + NotRequested + No RX1 DMA service requested + 0x0 + + + Requested + RX1 DMA Service requested + 0x1 + + + + + TXER + TX Event Service Request line of DMU + 3 + 3 + + + NotRequested + No TX Event DMA service requested + 0x0 + + + Requested + TX Event DMA Service requested + 0x1 + + + + + TFQPIP + TX FIFO/Queue Put Index Previous + 8 + 12 + + + ENA + DMU is enabled + 15 + 15 + + + Disabled + DMU is disabled + 0x0 + + + Enabled + DMU is enabled and can process DMA data + 0x1 + + + + + DEHS + Detect Element Handler State + 16 + 18 + + + DTX + Detect DMU Element Service + 20 + 20 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX0 + Detect DMU Element Service + 21 + 21 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX1 + Detect DMU Element Service + 22 + 22 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DTXE + Detect DMU Element Service + 23 + 23 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + EHS + Element Handler State + 24 + 26 + + + wait4cce + wait for bit MCAN:CCCR.CCE getting zero + 0x0 + + + wait4sa + wait for Start Address + 0x1 + + + wait4ta + wait for Trigger Address + 0x2 + + + transfer + wait for transfer of Element word + 0x3 + + + ack2mcan + acknowledge to MCAN + 0x4 + + + recovery + exception recovery + 0x5 + + + + + TX + Actual DMU Element Service + 28 + 28 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX0 + Actual DMU Element Service + 29 + 29 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX1 + Actual DMU Element Service + 30 + 30 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + TXE + Actual DMU Element Service + 31 + 31 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + + + DMUQC + DMU Queueing Counter + 0x3C8 + read-write + 0x00000000 + 0x20 + + + TXEEC + TX Element Enqueueing Counter + 0 + 7 + + + RX0EDC + RX0 Element Dequeueing Counter + 8 + 15 + + + RX1EDC + RX1 Element Dequeueing Counter + 16 + 23 + + + TXEEDC + TX Event Element Dequeueing Counter + 24 + 31 + + + + + DMUIR + DMU Interrupt Register + 0x3CC + read-write + 0x00000000 + 0x20 + + + TXENSA + TX Element Not Start Address + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal write access + 0x0 + + + Generated + Write to TX Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEIE + TX Element Illegal Enqueueing + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal enqueueing + 0x0 + + + Generated + Start of enqueueing without request detected, exception recovery started. + 0x1 + + + + + TXEIAS + TX Element Illegal Access Sequence + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEIDLC + TX Element Illegal DLC + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal DLC detected + 0x0 + + + Generated + DLC exceeds Tx Buffer element size of MCAN, exception recovery started. + 0x1 + + + + + TXEWATA + TX Element Write After Trigger Address + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write after Trigger Address + 0x0 + + + Generated + Write after Trigger address detected + 0x1 + + + + + TXEIR + TX Element Illegal Read + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read access + 0x0 + + + Generated + Illegal read access to DMU TX Element section detected, exception recovery started. + 0x1 + + + + + TXEE + A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx message enqueued + 0x0 + + + Generated + Tx message successfully enqueued + 0x1 + + + + + RX0ENSA + RX0 Element Not Start Address + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX0 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX0EID + RX0 Element Illegal Dequeueing + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX0EIAS + RX0 Element Illegal Access Sequence + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX0EIW + RX0 Element Illegal Write + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX0 Element detected, exception recovery started. + 0x1 + + + + + RX0ED + RX0 Element Dequeued + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX0EIO + RX0 Element Illegal Overwrite by timestamp + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + BEU + Bus Error Uncorrected + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + RX1ENSA + RX1 Element Not Start Address + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX1 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX1EID + RX1 Element Illegal Dequeueing + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX1EIAS + RX0 Element Illegal Access Sequence + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX1EIW + RX1 Element Illegal Write + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX1 Element detected, exception recovery started. + 0x1 + + + + + RX1ED + RX0 Element Dequeued + 20 + 20 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX1EIO + RX1 Element Illegal Overwrite by timestamp + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + TXEENSA + TX Event Element Not Start Address + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from TX Event Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEEID + TX Event Element Illegal Dequeueing + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started. + 0x1 + + + + + TXEEIAS + TX Event Element Illegal Access Sequence + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEEIW + TX Event Element Illegal Write + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU TX Event Element detected, exception recovery started. + 0x1 + + + + + TXEED + TX Event Element Dequeued + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No TX Event Element dequeued + 0x0 + + + Generated + TX Event Element successfully dequeued + 0x1 + + + + + DT + Debug Trigger + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Debug point not reached + 0x0 + + + Generated + Debug point reached + 0x1 + + + + + IAC + Illegal Access while in Configuration mode + 30 + 30 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Illegal Access while CCE mode + 0x0 + + + Generated + Illegal Access while CCE mode + 0x1 + + + + + + + DMUIE + DMU Interrupt Enable + 0x3D0 + read-write + 0x00000000 + 0x20 + + + TXENSAE + TX Element Not Start Address Enable + 0 + 0 + + + Disabled + Flag does not activate the interrupt line DMU + 0x0 + + + Enabled + the interrupt line DMU will be activated + 0x1 + + + + + + + DMUC + DMU Configuration + 0x3D4 + read-write + 0x00000000 + 0x20 + + + TTS + Transfer Timestamp + 0 + 0 + + + Disabled + No timestamp will be transferred via DMU Virtual Buffer + 0x0 + + + Enabled + Timestamp of message will be transferred from TSU via DMU Virtual Buffer + 0x1 + + + + + + + + + GLOBAL_MCAN120_NS + MCAN 0 + 0x2FBEF800 + GLOBAL_DMU120_NS + MCAN + + + + 0 + 0x1000 + registers + + MCAN + 0x20 + + + ENDN + Endian Register + 0x004 + read-only + 0x00000000 + 0x20 + + + ETV + Endianness Test Value + 0 + 31 + + + + + DBTP + Data Bit Timing and Prescaler Register + 0x00C + read-write + 0x00000000 + 0x20 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 3 + + + DTSEG2 + Data time segment after sample point + 4 + 7 + + + DTSEG1 + Data time segment before sample point + 8 + 12 + + + DBRP + Data Bit Rate Prescaler + 16 + 20 + + + TDC + Transmitter Delay Compensation + 23 + 23 + + + Disabled + Unspecified + 0x0 + + + Enabled + Unspecified + 0x1 + + + + + + + TEST + Test Register + 0x010 + read-write + 0x00000000 + 0x20 + + + LBCK + Loop Back Mode + 4 + 4 + + + Disabled + Loop Back Mode is disabled + 0x0 + + + Enabled + Loop Back Mode is enabled + 0x1 + + + + + TX + Control of Transmit Pin + 5 + 6 + + + CanCore + controlled by the CAN Core, updated at the end of the CAN bit time + 0x0 + + + Monitored + Sample Point can be monitored at pin m_can_tx + 0x1 + + + Dominant + Dominant (0) level at pin m_can_tx + 0x2 + + + Recessive + Recessive (1) at pin m_can_tx + 0x3 + + + + + RX + Receive Pin + 7 + 7 + + + Dominant + The CAN bus is dominant (m_can_rx = 0) + 0x0 + + + Recessive + The CAN bus is recessive (m_can_rx = '1') + 0x1 + + + + + TXBNP + Tx Buffer Number Prepared + 8 + 12 + + + PVAL + Prepared Valid + 13 + 13 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + TXBNS + Tx Buffer Number Started + 16 + 20 + + + SVAL + Started Valid + 21 + 21 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + + + RWD + RAM Watchdog + 0x014 + read-write + 0x00000000 + 0x20 + + + WDC + Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is + disabled. + 0 + 7 + + + WDV + Actual Message RAM Watchdog Counter Value. + 8 + 15 + + + + + CCCR + CC Control Register + 0x018 + read-write + 0x00000000 + 0x20 + + + INIT + Initialization + 0 + 0 + + + Normal + Normal Operation + 0x0 + + + Initialization + Initialization is started + 0x1 + + + + + CCE + Configuration Change Enable + 1 + 1 + + + Disabled + The CPU has no write access to the protected configuration registers + 0x0 + + + Enabled + The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + 0x1 + + + + + ASM + Restricted Operation Mode + 2 + 2 + + + Disabled + Normal CAN operation + 0x0 + + + Enabled + Restricted Operation Mode active + 0x1 + + + + + CSA + Clock Stop Acknowledge + 3 + 3 + + + Disabled + No clock stop acknowledged + 0x0 + + + Enabled + MCAN may be set in power down by stopping m_can_hclk and m_can_cclk + 0x1 + + + + + CSR + Clock Stop Request + 4 + 4 + + + Disabled + No clock stop is requested + 0x0 + + + Enabled + Clock stop requested. + 0x1 + + + + + MON + Bus Monitoring Mode + 5 + 5 + + + Disabled + Bus Monitoring Mode is disabled + 0x0 + + + Enabled + Bus Monitoring Mode is enabled + 0x1 + + + + + DAR + Disable Automatic Retransmission + 6 + 6 + + + Enabled + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + Disabled + Automatic retransmission disabled + 0x1 + + + + + TEST + Test Mode Enable + 7 + 7 + + + Disabled + Normal operation, register TEST holds reset values + 0x0 + + + Enabled + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD Operation Enable + 8 + 8 + + + Disabled + FD operation disabled + 0x0 + + + Enabled + FD operation enabled + 0x1 + + + + + BRSE + Bit Rate Switch Enable + 9 + 9 + + + Disabled + Bit rate switching for transmissions disabled + 0x0 + + + Enabled + Bit rate switching for transmissions enabled + 0x1 + + + + + WMM + Wide Message Marker + 11 + 11 + + + Disabled + 8-bit Message Marker used + 0x0 + + + Enabled + 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 0x1 + + + + + PXHD + Protocol Exception Handling Disable + 12 + 12 + + + Enabled + Protocol exception handling enabled + 0x0 + + + Disabled + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge Filtering during Bus Integration + 13 + 13 + + + Disabled + Edge filtering disabled + 0x0 + + + Enabled + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + Transmit Pause + 14 + 14 + + + Disabled + Transmit pause disabled + 0x0 + + + Enabled + Transmit pause enabled + 0x1 + + + + + NISO + Non ISO Operation + 15 + 15 + + + Disabled + CAN FD frame format according to ISO 11898-1:2015 + 0x0 + + + Enabled + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + NBTP + Nominal Bit Timing and Prescaler Register + 0x01C + read-write + 0x00000000 + 0x20 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 6 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 15 + + + NBRP + Nominal Bit Rate Prescaler + 16 + 24 + + + NSJW + Nominal (Re)Synchronization Jump Width + 25 + 31 + + + + + TSCC + Timestamp Counter Configuration + 0x020 + read-write + 0x00000000 + 0x20 + + + TSS + Timestamp Select + 0 + 1 + + + Zero + Timestamp counter value always 0x0000 + 0x0 + + + Increment + Timestamp counter value incremented according to TCP + 0x1 + + + External + External timestamp counter value used + 0x2 + + + Zero0 + Same as Zero + 0x3 + + + + + TCP + Timestamp Counter Prescaler + 16 + 19 + + + + + TSCV + Timestamp Counter Value + 0x024 + read-write + 0x00000000 + 0x20 + + + TSC + Timestamp Counter + 0 + 15 + + + + + TOCC + Timeout Counter Configuration + 0x028 + read-write + 0x00000000 + 0x20 + + + ETOC + Enable Timeout Counter + 0 + 0 + + + Disabled + Timeout Counter disabled + 0x0 + + + Enabled + Timeout Counter enabled + 0x1 + + + + + TOS + Timeout Select + 1 + 2 + + + Continuous + Continuous operation + 0x0 + + + TxEvent + Timeout controlled by Tx Event FIFO + 0x1 + + + RxFifo0 + Timeout controlled by Rx FIFO 0 + 0x2 + + + RxFifo1 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout Period + 16 + 31 + + + + + TOCV + Timeout Counter Value + 0x02C + read-write + 0x00000000 + 0x20 + + + TOC + Timeout Counter + 0 + 15 + + + + + ECR + Error Counter Register + 0x040 + read-write + 0x00000000 + 0x20 + + + TEC + Transmit Error Counter + 0 + 7 + + + REC + Receive Error Counter + 8 + 14 + + + RP + Receive Error Passive + 15 + 15 + + + Below + The Receive Error Counter is below the error passive level of 128 + 0x0 + + + Reached + The Receive Error Counter has reached the error passive level of 128 + 0x1 + + + + + CEL + CAN Error Logging + 16 + 23 + + + + + PSR + Protocol Status Register + 0x044 + read-write + 0x00000000 + 0x20 + + + LEC + Last Error Code + 0 + 2 + + + NoError + No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + StuffError + More than 5 equal bits in a sequence have occurred in a part of a received message + where this is not allowed. + 0x1 + + + FormError + A fixed format part of a received frame has the wrong format. + 0x2 + + + AckError + The message transmitted by the MCAN was not acknowledged by another node. + 0x3 + + + Bit1Error + During the transmission of a message (with the exception of the arbitration field), + the device wanted to send a recessive level (bit of logical value 1), but the monitored bus + value was dominant. + 0x4 + + + Bit0Error + During the transmission of a message (or acknowledge bit, or active error flag, or + overload flag), the device wanted to send a dominant level (data or identifier bit logical value + '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set + each time a sequence of 11 recessive bits has been monitored. This enables the CPU to + monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + dominant or continuously disturbed). + 0x5 + + + CRCError + The CRC check sum of a received message was incorrect. The CRC of an incoming + message does not match with the CRC calculated from the received data. + 0x6 + + + NoChange + Any read access to the Protocol Status Register re-initializes the LEC to '7'. + When the LEC shows the value '7', no CAN bus event was detected since the last CPU read + access to the Protocol Status Register. + 0x7 + + + + + ACT + Activity + 3 + 4 + + + Synchronizing + Node is synchronizing on CAN communication + 0x0 + + + Idle + Node is neither receiver nor tr ansmitter + 0x1 + + + Receiver + Node is operating as receiver + 0x2 + + + Transmitter + Node is operating as transmitter + 0x3 + + + + + EP + Error Passive + 5 + 5 + + + Active + The MCAN is in the Error_Active state. It normally takes part in bus communication and + sends an active error flag when an error has been detected + 0x0 + + + Passive + The MCAN is in the Error_Passive state + 0x1 + + + + + EW + Warning Status + 6 + 6 + + + Below + Both error counters are below the Error_Warning limit of 96 + 0x0 + + + Reached + At least one of error counter has reached the Error_Warning limit of 96 + 0x1 + + + + + BO + Bus_Off Status + 7 + 7 + + + On + The MCAN is not Bus_Off + 0x0 + + + Off + The MCAN is in Bus_Off state + 0x1 + + + + + DLEC + Data Phase Last Error Code + 8 + 10 + + + RESI + ESI flag of last received CAN FD Message + 11 + 11 + + + NotReceived + Last received CAN FD message did not ha ve its ESI flag set + 0x0 + + + Received + Last received CAN FD message had its ESI flag set + 0x1 + + + + + RBRS + BRS flag of last received CAN FD Message + 12 + 12 + + + NotReceived + Last received CAN FD message did not ha ve its BRS flag set + 0x0 + + + Received + Last received CAN FD message had its BRS flag set + 0x1 + + + + + RFDF + Received a CAN FD Message + 13 + 13 + + + NotReceived + Since this bit was reset by the CPU, no CAN FD message has been received + 0x0 + + + Received + Message in CAN FD format with FDF flag set has been received + 0x1 + + + + + PXE + Protocol Exception Event + 14 + 14 + + + NotTriggered + No protocol exception event occurred since last read access + 0x0 + + + Triggered + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter Delay Compensation Value + 16 + 22 + + + + + TDCR + Transmitter Delay Compensation Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TDCF + Transmitter Delay Compensation Filter Window Length + 0 + 6 + + + TDCO + Transmitter Delay Compensation SSP Offset + 8 + 14 + + + + + IR + Interrupt Register + 0x050 + read-write + 0x00000000 + 0x20 + + + RF0N + Rx FIFO 0 New Message + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 0 + 0x0 + + + Generated + New message written to Rx FIFO 0 + 0x1 + + + + + RF0W + Rx FIFO 0 Watermark Reached + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 fill level below watermark + 0x0 + + + Generated + Rx FIFO 0 fill level reached watermark + 0x1 + + + + + RF0F + Rx FIFO 0 Full + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 not full + 0x0 + + + Generated + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 0 message lost + 0x0 + + + Generated + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 0x1 + + + + + RF1N + Rx FIFO 1 New Message + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 1 + 0x0 + + + Generated + New message written to Rx FIFO 1 + 0x1 + + + + + RF1W + Rx FIFO 1 Watermark Reached + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 fill level below watermark + 0x0 + + + Generated + Rx FIFO 1 fill level reached watermark + 0x1 + + + + + RF1F + Rx FIFO 1 Full + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 not full + 0x0 + + + Generated + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 1 message lost + 0x0 + + + Generated + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + HPM + High Priority Message + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No high priority message received + 0x0 + + + Generated + High priority message received + 0x1 + + + + + TC + Transmission Completed + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission completed + 0x0 + + + Generated + Transmission completed + 0x1 + + + + + TCF + Transmission Cancellation Finished + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission cancellation finished + 0x0 + + + Generated + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO Empty + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx FIFO non-empty + 0x0 + + + Generated + Tx FIFO empty + 0x1 + + + + + TEFN + Tx Event FIFO New Entry + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO unchanged + 0x0 + + + Generated + Tx Handler wrote Tx Event FIFO element + 0x1 + + + + + TEFW + Tx Event FIFO Watermark Reached + 13 + 13 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO fill level below watermark + 0x0 + + + Generated + Tx Event FIFO fill level reached watermark + 0x1 + + + + + TEFF + Tx Event FIFO Full + 14 + 14 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO not full + 0x0 + + + Generated + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx Event FIFO element lost + 0x0 + + + Generated + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero + 0x1 + + + + + TSW + Timestamp Wraparound + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timestamp counter wrap-around + 0x0 + + + Generated + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM Access Failure + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM access failure occurred + 0x0 + + + Generated + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout Occurred + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timeout + 0x0 + + + Generated + Timeout reached + 0x1 + + + + + DRX + Message stored to Dedicated Rx Buffer + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx Buffer updated + 0x0 + + + Generated + At least one received message stored into an Rx Buff er + 0x1 + + + + + BEU + Bus Error Uncorrected + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + ELO + Error Logging Overflow + 22 + 22 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + CAN Error Logging Counter did not overflow + 0x0 + + + Generated + Overflow of CAN Error Logging Counter occurred + 0x1 + + + + + EP + Error Passive + 23 + 23 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Passive status unchanged + 0x0 + + + Generated + Error_Passive status changed + 0x1 + + + + + EW + Warning Status + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Warning status unchanged + 0x0 + + + Generated + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off Status + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Bus_Off status unchanged + 0x0 + + + Generated + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog Interrupt + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM Watchdog event occurred + 0x0 + + + Generated + Message RAM Watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in arbitration phase + 0x0 + + + Generated + Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 0x1 + + + + + PED + Protocol Error in Data Phase (Data Bit Time is used) + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in data phase + 0x0 + + + Generated + Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 0x1 + + + + + ARA + Access to Reserved Address + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No access to reserved address occurred + 0x0 + + + Generated + Access to reserved address occurred + 0x1 + + + + + + + IE + Interrupt Enable + 0x054 + read-write + 0x00000000 + 0x20 + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 0 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 2 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 3 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 4 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 5 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 6 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 7 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + HPME + High Priority Message Interrupt Enable + 8 + 8 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCE + Transmission Completed Interrupt Enable + 9 + 9 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 10 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 11 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 12 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 13 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 14 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 15 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 16 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 17 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 18 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 19 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BEUE + Bus Error Uncorrected Interrupt Enable + 21 + 21 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 22 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EPE + Error Passive Interrupt Enable + 23 + 23 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EWE + Warning Status Interrupt Enable + 24 + 24 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BOE + Bus_Off Status Interrupt Enable + 25 + 25 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + WDIE + Watchdog Interrupt Enable + 26 + 26 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 27 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEDE + Protocol Error in Data Phase Enable + 28 + 28 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ARAE + Access to Reserved Address Enable + 29 + 29 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + + + ILS + Interrupt Line Select + 0x058 + read-write + 0x00000000 + 0x20 + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 0 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 2 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 3 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 4 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 5 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 6 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 7 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + HPML + High Priority Message Interrupt Line + 8 + 8 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCL + Transmission Completed Interrupt Line + 9 + 9 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 10 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 11 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 12 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 13 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 14 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 15 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 16 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 17 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TOOL + Timeout Occurred Interrupt Line + 18 + 18 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 19 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BEUL + Bus Error Uncorrected Interrupt Line + 21 + 21 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 22 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EPL + Error Passive Interrupt Line + 23 + 23 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EWL + Warning Status Interrupt Line + 24 + 24 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BOL + Bus_Off Status Interrupt Line + 25 + 25 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + WDIL + Watchdog Interrupt Line + 26 + 26 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 27 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEDL + Protocol Error in Data Phase Line + 28 + 28 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ARAL + Access to Reserved Address Line + 29 + 29 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + + + ILE + Interrupt Line Enable + 0x05C + read-write + 0x00000000 + 0x20 + + + EINT0 + Enable Interrupt Line 0 + 0 + 0 + + + Disable + Interrupt line CORE0 disabled. + 0x0 + + + Enable + Interrupt line CORE0 enabled. + 0x1 + + + + + EINT1 + Enable Interrupt Line 1 + 1 + 1 + + + Disable + Interrupt line CORE1 disabled. + 0x0 + + + Enable + Interrupt line CORE1 enabled. + 0x1 + + + + + + + GFC + Global Filter Configuration + 0x080 + read-write + 0x00000000 + 0x20 + + + RRFE + Reject Remote Frames Extended + 0 + 0 + + + Filter + Filter remote frames with 29-bit extended IDs. + 0x0 + + + Reject + Reject all remote frames with 29-bit extended IDs. + 0x1 + + + + + RRFS + Reject Remote Frames Standard + 1 + 1 + + + Filter + Filter remote frames with 11-bit standard IDs. + 0x0 + + + Reject + Reject all remote frames with 11-bit standard IDs. + 0x1 + + + + + ANFE + Accept Non-matching Frames Extended + 2 + 3 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + ANFS + 4 + 5 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + + + SIDFC + Standard ID Filter Configuration + 0x084 + read-write + 0x00000000 + 0x20 + + + FLSSA + Filter List Standard Start Address + 2 + 15 + + + LSS + List Size Standard + 16 + 23 + + + + + XIDFC + Extended ID Filter Configuration + 0x088 + read-write + 0x00000000 + 0x20 + + + FLESA + Filter List Extended Start Address + 2 + 15 + + + LSE + List Size Extended + 16 + 22 + + + + + XIDAM + Extended ID AND Mask + 0x090 + read-write + 0x00000000 + 0x20 + + + EIDM + Extended ID Mask + 0 + 28 + + + + + HPMS + High Priority Message Status + 0x094 + read-only + 0x00000000 + 0x20 + + + BIDX + Buffer Index + 0 + 5 + + + MSI + Message Storage Indicator + 6 + 7 + + + NotSelected + No FIFO selected. + 0x0 + + + Lost + FIFO message lost. + 0x1 + + + Stored0 + Message stored in FIFO 0. + 0x2 + + + Stored1 + Message stored in FIFO 1. + 0x3 + + + + + FIDX + Filter Index + 8 + 14 + + + FLST + Filter List + 15 + 15 + + + Standard + Standard Filter List. + 0x0 + + + Extended + Extended Filter List. + 0x1 + + + + + + + NDAT1 + New Data 1 + 0x098 + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + NDAT2 + New Data 2 + 0x09C + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + RXF0C + Rx FIFO 0 Configuration + 0x0A0 + read-write + 0x00000000 + 0x20 + + + F0SA + Rx FIFO 0 Start Address + 2 + 15 + + + F0S + Rx FIFO 0 Size + 16 + 22 + + + F0WM + Rx FIFO 0 Watermark + 24 + 30 + + + F0OM + FIFO 0 Operation Mode + 31 + 31 + + + Blocking + FIFO 0 blocking mode. + 0x0 + + + Overwrite + FIFO 0 overwrite mode. + 0x1 + + + + + + + RXF0S + Rx FIFO 0 Status + 0x0A4 + read-only + 0x00000000 + 0x20 + + + F0FL + Rx FIFO 0 Fill Leve + 0 + 6 + + + F0GI + Rx FIFO 0 Get Index + 8 + 13 + + + F0PI + Rx FIFO 0 Put Index + 16 + 21 + + + F0F + Rx FIFO 0 Full + 24 + 24 + + + NotFull + Rx FIFO 0 not full. + 0x0 + + + Full + Rx FIFO 0 full. + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 25 + 25 + + + NotLost + No Rx FIFO 0 message lost. + 0x0 + + + Lost + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + 0x1 + + + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0x0A8 + read-write + 0x00000000 + 0x20 + + + F0AI + Rx FIFO 0 Acknowledge Index + 0 + 5 + + + + + RXBC + Rx Buffer Configuration + 0x0AC + read-write + 0x00000000 + 0x20 + + + RBSA + Rx Buffer Start Address + 2 + 15 + + + + + RXF1C + Rx FIFO 1 Configuration + 0x0B0 + read-write + 0x00000000 + 0x20 + + + F1SA + Rx FIFO 1 Start Address + 2 + 15 + + + F1S + Rx FIFO 1 Size + 16 + 22 + + + F1WM + Rx FIFO 1 Watermark + 24 + 30 + + + F1OM + FIFO 1 Operation Mode + 31 + 31 + + + BlockingMode + FIFO 1 blocking mode + 0x0 + + + OwerwriteMode + FIFO 1 overwrite mode + 0x1 + + + + + + + RXF1S + Rx FIFO 1 Status + 0x0B4 + read-only + 0x00000000 + 0x20 + + + F1FL + Rx FIFO 1 Fill Level + 0 + 6 + + + F1GI + Rx FIFO 1 Get Index + 8 + 13 + + + F1PI + Rx FIFO 1 Put Index + 16 + 21 + + + F1F + Rx FIFO 1 Full + 24 + 24 + + + NotFull + Rx FIFO 1 not full + 0x0 + + + Full + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 25 + 25 + + + NoMessageLost + No Rx FIFO 1 message lost + 0x0 + + + MessageLost + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + DMS + Debug Message Status + 30 + 31 + + + Idle + Idle state, wait for reception of debug messages, DMA request is cleared + 0x0 + + + ReceivedMesA + Debug message A received + 0x1 + + + ReceivedMesAB + Debug messages A, B received + 0x2 + + + ReceivedMesABC + Debug messages A, B, C received, DMA request is set + 0x3 + + + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0x0B8 + read-write + 0x00000000 + 0x20 + + + F1AI + Rx FIFO 1 Acknowledge Index + 0 + 5 + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0x0BC + read-write + 0x00000000 + 0x20 + + + F0DS + Rx FIFO 0 Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + F1DS + Rx FIFO 1 Data Field Size + 4 + 6 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + RBDS + Rx Buffer Data Field Size + 8 + 10 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBC + Tx Buffer Configuration + 0x0C0 + read-write + 0x00000000 + 0x20 + + + TBSA + Tx Buffers Start Address + 2 + 15 + + + NDTB + Number of Dedicated Transmit Buffers + 16 + 21 + + + TFQS + Transmit FIFO/Queue Size + 24 + 29 + + + TFQM + Tx FIFO/Queue Mode + 30 + 30 + + + TxFIFO + Tx FIFO operation + 0x0 + + + TxQueue + Tx Queue operation + 0x1 + + + + + + + TXFQS + Tx FIFO/Queue Status + 0x0C4 + read-only + 0x00000000 + 0x20 + + + TFFL + Tx FIFO Free Level + 0 + 5 + + + TFGI + Tx FIFO Get Index + 8 + 12 + + + TFQPI + Tx FIFO/Queue Put Index + 16 + 20 + + + TFQF + Tx FIFO/Queue Full + 21 + 21 + + + NotFull + Tx FIFO/Queue not full + 0x0 + + + Full + Tx FIFO/Queue full + 0x1 + + + + + + + TXESC + Tx Buffer Element Size Configuration + 0x0C8 + read-write + 0x00000000 + 0x20 + + + TBDS + Tx Buffer Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBRP + Tx Buffer Request Pending + 0x0CC + read-only + 0x00000000 + 0x20 + + + TRP + Transmission Request Pending + 0 + 31 + + + NoRequest + No transmission request pending + 0x00000000 + + + Request + Transmission request pending + 0x00000001 + + + + + + + TXBAR + Tx Buffer Add Request + 0x0D0 + read-write + 0x00000000 + 0x20 + + + AR + Add Request + 0 + 31 + + + NoRequest + No transmission request added + 0x00000000 + + + Request + Transmission requested added + 0x00000001 + + + + + + + TXBCR + Tx Buffer Cancellation Request + 0x0D4 + read-write + 0x00000000 + 0x20 + + + CR + Cancellation Request + 0 + 31 + + + NoCancellation + No cancellation pending + 0x00000000 + + + Cancellation + Cancellation pending + 0x00000001 + + + + + + + TXBTO + Tx Buffer Transmission Occurred + 0x0D8 + read-only + 0x00000000 + 0x20 + + + TO + Transmission Occurred + 0 + 31 + + + NoTransmittion + No transmission occurred + 0x00000000 + + + Transmittion + Transmission occurred + 0x00000001 + + + + + + + TXBCF + Tx Buffer Cancellation Finished + 0x0DC + read-only + 0x00000000 + 0x20 + + + CF + Cancellation Finished + 0 + 31 + + + NoCancellation + No transmit buffer cancellation + 0x00000000 + + + CancellationFinished + Transmit buffer cancellation finished + 0x00000001 + + + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0x0E0 + read-write + 0x00000000 + 0x20 + + + TIE + Transmission Interrupt Enable + 0 + 31 + + + Disable + Transmission interrupt disabled + 0x00000000 + + + Enable + Transmission interrupt enable + 0x00000001 + + + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0x0E4 + read-write + 0x00000000 + 0x20 + + + CFIE + Cancellation Finished Interrupt Enable + 0 + 31 + + + Disable + Cancellation finished interrupt disabled + 0x00000000 + + + Enable + Cancellation finished interrupt enabled + 0x00000001 + + + + + + + TXEFC + Tx Event FIFO Configuration + 0x0F0 + read-write + 0x00000000 + 0x20 + + + EFSA + Event FIFO Start Address + 2 + 15 + + + EFS + Event FIFO Size + 16 + 21 + + + EFWM + Event FIFO Watermark + 24 + 29 + + + + + TXEFS + Tx Event FIFO Status + 0x0F4 + read-only + 0x00000000 + 0x20 + + + EFFL + Event FIFO Fill Level + 0 + 5 + + + EFGI + Event FIFO Get Index + 8 + 12 + + + EFPI + Event FIFO Put Index + 16 + 20 + + + EFF + Event FIFO Full + 24 + 24 + + + NotFull + Tx Event FIFO not full + 0x0 + + + Full + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 25 + 25 + + + NotLost + No Tx Event FIFO element lost + 0x0 + + + Lost + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero. + 0x1 + + + + + + + TXEFA + Tx Event FIFO Acknowledge + 0x0F8 + read-write + 0x00000000 + 0x20 + + + EFAI + Event FIFO Acknowledge Index + 0 + 4 + + + + + + + GLOBAL_DMU121_NS + DMU 1 + 0x2FBF7800 + + + + + GLOBAL_MCAN121_NS + MCAN 1 + 0x2FBF7800 + GLOBAL_DMU121_NS + + + + + GLOBAL_STMDATA_NS + System Trace Macrocell data buffer 0 + 0xA0000000 + STMDATA + + + + + 0 + 0x10000000 + registers + + STMDATA + 0x20 + + + 16 + 0x1000000 + DOMAIN[%s] + Unspecified + STMDATA_DOMAIN + read-write + 0x000 + + 0x1000000 + 0x1 + DATA[%s] + Description collection: STM extended stimulus port data buffer area for domain n. NonSecure writes to this region generates trace packets with id n+96. Secure writes to this region generates trace packets with id n+32. + 0x000 + read-write + 0x00 + uint8_t + 0x8 + + + + + + + GLOBAL_STMDATA_S + System Trace Macrocell data buffer 1 + 0xA0000000 + GLOBAL_STMDATA_NS + + + + + + GLOBAL_TDDCONF_NS + TDDCONF 0 + 0xBF001000 + TDDCONF + + + + 0 + 0x1000 + registers + + TDDCONF + 0x20 + + + SYSPWRUPREQ + System power-up request + 0x400 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + DBGPWRUPREQ + Debug power-up request + 0x404 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + TRACEPORTSPEED + Trace port trace clock speed + 0x408 + read-write + 0x00000000 + 0x20 + + + SPEED + Trace clock speed + 0 + 1 + + + Speed100MHz + Speed 100MHz + 0x0 + + + Speed50MHz + Speed 50MHz + 0x1 + + + Speed25MHz + Speed 25MHz + 0x2 + + + Speed12500KHz + Speed 12.5MHz + 0x3 + + + + + + + DEBUGPOWERREQSTATUS + Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests + 0x40C + read-only + 0x00000000 + 0x20 + + + SYSPWRUPREQUESTED + System powerup request status + 0 + 0 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + DBGPWRUPREQUESTED + Debug domain powerup request status + 1 + 1 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + + + + + GLOBAL_TDDCONF_S + TDDCONF 1 + 0xBF001000 + GLOBAL_TDDCONF_NS + + + + + GLOBAL_STM_NS + System Trace Macrocell + 0xBF042000 + STM + + + + 0 + 0x1000 + registers + + STM + 0x20 + + + DMACTLR + Controls the DMA transfer request mechanism. + 0xC10 + read-write + 0x00000000 + 0x20 + + + SENS + Determines the sensitivity of the DMA request to the current buffer level in the STM + 2 + 3 + + + LT25 + Buffer is &lt;25 percent full. + 0x0 + + + LT50 + Buffer is &lt;50 percent full. + 0x1 + + + LT75 + Buffer is &lt;75 percent full. + 0x2 + + + LT100 + Buffer is &lt;100 percent full. + 0x3 + + + + + + + HEMASTR + Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. + 0xDF4 + read-only + 0x00000000 + 0x20 + + + MASTER + The STPv2 master number that hardware event traces should be associated with. + 0 + 16 + + + + + HEFEAT1R + Indicates the features of the STM. + 0xDF8 + read-only + 0x00000000 + 0x20 + + + HETER + STMHETER support + 0 + 0 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEERR + Hardware event error detection support + 2 + 2 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEMASTR + STMHEMASTR support + 3 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NUMHE + The number of hardware events supported by the STM + 15 + 23 + + + + + HEIDR + Indicates the features of hardware event tracing in the STM. + 0xDFC + read-only + 0x00000000 + 0x20 + + + CLASS + The CLASS field identifies the programmers model + 0 + 3 + + + HardwareEventControl + Hardware Event Control programmers model + 0x1 + + + + + CLASSREV + The CLASSREV field identifies the revision of the programmers model + 4 + 7 + + + VENDSPEC + The VENDSPEC field identifies any vendor specific modifications or mappings + 8 + 11 + + + + + TCSR + Controls the STM settings. + 0xE80 + read-write + 0x00000000 + 0x20 + + + EN + Global STM enable + 0 + 0 + + + Disabled + The STM is disabled. + 0x0 + + + Enabled + The STM is enabled. + 0x1 + + + + + TSEN + Enable or disable timestamp bundling. + 1 + 1 + + + Disabled + Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected. + 0x0 + + + Enabled + Time stamps are enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2. + 0x1 + + + + + SYNCEN + STMSYNCR is implemented so this value is Read As One. + 2 + 2 + + + Disabled + The STM Sync feature is disabled. + 0x0 + + + Enabled + The STM Sync feature is enabled. + 0x1 + + + + + COMPEN + Compression Enable for Stimulus Ports. + 5 + 5 + + + Disabled + Compression disabled, data transfers are transmitted at the size of the transaction. + 0x0 + + + Enabled + Compression enabled, data transfers are compressed to save bandwidth. + 0x1 + + + + + TRACEID + ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. + 16 + 22 + + + BUSY + STM is busy, for example the STM trace FIFO is not empty. + 23 + 23 + + + Ready + STM is not busy. + 0x0 + + + Busy + STM is busy. + 0x1 + + + + + + + AUXCR + Used for implementation defined STM controls. + 0xE94 + read-write + 0x00000000 + 0x20 + + + FIFOAF + FIFO Auto-flush. + 0 + 0 + + + Disabled + Auto-flush is disabled. + 0x0 + + + Enabled + Auto-flush is enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized. + 0x1 + + + + + ASYNCPE + Is ASYNC priority higher than trace? + 1 + 1 + + + Lower + ASYNC priority is always lower than trace. + 0x0 + + + Escalate + ASYNC priority escalates on second synchronization request. + 0x1 + + + + + PRIORINVDIS + Controls arbitration between AXI and HW during flush. + 2 + 2 + + + Enabled + Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done. + 0x0 + + + Disabled + Priority inversion disabled, AXI always has priority over HW. + 0x1 + + + + + CLKON + Provides override control for architectural clock gate enable. + 3 + 3 + + + Disabled + No override, clock gate is controlled by the state of STM. + 0x0 + + + Enabled + Override, clock is enabled. + 0x1 + + + + + AFREADYHIGH + Provides override control for the AFREADY output + 4 + 4 + + + Disabled + No override, AFREADY is controlled by the state of STM. + 0x0 + + + Enabled + Override, AFREADY is driven HIGH. + 0x1 + + + + + + + SPFEAT1R + Indicates the features of the STM. + 0xEA0 + read-write + 0x00000000 + 0x20 + + + PROT + Indicates the implemented STM protocol. + 0 + 3 + + + STPV2 + STM implements the STPV2 protocol. + 0x1 + + + + + TS + Timestamp support. + 4 + 5 + + + Absolute + Absolute timestamps implemented. + 0x1 + + + + + TSFREQ + Timestamp frequency indication configuration. + 6 + 6 + + + NotImplemented + STMTSFREQR is read-only. + 0x0 + + + Implemented + STMTSFREQR is read-write. + 0x1 + + + + + FORCETS + Timestamp force configuration. + 7 + 7 + + + NotImplemented + STMTSSTIMR bit 0 is read-only. + 0x0 + + + Implemented + STMTSSTIMR bit 0 is read-write. + 0x1 + + + + + TRACEBUS + Trace bus support. + 10 + 13 + + + TRIGCTL + Trigger control support. + 14 + 15 + + + TSPRESCALE + Timestamp prescale support + 16 + 17 + + + NotImplemented + Timestamp prescale is not implemented. + 0x0 + + + Implemented + Timestamp prescale is implemented. + 0x1 + + + + + HWTEN + STMTCSR.HWTEN support + 18 + 19 + + + NotImplemented + STMTCSR.HWTEN is not implemented + 0x1 + + + + + SYNCEN + STMTCSR.SYNCEN support + 20 + 21 + + + ReadAsOne + STMTCSR.SYNCEN implemented but always reads as b1 + 0x2 + + + + + SWOEN + STMTCSR.SWOEN support + 22 + 23 + + + NotImplemented + STMTCSR.SWOEN not implemented + 0x1 + + + + + + + SPFEAT2R + Indicates the features of the STM. + 0xEA4 + read-write + 0x00000000 + 0x20 + + + SPTER + STMSPTER support. + 0 + 1 + + + Implemented + STMSPTER is implemented. + 0x2 + + + + + SPER + STMSPER presence. + 2 + 2 + + + Implemented + STMSPER is implemented. + 0x0 + + + NotImplemented + STMSPER is not implemented. + 0x1 + + + + + SPCOMP + Data compression on stimulus ports support. + 4 + 5 + + + Programmable + Data compression support is programmable. STMTCSR.COMPEN is implemented. + 0x3 + + + + + SPOVERRIDE + Timestamp force configuration. + 6 + 6 + + + NotImplemented + STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. + 0x0 + + + Implemented + STMSPOVERRIDER and STMSPMOVERRIDER is implemented. + 0x1 + + + + + PRIVMASK + STMPRIVMASKR support. + 7 + 8 + + + NotImplemented + STMPRIVMASKR is not implemented. + 0x1 + + + + + SPTRTYPE + Stimulus port transaction type support. + 9 + 10 + + + InvariantAndGuaranteed + Both invariant timing and guaranteed transactions are supported. + 0x2 + + + + + DSIZE + Fundamental data size. + 12 + 15 + + + Bits32 + 32-bit data. + 0x0 + + + + + SPTYPE + Stimulus port type support + 18 + 19 + + + OnlyExtended + Only extended stimulus ports are implemented. + 0x1 + + + + + + + SPFEAT3R + Indicates the features of the STM. + 0xEA8 + read-write + 0x00000000 + 0x20 + + + NUMMAST + The number of stimulus ports masters implemented, minus 1. + 0 + 6 + + + Masters128 + Example: 128 masters implemented. + 0x3F + + + + + + + ITTRIGGER + Integration Test for Cross-Trigger Outputs Register. + 0xEE8 + write-only + 0x00000000 + 0x20 + + + TRIGOUTSPTE_W + Sets the value of the TRIGOUTSPTE output in integration mode. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTSW_W + Sets the value of the TRIGOUTSW output in integration mode. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTHETE_W + Sets the value of the TRIGOUTHETE output in integration mode. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ASYNCOUT_W + Sets the value of the ASYNCOUT output in integration mode. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBDATA0 + Controls the value of the ATDATAM output in integration mode. + 0xEEC + write-only + 0x00000000 + 0x20 + + + ATDATAM0_W + Sets the value of the ATDATAM[0]. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM7_W + Sets the value of the ATDATAM[7] output. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM15_W + Sets the value of the ATDATAM[15]. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM23_W + Sets the value of the ATDATAM[23]. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM31_W + Sets the value of the ATDATAM[31]. + 4 + 4 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBCTR2 + Controls the value of the ATDATAM output in integration mode. + 0xEF0 + write-only + 0x00000000 + 0x20 + + + ATREADYM_R + Reads the value of the ATREADYM input. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFVALIDM_R + Reads the value of the AFVALIDM input. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBID + Controls the value of the ATIDM output in integration mode. + 0xEF4 + write-only + 0x00000000 + 0x20 + + + ATIDM_W_0 + Sets the value of pin 0 of the ATIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_1 + Sets the value of pin 1 of the ATIDM output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_2 + Sets the value of pin 2 of the ATIDM output. + 2 + 2 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_3 + Sets the value of pin 3 of the ATIDM output. + 3 + 3 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_4 + Sets the value of pin 4 of the ATIDM output. + 4 + 4 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_5 + Sets the value of pin 5 of the ATIDM output. + 5 + 5 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_6 + Sets the value of pin 6 of the ATIDM output. + 6 + 6 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBCTR0 + Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. + 0xEF8 + write-only + 0x00000000 + 0x20 + + + ATVALIDM_W + Sets the value of the ATVALIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFREADYM_W + Sets the value of the AFREADYM_W output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_0 + Sets the value of pin 0 of the ATBYTESM output. + 8 + 8 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_1 + Sets the value of pin 1 of the ATBYTESM output. + 9 + 9 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the STM. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + NUMSP + This value indicates the number of stimulus ports implemented. + 0 + 16 + + + Max + Maximum 65,536 stimulus ports can be implemented. + 0x10000 + + + + + + + DEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + StimulusTrace + Peripheral is a stimulus trace source. + 0x6 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_TPIU_NS + Trace Port Interface Unit + 0xBF043000 + TPIU + + + + 0 + 0x1000 + registers + + TPIU + 0x20 + + + SUPPORTEDPORTSIZES + Each bit location is a single port size that is supported on the device. + 0x000 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates whether the TPIU supports port size of 1-bit. + 0 + 0 + + + NotSupported + Port size 1 is not supported. + 0x0 + + + Supported + Port size 1 is supported. + 0x1 + + + + + PORT_SIZE_2 + Indicates whether the TPIU supports port size of 2-bit. + 1 + 1 + + + NotSupported + Port size 2 is not supported. + 0x0 + + + Supported + Port size 2 is supported. + 0x1 + + + + + PORT_SIZE_3 + Indicates whether the TPIU supports port size of 3-bit. + 2 + 2 + + + NotSupported + Port size 3 is not supported. + 0x0 + + + Supported + Port size 3 is supported. + 0x1 + + + + + PORT_SIZE_4 + Indicates whether the TPIU supports port size of 4-bit. + 3 + 3 + + + NotSupported + Port size 4 is not supported. + 0x0 + + + Supported + Port size 4 is supported. + 0x1 + + + + + PORT_SIZE_5 + Indicates whether the TPIU supports port size of 5-bit. + 4 + 4 + + + NotSupported + Port size 5 is not supported. + 0x0 + + + Supported + Port size 5 is supported. + 0x1 + + + + + PORT_SIZE_6 + Indicates whether the TPIU supports port size of 6-bit. + 5 + 5 + + + NotSupported + Port size 6 is not supported. + 0x0 + + + Supported + Port size 6 is supported. + 0x1 + + + + + PORT_SIZE_7 + Indicates whether the TPIU supports port size of 7-bit. + 6 + 6 + + + NotSupported + Port size 7 is not supported. + 0x0 + + + Supported + Port size 7 is supported. + 0x1 + + + + + PORT_SIZE_8 + Indicates whether the TPIU supports port size of 8-bit. + 7 + 7 + + + NotSupported + Port size 8 is not supported. + 0x0 + + + Supported + Port size 8 is supported. + 0x1 + + + + + PORT_SIZE_9 + Indicates whether the TPIU supports port size of 9-bit. + 8 + 8 + + + NotSupported + Port size 9 is not supported. + 0x0 + + + Supported + Port size 9 is supported. + 0x1 + + + + + PORT_SIZE_10 + Indicates whether the TPIU supports port size of 10-bit. + 9 + 9 + + + NotSupported + Port size 10 is not supported. + 0x0 + + + Supported + Port size 10 is supported. + 0x1 + + + + + PORT_SIZE_11 + Indicates whether the TPIU supports port size of 11-bit. + 10 + 10 + + + NotSupported + Port size 11 is not supported. + 0x0 + + + Supported + Port size 11 is supported. + 0x1 + + + + + PORT_SIZE_12 + Indicates whether the TPIU supports port size of 12-bit. + 11 + 11 + + + NotSupported + Port size 12 is not supported. + 0x0 + + + Supported + Port size 12 is supported. + 0x1 + + + + + PORT_SIZE_13 + Indicates whether the TPIU supports port size of 13-bit. + 12 + 12 + + + NotSupported + Port size 13 is not supported. + 0x0 + + + Supported + Port size 13 is supported. + 0x1 + + + + + PORT_SIZE_14 + Indicates whether the TPIU supports port size of 14-bit. + 13 + 13 + + + NotSupported + Port size 14 is not supported. + 0x0 + + + Supported + Port size 14 is supported. + 0x1 + + + + + PORT_SIZE_15 + Indicates whether the TPIU supports port size of 15-bit. + 14 + 14 + + + NotSupported + Port size 15 is not supported. + 0x0 + + + Supported + Port size 15 is supported. + 0x1 + + + + + PORT_SIZE_16 + Indicates whether the TPIU supports port size of 16-bit. + 15 + 15 + + + NotSupported + Port size 16 is not supported. + 0x0 + + + Supported + Port size 16 is supported. + 0x1 + + + + + PORT_SIZE_17 + Indicates whether the TPIU supports port size of 17-bit. + 16 + 16 + + + NotSupported + Port size 17 is not supported. + 0x0 + + + Supported + Port size 17 is supported. + 0x1 + + + + + PORT_SIZE_18 + Indicates whether the TPIU supports port size of 18-bit. + 17 + 17 + + + NotSupported + Port size 18 is not supported. + 0x0 + + + Supported + Port size 18 is supported. + 0x1 + + + + + PORT_SIZE_19 + Indicates whether the TPIU supports port size of 19-bit. + 18 + 18 + + + NotSupported + Port size 19 is not supported. + 0x0 + + + Supported + Port size 19 is supported. + 0x1 + + + + + PORT_SIZE_20 + Indicates whether the TPIU supports port size of 20-bit. + 19 + 19 + + + NotSupported + Port size 20 is not supported. + 0x0 + + + Supported + Port size 20 is supported. + 0x1 + + + + + PORT_SIZE_21 + Indicates whether the TPIU supports port size of 21-bit. + 20 + 20 + + + NotSupported + Port size 21 is not supported. + 0x0 + + + Supported + Port size 21 is supported. + 0x1 + + + + + PORT_SIZE_22 + Indicates whether the TPIU supports port size of 22-bit. + 21 + 21 + + + NotSupported + Port size 22 is not supported. + 0x0 + + + Supported + Port size 22 is supported. + 0x1 + + + + + PORT_SIZE_23 + Indicates whether the TPIU supports port size of 23-bit. + 22 + 22 + + + NotSupported + Port size 23 is not supported. + 0x0 + + + Supported + Port size 23 is supported. + 0x1 + + + + + PORT_SIZE_24 + Indicates whether the TPIU supports port size of 24-bit. + 23 + 23 + + + NotSupported + Port size 24 is not supported. + 0x0 + + + Supported + Port size 24 is supported. + 0x1 + + + + + PORT_SIZE_25 + Indicates whether the TPIU supports port size of 25-bit. + 24 + 24 + + + NotSupported + Port size 25 is not supported. + 0x0 + + + Supported + Port size 25 is supported. + 0x1 + + + + + PORT_SIZE_26 + Indicates whether the TPIU supports port size of 26-bit. + 25 + 25 + + + NotSupported + Port size 26 is not supported. + 0x0 + + + Supported + Port size 26 is supported. + 0x1 + + + + + PORT_SIZE_27 + Indicates whether the TPIU supports port size of 27-bit. + 26 + 26 + + + NotSupported + Port size 27 is not supported. + 0x0 + + + Supported + Port size 27 is supported. + 0x1 + + + + + PORT_SIZE_28 + Indicates whether the TPIU supports port size of 28-bit. + 27 + 27 + + + NotSupported + Port size 28 is not supported. + 0x0 + + + Supported + Port size 28 is supported. + 0x1 + + + + + PORT_SIZE_29 + Indicates whether the TPIU supports port size of 29-bit. + 28 + 28 + + + NotSupported + Port size 29 is not supported. + 0x0 + + + Supported + Port size 29 is supported. + 0x1 + + + + + PORT_SIZE_30 + Indicates whether the TPIU supports port size of 30-bit. + 29 + 29 + + + NotSupported + Port size 30 is not supported. + 0x0 + + + Supported + Port size 30 is supported. + 0x1 + + + + + PORT_SIZE_31 + Indicates whether the TPIU supports port size of 31-bit. + 30 + 30 + + + NotSupported + Port size 31 is not supported. + 0x0 + + + Supported + Port size 31 is supported. + 0x1 + + + + + PORT_SIZE_32 + Indicates whether the TPIU supports port size of 32-bit. + 31 + 31 + + + NotSupported + Port size 32 is not supported. + 0x0 + + + Supported + Port size 32 is supported. + 0x1 + + + + + + + CURRENTPORTSIZE + Each bit location is a single port size. One bit can be set, and indicates the current port size. + 0x004 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates which port size is currently selected. + 0 + 0 + + + NotSelected + Port size 1 is not selected. + 0x0 + + + Selected + Port size 1 is selected. + 0x1 + + + + + PORT_SIZE_2 + Indicates which port size is currently selected. + 1 + 1 + + + NotSelected + Port size 2 is not selected. + 0x0 + + + Selected + Port size 2 is selected. + 0x1 + + + + + PORT_SIZE_3 + Indicates which port size is currently selected. + 2 + 2 + + + NotSelected + Port size 3 is not selected. + 0x0 + + + Selected + Port size 3 is selected. + 0x1 + + + + + PORT_SIZE_4 + Indicates which port size is currently selected. + 3 + 3 + + + NotSelected + Port size 4 is not selected. + 0x0 + + + Selected + Port size 4 is selected. + 0x1 + + + + + PORT_SIZE_5 + Indicates which port size is currently selected. + 4 + 4 + + + NotSelected + Port size 5 is not selected. + 0x0 + + + Selected + Port size 5 is selected. + 0x1 + + + + + PORT_SIZE_6 + Indicates which port size is currently selected. + 5 + 5 + + + NotSelected + Port size 6 is not selected. + 0x0 + + + Selected + Port size 6 is selected. + 0x1 + + + + + PORT_SIZE_7 + Indicates which port size is currently selected. + 6 + 6 + + + NotSelected + Port size 7 is not selected. + 0x0 + + + Selected + Port size 7 is selected. + 0x1 + + + + + PORT_SIZE_8 + Indicates which port size is currently selected. + 7 + 7 + + + NotSelected + Port size 8 is not selected. + 0x0 + + + Selected + Port size 8 is selected. + 0x1 + + + + + PORT_SIZE_9 + Indicates which port size is currently selected. + 8 + 8 + + + NotSelected + Port size 9 is not selected. + 0x0 + + + Selected + Port size 9 is selected. + 0x1 + + + + + PORT_SIZE_10 + Indicates which port size is currently selected. + 9 + 9 + + + NotSelected + Port size 10 is not selected. + 0x0 + + + Selected + Port size 10 is selected. + 0x1 + + + + + PORT_SIZE_11 + Indicates which port size is currently selected. + 10 + 10 + + + NotSelected + Port size 11 is not selected. + 0x0 + + + Selected + Port size 11 is selected. + 0x1 + + + + + PORT_SIZE_12 + Indicates which port size is currently selected. + 11 + 11 + + + NotSelected + Port size 12 is not selected. + 0x0 + + + Selected + Port size 12 is selected. + 0x1 + + + + + PORT_SIZE_13 + Indicates which port size is currently selected. + 12 + 12 + + + NotSelected + Port size 13 is not selected. + 0x0 + + + Selected + Port size 13 is selected. + 0x1 + + + + + PORT_SIZE_14 + Indicates which port size is currently selected. + 13 + 13 + + + NotSelected + Port size 14 is not selected. + 0x0 + + + Selected + Port size 14 is selected. + 0x1 + + + + + PORT_SIZE_15 + Indicates which port size is currently selected. + 14 + 14 + + + NotSelected + Port size 15 is not selected. + 0x0 + + + Selected + Port size 15 is selected. + 0x1 + + + + + PORT_SIZE_16 + Indicates which port size is currently selected. + 15 + 15 + + + NotSelected + Port size 16 is not selected. + 0x0 + + + Selected + Port size 16 is selected. + 0x1 + + + + + PORT_SIZE_17 + Indicates which port size is currently selected. + 16 + 16 + + + NotSelected + Port size 17 is not selected. + 0x0 + + + Selected + Port size 17 is selected. + 0x1 + + + + + PORT_SIZE_18 + Indicates which port size is currently selected. + 17 + 17 + + + NotSelected + Port size 18 is not selected. + 0x0 + + + Selected + Port size 18 is selected. + 0x1 + + + + + PORT_SIZE_19 + Indicates which port size is currently selected. + 18 + 18 + + + NotSelected + Port size 19 is not selected. + 0x0 + + + Selected + Port size 19 is selected. + 0x1 + + + + + PORT_SIZE_20 + Indicates which port size is currently selected. + 19 + 19 + + + NotSelected + Port size 20 is not selected. + 0x0 + + + Selected + Port size 20 is selected. + 0x1 + + + + + PORT_SIZE_21 + Indicates which port size is currently selected. + 20 + 20 + + + NotSelected + Port size 21 is not selected. + 0x0 + + + Selected + Port size 21 is selected. + 0x1 + + + + + PORT_SIZE_22 + Indicates which port size is currently selected. + 21 + 21 + + + NotSelected + Port size 22 is not selected. + 0x0 + + + Selected + Port size 22 is selected. + 0x1 + + + + + PORT_SIZE_23 + Indicates which port size is currently selected. + 22 + 22 + + + NotSelected + Port size 23 is not selected. + 0x0 + + + Selected + Port size 23 is selected. + 0x1 + + + + + PORT_SIZE_24 + Indicates which port size is currently selected. + 23 + 23 + + + NotSelected + Port size 24 is not selected. + 0x0 + + + Selected + Port size 24 is selected. + 0x1 + + + + + PORT_SIZE_25 + Indicates which port size is currently selected. + 24 + 24 + + + NotSelected + Port size 25 is not selected. + 0x0 + + + Selected + Port size 25 is selected. + 0x1 + + + + + PORT_SIZE_26 + Indicates which port size is currently selected. + 25 + 25 + + + NotSelected + Port size 26 is not selected. + 0x0 + + + Selected + Port size 26 is selected. + 0x1 + + + + + PORT_SIZE_27 + Indicates which port size is currently selected. + 26 + 26 + + + NotSelected + Port size 27 is not selected. + 0x0 + + + Selected + Port size 27 is selected. + 0x1 + + + + + PORT_SIZE_28 + Indicates which port size is currently selected. + 27 + 27 + + + NotSelected + Port size 28 is not selected. + 0x0 + + + Selected + Port size 28 is selected. + 0x1 + + + + + PORT_SIZE_29 + Indicates which port size is currently selected. + 28 + 28 + + + NotSelected + Port size 29 is not selected. + 0x0 + + + Selected + Port size 29 is selected. + 0x1 + + + + + PORT_SIZE_30 + Indicates which port size is currently selected. + 29 + 29 + + + NotSelected + Port size 30 is not selected. + 0x0 + + + Selected + Port size 30 is selected. + 0x1 + + + + + PORT_SIZE_31 + Indicates which port size is currently selected. + 30 + 30 + + + NotSelected + Port size 31 is not selected. + 0x0 + + + Selected + Port size 31 is selected. + 0x1 + + + + + PORT_SIZE_32 + Indicates which port size is currently selected. + 31 + 31 + + + NotSelected + Port size 32 is not selected. + 0x0 + + + Selected + Port size 32 is selected. + 0x1 + + + + + + + SUPPORTEDTRIGGERMODES + The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. + 0x100 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Indicates whether multiplying the trigger counter by 2^(0+1) is supported. + 0 + 0 + + + NotSelected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x1 + + + + + MULT_1 + Indicates whether multiplying the trigger counter by 2^(1+1) is supported. + 1 + 1 + + + NotSelected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x1 + + + + + MULT_2 + Indicates whether multiplying the trigger counter by 2^(2+1) is supported. + 2 + 2 + + + NotSelected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x1 + + + + + MULT_3 + Indicates whether multiplying the trigger counter by 2^(3+1) is supported. + 3 + 3 + + + NotSelected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x1 + + + + + MULT_4 + Indicates whether multiplying the trigger counter by 2^(4+1) is supported. + 4 + 4 + + + NotSelected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x1 + + + + + TCOUNT8 + Indicates whether an 8-bit wide counter register is implemented. + 8 + 8 + + + NotImplemented + An 8-bit wide counter register is implemented. + 0x0 + + + Implemented + An 8-bit wide counter register is implemented. + 0x1 + + + + + TRIGGERED + A trigger has occurred and the counter has reached 0. + 16 + 16 + + + NotOccured + Trigger has not occurred. + 0x0 + + + Occured + Trigger has occurred. + 0x1 + + + + + TRGRUN + A trigger has occurred but the counter is not at 0. + 17 + 17 + + + NotOccured + Either a trigger has not occurred or the counter is at 0. + 0x0 + + + Occured + A trigger has occurred but the counter is not at 0. + 0x1 + + + + + + + TRIGGERCOUNTERVALUE + The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. + 0x104 + read-write + 0x00000000 + 0x20 + + + TrigCount + 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. + 0 + 7 + + + + + TRIGGERMULTIPLIER + The Trigger_multiplier register contains the selectors for the trigger counter multiplier. + 0x108 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Multiply the Trigger Counter by 2^n. + 0 + 0 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_1 + Multiply the Trigger Counter by 2^n. + 1 + 1 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_2 + Multiply the Trigger Counter by 2^n. + 2 + 2 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_3 + Multiply the Trigger Counter by 2^n. + 3 + 3 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_4 + Multiply the Trigger Counter by 2^n. + 4 + 4 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + + + SUPPPORTEDTESTPATTERNMODES + The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. + 0x200 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + + + CURRENTTESTPATTERNMODES + Current_test_pattern_mode indicates the current test pattern or mode selected. + 0x204 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + + + TPRCR + The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. + 0x208 + read-write + 0x00000000 + 0x20 + + + PATTCOUNT + 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. + 0 + 7 + + + + + FFSR + The FFSR register indicates the current status of the formatter and flush features available in the TPIU. + 0x300 + read-write + 0x00000000 + 0x20 + + + FLINPROG + Flush in progress. + 0 + 0 + + + NotInProgress + A flush is not in progress. + 0x0 + + + InProgress + A flush is in progress. + 0x1 + + + + + FTSTOPPED + The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. + 1 + 1 + + + Running + Formatter has not stopped. + 0x0 + + + Stopped + Formatter has stopped. + 0x1 + + + + + TCPRESENT + Indicates whether the TRACECTL pin is available for use. + 2 + 2 + + + NotPresent + TRACECTL pin is not present. + 0x0 + + + Present + TRACECTL pin is present. + 0x1 + + + + + + + FFCR + The FFCR register controls the generation of stop, trigger, and flush events. + 0x304 + read-write + 0x00000000 + 0x20 + + + ENFTC + Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. + 0 + 0 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + ENFCONT + Is embedded in trigger packets and indicates that no cycle is using sync packets. + 1 + 1 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONFLIN + Enables the use of the flushin connection. + 4 + 4 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONTRIG + Initiates a manual flush of data in the system when a trigger event occurs. + 5 + 5 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANR + Generates a flush. This bit is set to 0 when this flush is serviced. + 6 + 6 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANW + Generates a flush. This bit is set to 1 when this flush is serviced. + 7 + 7 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGIN + Indicates a trigger when trigin is asserted. + 8 + 8 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGEVT + Indicates a trigger on a trigger event. + 9 + 9 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGFL + Indicates a trigger when flush completion on afreadys is returned. + 10 + 10 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPFL + Forces the FIFO to drain off any part-completed packets. + 12 + 12 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPTRIG + Stops the formatter after a trigger event is observed. Reset to disabled or 0. + 13 + 13 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + + + FSCR + The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. + 0x308 + read-write + 0x00000000 + 0x20 + + + CYCCOUNT + 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. + 0 + 11 + + + + + EXTCTLINPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. + 0x400 + read-write + 0x00000000 + 0x20 + + + EXTCTLIN_0 + EXTCTL inputs. + 0 + 0 + + + Low + Input EXTCTL0 is low. + 0x0 + + + High + Input EXTCTL0 is high. + 0x1 + + + + + EXTCTLIN_1 + EXTCTL inputs. + 1 + 1 + + + Low + Input EXTCTL1 is low. + 0x0 + + + High + Input EXTCTL1 is high. + 0x1 + + + + + EXTCTLIN_2 + EXTCTL inputs. + 2 + 2 + + + Low + Input EXTCTL2 is low. + 0x0 + + + High + Input EXTCTL2 is high. + 0x1 + + + + + EXTCTLIN_3 + EXTCTL inputs. + 3 + 3 + + + Low + Input EXTCTL3 is low. + 0x0 + + + High + Input EXTCTL3 is high. + 0x1 + + + + + EXTCTLIN_4 + EXTCTL inputs. + 4 + 4 + + + Low + Input EXTCTL4 is low. + 0x0 + + + High + Input EXTCTL4 is high. + 0x1 + + + + + EXTCTLIN_5 + EXTCTL inputs. + 5 + 5 + + + Low + Input EXTCTL5 is low. + 0x0 + + + High + Input EXTCTL5 is high. + 0x1 + + + + + EXTCTLIN_6 + EXTCTL inputs. + 6 + 6 + + + Low + Input EXTCTL6 is low. + 0x0 + + + High + Input EXTCTL6 is high. + 0x1 + + + + + EXTCTLIN_7 + EXTCTL inputs. + 7 + 7 + + + Low + Input EXTCTL7 is low. + 0x0 + + + High + Input EXTCTL7 is high. + 0x1 + + + + + + + EXTCTLOUTPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. + 0x404 + read-write + 0x00000000 + 0x20 + + + EXTCTLOUT_0 + EXTCTL outputs. + 0 + 0 + + + Low + Output EXTCTL0 is low. + 0x0 + + + High + Output EXTCTL0 is high. + 0x1 + + + + + EXTCTLOUT_1 + EXTCTL outputs. + 1 + 1 + + + Low + Output EXTCTL1 is low. + 0x0 + + + High + Output EXTCTL1 is high. + 0x1 + + + + + EXTCTLOUT_2 + EXTCTL outputs. + 2 + 2 + + + Low + Output EXTCTL2 is low. + 0x0 + + + High + Output EXTCTL2 is high. + 0x1 + + + + + EXTCTLOUT_3 + EXTCTL outputs. + 3 + 3 + + + Low + Output EXTCTL3 is low. + 0x0 + + + High + Output EXTCTL3 is high. + 0x1 + + + + + EXTCTLOUT_4 + EXTCTL outputs. + 4 + 4 + + + Low + Output EXTCTL4 is low. + 0x0 + + + High + Output EXTCTL4 is high. + 0x1 + + + + + EXTCTLOUT_5 + EXTCTL outputs. + 5 + 5 + + + Low + Output EXTCTL5 is low. + 0x0 + + + High + Output EXTCTL5 is high. + 0x1 + + + + + EXTCTLOUT_6 + EXTCTL outputs. + 6 + 6 + + + Low + Output EXTCTL6 is low. + 0x0 + + + High + Output EXTCTL6 is high. + 0x1 + + + + + EXTCTLOUT_7 + EXTCTL outputs. + 7 + 7 + + + Low + Output EXTCTL7 is low. + 0x0 + + + High + Output EXTCTL7 is high. + 0x1 + + + + + + + ITTRFLINACK + The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + TRIGINACK + Sets the value of triginack. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHINACK + Sets the value of flushinack. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITTRFLIN + The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. + 0xEE8 + read-write + 0x00000000 + 0x20 + + + TRIGIN + Reads the value of trigin. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHIN + Reads the value of flushin. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBDATA0 + The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + Enables control of the atreadys and afvalids outputs of the TPIU. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + Sets the value of afvalid. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + Sets the value of atready. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATID + Reads the value of atids. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. + To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + Reads the value of atvalids. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + Reads the value of afreadys. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + Reads the value of atbytess. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + MUXNUM + Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. + Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. + 0 + 4 + + + CLKRELAT + Indicates the relationship between atclk and traceclkin. + 5 + 5 + + + Synchronous + atclk and traceclkin are synchronous. + 0x0 + + + ASynchronous + atclk and traceclkin are asynchronous. + 0x1 + + + + + FIFOSIZE + FIFO size in powers of 2. + 6 + 8 + + + Entries4 + FIFO size of 4 entries, that is, 16 bytes. + 0x2 + + + + + TCLKDATA + Indicates whether trace clock plus data is supported. + 9 + 9 + + + Supported + Trace clock and data is supported. + 0x0 + + + NotSupported + Trace clock and data is not supported. + 0x1 + + + + + SWOMAN + Indicates whether Serial Wire Output, Manchester encoded format, is supported. + 10 + 10 + + + NotSupported + Serial Wire Output, Manchester encoded format, is not supported. + 0x0 + + + Supported + Serial Wire Output, Manchester encoded format, is supported. + 0x1 + + + + + SWOUARTNRZ + Indicates whether Serial Wire Output, UART or NRZ, is supported. + 11 + 11 + + + NotSupported + Serial Wire Output, UART or NRZ, is not supported. + 0x0 + + + Supported + Serial Wire Output, UART or NRZ, is supported. + 0x1 + + + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace sink. + 0x1 + + + + + SUB + The sub-type of the component + 4 + 7 + + + TracePort + Indicates that this component is a trace port component. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_CTI210_NS + Cross-Trigger Interface control 0 + 0xBF046000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + 0x20 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0x0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 0x1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + 0x20 + + + INTACK_0 + Acknowledges the ctitrigout 0 output. + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_1 + Acknowledges the ctitrigout 1 output. + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_2 + Acknowledges the ctitrigout 2 output. + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_3 + Acknowledges the ctitrigout 3 output. + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_4 + Acknowledges the ctitrigout 4 output. + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_5 + Acknowledges the ctitrigout 5 output. + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_6 + Acknowledges the ctitrigout 6 output. + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_7 + Acknowledges the ctitrigout 7 output. + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + 0x20 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0x0 + + + Active + Application trigger 0 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 0. + 0x1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0x0 + + + Active + Application trigger 1 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 1. + 0x1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0x0 + + + Active + Application trigger 2 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 2. + 0x1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0x0 + + + Active + Application trigger 3 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 3. + 0x1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + 0x20 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 0x1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 0x1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 0x1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 0x1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + 0x20 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 0x1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 0x1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 0x1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger to Channel Enable register + 0x020 + read-write + 0x00000000 + 0x20 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 0x1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 0x1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 0x1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Channel to Trigger Enable register + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + 0x20 + + + TRIGINSTATUS_0 + Shows the status of ctitrigin0 input. + 0 + 0 + + + Active + Ctitrigin 0 is active. + 0x1 + + + Inactive + Ctitrigin 0 is inactive. + 0x0 + + + + + TRIGINSTATUS_1 + Shows the status of ctitrigin1 input. + 1 + 1 + + + Active + Ctitrigin 1 is active. + 0x1 + + + Inactive + Ctitrigin 1 is inactive. + 0x0 + + + + + TRIGINSTATUS_2 + Shows the status of ctitrigin2 input. + 2 + 2 + + + Active + Ctitrigin 2 is active. + 0x1 + + + Inactive + Ctitrigin 2 is inactive. + 0x0 + + + + + TRIGINSTATUS_3 + Shows the status of ctitrigin3 input. + 3 + 3 + + + Active + Ctitrigin 3 is active. + 0x1 + + + Inactive + Ctitrigin 3 is inactive. + 0x0 + + + + + TRIGINSTATUS_4 + Shows the status of ctitrigin4 input. + 4 + 4 + + + Active + Ctitrigin 4 is active. + 0x1 + + + Inactive + Ctitrigin 4 is inactive. + 0x0 + + + + + TRIGINSTATUS_5 + Shows the status of ctitrigin5 input. + 5 + 5 + + + Active + Ctitrigin 5 is active. + 0x1 + + + Inactive + Ctitrigin 5 is inactive. + 0x0 + + + + + TRIGINSTATUS_6 + Shows the status of ctitrigin6 input. + 6 + 6 + + + Active + Ctitrigin 6 is active. + 0x1 + + + Inactive + Ctitrigin 6 is inactive. + 0x0 + + + + + TRIGINSTATUS_7 + Shows the status of ctitrigin7 input. + 7 + 7 + + + Active + Ctitrigin 7 is active. + 0x1 + + + Inactive + Ctitrigin 7 is inactive. + 0x0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + 0x20 + + + TRIGOUTSTATUS_0 + Shows the status of ctitrigout0 output. + 0 + 0 + + + Active + Ctitrigout 0 is active. + 0x1 + + + Inactive + Ctitrigout 0 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_1 + Shows the status of ctitrigout1 output. + 1 + 1 + + + Active + Ctitrigout 1 is active. + 0x1 + + + Inactive + Ctitrigout 1 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_2 + Shows the status of ctitrigout2 output. + 2 + 2 + + + Active + Ctitrigout 2 is active. + 0x1 + + + Inactive + Ctitrigout 2 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_3 + Shows the status of ctitrigout3 output. + 3 + 3 + + + Active + Ctitrigout 3 is active. + 0x1 + + + Inactive + Ctitrigout 3 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_4 + Shows the status of ctitrigout4 output. + 4 + 4 + + + Active + Ctitrigout 4 is active. + 0x1 + + + Inactive + Ctitrigout 4 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_5 + Shows the status of ctitrigout5 output. + 5 + 5 + + + Active + Ctitrigout 5 is active. + 0x1 + + + Inactive + Ctitrigout 5 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_6 + Shows the status of ctitrigout6 output. + 6 + 6 + + + Active + Ctitrigout 6 is active. + 0x1 + + + Inactive + Ctitrigout 6 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_7 + Shows the status of ctitrigout7 output. + 7 + 7 + + + Active + Ctitrigout 7 is active. + 0x1 + + + Inactive + Ctitrigout 7 is inactive. + 0x0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + 0x20 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 0x1 + + + Inactive + Ctichin 0 is inactive. + 0x0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 0x1 + + + Inactive + Ctichin 1 is inactive. + 0x0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 0x1 + + + Inactive + Ctichin 2 is inactive. + 0x0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 0x1 + + + Inactive + Ctichin 3 is inactive. + 0x0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + 0x20 + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 0x1 + + + Disabled + Disable ctichout channel 0 propagation. + 0x0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 0x1 + + + Disabled + Disable ctichout channel 1 propagation. + 0x0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 0x1 + + + Disabled + Disable ctichout channel 2 propagation. + 0x0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 0x1 + + + Disabled + Disable ctichout channel 3 propagation. + 0x0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + 0x20 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + 0x20 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + 0x20 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 0x4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 0x1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + 0x20 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 0x4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + 0x00000000 + 0x20 + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + 0x00000000 + 0x20 + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + 0x00000000 + 0x20 + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + 0x20 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + 0x20 + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 0xD + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 0xB + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + 0x20 + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 0x3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0x0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + 0x20 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0x0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0x0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + 0x20 + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + 0x20 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0x0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 0x9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + 0x20 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + 0x20 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + GLOBAL_CTI211_NS + Cross-Trigger Interface control 1 + 0xBF047000 + + + + + GLOBAL_ATBREPLICATOR210_NS + ATB Replicator module 0 + 0xBF048000 + ATBREPLICATOR + + + + 0 + 0x1000 + registers + + ATBREPLICATOR + 0x20 + + + IDFILTER0 + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ID0_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + IDFILTER1 + The IDFILTER1 register enables the programming of ID filtering for master port 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + ID1_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATREADYM0 + Reads the value of the atreadym0 input. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYM1 + Reads the value of the atreadym1 input. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDS + Reads the value of the atvalids input. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR0 + The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + Sets the value of the atvalidm0 output. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDM1 + Sets the value of the atvalidm1 output. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYS + Sets the value of the atreadys output. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTNUM + Indicates the number of master ports implemented. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + Indicates that this component replicates trace from a single source to multiple targets. + 0x2 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBREPLICATOR211_NS + ATB Replicator module 1 + 0xBF049000 + + + + + GLOBAL_ATBREPLICATOR212_NS + ATB Replicator module 2 + 0xBF04A000 + + + + + GLOBAL_ATBREPLICATOR213_NS + ATB Replicator module 3 + 0xBF04B000 + + + + + GLOBAL_ATBFUNNEL210_NS + ATB funnel module 0 + 0xBF04C000 + ATBFUNNEL + + + + 0 + 0x1000 + registers + + ATBFUNNEL + 0x20 + + + CTRLREG + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENS_0 + Enable slave port 0. + 0 + 0 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_1 + Enable slave port 1. + 1 + 1 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_2 + Enable slave port 2. + 2 + 2 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_3 + Enable slave port 3. + 3 + 3 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_4 + Enable slave port 4. + 4 + 4 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_5 + Enable slave port 5. + 5 + 5 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_6 + Enable slave port 6. + 6 + 6 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_7 + Enable slave port 7. + 7 + 7 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + HT + Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. + When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. + The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. + The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. + 8 + 11 + + + + + PRIORITYCTRLREG + The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. + 0x004 + read-write + 0x00000000 + 0x20 + + + PRIPORT0 + Priority value of port number 0. + 0 + 2 + + + PRIPORT1 + Priority value of port number 1. + 3 + 5 + + + PRIPORT2 + Priority value of port number 2. + 6 + 8 + + + PRIPORT3 + Priority value of port number 3. + 9 + 11 + + + PRIPORT4 + Priority value of port number 4. + 12 + 14 + + + PRIPORT5 + Priority value of port number 5. + 15 + 17 + + + PRIPORT6 + Priority value of port number 6. + 18 + 20 + + + PRIPORT7 + Priority value of port number 7. + 21 + 23 + + + + + ITATBDATA0 + The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_5 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 5 + 5 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_6 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 6 + 6 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_7 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 7 + 7 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_8 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 8 + 8 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_9 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 9 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_10 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 10 + 10 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_11 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 11 + 11 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_12 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 12 + 12 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_13 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 13 + 13 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_14 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 14 + 14 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_15 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 15 + 15 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_16 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 16 + 16 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + A read access returns the value of atreadym. + A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + A read access returns the value of afvalidm. + A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. +A write outputs the value to the atidm port. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. +A write outputs the value to atvalidm. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to afreadym. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to atbytesm. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTCOUNT + Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + This component arbitrates ATB inputs mapping to ATB outputs. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBFUNNEL211_NS + ATB funnel module 1 + 0xBF04D000 + + + + + GLOBAL_ATBFUNNEL212_NS + ATB funnel module 2 + 0xBF04E000 + + + + + GLOBAL_ATBFUNNEL213_NS + ATB funnel module 3 + 0xBF04F000 + + + + + ETM_NS + Embedded Trace Macrocell + 0xE0041000 + ETM + + + + 0 + 0x1000 + registers + + ETM + 0x20 + + + TRCPRGCTLR + Enables the trace unit. + 0x004 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCPROCSELR + Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero. + 0x008 + read-write + 0x00000000 + 0x20 + + + PROCSEL + PE select bits that select the PE to trace. + 0 + 4 + + + + + TRCSTATR + Idle status bit + 0x00C + read-write + 0x00000000 + 0x20 + + + IDLE + Trace unit enable bit + 0 + 0 + + + NotIdle + The trace unit is not idle. + 0x0 + + + Idle + The trace unit is idle. + 0x1 + + + + + PMSTABLE + Programmers' model stable bit + 1 + 1 + + + NotStable + The programmers' model is not stable. + 0x0 + + + Stable + The programmers' model is stable. + 0x1 + + + + + + + TRCCONFIGR + Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x010 + read-write + 0x00000000 + 0x20 + + + LOADASP0INST + Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. + 1 + 1 + + + No + Do not trace load instructions as P0 instructions. + 0x0 + + + Yes + Trace load instructions as P0 instructions. + 0x1 + + + + + STOREASP0INST + Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. + 2 + 2 + + + No + Do not trace store instructions as P0 instructions. + 0x0 + + + Yes + Trace store instructions as P0 instructions. + 0x1 + + + + + BB + Branch broadcast mode bit. + 3 + 3 + + + Disabled + Branch broadcast mode is disabled. + 0x0 + + + Enabled + Branch broadcast mode is enabled. + 0x1 + + + + + CCI + Cycle counting instruction trace bit. + 4 + 4 + + + Disabled + Cycle counting in the instruction trace is disabled. + 0x0 + + + Enabled + Cycle counting in the instruction trace is enabled. + 0x1 + + + + + CID + Context ID tracing bit. + 6 + 6 + + + Disabled + Context ID tracing is disabled. + 0x0 + + + Enabled + Context ID tracing is enabled. + 0x1 + + + + + VMID + Virtual context identifier tracing bit. + 7 + 7 + + + Disabled + Virtual context identifier tracing is disabled. + 0x0 + + + Enabled + Virtual context identifier tracing is enabled. + 0x1 + + + + + COND + Conditional instruction tracing bit. + 8 + 10 + + + Disabled + Conditional instruction tracing is disabled. + 0x0 + + + LoadOnly + Conditional load instructions are traced. + 0x1 + + + StoreOnly + Conditional store instructions are traced. + 0x2 + + + LoadAndStore + Conditional load and store instructions are traced. + 0x3 + + + All + All conditional instructions are traced. + 0x7 + + + + + TS + Global timestamp tracing bit. + 11 + 11 + + + Disabled + Global timestamp tracing is disabled. + 0x0 + + + Enabled + Global timestamp tracing is enabled. + 0x1 + + + + + RS + Return stack enable bit. + 12 + 12 + + + Disabled + Return stack is disabled. + 0x0 + + + Enabled + Return stack is enabled. + 0x1 + + + + + QE + Q element enable field. + 13 + 14 + + + Disabled + Q elements are disabled. + 0x0 + + + OnlyWithoutInstCounts + Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. + 0x1 + + + Enabled + Q elements with and without instruction counts are enabled. + 0x3 + + + + + VMIDOPT + Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. + 15 + 15 + + + VTTBR_EL2 + VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context +identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always +zero. If the trace unit supports a Virtual context identifier larger than 8 bits and +if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits +[15:8] of the trace unit Virtual context identifier are always zero. + 0x0 + + + CONTEXTIDR_EL2 + CONTEXTIDR_EL2 is used. + 0x1 + + + + + DA + Data address tracing bit. + 16 + 16 + + + Disabled + Data address tracing is disabled. + 0x0 + + + Enabled + Data address tracing is enabled. + 0x1 + + + + + DV + Data value tracing bit. + 17 + 17 + + + Disabled + Data value tracing is disabled. + 0x0 + + + Enabled + Data value tracing is enabled. + 0x1 + + + + + + + TRCEVENTCTL0R + Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. + 0x20 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate trace elements. + 0 + 7 + + + + + TRCEVENTCTL1R + Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x24 + read-write + 0x00000000 + 0x20 + + + INSTEN_0 + Instruction event enable field. + 0 + 0 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 0, in the instruction trace stream. + 0x1 + + + + + INSTEN_1 + Instruction event enable field. + 1 + 1 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 1, in the instruction trace stream. + 0x1 + + + + + INSTEN_2 + Instruction event enable field. + 2 + 2 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 2, in the instruction trace stream. + 0x1 + + + + + INSTEN_3 + Instruction event enable field. + 3 + 3 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 3, in the instruction trace stream. + 0x1 + + + + + DATAEN + Data event enable bit. + 4 + 4 + + + Disabled + The trace unit does not generate an Event element if event 0 occurs. + 0x0 + + + Enabled + The trace unit generates an Event element in the data trace stream if event 0 occurs. + 0x1 + + + + + ATB + AMBA Trace Bus (ATB) trigger enable bit. + 11 + 11 + + + Disabled + ATB trigger is disabled. + 0x0 + + + Enabled + ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event. + 0x1 + + + + + LPOVERRIDE + Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. + 12 + 12 + + + Disabled + Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state. + 0x0 + + + Enabled + Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation. + 0x1 + + + + + + + TRCSTALLCTLR + Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. + 0x2C + read-write + 0x00000000 + 0x20 + + + LEVEL + Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct. + 0 + 3 + + + Min + Zero invasion. This setting has a greater risk of a FIFO overflow + 0x0 + + + Max + Maximum invasion occurs but there is less risk of a FIFO overflow. + 0xF + + + + + ISTALL + Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL. + 8 + 8 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + DSTALL + Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL. + 9 + 9 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + INSTPRIORITY + Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL. + 10 + 10 + + + Disabled + The trace unit must not prioritize instruction trace. + 0x0 + + + Enabled + The trace unit can prioritize instruction trace. A trace unit might prioritize +instruction trace by preventing output of data trace, or other means which ensure +that the instruction trace has a higher priority than the data trace. + 0x1 + + + + + DATADISCARDLOAD + Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL. + 11 + 11 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data loads. + 0x1 + + + + + DATADISCARDSTORE + Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL. + 12 + 12 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data stores. + 0x1 + + + + + NOOVERFLOW + Trace overflow prevention bit. + 13 + 13 + + + Disabled + Trace overflow prevention is disabled. + 0x0 + + + Enabled + Trace overflow prevention is enabled. This might cause a significant performance impact. + 0x1 + + + + + + + TRCTSCTLR + Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. + 0x30 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate time stamps. + 0 + 7 + + + + + TRCSYNCPR + Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed. + 0x34 + read-write + 0x00000000 + 0x20 + + + PERIOD + Controls how many bytes of trace, the sum of instruction and data, that a trace unit can +generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD + 0 + 4 + + + Disabled + Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request. + 0x00 + + + + + + + TRCCCCTLR + Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1. + 0x38 + read-write + 0x00000000 + 0x20 + + + THRESHOLD + Sets the threshold value for instruction trace cycle counting. + 0 + 11 + + + + + TRCBBCTLR + Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. + 0x3C + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[0] controls the selection of address range comparator pair 0. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_1 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[1] controls the selection of address range comparator pair 1. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_2 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[2] controls the selection of address range comparator pair 2. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_3 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[3] controls the selection of address range comparator pair 3. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_4 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[4] controls the selection of address range comparator pair 4. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_5 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[5] controls the selection of address range comparator pair 5. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_6 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[6] controls the selection of address range comparator pair 6. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_7 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[7] controls the selection of address range comparator pair 7. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + + + TRCTRACEIDR + Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x40 + read-write + 0x00000000 + 0x20 + + + TRACEID + Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. + 0 + 6 + + + + + TRCQCTLR + Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. + 0x44 + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Specifies the address range comparators to be used for controlling Q elements. + 0 + 0 + + + Disabled + Address range comparator 0 is disabled. + 0x0 + + + Enabled + Address range comparator 0 is selected for use. + 0x1 + + + + + RANGE_1 + Specifies the address range comparators to be used for controlling Q elements. + 1 + 1 + + + Disabled + Address range comparator 1 is disabled. + 0x0 + + + Enabled + Address range comparator 1 is selected for use. + 0x1 + + + + + RANGE_2 + Specifies the address range comparators to be used for controlling Q elements. + 2 + 2 + + + Disabled + Address range comparator 2 is disabled. + 0x0 + + + Enabled + Address range comparator 2 is selected for use. + 0x1 + + + + + RANGE_3 + Specifies the address range comparators to be used for controlling Q elements. + 3 + 3 + + + Disabled + Address range comparator 3 is disabled. + 0x0 + + + Enabled + Address range comparator 3 is selected for use. + 0x1 + + + + + RANGE_4 + Specifies the address range comparators to be used for controlling Q elements. + 4 + 4 + + + Disabled + Address range comparator 4 is disabled. + 0x0 + + + Enabled + Address range comparator 4 is selected for use. + 0x1 + + + + + RANGE_5 + Specifies the address range comparators to be used for controlling Q elements. + 5 + 5 + + + Disabled + Address range comparator 5 is disabled. + 0x0 + + + Enabled + Address range comparator 5 is selected for use. + 0x1 + + + + + RANGE_6 + Specifies the address range comparators to be used for controlling Q elements. + 6 + 6 + + + Disabled + Address range comparator 6 is disabled. + 0x0 + + + Enabled + Address range comparator 6 is selected for use. + 0x1 + + + + + RANGE_7 + Specifies the address range comparators to be used for controlling Q elements. + 7 + 7 + + + Disabled + Address range comparator 7 is disabled. + 0x0 + + + Enabled + Address range comparator 7 is selected for use. + 0x1 + + + + + MODE + Selects whether the address range comparators selected by the RANGE field indicate +address ranges where the trace unit is permitted to generate Q elements or address ranges +where the trace unit is not permitted to generate Q elements: + 8 + 8 + + + Exclude + Exclude mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit cannot generate Q elements. If no +ranges are selected, Q elements are permitted across the entire memory map. + 0x0 + + + Include + Include mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit can generate Q elements. If all the +implemented bits in RANGE are set to 0 then Q elements are disabled. + 0x1 + + + + + + + TRCVICTLR + Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic. + 0x080 + read-write + 0x00000000 + 0x20 + + + EVENT_SEL + Select which resource number should be filtered. + 0 + 4 + + + Disabled + This event is not filtered. + 0x00 + + + Enabled + This event is filtered. + 0x01 + + + + + SSSTATUS + When TRCIDR4.NUMACPAIRS &gt; 0 or TRCIDR4.NUMPC &gt; 0, this bit returns the status of the start/stop logic. + 9 + 9 + + + Stopped + The start/stop logic is in the stopped state. + 0x0 + + + Started + The start/stop logic is in the started state. + 0x1 + + + + + TRCRESET + Controls whether a trace unit must trace a Reset exception. + 10 + 10 + + + Disabled + The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. + 0x0 + + + Enabled + The trace unit always traces a Reset exception. + 0x1 + + + + + TRCERR + When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. + 11 + 11 + + + Disabled + The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. + 0x0 + + + Enabled + The trace unit always traces a System error exception, regardless of the value of ViewInst. + 0x1 + + + + + EXLEVEL0_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 16 + 16 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 17 + 17 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 18 + 18 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 19 + 19 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 3. + 0x0 + + + + + EXLEVEL0_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 20 + 20 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 21 + 21 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 22 + 22 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 23 + 23 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 3. + 0x0 + + + + + + + TRCVIIECTLR + ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x084 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst exclude control. + 0x1 + + + + + + + TRCVISSCTLR + Use this to set, or read, the single address comparators that control the ViewInst start/stop +logic. The start/stop logic is active for an instruction which causes a start and remains active +up to and including an instruction which causes a stop, and then the start/stop logic becomes +inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x088 + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 16 + 16 + + + Disabled + The single address comparator 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 17 + 17 + + + Disabled + The single address comparator 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 18 + 18 + + + Disabled + The single address comparator 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 19 + 19 + + + Disabled + The single address comparator 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 20 + 20 + + + Disabled + The single address comparator 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 21 + 21 + + + Disabled + The single address comparator 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 22 + 22 + + + Disabled + The single address comparator 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 23 + 23 + + + Disabled + The single address comparator 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVIPCSSCTLR + Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x08C + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 0 + 0 + + + Disabled + The single PE comparator input 0, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 1 + 1 + + + Disabled + The single PE comparator input 1, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 2 + 2 + + + Disabled + The single PE comparator input 2, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 3 + 3 + + + Disabled + The single PE comparator input 3, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 4 + 4 + + + Disabled + The single PE comparator input 4, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 5 + 5 + + + Disabled + The single PE comparator input 5, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 6 + 6 + + + Disabled + The single PE comparator input 6, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 7 + 7 + + + Disabled + The single PE comparator input 7, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 16 + 16 + + + Disabled + The single PE comparator input 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 17 + 17 + + + Disabled + The single PE comparator input 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 18 + 18 + + + Disabled + The single PE comparator input 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 19 + 19 + + + Disabled + The single PE comparator input 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 20 + 20 + + + Disabled + The single PE comparator input 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 21 + 21 + + + Disabled + The single PE comparator input 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 22 + 22 + + + Disabled + The single PE comparator input 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 23 + 23 + + + Disabled + The single PE comparator input 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVDCTLR + Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. + 0x0A0 + read-write + 0x00000000 + 0x20 + + + EVENT_0 + Event unit enable bit. + 0 + 0 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_1 + Event unit enable bit. + 1 + 1 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_2 + Event unit enable bit. + 2 + 2 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_3 + Event unit enable bit. + 3 + 3 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_4 + Event unit enable bit. + 4 + 4 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_5 + Event unit enable bit. + 5 + 5 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_6 + Event unit enable bit. + 6 + 6 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_7 + Event unit enable bit. + 7 + 7 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + SPREL + Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). + 8 + 9 + + + Enabled + The trace unit does not affect the tracing of SP-relative transfers. + 0x0 + + + DataOnly + The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element. + 0x2 + + + Disabled + The trace unit does not trace the address or value portions of SP-relative transfers. + 0x3 + + + + + PCREL + Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). + 10 + 10 + + + Enabled + The trace unit does not affect the tracing of PC-relative transfers. + 0x0 + + + Disabled + The trace unit does not trace the address or value portions of PC-relative transfers. + 0x1 + + + + + TBI + Controls which information a trace unit populates in bits[63:56] of the data address. + 11 + 11 + + + SignExtend + The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value. + 0x0 + + + Copy + The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. + 0x1 + + + + + TRCEXDATA + Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs. + 12 + 12 + + + Disabled + Exception and exception return data transfers are not traced. + 0x0 + + + Enabled + Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced. + 0x1 + + + + + + + TRCVDSACCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A4 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Selects which single address comparators are in use with ViewData include control. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 0, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Selects which single address comparators are in use with ViewData include control. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 1, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Selects which single address comparators are in use with ViewData include control. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 2, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Selects which single address comparators are in use with ViewData include control. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 3, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Selects which single address comparators are in use with ViewData include control. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 4, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Selects which single address comparators are in use with ViewData include control. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 5, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Selects which single address comparators are in use with ViewData include control. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 6, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Selects which single address comparators are in use with ViewData include control. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 7, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Selects which single address comparators are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The single address comparator 0, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 0, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Selects which single address comparators are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The single address comparator 1, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 1, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Selects which single address comparators are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The single address comparator 2, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 2, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Selects which single address comparators are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The single address comparator 3, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 3, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Selects which single address comparators are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The single address comparator 4, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 4, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Selects which single address comparators are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The single address comparator 5, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 5, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Selects which single address comparators are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The single address comparator 6, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 6, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Selects which single address comparators are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The single address comparator 7, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 7, s selected for ViewData exclude control. + 0x1 + + + + + + + TRCVDARCCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A8 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 0 + 0 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 1 + 1 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 2 + 2 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 3 + 3 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 4 + 4 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 5 + 5 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 6 + 6 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 7 + 7 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, s selected for ViewData exclude control. + 0x1 + + + + + + + 0x3 + 0x4 + TRCSEQEVR[%s] + Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x100 + read-write + 0x00000000 + 0x20 + + + F_0 + Forward field. + 0 + 0 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_1 + Forward field. + 1 + 1 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_2 + Forward field. + 2 + 2 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_3 + Forward field. + 3 + 3 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_4 + Forward field. + 4 + 4 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_5 + Forward field. + 5 + 5 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_6 + Forward field. + 6 + 6 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_7 + Forward field. + 7 + 7 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + B_0 + Backward field. + 8 + 8 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_1 + Backward field. + 9 + 9 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_2 + Backward field. + 10 + 10 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_3 + Backward field. + 11 + 11 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_4 + Backward field. + 12 + 12 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_5 + Backward field. + 13 + 13 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_6 + Backward field. + 14 + 14 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_7 + Backward field. + 15 + 15 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + + + TRCSEQRSTEVR + Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should reset the sequencer. + 0 + 7 + + + + + TRCSEQSTR + Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x11C + read-write + 0x00000000 + 0x20 + + + STATE + Sets or returns the state of the sequencer. + 0 + 1 + + + State0 + The sequencer is in state 0. + 0x0 + + + State1 + The sequencer is in state 1. + 0x1 + + + State2 + The sequencer is in state 2. + 0x2 + + + State3 + The sequencer is in state 3. + 0x3 + + + + + + + TRCEXTINSELR + Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x120 + read-write + 0x00000000 + 0x20 + + + SEL_0 + Each field in this collection selects an external input as a resource for the trace unit. + 0 + 7 + + + SEL_1 + Each field in this collection selects an external input as a resource for the trace unit. + 8 + 15 + + + SEL_2 + Each field in this collection selects an external input as a resource for the trace unit. + 16 + 23 + + + SEL_3 + Each field in this collection selects an external input as a resource for the trace unit. + 24 + 31 + + + + + 0x4 + 0x4 + TRCCNTRLDVR[%s] + Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x140 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n. + 0 + 15 + + + + + 0x4 + 0x4 + TRCCNTCTLR[%s] + Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x150 + read-write + 0x00000000 + 0x20 + + + CNTEVENT + Selects an event, that when it occurs causes counter n to decrement. + 0 + 7 + + + RLDEVENT + Selects an event, that when it occurs causes a reload event for counter n. + 8 + 15 + + + RLDSELF + Controls whether a reload event occurs for counter n, when counter n reaches zero. + 16 + 16 + + + Disabled + The counter is in Normal mode. + 0x0 + + + Enabled + The counter is in Self-reload mode. + 0x1 + + + + + CNTCHAIN + For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. + 17 + 17 + + + Disabled + Counter n does not decrement when a reload event for counter n-1 occurs. + 0x0 + + + Enabled + Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. + 0x1 + + + + + + + 0x4 + 0x4 + TRCCNTVR[%s] + Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle. + 0x160 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the count value of counter n. + 0 + 15 + + + + + 0x1E + 0x4 + TRCRSCTLR[%s] + Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE +behavior of the resource selector occurs, so the resource selector might fire +unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + 0x200 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCSSCCR0 + Controls the single-shot comparator. + 0x280 + read-write + 0x00000000 + 0x20 + + + RST + Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected + 24 + 24 + + + Disabled + Multiple matches can not be detected. + 0x0 + + + Enabled + Multiple matches can occur. + 0x1 + + + + + + + TRCSSCSR0 + Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. + 0x2A0 + read-write + 0x00000000 + 0x20 + + + INST + Instruction address comparator support + 0 + 0 + + + False + Single-shot instruction address comparisons not supported. + 0x0 + + + True + Single-shot instruction address comparisons supported. + 0x1 + + + + + DA + Data address comparator support + 1 + 1 + + + False + Data address comparisons not supported. + 0x0 + + + True + Data address comparisons supported. + 0x1 + + + + + DV + Data value comparator support + 2 + 2 + + + False + Data value comparisons not supported. + 0x0 + + + True + Data value comparisons supported. + 0x1 + + + + + PC + Process counter value comparator support + 3 + 3 + + + False + Process counter value comparisons not supported. + 0x0 + + + True + Process counter value comparisons supported. + 0x1 + + + + + STATUS + Single-shot status. This indicates whether any of the selected comparators have matched. + 31 + 31 + + + NoMatch + Match has not occurred. + 0x0 + + + Match + Match has occurred at least once. + 0x1 + + + + + + + TRCSSPCICR0 + Selects the processor comparator inputs for Single-shot control. + 0x2C0 + read-write + 0x00000000 + 0x20 + + + PC_0 + Selects processor comparator 0 inputs for Single-shot control + 0 + 0 + + + Disabled + Processor comparator 0 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 0 is selected for Single-shot control. + 0x1 + + + + + PC_1 + Selects processor comparator 1 inputs for Single-shot control + 1 + 1 + + + Disabled + Processor comparator 1 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 1 is selected for Single-shot control. + 0x1 + + + + + PC_2 + Selects processor comparator 2 inputs for Single-shot control + 2 + 2 + + + Disabled + Processor comparator 2 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 2 is selected for Single-shot control. + 0x1 + + + + + PC_3 + Selects processor comparator 3 inputs for Single-shot control + 3 + 3 + + + Disabled + Processor comparator 3 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 3 is selected for Single-shot control. + 0x1 + + + + + + + TRCPDCR + Controls the single-shot comparator. + 0x310 + read-write + 0x00000000 + 0x20 + + + PU + Power up request, to request that power to ETM and access to the trace registers is maintained. + 24 + 24 + + + Disabled + Power not requested. + 0x0 + + + Enabled + Power requested. + 0x1 + + + + + + + TRCPDSR + Indicates the power down status of the ETM. + 0x314 + read-write + 0x00000000 + 0x20 + + + POWER + Indicates ETM is powered up + 0 + 0 + + + NotPoweredUp + ETM is not powered up. All registers are not accessible. + 0x0 + + + PoweredUp + ETM is powered up. All registers are accessible. + 0x1 + + + + + STICKYPD + Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR + 1 + 1 + + + NotPoweredDown + Trace register power has not been removed since the TRCPDSR was last read. + 0x0 + + + PoweredDown + Trace register power has been removed since the TRCPDSR was last read. + 0x1 + + + + + + + TRCITATBIDR + Sets the state of output pins. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + ID_0 + Drives the ATIDMI[0] output pin. + 0 + 0 + + + ID_1 + Drives the ATIDMI[1] output pin. + 1 + 1 + + + ID_2 + Drives the ATIDMI[2] output pin. + 2 + 2 + + + ID_3 + Drives the ATIDMI[3] output pin. + 3 + 3 + + + ID_4 + Drives the ATIDMI[4] output pin. + 4 + 4 + + + ID_5 + Drives the ATIDMI[5] output pin. + 5 + 5 + + + ID_6 + Drives the ATIDMI[6] output pin. + 6 + 6 + + + + + TRCITIATBINR + Reads the state of the input pins. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALID + Returns the value of the ATVALIDMI input pin. + 0 + 0 + + + AFREADY + Returns the value of the AFREADYMI input pin. + 1 + 1 + + + + + TRCITIATBOUTR + Sets the state of the output pins. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALID + Drives the ATVALIDMI output pin. + 0 + 0 + + + AFREADY + Drives the AFREADYMI output pin. + 1 + 1 + + + + + TRCITCTRL + Enables topology detection or integration testing, by putting ETM-M33 into integration mode. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration mode enable + 0 + 0 + + + Disabled + ETM is not in integration mode. + 0x0 + + + Enabled + ETM is in integration mode. + 0x1 + + + + + + + TRCCLAIMSET + Sets bits in the claim tag and determines the number of claim tag bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + SET_0 + Claim tag set register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Claim + Set claim tag 0. + 0x1 + + + + + SET_1 + Claim tag set register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Claim + Set claim tag 1. + 0x1 + + + + + SET_2 + Claim tag set register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Claim + Set claim tag 2. + 0x1 + + + + + SET_3 + Claim tag set register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Claim + Set claim tag 3. + 0x1 + + + + + + + TRCCLAIMCLR + Clears bits in the claim tag and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + CLR_0 + Claim tag clear register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Clear + Clear claim tag 0. + 0x1 + + + + + CLR_1 + Claim tag clear register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Clear + Clear claim tag 1. + 0x1 + + + + + CLR_2 + Claim tag clear register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Clear + Clear claim tag 2. + 0x1 + + + + + CLR_3 + Claim tag clear register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Clear + Clear claim tag 3. + 0x1 + + + + + + + TRCAUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + TRCDEVARCH + The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component + 0xFBC + read-only + 0x00000000 + 0x20 + + + ARCHID + Architecture ID + 0 + 15 + + + ETMv42 + Component is an ETMv4 component + 0x4A13 + + + + + REVISION + Architecture revision + 16 + 19 + + + v2 + Component is part of architecture 4.2 + 0x2 + + + + + PRESENT + This register is implemented + 20 + 20 + + + Absent + The register is not implemented. + 0x0 + + + Present + The register is implemented. + 0x1 + + + + + ARCHITECT + Defines the architect of the component + 21 + 31 + + + Arm + This peripheral was architected by Arm. + 0x23B + + + + + + + TRCDEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + ProcessorTrace + Peripheral is a processor trace source. + 0x1 + + + + + + + 0x8 + 0x4 + TRCPIDR[%s] + Description collection: Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + 0x4 + 0x4 + TRCCIDR[%s] + Description collection: Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + + + CTI_S + Cross-Trigger Interface control 2 + 0xE0042000 + + + + + CPUC_S + CM33 SubSystem + 0xE0080000 + CM33SS + + + + 0 + 0x1000 + registers + + CM33SS + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LOCK + Register to lock the certain parts of the CPU from being modified. + 0x500 + read-write + 0x00000000 + 0x20 + + + LOCKVTORAIRCRS + Locks both the Vector table Offset Register (VTOR) and + Application Interrupt and Reset Control Register (AIRCR) for secure mode. + 0 + 0 + + + NotLocked + Both VTOR and AIRCR can be changed. + 0x0 + + + Locked + Prevents changes to both VTOR and AIRCR. + 0x1 + + + + + LOCKVTORNS + Locks the Vector table Offset Register (VTOR) for non-secure mode. + 1 + 1 + + + NotLocked + VTOR can be changed. + 0x0 + + + Locked + Prevents changes to VTOR. + 0x1 + + + + + LOCKMPUS + Locks the Memory Protection Unit (MPU) for secure mode. + 2 + 2 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKMPUNS + Locks the Memory Protection Unit (MPU) for non secure mode. + 3 + 3 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKSAU + Locks the Security Attribution Unit (SAU) + 4 + 4 + + + NotLocked + SAU registers can be changed. + 0x0 + + + Locked + Prevents changes to SAU registers. + 0x1 + + + + + + + CPUID + The identifier for the CPU in this subsystem. + 0x504 + read-only + 0x00000000 + 0x20 + + + CPUID + The CPU identifier. + 0 + 31 + + + + + + + ICACHE_S + Cache 0 + 0xE0082000 + CACHE + + + + 0 + 0x1000 + registers + + CACHE + 0x20 + + + TASKS_SAVE + Save the cache state to a retained memory space. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SAVE + Save the cache state to a retained memory space. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESTORE + Restore the cache state from a retained memory space. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESTORE + Restore the cache state from a retained memory space. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEANCACHE + Clean the cache. + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEANCACHE + Clean the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSHCACHE + Flush the cache. + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHCACHE + Flush the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_INVALIDATELINE + Invalidate the line. + 0x014 + write-only + 0x00000000 + 0x20 + + + + TASKS_INVALIDATELINE + Invalidate the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEANLINE + Clean the line. + 0x018 + write-only + 0x00000000 + 0x20 + + + + TASKS_CLEANLINE + Clean the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSHLINE + Flush the line. + 0x01C + write-only + 0x00000000 + 0x20 + + + + TASKS_FLUSHLINE + Flush the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_ERASE + Erase the cache. + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_ERASE + Erase the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_DONE + Save or Restore task is done. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + Save or Restore task is done. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + DONE + Enable or disable interrupt for event DONE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DONE + Write '1' to enable interrupt for event DONE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DONE + Write '1' to disable interrupt for event DONE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + DONE + Read pending status of interrupt for event DONE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + Status of the cache activities. + 0x400 + read-only + 0x00000000 + 0x20 + + + BUSY + Busy status. + 0 + 0 + + + Ready + Activity is done and ready for the next activity. + 0x0 + + + Busy + Activity is in progress. + 0x1 + + + + + + + ENABLE + Enable cache. + 0x404 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable cache + 0 + 0 + + + Disabled + Disable cache + 0x0 + + + Enabled + Enable cache + 0x1 + + + + + + + LINEADDR + Memory address covered by the line to be maintained. + 0x410 + read-write + 0x00000000 + 0x20 + + + ADDR + Address. + 0 + 31 + + + + + PROFILING + Unspecified + CACHE_PROFILING + read-write + 0x414 + + ENABLE + Enable the profiling counters. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable the profiling counters + 0 + 0 + + + Disable + Disable profiling + 0x0 + + + Enable + Enable profiling + 0x1 + + + + + + + CLEAR + Clear the profiling counters. + 0x004 + write-only + 0x00000000 + 0x20 + + + CLEAR + Clearing the profiling counters + 0 + 0 + + + Clear + Clear the profiling counters + 0x1 + + + + + + + HIT + The cache hit counter for cache region. + 0x008 + read-only + 0x00000000 + 0x20 + + + HITS + Number of cache hits + 0 + 31 + + + + + MISS + The cache miss counter for cache region. + 0x00C + read-only + 0x00000000 + 0x20 + + + MISSES + Number of cache misses + 0 + 31 + + + + + LMISS + The cache line miss counter for cache region. + 0x010 + read-only + 0x00000000 + 0x20 + + + LMISSES + Number of cache line misses + 0 + 31 + + + + + READS + Number of reads for cache region. + 0x014 + read-only + 0x00000000 + 0x20 + + + READS + Number of reads for cache region. + 0 + 31 + + + + + WRITES + Number of writes for cache region. + 0x018 + read-only + 0x00000000 + 0x20 + + + WRITES + Number of writes for cache region. + 0 + 31 + + + + + + DEBUGLOCK + Lock debug mode. + 0x430 + read-writeonce + 0x00000000 + 0x20 + + + DEBUGLOCK + Lock debug mode + 0 + 0 + + + Unlocked + Debug mode unlocked + 0x0 + + + Locked + Debug mode locked. Ignores any other value written. + 0x1 + + + + + + + WRITELOCK + Lock cache updates. + 0x434 + read-write + 0x00000000 + 0x20 + + + WRITELOCK + Lock cache updates + 0 + 0 + + + Unlocked + Cache updates unlocked + 0x0 + + + Locked + Cache updates locked + 0x1 + + + + + + + + + DCACHE_S + Cache 1 + 0xE0083000 + + + + + SPU000_S + System protection unit 0 + 0x52000000 + SPU + + + + 0 + 0x1000 + registers + + + SPU000 + 0 + + SPU + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + PERIPHACCERR + Read pending status of interrupt for event PERIPHACCERR + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + PERIPHACCERR + Unspecified + SPU_PERIPHACCERR + read-write + 0x404 + + ADDRESS + Address of the transaction that caused first error. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Address + 0 + 15 + + + + + INFO + Information about the transaction that caused first error. + 0x004 + read-only + 0x00000000 + 0x20 + + + OWNERID + OWNERID + 0 + 3 + + + + + + 32 + 0x004 + PERIPH[%s] + Unspecified + SPU_PERIPH + read-write + 0x500 + + PERM + Description cluster: Get and set the applicable access permissions for the peripheral slave index n + 0x000 + read-write + 0x8000000A + 0x20 + + + SECUREMAPPING + Read capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0x0 + + + Secure + This peripheral is always accessible as a secure peripheral + 0x1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPH[n].PERM register + 0x2 + + + Split + This peripheral implements the split security mechanism. + 0x3 + + + + + DMA + Read the peripheral DMA capabilities + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0x0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 0x1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 0x2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + LOCK + Register lock + 8 + 8 + oneToSet + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can not be changed until the next reset + 0x1 + + + + + OWNERID + Peripheral owner ID + 16 + 19 + + + OWNERPROG + Indicates if OWNERID is programmable or not + 30 + 30 + read-only + + + NotProgrammable + OWNERID is not programmable + 0x0 + + + Programmable + OWNERID is programmable + 0x1 + + + + + PRESENT + Indicates if a peripheral is present with peripheral slave index n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0x0 + + + IsPresent + Peripheral is present + 0x1 + + + + + + + + FEATURE + Unspecified + SPU_FEATURE + read-write + 0x600 + + STRUCT0 + Unspecified + SPU_FEATURE_STRUCT0 + read-write + 0x000 + + IPCT + Unspecified + SPU_FEATURE_STRUCT0_IPCT + read-write + 0x000 + + 0x18 + 0x4 + CH[%s] + Description collection: Configuration of features for channel n of IPCT + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt n of IPCT + 0x060 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + DPPIC + Unspecified + SPU_FEATURE_STRUCT0_DPPIC + read-write + 0x080 + + 0x18 + 0x4 + CH[%s] + Description collection: Configuration of features for channel n of DPPIC + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + CHG[%s] + Description collection: Configuration of features for channel group n of DPPIC + 0x060 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + 2 + 0x040 + GPIOTE[%s] + Unspecified + SPU_FEATURE_STRUCT0_GPIOTE + read-write + 0x100 + + 0x8 + 0x4 + CH[%s] + Description collection: Configuration of features for channel o of GPIOTE[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt o of GPIOTE[n] + 0x020 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + 14 + 0x080 + GPIO[%s] + Unspecified + GPIO + read-write + 0x200 + + 0x20 + 0x4 + PIN[%s] + Description collection: Configuration of features for GPIO[n] PIN[o] + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + STRUCT0 + Unspecified + STRUCT0 + GPIO[%s] + read-write + 0x200 + + GRTC + Unspecified + STRUCT0_GRTC + read-write + 0x000 + + 0x10 + 0x4 + CC[%s] + Description collection: Configuration of features for CC n of GRTC + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + PWMCONFIG + Configuration of feature for PWMCONFIG of GRTC + 0x074 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + CLK + Configuration of features for CLKOUT/CLKCFG of GRTC + 0x078 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + SYSCOUNTER + Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC + 0x07C + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0xD + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt n of GRTC + 0x080 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + 2 + 0x00C + MRAMC[%s] + Unspecified + MRAMC + GPIO[%s] + read-write + 0x200 + + WAITSTATES + Description cluster: Configuration of features for WAITSTATES of MRAMC [n] + 0x400 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + AUTODPOWERDOWN + Description cluster: Configuration of features for POWER.AUTODPOWERDOWN of MRAMC [n] + 0x404 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + READY + Description cluster: Configuration of features for READY and READYNEXT of MRAMC [n] + 0x408 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + BELLS + Unspecified + SPU_FEATURE_BELLS + STRUCT0 + read-write + 0x000 + + 8 + 0x0C0 + PROCESSOR[%s] + Unspecified + SPU_FEATURE_BELLS_PROCESSOR + read-write + 0x000 + + 0x10 + 0x4 + TASKS[%s] + Description collection: Configuration of features for tasks pair [(o * 2) + 1:o * 2] of Processor ID n + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x10 + 0x4 + EVENTS[%s] + Description collection: Configuration of features for events pair [(o * 2) + 1:o * 2] of Processor ID n + 0x040 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x10 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt register pair [(o * 2) + 1:o * 2] of Processor ID n + 0x080 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + + + + MPC_S + Memory Privilege Controller + 0x52001000 + MPC + + + + 0 + 0x1000 + registers + + + MPC + 1 + + MPC + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Enable or disable interrupt for event MEMACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to enable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to disable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MEMACCERR + Memory Access Error status registers + MPC_MEMACCERR + read-write + 0x400 + + ADDRESS + Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is active. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Target address for erroneous access + 0 + 31 + + + + + INFO + Access information for the transaction that triggered a memory access error. Register content won't be changed as long as MEMACCERR event is active. + 0x004 + read-only + 0x00000000 + 0x20 + + + OWNERID + Owner identifier of the erroneous access + 0 + 3 + + + MASTERPORT + Master port where erroneous access is detected + 4 + 8 + + + READ + Read bit of bus access + 12 + 12 + + + Set + Read access bit was set + 0x1 + + + NotSet + Read access bit was not set + 0x0 + + + + + WRITE + Write bit of bus access + 13 + 13 + + + Set + Write access bit was set + 0x1 + + + NotSet + Write access bit was not set + 0x0 + + + + + EXECUTE + Execute bit of bus access + 14 + 14 + + + Set + Execute access bit was set + 0x1 + + + NotSet + Execute access bit was not set + 0x0 + + + + + SECURE + Secure bit of bus access + 15 + 15 + + + Set + Secure access bit was set + 0x1 + + + NotSet + Secure access bit was not set + 0x0 + + + + + ERRORSOURCE + Source of memory access error + 16 + 16 + + + MPC + Error was triggered by MPC module + 0x1 + + + Slave + Error was triggered by an AXI slave + 0x0 + + + + + + + + GLOBALSLAVE + Global slave master port connection information + MPC_GLOBALSLAVE + read-write + 0x410 + + MASTERPORT + Global slave connection information for master port + 0x000 + read-write + 0x00000000 + 0x20 + + + CONNECTION_0 + Global slave connection information for master port + 0 + 0 + + + Disabled + Master port 0 connection to global slave is disabled + 0x0 + + + Enabled + Master port 0 connection to global slave is enabled + 0x1 + + + + + CONNECTION_1 + Global slave connection information for master port + 1 + 1 + + + Disabled + Master port 1 connection to global slave is disabled + 0x0 + + + Enabled + Master port 1 connection to global slave is enabled + 0x1 + + + + + CONNECTION_2 + Global slave connection information for master port + 2 + 2 + + + Disabled + Master port 2 connection to global slave is disabled + 0x0 + + + Enabled + Master port 2 connection to global slave is enabled + 0x1 + + + + + CONNECTION_3 + Global slave connection information for master port + 3 + 3 + + + Disabled + Master port 3 connection to global slave is disabled + 0x0 + + + Enabled + Master port 3 connection to global slave is enabled + 0x1 + + + + + CONNECTION_4 + Global slave connection information for master port + 4 + 4 + + + Disabled + Master port 4 connection to global slave is disabled + 0x0 + + + Enabled + Master port 4 connection to global slave is enabled + 0x1 + + + + + CONNECTION_5 + Global slave connection information for master port + 5 + 5 + + + Disabled + Master port 5 connection to global slave is disabled + 0x0 + + + Enabled + Master port 5 connection to global slave is enabled + 0x1 + + + + + CONNECTION_6 + Global slave connection information for master port + 6 + 6 + + + Disabled + Master port 6 connection to global slave is disabled + 0x0 + + + Enabled + Master port 6 connection to global slave is enabled + 0x1 + + + + + CONNECTION_7 + Global slave connection information for master port + 7 + 7 + + + Disabled + Master port 7 connection to global slave is disabled + 0x0 + + + Enabled + Master port 7 connection to global slave is enabled + 0x1 + + + + + CONNECTION_8 + Global slave connection information for master port + 8 + 8 + + + Disabled + Master port 8 connection to global slave is disabled + 0x0 + + + Enabled + Master port 8 connection to global slave is enabled + 0x1 + + + + + CONNECTION_9 + Global slave connection information for master port + 9 + 9 + + + Disabled + Master port 9 connection to global slave is disabled + 0x0 + + + Enabled + Master port 9 connection to global slave is enabled + 0x1 + + + + + CONNECTION_10 + Global slave connection information for master port + 10 + 10 + + + Disabled + Master port 10 connection to global slave is disabled + 0x0 + + + Enabled + Master port 10 connection to global slave is enabled + 0x1 + + + + + CONNECTION_11 + Global slave connection information for master port + 11 + 11 + + + Disabled + Master port 11 connection to global slave is disabled + 0x0 + + + Enabled + Master port 11 connection to global slave is enabled + 0x1 + + + + + CONNECTION_12 + Global slave connection information for master port + 12 + 12 + + + Disabled + Master port 12 connection to global slave is disabled + 0x0 + + + Enabled + Master port 12 connection to global slave is enabled + 0x1 + + + + + CONNECTION_13 + Global slave connection information for master port + 13 + 13 + + + Disabled + Master port 13 connection to global slave is disabled + 0x0 + + + Enabled + Master port 13 connection to global slave is enabled + 0x1 + + + + + CONNECTION_14 + Global slave connection information for master port + 14 + 14 + + + Disabled + Master port 14 connection to global slave is disabled + 0x0 + + + Enabled + Master port 14 connection to global slave is enabled + 0x1 + + + + + CONNECTION_15 + Global slave connection information for master port + 15 + 15 + + + Disabled + Master port 15 connection to global slave is disabled + 0x0 + + + Enabled + Master port 15 connection to global slave is enabled + 0x1 + + + + + CONNECTION_16 + Global slave connection information for master port + 16 + 16 + + + Disabled + Master port 16 connection to global slave is disabled + 0x0 + + + Enabled + Master port 16 connection to global slave is enabled + 0x1 + + + + + CONNECTION_17 + Global slave connection information for master port + 17 + 17 + + + Disabled + Master port 17 connection to global slave is disabled + 0x0 + + + Enabled + Master port 17 connection to global slave is enabled + 0x1 + + + + + CONNECTION_18 + Global slave connection information for master port + 18 + 18 + + + Disabled + Master port 18 connection to global slave is disabled + 0x0 + + + Enabled + Master port 18 connection to global slave is enabled + 0x1 + + + + + CONNECTION_19 + Global slave connection information for master port + 19 + 19 + + + Disabled + Master port 19 connection to global slave is disabled + 0x0 + + + Enabled + Master port 19 connection to global slave is enabled + 0x1 + + + + + CONNECTION_20 + Global slave connection information for master port + 20 + 20 + + + Disabled + Master port 20 connection to global slave is disabled + 0x0 + + + Enabled + Master port 20 connection to global slave is enabled + 0x1 + + + + + CONNECTION_21 + Global slave connection information for master port + 21 + 21 + + + Disabled + Master port 21 connection to global slave is disabled + 0x0 + + + Enabled + Master port 21 connection to global slave is enabled + 0x1 + + + + + CONNECTION_22 + Global slave connection information for master port + 22 + 22 + + + Disabled + Master port 22 connection to global slave is disabled + 0x0 + + + Enabled + Master port 22 connection to global slave is enabled + 0x1 + + + + + CONNECTION_23 + Global slave connection information for master port + 23 + 23 + + + Disabled + Master port 23 connection to global slave is disabled + 0x0 + + + Enabled + Master port 23 connection to global slave is enabled + 0x1 + + + + + CONNECTION_24 + Global slave connection information for master port + 24 + 24 + + + Disabled + Master port 24 connection to global slave is disabled + 0x0 + + + Enabled + Master port 24 connection to global slave is enabled + 0x1 + + + + + CONNECTION_25 + Global slave connection information for master port + 25 + 25 + + + Disabled + Master port 25 connection to global slave is disabled + 0x0 + + + Enabled + Master port 25 connection to global slave is enabled + 0x1 + + + + + CONNECTION_26 + Global slave connection information for master port + 26 + 26 + + + Disabled + Master port 26 connection to global slave is disabled + 0x0 + + + Enabled + Master port 26 connection to global slave is enabled + 0x1 + + + + + CONNECTION_27 + Global slave connection information for master port + 27 + 27 + + + Disabled + Master port 27 connection to global slave is disabled + 0x0 + + + Enabled + Master port 27 connection to global slave is enabled + 0x1 + + + + + CONNECTION_28 + Global slave connection information for master port + 28 + 28 + + + Disabled + Master port 28 connection to global slave is disabled + 0x0 + + + Enabled + Master port 28 connection to global slave is enabled + 0x1 + + + + + CONNECTION_29 + Global slave connection information for master port + 29 + 29 + + + Disabled + Master port 29 connection to global slave is disabled + 0x0 + + + Enabled + Master port 29 connection to global slave is enabled + 0x1 + + + + + CONNECTION_30 + Global slave connection information for master port + 30 + 30 + + + Disabled + Master port 30 connection to global slave is disabled + 0x0 + + + Enabled + Master port 30 connection to global slave is enabled + 0x1 + + + + + CONNECTION_31 + Global slave connection information for master port + 31 + 31 + + + Disabled + Master port 31 connection to global slave is disabled + 0x0 + + + Enabled + Master port 31 connection to global slave is enabled + 0x1 + + + + + + + LOCK + Lock global slave registers + 0x004 + read-write + 0x00000000 + 0x20 + + + LOCK + Enable lock + 0 + 0 + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + + + + EXTENDCLKREQ + Extend clock request configuration + 0x418 + read-write + 0x00000003 + 0x20 + + + INIT + Initial value of the down counter used for extending the clock request. + 0 + 15 + + + ENABLE + Enable the extend clock request feature + 31 + 31 + + + Disable + Disable + 0x0 + + + Enable + Enable + 0x1 + + + + + + + RTCHOKE + Real time choke configuration for AXI master port + MPC_RTCHOKE + read-write + 0x420 + + WRITEACCESS + Enable AXI Write Address Channel Real Time Choke for master port + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable Real Time Choke for Write Address Channel + 0 + 0 + + + Disable + Real Time Choke is disabled for master port 0 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 0 Write Address Channel + 0x1 + + + + + ENABLE_1 + Enable Real Time Choke for Write Address Channel + 1 + 1 + + + Disable + Real Time Choke is disabled for master port 1 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 1 Write Address Channel + 0x1 + + + + + ENABLE_2 + Enable Real Time Choke for Write Address Channel + 2 + 2 + + + Disable + Real Time Choke is disabled for master port 2 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 2 Write Address Channel + 0x1 + + + + + ENABLE_3 + Enable Real Time Choke for Write Address Channel + 3 + 3 + + + Disable + Real Time Choke is disabled for master port 3 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 3 Write Address Channel + 0x1 + + + + + ENABLE_4 + Enable Real Time Choke for Write Address Channel + 4 + 4 + + + Disable + Real Time Choke is disabled for master port 4 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 4 Write Address Channel + 0x1 + + + + + ENABLE_5 + Enable Real Time Choke for Write Address Channel + 5 + 5 + + + Disable + Real Time Choke is disabled for master port 5 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 5 Write Address Channel + 0x1 + + + + + ENABLE_6 + Enable Real Time Choke for Write Address Channel + 6 + 6 + + + Disable + Real Time Choke is disabled for master port 6 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 6 Write Address Channel + 0x1 + + + + + ENABLE_7 + Enable Real Time Choke for Write Address Channel + 7 + 7 + + + Disable + Real Time Choke is disabled for master port 7 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 7 Write Address Channel + 0x1 + + + + + ENABLE_8 + Enable Real Time Choke for Write Address Channel + 8 + 8 + + + Disable + Real Time Choke is disabled for master port 8 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 8 Write Address Channel + 0x1 + + + + + ENABLE_9 + Enable Real Time Choke for Write Address Channel + 9 + 9 + + + Disable + Real Time Choke is disabled for master port 9 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 9 Write Address Channel + 0x1 + + + + + ENABLE_10 + Enable Real Time Choke for Write Address Channel + 10 + 10 + + + Disable + Real Time Choke is disabled for master port 10 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 10 Write Address Channel + 0x1 + + + + + ENABLE_11 + Enable Real Time Choke for Write Address Channel + 11 + 11 + + + Disable + Real Time Choke is disabled for master port 11 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 11 Write Address Channel + 0x1 + + + + + ENABLE_12 + Enable Real Time Choke for Write Address Channel + 12 + 12 + + + Disable + Real Time Choke is disabled for master port 12 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 12 Write Address Channel + 0x1 + + + + + ENABLE_13 + Enable Real Time Choke for Write Address Channel + 13 + 13 + + + Disable + Real Time Choke is disabled for master port 13 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 13 Write Address Channel + 0x1 + + + + + ENABLE_14 + Enable Real Time Choke for Write Address Channel + 14 + 14 + + + Disable + Real Time Choke is disabled for master port 14 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 14 Write Address Channel + 0x1 + + + + + ENABLE_15 + Enable Real Time Choke for Write Address Channel + 15 + 15 + + + Disable + Real Time Choke is disabled for master port 15 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 15 Write Address Channel + 0x1 + + + + + ENABLE_16 + Enable Real Time Choke for Write Address Channel + 16 + 16 + + + Disable + Real Time Choke is disabled for master port 16 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 16 Write Address Channel + 0x1 + + + + + ENABLE_17 + Enable Real Time Choke for Write Address Channel + 17 + 17 + + + Disable + Real Time Choke is disabled for master port 17 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 17 Write Address Channel + 0x1 + + + + + ENABLE_18 + Enable Real Time Choke for Write Address Channel + 18 + 18 + + + Disable + Real Time Choke is disabled for master port 18 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 18 Write Address Channel + 0x1 + + + + + ENABLE_19 + Enable Real Time Choke for Write Address Channel + 19 + 19 + + + Disable + Real Time Choke is disabled for master port 19 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 19 Write Address Channel + 0x1 + + + + + ENABLE_20 + Enable Real Time Choke for Write Address Channel + 20 + 20 + + + Disable + Real Time Choke is disabled for master port 20 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 20 Write Address Channel + 0x1 + + + + + ENABLE_21 + Enable Real Time Choke for Write Address Channel + 21 + 21 + + + Disable + Real Time Choke is disabled for master port 21 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 21 Write Address Channel + 0x1 + + + + + ENABLE_22 + Enable Real Time Choke for Write Address Channel + 22 + 22 + + + Disable + Real Time Choke is disabled for master port 22 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 22 Write Address Channel + 0x1 + + + + + ENABLE_23 + Enable Real Time Choke for Write Address Channel + 23 + 23 + + + Disable + Real Time Choke is disabled for master port 23 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 23 Write Address Channel + 0x1 + + + + + ENABLE_24 + Enable Real Time Choke for Write Address Channel + 24 + 24 + + + Disable + Real Time Choke is disabled for master port 24 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 24 Write Address Channel + 0x1 + + + + + ENABLE_25 + Enable Real Time Choke for Write Address Channel + 25 + 25 + + + Disable + Real Time Choke is disabled for master port 25 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 25 Write Address Channel + 0x1 + + + + + ENABLE_26 + Enable Real Time Choke for Write Address Channel + 26 + 26 + + + Disable + Real Time Choke is disabled for master port 26 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 26 Write Address Channel + 0x1 + + + + + ENABLE_27 + Enable Real Time Choke for Write Address Channel + 27 + 27 + + + Disable + Real Time Choke is disabled for master port 27 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 27 Write Address Channel + 0x1 + + + + + ENABLE_28 + Enable Real Time Choke for Write Address Channel + 28 + 28 + + + Disable + Real Time Choke is disabled for master port 28 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 28 Write Address Channel + 0x1 + + + + + ENABLE_29 + Enable Real Time Choke for Write Address Channel + 29 + 29 + + + Disable + Real Time Choke is disabled for master port 29 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 29 Write Address Channel + 0x1 + + + + + ENABLE_30 + Enable Real Time Choke for Write Address Channel + 30 + 30 + + + Disable + Real Time Choke is disabled for master port 30 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 30 Write Address Channel + 0x1 + + + + + ENABLE_31 + Enable Real Time Choke for Write Address Channel + 31 + 31 + + + Disable + Real Time Choke is disabled for master port 31 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 31 Write Address Channel + 0x1 + + + + + + + READACCESS + Enable AXI Read Address Channel Real Time Choke for master port + 0x004 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable Real Time Choke for Read Address Channel + 0 + 0 + + + Disable + Real Time Choke is disabled for master port 0 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 0 Read Address Channel + 0x1 + + + + + ENABLE_1 + Enable Real Time Choke for Read Address Channel + 1 + 1 + + + Disable + Real Time Choke is disabled for master port 1 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 1 Read Address Channel + 0x1 + + + + + ENABLE_2 + Enable Real Time Choke for Read Address Channel + 2 + 2 + + + Disable + Real Time Choke is disabled for master port 2 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 2 Read Address Channel + 0x1 + + + + + ENABLE_3 + Enable Real Time Choke for Read Address Channel + 3 + 3 + + + Disable + Real Time Choke is disabled for master port 3 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 3 Read Address Channel + 0x1 + + + + + ENABLE_4 + Enable Real Time Choke for Read Address Channel + 4 + 4 + + + Disable + Real Time Choke is disabled for master port 4 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 4 Read Address Channel + 0x1 + + + + + ENABLE_5 + Enable Real Time Choke for Read Address Channel + 5 + 5 + + + Disable + Real Time Choke is disabled for master port 5 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 5 Read Address Channel + 0x1 + + + + + ENABLE_6 + Enable Real Time Choke for Read Address Channel + 6 + 6 + + + Disable + Real Time Choke is disabled for master port 6 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 6 Read Address Channel + 0x1 + + + + + ENABLE_7 + Enable Real Time Choke for Read Address Channel + 7 + 7 + + + Disable + Real Time Choke is disabled for master port 7 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 7 Read Address Channel + 0x1 + + + + + ENABLE_8 + Enable Real Time Choke for Read Address Channel + 8 + 8 + + + Disable + Real Time Choke is disabled for master port 8 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 8 Read Address Channel + 0x1 + + + + + ENABLE_9 + Enable Real Time Choke for Read Address Channel + 9 + 9 + + + Disable + Real Time Choke is disabled for master port 9 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 9 Read Address Channel + 0x1 + + + + + ENABLE_10 + Enable Real Time Choke for Read Address Channel + 10 + 10 + + + Disable + Real Time Choke is disabled for master port 10 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 10 Read Address Channel + 0x1 + + + + + ENABLE_11 + Enable Real Time Choke for Read Address Channel + 11 + 11 + + + Disable + Real Time Choke is disabled for master port 11 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 11 Read Address Channel + 0x1 + + + + + ENABLE_12 + Enable Real Time Choke for Read Address Channel + 12 + 12 + + + Disable + Real Time Choke is disabled for master port 12 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 12 Read Address Channel + 0x1 + + + + + ENABLE_13 + Enable Real Time Choke for Read Address Channel + 13 + 13 + + + Disable + Real Time Choke is disabled for master port 13 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 13 Read Address Channel + 0x1 + + + + + ENABLE_14 + Enable Real Time Choke for Read Address Channel + 14 + 14 + + + Disable + Real Time Choke is disabled for master port 14 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 14 Read Address Channel + 0x1 + + + + + ENABLE_15 + Enable Real Time Choke for Read Address Channel + 15 + 15 + + + Disable + Real Time Choke is disabled for master port 15 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 15 Read Address Channel + 0x1 + + + + + ENABLE_16 + Enable Real Time Choke for Read Address Channel + 16 + 16 + + + Disable + Real Time Choke is disabled for master port 16 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 16 Read Address Channel + 0x1 + + + + + ENABLE_17 + Enable Real Time Choke for Read Address Channel + 17 + 17 + + + Disable + Real Time Choke is disabled for master port 17 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 17 Read Address Channel + 0x1 + + + + + ENABLE_18 + Enable Real Time Choke for Read Address Channel + 18 + 18 + + + Disable + Real Time Choke is disabled for master port 18 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 18 Read Address Channel + 0x1 + + + + + ENABLE_19 + Enable Real Time Choke for Read Address Channel + 19 + 19 + + + Disable + Real Time Choke is disabled for master port 19 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 19 Read Address Channel + 0x1 + + + + + ENABLE_20 + Enable Real Time Choke for Read Address Channel + 20 + 20 + + + Disable + Real Time Choke is disabled for master port 20 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 20 Read Address Channel + 0x1 + + + + + ENABLE_21 + Enable Real Time Choke for Read Address Channel + 21 + 21 + + + Disable + Real Time Choke is disabled for master port 21 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 21 Read Address Channel + 0x1 + + + + + ENABLE_22 + Enable Real Time Choke for Read Address Channel + 22 + 22 + + + Disable + Real Time Choke is disabled for master port 22 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 22 Read Address Channel + 0x1 + + + + + ENABLE_23 + Enable Real Time Choke for Read Address Channel + 23 + 23 + + + Disable + Real Time Choke is disabled for master port 23 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 23 Read Address Channel + 0x1 + + + + + ENABLE_24 + Enable Real Time Choke for Read Address Channel + 24 + 24 + + + Disable + Real Time Choke is disabled for master port 24 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 24 Read Address Channel + 0x1 + + + + + ENABLE_25 + Enable Real Time Choke for Read Address Channel + 25 + 25 + + + Disable + Real Time Choke is disabled for master port 25 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 25 Read Address Channel + 0x1 + + + + + ENABLE_26 + Enable Real Time Choke for Read Address Channel + 26 + 26 + + + Disable + Real Time Choke is disabled for master port 26 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 26 Read Address Channel + 0x1 + + + + + ENABLE_27 + Enable Real Time Choke for Read Address Channel + 27 + 27 + + + Disable + Real Time Choke is disabled for master port 27 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 27 Read Address Channel + 0x1 + + + + + ENABLE_28 + Enable Real Time Choke for Read Address Channel + 28 + 28 + + + Disable + Real Time Choke is disabled for master port 28 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 28 Read Address Channel + 0x1 + + + + + ENABLE_29 + Enable Real Time Choke for Read Address Channel + 29 + 29 + + + Disable + Real Time Choke is disabled for master port 29 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 29 Read Address Channel + 0x1 + + + + + ENABLE_30 + Enable Real Time Choke for Read Address Channel + 30 + 30 + + + Disable + Real Time Choke is disabled for master port 30 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 30 Read Address Channel + 0x1 + + + + + ENABLE_31 + Enable Real Time Choke for Read Address Channel + 31 + 31 + + + Disable + Real Time Choke is disabled for master port 31 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 31 Read Address Channel + 0x1 + + + + + + + 0x20 + 0x4 + DELAY[%s] + Description collection: Real Time Choke delay value for slave number n + 0x60 + read-write + 0x00000000 + 0x20 + + + DELAY + Real Time Choke delay in bus clock cycles. + 0 + 7 + + + + + + 32 + 0x010 + REGION[%s] + Memory region to slave decoding table + MPC_REGION + read-write + 0x600 + + CONFIG + Description cluster: Slave region n Configuration register + 0x000 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Locks the region n setting + 8 + 8 + read-writeonce + + + Unlocked + Region n settings can be updated + 0x0 + + + Locked + Region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Region n enable + 9 + 9 + + + Disabled + Region n is not used + 0x0 + + + Enabled + Region n is used + 0x1 + + + + + READ + Read access + 12 + 12 + + + NotAllowed + Read access to region n is not allowed + 0x0 + + + Allowed + Read access to region n is allowed + 0x1 + + + + + WRITE + Write access + 13 + 13 + + + NotAllowed + Write access to region n is not allowed + 0x0 + + + Allowed + Write access to region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 14 + 14 + + + NotAllowed + Software execution from region n is not allowed + 0x0 + + + Allowed + Software execution from region n is allowed + 0x1 + + + + + SECATTR + Memory security mapping + 15 + 15 + + + Secure + Memory is mapped in secure memory address space + 0x1 + + + NonSecure + Memory is mapped in non-secure memory address space + 0x0 + + + + + OWNERID + Region owner identifier. + 16 + 19 + + + + + STARTADDR + Description cluster: Region n start address + 0x004 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for memory region n + 0 + 31 + + + + + ADDRMASK + Description cluster: Select which bits of the incoming address are compared against the STARTADDR + 0x008 + read-write + 0x00000000 + 0x20 + + + ADDRMASK + Address mask for memory region n + 0 + 31 + + + + + MASTERPORT + Description cluster: Region n local master enable + 0x00C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable region n for master port 0 + 0 + 0 + + + Disable + Region n is disabled for master port 0 + 0x0 + + + Enable + Region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable region n for master port 1 + 1 + 1 + + + Disable + Region n is disabled for master port 1 + 0x0 + + + Enable + Region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable region n for master port 2 + 2 + 2 + + + Disable + Region n is disabled for master port 2 + 0x0 + + + Enable + Region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable region n for master port 3 + 3 + 3 + + + Disable + Region n is disabled for master port 3 + 0x0 + + + Enable + Region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable region n for master port 4 + 4 + 4 + + + Disable + Region n is disabled for master port 4 + 0x0 + + + Enable + Region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable region n for master port 5 + 5 + 5 + + + Disable + Region n is disabled for master port 5 + 0x0 + + + Enable + Region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable region n for master port 6 + 6 + 6 + + + Disable + Region n is disabled for master port 6 + 0x0 + + + Enable + Region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable region n for master port 7 + 7 + 7 + + + Disable + Region n is disabled for master port 7 + 0x0 + + + Enable + Region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable region n for master port 8 + 8 + 8 + + + Disable + Region n is disabled for master port 8 + 0x0 + + + Enable + Region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable region n for master port 9 + 9 + 9 + + + Disable + Region n is disabled for master port 9 + 0x0 + + + Enable + Region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable region n for master port 10 + 10 + 10 + + + Disable + Region n is disabled for master port 10 + 0x0 + + + Enable + Region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable region n for master port 11 + 11 + 11 + + + Disable + Region n is disabled for master port 11 + 0x0 + + + Enable + Region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable region n for master port 12 + 12 + 12 + + + Disable + Region n is disabled for master port 12 + 0x0 + + + Enable + Region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable region n for master port 13 + 13 + 13 + + + Disable + Region n is disabled for master port 13 + 0x0 + + + Enable + Region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable region n for master port 14 + 14 + 14 + + + Disable + Region n is disabled for master port 14 + 0x0 + + + Enable + Region n is enabled for master port 14 + 0x1 + + + + + ENABLE15 + Enable region n for master port 15 + 15 + 15 + + + Disable + Region n is disabled for master port 15 + 0x0 + + + Enable + Region n is enabled for master port 15 + 0x1 + + + + + ENABLE16 + Enable region n for master port 16 + 16 + 16 + + + Disable + Region n is disabled for master port 16 + 0x0 + + + Enable + Region n is enabled for master port 16 + 0x1 + + + + + ENABLE17 + Enable region n for master port 17 + 17 + 17 + + + Disable + Region n is disabled for master port 17 + 0x0 + + + Enable + Region n is enabled for master port 17 + 0x1 + + + + + ENABLE18 + Enable region n for master port 18 + 18 + 18 + + + Disable + Region n is disabled for master port 18 + 0x0 + + + Enable + Region n is enabled for master port 18 + 0x1 + + + + + ENABLE19 + Enable region n for master port 19 + 19 + 19 + + + Disable + Region n is disabled for master port 19 + 0x0 + + + Enable + Region n is enabled for master port 19 + 0x1 + + + + + ENABLE20 + Enable region n for master port 20 + 20 + 20 + + + Disable + Region n is disabled for master port 20 + 0x0 + + + Enable + Region n is enabled for master port 20 + 0x1 + + + + + ENABLE21 + Enable region n for master port 21 + 21 + 21 + + + Disable + Region n is disabled for master port 21 + 0x0 + + + Enable + Region n is enabled for master port 21 + 0x1 + + + + + ENABLE22 + Enable region n for master port 22 + 22 + 22 + + + Disable + Region n is disabled for master port 22 + 0x0 + + + Enable + Region n is enabled for master port 22 + 0x1 + + + + + ENABLE23 + Enable region n for master port 23 + 23 + 23 + + + Disable + Region n is disabled for master port 23 + 0x0 + + + Enable + Region n is enabled for master port 23 + 0x1 + + + + + ENABLE24 + Enable region n for master port 24 + 24 + 24 + + + Disable + Region n is disabled for master port 24 + 0x0 + + + Enable + Region n is enabled for master port 24 + 0x1 + + + + + ENABLE25 + Enable region n for master port 25 + 25 + 25 + + + Disable + Region n is disabled for master port 25 + 0x0 + + + Enable + Region n is enabled for master port 25 + 0x1 + + + + + ENABLE26 + Enable region n for master port 26 + 26 + 26 + + + Disable + Region n is disabled for master port 26 + 0x0 + + + Enable + Region n is enabled for master port 26 + 0x1 + + + + + ENABLE27 + Enable region n for master port 27 + 27 + 27 + + + Disable + Region n is disabled for master port 27 + 0x0 + + + Enable + Region n is enabled for master port 27 + 0x1 + + + + + ENABLE28 + Enable region n for master port 28 + 28 + 28 + + + Disable + Region n is disabled for master port 28 + 0x0 + + + Enable + Region n is enabled for master port 28 + 0x1 + + + + + ENABLE29 + Enable region n for master port 29 + 29 + 29 + + + Disable + Region n is disabled for master port 29 + 0x0 + + + Enable + Region n is enabled for master port 29 + 0x1 + + + + + ENABLE30 + Enable region n for master port 30 + 30 + 30 + + + Disable + Region n is disabled for master port 30 + 0x0 + + + Enable + Region n is enabled for master port 30 + 0x1 + + + + + ENABLE31 + Enable region n for master port 31 + 31 + 31 + + + Disable + Region n is disabled for master port 31 + 0x0 + + + Enable + Region n is enabled for master port 31 + 0x1 + + + + + + + + 40 + 0x020 + OVERRIDE[%s] + Special privilege tables + MPC_OVERRIDE + read-write + 0x800 + + CONFIG + Description cluster: Override region n Configuration register + 0x0 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for override region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Lock Override region n + 8 + 8 + read-writeonce + + + Unlocked + Override region n settings can be updated + 0x0 + + + Locked + Override region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Enable Override region n + 9 + 9 + + + Disabled + Override region n is not used + 0x0 + + + Enabled + Override region n is used + 0x1 + + + + + SECDOMENABLE + Secure domain access enable for Override region n + 10 + 10 + + + Disabled + Overriding of secure domain permissions is disabled for override region n + 0x0 + + + Enabled + Overriding of secure domain permissions is enabled for override region n + 0x1 + + + + + SECUREMASK + Secure mask enable for Override region n + 12 + 12 + read-only + + + Disabled + Mask is disabled for override region n + 0x0 + + + Enabled + Mask is enabled for override region n + 0x1 + + + + + + + STARTADDR + Description cluster: Override region n Start Address + 0x4 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for override region n + 0 + 31 + + + + + ENDADDR + Description cluster: Override region n End Address + 0x8 + read-write + 0x00000000 + 0x20 + + + ENDADDR + End address for override region n + 0 + 31 + + + + + OFFSET + Description cluster: Address offset value divided by 2 for override region n address re-map + 0x0C + read-write + 0x00000000 + int32_t + 0x20 + + + OFFSET + Offset value + 0 + 31 + + + + + PERM + Description cluster: Permission settings for override region n + 0x10 + read-write + 0x00000000 + 0x20 + + + READ + Read access + 0 + 0 + + + NotAllowed + Read access to override region n is not allowed + 0x0 + + + Allowed + Read access to override region n is allowed + 0x1 + + + + + WRITE + Write access + 1 + 1 + + + NotAllowed + Write access to override region n is not allowed + 0x0 + + + Allowed + Write access to override region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 2 + 2 + + + NotAllowed + Software execution from override region n is not allowed + 0x0 + + + Allowed + Software execution from override region n is allowed + 0x1 + + + + + SECATTR + Security mapping + 3 + 3 + + + Secure + Override region n is mapped in secure memory address space + 0x1 + + + NonSecure + Override region n is mapped in non-secure memory address space + 0x0 + + + + + + + PERMMASK + Description cluster: Masks permission setting fields from register OVERRIDE.PERM + 0x14 + read-write + 0x00000000 + 0x20 + + + READ + Read mask + 0 + 0 + + + Masked + Permission setting READ in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting READ in OVERRIDE register will be applied + 0x1 + + + + + WRITE + Write mask + 1 + 1 + + + Masked + Permission setting WRITE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting WRITE in OVERRIDE register will be applied + 0x1 + + + + + EXECUTE + Execute mask + 2 + 2 + + + Masked + Permission setting EXECUTE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting EXECUTE in OVERRIDE register will be applied + 0x1 + + + + + SECATTR + Security mapping mask + 3 + 3 + + + Masked + Permission setting SECATTR in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting SECATTR in OVERRIDE register will be applied + 0x1 + + + + + + + OWNER + Description cluster: Owner for override region + 0x18 + read-write + 0x00000000 + 0x20 + + + OWNERID + owner identifier for override region n + 0 + 3 + + + + + MASTERPORT + Description cluster: Override region n local master enable + 0x1C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable override + 0 + 0 + + + Disable + Override region n is disabled for master port 0 + 0x0 + + + Enable + Override region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable override + 1 + 1 + + + Disable + Override region n is disabled for master port 1 + 0x0 + + + Enable + Override region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable override + 2 + 2 + + + Disable + Override region n is disabled for master port 2 + 0x0 + + + Enable + Override region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable override + 3 + 3 + + + Disable + Override region n is disabled for master port 3 + 0x0 + + + Enable + Override region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable override + 4 + 4 + + + Disable + Override region n is disabled for master port 4 + 0x0 + + + Enable + Override region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable override + 5 + 5 + + + Disable + Override region n is disabled for master port 5 + 0x0 + + + Enable + Override region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable override + 6 + 6 + + + Disable + Override region n is disabled for master port 6 + 0x0 + + + Enable + Override region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable override + 7 + 7 + + + Disable + Override region n is disabled for master port 7 + 0x0 + + + Enable + Override region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable override + 8 + 8 + + + Disable + Override region n is disabled for master port 8 + 0x0 + + + Enable + Override region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable override + 9 + 9 + + + Disable + Override region n is disabled for master port 9 + 0x0 + + + Enable + Override region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable override + 10 + 10 + + + Disable + Override region n is disabled for master port 10 + 0x0 + + + Enable + Override region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable override + 11 + 11 + + + Disable + Override region n is disabled for master port 11 + 0x0 + + + Enable + Override region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable override + 12 + 12 + + + Disable + Override region n is disabled for master port 12 + 0x0 + + + Enable + Override region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable override + 13 + 13 + + + Disable + Override region n is disabled for master port 13 + 0x0 + + + Enable + Override region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable override + 14 + 14 + + + Disable + Override region n is disabled for master port 14 + 0x0 + + + Enable + Override region n is enabled for master port 14 + 0x1 + + + + + ENABLE15 + Enable override + 15 + 15 + + + Disable + Override region n is disabled for master port 15 + 0x0 + + + Enable + Override region n is enabled for master port 15 + 0x1 + + + + + ENABLE16 + Enable override + 16 + 16 + + + Disable + Override region n is disabled for master port 16 + 0x0 + + + Enable + Override region n is enabled for master port 16 + 0x1 + + + + + ENABLE17 + Enable override + 17 + 17 + + + Disable + Override region n is disabled for master port 17 + 0x0 + + + Enable + Override region n is enabled for master port 17 + 0x1 + + + + + ENABLE18 + Enable override + 18 + 18 + + + Disable + Override region n is disabled for master port 18 + 0x0 + + + Enable + Override region n is enabled for master port 18 + 0x1 + + + + + ENABLE19 + Enable override + 19 + 19 + + + Disable + Override region n is disabled for master port 19 + 0x0 + + + Enable + Override region n is enabled for master port 19 + 0x1 + + + + + ENABLE20 + Enable override + 20 + 20 + + + Disable + Override region n is disabled for master port 20 + 0x0 + + + Enable + Override region n is enabled for master port 20 + 0x1 + + + + + ENABLE21 + Enable override + 21 + 21 + + + Disable + Override region n is disabled for master port 21 + 0x0 + + + Enable + Override region n is enabled for master port 21 + 0x1 + + + + + ENABLE22 + Enable override + 22 + 22 + + + Disable + Override region n is disabled for master port 22 + 0x0 + + + Enable + Override region n is enabled for master port 22 + 0x1 + + + + + ENABLE23 + Enable override + 23 + 23 + + + Disable + Override region n is disabled for master port 23 + 0x0 + + + Enable + Override region n is enabled for master port 23 + 0x1 + + + + + ENABLE24 + Enable override + 24 + 24 + + + Disable + Override region n is disabled for master port 24 + 0x0 + + + Enable + Override region n is enabled for master port 24 + 0x1 + + + + + ENABLE25 + Enable override + 25 + 25 + + + Disable + Override region n is disabled for master port 25 + 0x0 + + + Enable + Override region n is enabled for master port 25 + 0x1 + + + + + ENABLE26 + Enable override + 26 + 26 + + + Disable + Override region n is disabled for master port 26 + 0x0 + + + Enable + Override region n is enabled for master port 26 + 0x1 + + + + + ENABLE27 + Enable override + 27 + 27 + + + Disable + Override region n is disabled for master port 27 + 0x0 + + + Enable + Override region n is enabled for master port 27 + 0x1 + + + + + ENABLE28 + Enable override + 28 + 28 + + + Disable + Override region n is disabled for master port 28 + 0x0 + + + Enable + Override region n is enabled for master port 28 + 0x1 + + + + + ENABLE29 + Enable override + 29 + 29 + + + Disable + Override region n is disabled for master port 29 + 0x0 + + + Enable + Override region n is enabled for master port 29 + 0x1 + + + + + ENABLE30 + Enable override + 30 + 30 + + + Disable + Override region n is disabled for master port 30 + 0x0 + + + Enable + Override region n is enabled for master port 30 + 0x1 + + + + + ENABLE31 + Enable override + 31 + 31 + + + Disable + Override region n is disabled for master port 31 + 0x0 + + + Enable + Override region n is enabled for master port 31 + 0x1 + + + + + + + + + + MVDMA_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x42003000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA + 3 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + MVDMA_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x52003000 + + + + MVDMA + 3 + + + + RAMC_NS + RAM Controller 0 + 0x42004000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + SECBASE + Base address for secure access area. + 0x600 + read-write + 0x00000000 + 0x20 + + + ADDR + Base address + 0 + 31 + + + + + SECENABLE + Enable secure access restrictions. + 0x604 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable secure access restrictions + 0 + 0 + + + Disable + Secure access restrictions disabled + 0x0 + + + Enable + Secure access restrictions enabled + 0x1 + + + + + + + + + RAMC_S + RAM Controller 1 + 0x52004000 + + + + + HSFLL_S + HSFLL + 0x5200D000 + HSFLL + + + + 0 + 0x1000 + registers + + HSFLL + 0x20 + + + TASKS_START + Start the HSFLL + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the HSFLL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the HSFLL + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the HSFLL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FREQMEAS + Start frequency measurement in software-controlled mode + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_FREQMEAS + Start frequency measurement in software-controlled mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FREQCHANGE + Trigger frequency change + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_FREQCHANGE + Trigger frequency change + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_STARTED + HSFLL started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + HSFLL started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + HSFLL stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + HSFLL stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FREQMDONE + Frequency measurement done + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_FREQMDONE + Frequency measurement done + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FREQCHANGED + Frequency change done + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_FREQCHANGED + Frequency change done + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + CLOCKSTATUS + Clock status + 0x400 + read-only + 0x00000000 + 0x20 + + + MODE + The HSFLL operating mode. + 0 + 1 + + + OpenLoop + Open loop mode. + 0x0 + + + ClosedLoop + Closed loop mode. + 0x1 + + + Bypass + Bypass mode. + 0x2 + + + + + OVERRIDE + HSFLL Override mode. + 4 + 4 + + + Disabled + Override mode disabled. + 0x0 + + + Enabled + Override mode enabled. + 0x1 + + + + + ACCURACY + Clock accuracy. + 9 + 9 + + + OutsideLimit + Clock accuracy is outside 2 percent. + 0x0 + + + WithinLimit + Clock accuracy is within 2 percent. + 0x1 + + + + + LOCKED + The HSFLL lock status. + 10 + 10 + + + NotLocked + Not locked to reference clock + 0x0 + + + Locked + Locked to reference clock. + 0x1 + + + + + + + FREQM + Unspecified + HSFLL_FREQM + read-write + 0x420 + + DONE + Frequency measurement done status + 0x000 + read-only + 0x00000000 + 0x20 + + + DONE + Measurement done. + 0 + 0 + + + InProgress + Frequency measurement is in progress. + 0x0 + + + Completed + Frequency measurement is completed. + 0x1 + + + + + + + ERROR + Frequency measurement error status + 0x004 + read-only + 0x00000000 + 0x20 + + + ERROR + Trim error status. + 0 + 0 + + + OutsideLimit + Frequency exceeded the accuracy 2 percent in closed loop mode. + 0x1 + + + WithinLimit + Frequency stayed within accuracy 2 percent in closed loop mode. + 0x0 + + + + + TRIMUNDERFLOW + Underflow error status. + 1 + 1 + + + OutsideLimit + Underflow + 0x1 + + + WithinLimit + No underflow + 0x0 + + + + + TRIMOVERFLOW + Overflow error status. + 2 + 2 + + + OutsideLimit + Overflow + 0x1 + + + WithinLimit + No overflow + 0x0 + + + + + + + MEAS + Frequency measurement + 0x008 + read-only + 0x00000000 + 0x20 + + + VALUE + Last frequency measurement value. + 0 + 7 + + + + + + TRIM + Unspecified + HSFLL_TRIM + read-write + 0x440 + + VSUP + Internal regulator voltage supply level trimming + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Trim value + 0 + 4 + + + + + COARSE + Coarse frequency trimming + 0x004 + read-write + 0x00000004 + 0x20 + + + VALUE + Coarse frequency trimming value. + 0 + 9 + + + + + FINE + Fine frequency trimming + 0x008 + read-write + 0x0000001E + 0x20 + + + VALUE + Fine frequency trimming value + 0 + 10 + + + + + + CLOCKCTRL + Unspecified + HSFLL_CLOCKCTRL + read-write + 0x460 + + MODE + Clock control + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + The HSFLL operating mode. + 0 + 1 + + + Auto + The PCGC controls the mode automatically. + 0x0 + + + OpenLoop + Open loop mode. + 0x1 + + + ClosedLoop + Closed loop mode. + 0x2 + + + Bypass + Bypass mode. + 0x3 + + + + + OVERRIDE + HSFLL override mode. + 4 + 4 + + + Disabled + Override mode disabled. + 0x0 + + + Enabled + Override mode enabled. + 0x1 + + + + + + + DITHERING + Clock dithering configuration + 0x004 + read-write + 0x00000033 + 0x20 + + + CYCLECOUNT + Cycle count configuration for clock dithering + 0 + 2 + + + MAXOFFSET + Maximum offset configuration for clock dithering + 4 + 6 + + + EN + Enable the clock dithering + 31 + 31 + + + Disabled + Clock dithering is disabled + 0x0 + + + Enabled + Clock dithering is enabled + 0x1 + + + + + + + MULT + Multiplication factor + 0x008 + read-write + 0x00000006 + 0x20 + + + VAL + Multiplication factor value. Valid range: 4 to 25. Output frequency is a multiplication of 16 MHz reference and the multiplication factor. + 0 + 4 + + + + + SLEEP + Sleep configuration + 0x00C + read-write + 0x00000001 + 0x20 + + + MODE + HSFLL sleep mode. + 0 + 0 + + + Normal + Normal mode operation + 0x0 + + + Sleep + Power down the HSFLL core + 0x1 + + + + + RETAIN + Retain. + 1 + 1 + + + Disabled + No retention while powered down + 0x0 + + + Enabled + Retain all inputs while powered down + 0x1 + + + + + + + RETAINFINETRIM + Fine trim retain control + 0x010 + read-write + 0x00000000 + 0x20 + + + RETAIN + Retain control + 0 + 0 + + + NoRetain + No retain. + 0x0 + + + Retain + Retain control when HSFLL goes to open-loop mode. + 0x1 + + + + + + + OVERRIDELOCKED + Override the LOCKED signal + 0x014 + read-write + 0x00000000 + 0x20 + + + OVERRIDE + Override + 0 + 0 + + + NoOperation + No Operation. + 0x0 + + + Override + Override + 0x1 + + + + + + + DITHERINIT + Clock dithering, configurable seed + 0x018 + read-write + 0x00000000 + 0x20 + + + SEED + Initial value for the PRBS + 0 + 31 + + + + + + MIRROR + Enable LOCK for mirrored registers + 0x480 + read-write + 0x00000001 + 0x20 + + + LOCK + Lock for mirrored registers + 0 + 0 + + + Disabled + Lock disabled + 0x0 + + + Enabled + Lock enabled + 0x1 + + + + + + + + + LRCCONF000_S + LRCCONF 0 + 0x5200E000 + LRCCONF + + + + 0 + 0x1000 + registers + + LRCCONF + 0x20 + + + 0x8 + 0x4 + TASKS_REQCLKSRC[%s] + Description collection: Request the clock source for clock [n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_REQCLKSRC + Request the clock source for clock [n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_STOPREQCLKSRC[%s] + Description collection: Stop requesting the clock source for clock [n] + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQCLKSRC + Stop requesting the clock source for clock [n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CONSTLAT + Peripheral tasks. + LRCCONF_TASKS_CONSTLAT + write-only + 0x040 + + ENABLE + Enable constant latency mode + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLE + Enable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DISABLE + Disable constant latency mode + 0x004 + write-only + 0x00000000 + 0x20 + + + DISABLE + Disable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TASKS_SYSTEMOFF + Peripheral tasks. + LRCCONF_TASKS_SYSTEMOFF + write-only + 0x048 + + NOTREADY + Not ready to go to System OFF + 0x000 + write-only + 0x00000000 + 0x20 + + + NOTREADY + Not ready to go to System OFF + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + READY + Ready to go to System OFF + 0x004 + write-only + 0x00000000 + 0x20 + + + READY + Ready to go to System OFF + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TASKS_REQHFXO + Request HFXO + 0x050 + write-only + 0x00000000 + 0x20 + + + TASKS_REQHFXO + Request HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQHFXO + Stop requesting HFXO + 0x054 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQHFXO + Stop requesting HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_CLKSRCSTARTED[%s] + Description collection: Clock source is started for clock [n] + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CLKSRCSTARTED + Clock source is started for clock [n] + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_HFXOSTARTED + HFXO is started + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_HFXOSTARTED + HFXO is started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + CLKSTAT[%s] + Unspecified + LRCCONF_CLKSTAT + read-write + 0x400 + + RUN + Description cluster: Status indicating that TASKS_REQCLKSRC task has been triggered for clock [n]. + 0x000 + read-write + 0x00000000 + 0x20 + + + STATUS + Clock start task triggered or not + 0 + 0 + read-only + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + SRC + Description cluster: Status indicating clock source for clock [n] + 0x004 + read-write + 0x00000000 + 0x20 + + + SRC + Clock source status + 0 + 0 + read-only + + + OpenLoop + Open loop. + 0x0 + + + ClosedLoop + Closed loop. + 0x1 + + + + + + + + 8 + 0x008 + CLKCTRL[%s] + Unspecified + LRCCONF_CLKCTRL + read-write + 0x440 + + ALWAYSRUN + Description cluster: Force the clock [n] and tree running always + 0x000 + read-write + 0x00000000 + 0x20 + + + FORCE + Force the clock always running + 0 + 0 + + + Automatic + Automatic clock control enabled + 0x0 + + + AlwaysRun + Clock always running + 0x1 + + + + + + + SRC + Description cluster: Select the clock source for clock [n] + 0x004 + read-write + 0x00000000 + 0x20 + + + SRC + Clock source + 0 + 0 + + + OpenLoop + Open loop. + 0x0 + + + ClosedLoop + Closed loop. + 0x1 + + + + + + + + CONSTLATSTAT + Status of constant latency + 0x480 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Disable + Constant latency disabled. + 0x0 + + + Enable + Constant latency enabled. + 0x1 + + + + + + + POWERON + Force power domain ON + 0x490 + read-write + 0x00000000 + 0x20 + + + MAIN + Force the main power domain ON + 0 + 0 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_0 + Force the active power domain[0] ON + 4 + 4 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_1 + Force the active power domain[1] ON + 5 + 5 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_2 + Force the active power domain[2] ON + 6 + 6 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_3 + Force the active power domain[3] ON + 7 + 7 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_4 + Force the active power domain[4] ON + 8 + 8 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_5 + Force the active power domain[5] ON + 9 + 9 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_6 + Force the active power domain[6] ON + 10 + 10 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_7 + Force the active power domain[7] ON + 11 + 11 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + + + RETAIN + Retain power domain + 0x494 + read-write + 0x00000FF1 + 0x20 + + + MAIN + Retain the main power domain + 0 + 0 + read-only + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_0 + Retain the active power domain[0] + 4 + 4 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_1 + Retain the active power domain[1] + 5 + 5 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_2 + Retain the active power domain[2] + 6 + 6 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_3 + Retain the active power domain[3] + 7 + 7 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_4 + Retain the active power domain[4] + 8 + 8 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_5 + Retain the active power domain[5] + 9 + 9 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_6 + Retain the active power domain[6] + 10 + 10 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_7 + Retain the active power domain[7] + 11 + 11 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + + + 0x10 + 0x4 + AX2XWAITSTATES[%s] + Description collection: AX2X bridge waitstates for the domain [n], where n is the Domain ID. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates + 0 + 2 + + + + + + + SPU010_S + System protection unit 1 + 0x52010000 + + + + SPU010 + 16 + + + + MEMCONF_NS + Memory configuration 0 + 0x42012000 + MEMCONF + + + + 0 + 0x1000 + registers + + MEMCONF + 0x20 + + + 2 + 0x010 + POWER[%s] + Unspecified + MEMCONF_POWER + read-write + 0x500 + + CONTROL + Description cluster: Control memory block power. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MEM0 + Keep the memory block MEM[0] on or off when in System ON mode. + 0 + 0 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM1 + Keep the memory block MEM[1] on or off when in System ON mode. + 1 + 1 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM2 + Keep the memory block MEM[2] on or off when in System ON mode. + 2 + 2 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM3 + Keep the memory block MEM[3] on or off when in System ON mode. + 3 + 3 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM4 + Keep the memory block MEM[4] on or off when in System ON mode. + 4 + 4 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM5 + Keep the memory block MEM[5] on or off when in System ON mode. + 5 + 5 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM6 + Keep the memory block MEM[6] on or off when in System ON mode. + 6 + 6 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM7 + Keep the memory block MEM[7] on or off when in System ON mode. + 7 + 7 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM8 + Keep the memory block MEM[8] on or off when in System ON mode. + 8 + 8 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM9 + Keep the memory block MEM[9] on or off when in System ON mode. + 9 + 9 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM10 + Keep the memory block MEM[10] on or off when in System ON mode. + 10 + 10 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM11 + Keep the memory block MEM[11] on or off when in System ON mode. + 11 + 11 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM12 + Keep the memory block MEM[12] on or off when in System ON mode. + 12 + 12 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM13 + Keep the memory block MEM[13] on or off when in System ON mode. + 13 + 13 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM14 + Keep the memory block MEM[14] on or off when in System ON mode. + 14 + 14 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM15 + Keep the memory block MEM[15] on or off when in System ON mode. + 15 + 15 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM16 + Keep the memory block MEM[16] on or off when in System ON mode. + 16 + 16 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM17 + Keep the memory block MEM[17] on or off when in System ON mode. + 17 + 17 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM18 + Keep the memory block MEM[18] on or off when in System ON mode. + 18 + 18 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM19 + Keep the memory block MEM[19] on or off when in System ON mode. + 19 + 19 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM20 + Keep the memory block MEM[20] on or off when in System ON mode. + 20 + 20 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM21 + Keep the memory block MEM[21] on or off when in System ON mode. + 21 + 21 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM22 + Keep the memory block MEM[22] on or off when in System ON mode. + 22 + 22 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM23 + Keep the memory block MEM[23] on or off when in System ON mode. + 23 + 23 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM24 + Keep the memory block MEM[24] on or off when in System ON mode. + 24 + 24 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM25 + Keep the memory block MEM[25] on or off when in System ON mode. + 25 + 25 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM26 + Keep the memory block MEM[26] on or off when in System ON mode. + 26 + 26 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM27 + Keep the memory block MEM[27] on or off when in System ON mode. + 27 + 27 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM28 + Keep the memory block MEM[28] on or off when in System ON mode. + 28 + 28 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM29 + Keep the memory block MEM[29] on or off when in System ON mode. + 29 + 29 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM30 + Keep the memory block MEM[30] on or off when in System ON mode. + 30 + 30 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM31 + Keep the memory block MEM[31] on or off when in System ON mode. + 31 + 31 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + + + RET + Description cluster: RAM retention for RAM [n]. + 0x008 + read-write + 0x00000000 + 0x20 + + + MEM0 + Keep the RAM block MEM[0] retained when the parent power domain of the RAM is off. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the RAM block MEM[1] retained when the parent power domain of the RAM is off. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the RAM block MEM[2] retained when the parent power domain of the RAM is off. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the RAM block MEM[3] retained when the parent power domain of the RAM is off. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the RAM block MEM[4] retained when the parent power domain of the RAM is off. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the RAM block MEM[5] retained when the parent power domain of the RAM is off. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the RAM block MEM[6] retained when the parent power domain of the RAM is off. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the RAM block MEM[7] retained when the parent power domain of the RAM is off. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the RAM block MEM[8] retained when the parent power domain of the RAM is off. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the RAM block MEM[9] retained when the parent power domain of the RAM is off. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the RAM block MEM[10] retained when the parent power domain of the RAM is off. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the RAM block MEM[11] retained when the parent power domain of the RAM is off. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the RAM block MEM[12] retained when the parent power domain of the RAM is off. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the RAM block MEM[13] retained when the parent power domain of the RAM is off. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the RAM block MEM[14] retained when the parent power domain of the RAM is off. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the RAM block MEM[15] retained when the parent power domain of the RAM is off. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the RAM block MEM[16] retained when the parent power domain of the RAM is off. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the RAM block MEM[17] retained when the parent power domain of the RAM is off. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the RAM block MEM[18] retained when the parent power domain of the RAM is off. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the RAM block MEM[19] retained when the parent power domain of the RAM is off. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the RAM block MEM[20] retained when the parent power domain of the RAM is off. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the RAM block MEM[21] retained when the parent power domain of the RAM is off. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the RAM block MEM[22] retained when the parent power domain of the RAM is off. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the RAM block MEM[23] retained when the parent power domain of the RAM is off. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the RAM block MEM[24] retained when the parent power domain of the RAM is off. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the RAM block MEM[25] retained when the parent power domain of the RAM is off. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the RAM block MEM[26] retained when the parent power domain of the RAM is off. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the RAM block MEM[27] retained when the parent power domain of the RAM is off. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the RAM block MEM[28] retained when the parent power domain of the RAM is off. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the RAM block MEM[29] retained when the parent power domain of the RAM is off. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the RAM block MEM[30] retained when the parent power domain of the RAM is off. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the RAM block MEM[31] retained when the parent power domain of the RAM is off. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + RET2 + Description cluster: RAM retention for the second bank in the RAM block + 0x00C + read-write + 0x00000000 + 0x20 + + + MEM0 + Keep the second bank in RAM block MEM[0] retained when parent power domain of the RAM is off. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the second bank in RAM block MEM[1] retained when parent power domain of the RAM is off. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the second bank in RAM block MEM[2] retained when parent power domain of the RAM is off. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the second bank in RAM block MEM[3] retained when parent power domain of the RAM is off. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the second bank in RAM block MEM[4] retained when parent power domain of the RAM is off. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the second bank in RAM block MEM[5] retained when parent power domain of the RAM is off. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the second bank in RAM block MEM[6] retained when parent power domain of the RAM is off. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the second bank in RAM block MEM[7] retained when parent power domain of the RAM is off. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the second bank in RAM block MEM[8] retained when parent power domain of the RAM is off. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the second bank in RAM block MEM[9] retained when parent power domain of the RAM is off. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the second bank in RAM block MEM[10] retained when parent power domain of the RAM is off. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the second bank in RAM block MEM[11] retained when parent power domain of the RAM is off. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the second bank in RAM block MEM[12] retained when parent power domain of the RAM is off. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the second bank in RAM block MEM[13] retained when parent power domain of the RAM is off. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the second bank in RAM block MEM[14] retained when parent power domain of the RAM is off. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the second bank in RAM block MEM[15] retained when parent power domain of the RAM is off. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the second bank in RAM block MEM[16] retained when parent power domain of the RAM is off. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the second bank in RAM block MEM[17] retained when parent power domain of the RAM is off. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the second bank in RAM block MEM[18] retained when parent power domain of the RAM is off. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the second bank in RAM block MEM[19] retained when parent power domain of the RAM is off. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the second bank in RAM block MEM[20] retained when parent power domain of the RAM is off. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the second bank in RAM block MEM[21] retained when parent power domain of the RAM is off. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the second bank in RAM block MEM[22] retained when parent power domain of the RAM is off. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the second bank in RAM block MEM[23] retained when parent power domain of the RAM is off. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the second bank in RAM block MEM[24] retained when parent power domain of the RAM is off. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the second bank in RAM block MEM[25] retained when parent power domain of the RAM is off. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the second bank in RAM block MEM[26] retained when parent power domain of the RAM is off. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the second bank in RAM block MEM[27] retained when parent power domain of the RAM is off. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the second bank in RAM block MEM[28] retained when parent power domain of the RAM is off. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the second bank in RAM block MEM[29] retained when parent power domain of the RAM is off. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the second bank in RAM block MEM[30] retained when parent power domain of the RAM is off. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the second bank in RAM block MEM[31] retained when parent power domain of the RAM is off. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + + 192 + 0x004 + REPAIR[%s] + Unspecified + MEMCONF_REPAIR + read-write + 0x600 + + BITLINE + Description cluster: Repair configuration for RAM blocks. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDR + Repair address of the bitline + 0 + 6 + + + EN + Enable bitline repair + 31 + 31 + + + Disabled + Repair disabled. + 0x0 + + + Enabled + Repair enabled. + 0x1 + + + + + + + + 64 + 0x004 + BLOCKTYPE[%s] + Unspecified + MEMCONF_BLOCKTYPE + read-write + 0x900 + + TRIM + Description cluster: Trim configuration for the memory block types. + 0x000 + read-write + 0x00000000 + 0x20 + + + MEMTRIM_0 + Read/write margin trim. + 0 + 0 + + + MEMTRIM_1 + Read/write margin trim. + 1 + 1 + + + MEMTRIM_2 + Read/write margin trim. + 2 + 2 + + + MEMTRIM_3 + Read/write margin trim. + 3 + 3 + + + MEMTRIM_4 + Read/write margin trim. + 4 + 4 + + + MEMTRIM_5 + Read/write margin trim. + 5 + 5 + + + MEMTRIM_6 + Read/write margin trim. + 6 + 6 + + + MEMTRIM_7 + Read/write margin trim. + 7 + 7 + + + MEMTRIM_8 + Read/write margin trim. + 8 + 8 + + + MEMTRIM_9 + Read/write margin trim. + 9 + 9 + + + MEMTRIM_10 + Read/write margin trim. + 10 + 10 + + + MEMTRIM_11 + Read/write margin trim. + 11 + 11 + + + MEMTRIM_12 + Read/write margin trim. + 12 + 12 + + + MEMTRIM_13 + Read/write margin trim. + 13 + 13 + + + MEMTRIM_14 + Read/write margin trim. + 14 + 14 + + + MEMTRIM_15 + Read/write margin trim. + 15 + 15 + + + MEMRETTRIM_0 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 16 + 16 + + + MEMRETTRIM_1 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 17 + 17 + + + MEMRETTRIM_2 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 18 + 18 + + + MEMRETTRIM_3 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 19 + 19 + + + MEMRETTRIM_4 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 20 + 20 + + + MEMRETTRIM_5 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 21 + 21 + + + MEMRETTRIM_6 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 22 + 22 + + + MEMRETTRIM_7 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 23 + 23 + + + MEMRETTRIM_8 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 24 + 24 + + + MEMRETTRIM_9 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 25 + 25 + + + MEMRETTRIM_10 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 26 + 26 + + + MEMRETTRIM_11 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 27 + 27 + + + MEMRETTRIM_12 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 28 + 28 + + + MEMRETTRIM_13 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 29 + 29 + + + MEMRETTRIM_14 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 30 + 30 + + + MEMRETTRIM_15 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 31 + 31 + + + + + + + + MEMCONF_S + Memory configuration 1 + 0x52012000 + + + + + WDT010_NS + Watchdog Timer 0 + 0x42014000 + WDT + + + + 0 + 0x1000 + registers + + + WDT010 + 20 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + 0x20 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0x0 + + + Run + Keep WDT running while the CPU is sleeping + 0x1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0x0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 0x1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0x0 + + + Enable + Allow stopping WDT + 0x1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + 0x20 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT010_S + Watchdog Timer 1 + 0x52014000 + + + + WDT010 + 20 + + + + WDT011_NS + Watchdog Timer 2 + 0x42015000 + + + + WDT011 + 21 + + + + WDT011_S + Watchdog Timer 3 + 0x52015000 + + + + WDT011 + 21 + + + + ABB_S + ABB peripheral + 0x5201C000 + ABB + + + + 0 + 0x1000 + registers + + ABB + 0x20 + + + STATUS + ABB status + 0x400 + read-only + 0x00000000 + 0x20 + + + OPPOINT + The current ABB operating point + 0 + 1 + + + OpPoint0V4 + Operating point 0.4V + 0x0 + + + OpPoint0V5 + Operating point 0.5V + 0x1 + + + OpPoint0V6 + Operating point 0.6V + 0x2 + + + OpPoint0V8 + Operating point 0.8V + 0x3 + + + + + EN + The ABB enable status. + 4 + 4 + + + Disabled + ABB disabled + 0x0 + + + Enabled + ABB enabled + 0x1 + + + + + LOCKED + The ABB lock status. + 5 + 5 + + + NotLocked + Not locked + 0x0 + + + Locked + Locked. + 0x1 + + + + + + + MODE + ABB control + 0x480 + read-write + 0x00000000 + 0x20 + + + OPPOINT + The ABB operating point. + 0 + 2 + + + Auto + The peripheral controls the operating point automatically based on request from the + master ABB controller. + 0x0 + + + OpPoint0V4 + Force the operating point to 0.4V + 0x1 + + + OpPoint0V5 + Force the operating point to 0.5V + 0x2 + + + OpPoint0V6 + Force the operating point to 0.6V + 0x3 + + + OpPoint0V8 + Force the operating point to 0.8V + 0x4 + + + + + ABBEN + Enable ABB. + 4 + 5 + + + Auto + The peripheral controls the ABB enable automatically based on request. + 0x0 + + + Enable + Force enable ABB + 0x1 + + + Disable + Force disable ABB + 0x2 + + + + + + + + + LRCCONF010_S + LRCCONF 1 + 0x5201E000 + + + + + RESETINFO_S + RESETINFO + 0x5201E000 + LRCCONF010_S + RESETINFO + + + + 0 + 0x1000 + registers + + RESETINFO + 0x20 + + + RESETREAS + Unspecified + RESETINFO_RESETREAS + read-write + 0x4A0 + + GLOBAL + Global reset reason. + 0x000 + read-write + 0x00000000 + 0x20 + + + RESETPORONLY + Reset from power on reset (reset reason POR or BOR). + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + RESETPIN + Reset from pin reset detected. + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOG + Reset from the SysCtrl watchdog timer detected. + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAP + Reset from CTRL-AP detected. + 3 + 3 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECSREQ + Reset due to secure domain system reset request. + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECWDT0 + Reset due to the first instance of watchdog timer in secure domain detected. + 5 + 5 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECWDT1 + Reset due to the second instance of watchdog timer in secure domain detected. + 6 + 6 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECLOCKUP + Reset due to secure domain lockup. + 7 + 7 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECTAMPER + Reset due to secure domain tamper detected + 8 + 8 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + RESETPOR + Reset from power on reset (reset reason other than POR or BOR). + 9 + 9 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO. + 16 + 16 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by LPCOMP (Low Power Comparator). + 17 + 17 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DIF + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode. + 18 + 18 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + GRTC + Reset due to wakeup from System OFF mode when wakeup is triggered by GRTC interrupt. + 19 + 19 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + NFC + Reset due to wakeup from System OFF mode when wakeup is triggered by NFC field detection in sense mode. + 20 + 20 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + VUSB + Reset after wakeup from System OFF mode due to VBUS rising into valid range. + 21 + 21 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + + + LOCAL + Local reset reason. + 0x004 + read-write + 0x00000000 + 0x20 + + + DOG + Reset from the local watchdog timer detected + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOGNS + Reset from the local non-secure watchdog timer detected + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SREQ + Reset from the local soft reset request detected. + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LOCKUP + Reset from local CPU lockup detected + 3 + 3 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CROSSDOMAIN + Reset due to cross domain reset source. + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + UNRETAINEDWAKE + Reset due to wake from unretained state. + 5 + 5 + + + + + + ERROR + Unspecified + RESETINFO_ERROR + read-write + 0x4A8 + + STATUS + Reset error status. + 0x000 + read-write + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status + 0 + 3 + + + + + ADDRESS + Reset error address. + 0x004 + read-write + 0x00000000 + 0x20 + + + ERRORADDRESS + Error address + 0 + 31 + + + + + + RESTOREVALID + Valid restore image is present in RAM. + 0x4C0 + read-write + 0x00000000 + 0x20 + + + RESTOREVALID + Valid restore image is present in RAM. + 0 + 0 + + + NotPreset + Not present + 0x0 + + + Present + Present + 0x1 + + + + + + + + + IPCT_NS + IPCT APB registers 0 + 0x42013000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT_0 + 64 + + + IPCT_1 + 65 + + IPCT + 0x20 + + + 0x4 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + IPCT_S + IPCT APB registers 1 + 0x52013000 + + + + + IPCT_0 + 64 + + + IPCT_1 + 65 + + + + SWI0_NS + Software interrupt 0 + 0x42058000 + SWI + + + + 0 + 0x1000 + registers + + + SWI0 + 88 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + SWI1_NS + Software interrupt 1 + 0x42059000 + + + + SWI1 + 89 + + + + SWI2_NS + Software interrupt 2 + 0x4205A000 + + + + SWI2 + 90 + + + + SWI3_NS + Software interrupt 3 + 0x4205B000 + + + + SWI3 + 91 + + + + SWI4_NS + Software interrupt 4 + 0x4205C000 + + + + SWI4 + 92 + + + + SWI5_NS + Software interrupt 5 + 0x4205D000 + + + + SWI5 + 93 + + + + SWI6_NS + Software interrupt 6 + 0x4205E000 + + + + SWI6 + 94 + + + + SWI7_NS + Software interrupt 7 + 0x4205F000 + + + + SWI7 + 95 + + + + BELLBOARD_NS + BELLBOARD APB registers 0 + 0x4F09A000 + BELLBOARD + + + + + 0 + 0x1000 + registers + + + BELLBOARD_0 + 96 + + + BELLBOARD_1 + 97 + + + BELLBOARD_2 + 98 + + + BELLBOARD_3 + 99 + + BELLBOARD + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + 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disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + 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+ + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + 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TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + 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Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + BELLBOARD_S + BELLBOARD APB registers 1 + 0x5F09A000 + + + + + BELLBOARD_0 + 96 + + + BELLBOARD_1 + 97 + + + BELLBOARD_2 + 98 + + + BELLBOARD_3 + 99 + + + + GLOBAL_GPIOTE130_NS + GPIO Tasks and Events 0 + 0x4F934000 + GPIOTE + + + + + 0 + 0x1000 + registers + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 4 + 0x008 + EVENTS_PORT[%s] + Peripheral events. + GLOBAL_GPIOTE_EVENTS_PORT + read-write + 0x140 + + NONSECURE + Description cluster: Non-secure port event from owner n + 0x000 + read-write + 0x00000000 + 0x20 + + + + NONSECURE + Non-secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SECURE + Description cluster: Secure port event from owner n + 0x004 + read-write + 0x00000000 + 0x20 + + + + SECURE + Secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 4 + 0x008 + PUBLISH_PORT[%s] + Publish configuration for events + GLOBAL_GPIOTE_PUBLISH_PORT + read-write + 0x1C0 + + NONSECURE + Description cluster: Publish configuration for event PORT[n].NONSECURE + 0x000 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].NONSECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SECURE + Description cluster: Publish configuration for event PORT[n].SECURE + 0x004 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].SECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + 0x20 + + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting + 0x0 + + + LowLatency + Low latency setting + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + 0x20 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 4 + 8 + + + PORT + Port number + 9 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + GLOBAL_GPIOTE130_S + GPIO Tasks and Events 1 + 0x5F934000 + + + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + + + GLOBAL_GPIOTE131_NS + GPIO Tasks and Events 2 + 0x4F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GPIOTE131_S + GPIO Tasks and Events 3 + 0x5F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GRTC_NS + Global Real-time counter 0 + 0x4F99C000 + GRTC + + + + + 0 + 0x1000 + registers + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + GRTC + 0x20 + + + 0x10 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture the counter value to CC[n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture the counter value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTART + Start the PWM + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTART + Start the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTOP + Stop the PWM + 0x070 + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTOP + Stop the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0x164 + read-write + 0x00000000 + 0x20 + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0x168 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0x16C + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN4 + Enable or disable interrupt + 0x340 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET4 + Enable interrupt + 0x344 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR4 + Disable interrupt + 0x348 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND4 + Pending interrupts + 0x34C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN5 + Enable or disable interrupt + 0x350 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET5 + Enable interrupt + 0x354 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR5 + Disable interrupt + 0x358 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND5 + Pending interrupts + 0x35C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN6 + Enable or disable interrupt + 0x360 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET6 + Enable interrupt + 0x364 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR6 + Disable interrupt + 0x368 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND6 + Pending interrupts + 0x36C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN7 + Enable or disable interrupt + 0x370 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET7 + Enable interrupt + 0x374 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR7 + Disable interrupt + 0x378 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND7 + Pending interrupts + 0x37C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN8 + Enable or disable interrupt + 0x380 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET8 + Enable interrupt + 0x384 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR8 + Disable interrupt + 0x388 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND8 + Pending interrupts + 0x38C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN9 + Enable or disable interrupt + 0x390 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET9 + Enable interrupt + 0x394 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR9 + Disable interrupt + 0x398 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND9 + Pending interrupts + 0x39C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN10 + Enable or disable interrupt + 0x3A0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x3A4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x3A8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND10 + Pending interrupts + 0x3AC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN11 + Enable or disable interrupt + 0x3B0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET11 + Enable interrupt + 0x3B4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x3B8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND11 + Pending interrupts + 0x3BC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN12 + Enable or disable interrupt + 0x3C0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET12 + Enable interrupt + 0x3C4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR12 + Disable interrupt + 0x3C8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND12 + Pending interrupts + 0x3CC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN13 + Enable or disable interrupt + 0x3D0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET13 + Enable interrupt + 0x3D4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR13 + Disable interrupt + 0x3D8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND13 + Pending interrupts + 0x3DC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN14 + Enable or disable interrupt + 0x3E0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET14 + Enable interrupt + 0x3E4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR14 + Disable interrupt + 0x3E8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND14 + Pending interrupts + 0x3EC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN15 + Enable or disable interrupt + 0x3F0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET15 + Enable interrupt + 0x3F4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR15 + Disable interrupt + 0x3F8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND15 + Pending interrupts + 0x3FC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x400 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Enable or disable event routing for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x404 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to enable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x408 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to disable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Counter mode selection + 0x510 + read-write + 0x00000000 + 0x20 + + + AUTOEN + Automatic enable to keep the SYSCOUNTER active. + 0 + 0 + + + Default + Default configuration to keep the SYSCOUNTER active. + 0x0 + + + CpuActive + In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. + 0x1 + + + + + SYSCOUNTEREN + Enable the SYSCOUNTER + 1 + 1 + + + Disabled + SYSCOUNTER disabled + 0x0 + + + Enabled + SYSCOUNTER enabled + 0x1 + + + + + + + 16 + 0x010 + CC[%s] + Unspecified + GRTC_CC + read-write + 0x520 + + CCL + Description cluster: The lower 32-bits of Capture/Compare register CC[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CCL + Capture/Compare low value in 1 us + 0 + 31 + + + + + CCH + Description cluster: The higher 32-bits of Capture/Compare register CC[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + CCH + Capture/Compare high value in 1 us + 0 + 19 + + + + + CCADD + Description cluster: Count to add to CC[n] when this register is written. + 0x008 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[n] + 0 + 30 + + + REFERENCE + Configure the Capture/Compare register + 31 + 31 + + + SYSCOUNTER + Adds SYSCOUNTER value. + 0x0 + + + CC + Adds CC value. + 0x1 + + + + + + + CCEN + Description cluster: Configure Capture/Compare register CC[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + ACTIVE + Configure the Capture/Compare register + 0 + 0 + + + Disable + Capture/Compare register CC[n] Disabled. + 0x0 + + + Enable + Capture/Compare register CC[n] enabled. + 0x1 + + + + + + + + KEEPRUNNING + Request to keep the SYSCOUNTER in the active state and prevent going to sleep + 0x6A0 + read-write + 0x00000000 + 0x20 + + + REQUEST_0 + Request from index [0] + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_1 + Request from index [1] + 1 + 1 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_2 + Request from index [2] + 2 + 2 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_3 + Request from index [3] + 3 + 3 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_4 + Request from index [4] + 4 + 4 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_5 + Request from index [5] + 5 + 5 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_6 + Request from index [6] + 6 + 6 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_7 + Request from index [7] + 7 + 7 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_8 + Request from index [8] + 8 + 8 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_9 + Request from index [9] + 9 + 9 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_10 + Request from index [10] + 10 + 10 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_11 + Request from index [11] + 11 + 11 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_12 + Request from index [12] + 12 + 12 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_13 + Request from index [13] + 13 + 13 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_14 + Request from index [14] + 14 + 14 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_15 + Request from index [15] + 15 + 15 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + TIMEOUT + Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER + 0x6A4 + read-write + 0x00000000 + 0x20 + + + VALUE + Number of 32Ki cycles + 0 + 15 + + + + + INTERVAL + Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. + 0x6A8 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[0] + 0 + 15 + + + + + PWMCONFIG + PWM configuration. + 0x710 + read-write + 0x00000000 + 0x20 + + + COMPAREVALUE + The PWM compare value + 0 + 7 + + + + + CLKOUT + Configuration of clock output + 0x714 + read-write + 0x00000000 + 0x20 + + + CLKOUT32K + Enable 32Ki clock output on pin + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + CLKOUTFAST + Enable fast clock output on pin + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + CLKCFG + Clock Configuration + 0x718 + read-write + 0x00010001 + 0x20 + + + CLKFASTDIV + Fast clock divisor value of clock output + 0 + 7 + + + CLKSEL + GRTC LFCLK clock source selection + 16 + 17 + + + LFXO + GRTC LFCLK clock source is LFXO + 0x0 + + + SystemLFCLK + GRTC LFCLK clock source is system LFCLK + 0x1 + + + + + + + 16 + 0x010 + SYSCOUNTER[%s] + Unspecified + GRTC_SYSCOUNTER + read-write + 0x720 + + SYSCOUNTERL + Description cluster: The lower 32-bits of the SYSCOUNTER for index [n] + 0x000 + read-only + 0x00000000 + 0x20 + + + VALUE + The lower 32-bits of the SYSCOUNTER value. + 0 + 31 + + + + + SYSCOUNTERH + Description cluster: The higher 20-bits of the SYSCOUNTER for index [n] + 0x004 + read-only + 0x40000000 + 0x20 + + + VALUE + The higher 20-bits of the SYSCOUNTER value. + 0 + 19 + + + BUSY + SYSCOUNTER busy status + 30 + 30 + + + Ready + SYSCOUNTER is ready for read + 0x0 + + + Busy + SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this register is not valid) + 0x1 + + + + + OVERFLOW + The SYSCOUNTERL overflow indication after reading it. + 31 + 31 + + + NoOverflow + SYSCOUNTERL is not overflown + 0x0 + + + Overflow + SYSCOUNTERL overflown + 0x1 + + + + + + + ACTIVE + Description cluster: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] + 0x008 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Keep SYSCOUNTER in active state + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + + + + GLOBAL_GRTC_S + Global Real-time counter 1 + 0x5F99C000 + + + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + + + GLOBAL_TBM_NS + Trace buffer monitor 0 + 0xBF003000 + TBM + + + + 0 + 0x1000 + registers + + + TBM + 127 + + TBM + 0x20 + + + TASKS_START + Start counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop counter, clear counter value + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop counter, clear counter value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_HALFFULL + Counter value equals half-full + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_HALFFULL + Counter value equals half-full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FULL + Counter value equals full + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FULL + Counter value equals full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Enable or disable interrupt for event HALFFULL + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FULL + Enable or disable interrupt for event FULL + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FLUSH + Enable or disable interrupt for event FLUSH + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to enable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FULL + Write '1' to enable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FLUSH + Write '1' to enable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to disable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FULL + Write '1' to disable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FLUSH + Write '1' to disable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + HALFFULL + Read pending status of interrupt for event HALFFULL + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FULL + Read pending status of interrupt for event FULL + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FLUSH + Read pending status of interrupt for event FLUSH + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + BUFFERSIZE + System RAM trace buffer total size in bytes + 0x400 + read-write + 0x00000400 + 0x20 + + + BUFFERSIZE + Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to make + half-buffer size always 64 bit word aligned. Typical minimum BUFFERSIZE value 0x010 i.e. 16 bytes, typical + maximum value 0x1000 i.e. 4096 bytes. + 0 + 12 + + + Zero + 0 bytes + 0x0000 + + + Min + 16 bytes + 0x0010 + + + Max + 4096 bytes + 0x1000 + + + + + + + COUNT + Counter current value + 0x404 + read-write + 0x00000000 + 0x20 + + + COUNT + Counter current value. Only writable when counter is in stopped state. Writing when not in stopped + state will generate a bus fault. + 0 + 12 + + + + + COUNTSNAPSHOT + Copy of the current COUNT value + 0x408 + read-only + 0x00000000 + 0x20 + + + COUNTSNAPSHOT + TASKS_FLUSH will copy the current COUNT value to this register. + 0 + 12 + + + + + + + GLOBAL_TBM_S + Trace buffer monitor 1 + 0xBF003000 + GLOBAL_TBM_NS + + + + TBM + 127 + + + + GLOBAL_USBHS_NS + USBHS 0 + 0x4F086000 + USBHS + + + + 0 + 0x1000 + registers + + + USBHS + 134 + + USBHS + 0x20 + + + TASKS_START + Start the USB peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the USB peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable USB peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + CORE + Enable USB Controller + 0 + 0 + + + Disabled + USB Controller disabled. + 0x0 + + + Enabled + USB Controller enabled. + 0x1 + + + + + PHY + Enable USB PHY + 1 + 1 + + + Disabled + USB PHY disabled. + 0x0 + + + Enabled + USB PHY enabled. + 0x1 + + + + + + + + + GLOBAL_USBHS_S + USBHS 1 + 0x5F086000 + + + + USBHS + 134 + + + + GLOBAL_EXMIF_NS + External Memory Interface 0 + 0x4F095000 + EXMIF + + + + 0 + 0x1000 + registers + + + EXMIF + 149 + + EXMIF + 0x20 + + + TASKS_START + Start operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + LOCKEDACCESS + Enable or disable locked APB access to serial memory controller. + 0x14 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable locked APB access to SSI. + 0 + 0 + + + Disabled + Disable locked APB access. + 0x0 + + + Enabled + Enable locked APB access. + 0x1 + + + + + + + RESET + Reset the external memory. + 0x1C + read-write + 0x00000000 + 0x20 + + + RESET + 0 + 0 + + + Clear + Reset is cleared. + 0x0 + + + Set + Reset is set. + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EXTCONF1 + Configuration for external memory device 1. + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 1. + 0x0 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 1. + 0x4 + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x10 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + EXTCONF2 + Configuration for external memory device 2. + EXTCONF2 + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 2. + 0x8 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 2. + 0xC + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x20 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + CORE + Unspecified + GLOBAL_EXMIF_CORE + read-write + 0x500 + + SSICADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICADDRESS + read-write + 0x000 + + CTRLR0 + This register controls the serial data transfer. + 0x000 + read-write + 0x00004007 + 0x20 + + + DFS + Data Frame Size. + 0 + 4 + + + DFS_01_BIT + Unspecified + 0x00 + + + DFS_02_BIT + Unspecified + 0x01 + + + DFS_03_BIT + Unspecified + 0x02 + + + DFS_04_BIT + Unspecified + 0x03 + + + DFS_05_BIT + Unspecified + 0x04 + + + DFS_06_BIT + Unspecified + 0x05 + + + DFS_07_BIT + Unspecified + 0x06 + + + DFS_08_BIT + Unspecified + 0x07 + + + DFS_09_BIT + Unspecified + 0x08 + + + DFS_10_BIT + Unspecified + 0x09 + + + DFS_11_BIT + Unspecified + 0x0A + + + DFS_12_BIT + Unspecified + 0x0B + + + DFS_13_BIT + Unspecified + 0x0C + + + DFS_14_BIT + Unspecified + 0x0D + + + DFS_15_BIT + Unspecified + 0x0E + + + DFS_16_BIT + Unspecified + 0x0F + + + DFS_17_BIT + Unspecified + 0x10 + + + DFS_18_BIT + Unspecified + 0x11 + + + DFS_19_BIT + Unspecified + 0x12 + + + DFS_20_BIT + Unspecified + 0x13 + + + DFS_21_BIT + Unspecified + 0x14 + + + DFS_22_BIT + Unspecified + 0x15 + + + DFS_23_BIT + Unspecified + 0x16 + + + DFS_24_BIT + Unspecified + 0x17 + + + DFS_25_BIT + Unspecified + 0x18 + + + DFS_26_BIT + Unspecified + 0x19 + + + DFS_27_BIT + Unspecified + 0x1A + + + DFS_28_BIT + Unspecified + 0x1B + + + DFS_29_BIT + Unspecified + 0x1C + + + DFS_30_BIT + Unspecified + 0x1D + + + DFS_31_BIT + Unspecified + 0x1E + + + DFS_32_BIT + Unspecified + 0x1F + + + + + FRF + Frame Format. + 6 + 7 + + + SPI + Unspecified + 0x0 + + + SSP + Unspecified + 0x1 + + + MICROWIRE + Unspecified + 0x2 + + + + + SCPH + Serial Clock Phase. + 8 + 8 + + + MIDDLE_BIT + Unspecified + 0x0 + + + START_BIT + Unspecified + 0x1 + + + + + SCPOL + Serial Clock Polarity. + 9 + 9 + + + INACTIVE_HIGH + Unspecified + 0x0 + + + INACTIVE_LOW + Unspecified + 0x1 + + + + + TMOD + Transfer Mode. + 10 + 11 + + + TX_AND_RX + Unspecified + 0x0 + + + TX_ONLY + Unspecified + 0x1 + + + RX_ONLY + Unspecified + 0x2 + + + EEPROM_READ + Unspecified + 0x3 + + + + + SLVOE + Slave Output Enable. + 12 + 12 + + + ENABLED + Unspecified + 0x0 + + + DISABLED + Unspecified + 0x1 + + + + + SRL + Shift Register Loop. + 13 + 13 + + + NORMAL_MODE + Unspecified + 0x0 + + + TESTING_MODE + Unspecified + 0x1 + + + + + SSTE + Slave Select Toggle Enable. + 14 + 14 + + + TOGGLE_DISABLE + Unspecified + 0x0 + + + TOGGLE_EN + Unspecified + 0x1 + + + + + CFS + Control Frame Size. + 16 + 19 + + + SIZE_01_BIT + Unspecified + 0x0 + + + SIZE_02_BIT + Unspecified + 0x1 + + + SIZE_03_BIT + Unspecified + 0x2 + + + SIZE_04_BIT + Unspecified + 0x3 + + + SIZE_05_BIT + Unspecified + 0x4 + + + SIZE_06_BIT + Unspecified + 0x5 + + + SIZE_07_BIT + Unspecified + 0x6 + + + SIZE_08_BIT + Unspecified + 0x7 + + + SIZE_09_BIT + Unspecified + 0x8 + + + SIZE_10_BIT + Unspecified + 0x9 + + + SIZE_11_BIT + Unspecified + 0xA + + + SIZE_12_BIT + Unspecified + 0xB + + + SIZE_13_BIT + Unspecified + 0xC + + + SIZE_14_BIT + Unspecified + 0xD + + + SIZE_15_BIT + Unspecified + 0xE + + + SIZE_16_BIT + Unspecified + 0xF + + + + + SPIFRF + SPI Frame Format + 22 + 23 + + + SPI_STANDARD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + SPIHYPERBUSEN + SPI Hyperbus Frame format enable. + 24 + 24 + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SPIDWSEN + Enable Dynamic wait states in SPI mode of operation. + 25 + 25 + read-only + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SSIISMST + This field selects if DWC_ssi is working in Master or Slave mode + 31 + 31 + read-only + + + SLAVE + Unspecified + 0x0 + + + MASTER + Unspecified + 0x1 + + + + + + + CTRLR1 + This register exists only when the DWC_ssi is configured as a master device. + 0x004 + read-write + 0x00000000 + 0x20 + + + NDF + Number of Data Frames. + 0 + 15 + + + + + SSIENR + This register enables and disables the DWC_ssi. + 0x008 + read-write + 0x00000000 + 0x20 + + + SSICEN + SSI Enable. + 0 + 0 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MWCR + This register controls the direction of the data word for the half-duplex Microwire serial protocol. + 0x00C + read-write + 0x00000000 + 0x20 + + + MWMOD + Microwire Transfer Mode. + 0 + 0 + + + NON_SEQUENTIAL + Unspecified + 0x0 + + + SEQUENTIAL + Unspecified + 0x1 + + + + + MDD + Microwire Control. + 1 + 1 + + + RECEIVE + Unspecified + 0x0 + + + TRANSMIT + Unspecified + 0x1 + + + + + MHS + Microwire Handshaking. + 2 + 2 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SER + This register is valid only when the DWC_ssi is configured as a master device. + 0x010 + read-write + 0x00000000 + 0x20 + + + SER + Slave Select Enable Flag. + 0 + 1 + + + NOTSELECTED + Unspecified + 0x0 + + + SELECTED + Unspecified + 0x1 + + + + + + + BAUDR + This register is valid only when the DWC_ssi is configured as a master device. + 0x014 + read-write + 0x00000000 + 0x20 + + + SCKDV + SSI Clock Divider. + 1 + 15 + + + + + TXFTLR + This register controls the threshold value for the transmit FIFO memory.. + 0x018 + read-write + 0x00000000 + 0x20 + + + TFT + Transmit FIFO Threshold. + 0 + 4 + + + TXFTHR + Transfer start FIFO level. + 16 + 20 + + + + + RXFTLR + This register controls the threshold value for the receive FIFO memory.. + 0x01C + read-write + 0x00000000 + 0x20 + + + RFT + Receive FIFO Threshold. + 0 + 4 + + + + + TXFLR + This register contains the number of valid data entries in the transmit FIFO memory. + 0x020 + read-write + 0x00000000 + 0x20 + + + TXTFL + Transmit FIFO Level. + 0 + 5 + read-only + + + + + RXFLR + This register contains the number of valid data entries in the receive FIFO memory. + 0x024 + read-write + 0x00000000 + 0x20 + + + RXTFL + Receive FIFO Level. + 0 + 5 + read-only + + + + + SR + This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. + 0x028 + read-write + 0x00000006 + 0x20 + + + BUSY + SSI Busy Flag. + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TFNF + Transmit FIFO Not Full. + 1 + 1 + read-only + + + FULL + Unspecified + 0x0 + + + NOT_FULL + Unspecified + 0x1 + + + + + TFE + Transmit FIFO Empty. + 2 + 2 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + RFNE + Receive FIFO Not Empty. + 3 + 3 + read-only + + + EMPTY + Unspecified + 0x0 + + + NOT_EMPTY + Unspecified + 0x1 + + + + + RFF + Receive FIFO Full. + 4 + 4 + read-only + + + NOT_FULL + Unspecified + 0x0 + + + FULL + Unspecified + 0x1 + + + + + TXE + Transmission Error. + 5 + 5 + read-only + + + NO_ERROR + Unspecified + 0x0 + + + TX_ERROR + Unspecified + 0x1 + + + + + DCOL + Data Collision Error. + 6 + 6 + read-only + + + NO_ERROR_CONDITION + Unspecified + 0x0 + + + TX_COLLISION_ERROR + Unspecified + 0x1 + + + + + + + IMR + This read/write register masks or enables all interrupts generated by the DWC_ssi. + 0x02C + read-write + 0x000000FF + 0x20 + + + TXEIM + Transmit FIFO Empty Interrupt Mask + 0 + 0 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXOIM + Transmit FIFO Overflow Interrupt Mask + 1 + 1 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXUIM + Receive FIFO Underflow Interrupt Mask + 2 + 2 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXOIM + Receive FIFO Overflow Interrupt Mask + 3 + 3 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXFIM + Receive FIFO Full Interrupt Mask + 4 + 4 + + + MASKED + ssi_rxf_intr interrupt is masked + 0x0 + + + UNMASKED + ssi_rxf_intr interrupt is not masked + 0x1 + + + + + MSTIM + Multi-Master Contention Interrupt Mask. + 5 + 5 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + XRXOIM + XIP Receive FIFO Overflow Interrupt Mask + 6 + 6 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXUIM + Transmit FIFO Underflow Interrupt Mask + 7 + 7 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + DONEM + SSI Done Interrupt Mask + 11 + 11 + read-only + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + + + ISR + This register reports the status of the DWC_ssi interrupts after they have been masked. + 0x030 + read-write + 0x00000000 + 0x20 + + + TXEIS + Transmit FIFO Empty Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIS + Transmit FIFO Overflow Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIS + Receive FIFO Underflow Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIS + Receive FIFO Overflow Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIS + Receive FIFO Full Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIS + Multi-Master Contention Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIS + XIP Receive FIFO Overflow Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIS + Transmit FIFO Underflow Interrupt Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONES + SSI Done Interrupt Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RISR + Raw Interrupt Status Register + 0x034 + read-write + 0x00000000 + 0x20 + + + TXEIR + Transmit FIFO Empty Raw Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIR + Transmit FIFO Overflow Raw Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIR + Receive FIFO Underflow Raw Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIR + Receive FIFO Overflow Raw Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIR + Receive FIFO Full Raw Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIR + Multi-Master Contention Raw Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIR + XIP Receive FIFO Overflow Raw Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIR + Transmit FIFO Underflow Interrupt Raw Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONER + SSI Done Interrupt Raw Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + TXEICR + Transmit FIFO Error Interrupt Clear Register + 0x038 + read-write + 0x00000000 + 0x20 + + + TXEICR + Clear Transmit FIFO Overflow/Underflow Interrupt. + 0 + 0 + read-only + + + + + RXOICR + Receive FIFO Overflow Interrupt Clear Register + 0x03C + read-write + 0x00000000 + 0x20 + + + RXOICR + Clear Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + RXUICR + Receive FIFO Underflow Interrupt Clear Register + 0x040 + read-write + 0x00000000 + 0x20 + + + RXUICR + Clear Receive FIFO Underflow Interrupt. + 0 + 0 + read-only + + + + + MSTICR + Multi-Master Interrupt Clear Register + 0x044 + read-write + 0x00000000 + 0x20 + + + MSTICR + Clear Multi-Master Contention Interrupt. + 0 + 0 + read-only + + + + + ICR + Interrupt Clear Register + 0x048 + read-write + 0x00000000 + 0x20 + + + ICR + Clear Interrupts. + 0 + 0 + read-only + + + + + IDR + This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. + 0x058 + read-write + 0x00010003 + 0x20 + + + IDCODE + Identification code. + 0 + 31 + read-only + + + + + SSICVERSIONID + This read-only register stores the specific DWC_ssi component version. + 0x05C + read-write + 0x3130332A + 0x20 + + + SSICCOMPVERSION + Contains the hex representation of the Synopsys component version. + 0 + 31 + read-only + + + + + 0x24 + 0x4 + DR[%s] + Description collection: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. + 0x060 + read-write + 0x00000000 + 0x20 + + + DR + Data Register. + 0 + 31 + + + + + RXSAMPLEDELAY + This register is only valid when the DWC_ssi is configured with rxd sample delay logic (SSIC_HAS_RX_SAMPLE_DELAY==1). + 0x0F0 + read-write + 0x00000000 + 0x20 + + + RSD + Receive Data (rxd) Sample Delay. + 0 + 7 + + + SE + Receive Data (rxd) Sampling Edge. + 16 + 16 + + + + + SPICTRLR0 + This register is used to control the serial data transfer in enhanced SPI mode of operation. + 0x0F4 + read-write + 0x00000A00 + 0x20 + + + TRANSTYPE + Address and instruction transfer format. + 0 + 1 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 2 + 5 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + XIPMDBITEN + Mode bits enable in XIP mode. + 7 + 7 + read-only + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 11 + 15 + + + SPIDDREN + SPI DDR Enable bit. + 16 + 16 + + + INSTDDREN + Instruction DDR Enable bit. + 17 + 17 + + + SPIRXDSEN + Read data strobe enable bit. + 18 + 18 + + + XIPDFSHC + Fix DFS for XIP transfers. + 19 + 19 + read-only + + + XIPINSTEN + XIP instruction enable bit. + 20 + 20 + read-only + + + SSICXIPCONTXFEREN + Enable continuous transfer in XIP mode. + 21 + 21 + read-only + + + SPIDMEN + SPI data mask enable bit. + 24 + 24 + + + SPIRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + read-only + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + read-only + + + CLKSTRETCHEN + Enables clock stretching capability in SPI transfers. + 30 + 30 + + + + + DDRDRIVEEDGE + This Register is valid only when SSIC_HAS_DDR is equal to 1. + 0x0F8 + read-write + 0x00000000 + 0x20 + + + TDE + TXD Drive edge register which decided the driving edge of transmit data. + 0 + 7 + + + + + XIPMODEBITS + This register carries the mode bits which are sent in the XIP mode of operation after address phase. + 0x0FC + read-write + 0x00000000 + 0x20 + + + XIPMDBITS + XIP mode bits to be sent after address phase of XIP transfer. + 0 + 15 + + + + + + SSICXIPADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICXIPADDRESS + read-write + 0x100 + + XIPINCRINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x000 + read-write + 0x00000000 + 0x20 + + + INCRINST + XIP INCR transfer opcode. + 0 + 15 + + + + + XIPWRAPINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + WRAPINST + XIP WRAP transfer opcode. + 0 + 15 + + + + + XIPCTRL + This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. + 0x008 + read-write + 0x08000401 + 0x20 + + + FRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + TRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 9 + 10 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + MDBITSEN + Mode bits enable in XIP mode. + 12 + 12 + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 13 + 17 + + + DFSHC + Fix DFS for XIP transfers. + 18 + 18 + + + DDREN + SPI DDR Enable bit. + 19 + 19 + + + INSTDDREN + Instruction DDR Enable bit. + 20 + 20 + + + RXDSEN + Read data strobe enable bit. + 21 + 21 + + + INSTEN + XIP instruction enable bit. + 22 + 22 + + + CONTXFEREN + Enable continuous transfer in XIP mode. + 23 + 23 + read-only + + + XIPHYPERBUSEN + SPI Hyperbus Frame format enable for XIP transfers. + 24 + 24 + + + RXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + + + + + XRXOICR + XIP Receive FIFO Overflow Interrupt Clear Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XRXOICR + Clear XIP Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + XIPWRITEINCRINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x040 + read-write + 0x00000000 + 0x20 + + + INCRWRITEINST + XIP Write INCR transfer opcode. + 0 + 15 + + + RSVDINCRINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITEWRAPINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x044 + read-write + 0x00000000 + 0x20 + + + WRAPWRITEINST + XIP Write WRAP transfer opcode. + 0 + 15 + + + RSVDWRAPINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITECTRL + This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. + 0x048 + read-write + 0x00000002 + 0x20 + + + WRFRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + WRTRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + WRADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + + + WRINSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WRSPIDDREN + SPI DDR Enable bit. + 10 + 10 + + + WRINSTDDREN + Instruction DDR Enable bit. + 11 + 11 + + + XIPWRHYPERBUSEN + SPI Hyperbus Frame format enable for XIP Write transfers. + 12 + 12 + + + XIPWRRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 13 + 13 + + + RSVDXIPWRITECTRL14TO15 + Reserved bits - Read Only + 14 + 15 + read-only + + + XIPWRWAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 16 + 20 + + + RSVDXIPWRITECTRL21TO31 + Reserved bits - Read Only + 21 + 31 + read-only + + + + + + + + + GLOBAL_EXMIF_S + External Memory Interface 1 + 0x5F095000 + + + + EXMIF + 149 + + + + GLOBAL_SECDOMBELLBOARD_NS + BELLBOARD public registers 0 + 0x4F099000 + BELLBOARDPUBLIC + + + + + 0 + 0x1000 + registers + + BELLBOARDPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_SECDOMBELLBOARD_S + BELLBOARD public registers 1 + 0x5F099000 + + + + + + GLOBAL_VPR120_NS + VPR peripheral registers 0 + 0x4F8C8000 + VPRPUBLIC + + + + 0 + 0x1000 + registers + + VPRPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_VPR120_S + VPR peripheral registers 1 + 0x5F8C8000 + + + + + GLOBAL_IPCT120_NS + IPCT APB registers 0 + 0x4F8D1000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT120_0 + 209 + + IPCT + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE4_FLUSH4 + Shortcut between event RECEIVE[4] and task FLUSH[4] + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE5_FLUSH5 + Shortcut between event RECEIVE[5] and task FLUSH[5] + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE6_FLUSH6 + Shortcut between event RECEIVE[6] and task FLUSH[6] + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE7_FLUSH7 + Shortcut between event RECEIVE[7] and task FLUSH[7] + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + GLOBAL_IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_4 + Overflow status for SEND[4] task + 4 + 4 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_5 + Overflow status for SEND[5] task + 5 + 5 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_6 + Overflow status for SEND[6] task + 6 + 6 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_7 + Overflow status for SEND[7] task + 7 + 7 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + GLOBAL_IPCT120_S + IPCT APB registers 1 + 0x5F8D1000 + + + + + IPCT120_0 + 209 + + + + GLOBAL_MUTEX120_NS + MUTEX 0 + 0x4F8D2000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x20 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + 0x00000000 + 0x20 + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0x0 + + + Locked + Mutex n is in locked state + 0x1 + + + + + + + + + GLOBAL_I3C120_NS + I3C 0 + 0x4F8D3000 + I3C + + + + 0 + 0x1000 + registers + + + I3C120 + 211 + + I3C + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable I3C peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + EN + Enable + 0 + 0 + + + Disabled + I3C peripheral disabled. + 0x0 + + + Enabled + I3C peripheral enabled. + 0x1 + + + + + + + CDR + Unspecified + I3C_CDR + read-write + 0x404 + + STARTOFFSET + Start offset of recovered clock + 0x000 + read-write + 0x00000004 + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXCYCLERATIO + Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock + 0x004 + read-write + 0x0000001C + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXSKEW + Maximum skew between SCL and SCL in CDR clock cycles + 0x008 + read-write + 0x00000005 + 0x20 + + + VAL + Value + 0 + 7 + + + + + + SLAVEIF0 + I3C slave interface 0 + 0x410 + read-write + 0x00000000 + 0x20 + + + MODEI2C + I2C or I3C mode select signal + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + ACTMODE + Slave activity mode for GETSTATUS CCC + 1 + 2 + + + PENDINGINT + Pending interrupt information for GETSTATUS CCC + 3 + 6 + + + STATICADDREN + Slave static address valid + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + STATICADDR + Slave static address + 8 + 14 + + + SLAVEMAXRDSPEED + Slave maximum read data rate + 15 + 17 + + + SLAVEMAXWRSPEED + Slave maximum write write rate + 18 + 20 + + + SLAVECLKDATATURNTIME + Slave maximum clock data turnaround time + 21 + 23 + + + SLAVEDCR + Device Characteristic Register value + 24 + 31 + + + + + SLAVEIF1 + I3C slave interface 1 + 0x414 + read-write + 0x00000000 + 0x20 + + + WAKEUP + Slave wakeup signal + 0 + 0 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SLAVEPID0 + Slave Device Provisioned ID 0 + 0x418 + read-write + 0x00000000 + 0x20 + + + ADDMEANING + Additional Meaning + 0 + 11 + + + INSTANCEID + Instance ID + 12 + 15 + + + PARTID + Part ID + 16 + 31 + + + + + SLAVEPID1 + Slave Device Provisioned ID 1 + 0x41C + read-write + 0x00000000 + 0x20 + + + PROVID + Provisional ID Type Selector + 0 + 0 + + + MIPIMID + MIPI Manufacturer ID + 1 + 15 + + + + + KEEPSDA + Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x420 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SDA high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + KEEPSCL + Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x424 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SCL high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + + + GLOBAL_I3C120_S + I3C 1 + 0x5F8D3000 + + + + I3C120 + 211 + + + + GLOBAL_VPR121_NS + VPR peripheral registers 0 + 0x4F8D4000 + VPR + + + + 0 + 0x1000 + registers + + + VPR121 + 212 + + VPR + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TASKS_TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + EN + Subscription enable bit + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: VPR event [n] register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + VPR event [n] register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event EVENTS_TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + EN + Publication enable bit + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + DEBUGIF + Unspecified + VPR_DEBUGIF + read-write + 0x400 + + DATA0 + Abstract Data 0. Read/write data for argument 0 + 0x10 + read-write + 0x00000000 + 0x20 + + + DATA0 + Abstract Data 0 + 0 + 31 + + + + + DATA1 + Abstract Data 1. Read/write data for argument 1 + 0x14 + read-write + 0x00000000 + 0x20 + + + DATA1 + Abstract Data 1 + 0 + 31 + + + + + DMCONTROL + Debug Module Control + 0x40 + read-write + 0x00000000 + 0x20 + + + DMACTIVE + Reset signal for the debug module. + 0 + 0 + + + Disabled + Reset the debug module itself + 0x0 + + + Enabled + Normal operation + 0x1 + + + + + NDMRESET + Reset signal output from the debug module to the system. + 1 + 1 + + + Inactive + Reset inactive + 0x0 + + + Active + Reset active + 0x1 + + + + + CLRRESETHALTREQ + Clear the halt on reset request. + 2 + 2 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the halt on reset request + 0x1 + + + + + SETRESETHALTREQ + Set the halt on reset request. + 3 + 3 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Sets the halt on reset request + 0x1 + + + + + HARTSELHI + The high 10 bits of hartsel. + 6 + 15 + write-only + + + HARTSELLO + The low 10 bits of hartsel. + 16 + 25 + write-only + + + HASEL + Definition of currently selected harts. + 26 + 26 + write-only + + + Single + Single hart selected. + 0x0 + + + Multiple + Multiple harts selected + 0x1 + + + + + ACKHAVERESET + Clear the havereset. + 28 + 28 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the havereset for selected harts. + 0x1 + + + + + HARTRESET + Reset harts. + 29 + 29 + + + Deasserted + Reset de-asserted. + 0x0 + + + Asserted + Reset asserted. + 0x1 + + + + + RESUMEREQ + Resume currently selected harts. + 30 + 30 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Resumed + Currently selected harts resumed. + 0x1 + + + + + HALTREQ + Halt currently selected harts. + 31 + 31 + write-only + + + Clear + Clears halt request bit for all currently selected harts. + 0x0 + + + Halt + Currently selected harts halted. + 0x1 + + + + + + + DMSTATUS + Debug Module Status + 0x44 + read-only + 0x00400082 + 0x20 + + + VERSION + Version of the debug module. + 0 + 3 + + + NotPresent + Debug module not present. + 0x0 + + + V011 + There is a Debug Module and it conforms to version 0.11 of this specifcation. + 0x1 + + + V013 + There is a Debug Module and it conforms to version 0.13 of this specifcation. + 0x2 + + + NonConform + There is a Debug Module but it does not conform to any available version of the spec. + 0xF + + + + + CONFSTRPTRVALID + Configuration string. + 4 + 4 + + + NotRelevant + The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. + 0x0 + + + Address + The confstrptr0..confstrptr3 holds the address of the configuration string. + 0x1 + + + + + HASRESETHALTREQ + Halt-on-reset support status. + 5 + 5 + + + No + Halt-on-reset is supported. + 0x0 + + + Yes + Halt-on-reset is not supported. + 0x1 + + + + + AUTHBUSY + Authentication busy status. + 6 + 6 + + + No + The authentication module is ready. + 0x0 + + + Yes + The authentication module is busy. + 0x1 + + + + + AUTHENTICATED + Authentication status. + 7 + 7 + + + No + Authentication required before using the debug module. + 0x0 + + + Yes + Authentication passed. + 0x1 + + + + + ANYHALTED + Any currently selected harts halted status. + 8 + 8 + + + No + None of the currently selected harts halted. + 0x0 + + + Yes + Any of the currently selected harts halted. + 0x1 + + + + + ALLHALTED + All currently selected harts halted status. + 9 + 9 + + + No + Not all of the currently selected harts halted. + 0x0 + + + Yes + All of the currently selected harts halted. + 0x1 + + + + + ANYRUNNING + Any currently selected harts running status. + 10 + 10 + + + No + None of the currently selected harts running. + 0x0 + + + Yes + Any of the currently selected harts running. + 0x1 + + + + + ALLRUNNING + All currently selected harts running status. + 11 + 11 + + + No + Not all of the currently selected harts running. + 0x0 + + + Yes + All of the currently selected harts running. + 0x1 + + + + + ANYUNAVAIL + Any currently selected harts unavailable status. + 12 + 12 + + + No + None of the currently selected harts unavailable. + 0x0 + + + Yes + Any of the currently selected harts unavailable. + 0x1 + + + + + ALLUNAVAIL + All currently selected harts unavailable status. + 13 + 13 + + + No + Not all of the currently selected harts unavailable. + 0x0 + + + Yes + All of the currently selected harts unavailable. + 0x1 + + + + + ANYNONEXISTENT + Any currently selected harts nonexistent status. + 14 + 14 + + + No + None of the currently selected harts nonexistent. + 0x0 + + + Yes + Any of the currently selected harts nonexistent. + 0x1 + + + + + ALLNONEXISTENT + All currently selected harts nonexistent status. + 15 + 15 + + + No + Not all of the currently selected harts nonexistent. + 0x0 + + + Yes + All of the currently selected harts nonexistent. + 0x1 + + + + + ANYRESUMEACK + Any currently selected harts acknowledged last resume request. + 16 + 16 + + + No + None of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + Any of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ALLRESUMEACK + All currently selected harts acknowledged last resume + 17 + 17 + + + No + Not all of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + All of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ANYHAVERESET + Any currently selected harts have been reset and reset is not acknowledged. + 18 + 18 + + + No + None of the currently selected harts have been reset and reset is not acknowledget. + 0x0 + + + Yes + Any of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + ALLHAVERESET + All currently selected harts have been reset and reset is not acknowledge + 19 + 19 + + + No + Not all of the currently selected harts have been reset and reset is not acknowledge. + 0x0 + + + Yes + All of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + IMPEBREAK + Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. + 22 + 22 + + + No + No implicit ebreak instruction. + 0x0 + + + Yes + Implicit ebreak instruction. + 0x1 + + + + + + + HARTINFO + Hart Information + 0x48 + read-write + 0x00000000 + 0x20 + + + DATAADDR + Data Address + 0 + 11 + read-only + + + DATASIZE + Data Size + 12 + 15 + read-only + + + DATAACCESS + Data Access + 16 + 16 + read-only + + + No + The data registers are shadowed in the hart + by CSRs. Each CSR is DXLEN bits in size, and + corresponds to a single argument. + 0x0 + + + Yes + The data registers are shadowed in the hart's + memory map. Each register takes up 4 bytes in + the memory map. + 0x1 + + + + + NSCRATCH + Number of dscratch registers + 20 + 23 + read-only + + + + + HALTSUM1 + Halt Summary 1 + 0x4C + read-write + 0x00000000 + 0x20 + + + HALTSUM1 + Halt Summary 1 + 0 + 31 + read-only + + + + + HAWINDOWSEL + Hart Array Window Select + 0x50 + read-write + 0x00000000 + 0x20 + + + HAWINDOWSEL + The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. + 0 + 14 + read-only + + + + + HAWINDOW + Hart Array Window + 0x54 + read-write + 0x00000000 + 0x20 + + + MASKDATA + Mask data. + 0 + 31 + + + + + ABSTRACTCS + Abstract Control and Status + 0x58 + read-write + 0x01000002 + 0x20 + + + DATACOUNT + Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. + 0 + 3 + read-only + + + CMDERR + Command error when the abstract command fails. + 8 + 10 + + + NoError + No error. + 0x0 + + + Busy + An abstract command was executing while command, + abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read + or written. This status is only written if cmderr contains 0 + 0x1 + + + NotSupported + The requested command is notsupported, + regardless of whether the hart is running or not. + 0x2 + + + Exception + An exception occurred while executing the + command (e.g. while executing theProgram Buffer). + 0x3 + + + HaltResume + The abstract command couldn't execute + because the hart wasn't in the required state (running/halted). or unavailable. + 0x4 + + + Bus + The abstract command failed due to abus + error (e.g. alignment, access size, or timeout). + 0x5 + + + Other + The command failed for another reason. + 0x7 + + + + + BUSY + Abstract command execution status. + 12 + 12 + read-only + + + NotBusy + Not busy. + 0x0 + + + Busy + An abstract command is currently being executed. + This bit is set as soon as command is written, and is not cleared until that command has completed. + 0x1 + + + + + PROGBUFSIZE + Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. + 24 + 28 + read-only + + + + + ABSTRACTCMD + Abstract command + 0x5C + write-only + 0x00000000 + 0x20 + + + CONTROL + This Field is interpreted in a command specific manner, described for each abstract command. + 0 + 23 + + + CMDTYPE + The type determines the overall functionality of this abstract command. + 24 + 31 + + + REGACCESS + Register Access Command + 0x00 + + + QUICKACCESS + Quick Access Command + 0x01 + + + MEMACCESS + Memory Access Command + 0x02 + + + + + + + ABSTRACTAUTO + Abstract Command Autoexec + 0x60 + read-write + 0x00000000 + 0x20 + + + AUTOEXECDATA + When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. + 0 + 11 + read-only + + + AUTOEXECPROGBUF + When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. + 16 + 31 + read-only + + + + + 0x4 + 0x4 + CONFSTRPTR[%s] + Description collection: Configuration String Pointer [n] + 0x64 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + NEXTDM + Next Debug Module + 0x74 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + 0x10 + 0x4 + PROGBUF[%s] + Description collection: Program Buffer [n] + 0x80 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + AUTHDATA + Authentication Data + 0xC0 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + HALTSUM2 + Halt Summary 2 + 0xD0 + read-write + 0x00000000 + 0x20 + + + HALTSUM2 + Halt Summary 2 + 0 + 31 + read-only + + + + + HALTSUM3 + Halt Summary 3 + 0xD4 + read-write + 0x00000000 + 0x20 + + + HALTSUM3 + Halt Summary 3 + 0 + 31 + read-only + + + + + SBADDRESS3 + System Bus Addres 127:96 + 0xDC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 127:96 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBCS + System Bus Access Control and Status + 0xE0 + read-write + 0x20000000 + 0x20 + + + SBACCESS8 + 0 + 0 + read-only + + + sbaccess8 + 8-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS16 + 1 + 1 + read-only + + + sbaccess16 + 16-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS32 + 2 + 2 + read-only + + + sbaccess32 + 32-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS64 + 3 + 3 + read-only + + + sbaccess64 + 64-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS128 + 4 + 4 + read-only + + + sbaccess128 + 128-bit system bus accesses are supported. + 0x1 + + + + + SBASIZE + Width of system bus addresses in bits. (0 indicates there is no bus access support.) + 5 + 11 + read-only + + + SBERROR + 12 + 14 + read-only + + + Normal + There was no bus error. + 0x0 + + + Timeout + There was a timeout. + 0x1 + + + Address + A bad address was accessed. + 0x2 + + + Alignment + There was an alignment error. + 0x3 + + + Size + An access of unsupported size was requested. + 0x4 + + + Other + Other. + 0x7 + + + + + SBREADONDATA + 15 + 15 + read-only + + + sbreadondata + Every read from sbdata0 automatically + triggers a system bus read at the (possibly autoincremented) address. + 0x1 + + + + + SBAUTOINCREMENT + 16 + 16 + read-only + + + sbautoincrement + sbaddress is incremented by the access + size (in bytes) selected in sbaccess after every system bus access. + 0x1 + + + + + SBACCESS + 17 + 19 + read-only + + + size8 + 8-bit. + 0x0 + + + size16 + 16-bit. + 0x1 + + + size32 + 32-bit. + 0x2 + + + size64 + 64-bit. + 0x3 + + + size128 + 128-bit. + 0x4 + + + + + SBREADONADDR + 20 + 20 + read-only + + + sbreadonaddr + Every write to sbaddress0 automatically + triggers a system bus read at the new address. + 0x1 + + + + + SBBUSY + 21 + 21 + read-only + + + notbusy + System bus master is not busy. + 0x0 + + + busy + System bus master is busy. + 0x1 + + + + + SBBUSYERROR + 22 + 22 + read-only + + + noerror + No error. + 0x0 + + + error + Debugger access attempted while one in progress. + 0x1 + + + + + SBVERSION + 29 + 31 + read-only + + + version0 + The System Bus interface conforms to mainline + drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. + 0x0 + + + version1 + The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. + Other values are reserved for future versions. + 0x1 + + + + + + + SBADDRESS0 + System Bus Addres 31:0 + 0xE4 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 31:0 of the physical address in + sbaddress. + 0 + 31 + read-only + + + + + SBADDRESS1 + System Bus Addres 63:32 + 0xE8 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 63:32 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBADDRESS2 + System Bus Addres 95:64 + 0xEC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 95:64 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBDATA0 + System Bus Data 31:0 + 0xF0 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 31:0 of sbdata + 0 + 31 + read-only + + + + + SBDATA1 + System Bus Data 63:32 + 0xF4 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 63:32 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA2 + System Bus Data 95:64 + 0xF8 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 95:64 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA3 + System Bus Data 127:96 + 0xFC + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 127:96 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + HALTSUM0 + Halt summary 0 + 0x100 + read-write + 0x00000000 + 0x20 + + + HALTSUM0 + Halt summary 0 + 0 + 31 + read-only + + + + + + CPURUN + State of the CPU after a core reset + 0x800 + read-write + 0x00000000 + 0x20 + + + EN + Controls CPU running state after a core reset. + 0 + 0 + + + Stopped + CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. + 0x0 + + + Running + CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. + 0x1 + + + + + + + INITPC + Initial value of the PC at CPU start. + 0x808 + read-write + 0x00000000 + 0x20 + + + INITPC + Initial value of the PC at CPU start. + 0 + 31 + + + + + + + GLOBAL_VPR121_S + VPR peripheral registers 1 + 0x5F8D4000 + + + + VPR121 + 212 + + + + GLOBAL_CAN120_NS + Controller Area Network 0 + 0x4F8D8000 + CAN + + + + 0 + 0x1000 + registers + + + CAN120 + 216 + + CAN + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the CAN peripheral + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_CORE[%s] + Description collection: Event indicating that interrupt n triggered at CAN core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt n triggered at CAN core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READYFORSTOP_STOP + Shortcut between event READYFORSTOP and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE0 + Enable or disable interrupt for event CORE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CORE1 + Enable or disable interrupt for event CORE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMU + Enable or disable interrupt for event DMU + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READYFORSTOP + Enable or disable interrupt for event READYFORSTOP + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to enable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CORE1 + Write '1' to enable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMU + Write '1' to enable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READYFORSTOP + Write '1' to enable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to disable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CORE1 + Write '1' to disable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMU + Write '1' to disable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READYFORSTOP + Write '1' to disable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE0 + Read pending status of interrupt for event CORE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CORE1 + Read pending status of interrupt for event CORE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMU + Read pending status of interrupt for event DMU + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READYFORSTOP + Read pending status of interrupt for event READYFORSTOP + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_CAN120_S + Controller Area Network 1 + 0x5F8D8000 + + + + CAN120 + 216 + + + + GLOBAL_MVDMA120_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x4F8D9000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA120 + 217 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + GLOBAL_MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + GLOBAL_MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + GLOBAL_MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + GLOBAL_MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + GLOBAL_MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + GLOBAL_MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + GLOBAL_MVDMA120_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x5F8D9000 + + + + MVDMA120 + 217 + + + + GLOBAL_RAMC122_NS + RAM Controller 0 + 0x4F8DA000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + + + GLOBAL_RAMC122_S + RAM Controller 1 + 0x5F8DA000 + + + + + GLOBAL_CAN121_NS + Controller Area Network 2 + 0x4F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_CAN121_S + Controller Area Network 3 + 0x5F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_MVDMA121_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 2 + 0x4F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_MVDMA121_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 3 + 0x5F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_RAMC123_NS + RAM Controller 2 + 0x4F8DD000 + + + + + GLOBAL_RAMC123_S + RAM Controller 3 + 0x5F8DD000 + + + + + GLOBAL_I3C121_NS + I3C 2 + 0x4F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_I3C121_S + I3C 3 + 0x5F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_DPPIC120_NS + Distributed programmable peripheral interconnect controller 0 + 0x4F8E1000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 4 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 4 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x4 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + 0x20 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + GLOBAL_DPPIC120_S + Distributed programmable peripheral interconnect controller 1 + 0x5F8E1000 + + + + + + GLOBAL_TIMER120_NS + Timer/Counter 0 + 0x4F8E2000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER120 + 226 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + 0x20 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + 0x20 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + 0x20 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + 0x00000000 + 0x20 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + + + GLOBAL_TIMER120_S + Timer/Counter 1 + 0x5F8E2000 + + + + TIMER120 + 226 + + + + GLOBAL_TIMER121_NS + Timer/Counter 2 + 0x4F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_TIMER121_S + Timer/Counter 3 + 0x5F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_PWM120_NS + Pulse width modulation unit 0 + 0x4F8E4000 + PWM + + + + 0 + 0x1000 + registers + + + PWM120 + 228 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + PWM_TASKS_DMA + write-only + 0x010 + + 2 + 0x008 + SEQ[%s] + Peripheral tasks. + PWM_TASKS_DMA_SEQ + write-only + 0x000 + + START + Description cluster: Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA + read-write + 0x090 + + 2 + 0x008 + SEQ[%s] + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA_SEQ + read-write + 0x000 + + START + Description cluster: Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PWM_EVENTS_DMA + read-write + 0x124 + + 2 + 0x00C + SEQ[%s] + Peripheral events. + PWM_EVENTS_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + Description cluster: An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + 0x4 + 0x4 + EVENTS_COMPAREMATCH[%s] + Description collection: This event is generated when the compare matches for the compare channel [n]. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPAREMATCH + This event is generated when the compare matches for the compare channel [n]. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RAMUNDERFLOW + Publish configuration for event RAMUNDERFLOW + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RAMUNDERFLOW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PWM_PUBLISH_DMA + read-write + 0x1A4 + + 2 + 0x00C + SEQ[%s] + Publish configuration for events + PWM_PUBLISH_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Description cluster: Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Description cluster: Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + 0x4 + 0x4 + PUBLISH_COMPAREMATCH[%s] + Description collection: Publish configuration for event COMPAREMATCH[n] + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPAREMATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + SEQEND0_STOP + Shortcut between event SEQEND[n] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[n] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RAMUNDERFLOW_STOP + Shortcut between event RAMUNDERFLOW and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ0_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ1_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RAMUNDERFLOW + Enable or disable interrupt for event RAMUNDERFLOW + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0END + Enable or disable interrupt for event DMASEQ0END + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0READY + Enable or disable interrupt for event DMASEQ0READY + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Enable or disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1END + Enable or disable interrupt for event DMASEQ1END + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1READY + Enable or disable interrupt for event DMASEQ1READY + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Enable or disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH0 + Enable or disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH1 + Enable or disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH2 + Enable or disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH3 + Enable or disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to enable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0END + Write '1' to enable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0READY + Write '1' to enable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to enable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1END + Write '1' to enable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1READY + Write '1' to enable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to enable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to enable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to enable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to enable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to enable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to disable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0END + Write '1' to disable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0READY + Write '1' to disable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1END + Write '1' to disable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1READY + Write '1' to disable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED0 + Read pending status of interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED1 + Read pending status of interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND0 + Read pending status of interrupt for event SEQEND[0] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND1 + Read pending status of interrupt for event SEQEND[1] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LOOPSDONE + Read pending status of interrupt for event LOOPSDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RAMUNDERFLOW + Read pending status of interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0END + Read pending status of interrupt for event DMASEQ0END + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0READY + Read pending status of interrupt for event DMASEQ0READY + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0BUSERROR + Read pending status of interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1END + Read pending status of interrupt for event DMASEQ1END + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1READY + Read pending status of interrupt for event DMASEQ1READY + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1BUSERROR + Read pending status of interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH0 + Read pending status of interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH1 + Read pending status of interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH2 + Read pending status of interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH3 + Read pending status of interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + IDLEOUT + Configure the output value on the PWM channel during idle + 0x518 + read-write + 0x00000000 + 0x20 + + + VAL_0 + Idle output value for PWM channel [0] + 0 + 0 + + + VAL_1 + Idle output value for PWM channel [1] + 1 + 1 + + + VAL_2 + Idle output value for PWM channel [2] + 2 + 2 + + + VAL_3 + Idle output value for PWM channel [3] + 3 + 3 + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + PWM_DMA + read-write + 0x700 + + 2 + 0x024 + SEQ[%s] + Unspecified + PWM_DMA_SEQ + read-write + 0x000 + + PTR + Description cluster: RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Description cluster: Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_PWM120_S + Pulse width modulation unit 1 + 0x5F8E4000 + + + + PWM120 + 228 + + + + GLOBAL_SPIS120_NS + SPI Slave 0 + 0x4F8E5000 + SPIS + + + + 0 + 0x1000 + registers + + + SPIS120 + 229 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIS_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIS_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIS_DMA + read-write + 0x700 + + RX + Unspecified + SPIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIS120_S + SPI Slave 1 + 0x5F8E5000 + + + + SPIS120 + 229 + + + + GLOBAL_SPIM120_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x4F8E6000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIM_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STARTED + SPI transaction has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + SPI transaction has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PRESCALER + The prescaler is used to set the SPI frequency. + 0x52C + read-write + 0x00000040 + 0x20 + + + DIVISOR + Core clock to SCK divisor + 0 + 6 + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x5AC + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of SPIM core clock cycles. + 0 + 7 + + + + + + DCXCNT + DCX configuration + 0x5B4 + read-write + 0x00000000 + 0x20 + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + CSNPOL + Polarity of CSN output + 0x5B8 + read-write + 0x00000000 + 0x20 + + + CSNPOL_0 + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0x0 + + + HIGH + Active high (idle state low) + 0x1 + + + + + + + CSNCONTROL + Selects which CSN is used, only one CSN can be active at one time. This register can be safely written during an ongoing SPI transaction. + 0x5BC + read-write + 0x00000000 + 0x20 + + + CSN + CSN Number. + 0 + 0 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DCX + Pin select for DCX signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + 0x1 + 0x4 + CSN[%s] + Description collection: Pin select for CSN + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIM_DMA + read-write + 0x700 + + RX + Unspecified + SPIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE120_NS + UART with EasyDMA 0 + 0x4F8E6000 + GLOBAL_SPIM120_NS + UARTE + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + UARTE + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + UARTE_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + UARTE_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + UARTE_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x124 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + UARTE_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + UARTE_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + UARTE_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0x174 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + UARTE_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + UARTE_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + UARTE_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + PUBLISH_FRAMETIMEOUT + Publish configuration for event FRAMETIMEOUT + 0x1F4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMETIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + DMA_RX_END_DMA_RX_START + Shortcut between event DMA.RX.END and task DMA.RX.START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_END_DMA_RX_STOP + Shortcut between event DMA.RX.END and task DMA.RX.STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_TX_END_DMA_TX_STOP + Shortcut between event DMA.TX.END and task DMA.TX.STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMETIMEOUT_DMA_RX_STOP + Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP + 29 + 29 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMETIMEOUT + Enable or disable interrupt for event FRAMETIMEOUT + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to enable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to disable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + CONFIG + Configuration of parity, hardware flow control, framesize, and packet timeout. + 0x56C + read-write + 0x00001000 + 0x20 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0x0 + + + Odd + Odd parity + 0x1 + + + + + FRAMESIZE + Set the data frame size + 9 + 12 + + + 9bit + 9 bit data frame size. 9th bit is treated as address bit. + 0x9 + + + 8bit + 8 bit data frame size. + 0x8 + + + 7bit + 7 bit data frame size. + 0x7 + + + 6bit + 6 bit data frame size. + 0x6 + + + 5bit + 5 bit data frame size. + 0x5 + + + 4bit + 4 bit data frame size. + 0x4 + + + + + ENDIAN + Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. + 13 + 13 + + + MSB + Data is trimmed from MSB end. + 0x0 + + + LSB + Data is trimmed from LSB end. + 0x1 + + + + + FRAMETIMEOUT + Enable packet timeout. + 14 + 14 + + + DISABLED + Packet timeout is disabled. + 0x0 + + + ENABLED + Packet timeout is enabled. + 0x1 + + + + + + + ADDRESS + Set the address of the UARTE for RX when used in 9 bit data frame mode. + 0x574 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Set address + 0 + 7 + + + + + FRAMETIMEOUT + Set the number of UARTE bits to count before triggering packet timeout. + 0x578 + read-write + 0x00000010 + 0x20 + + + COUNTERTOP + Number of UARTE bits before timeout. + 0 + 9 + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x604 + + TXD + Pin select for TXD signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RTS + Pin select for RTS signal + 0x0C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + UARTE_DMA + read-write + 0x700 + + RX + Unspecified + UARTE_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + UARTE_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + UARTE_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM120_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x5F8E6000 + + + + SPIM120_UARTE120 + 230 + + + + GLOBAL_UARTE120_S + UART with EasyDMA 1 + 0x5F8E6000 + GLOBAL_SPIM120_S + + + + SPIM120_UARTE120 + 230 + + + + GLOBAL_SPIM121_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x4F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_SPIM121_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x5F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_VPR130_NS + VPR peripheral registers 2 + 0x4F908000 + + + + VPR130 + 264 + + + + GLOBAL_VPR130_S + VPR peripheral registers 3 + 0x5F908000 + + + + VPR130 + 264 + + + + GLOBAL_IPCT130_NS + IPCT APB registers 2 + 0x4F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_IPCT130_S + IPCT APB registers 3 + 0x5F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_DPPIC130_NS + Distributed programmable peripheral interconnect controller 2 + 0x4F922000 + + + + + + GLOBAL_DPPIC130_S + Distributed programmable peripheral interconnect controller 3 + 0x5F922000 + + + + + + GLOBAL_MUTEX130_NS + MUTEX 1 + 0x4F927000 + + + + + GLOBAL_RTC130_NS + Real-time counter 0 + 0x4F928000 + RTC + + + + 0 + 0x1000 + registers + + + RTC130 + 296 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable event routing for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable event routing for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable event routing for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable event routing for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 31 + + + + + + + GLOBAL_RTC130_S + Real-time counter 1 + 0x5F928000 + + + + RTC130 + 296 + + + + GLOBAL_RTC131_NS + Real-time counter 2 + 0x4F929000 + + + + RTC131 + 297 + + + + GLOBAL_RTC131_S + Real-time counter 3 + 0x5F929000 + + + + RTC131 + 297 + + + + GLOBAL_WDT131_NS + Watchdog Timer 4 + 0x4F92B000 + + + + WDT131 + 299 + + + + GLOBAL_WDT131_S + Watchdog Timer 5 + 0x5F92B000 + + + + WDT131 + 299 + + + + GLOBAL_WDT132_NS + Watchdog Timer 6 + 0x4F92C000 + + + + WDT132 + 300 + + + + GLOBAL_WDT132_S + Watchdog Timer 7 + 0x5F92C000 + + + + WDT132 + 300 + + + + GLOBAL_EGU130_NS + Event generator unit 0 + 0x4F92D000 + EGU + + + + 0 + 0x1000 + registers + + + EGU130 + 301 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_EGU130_S + Event generator unit 1 + 0x5F92D000 + + + + EGU130 + 301 + + + + GLOBAL_P0_NS + GPIO Port 0 + 0x4F938000 + GPIO + + + + + 0 + 0x200 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x000 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x004 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x00C + read-only + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x010 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x014 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x018 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + 0x20 + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x024 + read-write + 0x00000000 + 0x20 + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + RETAIN + Enable retention for those GPIO registers marked as retained + 0x028 + read-write + 0x0000000C + 0x20 + + + APPLICAION + Enable retention for GPIO registers for Application domain + 2 + 2 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + RADIOCORE + Enable retention for GPIO registers for Radio core + 3 + 3 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + + + PORTCNF + Unspecified + GPIO_PORTCNF + read-write + 0x030 + + DRIVECTRL + Drive control for impedance matching of the pins in this port + 0x00 + read-write + 0x00000000 + 0x20 + + + + IMPEDANCE50 + Enable 50 ohms impedance to the pins in this port + 0 + 0 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE100 + Enable 100 ohms impedance to the pins in this port + 1 + 1 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE200 + Enable 200 ohms impedance to the pins in this port + 2 + 2 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE400 + Enable 400 ohms impedance to the pins in this port + 3 + 3 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE800 + Enable 800 ohms impedance to the pins in this port + 4 + 4 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE1600 + Enable 1600 ohms impedance to the pins in this port + 5 + 5 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Pin n configuration of GPIO pin + 0x080 + read-write + 0x00000002 + 0x20 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE0 + Drive configuration for '0' + 8 + 9 + + + S0 + Standard '0' + 0x0 + + + H0 + High drive '0' + 0x1 + + + D0 + Disconnect '0'(normally used for wired-or connections) + 0x2 + + + E0 + Extra high drive '0' + 0x3 + + + + + DRIVE1 + Drive configuration for '1' + 10 + 11 + + + S1 + Standard '1' + 0x0 + + + H1 + High drive '1' + 0x1 + + + D1 + Disconnect '1'(normally used for wired-or connections) + 0x2 + + + E1 + Extra high drive '1' + 0x3 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + CLOCKPIN + Enable clock on the pin. + 31 + 31 + + + Disabled + Clock disabled + 0x0 + + + Enabled + Clock enabled + 0x1 + + + + + + + + + GLOBAL_P1_NS + GPIO Port 1 + 0x4F938200 + + + + + + GLOBAL_P2_NS + GPIO Port 2 + 0x4F938400 + + + + + + GLOBAL_P6_NS + GPIO Port 3 + 0x4F938C00 + + + + + + GLOBAL_P0_S + GPIO Port 4 + 0x5F938000 + + + + + + GLOBAL_P1_S + GPIO Port 5 + 0x5F938200 + + + + + + GLOBAL_P2_S + GPIO Port 6 + 0x5F938400 + + + + + + GLOBAL_P6_S + GPIO Port 7 + 0x5F938C00 + + + + + + GLOBAL_P8_NS + GPIO Port 8 + 0x4F939000 + + + + + + GLOBAL_P9_NS + GPIO Port 9 + 0x4F939200 + + + + + + GLOBAL_P10_NS + GPIO Port 10 + 0x4F939400 + + + + + + GLOBAL_P11_NS + GPIO Port 11 + 0x4F939600 + + + + + + GLOBAL_P12_NS + GPIO Port 12 + 0x4F939800 + + + + + + GLOBAL_P13_NS + GPIO Port 13 + 0x4F939A00 + + + + + + GLOBAL_P8_S + GPIO Port 14 + 0x5F939000 + + + + + + GLOBAL_P9_S + GPIO Port 15 + 0x5F939200 + + + + + + GLOBAL_P10_S + GPIO Port 16 + 0x5F939400 + + + + + + GLOBAL_P11_S + GPIO Port 17 + 0x5F939600 + + + + + + GLOBAL_P12_S + GPIO Port 18 + 0x5F939800 + + + + + + GLOBAL_P13_S + GPIO Port 19 + 0x5F939A00 + + + + + + GLOBAL_DPPIC131_NS + Distributed programmable peripheral interconnect controller 4 + 0x4F981000 + + + + + + GLOBAL_DPPIC131_S + Distributed programmable peripheral interconnect controller 5 + 0x5F981000 + + + + + + GLOBAL_SAADC_NS + Analog to Digital Converter 0 + 0x4F982000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 386 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + GLOBAL_SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + GLOBAL_SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + TRIM + Unspecified + GLOBAL_SAADC_TRIM + read-write + 0x440 + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Linearity calibration coefficient + 0x000 + read-write + 0x00000000 + 0x20 + + + VAL + value + 0 + 15 + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + GLOBAL_SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x0 + read-write + 0x00000000 + 0x20 + + + PIN + Analog positive input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x4 + read-write + 0x00000000 + 0x20 + + + PIN + Analog negative input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + GAIN + Gain control + 8 + 9 + + + Gain2_3 + 2/3 + 0x0 + + + Gain1 + 1 + 0x1 + + + Gain2 + 2 + 0x2 + + + Gain4 + 4 + 0x3 + + + + + BURST + Enable burst mode + 11 + 11 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (1.024 V) + 0x0 + + + External + External reference given at PADC_EXT_REF_1V2 + 0x1 + + + + + MODE + Enable differential mode + 15 + 15 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) + 16 + 24 + + + TCONV + Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) + 28 + 30 + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + 0x20 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + GLOBAL_SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of buffer bytes to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer bytes transferred since last START + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + GLOBAL_SAADC_S + Analog to Digital Converter 1 + 0x5F982000 + + + + SAADC + 386 + + + + GLOBAL_COMP_NS + Comparator 0 + 0x4F983000 + COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (AVDD_AO_1V8 &gt;= 1.7 V) + 0x0 + + + AVDDAO1V8 + VREF = AVDD_AO_1V8 + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00002020 + 0x20 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 0 + + + Low + Low-power mode + 0x0 + + + High + High-speed mode + 0x1 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0x0 + + + Diff + Differential mode + 0x1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0x0 + + + Hyst40mV + Comparator hysteresis enabled + 0x1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + 0x00000000 + 0x20 + + + ISOURCE + Current source select on analog input + 0 + 1 + + + Off + Current source disabled + 0x0 + + + Ien2uA5 + Current source enabled (+/- 2.5 uA) + 0x1 + + + Ien5uA + Current source enabled (+/- 5 uA) + 0x2 + + + Ien10uA + Current source enabled (+/- 10 uA) + 0x3 + + + + + + + + + GLOBAL_LPCOMP_NS + Low-power comparator 0 + 0x4F983000 + GLOBAL_COMP_NS + LPCOMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0x0 + + + Enabled + Comparator hysteresis enabled + 0x1 + + + + + + + + + GLOBAL_COMP_S + Comparator 1 + 0x5F983000 + + + + COMP_LPCOMP + 387 + + + + GLOBAL_LPCOMP_S + Low-power comparator 1 + 0x5F983000 + GLOBAL_COMP_S + + + + COMP_LPCOMP + 387 + + + + GLOBAL_TEMP_NS + Temperature Sensor 0 + 0x4F984000 + TEMP + + + + 0 + 0x1000 + registers + + + TEMP + 388 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DATARDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + 0x00000000 + int32_t + 0x20 + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000276 + 0x20 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000324 + 0x20 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AB + 0x20 + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000453 + 0x20 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000049B + 0x20 + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x00000550 + 0x20 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + A6 + Slope of 7th piece wise linear function + 0x538 + read-write + 0x0000067E + 0x20 + + + A6 + Slope of 7th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00000FA6 + 0x20 + + + B0 + y-intercept of 1st piece wise linear function + 0 + 11 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00000F35 + 0x20 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 11 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00000FAA + 0x20 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 11 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x0000007E + 0x20 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 11 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x000000EA + 0x20 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 11 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x000001ED + 0x20 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 11 + + + + + B6 + y-intercept of 7th piece wise linear function + 0x558 + read-write + 0x00000378 + 0x20 + + + B6 + y-intercept of 7th piece wise linear function + 0 + 11 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000ED + 0x20 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000013 + 0x20 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000029 + 0x20 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + 0x20 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000044 + 0x20 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + T5 + End point of 6th piece wise linear function + 0x574 + read-write + 0x00000053 + 0x20 + + + T5 + End point of 6th piece wise linear function + 0 + 7 + + + + + + + GLOBAL_TEMP_S + Temperature Sensor 1 + 0x5F984000 + + + + TEMP + 388 + + + + GLOBAL_DPPIC132_NS + Distributed programmable peripheral interconnect controller 6 + 0x4F991000 + + + + + + GLOBAL_DPPIC132_S + Distributed programmable peripheral interconnect controller 7 + 0x5F991000 + + + + + + GLOBAL_I2S130_NS + Inter-IC Sound 0 + 0x4F992000 + I2S + + + + 0 + 0x1000 + registers + + + I2S130 + 402 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + GLOBAL_I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + 0x20 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + 0x20 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + 0x20 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + 0x20 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0x0 + + + 16Bit + 16 bit sample. + 0x1 + + + 24Bit + 24 bit sample. + 0x2 + + + 32Bit + 32 bit sample. + 0x3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 0x4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 0x5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 0x6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 0x7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + 0x20 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + 0x20 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + 0x20 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + 0x20 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0x0 + + + Enable + Enable bypass + 0x1 + + + + + + + + RXD + Unspecified + GLOBAL_I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + GLOBAL_I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + GLOBAL_I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + GLOBAL_I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + GLOBAL_I2S130_S + Inter-IC Sound 1 + 0x5F992000 + + + + I2S130 + 402 + + + + GLOBAL_PDM_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x4F993000 + PDM + + + + 0 + 0x1000 + registers + + + PDM + 403 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STARTED + Read pending status of interrupt for event STARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + END + Read pending status of interrupt for event END + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + 0x20 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + 0x20 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled. + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + 0x20 + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate + 0 + 2 + + + Ratio64 + Ratio of 64 + 0x0 + + + Ratio80 + Ratio of 80 + 0x1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + 0x20 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + 0x20 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + 0x20 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + DMA + Unspecified + PDM_DMA + read-write + 0x700 + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x004 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_PDM_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x5F993000 + + + + PDM + 403 + + + + GLOBAL_QDEC130_NS + Quadrature Decoder 0 + 0x4F994000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC130 + 404 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SAMPLERDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event REPORTRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACCOF will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DBLRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + 0x00000000 + 0x20 + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0x0 + + + ActiveHigh + Led active on output pin high + 0x1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0x0 + + + 256us + 256 us + 0x1 + + + 512us + 512 us + 0x2 + + + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0x0 + + + 40Smpl + 40 samples/report + 0x1 + + + 80Smpl + 80 samples/report + 0x2 + + + 120Smpl + 120 samples/report + 0x3 + + + 160Smpl + 160 samples/report + 0x4 + + + 200Smpl + 200 samples/report + 0x5 + + + 240Smpl + 240 samples/report + 0x6 + + + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0x0 + + + Enabled + Debounce input filters enabled + 0x1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + GLOBAL_QDEC130_S + Quadrature Decoder 1 + 0x5F994000 + + + + QDEC130 + 404 + + + + GLOBAL_QDEC131_NS + Quadrature Decoder 2 + 0x4F995000 + + + + QDEC131 + 405 + + + + GLOBAL_QDEC131_S + Quadrature Decoder 3 + 0x5F995000 + + + + QDEC131 + 405 + + + + GLOBAL_I2S131_NS + Inter-IC Sound 2 + 0x4F997000 + + + + I2S131 + 407 + + + + GLOBAL_I2S131_S + Inter-IC Sound 3 + 0x5F997000 + + + + I2S131 + 407 + + + + GLOBAL_DPPIC133_NS + Distributed programmable peripheral interconnect controller 8 + 0x4F9A1000 + + + + + + GLOBAL_DPPIC133_S + Distributed programmable peripheral interconnect controller 9 + 0x5F9A1000 + + + + + + GLOBAL_TIMER130_NS + Timer/Counter 4 + 0x4F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER130_S + Timer/Counter 5 + 0x5F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER131_NS + Timer/Counter 6 + 0x4F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_TIMER131_S + Timer/Counter 7 + 0x5F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_PWM130_NS + Pulse width modulation unit 2 + 0x4F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_PWM130_S + Pulse width modulation unit 3 + 0x5F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_SPIM130_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130_NS + SPI Slave 2 + 0x4F9A5000 + GLOBAL_SPIM130_NS + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x4F9A5000 + GLOBAL_SPIM130_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIM + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + TWIM_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + TWIM_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + LASTTX_DMA_RX_START + Shortcut between event LASTTX and task DMA.RX.START + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_DMA_TX_START + Shortcut between event LASTRX and task DMA.TX.START + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIM_DMA + read-write + 0x700 + + RX + Unspecified + TWIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_TWIS130_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x4F9A5000 + GLOBAL_SPIM130_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIS_TASKS_DMA + write-only + 0x030 + + RX + Peripheral tasks. + TWIS_TASKS_DMA_RX + write-only + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA + read-write + 0x0B0 + + RX + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA_RX + read-write + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + 0x20 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + 0x20 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIS_DMA + read-write + 0x700 + + RX + Unspecified + TWIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE130_NS + UART with EasyDMA 2 + 0x4F9A5000 + GLOBAL_SPIM130_NS + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM130_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130_S + SPI Slave 3 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_TWIS130_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_UARTE130_S + UART with EasyDMA 3 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM131_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131_NS + SPI Slave 4 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131_NS + UART with EasyDMA 4 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_SPIM131_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131_S + SPI Slave 5 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131_S + UART with EasyDMA 5 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_DPPIC134_NS + Distributed programmable peripheral interconnect controller 10 + 0x4F9B1000 + + + + + + GLOBAL_DPPIC134_S + Distributed programmable peripheral interconnect controller 11 + 0x5F9B1000 + + + + + + GLOBAL_TIMER132_NS + Timer/Counter 8 + 0x4F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER132_S + Timer/Counter 9 + 0x5F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER133_NS + Timer/Counter 10 + 0x4F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_TIMER133_S + Timer/Counter 11 + 0x5F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_PWM131_NS + Pulse width modulation unit 4 + 0x4F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_PWM131_S + Pulse width modulation unit 5 + 0x5F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_SPIM132_NS + Serial Peripheral Interface Master with EasyDMA 8 + 0x4F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132_NS + SPI Slave 6 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132_NS + UART with EasyDMA 6 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM132_S + Serial Peripheral Interface Master with EasyDMA 9 + 0x5F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132_S + SPI Slave 7 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132_S + UART with EasyDMA 7 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM133_NS + Serial Peripheral Interface Master with EasyDMA 10 + 0x4F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133_NS + SPI Slave 8 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133_NS + UART with EasyDMA 8 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_SPIM133_S + Serial Peripheral Interface Master with EasyDMA 11 + 0x5F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133_S + SPI Slave 9 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133_S + UART with EasyDMA 9 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_DPPIC135_NS + Distributed programmable peripheral interconnect controller 12 + 0x4F9C1000 + + + + + + GLOBAL_DPPIC135_S + Distributed programmable peripheral interconnect controller 13 + 0x5F9C1000 + + + + + + GLOBAL_TIMER134_NS + Timer/Counter 12 + 0x4F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER134_S + Timer/Counter 13 + 0x5F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER135_NS + Timer/Counter 14 + 0x4F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_TIMER135_S + Timer/Counter 15 + 0x5F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_PWM132_NS + Pulse width modulation unit 6 + 0x4F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_PWM132_S + Pulse width modulation unit 7 + 0x5F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_SPIM134_NS + Serial Peripheral Interface Master with EasyDMA 12 + 0x4F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134_NS + SPI Slave 10 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134_NS + I2C compatible Two-Wire Master Interface with EasyDMA 8 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 8 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134_NS + UART with EasyDMA 10 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM134_S + Serial Peripheral Interface Master with EasyDMA 13 + 0x5F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134_S + SPI Slave 11 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134_S + I2C compatible Two-Wire Master Interface with EasyDMA 9 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134_S + I2C compatible Two-Wire Slave Interface with EasyDMA 9 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134_S + UART with EasyDMA 11 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM135_NS + Serial Peripheral Interface Master with EasyDMA 14 + 0x4F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135_NS + SPI Slave 12 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135_NS + I2C compatible Two-Wire Master Interface with EasyDMA 10 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 10 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135_NS + UART with EasyDMA 12 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_SPIM135_S + Serial Peripheral Interface Master with EasyDMA 15 + 0x5F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135_S + SPI Slave 13 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135_S + I2C compatible Two-Wire Master Interface with EasyDMA 11 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135_S + I2C compatible Two-Wire Slave Interface with EasyDMA 11 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135_S + UART with EasyDMA 13 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_DPPIC136_NS + Distributed programmable peripheral interconnect controller 14 + 0x4F9D1000 + + + + + + GLOBAL_DPPIC136_S + Distributed programmable peripheral interconnect controller 15 + 0x5F9D1000 + + + + + + GLOBAL_TIMER136_NS + Timer/Counter 16 + 0x4F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER136_S + Timer/Counter 17 + 0x5F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER137_NS + Timer/Counter 18 + 0x4F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_TIMER137_S + Timer/Counter 19 + 0x5F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_PWM133_NS + Pulse width modulation unit 8 + 0x4F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_PWM133_S + Pulse width modulation unit 9 + 0x5F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_SPIM136_NS + Serial Peripheral Interface Master with EasyDMA 16 + 0x4F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136_NS + SPI Slave 14 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136_NS + I2C compatible Two-Wire Master Interface with EasyDMA 12 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 12 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136_NS + UART with EasyDMA 14 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM136_S + Serial Peripheral Interface Master with EasyDMA 17 + 0x5F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136_S + SPI Slave 15 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136_S + I2C compatible Two-Wire Master Interface with EasyDMA 13 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136_S + I2C compatible Two-Wire Slave Interface with EasyDMA 13 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136_S + UART with EasyDMA 15 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM137_NS + Serial Peripheral Interface Master with EasyDMA 18 + 0x4F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137_NS + SPI Slave 16 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137_NS + I2C compatible Two-Wire Master Interface with EasyDMA 14 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 14 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137_NS + UART with EasyDMA 16 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_SPIM137_S + Serial Peripheral Interface Master with EasyDMA 19 + 0x5F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137_S + SPI Slave 17 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137_S + I2C compatible Two-Wire Master Interface with EasyDMA 15 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137_S + I2C compatible Two-Wire Slave Interface with EasyDMA 15 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137_S + UART with EasyDMA 17 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + \ No newline at end of file diff --git a/mdk/nrf9230_enga_application_peripherals.h b/mdk/nrf9230_enga_application_peripherals.h new file mode 100644 index 000000000..f3bfa1a78 --- /dev/null +++ b/mdk/nrf9230_enga_application_peripherals.h @@ -0,0 +1,1480 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_APPLICATION_PERIPHERALS_H +#define NRF9230_ENGA_APPLICATION_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +/*Extended UICR.*/ +#define UICREXTENDED_PRESENT 1 +#define UICREXTENDED_COUNT 1 + +/*CACHEDATA*/ +#define ICACHEDATA_PRESENT 1 +#define ICACHEDATA_COUNT 1 + +#define ICACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ +#define ICACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ +#define ICACHEDATA_NUMDATAUNIT 4 /*!< Number of data units : 4 */ +#define ICACHEDATA_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ + +/*CACHEINFO*/ +#define ICACHEINFO_PRESENT 1 +#define ICACHEINFO_COUNT 1 + +#define ICACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ +#define ICACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ +#define ICACHEINFO_NUMDATAUNIT 4 /*!< Number of data units : 4 */ +#define ICACHEINFO_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ +#define ICACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ +#define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ + +/*User information configuration registers*/ +#define UICR_PRESENT 1 +#define UICR_COUNT 1 + +/*Board information configuration registers*/ +#define BICR_PRESENT 1 +#define BICR_COUNT 1 + +#define BICR_P0_INTERNAL 1 /*!< (unspecified) */ +#define BICR_P0_POWER 0 /*!< (unspecified) */ +#define BICR_P1_POWER 1 /*!< (unspecified) */ +#define BICR_P2_POWER 1 /*!< (unspecified) */ +#define BICR_P3_POWER 0 /*!< (unspecified) */ +#define BICR_P4_POWER 0 /*!< (unspecified) */ +#define BICR_P5_POWER 0 /*!< (unspecified) */ +#define BICR_P6_POWER 1 /*!< (unspecified) */ +#define BICR_P7_POWER 0 /*!< (unspecified) */ +#define BICR_P8_POWER 1 /*!< (unspecified) */ +#define BICR_P9_POWER 1 /*!< (unspecified) */ +#define BICR_P10_POWER 1 /*!< (unspecified) */ +#define BICR_P11_POWER 1 /*!< (unspecified) */ +#define BICR_P12_POWER 1 /*!< (unspecified) */ +#define BICR_P13_POWER 1 /*!< (unspecified) */ +#define BICR_P14_POWER 0 /*!< (unspecified) */ +#define BICR_P15_POWER 0 /*!< (unspecified) */ +#define BICR_P0_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P1_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P2_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P3_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P4_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P5_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P6_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P7_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P8_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P9_POWER_3V 1 /*!< (unspecified) */ +#define BICR_P10_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P11_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P12_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P13_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P14_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P15_POWER_3V 0 /*!< (unspecified) */ +#define BICR_P0_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P1_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P2_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P3_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P4_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P5_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P6_DRIVECTRL 1 /*!< (unspecified) */ +#define BICR_P7_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P8_DRIVECTRL 1 /*!< (unspecified) */ +#define BICR_P9_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P10_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P11_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P12_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P13_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P14_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P15_DRIVECTRL 0 /*!< (unspecified) */ +#define BICR_P0_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P1_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P2_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P3_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P4_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P5_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P6_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P7_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P8_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P9_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P10_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P11_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P12_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P13_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P14_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_P15_BIASCTRL 0 /*!< (unspecified) */ +#define BICR_PMICLDO 1 /*!< (unspecified) */ + +/*CACHEDATA*/ +#define DCACHEDATA_PRESENT 1 +#define DCACHEDATA_COUNT 1 + +#define DCACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ +#define DCACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ +#define DCACHEDATA_NUMDATAUNIT 8 /*!< Number of data units : 8 */ +#define DCACHEDATA_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ + +/*CACHEINFO*/ +#define DCACHEINFO_PRESENT 1 +#define DCACHEINFO_COUNT 1 + +#define DCACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ +#define DCACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ +#define DCACHEINFO_NUMDATAUNIT 8 /*!< Number of data units : 8 */ +#define DCACHEINFO_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ +#define DCACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ +#define DCACHEINFO_DU_EXTENSION 1 /*!< (unspecified) */ + +/*Embedded Trace Macrocell*/ +#define ETM_PRESENT 1 +#define ETM_COUNT 1 + +/*Cross-Trigger Interface control*/ +#define CTI_PRESENT 1 +#define CTI_COUNT 3 + +/*CM33 SubSystem*/ +#define CM33SS_PRESENT 1 +#define CM33SS_COUNT 1 + +#define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ + +/*Cache*/ +#define CACHE_PRESENT 1 +#define CACHE_COUNT 2 + +#define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ +#define ICACHE_FLUSH 0 /*!< (unspecified) */ +#define ICACHE_CLEAN 0 /*!< (unspecified) */ +#define ICACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ +#define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ +#define ICACHE_SECUREINVALIDATE 0 /*!< (unspecified) */ + +#define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ +#define DCACHE_FLUSH 1 /*!< (unspecified) */ +#define DCACHE_CLEAN 1 /*!< (unspecified) */ +#define DCACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ +#define DCACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ +#define DCACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ +#define DCACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ +#define DCACHE_SECUREINVALIDATE 0 /*!< (unspecified) */ + +/*System protection unit*/ +#define SPU_PRESENT 1 +#define SPU_COUNT 2 + +#define SPU000_BELLS 0 /*!< (unspecified) */ +#define SPU000_IPCT 0 /*!< (unspecified) */ +#define SPU000_DPPI 0 /*!< (unspecified) */ +#define SPU000_GPIOTE 0 /*!< (unspecified) */ +#define SPU000_GRTC 0 /*!< (unspecified) */ +#define SPU000_GPIO 0 /*!< (unspecified) */ +#define SPU000_CRACEN 0 /*!< (unspecified) */ +#define SPU000_MRAMC 0 /*!< (unspecified) */ +#define SPU000_COEXC 0 /*!< (unspecified) */ +#define SPU000_ANTSWC 0 /*!< (unspecified) */ +#define SPU000_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU010_BELLS 0 /*!< (unspecified) */ +#define SPU010_IPCT 1 /*!< (unspecified) */ +#define SPU010_DPPI 0 /*!< (unspecified) */ +#define SPU010_GPIOTE 0 /*!< (unspecified) */ +#define SPU010_GRTC 0 /*!< (unspecified) */ +#define SPU010_GPIO 0 /*!< (unspecified) */ +#define SPU010_CRACEN 0 /*!< (unspecified) */ +#define SPU010_MRAMC 0 /*!< (unspecified) */ +#define SPU010_COEXC 0 /*!< (unspecified) */ +#define SPU010_ANTSWC 0 /*!< (unspecified) */ +#define SPU010_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +/*Memory Privilege Controller*/ +#define MPC_PRESENT 1 +#define MPC_COUNT 1 + +#define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ +#define MPC_RTCHOKE 1 /*!< (unspecified) */ +#define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ + +/*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ + +#define MVDMA_PRESENT 1 +#define MVDMA_COUNT 3 + +#define MVDMA_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA_DPPI_DISCONNECTED 0 /*!< (unspecified) */ +#define MVDMA_INSTANCE_IN_WRAPPER 0 /*!< (unspecified) */ + +#define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +#define MVDMA121_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA121_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA121_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +/*RAM Controller*/ +#define RAMC_PRESENT 1 +#define RAMC_COUNT 3 + +#define RAMC_ECC 0 /*!< (unspecified) */ +#define RAMC_SEC 1 /*!< (unspecified) */ + +#define RAMC122_ECC 0 /*!< (unspecified) */ +#define RAMC122_SEC 0 /*!< (unspecified) */ + +#define RAMC123_ECC 0 /*!< (unspecified) */ +#define RAMC123_SEC 0 /*!< (unspecified) */ + +/*HSFLL*/ +#define HSFLL_PRESENT 1 +#define HSFLL_COUNT 1 + +#define HSFLL_DITHER_32B 1 /*!< (unspecified) */ +#define HSFLL_CLOCKCTRL_MULT_RESET 6 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ + +/*LRCCONF*/ +#define LRCCONF_PRESENT 1 +#define LRCCONF_COUNT 2 + +#define LRCCONF000_POWERON 0 /*!< (unspecified) */ +#define LRCCONF000_RETAIN 0 /*!< (unspecified) */ +#define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ +#define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ +#define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF000_PDACT 0 /*!< (unspecified) */ +#define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF000_OTHERON 0 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ +#define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ +#define LRCCONF000_POWERON_MAIN_RESET 0 /*!< (unspecified) */ +#define LRCCONF000_POWERON_ACT_RESET 0 /*!< (unspecified) */ +#define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ +#define LRCCONF000_RETAIN_ACT_RESET 1 /*!< (unspecified) */ + +#define LRCCONF010_POWERON 1 /*!< (unspecified) */ +#define LRCCONF010_RETAIN 1 /*!< (unspecified) */ +#define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ +#define LRCCONF010_LRCREQHFXO 1 /*!< (unspecified) */ +#define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NCLK_MAX 0 /*!< (unspecified) */ +#define LRCCONF010_NCLK_SIZE 1 /*!< (unspecified) */ +#define LRCCONF010_CLKCTRL 1 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_MAX 0 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_SIZE 1 /*!< (unspecified) */ +#define LRCCONF010_PDACT 1 /*!< (unspecified) */ +#define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF010_OTHERON 0 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ +#define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ +#define LRCCONF010_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ +#define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ +#define LRCCONF010_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ +#define LRCCONF010_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ + +/*Memory configuration*/ +#define MEMCONF_PRESENT 1 +#define MEMCONF_COUNT 1 + +#define MEMCONF_RETTRIM 1 /*!< (unspecified) */ +#define MEMCONF_REPAIR 0 /*!< (unspecified) */ +#define MEMCONF_POWER 1 /*!< (unspecified) */ + +/*Watchdog Timer*/ +#define WDT_PRESENT 1 +#define WDT_COUNT 4 + +#define WDT010_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT010_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT011_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT011_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT131_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT132_HAS_INTEN 0 /*!< (unspecified) */ + +/*ABB peripheral*/ +#define ABB_PRESENT 1 +#define ABB_COUNT 1 + +/*RESETINFO*/ +#define RESETINFO_PRESENT 1 +#define RESETINFO_COUNT 1 + +#define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ +#define RESETINFO_CROSSDOMAINRESET 1 /*!< (unspecified) */ + +/*IPCT APB registers*/ +#define IPCT_PRESENT 1 +#define IPCT_COUNT 3 + +#define IPCT_IRQ_COUNT 2 + +#define IPCT120_IRQ_COUNT 1 + +#define IPCT130_IRQ_COUNT 1 + +/*Software interrupt*/ +#define SWI_PRESENT 1 +#define SWI_COUNT 8 + +/*BELLBOARD APB registers*/ +#define BELLBOARD_PRESENT 1 +#define BELLBOARD_COUNT 1 + +#define BELLBOARD_IRQ_COUNT 4 + +/*Factory Information Configuration Registers*/ +#define FICR_PRESENT 1 +#define FICR_COUNT 1 + +/*USBHSCORE*/ +#define USBHSCORE_PRESENT 1 +#define USBHSCORE_COUNT 1 + +/*I3CCORE*/ +#define I3CCORE_PRESENT 1 +#define I3CCORE_COUNT 2 + +/*DMU*/ +#define DMU_PRESENT 1 +#define DMU_COUNT 2 + +/*MCAN*/ +#define MCAN_PRESENT 1 +#define MCAN_COUNT 2 + +/*System Trace Macrocell data buffer*/ +#define STMDATA_PRESENT 1 +#define STMDATA_COUNT 1 + +/*TDDCONF*/ +#define TDDCONF_PRESENT 1 +#define TDDCONF_COUNT 1 + +#define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 0 /*!< (unspecified) */ +#define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 1 /*!< (unspecified) */ + +/*System Trace Macrocell*/ +#define STM_PRESENT 1 +#define STM_COUNT 1 + +/*Trace Port Interface Unit*/ +#define TPIU_PRESENT 1 +#define TPIU_COUNT 1 + +/*ATB Replicator module*/ +#define ATBREPLICATOR_PRESENT 1 +#define ATBREPLICATOR_COUNT 4 + +/*ATB funnel module*/ +#define ATBFUNNEL_PRESENT 1 +#define ATBFUNNEL_COUNT 4 + +/*GPIO Tasks and Events*/ +#define GPIOTE_PRESENT 1 +#define GPIOTE_COUNT 2 + +#define GPIOTE130_IRQ_COUNT 2 +#define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +#define GPIOTE131_IRQ_COUNT 2 +#define GPIOTE131_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +/*Global Real-time counter*/ +#define GRTC_PRESENT 1 +#define GRTC_COUNT 1 + +#define GRTC_IRQ_COUNT 3 +#define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_PWMREGS 1 /*!< (unspecified) */ +#define GRTC_CLKOUTREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ + +/*Trace buffer monitor*/ +#define TBM_PRESENT 1 +#define TBM_COUNT 1 + +/*USBHS*/ +#define USBHS_PRESENT 1 +#define USBHS_COUNT 1 + +/*External Memory Interface*/ +#define EXMIF_PRESENT 1 +#define EXMIF_COUNT 1 + +/*BELLBOARD public registers*/ +#define BELLBOARDPUBLIC_PRESENT 1 +#define BELLBOARDPUBLIC_COUNT 1 + +/*VPR peripheral registers*/ +#define VPRPUBLIC_PRESENT 1 +#define VPRPUBLIC_COUNT 1 + +#define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ + +/*MUTEX*/ +#define MUTEX_PRESENT 1 +#define MUTEX_COUNT 2 + +/*I3C*/ +#define I3C_PRESENT 1 +#define I3C_COUNT 2 + +/*VPR peripheral registers*/ +#define VPR_PRESENT 1 +#define VPR_COUNT 2 + +#define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ +#define VPR121_RAM_SZ 15 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ +#define VPR121_RETAINED 0 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ +#define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ + +#define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ +#define VPR130_RAM_SZ 15 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ +#define VPR130_RETAINED 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ + +/*Controller Area Network*/ +#define CAN_PRESENT 1 +#define CAN_COUNT 2 + +/*Distributed programmable peripheral interconnect controller*/ +#define DPPIC_PRESENT 1 +#define DPPIC_COUNT 8 + +#define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +/*Timer/Counter*/ +#define TIMER_PRESENT 1 +#define TIMER_COUNT 10 + +#define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ + +/*Pulse width modulation unit*/ +#define PWM_PRESENT 1 +#define PWM_COUNT 5 + +#define PWM120_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM120_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM130_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM130_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM131_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM131_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM132_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM132_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM133_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM133_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*SPI Slave*/ +#define SPIS_PRESENT 1 +#define SPIS_COUNT 9 + +#define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Serial Peripheral Interface Master with EasyDMA*/ +#define SPIM_PRESENT 1 +#define SPIM_COUNT 10 + +#define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +/*UART with EasyDMA*/ +#define UARTE_PRESENT 1 +#define UARTE_COUNT 9 + +#define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ +#define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ +#define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Real-time counter*/ +#define RTC_PRESENT 1 +#define RTC_COUNT 2 + +#define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ + +#define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ + +/*Event generator unit*/ +#define EGU_PRESENT 1 +#define EGU_COUNT 1 + +#define EGU130_PEND 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ + +/*GPIO Port*/ +#define GPIO_PRESENT 1 +#define GPIO_COUNT 10 + +#define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MAX 12 /*!< (unspecified) */ +#define P0_PIN_NUM_SIZE 13 /*!< (unspecified) */ +#define P0_FEATURE_PINS_PRESENT 0x00001FFFUL /*!< (unspecified) */ +#define P0_DRIVECTRL 0 /*!< (unspecified) */ +#define P0_RETAIN 1 /*!< (unspecified) */ +#define P0_PWRCTRL 0 /*!< (unspecified) */ +#define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P0_BIASCTRL 0 /*!< (unspecified) */ + +#define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P1_DRIVECTRL 0 /*!< (unspecified) */ +#define P1_RETAIN 1 /*!< (unspecified) */ +#define P1_PWRCTRL 0 /*!< (unspecified) */ +#define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P1_BIASCTRL 0 /*!< (unspecified) */ + +#define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P2_DRIVECTRL 0 /*!< (unspecified) */ +#define P2_RETAIN 1 /*!< (unspecified) */ +#define P2_PWRCTRL 0 /*!< (unspecified) */ +#define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P2_BIASCTRL 0 /*!< (unspecified) */ + +#define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ +#define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ +#define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ +#define P6_DRIVECTRL 1 /*!< (unspecified) */ +#define P6_RETAIN 1 /*!< (unspecified) */ +#define P6_PWRCTRL 0 /*!< (unspecified) */ +#define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P6_BIASCTRL 0 /*!< (unspecified) */ + +#define P8_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MAX 4 /*!< (unspecified) */ +#define P8_PIN_NUM_SIZE 5 /*!< (unspecified) */ +#define P8_FEATURE_PINS_PRESENT 0x0000001FUL /*!< (unspecified) */ +#define P8_DRIVECTRL 1 /*!< (unspecified) */ +#define P8_RETAIN 1 /*!< (unspecified) */ +#define P8_PWRCTRL 0 /*!< (unspecified) */ +#define P8_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P8_BIASCTRL 0 /*!< (unspecified) */ + +#define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ +#define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ +#define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ +#define P9_DRIVECTRL 0 /*!< (unspecified) */ +#define P9_RETAIN 1 /*!< (unspecified) */ +#define P9_PWRCTRL 1 /*!< (unspecified) */ +#define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P9_BIASCTRL 0 /*!< (unspecified) */ + +#define P10_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P10_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P10_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P10_DRIVECTRL 0 /*!< (unspecified) */ +#define P10_RETAIN 1 /*!< (unspecified) */ +#define P10_PWRCTRL 0 /*!< (unspecified) */ +#define P10_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P10_BIASCTRL 0 /*!< (unspecified) */ + +#define P11_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P11_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P11_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P11_DRIVECTRL 0 /*!< (unspecified) */ +#define P11_RETAIN 1 /*!< (unspecified) */ +#define P11_PWRCTRL 0 /*!< (unspecified) */ +#define P11_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P11_BIASCTRL 0 /*!< (unspecified) */ + +#define P12_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MAX 2 /*!< (unspecified) */ +#define P12_PIN_NUM_SIZE 3 /*!< (unspecified) */ +#define P12_FEATURE_PINS_PRESENT 0x00000007UL /*!< (unspecified) */ +#define P12_DRIVECTRL 0 /*!< (unspecified) */ +#define P12_RETAIN 1 /*!< (unspecified) */ +#define P12_PWRCTRL 0 /*!< (unspecified) */ +#define P12_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P12_BIASCTRL 0 /*!< (unspecified) */ + +#define P13_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MAX 3 /*!< (unspecified) */ +#define P13_PIN_NUM_SIZE 4 /*!< (unspecified) */ +#define P13_FEATURE_PINS_PRESENT 0x0000000FUL /*!< (unspecified) */ +#define P13_DRIVECTRL 0 /*!< (unspecified) */ +#define P13_RETAIN 1 /*!< (unspecified) */ +#define P13_PWRCTRL 0 /*!< (unspecified) */ +#define P13_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P13_BIASCTRL 0 /*!< (unspecified) */ + +/*Analog to Digital Converter*/ +#define SAADC_PRESENT 1 +#define SAADC_COUNT 1 + +#define SAADC_PSEL_V2 1 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Comparator*/ +#define COMP_PRESENT 1 +#define COMP_COUNT 1 + +/*Low-power comparator*/ +#define LPCOMP_PRESENT 1 +#define LPCOMP_COUNT 1 + +/*Temperature Sensor*/ +#define TEMP_PRESENT 1 +#define TEMP_COUNT 1 + +/*Inter-IC Sound*/ +#define I2S_PRESENT 1 +#define I2S_COUNT 2 + +/*Pulse Density Modulation (Digital Microphone) Interface*/ +#define PDM_PRESENT 1 +#define PDM_COUNT 1 + +#define PDM_SAMPLE16 1 /*!< (unspecified) */ +#define PDM_SAMPLE48 0 /*!< (unspecified) */ +#define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Quadrature Decoder*/ +#define QDEC_PRESENT 1 +#define QDEC_COUNT 2 + +/*I2C compatible Two-Wire Master Interface with EasyDMA*/ +#define TWIM_PRESENT 1 +#define TWIM_COUNT 8 + +#define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*I2C compatible Two-Wire Slave Interface with EasyDMA*/ +#define TWIS_PRESENT 1 +#define TWIS_COUNT 8 + +#define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/* ============================================= SPU010 Split Security Features ============================================== */ +/** + * @brief Indexes in SPU010.FEATURES controlling access permissions of features with split security + */ +typedef enum { + NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_0 = 0, /*!< Index of access permissions for channel 0 of IPCT */ + NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_1 = 1, /*!< Index of access permissions for channel 1 of IPCT */ + NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_2 = 2, /*!< Index of access permissions for channel 2 of IPCT */ + NRF_APPLICATION_SPU010_FEATURES_IPCT_CH_3 = 3, /*!< Index of access permissions for channel 3 of IPCT */ + NRF_APPLICATION_SPU010_FEATURES_IPCT_INTERRUPT_0 = 24, /*!< Index of access permissions for interrupt 0 of IPCT */ + NRF_APPLICATION_SPU010_FEATURES_IPCT_INTERRUPT_1 = 25, /*!< Index of access permissions for interrupt 1 of IPCT */ +} NRF_APPLICATION_SPU010_FEATURES_ENUM_t; + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_APPLICATION_PERIPHERALS_H */ + diff --git a/mdk/nrf9230_enga_application_vectors.h b/mdk/nrf9230_enga_application_vectors.h new file mode 100644 index 000000000..32a9d013a --- /dev/null +++ b/mdk/nrf9230_enga_application_vectors.h @@ -0,0 +1,694 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SecureFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void SPU000_IRQHandler (void); + __HANDLER("Default_Handler") void MPC_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA_IRQHandler (void); + __HANDLER("Default_Handler") void SPU010_IRQHandler (void); + __HANDLER("Default_Handler") void WDT010_IRQHandler (void); + __HANDLER("Default_Handler") void WDT011_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT_0_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT_1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + __HANDLER("Default_Handler") void SWI6_IRQHandler (void); + __HANDLER("Default_Handler") void SWI7_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_0_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_1_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_2_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_3_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_0_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_2_IRQHandler (void); + __HANDLER("Default_Handler") void TBM_IRQHandler (void); + __HANDLER("Default_Handler") void USBHS_IRQHandler (void); + __HANDLER("Default_Handler") void EXMIF_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT120_0_IRQHandler (void); + __HANDLER("Default_Handler") void I3C120_IRQHandler (void); + __HANDLER("Default_Handler") void VPR121_IRQHandler (void); + __HANDLER("Default_Handler") void CAN120_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA120_IRQHandler (void); + __HANDLER("Default_Handler") void CAN121_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA121_IRQHandler (void); + __HANDLER("Default_Handler") void I3C121_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER120_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER121_IRQHandler (void); + __HANDLER("Default_Handler") void PWM120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIS120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM120_UARTE120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM121_IRQHandler (void); + __HANDLER("Default_Handler") void VPR130_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT130_0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC130_IRQHandler (void); + __HANDLER("Default_Handler") void RTC131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT132_IRQHandler (void); + __HANDLER("Default_Handler") void EGU130_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void I2S130_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC130_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC131_IRQHandler (void); + __HANDLER("Default_Handler") void I2S131_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER130_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER131_IRQHandler (void); + __HANDLER("Default_Handler") void PWM130_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER132_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER133_IRQHandler (void); + __HANDLER("Default_Handler") void PWM131_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL2_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER134_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER135_IRQHandler (void); + __HANDLER("Default_Handler") void PWM132_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL4_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER136_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER137_IRQHandler (void); + __HANDLER("Default_Handler") void PWM133_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL6_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL7_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + SPU000_IRQHandler, + MPC_IRQHandler, + 0, + MVDMA_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SPU010_IRQHandler, + 0, + 0, + 0, + WDT010_IRQHandler, + WDT011_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT_0_IRQHandler, + IPCT_1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + SWI6_IRQHandler, + SWI7_IRQHandler, + BELLBOARD_0_IRQHandler, + BELLBOARD_1_IRQHandler, + BELLBOARD_2_IRQHandler, + BELLBOARD_3_IRQHandler, + 0, + 0, + 0, + 0, + GPIOTE130_0_IRQHandler, + GPIOTE130_1_IRQHandler, + GPIOTE131_0_IRQHandler, + GPIOTE131_1_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TBM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + USBHS_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXMIF_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT120_0_IRQHandler, + 0, + I3C120_IRQHandler, + VPR121_IRQHandler, + 0, + 0, + 0, + CAN120_IRQHandler, + MVDMA120_IRQHandler, + 0, + CAN121_IRQHandler, + MVDMA121_IRQHandler, + 0, + I3C121_IRQHandler, + 0, + 0, + 0, + TIMER120_IRQHandler, + TIMER121_IRQHandler, + PWM120_IRQHandler, + SPIS120_IRQHandler, + SPIM120_UARTE120_IRQHandler, + SPIM121_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + VPR130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT130_0_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + RTC130_IRQHandler, + RTC131_IRQHandler, + 0, + WDT131_IRQHandler, + WDT132_IRQHandler, + EGU130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SAADC_IRQHandler, + COMP_LPCOMP_IRQHandler, + TEMP_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + I2S130_IRQHandler, + PDM_IRQHandler, + QDEC130_IRQHandler, + QDEC131_IRQHandler, + 0, + I2S131_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER130_IRQHandler, + TIMER131_IRQHandler, + PWM130_IRQHandler, + SERIAL0_IRQHandler, + SERIAL1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER132_IRQHandler, + TIMER133_IRQHandler, + PWM131_IRQHandler, + SERIAL2_IRQHandler, + SERIAL3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER134_IRQHandler, + TIMER135_IRQHandler, + PWM132_IRQHandler, + SERIAL4_IRQHandler, + SERIAL5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER136_IRQHandler, + TIMER137_IRQHandler, + PWM133_IRQHandler, + SERIAL6_IRQHandler, + SERIAL7_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf9230_enga_flpr.h b/mdk/nrf9230_enga_flpr.h new file mode 100644 index 000000000..b02799354 --- /dev/null +++ b/mdk/nrf9230_enga_flpr.h @@ -0,0 +1,342 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_FLPR_H +#define NRF9230_ENGA_FLPR_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_FLPR /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ +/* ============================================== Processor Specific Interrupts ============================================== */ + VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ + VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ + VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ + VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ + VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ + VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ + VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ + VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ + VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ + VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ + VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ + VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ + VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ + VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ + VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ + VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ + VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ + VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ + VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ + VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ + VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ + VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ + VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ + VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ + VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ + VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ + VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ + VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ + VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ + VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ + VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ + VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ + VPRTIM_IRQn = 32, /*!< 32 VPRTIM */ + GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ + GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ + GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ + GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ + GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ + GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ + GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ + TBM_IRQn = 127, /*!< 127 TBM */ + USBHS_IRQn = 134, /*!< 134 USBHS */ + EXMIF_IRQn = 149, /*!< 149 EXMIF */ + IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ + I3C120_IRQn = 211, /*!< 211 I3C120 */ + VPR121_IRQn = 212, /*!< 212 VPR121 */ + CAN120_IRQn = 216, /*!< 216 CAN120 */ + MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ + CAN121_IRQn = 219, /*!< 219 CAN121 */ + MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ + I3C121_IRQn = 222, /*!< 222 I3C121 */ + TIMER120_IRQn = 226, /*!< 226 TIMER120 */ + TIMER121_IRQn = 227, /*!< 227 TIMER121 */ + PWM120_IRQn = 228, /*!< 228 PWM120 */ + SPIS120_IRQn = 229, /*!< 229 SPIS120 */ + SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ + SPIM121_IRQn = 231, /*!< 231 SPIM121 */ + VPR130_IRQn = 264, /*!< 264 VPR130 */ + IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ + RTC130_IRQn = 296, /*!< 296 RTC130 */ + RTC131_IRQn = 297, /*!< 297 RTC131 */ + WDT131_IRQn = 299, /*!< 299 WDT131 */ + WDT132_IRQn = 300, /*!< 300 WDT132 */ + EGU130_IRQn = 301, /*!< 301 EGU130 */ + SAADC_IRQn = 386, /*!< 386 SAADC */ + COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ + TEMP_IRQn = 388, /*!< 388 TEMP */ + I2S130_IRQn = 402, /*!< 402 I2S130 */ + PDM_IRQn = 403, /*!< 403 PDM */ + QDEC130_IRQn = 404, /*!< 404 QDEC130 */ + QDEC131_IRQn = 405, /*!< 405 QDEC131 */ + I2S131_IRQn = 407, /*!< 407 I2S131 */ + TIMER130_IRQn = 418, /*!< 418 TIMER130 */ + TIMER131_IRQn = 419, /*!< 419 TIMER131 */ + PWM130_IRQn = 420, /*!< 420 PWM130 */ + SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ + SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ + TIMER132_IRQn = 434, /*!< 434 TIMER132 */ + TIMER133_IRQn = 435, /*!< 435 TIMER133 */ + PWM131_IRQn = 436, /*!< 436 PWM131 */ + SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ + SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ + TIMER134_IRQn = 450, /*!< 450 TIMER134 */ + TIMER135_IRQn = 451, /*!< 451 TIMER135 */ + PWM132_IRQn = 452, /*!< 452 PWM132 */ + SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ + SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ + TIMER136_IRQn = 466, /*!< 466 TIMER136 */ + TIMER137_IRQn = 467, /*!< 467 TIMER137 */ + PWM133_IRQn = 468, /*!< 468 PWM133 */ + SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ + SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define SPIM120_IRQn SPIM120_UARTE120_IRQn +#define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler +#define UARTE120_IRQn SPIM120_UARTE120_IRQn +#define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SPIM130_IRQn SERIAL0_IRQn +#define SPIM130_IRQHandler SERIAL0_IRQHandler +#define SPIS130_IRQn SERIAL0_IRQn +#define SPIS130_IRQHandler SERIAL0_IRQHandler +#define TWIM130_IRQn SERIAL0_IRQn +#define TWIM130_IRQHandler SERIAL0_IRQHandler +#define TWIS130_IRQn SERIAL0_IRQn +#define TWIS130_IRQHandler SERIAL0_IRQHandler +#define UARTE130_IRQn SERIAL0_IRQn +#define UARTE130_IRQHandler SERIAL0_IRQHandler +#define SPIM131_IRQn SERIAL1_IRQn +#define SPIM131_IRQHandler SERIAL1_IRQHandler +#define SPIS131_IRQn SERIAL1_IRQn +#define SPIS131_IRQHandler SERIAL1_IRQHandler +#define TWIM131_IRQn SERIAL1_IRQn +#define TWIM131_IRQHandler SERIAL1_IRQHandler +#define TWIS131_IRQn SERIAL1_IRQn +#define TWIS131_IRQHandler SERIAL1_IRQHandler +#define UARTE131_IRQn SERIAL1_IRQn +#define UARTE131_IRQHandler SERIAL1_IRQHandler +#define SPIM132_IRQn SERIAL2_IRQn +#define SPIM132_IRQHandler SERIAL2_IRQHandler +#define SPIS132_IRQn SERIAL2_IRQn +#define SPIS132_IRQHandler SERIAL2_IRQHandler +#define TWIM132_IRQn SERIAL2_IRQn +#define TWIM132_IRQHandler SERIAL2_IRQHandler +#define TWIS132_IRQn SERIAL2_IRQn +#define TWIS132_IRQHandler SERIAL2_IRQHandler +#define UARTE132_IRQn SERIAL2_IRQn +#define UARTE132_IRQHandler SERIAL2_IRQHandler +#define SPIM133_IRQn SERIAL3_IRQn +#define SPIM133_IRQHandler SERIAL3_IRQHandler +#define SPIS133_IRQn SERIAL3_IRQn +#define SPIS133_IRQHandler SERIAL3_IRQHandler +#define TWIM133_IRQn SERIAL3_IRQn +#define TWIM133_IRQHandler SERIAL3_IRQHandler +#define TWIS133_IRQn SERIAL3_IRQn +#define TWIS133_IRQHandler SERIAL3_IRQHandler +#define UARTE133_IRQn SERIAL3_IRQn +#define UARTE133_IRQHandler SERIAL3_IRQHandler +#define SPIM134_IRQn SERIAL4_IRQn +#define SPIM134_IRQHandler SERIAL4_IRQHandler +#define SPIS134_IRQn SERIAL4_IRQn +#define SPIS134_IRQHandler SERIAL4_IRQHandler +#define TWIM134_IRQn SERIAL4_IRQn +#define TWIM134_IRQHandler SERIAL4_IRQHandler +#define TWIS134_IRQn SERIAL4_IRQn +#define TWIS134_IRQHandler SERIAL4_IRQHandler +#define UARTE134_IRQn SERIAL4_IRQn +#define UARTE134_IRQHandler SERIAL4_IRQHandler +#define SPIM135_IRQn SERIAL5_IRQn +#define SPIM135_IRQHandler SERIAL5_IRQHandler +#define SPIS135_IRQn SERIAL5_IRQn +#define SPIS135_IRQHandler SERIAL5_IRQHandler +#define TWIM135_IRQn SERIAL5_IRQn +#define TWIM135_IRQHandler SERIAL5_IRQHandler +#define TWIS135_IRQn SERIAL5_IRQn +#define TWIS135_IRQHandler SERIAL5_IRQHandler +#define UARTE135_IRQn SERIAL5_IRQn +#define UARTE135_IRQHandler SERIAL5_IRQHandler +#define SPIM136_IRQn SERIAL6_IRQn +#define SPIM136_IRQHandler SERIAL6_IRQHandler +#define SPIS136_IRQn SERIAL6_IRQn +#define SPIS136_IRQHandler SERIAL6_IRQHandler +#define TWIM136_IRQn SERIAL6_IRQn +#define TWIM136_IRQHandler SERIAL6_IRQHandler +#define TWIS136_IRQn SERIAL6_IRQn +#define TWIS136_IRQHandler SERIAL6_IRQHandler +#define UARTE136_IRQn SERIAL6_IRQn +#define UARTE136_IRQHandler SERIAL6_IRQHandler +#define SPIM137_IRQn SERIAL7_IRQn +#define SPIM137_IRQHandler SERIAL7_IRQHandler +#define SPIS137_IRQn SERIAL7_IRQn +#define SPIS137_IRQHandler SERIAL7_IRQHandler +#define TWIM137_IRQn SERIAL7_IRQn +#define TWIM137_IRQHandler SERIAL7_IRQHandler +#define TWIS137_IRQn SERIAL7_IRQn +#define TWIS137_IRQHandler SERIAL7_IRQHandler +#define UARTE137_IRQn SERIAL7_IRQn +#define UARTE137_IRQHandler SERIAL7_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ +#define __VPR_REV 1.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ + +#define NRF_VPR NRF_VPR121 /*!< VPR instance name */ +#include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ +#include "system_nrf.h" /*!< nrf9230_enga_flpr System Library */ + +#endif /*!< NRF_FLPR */ + + +#ifdef NRF_FLPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST + #define NRF_PROCESSOR NRF_PROCESSOR_FLPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_FLPR */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_FLPR_VPRCLIC_BASE 0x5F8D5000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_FLPR_VPRCLIC ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_BASE) + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #define NRF_VPRCLIC NRF_FLPR_VPRCLIC +#endif /*!< NRF_FLPR */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_FLPR_H */ + diff --git a/mdk/nrf9230_enga_flpr.svd b/mdk/nrf9230_enga_flpr.svd new file mode 100644 index 000000000..f52a510d6 --- /dev/null +++ b/mdk/nrf9230_enga_flpr.svd @@ -0,0 +1,138985 @@ + + + + Nordic Semiconductor + Nordic + nrf9230_enga_flpr + nRF92 + 1 + nRF9230_enga reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + system_nrf9230_enga_flpr + + 480 + + + + GLOBAL_FICR + Factory Information Configuration Registers + 0x0FFFE000 + + + + 0 + 0xC00 + registers + + FICR + 0x20 + + + BLE + Unspecified + FICR_BLE + read-write + 0x00C + + ADDRTYPE + Device address type. + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + TYPE + Device address type. + 0 + 0 + + + Public + Public address. + 0x0 + + + Random + Random address. + 0x1 + + + + + + + 0x2 + 0x4 + ADDR[%s] + Description collection: 48 bit device address. + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + ADDR + Device address [n]. + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root. + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + ER + Encryption root word [n]. + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root. + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + IR + Identity root word [n]. + 0 + 31 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x050 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + HWID + Identification number for the HW + 0 + 15 + + + + + PART + Part code + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + PART + Part code + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x008 + read-only + 0xFFFFFFFF + 0x20 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + PACKAGE + Package option + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x010 + read-only + 0xFFFFFFFF + 0x20 + + + RAM + RAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + MRAM + MRAM variant + 0x014 + read-only + 0xFFFFFFFF + 0x20 + + + MRAM + MRAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x018 + read-only + 0x00001000 + 0x20 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODESIZE + Code memory size + 0x01C + read-only + 0x00000100 + 0x20 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + DEVICETYPE + Device type + 0x020 + read-only + 0x00000000 + 0x20 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x00000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x080 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + PARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0xFF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0xFF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + PMICVERSION + PMIC version + 0x00C + read-only + 0x00000000 + 0x20 + + + PMICVERSION + PMIC version, incremental code + 0 + 31 + + + + + 0x4 + 0x1 + TESTSITE[%s] + Description collection: Test site, in ascii + 0x010 + read-only + 0x00 + uint8_t + 0x8 + + + LOT + Lot number + test index in hex format (number digits 0-9). + 0x014 + read-only + 0x00000000 + 0x20 + + + LOTID + Lot number in hex format + 0 + 23 + + + TESTID + Test ID in hex format + 24 + 31 + + + + + 0x4 + 0x1 + TESTPROGRAMID[%s] + Description collection: Test program id, in ascii + 0x018 + read-only + 0x00 + uint8_t + 0x8 + + + OSATPARTNO + OSAT part number + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + OSATPARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWBUILDVERSION[%s] + Description collection: OSAT production build version + 0x020 + read-only + 0xFF + uint8_t + 0x8 + + + OVERRIDE + Unspecified + FICR_SIPINFO_OVERRIDE + read-write + 0x024 + + LFOSC + Unspecified + FICR_SIPINFO_OVERRIDE_LFOSC + read-write + 0x000 + + CONFIG + LF oscillator configuration. Note. This configuration overrides corresponding LF oscillator configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SRC + LF oscillator source. + 0 + 3 + + + Unconfigured + LF oscillator source is unconfigured. Default will be used. + 0xF + + + LFXO + Use LFXO as source for the LF oscillator. + 0x0 + + + LFRC + Use LFRC as source for the LF oscillator. + 0x1 + + + LFLPRC + Use LFLPRC as source for the LF oscillator. + 0x2 + + + Synth + Use LF Synth as source for the LF oscillator. + 0x3 + + + + + + + LFXOCONFIG + LFXO configuration. Note. This configuration overrides corresponding LFXO configuration in BICR when set. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + ACCURACY + LFXO crystal or external signal accuracy. + 0 + 3 + + + Unconfigured + The accuracy is unconfigured. + 0xF + + + 500ppm + LFXO crystal or external signal has an accuracy of 500 ppm. + 0x0 + + + 250ppm + LFXO crystal or external signal has an accuracy of 250 ppm. + 0x1 + + + 150ppm + LFXO crystal or external signal has an accuracy of 150 ppm. + 0x2 + + + 100ppm + LFXO crystal or external signal has an accuracy of 100 ppm. + 0x3 + + + 75ppm + LFXO crystal or external signal has an accuracy of 75 ppm. + 0x4 + + + 50ppm + LFXO crystal or external signal has an accuracy of 50 ppm. + 0x5 + + + 30ppm + LFXO crystal or external signal has an accuracy of 30 ppm. + 0x6 + + + 20ppm + LFXO crystal or external signal has an accuracy of 20 ppm. + 0x7 + + + + + MODE + LFXO mode. LFXO will not start unless MODE is configured. + 4 + 6 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Pierce + LFXO Pierce mode. + 0x0 + + + PIXO + LFXO PIXO mode. + 0x1 + + + ExtSine + LFXO in external sine wave mode. + 0x2 + + + ExtSquare + LFXO in external square wave mode. + 0x3 + + + + + LOADCAP + Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. + 8 + 15 + + + Unconfigured + The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is configured. + 0xFF + + + External + Do not use the built-in load capacitors, only external capacitors will be used. + 0x00 + + + + + TIME + LFXO startup time in ms. + 16 + 27 + + + Unconfigured + Startup time has not been configured. + 0xFFF + + + + + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. Note. This configuration overrides corresponding LFXO calibration in BICR when set. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0 + 31 + + + Calibrate + Calibrate the LFXO at startup. + 0xFFFFFFFF + + + + + + + LFRCAUTOCALCONFIG + LFRC autocalibration configuration. Note. This configuration overrides corresponding LFRC autocalibration configuration in BICR when set. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TEMPINTERVAL + Temperature measurement interval in 0.25 s steps. + 0 + 6 + + + TEMPDELTA + Temperature delta that should trigger a calibration in 0.25 degrees steps. + 8 + 13 + + + INTERVALMAXNO + Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature changes. + 16 + 20 + + + ENABLE + LFRC.AUTOCALCONFIG register enable. + 31 + 31 + + + Enabled + LFRC.AUTOCALCONFIG register has been configured and can be used. + 0x0 + + + Disabled + LFRC.AUTOCALCONFIG register has not been configured and cannot be used. + 0x1 + + + + + + + + HFXO64M + Unspecified + FICR_SIPINFO_OVERRIDE_HFXO64M + read-write + 0x010 + + CONFIG + HFXO64M configuration. Note. This configuration overrides corresponding XO configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MODE + HFXO64M mode. + 0 + 2 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Normal + Normal operating mode. + 0x0 + + + TCXO + TCXO/bypass mode + 0x1 + + + Crystal2 + Reserved value + 0x2 + + + Crystal3 + Reserved value + 0x3 + + + Crystal4 + Reserved value + 0x4 + + + Crystal5 + Reserved value + 0x5 + + + Crystal6 + Reserved value + 0x6 + + + + + + + + + + TRIM + Unspecified + FICR_TRIM + read-write + 0x100 + + GLOBAL + Unspecified + FICR_TRIM_GLOBAL + read-write + 0x244 + + SAADC + Unspecified + FICR_TRIM_GLOBAL_SAADC + read-write + 0x0 + + CALVREF + Trim value for GLOBAL.SAADC.CALVREF + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x3 + 0x4 + CALGAIN[%s] + Description collection: Trim value for GLOBAL.SAADC.CALGAIN + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALOFFSET + Trim value for GLOBAL.SAADC.CALOFFSET + 0x10 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF + 0x14 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALIREF + Trim value for GLOBAL.SAADC.CALIREF + 0x2C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALVREFTC + Trim value for GLOBAL.SAADC.CALVREFTC + 0x30 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + CANPLL + Unspecified + FICR_TRIM_GLOBAL_CANPLL + read-write + 0x3C + + TRIM + Unspecified + FICR_TRIM_GLOBAL_CANPLL_TRIM + read-write + 0x0 + + CTUNE + Trim value for GLOBAL.CANPLL.TRIM.CTUNE + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + COMP + Unspecified + FICR_TRIM_GLOBAL_COMP + read-write + 0x4C + + REFTRIM + Trim value for GLOBAL.COMP.REFTRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + APPLICATION + Unspecified + FICR_TRIM_APPLICATION + read-write + 0x298 + + HSFLL + Unspecified + FICR_TRIM_APPLICATION_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_APPLICATION_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for APPLICATION.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_APPLICATION_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + RADIOCORE + Unspecified + FICR_TRIM_RADIOCORE + read-write + 0x2DC + + HSFLL + Unspecified + FICR_TRIM_RADIOCORE_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_RADIOCORE_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for RADIOCORE.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + + + + GLOBAL_USBHSCORE0 + USBHSCORE + 0x2F700000 + USBHSCORE + + + + 0 + 0x24000 + registers + + USBHSCORE + 0x20 + + + GOTGCTL + Control and Status Register + 0x000 + read-write + 0x000D0000 + 0x20 + + + VBVALIDOVEN + Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) + 2 + 2 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller + 0x0 + + + ENABLED + The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal + 0x1 + + + + + VBVALIDOVVAL + Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) + 3 + 3 + + + SET0 + vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + 0x0 + + + SET1 + vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + 0x1 + + + + + AVALIDOVEN + Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) + 4 + 4 + + + DISABLED + Derive AValid from PHY + 0x0 + + + ENABLED + Derive Avalid from GOTGCTL.AvalidOvVal + 0x1 + + + + + AVALIDOVVAL + Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) + 5 + 5 + + + VALUE0 + Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + 0x0 + + + VALUE1 + Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + 0x1 + + + + + BVALIDOVEN + Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) + 6 + 6 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + ENABLED + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal + 0x1 + + + + + BVALIDOVVAL + Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) + 7 + 7 + + + VALUE0 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x0 + + + VALUE1 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x1 + + + + + DBNCEFLTRBYPASS + Mode: Host and Device. Debounce Filter Bypass + 15 + 15 + + + DISABLED + Debounce Filter Bypass is disabled. + 0x0 + + + ENABLED + Debounce Filter Bypass is enabled. + 0x1 + + + + + CONIDSTS + Mode: Host and Device. Connector ID Status (ConIDSts) + 16 + 16 + read-only + + + MODEA + The core is in A-Device mode. + 0x0 + + + MODEB + The core is in B-Device mode. + 0x1 + + + + + DBNCTIME + Mode: Host only. Long/Short Debounce Time (DbncTime) + 17 + 17 + read-only + + + LONG + Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + 0x0 + + + SHORT + Short debounce time, used for soft connections (2.5 micro-sec) + 0x1 + + + + + ASESVLD + Mode: Host only. A-Session Valid (ASesVld) + 18 + 18 + read-only + + + NOTVALID + A-session is not valid. + 0x0 + + + VALID + A-session is valid. + 0x1 + + + + + BSESVLD + Mode: Device only. B-Session Valid (BSesVld) + 19 + 19 + read-only + + + NOTVALID + B-session is not valid. + 0x0 + + + VALID + B-session is valid. + 0x1 + + + + + OTGVER + OTG Version (OTGVer) + 20 + 20 + + + VER13 + Supports OTG Version 1.3 + 0x0 + + + VER20 + Supports OTG Version 2.0 + 0x1 + + + + + CURMOD + Current Mode of Operation (CurMod) + 21 + 21 + read-only + + + DEVICEMODE + Current mode is device mode. + 0x0 + + + HOSTMODE + Current mode is host mode. + 0x1 + + + + + MULTVALIDBC + Mode: Host and Device. Multi Valued ID pin (MultValIdBC) + 22 + 26 + read-only + + + RID_C + B-Device connected to ACA. VBUS is on. + 0x01 + + + RID_B + B-Device connected to ACA. VBUS is off. + 0x02 + + + RID_A + A-Device connected to ACA + 0x04 + + + RID_GND + A-Device not connected to ACA + 0x08 + + + RID_FLOAT + B-Device not connected to ACA + 0x10 + + + + + CHIRPEN + Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used + 27 + 27 + + + CHIRP_DISABLE + The controller does not assert chirp_on before sending an actual Chirp 'K' signal on USB. + 0x0 + + + CHIRP_ENABLE + The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB. + 0x1 + + + + + + + GOTGINT + Interrupt Register + 0x004 + read-write + 0x00000000 + 0x20 + + + SESENDDET + Mode: Host and Device. Session End Detected (SesEndDet) + 2 + 2 + + + INACTIVE + Session is Active + 0x0 + + + ACTIVE + SessionEnd utmiotg_bvalid signal is deasserted + 0x1 + + + + + SESREQSUCSTSCHNG + Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) + 8 + 8 + + + INACTIVE + No Change in Session Request Status + 0x0 + + + ACTIVE + Session Request Status has changed + 0x1 + + + + + HSTNEGSUCSTSCHNG + Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) + 9 + 9 + + + INACTIVE + No Change + 0x0 + + + ACTIVE + Host Negotiation Status Change + 0x1 + + + + + HSTNEGDET + Mode:Host and Device. Host Negotiation Detected (HstNegDet) + 17 + 17 + + + INACTIVE + No Active HNP Request + 0x0 + + + ACTIVE + Active HNP request detected + 0x1 + + + + + ADEVTOUTCHG + Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) + 18 + 18 + + + INACTIVE + No A-Device Timeout + 0x0 + + + ACTIVE + A-Device Timeout + 0x1 + + + + + DBNCEDONE + Mode: Host only. Debounce Done (DbnceDone) + 19 + 19 + + + INACTIVE + After Connect waiting for Debounce to complete + 0x0 + + + ACTIVE + Debounce completed + 0x1 + + + + + MULTVALIPCHNG + This bit when set indicates that there is a change in the value of at least one ACA pin value. + 20 + 20 + + + NO_ACA_PIN_CHANGE + Indicates there is no change in ACA pin value + 0x0 + + + ACA_PIN_CHANGE + Indicates there is a change in ACA pin value + 0x1 + + + + + + + GAHBCFG + AHB Configuration Register + 0x008 + read-write + 0x00000000 + 0x20 + + + GLBLINTRMSK + Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) + 0 + 0 + + + MASK + Mask the interrupt assertion to the application + 0x0 + + + NOMASK + Unmask the interrupt assertion to the application. + 0x1 + + + + + HBSTLEN + Mode: Host and device. Burst Length/Type (HBstLen) + 1 + 4 + + + WORD1ORSINGLE + 1 word or single + 0x0 + + + WORD4ORINCR + 4 words or INCR + 0x1 + + + WORD8 + 8 words + 0x2 + + + WORD16ORINCR4 + 16 words or INCR4 + 0x3 + + + WORD32 + 32 words + 0x4 + + + WORD64ORINCR8 + 64 words or INCR8 + 0x5 + + + WORD128 + 128 words + 0x6 + + + WORD256ORINCR16 + 256 words or INCR16 + 0x7 + + + WORDX + Others reserved + 0x8 + + + + + DMAEN + Mode: Host and device. DMA Enable (DMAEn) + 5 + 5 + + + SLAVEMODE + Core operates in Slave mode + 0x0 + + + DMAMODE + Core operates in a DMA mode + 0x1 + + + + + NPTXFEMPLVL + Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + 7 + 7 + + + HALFEMPTY + DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or that the IN Endpoint TxFIFO is half empty. + 0x0 + + + EMPTY + GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty or that the IN Endpoint TxFIFO is completely empty. + 0x1 + + + + + REMMEMSUPP + Mode: Host and Device. Remote Memory Support (RemMemSupp) + 21 + 21 + + + DISABLED + Remote Memory Support Feature disabled + 0x0 + + + ENABLED + Remote Memory Support Feature enabled + 0x1 + + + + + NOTIALLDMAWRIT + Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) + 22 + 22 + + + LASTTRANS + Unspecified + 0x0 + + + ALLTRANS + The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint + 0x1 + + + + + AHBSINGLE + Mode: Host and Device. AHB Single Support (AHBSingle) + 23 + 23 + + + INCRBURST + The remaining data in the transfer is sent using INCR burst size + 0x0 + + + SINGLEBURST + The remaining data in the transfer is sent using Single burst size + 0x1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + read-write + 0x10001400 + 0x20 + + + TOUTCAL + Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) + 0 + 2 + + + ZERO + Add 0 PHY clocks + 0x0 + + + ONE + Add 1 PHY clocks + 0x1 + + + TWO + Add 2 PHY clocks + 0x2 + + + THREE + Add 3 PHY clocks + 0x3 + + + FOUR + Add 4 PHY clocks + 0x4 + + + FIVE + Add 5 PHY clocks + 0x5 + + + SIX + Add 6 PHY clocks + 0x6 + + + SEVEN + Add 7 PHY clocks + 0x7 + + + + + PHYIF + Mode: Host and Device. PHY Interface (PHYIf) + 3 + 3 + + + BITS8 + PHY 8bit Mode + 0x0 + + + BITS16 + PHY 16bit Mode + 0x1 + + + + + ULPIUTMISEL + Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) + 4 + 4 + read-only + + + UTMI + UTMI+ Interface + 0x0 + + + ULPI + ULPI Interface + 0x1 + + + + + FSINTF + Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) + 5 + 5 + read-only + + + FS6PIN + 6-pin unidirectional full-speed serial interface + 0x0 + + + FS3PIN + 3-pin bidirectional full-speed serial interface + 0x1 + + + + + PHYSEL + PHYSel + 6 + 6 + read-only + + + USB20 + USB 2.0 high-speed UTMI+ or ULPI PHY is selected + 0x0 + + + USB11 + USB 1.1 full-speed serial transceiver is selected + 0x1 + + + + + USBTRDTIM + Mode: Device only. USB Turnaround Time (USBTrdTim) + 10 + 13 + + + TURNTIME16BIT + MAC interface is 16-bit UTMI+. + 0x5 + + + TURNTIME8BIT + MAC interface is 8-bit UTMI+. + 0x9 + + + + + PHYLPWRCLKSEL + PHY Low-Power Clock Select (PhyLPwrClkSel) + 15 + 15 + + + INTPLLCLK + 480-MHz Internal PLL clock + 0x0 + + + EXTCLK + 48-MHz External Clock + 0x1 + + + + + TERMSELDLPULSE + Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) + 22 + 22 + + + TXVALID + Data line pulsing using utmi_txvalid + 0x0 + + + TERMSEL + Data line pulsing using utmi_termsel + 0x1 + + + + + ICUSBCAP + Mode: Host and Device. IC_USB-Capable (IC_USBCap) + 26 + 26 + read-only + + + NOTSELECTED + IC_USB PHY Interface is not selected + 0x0 + + + SELECTED + IC_USB PHY Interface is selected + 0x1 + + + + + TXENDDELAY + Mode: Device only. Tx End Delay (TxEndDelay) + 28 + 28 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Tx End delay + 0x1 + + + + + FORCEHSTMODE + Mode: Host and device. Force Host Mode (ForceHstMode) + 29 + 29 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Host Mode + 0x1 + + + + + FORCEDEVMODE + Mode:Host and device. Force Device Mode (ForceDevMode) + 30 + 30 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Device Mode + 0x1 + + + + + CORRUPTTXPKT + Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) + 31 + 31 + write-only + + + Disabled + Normal Mode + 0x0 + + + Enabled + Debug Mode + 0x1 + + + + + + + GRSTCTL + Reset Register + 0x010 + read-write + 0x80000000 + 0x20 + + + CSFTRST + Mode: Host and Device. Core Soft Reset (CSftRst) + 0 + 0 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Resets hclk and phy_clock domains + 0x1 + + + + + PIUFSSFTRST + Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + 1 + 1 + + + RESET_INACTIVE + No Reset + 0x0 + + + RESET_ACTIVE + PIU FS Dedicated Controller Soft Reset + 0x1 + + + + + FRMCNTRRST + Mode: Host only. Host Frame Counter Reset (FrmCntrRst) + 2 + 2 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Host Frame Counter Reset + 0x1 + + + + + RXFFLSH + Mode: Host and Device. RxFIFO Flush (RxFFlsh) + 4 + 4 + + + INACTIVE + Does not flush the entire RxFIFO + 0x0 + + + ACTIVE + Flushes the entire RxFIFO + 0x1 + + + + + TXFFLSH + Mode: Host and Device. TxFIFO Flush (TxFFlsh) + 5 + 5 + + + INACTIVE + No Flush + 0x0 + + + ACTIVE + Selectively flushes a single or all transmit FIFOs + 0x1 + + + + + TXFNUM + Mode: Host and Device. TxFIFO Number (TxFNum) + 6 + 10 + + + TXF0 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in shared FIFO operation -TXFIFO 0 flush in device mode when in dedicated FIFO mode + 0x00 + + + TXF1 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in shared FIFO operation -TXFIFO 1 flush in device mode when in dedicated FIFO mode + 0x01 + + + TXF2 + -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush in device mode when in dedicated FIFO mode + 0x02 + + + TXF3 + -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush in device mode when in dedicated FIFO mode + 0x03 + + + TXF4 + -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush in device mode when in dedicated FIFO mode + 0x04 + + + TXF5 + -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush in device mode when in dedicated FIFO mode + 0x05 + + + TXF6 + -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush in device mode when in dedicated FIFO mode + 0x06 + + + TXF7 + -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush in device mode when in dedicated FIFO mode + 0x07 + + + TXF8 + -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush in device mode when in dedicated FIFO mode + 0x08 + + + TXF9 + -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush in device mode when in dedicated FIFO mode + 0x09 + + + TXF10 + -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flush in device mode when in dedicated FIFO mode + 0x0A + + + TXF11 + -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flush in device mode when in dedicated FIFO mode + 0x0B + + + TXF12 + -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flush in device mode when in dedicated FIFO mode + 0x0C + + + TXF13 + -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flush in device mode when in dedicated FIFO mode + 0x0D + + + TXF14 + -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flush in device mode when in dedicated FIFO mode + 0x0E + + + TXF15 + -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flush in device mode when in dedicated FIFO mode + 0x0F + + + TXF16 + Flush all the transmit FIFOs in device or host mode + 0x10 + + + + + CSFTRSTDONE + Mode: Host and Device. Core Soft Reset Done (CSftRstDone) + 29 + 29 + + + INACTIVE + No reset + 0x0 + + + ACTIVE + Core Soft Reset is done + 0x1 + + + + + DMAREQ + Mode: Host and Device. DMA Request Signal (DMAReq) + 30 + 30 + read-only + + + INACTIVE + No DMA request + 0x0 + + + ACTIVE + DMA request is in progress + 0x1 + + + + + AHBIDLE + Mode: Host and Device. AHB Master Idle (AHBIdle) + 31 + 31 + read-only + + + INACTIVE + Not Idle + 0x0 + + + ACTIVE + AHB Master Idle + 0x1 + + + + + + + GINTSTS + Interrupt Register + 0x014 + read-write + 0x00000020 + 0x20 + + + CURMOD + Mode: Host and Device. Current Mode of Operation (CurMod) + 0 + 0 + read-only + + + DEVICE + Device mode + 0x0 + + + HOST + Host mode + 0x1 + + + + + MODEMIS + Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) + 1 + 1 + + + INACTIVE + No Mode Mismatch Interrupt + 0x0 + + + ACTIVE + Mode Mismatch Interrupt + 0x1 + + + + + OTGINT + Mode: Host and Device. OTG Interrupt (OTGInt) + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + OTG Interrupt + 0x1 + + + + + SOF + Mode: Host and Device. Start of (micro)Frame (Sof) + 3 + 3 + + + INTACTIVE + No Start of Frame + 0x0 + + + ACTIVE + Start of Frame + 0x1 + + + + + RXFLVL + Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) + 4 + 4 + read-only + + + INACTIVE + Rx Fifo is empty + 0x0 + + + ACTIVE + Rx Fifo is not empty + 0x1 + + + + + NPTXFEMP + Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) + 5 + 5 + read-only + + + INACTIVE + Non-periodic TxFIFO is not empty + 0x0 + + + ACTIVE + Non-periodic TxFIFO is empty + 0x1 + + + + + GINNAKEFF + Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) + 6 + 6 + read-only + + + INACTIVE + Global Non-periodic IN NAK not active + 0x0 + + + ACTIVE + Set Global Non-periodic IN NAK bit + 0x1 + + + + + GOUTNAKEFF + Mode: Device only. Global OUT NAK Effective (GOUTNakEff) + 7 + 7 + read-only + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Global OUT NAK Effective + 0x1 + + + + + ERLYSUSP + Mode: Device only. Early Suspend (ErlySusp) + 10 + 10 + + + INACTIVE + No Idle state detected + 0x0 + + + ACTIVE + 3ms of Idle state detected + 0x1 + + + + + USBSUSP + Mode: Device only. USB Suspend (USBSusp) + 11 + 11 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + USB Suspend + 0x1 + + + + + USBRST + Mode: Device only. USB Reset (USBRst) + 12 + 12 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + USB Reset + 0x1 + + + + + ENUMDONE + Mode: Device only. Enumeration Done (EnumDone) + 13 + 13 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Enumeration Done + 0x1 + + + + + ISOOUTDROP + Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + 14 + 14 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Isochronous OUT Packet Dropped Interrupt + 0x1 + + + + + EOPF + Mode: Device only. End of Periodic Frame Interrupt (EOPF) + 15 + 15 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + End of Periodic Frame Interrupt + 0x1 + + + + + RSTRDONEINT + Mode: Device only. Restore Done Interrupt (RstrDoneInt) + 16 + 16 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Restore Done Interrupt + 0x1 + + + + + EPMIS + Mode: Device only. Endpoint Mismatch Interrupt (EPMis) + 17 + 17 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Endpoint Mismatch Interrupt + 0x1 + + + + + IEPINT + Mode: Device only. IN Endpoints Interrupt (IEPInt) + 18 + 18 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + IN Endpoints Interrupt + 0x1 + + + + + OEPINT + Mode: Device only. OUT Endpoints Interrupt (OEPInt) + 19 + 19 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + OUT Endpoints Interrupt + 0x1 + + + + + INCOMPISOIN + Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) + 20 + 20 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Isochronous IN Transfer + 0x1 + + + + + INCOMPLP + Incomplete Periodic Transfer (incomplP) + 21 + 21 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Periodic Transfer + 0x1 + + + + + FETSUSP + Mode: Device only. Data Fetch Suspended (FetSusp) + 22 + 22 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Data Fetch Suspended + 0x1 + + + + + RESETDET + Mode: Device only. Reset detected Interrupt (ResetDet) + 23 + 23 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Reset detected Interrupt + 0x1 + + + + + PRTINT + Mode: Host only. Host Port Interrupt (PrtInt) + 24 + 24 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Port Interrupt + 0x1 + + + + + HCHINT + Mode: Host only. Host Channels Interrupt (HChInt) + 25 + 25 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Channels Interrupt + 0x1 + + + + + LPMINT + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). + 27 + 27 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + LPM Transaction Received Interrupt + 0x1 + + + + + CONIDSTSCHNG + Mode: Host and Device. Connector ID Status Change (ConIDStsChng) + 28 + 28 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Connector ID Status Change + 0x1 + + + + + DISCONNINT + Mode: Host only. Disconnect Detected Interrupt (DisconnInt) + 29 + 29 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Disconnect Detected Interrupt + 0x1 + + + + + SESSREQINT + Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) + 30 + 30 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Session Request New Session Detected Interrupt + 0x1 + + + + + WKUPINT + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) + 31 + 31 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Resume or Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GINTMSK + Interrupt Mask Register + 0x018 + read-write + 0x00000000 + 0x20 + + + MODEMISMSK + Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) + 1 + 1 + + + MASK + Mode Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Mode Mismatch Interrupt Mask + 0x1 + + + + + OTGINTMSK + Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) + 2 + 2 + + + MASK + OTG Interrupt Mask + 0x0 + + + NOMASK + No OTG Interrupt Mask + 0x1 + + + + + SOFMSK + Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) + 3 + 3 + + + MASK + Start of Frame Mask + 0x0 + + + NOMASK + No Start of Frame Mask + 0x1 + + + + + RXFLVLMSK + Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) + 4 + 4 + + + MASK + Receive FIFO Non-Empty Mask + 0x0 + + + NOMASK + No Receive FIFO Non-Empty Mask + 0x1 + + + + + NPTXFEMPMSK + Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + 5 + 5 + + + MASK + Non-periodic TxFIFO Empty Mask + 0x0 + + + NOMASK + No Non-periodic TxFIFO Empty Mask + 0x1 + + + + + GINNAKEFFMSK + Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + 6 + 6 + + + MASK + Global Non-periodic IN NAK Effective Mask + 0x0 + + + NOMASK + No Global Non-periodic IN NAK Effective Mask + 0x1 + + + + + GOUTNAKEFFMSK + Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) + 7 + 7 + + + MASK + Global OUT NAK Effective Mask + 0x0 + + + NOMASK + No Global OUT NAK Effective Mask + 0x1 + + + + + ERLYSUSPMSK + Mode: Device only. Early Suspend Mask (ErlySuspMsk) + 10 + 10 + + + MASK + Early Suspend Mask + 0x0 + + + NOMASK + No Early Suspend Mask + 0x1 + + + + + USBSUSPMSK + Mode: Device only. USB Suspend Mask (USBSuspMsk) + 11 + 11 + + + MASK + USB Suspend Mask + 0x0 + + + NOMASK + No USB Suspend Mask + 0x1 + + + + + USBRSTMSK + Mode: Device only. USB Reset Mask (USBRstMsk) + 12 + 12 + + + MASK + USB Reset Mask + 0x0 + + + NOMASK + No USB Reset Mask + 0x1 + + + + + ENUMDONEMSK + Mode: Device only. Enumeration Done Mask (EnumDoneMsk) + 13 + 13 + + + MASK + Enumeration Done Mask + 0x0 + + + NOMASK + No Enumeration Done Mask + 0x1 + + + + + ISOOUTDROPMSK + Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + 14 + 14 + + + MASK + Isochronous OUT Packet Dropped Interrupt Mask + 0x0 + + + NOMASK + No Isochronous OUT Packet Dropped Interrupt Mask + 0x1 + + + + + EOPFMSK + Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) + 15 + 15 + + + MASK + End of Periodic Frame Interrupt Mask + 0x0 + + + NOMASK + No End of Periodic Frame Interrupt Mask + 0x1 + + + + + RSTRDONEINTMSK + Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) + 16 + 16 + + + MASK + Restore Done Interrupt Mask + 0x0 + + + NOMASK + No Restore Done Interrupt Mask + 0x1 + + + + + EPMISMSK + Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) + 17 + 17 + + + MASK + Endpoint Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Endpoint Mismatch Interrupt Mask + 0x1 + + + + + IEPINTMSK + Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) + 18 + 18 + + + MASK + IN Endpoints Interrupt Mask + 0x0 + + + NOMASK + No IN Endpoints Interrupt Mask + 0x1 + + + + + OEPINTMSK + Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) + 19 + 19 + + + MASK + OUT Endpoints Interrupt Mask + 0x0 + + + NOMASK + No OUT Endpoints Interrupt Mask + 0x1 + + + + + INCOMPLPMSK + Incomplete Periodic Transfer Mask (incomplPMsk) + 21 + 21 + + + MASK + Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT Transfer Mask + 0x0 + + + NOMASK + Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous OUT Transfer Mask + 0x1 + + + + + FETSUSPMSK + Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) + 22 + 22 + + + MASK + Data Fetch Suspended Mask + 0x0 + + + NOMASK + No Data Fetch Suspended Mask + 0x1 + + + + + RESETDETMSK + Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) + 23 + 23 + + + MASK + Reset detected Interrupt Mask + 0x0 + + + NOMASK + No Reset detected Interrupt Mask + 0x1 + + + + + PRTINTMSK + Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) + 24 + 24 + + + MASK + Host Port Interrupt Mask + 0x0 + + + NOMASK + No Host Port Interrupt Mask + 0x1 + + + + + HCHINTMSK + Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) + 25 + 25 + + + MASK + Host Channels Interrupt Mask + 0x0 + + + NOMASK + No Host Channels Interrupt Mask + 0x1 + + + + + LPMINTMSK + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) + 27 + 27 + + + MASK + LPM Transaction received interrupt Mask + 0x0 + + + NOMASK + No LPM Transaction received interrupt Mask + 0x1 + + + + + CONIDSTSCHNGMSK + Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) + 28 + 28 + + + MASK + Connector ID Status Change Mask + 0x0 + + + NOMASK + No Connector ID Status Change Mask + 0x1 + + + + + DISCONNINTMSK + Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) + 29 + 29 + + + MASK + Disconnect Detected Interrupt Mask + 0x0 + + + NOMASK + No Disconnect Detected Interrupt Mask + 0x1 + + + + + SESSREQINTMSK + Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + 30 + 30 + + + MASK + Session Request or New Session Detected Interrupt Mask + 0x0 + + + NOMASK + No Session Request or New Session Detected Interrupt Mask + 0x1 + + + + + WKUPINTMSK + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + 31 + 31 + + + MASK + Resume or Remote Wakeup Detected Interrupt Mask + 0x0 + + + NOMASK + Unmask Resume Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GRXSTSR + Receive Status Debug Read Register + 0x01C + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + DSETUPRX + SETUP data packet received in device mode + 0x6 + + + CHHALT + Channel halted in host mode (triggers an interrupt) + 0x7 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXSTSP + Receive Status Read/Pop Register + 0x020 + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + read-write + 0x00000224 + 0x20 + + + RXFDEP + Mode: Host and Device. RxFIFO Depth (RxFDep) + 0 + 9 + + + + + GNPTXFSIZ + Non-periodic Transmit FIFO Size Register + 0x028 + read-write + 0x02000224 + 0x20 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start Address (NPTxFStAddr) + 0 + 9 + + + NPTXFDEP + Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) + 16 + 25 + + + + + GNPTXSTS + Non-periodic Transmit FIFO/Queue Status Register + 0x02C + read-write + 0x00080200 + 0x20 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + 0 + 15 + read-only + + + NPTXQSPCAVAIL + Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + 16 + 23 + read-only + + + FULL + Non-periodic Transmit Request Queue is full + 0x00 + + + QUE1 + 1 location available + 0x01 + + + QUE2 + 2 locations available + 0x02 + + + QUE3 + 3 locations available + 0x03 + + + QUE4 + 4 locations available + 0x04 + + + QUE5 + 5 locations available + 0x05 + + + QUE6 + 6 locations available + 0x06 + + + QUE7 + 7 locations available + 0x07 + + + QUE8 + 8 locations available + 0x08 + + + + + NPTXQTOP + Top of the Non-periodic Transmit Request Queue (NPTxQTop) + 24 + 30 + read-only + + + INOUTTK + IN/OUT token + 0x00 + + + ZEROTX + Zero-length transmit packet (device IN/host OUT) + 0x01 + + + PINGCSPLIT + PING/CSPLIT token + 0x02 + + + CHNHALT + Channel halt command + 0x03 + + + + + + + GGPIO + General Purpose Input/Output Register + 0x038 + read-write + 0x00000000 + 0x20 + + + GPI + 0 + 15 + read-only + + + GPO + 16 + 31 + + + + + GUID + User ID Register + 0x03C + read-write + 0x00000000 + 0x20 + + + GUID + User ID (UserID) Application-programmable ID field. + 0 + 31 + + + + + GSNPSID + Synopsys ID Register + 0x040 + read-write + 0x4F54430A + 0x20 + + + SYNOPSYSID + Release number of the controller being used currently. + 0 + 31 + read-only + + + + + GHWCFG1 + User Hardware Configuration 1 Register + 0x044 + read-write + 0xAA555000 + 0x20 + + + EPDIR + This 32-bit field uses two bits per + 0 + 31 + read-only + + + + + GHWCFG2 + User Hardware Configuration 2 Register + 0x048 + read-write + 0x228BFC72 + 0x20 + + + OTGMODE + Mode of Operation (OtgMode) + 0 + 2 + read-only + + + HNPSRP + HNP- and SRP-Capable OTG (Host and Device) + 0x0 + + + SRPOTG + SRP-Capable OTG (Host and Device) + 0x1 + + + NHNPNSRP + Non-HNP and Non-SRP Capable OTG (Host and Device) + 0x2 + + + SRPCAPD + SRP-Capable Device + 0x3 + + + NONOTGD + Non-OTG Device + 0x4 + + + SRPCAPH + SRP-Capable Host + 0x5 + + + NONOTGH + Non-OTG Host + 0x6 + + + + + OTGARCH + Architecture (OtgArch) + 3 + 4 + read-only + + + SLAVEMODE + Slave Mode + 0x0 + + + EXTERNALDMA + External DMA Mode + 0x1 + + + INTERNALDMA + Internal DMA Mode + 0x2 + + + + + SINGPNT + Point-to-Point (SingPnt) + 5 + 5 + read-only + + + MULTIPOINT + Multi-point application (hub and split support) + 0x0 + + + SINGLEPOINT + Single-point application (no hub and split support) + 0x1 + + + + + HSPHYTYPE + High-Speed PHY Interface Type (HSPhyType) + 6 + 7 + read-only + + + NOHS + High-Speed interface not supported + 0x0 + + + UTMIPLUS + High Speed Interface UTMI+ is supported + 0x1 + + + ULPI + High Speed Interface ULPI is supported + 0x2 + + + UTMIPUSULPI + High Speed Interfaces UTMI+ and ULPI is supported + 0x3 + + + + + FSPHYTYPE + Full-Speed PHY Interface Type (FSPhyType) + 8 + 9 + read-only + + + NO_FS + Full-speed interface not supported + 0x0 + + + FS + Dedicated full-speed interface is supported + 0x1 + + + FSPLUSUTMI + FS pins shared with UTMI+ pins is supported + 0x2 + + + FSPLUSULPI + FS pins shared with ULPI pins is supported + 0x3 + + + + + NUMDEVEPS + Number of Device Endpoints (NumDevEps) + 10 + 13 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + NUMHSTCHNL + Number of Host Channels (NumHstChnl) + 14 + 17 + read-only + + + HOSTCH0 + Host Channel 1 + 0x0 + + + HOSTCH1 + Host Channel 2 + 0x1 + + + HOSTCH2 + Host Channel 3 + 0x2 + + + HOSTCH3 + Host Channel 4 + 0x3 + + + HOSTCH4 + Host Channel 5 + 0x4 + + + HOSTCH5 + Host Channel 6 + 0x5 + + + HOSTCH6 + Host Channel 7 + 0x6 + + + HOSTCH7 + Host Channel 8 + 0x7 + + + HOSTCH8 + Host Channel 9 + 0x8 + + + HOSTCH9 + Host Channel 10 + 0x9 + + + HOSTCH10 + Host Channel 11 + 0xA + + + HOSTCH11 + Host Channel 12 + 0xB + + + HOSTCH12 + Host Channel 13 + 0xC + + + HOSTCH13 + Host Channel 14 + 0xD + + + HOSTCH14 + Host Channel 15 + 0xE + + + HOSTCH15 + Host Channel 16 + 0xF + + + + + PERIOSUPPORT + Periodic OUT Channels Supported in Host Mode (PerioSupport) + 18 + 18 + read-only + + + DISABLED + Periodic OUT Channels is not supported in Host Mode + 0x0 + + + ENABLED + Periodic OUT Channels Supported in Host Mode Supported + 0x1 + + + + + DYNFIFOSIZING + Dynamic FIFO Sizing Enabled (DynFifoSizing) + 19 + 19 + read-only + + + DISABLED + Dynamic FIFO Sizing Disabled + 0x0 + + + ENABLED + Dynamic FIFO Sizing Enabled + 0x1 + + + + + MULTIPROCINTRPT + Multi Processor Interrupt Enabled (MultiProcIntrpt) + 20 + 20 + read-only + + + DISABLED + No Multi Processor Interrupt Enabled + 0x0 + + + ENABLED + Multi Processor Interrupt Enabled + 0x1 + + + + + NPTXQDEPTH + Non-periodic Request Queue Depth (NPTxQDepth) + 22 + 23 + read-only + + + TWO + Queue size 2 + 0x0 + + + FOUR + Queue size 4 + 0x1 + + + EIGHT + Queue size 8 + 0x2 + + + + + PTXQDEPTH + Host Mode Periodic Request Queue Depth (PTxQDepth) + 24 + 25 + read-only + + + QUE2 + Queue Depth 2 + 0x0 + + + QUE4 + Queue Depth 4 + 0x1 + + + QUE8 + Queue Depth 8 + 0x2 + + + QUE16 + Queue Depth 16 + 0x3 + + + + + TKNQDEPTH + Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + 26 + 30 + read-only + + + + + GHWCFG3 + User Hardware Configuration 3 Register + 0x04C + read-write + 0x0BEAC0E8 + 0x20 + + + XFERSIZEWIDTH + Width of Transfer Size Counters (XferSizeWidth) + 0 + 3 + read-only + + + WIDTH11 + Width of Transfer Size Counter 11 bits + 0x0 + + + WIDTH12 + Width of Transfer Size Counter 12 bits + 0x1 + + + WIDTH13 + Width of Transfer Size Counter 13 bits + 0x2 + + + WIDTH14 + Width of Transfer Size Counter 14 bits + 0x3 + + + WIDTH15 + Width of Transfer Size Counter 15 bits + 0x4 + + + WIDTH16 + Width of Transfer Size Counter 16 bits + 0x5 + + + WIDTH17 + Width of Transfer Size Counter 17 bits + 0x6 + + + WIDTH18 + Width of Transfer Size Counter 18 bits + 0x7 + + + WIDTH19 + Width of Transfer Size Counter 19 bits + 0x8 + + + + + PKTSIZEWIDTH + Width of Packet Size Counters (PktSizeWidth) + 4 + 6 + read-only + + + BITS4 + Width of Packet Size Counter 4 + 0x0 + + + BITS5 + Width of Packet Size Counter 5 + 0x1 + + + BITS6 + Width of Packet Size Counter 6 + 0x2 + + + BITS7 + Width of Packet Size Counter 7 + 0x3 + + + BITS8 + Width of Packet Size Counter 8 + 0x4 + + + BITS9 + Width of Packet Size Counter 9 + 0x5 + + + BITS10 + Width of Packet Size Counter 10 + 0x6 + + + + + OTGEN + OTG Function Enabled (OtgEn) + 7 + 7 + read-only + + + DISABLED + Not OTG Capable + 0x0 + + + ENABLED + OTG Capable + 0x1 + + + + + I2CINTSEL + I2C Selection (I2CIntSel) + 8 + 8 + read-only + + + DISABLED + I2C Interface is not available + 0x0 + + + ENABLED + I2C Interface is available + 0x1 + + + + + VNDCTLSUPT + Vendor Control Interface Support (VndctlSupt) + 9 + 9 + read-only + + + DISABLED + Vendor Control Interface is not available. + 0x0 + + + ENABLED + Vendor Control Interface is available. + 0x1 + + + + + OPTFEATURE + Optional Features Removed (OptFeature) + 10 + 10 + read-only + + + DISABLED + Optional features were not Removed + 0x0 + + + ENABLED + Optional Features have been Removed + 0x1 + + + + + RSTTYPE + Reset Style for Clocked always Blocks in RTL (RstType) + 11 + 11 + read-only + + + ASYNCRST + Asynchronous reset is used in the core + 0x0 + + + SYNCRST + Synchronous reset is used in the core + 0x1 + + + + + ADPSUPPORT + This bit indicates whether ADP logic is present within or external to the controller + 12 + 12 + read-only + + + DISABLED + ADP logic is not present along with the controller + 0x0 + + + ENABLED + ADP logic is present along with the controller + 0x1 + + + + + HSICMODE + HSIC mode specified for Mode of Operation + 13 + 13 + read-only + + + DISABLED + No HSIC capability + 0x0 + + + ENABLED + HSIC-capable with shared UTMI PHY interface + 0x1 + + + + + BCSUPPORT + This bit indicates the controller support for Battery Charger. + 14 + 14 + read-only + + + DISABLED + No Battery Charger Support + 0x0 + + + ENABLED + Battery Charger Support present + 0x1 + + + + + LPMMODE + LPM mode specified for Mode of Operation. + 15 + 15 + read-only + + + DISABLED + LPM disabled + 0x0 + + + ENABLED + LPM enabled + 0x1 + + + + + DFIFODEPTH + DFIFO Depth (DfifoDepth - EP_LOC_CNT) + 16 + 31 + read-only + + + + + GHWCFG4 + User Hardware Configuration 4 Register + 0x050 + read-write + 0x1E10AA60 + 0x20 + + + NUMDEVPERIOEPS + Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + 0 + 3 + read-only + + + Value0 + Number of Periodic IN EPs is 0 + 0x0 + + + Value1 + Number of Periodic IN EPs is 1 + 0x1 + + + Value2 + Number of Periodic IN EPs is 2 + 0x2 + + + Value3 + Number of Periodic IN EPs is 3 + 0x3 + + + Value4 + Number of Periodic IN EPs is 4 + 0x4 + + + Value5 + Number of Periodic IN EPs is 5 + 0x5 + + + Value6 + Number of Periodic IN EPs is 6 + 0x6 + + + Value7 + Number of Periodic IN EPs is 7 + 0x7 + + + Value8 + Number of Periodic IN EPs is 8 + 0x8 + + + Value9 + Number of Periodic IN EPs is 9 + 0x9 + + + Value10 + Number of Periodic IN EPs is 10 + 0xA + + + Value11 + Number of Periodic IN EPs is 11 + 0xB + + + Value12 + Number of Periodic IN EPs is 12 + 0xC + + + Value13 + Number of Periodic IN EPs is 13 + 0xD + + + Value14 + Number of Periodic IN EPs is 14 + 0xE + + + Value15 + Number of Periodic IN EPs is 15 + 0xF + + + + + PARTIALPWRDN + Enable Partial Power Down (PartialPwrDn) + 4 + 4 + read-only + + + DISABLED + Partial Power Down disabled + 0x0 + + + ENABLED + Partial Power Down enabled + 0x1 + + + + + AHBFREQ + Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + 5 + 5 + read-only + + + DISABLED + Minimum AHB Frequency More Than 60 MHz + 0x0 + + + ENABLED + Minimum AHB Frequency Less Than 60 MHz + 0x1 + + + + + HIBERNATION + Enable Hibernation (Hibernation) + 6 + 6 + read-only + + + DISABLED + Hibernation feature disabled + 0x0 + + + ENABLED + Hibernation feature enabled + 0x1 + + + + + EXTENDEDHIBERNATION + Enable Hibernation + 7 + 7 + read-only + + + DISABLED + Extended Hibernation feature not enabled + 0x0 + + + ENABLED + Extended Hibernation feature enabled + 0x1 + + + + + ENHANCEDLPMSUPT1 + Enhanced LPM Support1 (EnhancedLPMSupt1) + 9 + 9 + read-only + + + DISABLED + Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty. + 0x0 + + + ENABLED + Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty + 0x1 + + + + + SERVINTFLOW + Service Interval Flow + 10 + 10 + read-only + + + DISABLED + Service Interval Flow not supported + 0x0 + + + ENABLED + Service Interval Flow supported + 0x1 + + + + + IPGISOCSUPT + Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) + 11 + 11 + read-only + + + DISABLED + Interpacket Gap ISOC OUT Worst-case Support is Disabled + 0x0 + + + ENABLED + Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) + 0x1 + + + + + ACGSUPT + Active Clock Gating Support + 12 + 12 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Active Clock Gating Support + 0x1 + + + + + ENHANCEDLPMSUPT + Enhanced LPM Support (EnhancedLPMSupt) + 13 + 13 + read-only + + + ENABLED + Enhanced LPM Support is enabled + 0x1 + + + + + PHYDATAWIDTH + UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + 14 + 15 + read-only + + + WIDTH1 + 8 bits + 0x0 + + + WIDTH2 + 16 bits + 0x1 + + + WIDTH3 + 8/16 bits, software selectable + 0x2 + + + + + NUMCTLEPS + Number of Device Mode Control Endpoints in Addition to + 16 + 19 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + IDDGFLTR + IDDIG Filter Enable (IddgFltr) + 20 + 20 + read-only + + + DISABLED + Iddig Filter Disabled + 0x0 + + + ENABLED + Iddig Filter Enabled + 0x1 + + + + + VBUSVALIDFLTR + VBUS Valid Filter Enabled (VBusValidFltr) + 21 + 21 + read-only + + + DISABLED + Vbus Valid Filter Disabled + 0x0 + + + ENABLED + Vbus Valid Filter Enabled + 0x1 + + + + + AVALIDFLTR + a_valid Filter Enabled (AValidFltr) + 22 + 22 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + BVALIDFLTR + b_valid Filter Enabled (BValidFltr) + 23 + 23 + read-only + + + DISABLED + No Filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + SESSENDFLTR + session_end Filter Enabled (SessEndFltr) + 24 + 24 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + DEDFIFOMODE + Enable Dedicated Transmit FIFO for device IN Endpoints + 25 + 25 + read-only + + + DISABLED + Dedicated Transmit FIFO Operation not enabled + 0x0 + + + ENABLED + Dedicated Transmit FIFO Operation enabled + 0x1 + + + + + INEPS + Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + 26 + 29 + read-only + + + ENDPT1 + 1 IN Endpoint + 0x0 + + + ENDPT2 + 2 IN Endpoints + 0x1 + + + ENDPT3 + 3 IN Endpoints + 0x2 + + + ENDPT4 + 4 IN Endpoints + 0x3 + + + ENDPT5 + 5 IN Endpoints + 0x4 + + + ENDPT6 + 6 IN Endpoints + 0x5 + + + ENDPT7 + 7 IN Endpoints + 0x6 + + + ENDPT8 + 8 IN Endpoints + 0x7 + + + ENDPT9 + 9 IN Endpoints + 0x8 + + + ENDPT10 + 10 IN Endpoints + 0x9 + + + ENDPT11 + 11 IN Endpoints + 0xA + + + ENDPT12 + 12 IN Endpoints + 0xB + + + ENDPT13 + 13 IN Endpoints + 0xC + + + ENDPT14 + 14 IN Endpoints + 0xD + + + ENDPT15 + 15 IN Endpoints + 0xE + + + ENDPT16 + 16 IN Endpoints + 0xF + + + + + DESCDMAENABLED + Scatter/Gather DMA configuration + 30 + 30 + read-only + + + DISABLE + Non-Scatter/Gather DMA configuration + 0x0 + + + ENABLE + Scatter/Gather DMA configuration + 0x1 + + + + + DESCDMA + Scatter/Gather DMA configuration + 31 + 31 + read-only + + + CONFIG1 + Non Dynamic configuration + 0x0 + + + CONFIG2 + Dynamic configuration + 0x1 + + + + + + + GLPMCFG + LPM Config Register + 0x054 + read-write + 0x00000000 + 0x20 + + + LPMCAP + LPM-Capable (LPMCap) + 0 + 0 + + + DISABLED + LPM capability is not enabled + 0x0 + + + ENABLED + LPM capability is enabled + 0x1 + + + + + APPL1RES + Mode: Device only. LPM response programmed by application (AppL1Res) + 1 + 1 + + + NYET_RESP + The core responds with a NYET when an error is detected in either of the LPM token packets due to corruption + 0x0 + + + ACK_RESP + The core responds with an ACK only on a successful LPM transaction + 0x1 + + + + + HIRD + Host-Initiated Resume Duration (HIRD) + 2 + 5 + + + BREMOTEWAKE + RemoteWakeEnable (bRemoteWake) + 6 + 6 + + + DISABLED + Remote Wakeup is disabled + 0x0 + + + ENABLED + In Host or device mode, this field takes the value of remote wake up + 0x1 + + + + + ENBLSLPM + Enable utmi_sleep_n (EnblSlpM) + 7 + 7 + + + DISABLED + utmi_sleep_n assertion from the core is not transferred to the external PHY + 0x0 + + + ENABLED + utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted + 0x1 + + + + + HIRDTHRES + BESL/HIRD Threshold (HIRD_Thres) + 8 + 12 + + + COREL1RES + LPM Response (CoreL1Res) + 13 + 14 + read-only + + + LPMRESP1 + ERROR : No handshake response + 0x0 + + + LPMRESP2 + STALL response + 0x1 + + + LPMRESP3 + NYET response + 0x2 + + + LPMRESP4 + ACK response + 0x3 + + + + + SLPSTS + Port Sleep Status (SlpSts) + 15 + 15 + read-only + + + CORE_NOT_IN_L1 + In Host or Device mode, this bit indicates core is not in L1 + 0x0 + + + CORE_IN_L1 + In Host mode, this bit indicates the core transitions to Sleep state as a successful LPM transaction. In Device mode, the core enters the Sleep state when an ACK response is sent to an LPM transaction + 0x1 + + + + + L1RESUMEOK + Sleep State Resume OK (L1ResumeOK) + 16 + 16 + read-only + + + NOTOK + The application/core cannot start Resume from Sleep state + 0x0 + + + OK + The application/core can start Resume from Sleep state + 0x1 + + + + + LPMCHNLINDX + LPM Channel Index + 17 + 20 + + + CH0 + Channel 0 + 0x0 + + + CH1 + Channel 1 + 0x1 + + + CH2 + Channel 2 + 0x2 + + + CH3 + Channel 3 + 0x3 + + + CH4 + Channel 4 + 0x4 + + + CH5 + Channel 5 + 0x5 + + + CH6 + Channel 6 + 0x6 + + + CH7 + Channel 7 + 0x7 + + + CH8 + Channel 8 + 0x8 + + + CH9 + Channel 9 + 0x9 + + + CH10 + Channel 10 + 0xA + + + CH11 + Channel 11 + 0xB + + + CH12 + Channel 12 + 0xC + + + CH13 + Channel 13 + 0xD + + + CH14 + Channel 14 + 0xE + + + CH15 + Channel15 + 0xF + + + + + LPMRETRYCNT + LPM Retry Count (LPM_Retry_Cnt) + 21 + 23 + + + RETRY0 + Zero LPM retries + 0x0 + + + RETRY1 + One LPM retry + 0x1 + + + RETRY2 + Two LPM retries + 0x2 + + + RETRY3 + Three LPM retries + 0x3 + + + RETRY4 + Four LPM retries + 0x4 + + + RETRY5 + Five LPM retries + 0x5 + + + RETRY6 + Six LPM retries + 0x6 + + + RETRY7 + Seven LPM retries + 0x7 + + + + + SNDLPM + Send LPM Transaction (SndLPM) + 24 + 24 + + + DISABLED + In host-only mode: Received the response from the device for the LPM transaction + 0x0 + + + ENABLED + In host-only mode: Sending LPM transaction containing EXT and LPM tokens + 0x1 + + + + + LPMRETRYCNTSTS + LPM Retry Count Status (LPM_RetryCnt_Sts) + 25 + 27 + read-only + + + RETRY_REM0 + Zero LPM retries remaining + 0x0 + + + RETRY_REM1 + One LPM retry remaining + 0x1 + + + RETRY_REM2 + Two LPM retries remaining + 0x2 + + + RETRY_REM3 + Three LPM retries remaining + 0x3 + + + RETRY_REM4 + Four LPM retries remaining + 0x4 + + + RETRY_REM5 + Five LPM retries remaining + 0x5 + + + RETRY_REM6 + Six LPM retries remaining + 0x6 + + + RETRY_REM7 + Seven LPM retries remaining + 0x7 + + + + + LPMENBESL + LPM Enable BESL (LPM_EnBESL) + 28 + 28 + + + DISABLED + BESL is disabled + 0x0 + + + ENABLED + BESL is enabled as defined in LPM Errata + 0x1 + + + + + LPMRESTORESLPSTS + LPM Restore Sleep Status (LPM_RestoreSlpSts) + 29 + 29 + + + DISABLED + Puts the core in Shallow Sleep mode based on the BESL value from the Host + 0x0 + + + ENABLED + Puts the core in Deep Sleep mode based on the BESL value from the Host + 0x1 + + + + + + + GPWRDN + Global Power Down Register + 0x058 + read-write + 0x00000010 + 0x20 + + + PMUINTSEL + PMU Interrupt Select (PMUIntSel) + 0 + 0 + + + DISABLE + Internal DWC_otg_core interrupt is selected + 0x0 + + + ENABLE + External DWC_otg_pmu interrupt is selected + 0x1 + + + + + PMUACTV + PMU Active (PMUActv) + 1 + 1 + + + DISABLE + Disable PMU module + 0x0 + + + ENABLE + Enable PMU module + 0x1 + + + + + RESTORE + Restore + 2 + 2 + + + DISABLE + The controller in normal mode of operation + 0x0 + + + ENABLE + The controller in Restore mode + 0x1 + + + + + PWRDNCLMP + Power Down Clamp (PwrDnClmp) + 3 + 3 + + + DISABLE + Disable PMU power clamp + 0x0 + + + ENABLE + Enable PMU power clamp + 0x1 + + + + + PWRDNRSTN + Power Down ResetN (PwrDnRst_n) + 4 + 4 + + + DISABLE + Reset the controller + 0x0 + + + ENABLE + The controller is in normal operation + 0x1 + + + + + PWRDNSWTCH + Power Down Switch (PwrDnSwtch) + 5 + 5 + + + ON + The controller is in ON state + 0x0 + + + OFF + The controller is in OFF state + 0x1 + + + + + DISABLEVBUS + DisableVBUS + 6 + 6 + + + DISABLED + Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid + 0x0 + + + ENABLED + Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End + 0x1 + + + + + LNSTSCHNG + Line State Change (LnStsChng) + 7 + 7 + + + DISABLED + No LineState change on USB + 0x0 + + + ENABLED + LineState change on USB + 0x1 + + + + + LINESTAGECHANGEMSK + LineStageChangeMsk + 8 + 8 + + + NOMASK + No LineStateChange Interrupt Mask + 0x0 + + + MASK + Mask for LineStateChange Interrupt + 0x1 + + + + + RESETDETECTED + ResetDetected + 9 + 9 + + + DISABLED + Reset not detected + 0x0 + + + ENABLED + Reset detected + 0x1 + + + + + RESETDETMSK + ResetDetMsk + 10 + 10 + + + NOMASK + No ResetDetect Interrupt Mask + 0x0 + + + MASK + Mask for ResetDetect Interrupt + 0x1 + + + + + DISCONNECTDETECT + DisconnectDetect + 11 + 11 + + + DISABLED + Disconnect not detected + 0x0 + + + ENABLED + Disconnect detected + 0x1 + + + + + DISCONNECTDETECTMSK + DisconnectDetectMsk + 12 + 12 + + + NOMASK + No DisconnectDetect Interrupt Mask + 0x0 + + + MASK + Mask for DisconnectDetect Interrupt + 0x1 + + + + + CONNECTDET + ConnectDet + 13 + 13 + + + DISABLED + Connect not detected + 0x0 + + + ENABLED + Connect detected + 0x1 + + + + + CONNDETMSK + ConnDetMsk + 14 + 14 + + + NOMASK + No ConnectDet Interrupt Mask + 0x0 + + + MASK + Mask for ConnectDet Interrupt + 0x1 + + + + + SRPDETECT + SRPDetect + 15 + 15 + + + DISABLED + SRP not detected + 0x0 + + + ENABLED + SRP detected + 0x1 + + + + + SRPDETECTMSK + SRPDetectMsk + 16 + 16 + + + NOMASK + No SRPDetect Interrupt Mask + 0x0 + + + MASK + Mask for SRPDetect Interrupt + 0x1 + + + + + STSCHNGINT + Status Change Interrupt (StsChngInt) + 17 + 17 + + + DISABLED + No Status change + 0x0 + + + ENABLED + Status change detected + 0x1 + + + + + STSCHNGINTMSK + StsChngIntMsk + 18 + 18 + + + NOMASK + No Status Change Interrupt Mask + 0x0 + + + MASK + Mask for Status Change Interrupt + 0x1 + + + + + LINESTATE + LineState + 19 + 20 + read-only + + + LS1 + Linestate on USB: DM = 0, DP = 0 + 0x0 + + + LS2 + Linestate on USB: DM = 0, DP = 1 + 0x1 + + + LS3 + Linestate on USB: DM = 1, DP = 0 + 0x2 + + + LS4 + Linestate on USB: Not-defined + 0x3 + + + + + IDDIG + This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application. + 21 + 21 + read-only + + + DISABLED + Host Mode + 0x0 + + + ENABLED + Device Mode + 0x1 + + + + + BSESSVLD + B Session Valid (BSessVld) + 22 + 22 + read-only + + + NOTVALID + B_Valid is 0 + 0x0 + + + VALID + B_Valid is 1 + 0x1 + + + + + MULTVALIDBC + MultValIdBC + 24 + 28 + read-only + + + RID_0 + OTG device as B-device + 0x00 + + + RID_C + OTG device as B-device, can connect + 0x01 + + + RID_B + OTG device as B-device, cannot connect + 0x02 + + + RID_A + OTG device as A-device + 0x04 + + + RID_GND + ID_OTG pin is grounded + 0x08 + + + RID_A_RID_GND + OTG device as A-device, RID_A=1 and RID_GND=1 + 0x0C + + + RID_FLOAT + ID pull down when ID_OTG is floating + 0x10 + + + RID_C_RID_FLOAT + OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1 + 0x11 + + + RID_B_RID_FLOAT + OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1 + 0x12 + + + RID_1 + OTG device as A-device + 0x1F + + + + + + + GDFIFOCFG + Global DFIFO Configuration Register + 0x05C + read-write + 0x0BEA0C00 + 0x20 + + + GDFIFOCFG + GDFIFOCfg + 0 + 15 + + + EPINFOBASEADDR + This field provides the start address of the EP info controller. + 16 + 31 + + + + + GINTMSK2 + Interrupt Mask Register 2 + 0x068 + read-write + 0x00000000 + 0x20 + + + GINTMSK2 + 0 + 31 + + + + + GINTSTS2 + Interrupt Register 2 + 0x06C + read-write + 0x00000000 + 0x20 + + + GINTSTS2 + 0 + 31 + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + read-write + 0x04000424 + 0x20 + + + PTXFSTADDR + Host Periodic TxFIFO Start Address (PTxFStAddr) + 0 + 10 + + + PTXFSIZE + Host Periodic TxFIFO Depth (PTxFSize) + 16 + 26 + + + + + 0x7 + 0x4 + DIEPTXF[%s] + Description collection: Device IN Endpoint Transmit FIFO Size Register + 0x104 + read-write + 0x02000424 + 0x20 + + + INEPNTXFSTADDR + IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + 0 + 10 + + + INEPNTXFDEP + IN Endpoint TxFIFO Depth (INEPnTxFDep) + 16 + 25 + + + + + HCFG + Host Configuration Register + 0x400 + read-write + 0x00000200 + 0x20 + + + FSLSPCLKSEL + FS/LS PHY Clock Select (FSLSPclkSel) + 0 + 1 + + + CLK3060 + PHY clock is running at 30/60 MHz + 0x0 + + + CLK48 + PHY clock is running at 48 MHz + 0x1 + + + CLK6 + PHY clock is running at 6 MHz + 0x2 + + + + + FSLSSUPP + FS- and LS-Only Support (FSLSSupp) + 2 + 2 + + + HSFSLS + HS/FS/LS, based on the maximum speed supported by the connected device + 0x0 + + + FSLS + FS/LS-only, even if the connected device can support HS + 0x1 + + + + + ENA32KHZS + Enable 32 KHz Suspend mode (Ena32KHzS) + 7 + 7 + + + DISABLED + 32 KHz Suspend mode disabled + 0x0 + + + ENABLED + 32 KHz Suspend mode enabled + 0x1 + + + + + RESVALID + Resume Validation Period (ResValid) + 8 + 15 + + + MODECHTIMEN + Mode Change Ready Timer Enable (ModeChTimEn) + 31 + 31 + + + ENABLED + The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x0 + + + DISABLED + The Host core waits only for a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x1 + + + + + + + HFIR + Host Frame Interval Register + 0x404 + read-write + 0x0000EA60 + 0x20 + + + FRINT + Frame Interval (FrInt) + 0 + 15 + + + HFIRRLDCTRL + Reload Control (HFIRRldCtrl) + 16 + 16 + + + DISABLED + The HFIR cannot be reloaded dynamically + 0x0 + + + ENABLED + The HFIR can be dynamically reloaded during runtime + 0x1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + read-write + 0x00003FFF + 0x20 + + + FRNUM + Frame Number (FrNum) + 0 + 15 + read-only + + + INACTIVE + No SOF is transmitted + 0x0000 + + + ACTIVE + SOF is transmitted + 0x0001 + + + + + FRREM + Frame Time Remaining (FrRem) + 16 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + read-write + 0x00000000 + 0x20 + + + HAINT + 0 + 15 + read-only + + + INACTIVE + Not active + 0x0000 + + + ACTIVE + Host Channel Interrupt + 0x0001 + + + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + read-write + 0x00000000 + 0x20 + + + HAINTMSK + Channel Interrupt Mask (HAINTMsk) + 0 + 15 + + + UNMASK + Unmask Channel interrupt + 0x0000 + + + MASK + Mask Channel interrupt + 0x0001 + + + + + + + HPRT + Host Port Control and Status Register + 0x440 + read-write + 0x00000000 + 0x20 + + + PRTCONNSTS + Port Connect Status (PrtConnSts) + 0 + 0 + read-only + + + NOTATTACHED + No device is attached to the port + 0x0 + + + ATTACHED + A device is attached to the port + 0x1 + + + + + PRTCONNDET + Port Connect Detected (PrtConnDet) + 1 + 1 + + + INACTIVE + No device connection detected + 0x0 + + + ACTIVE + Device connection detected + 0x1 + + + + + PRTENA + Port Enable (PrtEna) + 2 + 2 + + + DISABLED + Port disabled + 0x0 + + + ENABLED + Port enabled + 0x1 + + + + + PRTENCHNG + Port Enable/Disable Change (PrtEnChng) + 3 + 3 + + + INACTIVE + Port Enable bit 2 has not changed + 0x0 + + + ACTIVE + Port Enable bit 2 changed + 0x1 + + + + + PRTOVRCURRACT + Port Overcurrent Active (PrtOvrCurrAct) + 4 + 4 + read-only + + + INACTIVE + No overcurrent condition + 0x0 + + + ACTIVE + Overcurrent condition + 0x1 + + + + + PRTOVRCURRCHNG + Port Overcurrent Change (PrtOvrCurrChng) + 5 + 5 + + + INACTIVE + Status of port overcurrent status is not changed + 0x0 + + + ACTIVE + Status of port overcurrent changed + 0x1 + + + + + PRTRES + Port Resume (PrtRes) + 6 + 6 + + + NORESUME + No resume driven + 0x0 + + + RESUME + Resume driven + 0x1 + + + + + PRTSUSP + Port Suspend (PrtSusp) + 7 + 7 + + + INACTIVE + Port not in Suspend mode + 0x0 + + + ACTIVE + Port in Suspend mode + 0x1 + + + + + PRTRST + Port Reset (PrtRst) + 8 + 8 + + + DISABLED + Port not in reset + 0x0 + + + ENABLED + Port in reset + 0x1 + + + + + PRTLNSTS + Port Line Status (PrtLnSts) + 10 + 11 + read-only + + + PLUSD + Logic level of D+ + 0x1 + + + MINUSD + Logic level of D- + 0x2 + + + + + PRTPWR + Port Power (PrtPwr) + 12 + 12 + + + OFF + Power off + 0x0 + + + ON + Power on + 0x1 + + + + + PRTTSTCTL + Port Test Control (PrtTstCtl) + 13 + 16 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFENB + Test_force_Enable + 0x5 + + + + + PRTSPD + Port Speed (PrtSpd) + 17 + 18 + read-only + + + HIGHSPD + High speed + 0x0 + + + FULLSPD + Full speed + 0x1 + + + LOWSPD + Low speed + 0x2 + + + + + + + 16 + 0x018 + HC[%s] + Unspecified + USBHSCORE_HC + read-write + 0x500 + + CHAR + Description cluster: Host Channel Characteristics Register + 0x000 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + EPNUM + Endpoint Number (EPNum) + 11 + 14 + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + EPDIR + Endpoint Direction (EPDir) + 15 + 15 + + + OUT + OUT Direction + 0x0 + + + IN + IN Direction + 0x1 + + + + + LSPDDEV + Low-Speed Device (LSpdDev) + 17 + 17 + + + DISABLED + Not Communicating with low speed device + 0x0 + + + ENABLED + Communicating with low speed device + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CTRL + Control + 0x0 + + + ISOC + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERR + Interrupt + 0x3 + + + + + EC + Multi Count (MC) / Error Count (EC) + 20 + 21 + + + TRANSONE + 1 transaction + 0x1 + + + TRANSTWO + 2 transactions to be issued for this endpoint per microframe + 0x2 + + + TRANSTHREE + 3 transactions to be issued for this endpoint per microframe + 0x3 + + + + + DEVADDR + Device Address (DevAddr) + 22 + 28 + + + ODDFRM + Odd Frame (OddFrm) + 29 + 29 + + + EFRAME + Even Frame Transfer + 0x0 + + + OFRAME + Odd Frame Transfer + 0x1 + + + + + CHDIS + Channel Disable (ChDis) + 30 + 30 + + + INACTIVE + Transmit/Recieve normal + 0x0 + + + ACTIVE + Stop transmitting/receiving data on channel + 0x1 + + + + + CHENA + Channel Enable (ChEna) + 31 + 31 + + + DISABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is disabled. + 0x0 + + + ENABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure and data buffer with data is set up and this channel can access the descriptor. If Scatter/Gather mode is disabled, indicates that the channel is enabled. + 0x1 + + + + + + + INT + Description cluster: Host Channel Interrupt Register + 0x008 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed (XferCompl) + 0 + 0 + + + INACTIVE + Transfer in progress or No Active Transfer + 0x0 + + + ACTIVE + Transfer completed normally without any errors + 0x1 + + + + + CHHLTD + Channel Halted (ChHltd) + 1 + 1 + + + INACTIVE + Channel not halted + 0x0 + + + ACTIVE + Channel Halted + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB error + 0x0 + + + ACTIVE + AHB error during AHB read/write + 0x1 + + + + + STALL + STALL Response Received Interrupt (STALL) + 3 + 3 + + + INACTIVE + No Stall Response Received Interrupt + 0x0 + + + ACTIVE + Stall Response Received Interrupt + 0x1 + + + + + NAK + NAK Response Received Interrupt (NAK) + 4 + 4 + + + INACTIVE + No NAK Response Received Interrupt + 0x0 + + + ACTIVE + NAK Response Received Interrupt + 0x1 + + + + + ACK + ACK Response Received/Transmitted Interrupt (ACK) + 5 + 5 + + + INACTIVE + No ACK Response Received or Transmitted Interrupt + 0x0 + + + ACTIVE + ACK Response Received or Transmitted Interrup + 0x1 + + + + + NYET + NYET Response Received Interrupt (NYET) + 6 + 6 + + + INACTIVE + No NYET Response Received Interrupt + 0x0 + + + ACTIVE + NYET Response Received Interrupt + 0x1 + + + + + XACTERR + Transaction Error (XactErr) + 7 + 7 + + + INACTIVE + No Transaction Error + 0x0 + + + ACTIVE + Transaction Error + 0x1 + + + + + BBLERR + Babble Error (BblErr) + 8 + 8 + + + INACTIVE + No Babble Error + 0x0 + + + ACTIVE + Babble Error + 0x1 + + + + + FRMOVRUN + Frame Overrun (FrmOvrun). + 9 + 9 + + + INACTIVE + No Frame Overrun + 0x0 + + + ACTIVE + Frame Overrun + 0x1 + + + + + DATATGLERR + 10 + 10 + + + INACTIVE + No Data Toggle Error + 0x0 + + + ACTIVE + Data Toggle Error + 0x1 + + + + + + + INTMSK + Description cluster: Host Channel Interrupt Mask Register + 0x00C + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + 0 + 0 + + + MASK + Transfer Completed Mask + 0x0 + + + NOMASK + No Transfer Completed Mask + 0x1 + + + + + CHHLTDMSK + 1 + 1 + + + MASK + Channel Halted Mask + 0x0 + + + NOMASK + No Channel Halted Mask + 0x1 + + + + + AHBERRMSK + 2 + 2 + + + MASK + AHB Error Mask + 0x0 + + + NOMASK + No AHB Error Mask + 0x1 + + + + + STALLMSK + 3 + 3 + + + MASK + Mask STALL Response Received Interrupt + 0x0 + + + NOMASK + No STALL Response Received Interrupt Mask + 0x1 + + + + + NAKMSK + 4 + 4 + + + MASK + Mask NAK Response Received Interrupt + 0x0 + + + NOMASK + No NAK Response Received Interrupt Mask + 0x1 + + + + + ACKMSK + 5 + 5 + + + MASK + Mask ACK Response Received/Transmitted Interrupt + 0x0 + + + NOMASK + No ACK Response Received/Transmitted Interrupt Mask + 0x1 + + + + + NYETMSK + 6 + 6 + + + MASK + Mask NYET Response Received Interrupt + 0x0 + + + NOMASK + No NYET Response Received Interrupt Mask + 0x1 + + + + + XACTERRMSK + 7 + 7 + + + MASK + Mask Transaction Error + 0x0 + + + NOMASK + No Transaction Error Mask + 0x1 + + + + + BBLERRMSK + 8 + 8 + + + MASK + Mask Babble Error + 0x0 + + + NOMASK + No Babble Error Mask + 0x1 + + + + + FRMOVRUNMSK + 9 + 9 + + + MASK + Mask Overrun Mask + 0x0 + + + NOMASK + No Frame Overrun Mask + 0x1 + + + + + DATATGLERRMSK + 10 + 10 + + + MASK + Mask Data Toggle Error + 0x0 + + + NOMASK + No Data Toggle Error Mask + 0x1 + + + + + + + TSIZ + Description cluster: Host Channel Transfer Size Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Non-Scatter/Gather DMA Mode: + 0 + 18 + + + PKTCNT + Non-Scatter/Gather DMA Mode: + 19 + 28 + + + PID + PID (Pid) + 29 + 30 + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA (non-control)/SETUP (control) + 0x3 + + + + + DOPNG + Do Ping (DoPng) + 31 + 31 + + + NOPING + No ping protocol + 0x0 + + + PING + Ping protocol + 0x1 + + + + + + + DMA + Description cluster: Host Channel DMA Address Register + 0x014 + read-write + 0x00000000 + 0x20 + + + DMAADDR + In Buffer DMA Mode: + 0 + 31 + + + + + + DCFG + Device Configuration Register + 0x800 + read-write + 0x08020000 + 0x20 + + + DEVSPD + Device Speed (DevSpd) + 0 + 1 + + + USBHS20 + High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x0 + + + USBFS20 + Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x1 + + + USBLS116 + Low speed USB 1.1 transceiver clock is 6 MHz + 0x2 + + + USBFS1148 + Full speed USB 1.1 transceiver clock is 48 MHz + 0x3 + + + + + NZSTSOUTHSHK + Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + 2 + 2 + + + SENDOUT + Send the received OUT packet to the application (zero-length or non-zero length) and send a handshake based on NAK and STALL bits for the endpoint in the Devce Endpoint Control Register + 0x0 + + + SENDSTALL + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application + 0x1 + + + + + ENA32KHZSUSP + Enable 32 KHz Suspend mode (Ena32KHzSusp) + 3 + 3 + + + DISABLED + USB 1.1 Full-Speed Serial Transceiver not selected + 0x0 + + + ENABLED + USB 1.1 Full-Speed Serial Transceiver Interface selected + 0x1 + + + + + DEVADDR + Device Address (DevAddr) + 4 + 10 + + + PERFRINT + Periodic Frame Interval (PerFrInt) + 11 + 12 + + + EOPF80 + 80 percent of the (micro)Frame interval + 0x0 + + + EOPF85 + 85 percent of the (micro)Frame interval + 0x1 + + + EOPF90 + 90 percent of the (micro)Frame interval + 0x2 + + + EOPF95 + 95 percent of the (micro)Frame interval + 0x3 + + + + + XCVRDLY + XCVRDLY + 14 + 14 + + + DISABLE + No delay between xcvr_sel and txvalid during Device chirp + 0x0 + + + ENABLE + Enable delay between xcvr_sel and txvalid during Device chirp + 0x1 + + + + + ERRATICINTMSK + Erratic Error Interrupt Mask + 15 + 15 + + + NOMASK + Early suspend interrupt is generated on erratic error + 0x0 + + + MASK + Mask early suspend interrupt on erratic error + 0x1 + + + + + IPGISOCSUPT + Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) + 17 + 17 + + + DISABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is disabled + 0x0 + + + ENABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is enabled + 0x1 + + + + + PERSCHINTVL + Periodic Scheduling Interval (PerSchIntvl) + 24 + 25 + + + MF25 + 25 percent of (micro)Frame + 0x0 + + + MF50 + 50 percent of (micro)Frame + 0x1 + + + MF75 + 75 percent of (micro)Frame + 0x2 + + + + + RESVALID + Resume Validation Period (ResValid) + 26 + 31 + + + + + DCTL + Device Control Register + 0x804 + read-write + 0x00000002 + 0x20 + + + RMTWKUPSIG + Remote Wakeup Signaling (RmtWkUpSig) + 0 + 0 + + + DISABLEDRMWKUP + Core does not send Remote Wakeup Signaling + 0x0 + + + ENABLERMWKUP + Core sends Remote Wakeup Signaling + 0x1 + + + + + SFTDISCON + Soft Disconnect (SftDiscon) + 1 + 1 + + + NODISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + 0x0 + + + DISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host + 0x1 + + + + + GNPINNAKSTS + Global Non-periodic IN NAK Status (GNPINNakSts) + 2 + 2 + read-only + + + INACTIVE + A handshake is sent out based on the data availability in the transmit FIFO + 0x0 + + + ACTIVE + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + 0x1 + + + + + GOUTNAKSTS + Global OUT NAK Status (GOUTNakSts) + 3 + 3 + read-only + + + INACTIVE + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + 0x0 + + + ACTIVE + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + 0x1 + + + + + TSTCTL + Test Control (TstCtl) + 4 + 6 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFE + Test_force_Enable + 0x5 + + + + + SGNPINNAK + Set Global Non-periodic IN NAK (SGNPInNak) + 7 + 7 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Set Global Non-periodic IN NAK + 0x1 + + + + + CGNPINNAK + Clear Global Non-periodic IN NAK (CGNPInNak) + 8 + 8 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Clear Global Non-periodic IN NAK + 0x1 + + + + + SGOUTNAK + Set Global OUT NAK (SGOUTNak) + 9 + 9 + write-only + + + DISABLED + Disable Global OUT NAK + 0x0 + + + ENABLED + Set Global OUT NAK + 0x1 + + + + + CGOUTNAK + Clear Global OUT NAK (CGOUTNak) + 10 + 10 + write-only + + + DISABLED + Disable Clear Global OUT NAK + 0x0 + + + ENABLED + Clear Global OUT NAK + 0x1 + + + + + PWRONPRGDONE + Power-On Programming Done (PWROnPrgDone) + 11 + 11 + + + NOTDONE + Power-On Programming not done + 0x0 + + + DONE + Power-On Programming Done + 0x1 + + + + + IGNRFRMNUM + Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + 15 + 15 + + + DISABLED + Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in which they are intended to be transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is disabled. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediately as the packets are ready.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is enabled. + 0x1 + + + + + NAKONBBLE + NAK on Babble Error (NakOnBble) + 16 + 16 + + + DISABLED + Disable NAK on Babble Error + 0x0 + + + ENABLED + NAK on Babble Error + 0x1 + + + + + DEEPSLEEPBESLREJECT + DeepSleepBESLReject + 18 + 18 + + + DISABLED + Deep Sleep BESL Reject feature is disabled + 0x0 + + + ENABLED + Deep Sleep BESL Reject feature is enabled + 0x1 + + + + + SERVINT + Service Interval based scheduling for Isochronous IN Endpoints + 19 + 19 + + + DISABLED + The controller behavior depends on DCTL.IgnrFrmNum field. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the service interval. + 0x1 + + + + + UTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface. + 30 + 30 + + + DISABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW (1'b0)on soft disconnect. + 0x0 + + + ENABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft disconnect. + 0x1 + + + + + UTMITERMSELCORRDIS + Disable the correction of TermSel on UTMI Interface. + 31 + 31 + + + DISABLED + Valid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x0 + + + ENABLED + Invalid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x1 + + + + + + + DSTS + Device Status Register + 0x808 + read-write + 0x00000002 + 0x20 + + + SUSPSTS + Suspend Status (SuspSts) + 0 + 0 + read-only + + + INACTIVE + No suspend state + 0x0 + + + ACTIVE + Suspend state + 0x1 + + + + + ENUMSPD + Enumerated Speed (EnumSpd) + 1 + 2 + read-only + + + HS3060 + High speed (PHY clock is running at 30 or 60 MHz) + 0x0 + + + FS3060 + Full speed (PHY clock is running at 30 or 60 MHz) + 0x1 + + + LS6 + Low speed (PHY clock is running at 6 MHz) + 0x2 + + + FS48 + Full speed (PHY clock is running at 48 MHz) + 0x3 + + + + + ERRTICERR + Erratic Error (ErrticErr) + 3 + 3 + read-only + + + INACTIVE + No Erratic Error + 0x0 + + + ACTIVE + Erratic Error + 0x1 + + + + + SOFFN + Frame or Microframe Number of the Received SOF (SOFFN) + 8 + 21 + read-only + + + DEVLNSTS + Device Line Status (DevLnSts) + 22 + 23 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error Mask (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + TIMEOUTMSK + Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + 3 + 3 + + + MASK + Mask Timeout Condition Interrupt + 0x0 + + + NOMASK + No Timeout Condition Interrupt Mask + 0x1 + + + + + INTKNTXFEMPMSK + IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + 4 + 4 + + + MASK + Mask IN Token Received When TxFIFO Empty Interrupt + 0x0 + + + NOMASK + No IN Token Received When TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMISMSK + IN Token received with EP Mismatch Mask (INTknEPMisMsk) + 5 + 5 + + + MASK + Mask IN Token received with EP Mismatch Interrupt + 0x0 + + + NOMASK + No Mask IN Token received with EP Mismatch Interrupt + 0x1 + + + + + INEPNAKEFFMSK + IN Endpoint NAK Effective Mask (INEPNakEffMsk) + 6 + 6 + + + MASK + Mask IN Endpoint NAK Effective Interrupt + 0x0 + + + NOMASK + No IN Endpoint NAK Effective Interrupt Mask + 0x1 + + + + + TXFIFOUNDRNMSK + Fifo Underrun Mask (TxfifoUndrnMsk) + 8 + 8 + + + MASK + Mask Fifo Underrun Interrupt + 0x0 + + + NOMASK + No Fifo Underrun Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No Mask NAK Interrupt + 0x1 + + + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + SETUPMSK + SETUP Phase Done Mask (SetUPMsk) + 3 + 3 + + + MASK + Mask SETUP Phase Done Interrupt + 0x0 + + + NOMASK + No SETUP Phase Done Interrupt Mask + 0x1 + + + + + OUTTKNEPDISMSK + OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + 4 + 4 + + + MASK + Mask OUT Token Received when Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No OUT Token Received when Endpoint Disabled Interrupt Mask + 0x1 + + + + + STSPHSERCVDMSK + Status Phase Received Mask (StsPhseRcvdMsk) + 5 + 5 + + + MASK + Status Phase Received Mask + 0x0 + + + NOMASK + No Status Phase Received Mask + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + 6 + 6 + + + MASK + Mask Back-to-Back SETUP Packets Received Interrupt + 0x0 + + + NOMASK + No Back-to-Back SETUP Packets Received Interrupt Mask + 0x1 + + + + + OUTPKTERRMSK + OUT Packet Error Mask (OutPktErrMsk) + 8 + 8 + + + MASK + Mask OUT Packet Error Interrupt + 0x0 + + + NOMASK + No OUT Packet Error Interrupt Mask + 0x1 + + + + + BBLEERRMSK + Babble Error interrupt Mask (BbleErrMsk) + 12 + 12 + + + MASK + Mask Babble Error Interrupt + 0x0 + + + NOMASK + No Babble Error Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No NAK Interrupt Mask + 0x1 + + + + + NYETMSK + NYET interrupt Mask (NYETMsk) + 14 + 14 + + + MASK + Mask NYET Interrupt + 0x0 + + + NOMASK + No NYET Interrupt Mask + 0x1 + + + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + read-write + 0x00000000 + 0x20 + + + INEPINT0 + IN Endpoint 0 Interrupt Bit + 0 + 0 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for IN EP0 + 0x1 + + + + + INEPINT1 + IN Endpoint 1 Interrupt Bit + 1 + 1 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT2 + IN Endpoint 2 Interrupt Bit + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT3 + IN Endpoint 3 Interrupt Bit + 3 + 3 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT4 + IN Endpoint 4 Interrupt Bit + 4 + 4 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT5 + IN Endpoint 5 Interrupt Bit + 5 + 5 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT6 + IN Endpoint 6 Interrupt Bit + 6 + 6 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT7 + IN Endpoint 7 Interrupt Bit + 7 + 7 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT8 + IN Endpoint 8 Interrupt Bit + 8 + 8 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT9 + IN Endpoint 9 Interrupt Bit + 9 + 9 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT10 + IN Endpoint 10 Interrupt Bit + 10 + 10 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT11 + IN Endpoint 11 Interrupt Bit + 11 + 11 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + OUTEPINT0 + OUT Endpoint 0 Interrupt Bit + 16 + 16 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for OUT EP0 + 0x1 + + + + + OUTEPINT1 + OUT Endpoint 1 Interrupt Bit + 17 + 17 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT2 + OUT Endpoint 2 Interrupt Bit + 18 + 18 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT3 + OUT Endpoint 3 Interrupt Bit + 19 + 19 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT4 + OUT Endpoint 4 Interrupt Bit + 20 + 20 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT5 + OUT Endpoint 5 Interrupt Bit + 21 + 21 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT12 + OUT Endpoint 12 Interrupt Bit + 28 + 28 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT13 + OUT Endpoint 13 Interrupt Bit + 29 + 29 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT14 + OUT Endpoint 14 Interrupt Bit + 30 + 30 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT15 + OUT Endpoint 15 Interrupt Bit + 31 + 31 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + read-write + 0x00000000 + 0x20 + + + INEPMSK0 + IN Endpoint 0 Interrupt mask Bit + 0 + 0 + + + MASK + Mask IN Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK1 + IN Endpoint 1 Interrupt mask Bit + 1 + 1 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK2 + IN Endpoint 2 Interrupt mask Bit + 2 + 2 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK3 + IN Endpoint 3 Interrupt mask Bit + 3 + 3 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK4 + IN Endpoint 4 Interrupt mask Bit + 4 + 4 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK5 + IN Endpoint 5 Interrupt mask Bit + 5 + 5 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK6 + IN Endpoint 6 Interrupt mask Bit + 6 + 6 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK7 + IN Endpoint 7 Interrupt mask Bit + 7 + 7 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK8 + IN Endpoint 8 Interrupt mask Bit + 8 + 8 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK9 + IN Endpoint 9 Interrupt mask Bit + 9 + 9 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK10 + IN Endpoint 10 Interrupt mask Bit + 10 + 10 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK11 + IN Endpoint 11 Interrupt mask Bit + 11 + 11 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK0 + OUT Endpoint 0 Interrupt mask Bit + 16 + 16 + + + MASK + Mask OUT Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK1 + OUT Endpoint 1 Interrupt mask Bit + 17 + 17 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK2 + OUT Endpoint 2 Interrupt mask Bit + 18 + 18 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK3 + OUT Endpoint 3 Interrupt mask Bit + 19 + 19 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK4 + OUT Endpoint 4 Interrupt mask Bit + 20 + 20 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK5 + OUT Endpoint 5 Interrupt mask Bit + 21 + 21 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK12 + OUT Endpoint 12 Interrupt mask Bit + 28 + 28 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK13 + OUT Endpoint 13 Interrupt mask Bit + 29 + 29 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK14 + OUT Endpoint 14 Interrupt mask Bit + 30 + 30 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK15 + OUT Endpoint 15 Interrupt mask Bit + 31 + 31 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + read-write + 0x000017D7 + 0x20 + + + DVBUSDIS + Device VBUS Discharge Time (DVBUSDis) + 0 + 15 + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + read-write + 0x000005B8 + 0x20 + + + DVBUSPULSE + Device VBUS Pulsing Time (DVBUSPulse) + 0 + 11 + + + + + DTHRCTL + Device Threshold Control Register + 0x830 + read-write + 0x08100020 + 0x20 + + + NONISOTHREN + Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + 0 + 0 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enable thresholding for non-isochronous IN endpoints + 0x1 + + + + + ISOTHREN + 1 + 1 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enables thresholding for isochronous IN endpoints + 0x1 + + + + + TXTHRLEN + Transmit Threshold Length (TxThrLen) + 2 + 10 + + + AHBTHRRATIO + AHB Threshold Ratio (AHBThrRatio) + 11 + 12 + + + THRESZERO + AHB threshold = MAC threshold + 0x0 + + + THRESONE + AHB threshold = MAC threshold /2 + 0x1 + + + THRESTWO + AHB threshold = MAC threshold /4 + 0x2 + + + THRESTHREE + AHB threshold = MAC threshold /8 + 0x3 + + + + + RXTHREN + Receive Threshold Enable (RxThrEn) + 16 + 16 + + + DISABLED + Disable thresholding + 0x0 + + + ENABLED + Enable thresholding in the receive direction + 0x1 + + + + + RXTHRLEN + Receive Threshold Length (RxThrLen) + 17 + 25 + + + ARBPRKEN + Arbiter Parking Enable (ArbPrkEn) + 27 + 27 + + + DISABLED + Disable DMA arbiter parking + 0x0 + + + ENABLED + Enable DMA arbiter parking for IN endpoints + 0x1 + + + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + read-write + 0x00000000 + 0x20 + + + INEPTXFEMPMSK + IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + 0 + 15 + + + EP0_MASK + Mask IN EP0 Tx FIFO Empty Interrupt + 0x0001 + + + EP1_MASK + Mask IN EP1 Tx FIFO Empty Interrupt + 0x0002 + + + EP2_MASK + Mask IN EP2 Tx FIFO Empty Interrupt + 0x0004 + + + EP3_MASK + Mask IN EP3 Tx FIFO Empty Interrupt + 0x0008 + + + EP4_MASK + Mask IN EP4 Tx FIFO Empty Interrupt + 0x0010 + + + EP5_MASK + Mask IN EP5 Tx FIFO Empty Interrupt + 0x0020 + + + EP6_MASK + Mask IN EP6 Tx FIFO Empty Interrupt + 0x0040 + + + EP7_MASK + Mask IN EP7 Tx FIFO Empty Interrupt + 0x0080 + + + EP8_MASK + Mask IN EP8 Tx FIFO Empty Interrupt + 0x0100 + + + EP9_MASK + Mask IN EP9 Tx FIFO Empty Interrupt + 0x0200 + + + EP10_MASK + Mask IN EP10 Tx FIFO Empty Interrupt + 0x0400 + + + EP11_MASK + Mask IN EP11 Tx FIFO Empty Interrupt + 0x0800 + + + EP12_MASK + Mask IN EP12 Tx FIFO Empty Interrupt + 0x1000 + + + EP13_MASK + Mask IN EP13 Tx FIFO Empty Interrupt + 0x2000 + + + EP14_MASK + Mask IN EP14 Tx FIFO Empty Interrupt + 0x4000 + + + EP15_MASK + Mask IN EP15 Tx FIFO Empty Interrupt + 0x8000 + + + + + + + DIEPCTL0 + Device Control IN Endpoint 0 Control Register + 0x900 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + + + BYTES64 + 64 bytes + 0x0 + + + BYTES32 + 32 bytes + 0x1 + + + BYTES16 + 16 bytes + 0x2 + + + BYTES8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE0 + Control endpoint is always active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Disabled Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT0 + Device IN Endpoint 0 Interrupt Register + 0x908 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Completed Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received when TxFIFO Empty interrupt + 0x0 + + + ACTIVE + IN Token Received when TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No IN Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Fifo Underrun interrupt + 0x0 + + + ACTIVE + Fifo Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ0 + Device IN Endpoint 0 Transfer Size Register + 0x910 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 20 + + + + + DIEPDMA0 + Device IN Endpoint 0 DMA Address Register + 0x914 + read-write + 0x00000000 + 0x20 + + + DMAADDR + DMAAddr + 0 + 31 + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register 0 + 0x918 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL1 + Device Control IN Endpoint Control Register + 0x920 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT1 + Device IN Endpoint Interrupt Register + 0x928 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ1 + Device IN Endpoint Transfer Size Register + 0x930 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA1 + Device IN Endpoint DMA Address Register + 0x934 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS1 + Device IN Endpoint Transmit FIFO Status Register + 0x938 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL2 + Device Control IN Endpoint Control Register + 0x940 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT2 + Device IN Endpoint Interrupt Register + 0x948 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ2 + Device IN Endpoint Transfer Size Register + 0x950 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA2 + Device IN Endpoint DMA Address Register + 0x954 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS2 + Device IN Endpoint Transmit FIFO Status Register + 0x958 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL3 + Device Control IN Endpoint Control Register + 0x960 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT3 + Device IN Endpoint Interrupt Register + 0x968 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ3 + Device IN Endpoint Transfer Size Register + 0x970 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA3 + Device IN Endpoint DMA Address Register + 0x974 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS3 + Device IN Endpoint Transmit FIFO Status Register + 0x978 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL4 + Device Control IN Endpoint Control Register + 0x980 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT4 + Device IN Endpoint Interrupt Register + 0x988 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ4 + Device IN Endpoint Transfer Size Register + 0x990 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA4 + Device IN Endpoint DMA Address Register + 0x994 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS4 + Device IN Endpoint Transmit FIFO Status Register + 0x998 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL5 + Device Control IN Endpoint Control Register + 0x9A0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT5 + Device IN Endpoint Interrupt Register + 0x9A8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ5 + Device IN Endpoint Transfer Size Register + 0x9B0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA5 + Device IN Endpoint DMA Address Register + 0x9B4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS5 + Device IN Endpoint Transmit FIFO Status Register + 0x9B8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL6 + Device Control IN Endpoint Control Register + 0x9C0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT6 + Device IN Endpoint Interrupt Register + 0x9C8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ6 + Device IN Endpoint Transfer Size Register + 0x9D0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA6 + Device IN Endpoint DMA Address Register + 0x9D4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS6 + Device IN Endpoint Transmit FIFO Status Register + 0x9D8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL7 + Device Control IN Endpoint Control Register + 0x9E0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT7 + Device IN Endpoint Interrupt Register + 0x9E8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ7 + Device IN Endpoint Transfer Size Register + 0x9F0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA7 + Device IN Endpoint DMA Address Register + 0x9F4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS7 + Device IN Endpoint Transmit FIFO Status Register + 0x9F8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL8 + Device Control IN Endpoint Control Register + 0xA00 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT8 + Device IN Endpoint Interrupt Register + 0xA08 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ8 + Device IN Endpoint Transfer Size Register + 0xA10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA8 + Device IN Endpoint DMA Address Register + 0xA14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS8 + Device IN Endpoint Transmit FIFO Status Register + 0xA18 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL9 + Device Control IN Endpoint Control Register + 0xA20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT9 + Device IN Endpoint Interrupt Register + 0xA28 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ9 + Device IN Endpoint Transfer Size Register + 0xA30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA9 + Device IN Endpoint DMA Address Register + 0xA34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS9 + Device IN Endpoint Transmit FIFO Status Register + 0xA38 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL10 + Device Control IN Endpoint Control Register + 0xA40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT10 + Device IN Endpoint Interrupt Register + 0xA48 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ10 + Device IN Endpoint Transfer Size Register + 0xA50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA10 + Device IN Endpoint DMA Address Register + 0xA54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS10 + Device IN Endpoint Transmit FIFO Status Register + 0xA58 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL11 + Device Control IN Endpoint Control Register + 0xA60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT11 + Device IN Endpoint Interrupt Register + 0xA68 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ11 + Device IN Endpoint Transfer Size Register + 0xA70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA11 + Device IN Endpoint DMA Address Register + 0xA74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS11 + Device IN Endpoint Transmit FIFO Status Register + 0xA78 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint 0 Control Register + 0xB00 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + read-only + + + BYTE64 + 64 bytes + 0x0 + + + BYTE32 + 32 bytes + 0x1 + + + BYTE16 + 16 bytes + 0x2 + + + BYTE8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE + USB Active Endpoint 0 + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + read-only + + + INACTIVE + No Endpoint disable + 0x0 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT0 + Device OUT Endpoint 0 Interrupt Register + 0xB08 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ0 + Device OUT Endpoint 0 Transfer Size Register + 0xB10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 19 + + + SUPCNT + SETUP Packet Count (SUPCnt) + 29 + 30 + + + ONEPACKET + 1 packet + 0x1 + + + TWOPACKET + 2 packets + 0x2 + + + THREEPACKET + 3 packets + 0x3 + + + + + + + DOEPDMA0 + Device OUT Endpoint 0 DMA Address Register + 0xB14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL1 + Device Control OUT Endpoint Control Register + 0xB20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT1 + Device OUT Endpoint Interrupt Register + 0xB28 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ1 + Device OUT Endpoint Transfer Size Register + 0xB30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA1 + Device OUT Endpoint DMA Address Register + 0xB34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL2 + Device Control OUT Endpoint Control Register + 0xB40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT2 + Device OUT Endpoint Interrupt Register + 0xB48 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ2 + Device OUT Endpoint Transfer Size Register + 0xB50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA2 + Device OUT Endpoint DMA Address Register + 0xB54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL3 + Device Control OUT Endpoint Control Register + 0xB60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT3 + Device OUT Endpoint Interrupt Register + 0xB68 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ3 + Device OUT Endpoint Transfer Size Register + 0xB70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA3 + Device OUT Endpoint DMA Address Register + 0xB74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL4 + Device Control OUT Endpoint Control Register + 0xB80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT4 + Device OUT Endpoint Interrupt Register + 0xB88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ4 + Device OUT Endpoint Transfer Size Register + 0xB90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA4 + Device OUT Endpoint DMA Address Register + 0xB94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL5 + Device Control OUT Endpoint Control Register + 0xBA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT5 + Device OUT Endpoint Interrupt Register + 0xBA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ5 + Device OUT Endpoint Transfer Size Register + 0xBB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA5 + Device OUT Endpoint DMA Address Register + 0xBB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL12 + Device Control OUT Endpoint Control Register + 0xC80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT12 + Device OUT Endpoint Interrupt Register + 0xC88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ12 + Device OUT Endpoint Transfer Size Register + 0xC90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA12 + Device OUT Endpoint DMA Address Register + 0xC94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL13 + Device Control OUT Endpoint Control Register + 0xCA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT13 + Device OUT Endpoint Interrupt Register + 0xCA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ13 + Device OUT Endpoint Transfer Size Register + 0xCB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA13 + Device OUT Endpoint DMA Address Register + 0xCB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL14 + Device Control OUT Endpoint Control Register + 0xCC0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT14 + Device OUT Endpoint Interrupt Register + 0xCC8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ14 + Device OUT Endpoint Transfer Size Register + 0xCD0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA14 + Device OUT Endpoint DMA Address Register + 0xCD4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL15 + Device Control OUT Endpoint Control Register + 0xCE0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT15 + Device OUT Endpoint Interrupt Register + 0xCE8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ15 + Device OUT Endpoint Transfer Size Register + 0xCF0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA15 + Device OUT Endpoint DMA Address Register + 0xCF4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + read-write + 0x880A0000 + 0x20 + + + STOPPCLK + Stop Pclk (StopPclk) + 0 + 0 + + + DISABLED + Disable Stop Pclk + 0x0 + + + ENABLED + Enable Stop Pclk + 0x1 + + + + + GATEHCLK + Gate Hclk (GateHclk) + 1 + 1 + + + DISABLED + Clears this bit when the USB is resumed or a new session starts + 0x0 + + + ENABLED + Sets this bit to gate hclk to modules when the USB is suspended or the session is not valid + 0x1 + + + + + RSTPDWNMODULE + Reset Power-Down Modules (RstPdwnModule) + 3 + 3 + + + ON + Power is turned on + 0x0 + + + OFF + Power is turned off + 0x1 + + + + + ENBLL1GATING + Enable Sleep Clock Gating + 5 + 5 + + + DISABLED + The PHY clock is not gated in Sleep state + 0x0 + + + ENABLED + The Core internal clock gating is enabled in Sleep state + 0x1 + + + + + PHYSLEEP + PHY In Sleep + 6 + 6 + read-only + + + INACTIVE + Phy not in Sleep state + 0x0 + + + ACTIVE + Phy in Sleep state + 0x1 + + + + + L1SUSPENDED + L1 Deep Sleep + 7 + 7 + read-only + + + INACTIVE + Non Deep Sleep + 0x0 + + + ACTIVE + Deep Sleep + 0x1 + + + + + RESTOREMODE + Restore Mode (RestoreMode) + 9 + 9 + + + DISABLED + In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this bit indicates Device-initiated Remote Wakeup + 0x0 + + + ENABLED + In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this bit indicates Host-initiated Resume and Reset + 0x1 + + + + + ESSREGRESTORED + Essential Register Values Restored (EssRegRestored) + 13 + 13 + write-only + + + NOT_RESTORED + Register values of essential registers are not restored + 0x0 + + + RESTORED + Register values of essential registers have been restored + 0x1 + + + + + RESTOREVALUE + Restore Value (RestoreValue) + 14 + 31 + + + + + GSTARFXDIS + Global STAR Fix Disable Register + 0xF00 + read-write + 0x00002200 + 0x20 + + + HOSTIGNORESRMTWKUPDIS + Disable the STAR fix added for Device controller to go back to low power mode when Host ignores Remote wakeup + 0 + 0 + + + ENABLE_FIX + Device controller goes back into SUSPENDED state when host ignores Remote Wakeup + 0x0 + + + DISABLE_FIX + Device controller waits indefinitely without entering SUSPENDED state when host ignores the Remote Wakeup + 0x1 + + + + + RESUMEFRMCHKBUSDIS + Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after the 50us pull-up delay ends + 1 + 1 + + + ENABLE_FIX + Device controller detects line K and resumes + 0x0 + + + DISABLE_FIX + Device controller does not detect line K and resume + 0x1 + + + + + IGNORECTLOUTDATA0DIS + Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data Phase and Control Status OUT Phase + 2 + 2 + + + ENABLE_FIX + Transaction Error reported when host sends DATA0 PID + 0x0 + + + DISABLE_FIX + Transaction Error not reported when host sends DATA0 PID + 0x1 + + + + + SSPLITSTALLNYETERRDIS + Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET + 3 + 3 + + + ENABLE_FIX + Transaction Error reported when device sends STALL/NYET for SSPLIT + 0x0 + + + DISABLE_FIX + Transaction Error not reported when device sends STALL/NYET for SSPLIT + 0x1 + + + + + ACCEPTISOCSPLITDATA1DIS + Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC Split transfers + 4 + 4 + + + ENABLE_FIX + Transaction Error not reported when device sends DATA1 PID for ISOC Split + 0x0 + + + DISABLE_FIX + Transaction Error reported when device sends DATA1 PID for ISOC Split + 0x1 + + + + + HANDLEFAULTYCABLEDIS + Disable the STAR fix added for Host controller to handle Faulty cable scenarios + 5 + 5 + + + ENABLE_FIX + Fix for handling faulty cable enabled + 0x0 + + + DISABLE_FIX + Fix for handling faulty cable disabled + 0x1 + + + + + LSIPGINCRDIS + Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit times + 6 + 6 + + + ENABLE_FIX + Host LS mode IPG is 3 LS bit times + 0x0 + + + DISABLE_FIX + Host LS mode IPG is 2 LS bit times + 0x1 + + + + + FSDISCIDLEDIS + Disable the STAR fix added for Device controller to transition to IDLE state during FS device disconnect + 7 + 7 + + + ENABLE_FIX + Device controller transitions to IDLE state during FS device disconnect + 0x0 + + + DISABLE_FIX + Device controller does not transition to IDLE state during FS device disconnect + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEDIS + Disable the STAR fix added for Device controller to not start Remote Wakeup signalling when USB resume has already started + 8 + 8 + + + ENABLE_FIX + Device controller does not start remote wakeup signalling when host resume has already started + 0x0 + + + DISABLE_FIX + Device controller is allowed to start remote wakeup signalling when host resume has already started + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEHIBDIS + Disable the STAR fix added for Device controller to not hang when Remote Wakeup signalling clashes with Host resume + 9 + 9 + + + ENABLE_FIX + Device controller does not hang when remote wakeup signalling clashes with host resume during Hibernation exit + 0x0 + + + DISABLE_FIX + Device controller hangs when remote wakeup signalling clashes with host resume during Hibernation exit + 0x1 + + + + + LSIPGCHKAFTERNAKSTALLFORINDIS + Disable the STAR fix added for Host controller to wait for IPG duration to send next token after receiving NAK/STALL for previous IN token with FS/LS device + 10 + 10 + + + ENABLE_FIX + Host controller checks IPG after NAK/STALL for IN token + 0x0 + + + DISABLE_FIX + Host controller does not check IPG after NAK/STALL for IN token + 0x1 + + + + + PHYIOPXCVRSELTXVLDCORRDIS + Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode + 11 + 11 + + + ENABLE_FIX + Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect switching + 0x0 + + + DISABLE_FIX + Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect switching + 0x1 + + + + + ULPIXCVRSELSWITCHCORRDIS + Disable the STAR fix added for Host controller to increase the preamble transceiver select switch delay to accommodate time taken for ULPI function control write + 12 + 12 + + + ENABLE_FIX + Host controller waits for previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x0 + + + DISABLE_FIX + Host controller does not wait for the previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x1 + + + + + XACTERRDATA0CTRLSTSINDIS + Disable the STAR fix added for Host controller to report transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 13 + 13 + + + ENABLE_FIX + Host controller reports transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x0 + + + DISABLE_FIX + Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x1 + + + + + HOSTUTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. + 16 + 16 + + + ENABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1'b0) + 0x0 + + + DISABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxValid to go LOW (1'b0) during SOF transmission + 0x1 + + + + + OPMODEXCVRSELCHIRPENCORRDIS + Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when reset is detected in suspend state. + 17 + 17 + + + ENABLE_FIX + Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x0 + + + DISABLE_FIX + Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x1 + + + + + TXVALIDDEASSERTIONCORRDIS + Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft disconnect is done. + 18 + 18 + + + ENABLE_FIX + Txvalid is deasserted during soft disconnect after receiving Txready from the PHY + 0x0 + + + DISABLE_FIX + Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY + 0x1 + + + + + HOSTNOXFERAFTERPRTDISFIXDIS + Disable the STAR fix added for correcting Host behavior when port is disabled. + 19 + 19 + + + ENABLE_FIX + Txvalid is not asserted when port is disabled + 0x0 + + + DISABLE_FIX + Txvalid can be asserted when port is disabled + 0x1 + + + + + + + 16 + 0x1000 + DWCOTGDFIFO[%s] + Unspecified + USBHSCORE_DWCOTGDFIFO + read-write + 0x1000 + + 0x400 + 0x4 + DATA[%s] + Description collection: Data FIFO Access Register Map 0 + 0x0000 + read-write + 0x00000000 + 0x20 + + + + DWCOTGDFIFODIRECTACCESS + Unspecified + USBHSCORE_DWCOTGDFIFODIRECTACCESS + read-write + 0x20000 + + 0x8000 + 0x4 + DATA[%s] + Description collection: Data FIFO Direct Access Register Map + 0x00000 + read-write + 0x00000000 + 0x20 + + + + + + GLOBAL_I3CCORE120 + I3CCORE 0 + 0x2FBE0000 + I3CCORE + + + + 0 + 0x1000 + registers + + I3CCORE + 0x20 + + + CORE + Unspecified + I3CCORE_CORE + read-write + 0x000 + + DEVICECTRL + DWC_mipi_i3c control Register + 0x000 + read-write + 0x00000000 + 0x20 + + + IBAINCLUDE + I3C Broadcast Address include + 0 + 0 + + + NOT_INCLUDED + Unspecified + 0x0 + + + INCLUDED + Unspecified + 0x1 + + + + + I2CSLAVEPRESENT + I2C Slave Present + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + HOTJOINCTRL + Hot-Join ACK/NACK Control + 8 + 8 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + IDLECNTMULTPLIER + Idle Count Multiplier + 24 + 25 + + + MultiplyBy1 + Unspecified + 0x0 + + + MultiplyBy2 + Unspecified + 0x1 + + + MultiplyBy4 + Unspecified + 0x2 + + + MultiplyBy8 + Unspecified + 0x3 + + + + + ADAPTIVEI2CI3C + This field is used in Slave mode of operation. + 27 + 27 + + + DMAENABLE + DMA Handshake Interface Enable + 28 + 28 + + + DISABLE + The DMA handshake control has no significance. + 0x0 + + + ENABLE + Enables the DMA handshake control to interact with external DMA. + 0x1 + + + + + ABORT + DWC_mipi_i3c Abort + 29 + 29 + + + RESUME + DWC_mipi_i3c Resume + 30 + 30 + + + ENABLE + Controls whether or not DWC_mipi_i3c is enabled. + 31 + 31 + + + DISABLE + Disables the DWC_mipi_i3c controller + 0x0 + + + ENABLE + Enables the DWC_mipi_i3c controller. + 0x1 + + + + + + + DEVICEADDR + In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit. + 0x004 + read-write + 0x80000000 + 0x20 + + + STATICADDR + Device Static Address. + 0 + 6 + + + STATICADDRVALID + Static Address Valid. + 15 + 15 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + DYNAMICADDR + Device Dynamic Address. + 16 + 22 + + + DYNAMICADDRVALID + Dynamic Address Valid + 31 + 31 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + + + HWCAPABILITY + Hardware Capability register + 0x008 + read-write + 0x000E187B + 0x20 + + + DEVICEROLECONFIG + Reflects the IC_DEVICE_ROLE Configurable Parameter. + 0 + 2 + read-only + + + MASTER + Master Only + 0x1 + + + PMASTERSLAVE + Programmable Master-Slave + 0x2 + + + SECONDARYMASTER + Secondary Master + 0x3 + + + SLAVE + Slave Only + 0x4 + + + + + HDRDDREN + Reflects the IC_SPEED_HDR_DDR Configurable Parameter. + 3 + 3 + read-only + + + NOTSUPPORTED + HDR-DDR not supported + 0x0 + + + SUPPORTED + HDR-DDR supported + 0x1 + + + + + HDRTSEN + Reflects the IC_SPEED_HDR_TS Configurable Parameter. + 4 + 4 + read-only + + + NOTSUPPORTED + HDR-TS not supported + 0x0 + + + SUPPORTED + HDR-TS supported + 0x1 + + + + + CLOCKPERIOD + Reflects the IC_CLK_PERIOD Configurable Parameter + 5 + 10 + read-only + + + HDRTXCLOCKPERIOD + Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. + 11 + 16 + read-only + + + DMAEN + Reflects the IC_HAS_DMA Configurable Parameter. + 17 + 17 + read-only + + + SLVHJCAP + Reflects the IC_SLV_HJ Configurable Parameter. + 18 + 18 + read-only + + + SLVIBICAP + Reflects the IC_SLV_IBI Configurable Parameter. + 19 + 19 + read-only + + + + + COMMANDQUEUEPORT + Command Queue Port. + 0x00C + read-write + 0x00000000 + 0x20 + + + COMMAND + 32 bit command + 0 + 31 + write-only + + + + + RESPONSEQUEUEPORT + Response Queue Port + 0x010 + read-write + 0x00000000 + 0x20 + + + RESPONSE + 32 bit Response + 0 + 31 + read-only + + + + + RXDATAPORT + Receive Data Port Register + 0x014 + read-write + 0x00000000 + 0x20 + + + RXDATAPORT + Receive Data Port. + 0 + 31 + read-only + + + + + TXDATAPORT + Transmit Data Port Register + 0x014 + read-write + 0x00000000 + RXDATAPORT + 0x20 + + + TXDATAPORT + Transmit Data Port + 0 + 31 + write-only + + + + + IBIQUEUEDATA + In-Band Interrupt Queue Data Register + 0x018 + read-write + 0x00000000 + 0x20 + + + IBIDATA + In-Band Interrupt Data + 0 + 31 + read-only + + + + + IBIQUEUESTATUS + In-Band Interrupt Queue Status Register + 0x018 + read-write + 0x00000000 + IBIQUEUEDATA + 0x20 + + + DATALENGTH + In-Band Interrupt data length. + 0 + 7 + read-only + + + IBIID + IBI Identifier. + 8 + 15 + read-only + + + IBIACK + The acknowledge bit of the IBI Received Status (IBISTS) bitfield. + 31 + 31 + read-only + + + ACK + Responded with ACK + 0x0 + + + NACK + Responded with NACK + 0x1 + + + + + + + QUEUETHLDCTRL + Queue Threshold Control Register + 0x01C + read-write + 0x01000101 + 0x20 + + + CMDEMPTYBUFTHLD + Command Buffer Empty Threshold Value. + 0 + 7 + + + RESPBUFTHLD + Response Buffer Threshold Value. + 8 + 15 + + + IBISTATUSTHLD + In-Band Interrupt Status Threshold Value. + 24 + 31 + + + + + DATABUFFERTHLDCTRL + Data Buffer Threshold Control Register + 0x020 + read-write + 0x01010101 + 0x20 + + + TXEMPTYBUFTHLD + Transmit Buffer Threshold Value + 0 + 2 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD14 + Unspecified + 0x1 + + + THRESHOLD18 + Unspecified + 0x2 + + + THRESHOLD116 + Unspecified + 0x3 + + + THRESHOLD132 + Unspecified + 0x4 + + + THRESHOLD164 + Unspecified + 0x5 + + + + + RXBUFTHLD + Receive Buffer Threshold Value + 8 + 10 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + TXSTARTTHLD + Transfer Start Threshold Value + 16 + 18 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + RXSTARTTHLD + Receive Start Threshold Value + 24 + 26 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + + + IBIQUEUECTRL + This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked). + 0x024 + read-write + 0x00000000 + 0x20 + + + NOTIFYHJREJECTED + Notify Rejected Hot-Join Control. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + NOTIFYMRREJECTED + Notify Rejected Master Request Control. + 1 + 1 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x1 + + + + + NOTIFYSIRREJECTED + Notify Rejected Slave Interrupt Request Control. + 3 + 3 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x1 + + + + + + + IBIMRREQREJECT + IBI Master Request Rejection Control Register. + 0x02C + read-write + 0x00000000 + 0x20 + + + MRREQREJECT + In-band Master Request Reject. + 0 + 31 + + + ACK + ACK Master Request. + 0x00000000 + + + NACK + NACK and send Directed DISEC CCC to disable the interrupting slave. + 0x00000001 + + + + + + + IBISIRREQREJECT + IBI SIR Request Rejection Control + 0x030 + read-write + 0x00000000 + 0x20 + + + SIRREQREJECT + In-band Slave Interrupt Request Reject + 0 + 31 + + + ACK + ACK the SIR Request. + 0x00000000 + + + NACK + NACK and send directed auto disable CCC. + 0x00000001 + + + + + + + RESETCTRL + This Register is used for general software reset and for individual buffer reset. + 0x034 + read-write + 0x00000000 + 0x20 + + + SOFTRST + Core Software Reset. + 0 + 0 + + + CMDQUEUERST + Command Queue Software Reset + 1 + 1 + + + RESPQUEUERST + Response Queue Software Reset + 2 + 2 + + + TXFIFORST + Transmit Buffer Software Reset + 3 + 3 + + + RXFIFORST + Receive Buffer Software Reset. + 4 + 4 + + + IBIQUEUERST + IBI Queue Software Reset. + 5 + 5 + + + BUSRESETTYPE + Bus Reset type + 29 + 30 + + + EXIT + Exit Pattern. + 0x0 + + + SCL_LOW_RESET + SCL_LOW_RESET Pattern. + 0x3 + + + + + BUSRESET + Bus Reset. + 31 + 31 + + + + + SLVEVENTSTATUS + This register indicates the status/values of some events/controls that are relavant to slave mode of operation. + 0x038 + read-write + 0x0000000B + 0x20 + + + SIREN + Slave Interrupt Request Enable. + 0 + 0 + read-only + + + MREN + Master Request Enable. + 1 + 1 + read-only + + + HJEN + Hot-Join Interrupt Enable + 3 + 3 + + + ACTIVITYSTATE + Activity State Status. + 4 + 5 + read-only + + + ENTAS0 + Unspecified + 0x0 + + + ENTAS1 + Unspecified + 0x1 + + + ENTAS2 + Unspecified + 0x2 + + + ENTAS3 + Unspecified + 0x3 + + + + + MRLUPDATED + MRL Updated Status. + 6 + 6 + + + MWLUPDATED + MWL Updated Status. + 7 + 7 + + + + + INTRSTATUS + Interrupt Status Register + 0x03C + read-write + 0x00000000 + 0x20 + + + TXTHLDSTS + Transmit Buffer Threshold Status + 0 + 0 + read-only + + + RXTHLDSTS + Receive Buffer Threshold Status. + 1 + 1 + read-only + + + IBITHLDSTS + IBI Buffer Threshold Status. + 2 + 2 + read-only + + + CMDQUEUEREADYSTS + Command Queue Ready. + 3 + 3 + read-only + + + RESPREADYSTS + Response Queue Ready Status. + 4 + 4 + read-only + + + TRANSFERABORTSTS + Transfer Abort Status. + 5 + 5 + + + CCCUPDATEDSTS + CCC Table Updated Status. + 6 + 6 + + + DYNADDRASSGNSTS + Dynamic Address Assigned Status. + 8 + 8 + + + TRANSFERERRSTS + Transfer Error Status. + 9 + 9 + + + DEFSLVSTS + Define Slave CCC Received Status. + 10 + 10 + + + READREQRECVSTS + Read Request Received. + 11 + 11 + + + IBIUPDATEDSTS + IBI status is updated. + 12 + 12 + + + BUSOWNERUPDATEDSTS + This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa. + 13 + 13 + + + BUSRESETDONESTS + Bus Reset Pattern Generation Done Status. + 15 + 15 + + + + + INTRSTATUSEN + Interrupt Status Enable Register. + 0x040 + read-write + 0x00000000 + 0x20 + + + TXTHLDSTSEN + Transmit Buffer Threshold Status Enable. + 0 + 0 + + + RXTHLDSTSEN + Receive Buffer Threshold Status Enable + 1 + 1 + + + IBITHLDSTSEN + IBI Buffer Threshold Status Enable. + 2 + 2 + + + CMDQUEUEREADYSTSEN + Command Queue Ready Status Enable + 3 + 3 + + + RESPREADYSTSEN + Response Queue Ready Status Enable + 4 + 4 + + + TRANSFERABORTSTSEN + Transfer Abort Status Enable. + 5 + 5 + + + CCCUPDATEDSTSEN + CCC Table Updated Status Enable. + 6 + 6 + + + DYNADDRASSGNSTSEN + Dynamic Address Assigned Status Enable + 8 + 8 + + + TRANSFERERRSTSEN + Transfer Error Status Enable + 9 + 9 + + + DEFSLVSTSEN + Define Slave CCC Received Status Enable + 10 + 10 + + + READREQRECVSTSEN + Read Request Received Status Enable + 11 + 11 + + + IBIUPDATEDSTSEN + IBI Updated Status Enable + 12 + 12 + + + BUSOWNERUPDATEDSTSEN + Bus owner Updated Status Enable + 13 + 13 + + + BUSRESETDONESTSEN + Bus Reset Pattern Generation Done Status Enable. + 15 + 15 + + + + + INTRSIGNALEN + Interrupt Signal Enable Register + 0x044 + read-write + 0x00000000 + 0x20 + + + TXTHLDSIGNALEN + Transmit Buffer Threshold Signal Enable + 0 + 0 + + + RXTHLDSIGNALEN + Receive Buffer Threshold Signal Enable + 1 + 1 + + + IBITHLDSIGNALEN + IBI Buffer Threshold Signal Enable + 2 + 2 + + + CMDQUEUEREADYSIGNALEN + Command Queue Ready Signal Enable + 3 + 3 + + + RESPREADYSIGNALEN + Response Queue Ready Signal Enable + 4 + 4 + + + TRANSFERABORTSIGNALEN + Transfer Abort Signal Enable + 5 + 5 + + + CCCUPDATEDSIGNALEN + CCC Table Updated Signal Enable + 6 + 6 + + + DYNADDRASSGNSIGNALEN + Dynamic Address Assigned Signal Enable + 8 + 8 + + + TRANSFERERRSIGNALEN + Transfer Error Signal Enable + 9 + 9 + + + DEFSLVSIGNALEN + Define Slave CCC Received Signal Enable + 10 + 10 + + + READREQRECVSIGNALEN + Read Request Received Signal Enable + 11 + 11 + + + IBIUPDATEDSIGNALEN + IBI Updated Signal Enable + 12 + 12 + + + BUSOWNERUPDATEDSIGNALEN + Bus owner Updated Signal Enable + 13 + 13 + + + BUSRESETDONESIGNALEN + Bus Reset Pattern Generation Done Signal Enable. + 15 + 15 + + + + + INTRFORCE + Interrupt Force Enable Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TXTHLDFORCEEN + Transmit Buffer Threshold Force Enable + 0 + 0 + write-only + + + RXTHLDFORCEEN + Receive Buffer Threshold Force Enable + 1 + 1 + write-only + + + IBITHLDFORCEEN + IBI Buffer Threshold Force Enable + 2 + 2 + write-only + + + CMDQUEUEREADYFORCEEN + Command Queue Ready Force Enable + 3 + 3 + write-only + + + RESPREADYFORCEEN + Response Queue Ready Force Enable + 4 + 4 + write-only + + + TRANSFERABORTFORCEEN + Transfer Abort Force Enable + 5 + 5 + write-only + + + CCCUPDATEDFORCEEN + CCC Table Updated Force Enable + 6 + 6 + write-only + + + DYNADDRASSGNFORCEEN + Dynamic Address Assigned Force Enable + 8 + 8 + write-only + + + TRANSFERERRFORCEEN + Transfer Error Force Enable + 9 + 9 + write-only + + + DEFSLVFORCEEN + Define Slave CCC Received Force Enable + 10 + 10 + write-only + + + READREQFORCEEN + Read Request Received Force Enable + 11 + 11 + write-only + + + IBIUPDATEDFORCEEN + IBI Updated Force Enable + 12 + 12 + write-only + + + BUSOWNERUPDATEDFORCEEN + Bus owner Updated Force Enable + 13 + 13 + write-only + + + BUSRESETDONEFORCEEN + Bus Reset Pattern Generation Done Force Enable. + 15 + 15 + write-only + + + + + QUEUESTATUSLEVEL + Queue Status Level Register. + 0x04C + read-write + 0x00000010 + 0x20 + + + CMDQUEUEEMPTYLOC + Command Queue Empty Locations. + 0 + 7 + read-only + + + RESPBUFBLR + Response Buffer Level Value. + 8 + 15 + read-only + + + IBIBUFBLR + IBI Buffer Level Value. + 16 + 23 + read-only + + + IBISTSCNT + IBI Buffer Status Count. + 24 + 28 + read-only + + + + + DATABUFFERSTATUSLEVEL + Data Buffer Status Level Register. + 0x050 + read-write + 0x00000040 + 0x20 + + + TXBUFEMPTYLOC + Transmit Buffer Empty Level Value. + 0 + 7 + read-only + + + RXBUFBLR + Receive Buffer Level Value. + 16 + 23 + read-only + + + + + PRESENTSTATEM + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Master). + 0x054 + read-write + 0x10000003 + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + IDLE + Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + BCCCWTRANSFER + Broadcast CCC Write Transfer. + 0x01 + + + DCCCWTRANSFER + Directed CCC Write Transfer. + 0x02 + + + DCCCRTRANSFER + Directed CCC Read Transfer. + 0x03 + + + ENTDAATRANSFER + ENTDAA Address Assignment Transfer. + 0x04 + + + SETDASATRANSFER + SETDASA Address Assignment Transfer. + 0x05 + + + SDRWTRANSFER + Private I3C SDR Write Transfer. + 0x06 + + + SDRRTRANSFER + Private I3C SDR Read Transfer. + 0x07 + + + SDRWTRANSFERI2C + Private I2C SDR Write Transfer. + 0x08 + + + SDRRTRANSFERI2C + Private I2C SDR Read Transfer. + 0x09 + + + TSWTRANSFER + Private HDR Ternary Symbol(TS) Write Transfer. + 0x0A + + + TSRTRANSFER + Private HDR Ternary Symbol(TS) Read Transfer. + 0x0B + + + DDRWTRANSFER + Private HDR Double-Data Rate(DDR) Write Transfer. + 0x0C + + + DDRRTRANSFER + Private HDR Double-Data Rate(DDR) Read Transfer. + 0x0D + + + IBITRANSFER + Servicing In-Band Interrupt Transfer. + 0x0E + + + HALT + Halt state. Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register. + 0x0F + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + IDLE + Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + START + START Generation State. + 0x01 + + + RESTART + RESTART Generation State. + 0x02 + + + STOP + STOP Genration State. + 0x03 + + + STARTH + START Hold Generation for the Slave Initiated START State. + 0x04 + + + BWADDRGEN + Broadcast Write Address Header(7h7E,W) Generation State. + 0x05 + + + BRADDRGEN + Broadcast Read Address Header(7h7E,R) Generation State. + 0x06 + + + DAA + Dynamic Address Assignment State. + 0x07 + + + ADDRGEN + Slave Address Generation State. + 0x08 + + + CCCBYTEGEN + CCC Byte Generation State. + 0x0B + + + HDRCMDGEN + HDR Command Generation State. + 0x0C + + + WTRANSFER + Write Data Transfer State. + 0x0D + + + RTRANSFER + Read Data Transfer State. + 0x0E + + + RIBI + In-Band Interrupt(SIR) Read Data State. + 0x0F + + + IBIAUTODISABLE + In-Band Interrupt Auto-Disable State + 0x10 + + + DDRCRCGEN + HDR-DDR CRC Data Generation/Receive State. + 0x11 + + + CLKEXTEND + Clock Extension State. + 0x12 + + + HALT + Halt State. + 0x13 + + + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + PRESENTSTATES + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Slave). + 0x054 + read-write + 0x10000003 + PRESENTSTATEM + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + SLAVEIDLE + Controller is in Idle state. + 0x00 + + + SLAVEHOTJOIN + Hot-Join transfer state. + 0x01 + + + SLAVEIBITRANSFER + IBI transfer state. + 0x02 + + + SLAVEWTRANSFER + Master write transfer ongoing. + 0x03 + + + SLAVERPREFETCH + Read data prefetch state. + 0x04 + + + SLAVERTRANSFER + Master read transfer ongoing. + 0x05 + + + SLAVEHALT + Slave controller in Halt State waiting for resume from application. + 0x06 + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + CCCDEVICESTATUS + Device Operating Status Register. + 0x058 + read-write + 0x00000000 + 0x20 + + + PENDINGINTR + Pending Interrupt + 0 + 3 + read-only + + + PROTOCOLERR + Protocol Error + 5 + 5 + read-only + + + ACTIVITYMODE + Activity Mode + 6 + 7 + read-only + + + UNDERFLOWERR + Underflow error + 8 + 8 + read-only + + + SLAVEBUSY + Slave Busy + 9 + 9 + read-only + + + OVERFLOWERR + Overflow Error + 10 + 10 + read-only + + + DATANOTREADY + Data not ready + 11 + 11 + read-only + + + BUFFERNOTAVAIL + Buffer not available + 12 + 12 + read-only + + + FRAMEERROR + Frame Error + 13 + 13 + read-only + + + + + DEVICEADDRTABLEPOINTER + Pointer for Device Address Table + 0x05C + read-write + 0x000A02C0 + 0x20 + + + PDEVADDRTABLESTARTADDR + Start Address of Device Address Table. + 0 + 15 + read-only + + + DEVADDRTABLEDEPTH + Depth of Device Address Table + 16 + 31 + read-only + + + + + DEVCHARTABLEPOINTER + Pointer for Device Characteristics Table + 0x060 + read-write + 0x00028200 + 0x20 + + + PDEVCHARTABLESTARTADDR + Start Address of Device Characteristics Table. + 0 + 11 + read-only + + + DEVCHARTABLEDEPTH + Depth of Device Characteristics Table + 12 + 18 + read-only + + + PRESENTDEVCHARTABLEINDX + Current index of Device Characteristics Table. + 19 + 22 + + + + + VENDORSPECIFICREGPOINTER + Pointer for Vendor Specific Registers. + 0x06C + read-write + 0x000000B0 + 0x20 + + + PVENDORREGSTARTADDR + Start Address of Vendor specific registers. + 0 + 15 + read-only + + + + + SLVMIPIIDVALUE + I3C MIPI Manufacturer ID Register. + 0x070 + read-write + 0x00000000 + 0x20 + + + SLVPROVIDSEL + Specifies the Provisional ID Type Selector (PID[32]). + 0 + 0 + + + SLVMIPIMFGID + Specifies the MIPI Manufacturer ID. + 1 + 15 + + + + + SLVPIDVALUE + I3C Normal Provisional ID Register. + 0x074 + read-write + 0x00000000 + 0x20 + + + SLVPIDDCR + Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). + 0 + 11 + + + SLVINSTID + This field is used to program the instance ID of the Slave. + 12 + 15 + + + SLVPARTID + Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) + 16 + 31 + + + + + SLVCHARCTRL + I3C Slave Characteristic Register. + 0x078 + read-write + 0x00070062 + 0x20 + + + MAXDATASPEEDLIMIT + Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). + 0 + 0 + + + IBIREQUESTCAPABLE + IBI Request Capable field in Bus Characteristic Register (BCR[1]). + 1 + 1 + read-only + + + IBIPAYLOAD + IBI Payload field in Bus Characteristic Register (BCR[2]). + 2 + 2 + read-only + + + OFFLINECAPABLE + Offline Capable field in Bus Characteristic Register (BCR[3]). + 3 + 3 + read-only + + + BRIDGEIDENTIFIER + Bridge Identifier field in Bus Characteristic Register (BCR[4]). + 4 + 4 + read-only + + + HDRCAPABLE + SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). + 5 + 5 + + + DEVICEROLE + Device Role field in Bus Characteristic Register (BCR[7:6]). + 6 + 7 + + + DCR + I3C Device Characteristic Value. + 8 + 15 + + + HDRCAP + I3C Device HDR Capability Register Value. + 16 + 23 + read-only + + + + + SLVMAXLEN + I3C Max Write/Read Length Register. + 0x07C + read-write + 0x00FF00FF + 0x20 + + + MWL + I3C Device Max Write Length + 0 + 15 + read-only + + + MRL + I3C Device Max Read Length. + 16 + 31 + read-only + + + + + MAXREADTURNAROUND + MXDS Maximum Read Turnaround Time. + 0x080 + read-write + 0x00000000 + 0x20 + + + MXDSMAXRDTURN + Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. + 0 + 23 + read-only + + + + + MAXDATASPEED + The values in this register are returned by the slave as GETACCMST CCC data. + 0x084 + read-write + 0x00000000 + 0x20 + + + MXDSMAXWRSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device + 0 + 2 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSMAXRDSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device + 8 + 10 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSCLKDATATURN + Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device + 16 + 18 + + + 8NS + 8ns + 0x0 + + + 9NS + 9ns + 0x1 + + + 10NS + 10ns + 0x2 + + + 11NS + 11ns + 0x3 + + + 12NS + 12ns + 0x4 + + + + + + + SLVINTRREQ + This register is used in slave mode of operation. + 0x08C + read-write + 0x00000000 + 0x20 + + + SIR + Slave Interrupt Request + 0 + 0 + + + SIRCTRL + Slave Interrupt Request Control + 1 + 2 + + + SEND + Send the Assigned Dynamic Address + 0x0 + + + + + MR + Master Request + 3 + 3 + + + IBISTS + IBI Completion Status + 8 + 9 + read-only + + + ACCEPTED + IBI accepted by the Master (ACK response received) + 0x1 + + + NOATTEMPT + IBI Not Attempted + 0x3 + + + + + + + SLVTSXSYMBLTIMING + TSP/TSL Symbol Timing Register + 0x090 + read-write + 0x0000003F + 0x20 + + + SLVTSXSYMBLCNT + TSP/TSL Symbol Count Value. + 0 + 5 + + + + + DEVICECTRLEXTENDED + Device Control Extended register. + 0x0B0 + read-write + 0x00000000 + 0x20 + + + DEVOPERATIONMODE + This bit is used to select the Device Operation Mode before the controller is enabled. + 0 + 1 + + + MASTER + Unspecified + 0x0 + + + SLAVE + Unspecified + 0x1 + + + + + REQMSTACKCTRL + In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current master. + 3 + 3 + + + ACK + ACK GETACCMST CCC + 0x0 + + + NACK + NACK GETACCMST CCC + 0x1 + + + + + + + SCLI3CODTIMING + SCL I3C Open Drain Timing Register + 0x0B4 + read-write + 0x000A0010 + 0x20 + + + I3CODLCNT + I3C Open Drain Low Count. + 0 + 7 + + + I3CODHCNT + I3C Open Drain High Count. + 16 + 23 + + + + + SCLI3CPPTIMING + SCL I3C Push Pull Timing Register + 0x0B8 + read-write + 0x000A000A + 0x20 + + + I3CPPLCNT + I3C Push Pull Low Count. + 0 + 7 + + + I3CPPHCNT + I3C Push Pull High Count. + 16 + 23 + + + + + SCLI2CFMTIMING + SCL I2C Fast Mode Timing Register + 0x0BC + read-write + 0x00100010 + 0x20 + + + I2CFMLCNT + I2C Fast Mode Low Count + 0 + 15 + + + I2CFMHCNT + I2C Fast Mode High Count + 16 + 31 + + + + + SCLI2CFMPTIMING + SCL I2C Fast Mode Plus Timing Register + 0x0C0 + read-write + 0x00100010 + 0x20 + + + I2CFMPLCNT + I2C Fast Mode Plus Low Count + 0 + 15 + + + I2CFMPHCNT + I2C Fast Mode Plus High Count + 16 + 23 + + + + + SCLEXTLCNTTIMING + SCL Extended Low Count Timing Register. + 0x0C8 + read-write + 0x20202020 + 0x20 + + + I3CEXTLCNT1 + I3C Extended Low Count Register 1 + 0 + 7 + + + I3CEXTLCNT2 + I3C Extended Low Count Register 2 + 8 + 15 + + + I3CEXTLCNT3 + I3C Extended Low Count Register 3 + 16 + 23 + + + I3CEXTLCNT4 + I3C Extended Low Count Register 4 + 24 + 31 + + + + + SCLEXTTERMNLCNTTIMING + SCL Termination Bit Low Count Timing Register + 0x0CC + read-write + 0x00030000 + 0x20 + + + I3CEXTTERMNLCNT + I3C Read Termination Bit Low count. + 0 + 3 + + + I3CTSSKEWCNT + I3C HDR Ternary Skew Count. + 16 + 19 + + + + + SDAHOLDSWITCHDLYTIMING + SDA Hold and Mode Switch Delay Timing Register + 0x0D0 + read-write + 0x00010000 + 0x20 + + + SDATXHOLD + This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with + 16 + 18 + + + + + BUSFREEAVAILTIMING + Bus Free and Available Timing Register + 0x0D4 + read-write + 0x00200020 + 0x20 + + + BUSFREETIME + This register field is used only in Master mode of operation + 0 + 15 + + + BUSAVAILABLETIME + This register field is used only in Slave mode of operation + 16 + 31 + + + + + BUSIDLETIMING + Bus Idle Timing Register + 0x0D8 + read-write + 0x00000020 + 0x20 + + + BUSIDLETIME + Bus Idle Count Value. + 0 + 19 + + + + + SCLLOWMSTEXTTIMEOUT + The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low Bus Reset Pattern. + 0x0DC + read-write + 0x003567E0 + 0x20 + + + SCLLOWMSTTIMEOUTCOUNT + This count defines the number of core clock periods to count for generation of the SCL Low Bus Reset Pattern. + 0 + 25 + + + + + I3CVERID + This register reflects the current release number of DWC_mipi_i3c + 0x0E0 + read-write + 0x3130302A + 0x20 + + + I3CVERID + Current release number + 0 + 31 + read-only + + + + + I3CVERTYPE + This register reflects the current release type of DWC_mipi_i3c. + 0x0E4 + read-write + 0x6C633033 + 0x20 + + + I3CVERTYPE + Current release type + 0 + 31 + read-only + + + + + QUEUESIZECAPABILITY + This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. + 0x0E8 + read-write + 0x00022355 + 0x20 + + + TXBUFSIZE + Transmit Data Buffer Size + 0 + 3 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + RXBUFSIZE + Receive Data Buffer Size + 4 + 7 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + CMDBUFSIZE + Command Queue Size + 8 + 11 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + RESPBUFSIZE + Response Queue Size + 12 + 15 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + IBIBUFSIZE + IBI Queue Size + 16 + 19 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + + + 10 + 0x010 + DEVCHARTABLE[%s] + Unspecified + DEVCHARTABLE + read-write + 0x200 + + LOC1 + Description cluster: Device Characteristic Table Location-1 of Device [n] + 0x0 + read-write + 0x00000000 + 0x20 + + + LSBPROVISIONALID + The LSB 32-bit value of Provisional-ID + 0 + 31 + read-only + + + + + LOC2 + Description cluster: Device Characteristic Table Location-2 of Device [n] + 0x4 + read-write + 0x00000000 + 0x20 + + + MSBPROVISIONALID + The MSB 16-bit value of Provisional-ID + 0 + 15 + read-only + + + + + LOC3 + Description cluster: Device Characteristic Table Location-3 of Device [n] + 0x8 + read-write + 0x00000000 + 0x20 + + + DCR + Device Characteristic Value + 0 + 7 + read-only + + + BCR + Bus Characteristic Value + 8 + 15 + read-only + + + + + LOC4 + Description cluster: Device Characteristic Table Location-4 of Device [n] + 0xC + read-write + 0x00000000 + 0x20 + + + DEVDYNAMICADDR + Device Dynamic Address assigned. + 0 + 7 + read-only + + + + + + 0x20 + 0x4 + SECDEVCHARTABLE[%s] + Description collection: Secondary Master Device Characteristic Table Location of Device [n] + 0x200 + read-write + 0x00000000 + 0x20 + + + DYNAMICADDR + The Dynamic Addr of Device [n] + 0 + 7 + read-only + + + DCRTYPE + The DCR TYPE of Device [n] + 8 + 15 + read-only + + + BCRTYPE + The BCR TYPE of Device [n] + 16 + 23 + read-only + + + STATICADDR + The Static Addr of Device [n] + 24 + 31 + read-only + + + + + 0xA + 0x4 + DEVADDRTABLELOC[%s] + Description collection: Device Address Table of Device [n] + 0x2C0 + read-write + 0x00000000 + 0x20 + + + DEVSTATICADDR + Device Static Address. + 0 + 6 + + + DEVDYNAMICADDR + Device Dynamic Address with parity. + 16 + 23 + + + DEVNACKRETRYCNT + This field is used to set the Device NACK Retry count for the particular device. + 29 + 30 + + + LEGACYI2CDEVICE + Legacy I2C device or not. + 31 + 31 + + + + + + DMA + Unspecified + I3CCORE_DMA + read-write + 0x900 + + CH0 + Unspecified + I3CCORE_DMA_CH0 + read-write + 0x000 + + SAR0 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR0 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL00 + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x02504821 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + DSTTRWIDTH + Destination Transfer Width. + 1 + 3 + + + DST_TR_WIDTH_0 + Unspecified + 0x0 + + + DST_TR_WIDTH_1 + Unspecified + 0x1 + + + DST_TR_WIDTH_2 + Unspecified + 0x2 + + + DST_TR_WIDTH_3 + Unspecified + 0x3 + + + DST_TR_WIDTH_4 + Unspecified + 0x4 + + + DST_TR_WIDTH_5 + Unspecified + 0x5 + + + DST_TR_WIDTH_6 + Unspecified + 0x6 + + + DST_TR_WIDTH_7 + Unspecified + 0x7 + + + + + RSVDSRCTRWIDTH + Reserved field - read-only + 4 + 6 + read-only + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + RSVDSRCGATHEREN + Reserved field - read-only + 17 + 17 + read-only + + + DSTSCATTEREN + Destination scatter enable. + 18 + 18 + + + DST_SCATTER_DISABLE + Unspecified + 0x0 + + + DST_SCATTER_ENABLE + Unspecified + 0x1 + + + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL01 + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG0L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E00 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG0H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + RSVD2CFG + Reserved field - read-only + 12 + 14 + read-only + + + RSVD3CFG + Reserved field - read-only + 15 + 31 + read-only + + + + + DSR0 + Destination Scatter register. + 0x050 + read-write + 0x00000000 + 0x20 + + + DSI + Destination Scatter Interval. + 0 + 19 + + + DSC + Destination Scatter Count. + 20 + 24 + + + + + + CH1 + Unspecified + I3CCORE_DMA_CH1 + read-write + 0x058 + + SAR1 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR1 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL1L + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x00F04805 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTTRWIDTH + Reserved field - read-only + 1 + 3 + read-only + + + SRCTRWIDTH + Source Transfer Width. + 4 + 6 + + + SRC_TR_WIDTH_0 + Unspecified + 0x0 + + + SRC_TR_WIDTH_1 + Unspecified + 0x1 + + + SRC_TR_WIDTH_2 + Unspecified + 0x2 + + + SRC_TR_WIDTH_3 + Unspecified + 0x3 + + + SRC_TR_WIDTH_4 + Unspecified + 0x4 + + + SRC_TR_WIDTH_5 + Unspecified + 0x5 + + + SRC_TR_WIDTH_6 + Unspecified + 0x6 + + + SRC_TR_WIDTH_7 + Unspecified + 0x7 + + + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + SRCGATHEREN + Source gather enable. + 17 + 17 + + + SRC_GATHER_DISABLE + Unspecified + 0x0 + + + SRC_GATHER_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTSCATTEREN + Reserved field - read-only + 18 + 18 + read-only + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL1H + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG1L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E20 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG1H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + + + SGR1 + Source Gather register + 0x048 + read-write + 0x00000000 + 0x20 + + + SGI + Source Gather Interval. + 0 + 19 + + + SGC + Source Gather Count. + 20 + 24 + + + + + + INT + Unspecified + I3CCORE_DMA_INT + read-write + 0x2C0 + + RAWTFR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x000 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntTfr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWBLOCK + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x008 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntBlock Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWSRCTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x010 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntSrcTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWDSTTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x018 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntDstTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWERR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x020 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntErr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSTFR + Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x028 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntTfr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSBLOCK + Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x030 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntBlock Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSSRCTRAN + Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x038 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntSrcTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSDSTTRAN + Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x040 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntDstTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSERR + Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x048 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntErr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + MASKTFR + The contents of the Raw Status register RawTfr is masked with the contents of the Mask register MaskTfr. + 0x050 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntTfr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKTFR + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKBLOCK + The contents of the Raw Status register RawBlock is masked with the contents of the Mask register MaskBlock. + 0x058 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntBlock Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKBLOCK + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKSRCTRAN + The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask register MaskSrcTran. + 0x060 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntSrcTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKSRCTRAN + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKDSTTRAN + The contents of the Raw Status register RawDstTran is masked with the contents of the Mask register MaskDstTran. + 0x068 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntDstTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKDSTTRAN + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKERR + The contents of the Raw Status register RawErr is masked with the contents of the Mask register MaskErr. + 0x070 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntErr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKERR + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CLEARTFR + Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x078 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntTfr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARBLOCK + Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x080 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntBlock Interrupt + 0 + 1 + write-only + + + + + CLEARSRCTRAN + Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x088 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntSrcTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARDSTTRAN + Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x090 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntDstTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARERR + Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x098 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntErr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + STATUSINT + The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TFR + OR of the contents of StatusTfr register + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + BLOCK + OR of the contents of StatusBlock register + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + SRCT + OR of the contents of StatusSrcTran + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DSTT + OR of the contents of StatusDstTran + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + ERR + OR of the contents of StatusErr + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + + SWHANDSHAKE + Unspecified + I3CCORE_DMA_SWHANDSHAKE + read-write + 0x368 + + REQSRCREG + A bit is assigned for each channel in this register. + 0x000 + read-write + 0x00000000 + 0x20 + + + SRCREQ + Source Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCREQWE + Source Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + REQDSTREG + A bit is assigned for each channel in this register. + 0x008 + read-write + 0x00000000 + 0x20 + + + DSTREQ + Destination Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTREQWE + Destination Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQSRCREG + A bit is assigned for each channel in this register. + 0x010 + read-write + 0x00000000 + 0x20 + + + SRCSGLREQ + Source Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCSGLREQWE + Source Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQDSTREG + A bit is assigned for each channel in this register. + 0x018 + read-write + 0x00000000 + 0x20 + + + DSTSGLREQ + Destination Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTSGLREQWE + Destination Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTSRCREG + A bit is assigned for each channel in this register. + 0x020 + read-write + 0x00000000 + 0x20 + + + LSTSRC + Source Last Transaction Request register + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTSRCREG + Reserved field- read-only + 2 + 7 + read-only + + + LSTSRCWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTDSTREG + A bit is assigned for each channel in this register. + 0x028 + read-write + 0x00000000 + 0x20 + + + LSTDST + Destination Last Transaction Request + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + LSTDSTWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + + MISC + Unspecified + I3CCORE_DMA_MISC + read-write + 0x398 + + DMACFGREG + This register is used to enable the DW_ahb_dmac, which must be done before any channel activity can begin. + 0x000 + read-write + 0x00000000 + 0x20 + + + DMAEN + DW_ahb_dmac Enable bit. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CHENREG + This is the DW_ahb_dmac Channel Enable Register. + 0x008 + read-write + 0x00000000 + 0x20 + + + CHEN + Channel Enable. + 0 + 1 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + RSVDCHENREG + Reserved field - read-only + 2 + 7 + read-only + + + CHENWE + Channel enable register + 8 + 9 + write-only + + + + + DMAIDREG + This is the DW_ahb_dmac ID register, which is a read-only register that reads back the coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. + 0x010 + read-write + 0x00000000 + 0x20 + + + DMAID + Hardcoded DW_ahb_dmac peripheral ID. + 0 + 31 + read-only + + + + + DMATESTREG + This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written, assuming the DW_ahb_dmac configuration has not optimized the same registers. + 0x018 + read-write + 0x00000000 + 0x20 + + + TESTSLVIF + DMA Test register + 0 + 0 + + + NORMAL_MODE + Unspecified + 0x0 + + + TEST_MODE + Unspecified + 0x1 + + + + + + + DMALPTIMEOUTREG + This register holds the timeout value of Low Power Counter. + 0x020 + read-write + 0x00000008 + 0x20 + + + DMALPTIMEOUT + This field holds timeout value of low power counter register. + 0 + 3 + + + + + DMACOMPPARAMS6L + DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about the component parameter settings for Channel 7. + 0x034 + read-write + 0x00000000 + 0x20 + + + CH7DTW + The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. + 0 + 2 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + DTW_8 + Unspecified + 0x1 + + + DTW_16 + Unspecified + 0x2 + + + DTW_32 + Unspecified + 0x3 + + + DTW_64 + Unspecified + 0x4 + + + DTW_128 + Unspecified + 0x5 + + + DTW_256 + Unspecified + 0x6 + + + + + CH7STW + The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. + 3 + 5 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + STW_8 + Unspecified + 0x1 + + + STW_16 + Unspecified + 0x2 + + + STW_32 + Unspecified + 0x3 + + + STW_64 + Unspecified + 0x4 + + + STW_128 + Unspecified + 0x5 + + + STW_256 + Unspecified + 0x6 + + + + + CH7STATDST + The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7STATSRC + The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7DSTSCAEN + The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7SRCGATEN + The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7LOCKEN + The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7MULTIBLKEN + The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7CTLWBEN + The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7HCLLP + The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH7FC + The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH7MAXMULTSIZE + The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH7DMS + The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7LMS + The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7SMS + The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7FIFODEPTH + The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5L + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x038 + read-write + 0x00000000 + 0x20 + + + CH6DTW + The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STW + The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STATDST + The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6STATSRC + The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6DSTSCAEN + The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6SRCGATEN + The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6LOCKEN + The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6MULTIBLKEN + The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6CTLWBEN + The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6HCLLP + The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH6FC + The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH6MAXMULTSIZE + The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH6DMS + The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6LMS + The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6SMS + The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6FIFODEPTH + The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + IFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5H + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x03C + read-write + 0x00000000 + 0x20 + + + CH5DTW + The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STW + The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STATDST + The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5STATSRC + The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5DSTSCAEN + The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5SRCGATEN + The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5LOCKEN + The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5MULTIBLKEN + The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5CTLWBEN + The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5HCLLP + The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH5FC + The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH5MAXMULTSIZE + The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH5DMS + The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5LMS + The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5SMS + The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5FIFODEPTH + The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4L + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x040 + read-write + 0x00000000 + 0x20 + + + CH4DTW + The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STW + The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STATDST + The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4STATSRC + The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4DSTSCAEN + The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4SRCGATEN + The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4LOCKEN + The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4MULTIBLKEN + The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4CTLWBEN + The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4HCLLP + The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH4FC + The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH4MAXMULTSIZE + The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH4DMS + The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4LMS + The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4SMS + The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4FIFODEPTH + The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4H + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x044 + read-write + 0x00000000 + 0x20 + + + CH3DTW + The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STW + The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STATDST + The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3STATSRC + The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3DSTSCAEN + The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3SRCGATEN + The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3LOCKEN + The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3MULTIBLKEN + The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3CTLWBEN + The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3HCLLP + The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH3FC + The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH3MAXMULTSIZE + The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH3DMS + The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3LMS + The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3SMS + The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3FIFODEPTH + The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3L + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x048 + read-write + 0x00000000 + 0x20 + + + CH2DTW + The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STW + The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STATDST + The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2STATSRC + The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2DSTSCAEN + The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2SRCGATEN + The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2LOCKEN + The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2MULTIBLKEN + The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2CTLWBEN + The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2HCLLP + The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH2FC + The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH2MAXMULTSIZE + The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH2DMS + The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH2LMS + The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2SMS + The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2FIFODEPTH + The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3H + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x04C + read-write + 0x1109A203 + 0x20 + + + CH1DTW + The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STW + The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STATDST + The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1STATSRC + The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1DSTSCAEN + The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1SRCGATEN + The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1LOCKEN + The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1MULTIBLKEN + The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1CTLWBEN + The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1HCLLP + The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH1FC + The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH1MAXMULTSIZE + The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH1DMS + The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1LMS + The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1SMS + The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1FIFODEPTH + The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2L + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x050 + read-write + 0x13016118 + 0x20 + + + CH0DTW + The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STW + The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STATDST + The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0STATSRC + The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0DSTSCAEN + The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0SRCGATEN + The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0LOCKEN + The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0MULTIBLKEN + The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0CTLWBEN + The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0HCLLP + The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH0FC + The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH0MAXMULTSIZE + The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH0DMS + The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0LMS + The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0SMS + The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0FIFODEPTH + The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2H + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x054 + read-write + 0x00000000 + 0x20 + + + CHOMULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant parameter. + 0 + 3 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH1MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant parameter. + 4 + 7 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH2MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant parameter. + 8 + 11 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH3MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant parameter. + 12 + 15 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH4MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant parameter. + 16 + 19 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH5MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant parameter. + 20 + 23 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH6MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant parameter. + 24 + 27 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH7MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant parameter. + 28 + 31 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + + + DMACOMPPARAMS1L + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x058 + read-write + 0x33333333 + 0x20 + + + CHOMAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant parameter. + 0 + 3 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH1MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant parameter. + 4 + 7 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH2MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant parameter. + 8 + 11 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH3MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant parameter. + 12 + 15 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH4MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant parameter. + 16 + 19 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH5MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant parameter. + 20 + 23 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH6MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant parameter. + 24 + 27 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH7MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant parameter. + 28 + 31 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + + + DMACOMPPARAMS1H + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x05C + read-write + 0x3120090C + 0x20 + + + BIGENDIAN + The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. + 0 + 0 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + INTRIO + The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. + 1 + 2 + read-only + + + ALL_INT + Unspecified + 0x0 + + + TYPE_INT + Unspecified + 0x1 + + + COMBINED_INT + Unspecified + 0x2 + + + + + MAXABRST + The value of this register is derived from the DMAH_MABRST coreConsultant parameter. + 3 + 3 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + RSVDDMACOMPPARAMS1 + Reserved field- read-only + 4 + 7 + read-only + + + NUMCHANNELS + The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. + 8 + 10 + read-only + + + NUM_CHANNEL_1 + Unspecified + 0x0 + + + NUM_CHANNEL_2 + Unspecified + 0x1 + + + NUM_CHANNEL_3 + Unspecified + 0x2 + + + NUM_CHANNEL_4 + Unspecified + 0x3 + + + NUM_CHANNEL_5 + Unspecified + 0x4 + + + NUM_CHANNEL_6 + Unspecified + 0x5 + + + NUM_CHANNEL_7 + Unspecified + 0x6 + + + NUM_CHANNEL_8 + Unspecified + 0x7 + + + + + NUMMASTERINT + The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. + 11 + 12 + read-only + + + NUM_MST_INTERFACE_1 + Unspecified + 0x0 + + + NUM_MST_INTERFACE_2 + Unspecified + 0x1 + + + NUM_MST_INTERFACE_3 + Unspecified + 0x2 + + + NUM_MST_INTERFACE_4 + Unspecified + 0x3 + + + + + SHDATAWIDTH + The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. + 13 + 14 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M4HDATAWIDTH + The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. + 15 + 16 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M3HDATAWIDTH + The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. + 17 + 18 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M2HDATAWIDTH + The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. + 19 + 20 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M1HDATAWIDTH + The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. + 21 + 22 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + NUMHSINT + The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. + 23 + 27 + read-only + + + HS_INTERFACE_0 + Unspecified + 0x00 + + + HS_INTERFACE_1 + Unspecified + 0x01 + + + HS_INTERFACE_2 + Unspecified + 0x02 + + + HS_INTERFACE_3 + Unspecified + 0x03 + + + HS_INTERFACE_4 + Unspecified + 0x04 + + + HS_INTERFACE_5 + Unspecified + 0x05 + + + HS_INTERFACE_6 + Unspecified + 0x06 + + + HS_INTERFACE_7 + Unspecified + 0x07 + + + HS_INTERFACE_8 + Unspecified + 0x08 + + + HS_INTERFACE_9 + Unspecified + 0x09 + + + HS_INTERFACE_a + Unspecified + 0x0A + + + HS_INTERFACE_b + Unspecified + 0x0B + + + HS_INTERFACE_c + Unspecified + 0x0C + + + HS_INTERFACE_d + Unspecified + 0x0D + + + HS_INTERFACE_e + Unspecified + 0x0E + + + HS_INTERFACE_f + Unspecified + 0x0F + + + HS_INTERFACE_10 + Unspecified + 0x10 + + + + + ADDENCODEDPARAMS + The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. + 28 + 28 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + STATICENDIANSELECT + The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant parameter. + 29 + 29 + read-only + + + + + DMACOMPSID0 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the component type. + 0x060 + read-write + 0x44571110 + 0x20 + + + DMACOMPTYPE + DMA Component Type Number = `h44571110. + 0 + 31 + read-only + + + + + DMACOMPSID1 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the version of the packaged component. + 0x064 + read-write + 0x3232322A + 0x20 + + + DMACOMPVERSION + DMA Component Version. + 0 + 31 + read-only + + + + + + + + + GLOBAL_I3CCORE121 + I3CCORE 1 + 0x2FBE1000 + + + + + GLOBAL_DMU120 + DMU 0 + 0x2FBEF800 + DMU + + + + 0 + 0x1000 + registers + + DMU + 0x20 + + + DMUCR + DMU Core Release + 0x3C0 + read-only + 0x00000000 + 0x20 + + + REL + Core Release + 1 + 1 + + + STEP + Step of Core Release + 2 + 2 + + + SUBSTEP + Sub-step of Core Release + 3 + 3 + + + YEAR + Time Stamp Year + 4 + 4 + + + MON + Time Stamp Month + 6 + 6 + + + DAY + Time Stamp Day + 8 + 8 + + + + + DMUI + DMU Internals + 0x3C4 + read-write + 0x00070000 + 0x20 + + + TXR + TX Service Request line of DMU + 0 + 0 + + + NotRequested + No TX DMA service requested + 0x0 + + + Requested + TX DMA Service requested + 0x1 + + + + + RX0R + RX0 Service Request line of DMU + 1 + 1 + + + NotRequested + No RX0 DMA service requested + 0x0 + + + Requested + RX0 DMA Service requested + 0x1 + + + + + RX1R + RX1 Service Request line of DMU + 2 + 2 + + + NotRequested + No RX1 DMA service requested + 0x0 + + + Requested + RX1 DMA Service requested + 0x1 + + + + + TXER + TX Event Service Request line of DMU + 3 + 3 + + + NotRequested + No TX Event DMA service requested + 0x0 + + + Requested + TX Event DMA Service requested + 0x1 + + + + + TFQPIP + TX FIFO/Queue Put Index Previous + 8 + 12 + + + ENA + DMU is enabled + 15 + 15 + + + Disabled + DMU is disabled + 0x0 + + + Enabled + DMU is enabled and can process DMA data + 0x1 + + + + + DEHS + Detect Element Handler State + 16 + 18 + + + DTX + Detect DMU Element Service + 20 + 20 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX0 + Detect DMU Element Service + 21 + 21 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX1 + Detect DMU Element Service + 22 + 22 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DTXE + Detect DMU Element Service + 23 + 23 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + EHS + Element Handler State + 24 + 26 + + + wait4cce + wait for bit MCAN:CCCR.CCE getting zero + 0x0 + + + wait4sa + wait for Start Address + 0x1 + + + wait4ta + wait for Trigger Address + 0x2 + + + transfer + wait for transfer of Element word + 0x3 + + + ack2mcan + acknowledge to MCAN + 0x4 + + + recovery + exception recovery + 0x5 + + + + + TX + Actual DMU Element Service + 28 + 28 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX0 + Actual DMU Element Service + 29 + 29 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX1 + Actual DMU Element Service + 30 + 30 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + TXE + Actual DMU Element Service + 31 + 31 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + + + DMUQC + DMU Queueing Counter + 0x3C8 + read-write + 0x00000000 + 0x20 + + + TXEEC + TX Element Enqueueing Counter + 0 + 7 + + + RX0EDC + RX0 Element Dequeueing Counter + 8 + 15 + + + RX1EDC + RX1 Element Dequeueing Counter + 16 + 23 + + + TXEEDC + TX Event Element Dequeueing Counter + 24 + 31 + + + + + DMUIR + DMU Interrupt Register + 0x3CC + read-write + 0x00000000 + 0x20 + + + TXENSA + TX Element Not Start Address + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal write access + 0x0 + + + Generated + Write to TX Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEIE + TX Element Illegal Enqueueing + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal enqueueing + 0x0 + + + Generated + Start of enqueueing without request detected, exception recovery started. + 0x1 + + + + + TXEIAS + TX Element Illegal Access Sequence + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEIDLC + TX Element Illegal DLC + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal DLC detected + 0x0 + + + Generated + DLC exceeds Tx Buffer element size of MCAN, exception recovery started. + 0x1 + + + + + TXEWATA + TX Element Write After Trigger Address + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write after Trigger Address + 0x0 + + + Generated + Write after Trigger address detected + 0x1 + + + + + TXEIR + TX Element Illegal Read + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read access + 0x0 + + + Generated + Illegal read access to DMU TX Element section detected, exception recovery started. + 0x1 + + + + + TXEE + A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx message enqueued + 0x0 + + + Generated + Tx message successfully enqueued + 0x1 + + + + + RX0ENSA + RX0 Element Not Start Address + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX0 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX0EID + RX0 Element Illegal Dequeueing + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX0EIAS + RX0 Element Illegal Access Sequence + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX0EIW + RX0 Element Illegal Write + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX0 Element detected, exception recovery started. + 0x1 + + + + + RX0ED + RX0 Element Dequeued + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX0EIO + RX0 Element Illegal Overwrite by timestamp + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + BEU + Bus Error Uncorrected + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + RX1ENSA + RX1 Element Not Start Address + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX1 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX1EID + RX1 Element Illegal Dequeueing + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX1EIAS + RX0 Element Illegal Access Sequence + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX1EIW + RX1 Element Illegal Write + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX1 Element detected, exception recovery started. + 0x1 + + + + + RX1ED + RX0 Element Dequeued + 20 + 20 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX1EIO + RX1 Element Illegal Overwrite by timestamp + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + TXEENSA + TX Event Element Not Start Address + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from TX Event Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEEID + TX Event Element Illegal Dequeueing + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started. + 0x1 + + + + + TXEEIAS + TX Event Element Illegal Access Sequence + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEEIW + TX Event Element Illegal Write + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU TX Event Element detected, exception recovery started. + 0x1 + + + + + TXEED + TX Event Element Dequeued + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No TX Event Element dequeued + 0x0 + + + Generated + TX Event Element successfully dequeued + 0x1 + + + + + DT + Debug Trigger + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Debug point not reached + 0x0 + + + Generated + Debug point reached + 0x1 + + + + + IAC + Illegal Access while in Configuration mode + 30 + 30 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Illegal Access while CCE mode + 0x0 + + + Generated + Illegal Access while CCE mode + 0x1 + + + + + + + DMUIE + DMU Interrupt Enable + 0x3D0 + read-write + 0x00000000 + 0x20 + + + TXENSAE + TX Element Not Start Address Enable + 0 + 0 + + + Disabled + Flag does not activate the interrupt line DMU + 0x0 + + + Enabled + the interrupt line DMU will be activated + 0x1 + + + + + + + DMUC + DMU Configuration + 0x3D4 + read-write + 0x00000000 + 0x20 + + + TTS + Transfer Timestamp + 0 + 0 + + + Disabled + No timestamp will be transferred via DMU Virtual Buffer + 0x0 + + + Enabled + Timestamp of message will be transferred from TSU via DMU Virtual Buffer + 0x1 + + + + + + + + + GLOBAL_MCAN120 + MCAN 0 + 0x2FBEF800 + GLOBAL_DMU120 + MCAN + + + + 0 + 0x1000 + registers + + MCAN + 0x20 + + + ENDN + Endian Register + 0x004 + read-only + 0x00000000 + 0x20 + + + ETV + Endianness Test Value + 0 + 31 + + + + + DBTP + Data Bit Timing and Prescaler Register + 0x00C + read-write + 0x00000000 + 0x20 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 3 + + + DTSEG2 + Data time segment after sample point + 4 + 7 + + + DTSEG1 + Data time segment before sample point + 8 + 12 + + + DBRP + Data Bit Rate Prescaler + 16 + 20 + + + TDC + Transmitter Delay Compensation + 23 + 23 + + + Disabled + Unspecified + 0x0 + + + Enabled + Unspecified + 0x1 + + + + + + + TEST + Test Register + 0x010 + read-write + 0x00000000 + 0x20 + + + LBCK + Loop Back Mode + 4 + 4 + + + Disabled + Loop Back Mode is disabled + 0x0 + + + Enabled + Loop Back Mode is enabled + 0x1 + + + + + TX + Control of Transmit Pin + 5 + 6 + + + CanCore + controlled by the CAN Core, updated at the end of the CAN bit time + 0x0 + + + Monitored + Sample Point can be monitored at pin m_can_tx + 0x1 + + + Dominant + Dominant (0) level at pin m_can_tx + 0x2 + + + Recessive + Recessive (1) at pin m_can_tx + 0x3 + + + + + RX + Receive Pin + 7 + 7 + + + Dominant + The CAN bus is dominant (m_can_rx = 0) + 0x0 + + + Recessive + The CAN bus is recessive (m_can_rx = '1') + 0x1 + + + + + TXBNP + Tx Buffer Number Prepared + 8 + 12 + + + PVAL + Prepared Valid + 13 + 13 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + TXBNS + Tx Buffer Number Started + 16 + 20 + + + SVAL + Started Valid + 21 + 21 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + + + RWD + RAM Watchdog + 0x014 + read-write + 0x00000000 + 0x20 + + + WDC + Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is + disabled. + 0 + 7 + + + WDV + Actual Message RAM Watchdog Counter Value. + 8 + 15 + + + + + CCCR + CC Control Register + 0x018 + read-write + 0x00000000 + 0x20 + + + INIT + Initialization + 0 + 0 + + + Normal + Normal Operation + 0x0 + + + Initialization + Initialization is started + 0x1 + + + + + CCE + Configuration Change Enable + 1 + 1 + + + Disabled + The CPU has no write access to the protected configuration registers + 0x0 + + + Enabled + The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + 0x1 + + + + + ASM + Restricted Operation Mode + 2 + 2 + + + Disabled + Normal CAN operation + 0x0 + + + Enabled + Restricted Operation Mode active + 0x1 + + + + + CSA + Clock Stop Acknowledge + 3 + 3 + + + Disabled + No clock stop acknowledged + 0x0 + + + Enabled + MCAN may be set in power down by stopping m_can_hclk and m_can_cclk + 0x1 + + + + + CSR + Clock Stop Request + 4 + 4 + + + Disabled + No clock stop is requested + 0x0 + + + Enabled + Clock stop requested. + 0x1 + + + + + MON + Bus Monitoring Mode + 5 + 5 + + + Disabled + Bus Monitoring Mode is disabled + 0x0 + + + Enabled + Bus Monitoring Mode is enabled + 0x1 + + + + + DAR + Disable Automatic Retransmission + 6 + 6 + + + Enabled + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + Disabled + Automatic retransmission disabled + 0x1 + + + + + TEST + Test Mode Enable + 7 + 7 + + + Disabled + Normal operation, register TEST holds reset values + 0x0 + + + Enabled + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD Operation Enable + 8 + 8 + + + Disabled + FD operation disabled + 0x0 + + + Enabled + FD operation enabled + 0x1 + + + + + BRSE + Bit Rate Switch Enable + 9 + 9 + + + Disabled + Bit rate switching for transmissions disabled + 0x0 + + + Enabled + Bit rate switching for transmissions enabled + 0x1 + + + + + WMM + Wide Message Marker + 11 + 11 + + + Disabled + 8-bit Message Marker used + 0x0 + + + Enabled + 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 0x1 + + + + + PXHD + Protocol Exception Handling Disable + 12 + 12 + + + Enabled + Protocol exception handling enabled + 0x0 + + + Disabled + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge Filtering during Bus Integration + 13 + 13 + + + Disabled + Edge filtering disabled + 0x0 + + + Enabled + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + Transmit Pause + 14 + 14 + + + Disabled + Transmit pause disabled + 0x0 + + + Enabled + Transmit pause enabled + 0x1 + + + + + NISO + Non ISO Operation + 15 + 15 + + + Disabled + CAN FD frame format according to ISO 11898-1:2015 + 0x0 + + + Enabled + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + NBTP + Nominal Bit Timing and Prescaler Register + 0x01C + read-write + 0x00000000 + 0x20 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 6 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 15 + + + NBRP + Nominal Bit Rate Prescaler + 16 + 24 + + + NSJW + Nominal (Re)Synchronization Jump Width + 25 + 31 + + + + + TSCC + Timestamp Counter Configuration + 0x020 + read-write + 0x00000000 + 0x20 + + + TSS + Timestamp Select + 0 + 1 + + + Zero + Timestamp counter value always 0x0000 + 0x0 + + + Increment + Timestamp counter value incremented according to TCP + 0x1 + + + External + External timestamp counter value used + 0x2 + + + Zero0 + Same as Zero + 0x3 + + + + + TCP + Timestamp Counter Prescaler + 16 + 19 + + + + + TSCV + Timestamp Counter Value + 0x024 + read-write + 0x00000000 + 0x20 + + + TSC + Timestamp Counter + 0 + 15 + + + + + TOCC + Timeout Counter Configuration + 0x028 + read-write + 0x00000000 + 0x20 + + + ETOC + Enable Timeout Counter + 0 + 0 + + + Disabled + Timeout Counter disabled + 0x0 + + + Enabled + Timeout Counter enabled + 0x1 + + + + + TOS + Timeout Select + 1 + 2 + + + Continuous + Continuous operation + 0x0 + + + TxEvent + Timeout controlled by Tx Event FIFO + 0x1 + + + RxFifo0 + Timeout controlled by Rx FIFO 0 + 0x2 + + + RxFifo1 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout Period + 16 + 31 + + + + + TOCV + Timeout Counter Value + 0x02C + read-write + 0x00000000 + 0x20 + + + TOC + Timeout Counter + 0 + 15 + + + + + ECR + Error Counter Register + 0x040 + read-write + 0x00000000 + 0x20 + + + TEC + Transmit Error Counter + 0 + 7 + + + REC + Receive Error Counter + 8 + 14 + + + RP + Receive Error Passive + 15 + 15 + + + Below + The Receive Error Counter is below the error passive level of 128 + 0x0 + + + Reached + The Receive Error Counter has reached the error passive level of 128 + 0x1 + + + + + CEL + CAN Error Logging + 16 + 23 + + + + + PSR + Protocol Status Register + 0x044 + read-write + 0x00000000 + 0x20 + + + LEC + Last Error Code + 0 + 2 + + + NoError + No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + StuffError + More than 5 equal bits in a sequence have occurred in a part of a received message + where this is not allowed. + 0x1 + + + FormError + A fixed format part of a received frame has the wrong format. + 0x2 + + + AckError + The message transmitted by the MCAN was not acknowledged by another node. + 0x3 + + + Bit1Error + During the transmission of a message (with the exception of the arbitration field), + the device wanted to send a recessive level (bit of logical value 1), but the monitored bus + value was dominant. + 0x4 + + + Bit0Error + During the transmission of a message (or acknowledge bit, or active error flag, or + overload flag), the device wanted to send a dominant level (data or identifier bit logical value + '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set + each time a sequence of 11 recessive bits has been monitored. This enables the CPU to + monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + dominant or continuously disturbed). + 0x5 + + + CRCError + The CRC check sum of a received message was incorrect. The CRC of an incoming + message does not match with the CRC calculated from the received data. + 0x6 + + + NoChange + Any read access to the Protocol Status Register re-initializes the LEC to '7'. + When the LEC shows the value '7', no CAN bus event was detected since the last CPU read + access to the Protocol Status Register. + 0x7 + + + + + ACT + Activity + 3 + 4 + + + Synchronizing + Node is synchronizing on CAN communication + 0x0 + + + Idle + Node is neither receiver nor tr ansmitter + 0x1 + + + Receiver + Node is operating as receiver + 0x2 + + + Transmitter + Node is operating as transmitter + 0x3 + + + + + EP + Error Passive + 5 + 5 + + + Active + The MCAN is in the Error_Active state. It normally takes part in bus communication and + sends an active error flag when an error has been detected + 0x0 + + + Passive + The MCAN is in the Error_Passive state + 0x1 + + + + + EW + Warning Status + 6 + 6 + + + Below + Both error counters are below the Error_Warning limit of 96 + 0x0 + + + Reached + At least one of error counter has reached the Error_Warning limit of 96 + 0x1 + + + + + BO + Bus_Off Status + 7 + 7 + + + On + The MCAN is not Bus_Off + 0x0 + + + Off + The MCAN is in Bus_Off state + 0x1 + + + + + DLEC + Data Phase Last Error Code + 8 + 10 + + + RESI + ESI flag of last received CAN FD Message + 11 + 11 + + + NotReceived + Last received CAN FD message did not ha ve its ESI flag set + 0x0 + + + Received + Last received CAN FD message had its ESI flag set + 0x1 + + + + + RBRS + BRS flag of last received CAN FD Message + 12 + 12 + + + NotReceived + Last received CAN FD message did not ha ve its BRS flag set + 0x0 + + + Received + Last received CAN FD message had its BRS flag set + 0x1 + + + + + RFDF + Received a CAN FD Message + 13 + 13 + + + NotReceived + Since this bit was reset by the CPU, no CAN FD message has been received + 0x0 + + + Received + Message in CAN FD format with FDF flag set has been received + 0x1 + + + + + PXE + Protocol Exception Event + 14 + 14 + + + NotTriggered + No protocol exception event occurred since last read access + 0x0 + + + Triggered + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter Delay Compensation Value + 16 + 22 + + + + + TDCR + Transmitter Delay Compensation Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TDCF + Transmitter Delay Compensation Filter Window Length + 0 + 6 + + + TDCO + Transmitter Delay Compensation SSP Offset + 8 + 14 + + + + + IR + Interrupt Register + 0x050 + read-write + 0x00000000 + 0x20 + + + RF0N + Rx FIFO 0 New Message + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 0 + 0x0 + + + Generated + New message written to Rx FIFO 0 + 0x1 + + + + + RF0W + Rx FIFO 0 Watermark Reached + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 fill level below watermark + 0x0 + + + Generated + Rx FIFO 0 fill level reached watermark + 0x1 + + + + + RF0F + Rx FIFO 0 Full + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 not full + 0x0 + + + Generated + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 0 message lost + 0x0 + + + Generated + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 0x1 + + + + + RF1N + Rx FIFO 1 New Message + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 1 + 0x0 + + + Generated + New message written to Rx FIFO 1 + 0x1 + + + + + RF1W + Rx FIFO 1 Watermark Reached + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 fill level below watermark + 0x0 + + + Generated + Rx FIFO 1 fill level reached watermark + 0x1 + + + + + RF1F + Rx FIFO 1 Full + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 not full + 0x0 + + + Generated + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 1 message lost + 0x0 + + + Generated + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + HPM + High Priority Message + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No high priority message received + 0x0 + + + Generated + High priority message received + 0x1 + + + + + TC + Transmission Completed + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission completed + 0x0 + + + Generated + Transmission completed + 0x1 + + + + + TCF + Transmission Cancellation Finished + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission cancellation finished + 0x0 + + + Generated + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO Empty + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx FIFO non-empty + 0x0 + + + Generated + Tx FIFO empty + 0x1 + + + + + TEFN + Tx Event FIFO New Entry + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO unchanged + 0x0 + + + Generated + Tx Handler wrote Tx Event FIFO element + 0x1 + + + + + TEFW + Tx Event FIFO Watermark Reached + 13 + 13 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO fill level below watermark + 0x0 + + + Generated + Tx Event FIFO fill level reached watermark + 0x1 + + + + + TEFF + Tx Event FIFO Full + 14 + 14 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO not full + 0x0 + + + Generated + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx Event FIFO element lost + 0x0 + + + Generated + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero + 0x1 + + + + + TSW + Timestamp Wraparound + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timestamp counter wrap-around + 0x0 + + + Generated + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM Access Failure + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM access failure occurred + 0x0 + + + Generated + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout Occurred + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timeout + 0x0 + + + Generated + Timeout reached + 0x1 + + + + + DRX + Message stored to Dedicated Rx Buffer + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx Buffer updated + 0x0 + + + Generated + At least one received message stored into an Rx Buff er + 0x1 + + + + + BEU + Bus Error Uncorrected + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + ELO + Error Logging Overflow + 22 + 22 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + CAN Error Logging Counter did not overflow + 0x0 + + + Generated + Overflow of CAN Error Logging Counter occurred + 0x1 + + + + + EP + Error Passive + 23 + 23 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Passive status unchanged + 0x0 + + + Generated + Error_Passive status changed + 0x1 + + + + + EW + Warning Status + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Warning status unchanged + 0x0 + + + Generated + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off Status + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Bus_Off status unchanged + 0x0 + + + Generated + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog Interrupt + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM Watchdog event occurred + 0x0 + + + Generated + Message RAM Watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in arbitration phase + 0x0 + + + Generated + Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 0x1 + + + + + PED + Protocol Error in Data Phase (Data Bit Time is used) + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in data phase + 0x0 + + + Generated + Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 0x1 + + + + + ARA + Access to Reserved Address + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No access to reserved address occurred + 0x0 + + + Generated + Access to reserved address occurred + 0x1 + + + + + + + IE + Interrupt Enable + 0x054 + read-write + 0x00000000 + 0x20 + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 0 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 2 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 3 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 4 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 5 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 6 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 7 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + HPME + High Priority Message Interrupt Enable + 8 + 8 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCE + Transmission Completed Interrupt Enable + 9 + 9 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 10 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 11 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 12 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 13 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 14 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 15 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 16 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 17 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 18 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 19 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BEUE + Bus Error Uncorrected Interrupt Enable + 21 + 21 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 22 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EPE + Error Passive Interrupt Enable + 23 + 23 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EWE + Warning Status Interrupt Enable + 24 + 24 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BOE + Bus_Off Status Interrupt Enable + 25 + 25 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + WDIE + Watchdog Interrupt Enable + 26 + 26 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 27 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEDE + Protocol Error in Data Phase Enable + 28 + 28 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ARAE + Access to Reserved Address Enable + 29 + 29 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + + + ILS + Interrupt Line Select + 0x058 + read-write + 0x00000000 + 0x20 + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 0 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 2 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 3 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 4 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 5 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 6 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 7 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + HPML + High Priority Message Interrupt Line + 8 + 8 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCL + Transmission Completed Interrupt Line + 9 + 9 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 10 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 11 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 12 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 13 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 14 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 15 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 16 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 17 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TOOL + Timeout Occurred Interrupt Line + 18 + 18 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 19 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BEUL + Bus Error Uncorrected Interrupt Line + 21 + 21 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 22 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EPL + Error Passive Interrupt Line + 23 + 23 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EWL + Warning Status Interrupt Line + 24 + 24 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BOL + Bus_Off Status Interrupt Line + 25 + 25 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + WDIL + Watchdog Interrupt Line + 26 + 26 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 27 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEDL + Protocol Error in Data Phase Line + 28 + 28 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ARAL + Access to Reserved Address Line + 29 + 29 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + + + ILE + Interrupt Line Enable + 0x05C + read-write + 0x00000000 + 0x20 + + + EINT0 + Enable Interrupt Line 0 + 0 + 0 + + + Disable + Interrupt line CORE0 disabled. + 0x0 + + + Enable + Interrupt line CORE0 enabled. + 0x1 + + + + + EINT1 + Enable Interrupt Line 1 + 1 + 1 + + + Disable + Interrupt line CORE1 disabled. + 0x0 + + + Enable + Interrupt line CORE1 enabled. + 0x1 + + + + + + + GFC + Global Filter Configuration + 0x080 + read-write + 0x00000000 + 0x20 + + + RRFE + Reject Remote Frames Extended + 0 + 0 + + + Filter + Filter remote frames with 29-bit extended IDs. + 0x0 + + + Reject + Reject all remote frames with 29-bit extended IDs. + 0x1 + + + + + RRFS + Reject Remote Frames Standard + 1 + 1 + + + Filter + Filter remote frames with 11-bit standard IDs. + 0x0 + + + Reject + Reject all remote frames with 11-bit standard IDs. + 0x1 + + + + + ANFE + Accept Non-matching Frames Extended + 2 + 3 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + ANFS + 4 + 5 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + + + SIDFC + Standard ID Filter Configuration + 0x084 + read-write + 0x00000000 + 0x20 + + + FLSSA + Filter List Standard Start Address + 2 + 15 + + + LSS + List Size Standard + 16 + 23 + + + + + XIDFC + Extended ID Filter Configuration + 0x088 + read-write + 0x00000000 + 0x20 + + + FLESA + Filter List Extended Start Address + 2 + 15 + + + LSE + List Size Extended + 16 + 22 + + + + + XIDAM + Extended ID AND Mask + 0x090 + read-write + 0x00000000 + 0x20 + + + EIDM + Extended ID Mask + 0 + 28 + + + + + HPMS + High Priority Message Status + 0x094 + read-only + 0x00000000 + 0x20 + + + BIDX + Buffer Index + 0 + 5 + + + MSI + Message Storage Indicator + 6 + 7 + + + NotSelected + No FIFO selected. + 0x0 + + + Lost + FIFO message lost. + 0x1 + + + Stored0 + Message stored in FIFO 0. + 0x2 + + + Stored1 + Message stored in FIFO 1. + 0x3 + + + + + FIDX + Filter Index + 8 + 14 + + + FLST + Filter List + 15 + 15 + + + Standard + Standard Filter List. + 0x0 + + + Extended + Extended Filter List. + 0x1 + + + + + + + NDAT1 + New Data 1 + 0x098 + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + NDAT2 + New Data 2 + 0x09C + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + RXF0C + Rx FIFO 0 Configuration + 0x0A0 + read-write + 0x00000000 + 0x20 + + + F0SA + Rx FIFO 0 Start Address + 2 + 15 + + + F0S + Rx FIFO 0 Size + 16 + 22 + + + F0WM + Rx FIFO 0 Watermark + 24 + 30 + + + F0OM + FIFO 0 Operation Mode + 31 + 31 + + + Blocking + FIFO 0 blocking mode. + 0x0 + + + Overwrite + FIFO 0 overwrite mode. + 0x1 + + + + + + + RXF0S + Rx FIFO 0 Status + 0x0A4 + read-only + 0x00000000 + 0x20 + + + F0FL + Rx FIFO 0 Fill Leve + 0 + 6 + + + F0GI + Rx FIFO 0 Get Index + 8 + 13 + + + F0PI + Rx FIFO 0 Put Index + 16 + 21 + + + F0F + Rx FIFO 0 Full + 24 + 24 + + + NotFull + Rx FIFO 0 not full. + 0x0 + + + Full + Rx FIFO 0 full. + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 25 + 25 + + + NotLost + No Rx FIFO 0 message lost. + 0x0 + + + Lost + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + 0x1 + + + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0x0A8 + read-write + 0x00000000 + 0x20 + + + F0AI + Rx FIFO 0 Acknowledge Index + 0 + 5 + + + + + RXBC + Rx Buffer Configuration + 0x0AC + read-write + 0x00000000 + 0x20 + + + RBSA + Rx Buffer Start Address + 2 + 15 + + + + + RXF1C + Rx FIFO 1 Configuration + 0x0B0 + read-write + 0x00000000 + 0x20 + + + F1SA + Rx FIFO 1 Start Address + 2 + 15 + + + F1S + Rx FIFO 1 Size + 16 + 22 + + + F1WM + Rx FIFO 1 Watermark + 24 + 30 + + + F1OM + FIFO 1 Operation Mode + 31 + 31 + + + BlockingMode + FIFO 1 blocking mode + 0x0 + + + OwerwriteMode + FIFO 1 overwrite mode + 0x1 + + + + + + + RXF1S + Rx FIFO 1 Status + 0x0B4 + read-only + 0x00000000 + 0x20 + + + F1FL + Rx FIFO 1 Fill Level + 0 + 6 + + + F1GI + Rx FIFO 1 Get Index + 8 + 13 + + + F1PI + Rx FIFO 1 Put Index + 16 + 21 + + + F1F + Rx FIFO 1 Full + 24 + 24 + + + NotFull + Rx FIFO 1 not full + 0x0 + + + Full + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 25 + 25 + + + NoMessageLost + No Rx FIFO 1 message lost + 0x0 + + + MessageLost + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + DMS + Debug Message Status + 30 + 31 + + + Idle + Idle state, wait for reception of debug messages, DMA request is cleared + 0x0 + + + ReceivedMesA + Debug message A received + 0x1 + + + ReceivedMesAB + Debug messages A, B received + 0x2 + + + ReceivedMesABC + Debug messages A, B, C received, DMA request is set + 0x3 + + + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0x0B8 + read-write + 0x00000000 + 0x20 + + + F1AI + Rx FIFO 1 Acknowledge Index + 0 + 5 + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0x0BC + read-write + 0x00000000 + 0x20 + + + F0DS + Rx FIFO 0 Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + F1DS + Rx FIFO 1 Data Field Size + 4 + 6 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + RBDS + Rx Buffer Data Field Size + 8 + 10 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBC + Tx Buffer Configuration + 0x0C0 + read-write + 0x00000000 + 0x20 + + + TBSA + Tx Buffers Start Address + 2 + 15 + + + NDTB + Number of Dedicated Transmit Buffers + 16 + 21 + + + TFQS + Transmit FIFO/Queue Size + 24 + 29 + + + TFQM + Tx FIFO/Queue Mode + 30 + 30 + + + TxFIFO + Tx FIFO operation + 0x0 + + + TxQueue + Tx Queue operation + 0x1 + + + + + + + TXFQS + Tx FIFO/Queue Status + 0x0C4 + read-only + 0x00000000 + 0x20 + + + TFFL + Tx FIFO Free Level + 0 + 5 + + + TFGI + Tx FIFO Get Index + 8 + 12 + + + TFQPI + Tx FIFO/Queue Put Index + 16 + 20 + + + TFQF + Tx FIFO/Queue Full + 21 + 21 + + + NotFull + Tx FIFO/Queue not full + 0x0 + + + Full + Tx FIFO/Queue full + 0x1 + + + + + + + TXESC + Tx Buffer Element Size Configuration + 0x0C8 + read-write + 0x00000000 + 0x20 + + + TBDS + Tx Buffer Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBRP + Tx Buffer Request Pending + 0x0CC + read-only + 0x00000000 + 0x20 + + + TRP + Transmission Request Pending + 0 + 31 + + + NoRequest + No transmission request pending + 0x00000000 + + + Request + Transmission request pending + 0x00000001 + + + + + + + TXBAR + Tx Buffer Add Request + 0x0D0 + read-write + 0x00000000 + 0x20 + + + AR + Add Request + 0 + 31 + + + NoRequest + No transmission request added + 0x00000000 + + + Request + Transmission requested added + 0x00000001 + + + + + + + TXBCR + Tx Buffer Cancellation Request + 0x0D4 + read-write + 0x00000000 + 0x20 + + + CR + Cancellation Request + 0 + 31 + + + NoCancellation + No cancellation pending + 0x00000000 + + + Cancellation + Cancellation pending + 0x00000001 + + + + + + + TXBTO + Tx Buffer Transmission Occurred + 0x0D8 + read-only + 0x00000000 + 0x20 + + + TO + Transmission Occurred + 0 + 31 + + + NoTransmittion + No transmission occurred + 0x00000000 + + + Transmittion + Transmission occurred + 0x00000001 + + + + + + + TXBCF + Tx Buffer Cancellation Finished + 0x0DC + read-only + 0x00000000 + 0x20 + + + CF + Cancellation Finished + 0 + 31 + + + NoCancellation + No transmit buffer cancellation + 0x00000000 + + + CancellationFinished + Transmit buffer cancellation finished + 0x00000001 + + + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0x0E0 + read-write + 0x00000000 + 0x20 + + + TIE + Transmission Interrupt Enable + 0 + 31 + + + Disable + Transmission interrupt disabled + 0x00000000 + + + Enable + Transmission interrupt enable + 0x00000001 + + + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0x0E4 + read-write + 0x00000000 + 0x20 + + + CFIE + Cancellation Finished Interrupt Enable + 0 + 31 + + + Disable + Cancellation finished interrupt disabled + 0x00000000 + + + Enable + Cancellation finished interrupt enabled + 0x00000001 + + + + + + + TXEFC + Tx Event FIFO Configuration + 0x0F0 + read-write + 0x00000000 + 0x20 + + + EFSA + Event FIFO Start Address + 2 + 15 + + + EFS + Event FIFO Size + 16 + 21 + + + EFWM + Event FIFO Watermark + 24 + 29 + + + + + TXEFS + Tx Event FIFO Status + 0x0F4 + read-only + 0x00000000 + 0x20 + + + EFFL + Event FIFO Fill Level + 0 + 5 + + + EFGI + Event FIFO Get Index + 8 + 12 + + + EFPI + Event FIFO Put Index + 16 + 20 + + + EFF + Event FIFO Full + 24 + 24 + + + NotFull + Tx Event FIFO not full + 0x0 + + + Full + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 25 + 25 + + + NotLost + No Tx Event FIFO element lost + 0x0 + + + Lost + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero. + 0x1 + + + + + + + TXEFA + Tx Event FIFO Acknowledge + 0x0F8 + read-write + 0x00000000 + 0x20 + + + EFAI + Event FIFO Acknowledge Index + 0 + 4 + + + + + + + GLOBAL_DMU121 + DMU 1 + 0x2FBF7800 + + + + + GLOBAL_MCAN121 + MCAN 1 + 0x2FBF7800 + GLOBAL_DMU121 + + + + + GLOBAL_STMDATA + System Trace Macrocell data buffer + 0xA0000000 + + + + + 0 + 0x10000000 + registers + + STMDATA + 0x20 + + + 16 + 0x1000000 + DOMAIN[%s] + Unspecified + STMDATA_DOMAIN + read-write + 0x000 + + 0x1000000 + 0x1 + DATA[%s] + Description collection: STM extended stimulus port data buffer area for domain n. NonSecure writes to this region generates trace packets with id n+96. Secure writes to this region generates trace packets with id n+32. + 0x000 + read-write + 0x00 + uint8_t + 0x8 + + + + + + + GLOBAL_TDDCONF + TDDCONF + 0xBF001000 + + + + 0 + 0x1000 + registers + + TDDCONF + 0x20 + + + SYSPWRUPREQ + System power-up request + 0x400 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + DBGPWRUPREQ + Debug power-up request + 0x404 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + TRACEPORTSPEED + Trace port trace clock speed + 0x408 + read-write + 0x00000000 + 0x20 + + + SPEED + Trace clock speed + 0 + 1 + + + Speed100MHz + Speed 100MHz + 0x0 + + + Speed50MHz + Speed 50MHz + 0x1 + + + Speed25MHz + Speed 25MHz + 0x2 + + + Speed12500KHz + Speed 12.5MHz + 0x3 + + + + + + + DEBUGPOWERREQSTATUS + Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests + 0x40C + read-only + 0x00000000 + 0x20 + + + SYSPWRUPREQUESTED + System powerup request status + 0 + 0 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + DBGPWRUPREQUESTED + Debug domain powerup request status + 1 + 1 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + + + + + GLOBAL_STM + System Trace Macrocell + 0xBF042000 + + + + 0 + 0x1000 + registers + + STM + 0x20 + + + DMACTLR + Controls the DMA transfer request mechanism. + 0xC10 + read-write + 0x00000000 + 0x20 + + + SENS + Determines the sensitivity of the DMA request to the current buffer level in the STM + 2 + 3 + + + LT25 + Buffer is &lt;25 percent full. + 0x0 + + + LT50 + Buffer is &lt;50 percent full. + 0x1 + + + LT75 + Buffer is &lt;75 percent full. + 0x2 + + + LT100 + Buffer is &lt;100 percent full. + 0x3 + + + + + + + HEMASTR + Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. + 0xDF4 + read-only + 0x00000000 + 0x20 + + + MASTER + The STPv2 master number that hardware event traces should be associated with. + 0 + 16 + + + + + HEFEAT1R + Indicates the features of the STM. + 0xDF8 + read-only + 0x00000000 + 0x20 + + + HETER + STMHETER support + 0 + 0 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEERR + Hardware event error detection support + 2 + 2 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEMASTR + STMHEMASTR support + 3 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NUMHE + The number of hardware events supported by the STM + 15 + 23 + + + + + HEIDR + Indicates the features of hardware event tracing in the STM. + 0xDFC + read-only + 0x00000000 + 0x20 + + + CLASS + The CLASS field identifies the programmers model + 0 + 3 + + + HardwareEventControl + Hardware Event Control programmers model + 0x1 + + + + + CLASSREV + The CLASSREV field identifies the revision of the programmers model + 4 + 7 + + + VENDSPEC + The VENDSPEC field identifies any vendor specific modifications or mappings + 8 + 11 + + + + + TCSR + Controls the STM settings. + 0xE80 + read-write + 0x00000000 + 0x20 + + + EN + Global STM enable + 0 + 0 + + + Disabled + The STM is disabled. + 0x0 + + + Enabled + The STM is enabled. + 0x1 + + + + + TSEN + Enable or disable timestamp bundling. + 1 + 1 + + + Disabled + Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected. + 0x0 + + + Enabled + Time stamps are enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2. + 0x1 + + + + + SYNCEN + STMSYNCR is implemented so this value is Read As One. + 2 + 2 + + + Disabled + The STM Sync feature is disabled. + 0x0 + + + Enabled + The STM Sync feature is enabled. + 0x1 + + + + + COMPEN + Compression Enable for Stimulus Ports. + 5 + 5 + + + Disabled + Compression disabled, data transfers are transmitted at the size of the transaction. + 0x0 + + + Enabled + Compression enabled, data transfers are compressed to save bandwidth. + 0x1 + + + + + TRACEID + ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. + 16 + 22 + + + BUSY + STM is busy, for example the STM trace FIFO is not empty. + 23 + 23 + + + Ready + STM is not busy. + 0x0 + + + Busy + STM is busy. + 0x1 + + + + + + + AUXCR + Used for implementation defined STM controls. + 0xE94 + read-write + 0x00000000 + 0x20 + + + FIFOAF + FIFO Auto-flush. + 0 + 0 + + + Disabled + Auto-flush is disabled. + 0x0 + + + Enabled + Auto-flush is enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized. + 0x1 + + + + + ASYNCPE + Is ASYNC priority higher than trace? + 1 + 1 + + + Lower + ASYNC priority is always lower than trace. + 0x0 + + + Escalate + ASYNC priority escalates on second synchronization request. + 0x1 + + + + + PRIORINVDIS + Controls arbitration between AXI and HW during flush. + 2 + 2 + + + Enabled + Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done. + 0x0 + + + Disabled + Priority inversion disabled, AXI always has priority over HW. + 0x1 + + + + + CLKON + Provides override control for architectural clock gate enable. + 3 + 3 + + + Disabled + No override, clock gate is controlled by the state of STM. + 0x0 + + + Enabled + Override, clock is enabled. + 0x1 + + + + + AFREADYHIGH + Provides override control for the AFREADY output + 4 + 4 + + + Disabled + No override, AFREADY is controlled by the state of STM. + 0x0 + + + Enabled + Override, AFREADY is driven HIGH. + 0x1 + + + + + + + SPFEAT1R + Indicates the features of the STM. + 0xEA0 + read-write + 0x00000000 + 0x20 + + + PROT + Indicates the implemented STM protocol. + 0 + 3 + + + STPV2 + STM implements the STPV2 protocol. + 0x1 + + + + + TS + Timestamp support. + 4 + 5 + + + Absolute + Absolute timestamps implemented. + 0x1 + + + + + TSFREQ + Timestamp frequency indication configuration. + 6 + 6 + + + NotImplemented + STMTSFREQR is read-only. + 0x0 + + + Implemented + STMTSFREQR is read-write. + 0x1 + + + + + FORCETS + Timestamp force configuration. + 7 + 7 + + + NotImplemented + STMTSSTIMR bit 0 is read-only. + 0x0 + + + Implemented + STMTSSTIMR bit 0 is read-write. + 0x1 + + + + + TRACEBUS + Trace bus support. + 10 + 13 + + + TRIGCTL + Trigger control support. + 14 + 15 + + + TSPRESCALE + Timestamp prescale support + 16 + 17 + + + NotImplemented + Timestamp prescale is not implemented. + 0x0 + + + Implemented + Timestamp prescale is implemented. + 0x1 + + + + + HWTEN + STMTCSR.HWTEN support + 18 + 19 + + + NotImplemented + STMTCSR.HWTEN is not implemented + 0x1 + + + + + SYNCEN + STMTCSR.SYNCEN support + 20 + 21 + + + ReadAsOne + STMTCSR.SYNCEN implemented but always reads as b1 + 0x2 + + + + + SWOEN + STMTCSR.SWOEN support + 22 + 23 + + + NotImplemented + STMTCSR.SWOEN not implemented + 0x1 + + + + + + + SPFEAT2R + Indicates the features of the STM. + 0xEA4 + read-write + 0x00000000 + 0x20 + + + SPTER + STMSPTER support. + 0 + 1 + + + Implemented + STMSPTER is implemented. + 0x2 + + + + + SPER + STMSPER presence. + 2 + 2 + + + Implemented + STMSPER is implemented. + 0x0 + + + NotImplemented + STMSPER is not implemented. + 0x1 + + + + + SPCOMP + Data compression on stimulus ports support. + 4 + 5 + + + Programmable + Data compression support is programmable. STMTCSR.COMPEN is implemented. + 0x3 + + + + + SPOVERRIDE + Timestamp force configuration. + 6 + 6 + + + NotImplemented + STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. + 0x0 + + + Implemented + STMSPOVERRIDER and STMSPMOVERRIDER is implemented. + 0x1 + + + + + PRIVMASK + STMPRIVMASKR support. + 7 + 8 + + + NotImplemented + STMPRIVMASKR is not implemented. + 0x1 + + + + + SPTRTYPE + Stimulus port transaction type support. + 9 + 10 + + + InvariantAndGuaranteed + Both invariant timing and guaranteed transactions are supported. + 0x2 + + + + + DSIZE + Fundamental data size. + 12 + 15 + + + Bits32 + 32-bit data. + 0x0 + + + + + SPTYPE + Stimulus port type support + 18 + 19 + + + OnlyExtended + Only extended stimulus ports are implemented. + 0x1 + + + + + + + SPFEAT3R + Indicates the features of the STM. + 0xEA8 + read-write + 0x00000000 + 0x20 + + + NUMMAST + The number of stimulus ports masters implemented, minus 1. + 0 + 6 + + + Masters128 + Example: 128 masters implemented. + 0x3F + + + + + + + ITTRIGGER + Integration Test for Cross-Trigger Outputs Register. + 0xEE8 + write-only + 0x00000000 + 0x20 + + + TRIGOUTSPTE_W + Sets the value of the TRIGOUTSPTE output in integration mode. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTSW_W + Sets the value of the TRIGOUTSW output in integration mode. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTHETE_W + Sets the value of the TRIGOUTHETE output in integration mode. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ASYNCOUT_W + Sets the value of the ASYNCOUT output in integration mode. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBDATA0 + Controls the value of the ATDATAM output in integration mode. + 0xEEC + write-only + 0x00000000 + 0x20 + + + ATDATAM0_W + Sets the value of the ATDATAM[0]. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM7_W + Sets the value of the ATDATAM[7] output. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM15_W + Sets the value of the ATDATAM[15]. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM23_W + Sets the value of the ATDATAM[23]. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM31_W + Sets the value of the ATDATAM[31]. + 4 + 4 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBCTR2 + Controls the value of the ATDATAM output in integration mode. + 0xEF0 + write-only + 0x00000000 + 0x20 + + + ATREADYM_R + Reads the value of the ATREADYM input. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFVALIDM_R + Reads the value of the AFVALIDM input. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBID + Controls the value of the ATIDM output in integration mode. + 0xEF4 + write-only + 0x00000000 + 0x20 + + + ATIDM_W_0 + Sets the value of pin 0 of the ATIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_1 + Sets the value of pin 1 of the ATIDM output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_2 + Sets the value of pin 2 of the ATIDM output. + 2 + 2 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_3 + Sets the value of pin 3 of the ATIDM output. + 3 + 3 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_4 + Sets the value of pin 4 of the ATIDM output. + 4 + 4 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_5 + Sets the value of pin 5 of the ATIDM output. + 5 + 5 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_6 + Sets the value of pin 6 of the ATIDM output. + 6 + 6 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBCTR0 + Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. + 0xEF8 + write-only + 0x00000000 + 0x20 + + + ATVALIDM_W + Sets the value of the ATVALIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFREADYM_W + Sets the value of the AFREADYM_W output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_0 + Sets the value of pin 0 of the ATBYTESM output. + 8 + 8 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_1 + Sets the value of pin 1 of the ATBYTESM output. + 9 + 9 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the STM. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + NUMSP + This value indicates the number of stimulus ports implemented. + 0 + 16 + + + Max + Maximum 65,536 stimulus ports can be implemented. + 0x10000 + + + + + + + DEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + StimulusTrace + Peripheral is a stimulus trace source. + 0x6 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_TPIU + Trace Port Interface Unit + 0xBF043000 + + + + 0 + 0x1000 + registers + + TPIU + 0x20 + + + SUPPORTEDPORTSIZES + Each bit location is a single port size that is supported on the device. + 0x000 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates whether the TPIU supports port size of 1-bit. + 0 + 0 + + + NotSupported + Port size 1 is not supported. + 0x0 + + + Supported + Port size 1 is supported. + 0x1 + + + + + PORT_SIZE_2 + Indicates whether the TPIU supports port size of 2-bit. + 1 + 1 + + + NotSupported + Port size 2 is not supported. + 0x0 + + + Supported + Port size 2 is supported. + 0x1 + + + + + PORT_SIZE_3 + Indicates whether the TPIU supports port size of 3-bit. + 2 + 2 + + + NotSupported + Port size 3 is not supported. + 0x0 + + + Supported + Port size 3 is supported. + 0x1 + + + + + PORT_SIZE_4 + Indicates whether the TPIU supports port size of 4-bit. + 3 + 3 + + + NotSupported + Port size 4 is not supported. + 0x0 + + + Supported + Port size 4 is supported. + 0x1 + + + + + PORT_SIZE_5 + Indicates whether the TPIU supports port size of 5-bit. + 4 + 4 + + + NotSupported + Port size 5 is not supported. + 0x0 + + + Supported + Port size 5 is supported. + 0x1 + + + + + PORT_SIZE_6 + Indicates whether the TPIU supports port size of 6-bit. + 5 + 5 + + + NotSupported + Port size 6 is not supported. + 0x0 + + + Supported + Port size 6 is supported. + 0x1 + + + + + PORT_SIZE_7 + Indicates whether the TPIU supports port size of 7-bit. + 6 + 6 + + + NotSupported + Port size 7 is not supported. + 0x0 + + + Supported + Port size 7 is supported. + 0x1 + + + + + PORT_SIZE_8 + Indicates whether the TPIU supports port size of 8-bit. + 7 + 7 + + + NotSupported + Port size 8 is not supported. + 0x0 + + + Supported + Port size 8 is supported. + 0x1 + + + + + PORT_SIZE_9 + Indicates whether the TPIU supports port size of 9-bit. + 8 + 8 + + + NotSupported + Port size 9 is not supported. + 0x0 + + + Supported + Port size 9 is supported. + 0x1 + + + + + PORT_SIZE_10 + Indicates whether the TPIU supports port size of 10-bit. + 9 + 9 + + + NotSupported + Port size 10 is not supported. + 0x0 + + + Supported + Port size 10 is supported. + 0x1 + + + + + PORT_SIZE_11 + Indicates whether the TPIU supports port size of 11-bit. + 10 + 10 + + + NotSupported + Port size 11 is not supported. + 0x0 + + + Supported + Port size 11 is supported. + 0x1 + + + + + PORT_SIZE_12 + Indicates whether the TPIU supports port size of 12-bit. + 11 + 11 + + + NotSupported + Port size 12 is not supported. + 0x0 + + + Supported + Port size 12 is supported. + 0x1 + + + + + PORT_SIZE_13 + Indicates whether the TPIU supports port size of 13-bit. + 12 + 12 + + + NotSupported + Port size 13 is not supported. + 0x0 + + + Supported + Port size 13 is supported. + 0x1 + + + + + PORT_SIZE_14 + Indicates whether the TPIU supports port size of 14-bit. + 13 + 13 + + + NotSupported + Port size 14 is not supported. + 0x0 + + + Supported + Port size 14 is supported. + 0x1 + + + + + PORT_SIZE_15 + Indicates whether the TPIU supports port size of 15-bit. + 14 + 14 + + + NotSupported + Port size 15 is not supported. + 0x0 + + + Supported + Port size 15 is supported. + 0x1 + + + + + PORT_SIZE_16 + Indicates whether the TPIU supports port size of 16-bit. + 15 + 15 + + + NotSupported + Port size 16 is not supported. + 0x0 + + + Supported + Port size 16 is supported. + 0x1 + + + + + PORT_SIZE_17 + Indicates whether the TPIU supports port size of 17-bit. + 16 + 16 + + + NotSupported + Port size 17 is not supported. + 0x0 + + + Supported + Port size 17 is supported. + 0x1 + + + + + PORT_SIZE_18 + Indicates whether the TPIU supports port size of 18-bit. + 17 + 17 + + + NotSupported + Port size 18 is not supported. + 0x0 + + + Supported + Port size 18 is supported. + 0x1 + + + + + PORT_SIZE_19 + Indicates whether the TPIU supports port size of 19-bit. + 18 + 18 + + + NotSupported + Port size 19 is not supported. + 0x0 + + + Supported + Port size 19 is supported. + 0x1 + + + + + PORT_SIZE_20 + Indicates whether the TPIU supports port size of 20-bit. + 19 + 19 + + + NotSupported + Port size 20 is not supported. + 0x0 + + + Supported + Port size 20 is supported. + 0x1 + + + + + PORT_SIZE_21 + Indicates whether the TPIU supports port size of 21-bit. + 20 + 20 + + + NotSupported + Port size 21 is not supported. + 0x0 + + + Supported + Port size 21 is supported. + 0x1 + + + + + PORT_SIZE_22 + Indicates whether the TPIU supports port size of 22-bit. + 21 + 21 + + + NotSupported + Port size 22 is not supported. + 0x0 + + + Supported + Port size 22 is supported. + 0x1 + + + + + PORT_SIZE_23 + Indicates whether the TPIU supports port size of 23-bit. + 22 + 22 + + + NotSupported + Port size 23 is not supported. + 0x0 + + + Supported + Port size 23 is supported. + 0x1 + + + + + PORT_SIZE_24 + Indicates whether the TPIU supports port size of 24-bit. + 23 + 23 + + + NotSupported + Port size 24 is not supported. + 0x0 + + + Supported + Port size 24 is supported. + 0x1 + + + + + PORT_SIZE_25 + Indicates whether the TPIU supports port size of 25-bit. + 24 + 24 + + + NotSupported + Port size 25 is not supported. + 0x0 + + + Supported + Port size 25 is supported. + 0x1 + + + + + PORT_SIZE_26 + Indicates whether the TPIU supports port size of 26-bit. + 25 + 25 + + + NotSupported + Port size 26 is not supported. + 0x0 + + + Supported + Port size 26 is supported. + 0x1 + + + + + PORT_SIZE_27 + Indicates whether the TPIU supports port size of 27-bit. + 26 + 26 + + + NotSupported + Port size 27 is not supported. + 0x0 + + + Supported + Port size 27 is supported. + 0x1 + + + + + PORT_SIZE_28 + Indicates whether the TPIU supports port size of 28-bit. + 27 + 27 + + + NotSupported + Port size 28 is not supported. + 0x0 + + + Supported + Port size 28 is supported. + 0x1 + + + + + PORT_SIZE_29 + Indicates whether the TPIU supports port size of 29-bit. + 28 + 28 + + + NotSupported + Port size 29 is not supported. + 0x0 + + + Supported + Port size 29 is supported. + 0x1 + + + + + PORT_SIZE_30 + Indicates whether the TPIU supports port size of 30-bit. + 29 + 29 + + + NotSupported + Port size 30 is not supported. + 0x0 + + + Supported + Port size 30 is supported. + 0x1 + + + + + PORT_SIZE_31 + Indicates whether the TPIU supports port size of 31-bit. + 30 + 30 + + + NotSupported + Port size 31 is not supported. + 0x0 + + + Supported + Port size 31 is supported. + 0x1 + + + + + PORT_SIZE_32 + Indicates whether the TPIU supports port size of 32-bit. + 31 + 31 + + + NotSupported + Port size 32 is not supported. + 0x0 + + + Supported + Port size 32 is supported. + 0x1 + + + + + + + CURRENTPORTSIZE + Each bit location is a single port size. One bit can be set, and indicates the current port size. + 0x004 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates which port size is currently selected. + 0 + 0 + + + NotSelected + Port size 1 is not selected. + 0x0 + + + Selected + Port size 1 is selected. + 0x1 + + + + + PORT_SIZE_2 + Indicates which port size is currently selected. + 1 + 1 + + + NotSelected + Port size 2 is not selected. + 0x0 + + + Selected + Port size 2 is selected. + 0x1 + + + + + PORT_SIZE_3 + Indicates which port size is currently selected. + 2 + 2 + + + NotSelected + Port size 3 is not selected. + 0x0 + + + Selected + Port size 3 is selected. + 0x1 + + + + + PORT_SIZE_4 + Indicates which port size is currently selected. + 3 + 3 + + + NotSelected + Port size 4 is not selected. + 0x0 + + + Selected + Port size 4 is selected. + 0x1 + + + + + PORT_SIZE_5 + Indicates which port size is currently selected. + 4 + 4 + + + NotSelected + Port size 5 is not selected. + 0x0 + + + Selected + Port size 5 is selected. + 0x1 + + + + + PORT_SIZE_6 + Indicates which port size is currently selected. + 5 + 5 + + + NotSelected + Port size 6 is not selected. + 0x0 + + + Selected + Port size 6 is selected. + 0x1 + + + + + PORT_SIZE_7 + Indicates which port size is currently selected. + 6 + 6 + + + NotSelected + Port size 7 is not selected. + 0x0 + + + Selected + Port size 7 is selected. + 0x1 + + + + + PORT_SIZE_8 + Indicates which port size is currently selected. + 7 + 7 + + + NotSelected + Port size 8 is not selected. + 0x0 + + + Selected + Port size 8 is selected. + 0x1 + + + + + PORT_SIZE_9 + Indicates which port size is currently selected. + 8 + 8 + + + NotSelected + Port size 9 is not selected. + 0x0 + + + Selected + Port size 9 is selected. + 0x1 + + + + + PORT_SIZE_10 + Indicates which port size is currently selected. + 9 + 9 + + + NotSelected + Port size 10 is not selected. + 0x0 + + + Selected + Port size 10 is selected. + 0x1 + + + + + PORT_SIZE_11 + Indicates which port size is currently selected. + 10 + 10 + + + NotSelected + Port size 11 is not selected. + 0x0 + + + Selected + Port size 11 is selected. + 0x1 + + + + + PORT_SIZE_12 + Indicates which port size is currently selected. + 11 + 11 + + + NotSelected + Port size 12 is not selected. + 0x0 + + + Selected + Port size 12 is selected. + 0x1 + + + + + PORT_SIZE_13 + Indicates which port size is currently selected. + 12 + 12 + + + NotSelected + Port size 13 is not selected. + 0x0 + + + Selected + Port size 13 is selected. + 0x1 + + + + + PORT_SIZE_14 + Indicates which port size is currently selected. + 13 + 13 + + + NotSelected + Port size 14 is not selected. + 0x0 + + + Selected + Port size 14 is selected. + 0x1 + + + + + PORT_SIZE_15 + Indicates which port size is currently selected. + 14 + 14 + + + NotSelected + Port size 15 is not selected. + 0x0 + + + Selected + Port size 15 is selected. + 0x1 + + + + + PORT_SIZE_16 + Indicates which port size is currently selected. + 15 + 15 + + + NotSelected + Port size 16 is not selected. + 0x0 + + + Selected + Port size 16 is selected. + 0x1 + + + + + PORT_SIZE_17 + Indicates which port size is currently selected. + 16 + 16 + + + NotSelected + Port size 17 is not selected. + 0x0 + + + Selected + Port size 17 is selected. + 0x1 + + + + + PORT_SIZE_18 + Indicates which port size is currently selected. + 17 + 17 + + + NotSelected + Port size 18 is not selected. + 0x0 + + + Selected + Port size 18 is selected. + 0x1 + + + + + PORT_SIZE_19 + Indicates which port size is currently selected. + 18 + 18 + + + NotSelected + Port size 19 is not selected. + 0x0 + + + Selected + Port size 19 is selected. + 0x1 + + + + + PORT_SIZE_20 + Indicates which port size is currently selected. + 19 + 19 + + + NotSelected + Port size 20 is not selected. + 0x0 + + + Selected + Port size 20 is selected. + 0x1 + + + + + PORT_SIZE_21 + Indicates which port size is currently selected. + 20 + 20 + + + NotSelected + Port size 21 is not selected. + 0x0 + + + Selected + Port size 21 is selected. + 0x1 + + + + + PORT_SIZE_22 + Indicates which port size is currently selected. + 21 + 21 + + + NotSelected + Port size 22 is not selected. + 0x0 + + + Selected + Port size 22 is selected. + 0x1 + + + + + PORT_SIZE_23 + Indicates which port size is currently selected. + 22 + 22 + + + NotSelected + Port size 23 is not selected. + 0x0 + + + Selected + Port size 23 is selected. + 0x1 + + + + + PORT_SIZE_24 + Indicates which port size is currently selected. + 23 + 23 + + + NotSelected + Port size 24 is not selected. + 0x0 + + + Selected + Port size 24 is selected. + 0x1 + + + + + PORT_SIZE_25 + Indicates which port size is currently selected. + 24 + 24 + + + NotSelected + Port size 25 is not selected. + 0x0 + + + Selected + Port size 25 is selected. + 0x1 + + + + + PORT_SIZE_26 + Indicates which port size is currently selected. + 25 + 25 + + + NotSelected + Port size 26 is not selected. + 0x0 + + + Selected + Port size 26 is selected. + 0x1 + + + + + PORT_SIZE_27 + Indicates which port size is currently selected. + 26 + 26 + + + NotSelected + Port size 27 is not selected. + 0x0 + + + Selected + Port size 27 is selected. + 0x1 + + + + + PORT_SIZE_28 + Indicates which port size is currently selected. + 27 + 27 + + + NotSelected + Port size 28 is not selected. + 0x0 + + + Selected + Port size 28 is selected. + 0x1 + + + + + PORT_SIZE_29 + Indicates which port size is currently selected. + 28 + 28 + + + NotSelected + Port size 29 is not selected. + 0x0 + + + Selected + Port size 29 is selected. + 0x1 + + + + + PORT_SIZE_30 + Indicates which port size is currently selected. + 29 + 29 + + + NotSelected + Port size 30 is not selected. + 0x0 + + + Selected + Port size 30 is selected. + 0x1 + + + + + PORT_SIZE_31 + Indicates which port size is currently selected. + 30 + 30 + + + NotSelected + Port size 31 is not selected. + 0x0 + + + Selected + Port size 31 is selected. + 0x1 + + + + + PORT_SIZE_32 + Indicates which port size is currently selected. + 31 + 31 + + + NotSelected + Port size 32 is not selected. + 0x0 + + + Selected + Port size 32 is selected. + 0x1 + + + + + + + SUPPORTEDTRIGGERMODES + The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. + 0x100 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Indicates whether multiplying the trigger counter by 2^(0+1) is supported. + 0 + 0 + + + NotSelected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x1 + + + + + MULT_1 + Indicates whether multiplying the trigger counter by 2^(1+1) is supported. + 1 + 1 + + + NotSelected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x1 + + + + + MULT_2 + Indicates whether multiplying the trigger counter by 2^(2+1) is supported. + 2 + 2 + + + NotSelected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x1 + + + + + MULT_3 + Indicates whether multiplying the trigger counter by 2^(3+1) is supported. + 3 + 3 + + + NotSelected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x1 + + + + + MULT_4 + Indicates whether multiplying the trigger counter by 2^(4+1) is supported. + 4 + 4 + + + NotSelected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x1 + + + + + TCOUNT8 + Indicates whether an 8-bit wide counter register is implemented. + 8 + 8 + + + NotImplemented + An 8-bit wide counter register is implemented. + 0x0 + + + Implemented + An 8-bit wide counter register is implemented. + 0x1 + + + + + TRIGGERED + A trigger has occurred and the counter has reached 0. + 16 + 16 + + + NotOccured + Trigger has not occurred. + 0x0 + + + Occured + Trigger has occurred. + 0x1 + + + + + TRGRUN + A trigger has occurred but the counter is not at 0. + 17 + 17 + + + NotOccured + Either a trigger has not occurred or the counter is at 0. + 0x0 + + + Occured + A trigger has occurred but the counter is not at 0. + 0x1 + + + + + + + TRIGGERCOUNTERVALUE + The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. + 0x104 + read-write + 0x00000000 + 0x20 + + + TrigCount + 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. + 0 + 7 + + + + + TRIGGERMULTIPLIER + The Trigger_multiplier register contains the selectors for the trigger counter multiplier. + 0x108 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Multiply the Trigger Counter by 2^n. + 0 + 0 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_1 + Multiply the Trigger Counter by 2^n. + 1 + 1 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_2 + Multiply the Trigger Counter by 2^n. + 2 + 2 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_3 + Multiply the Trigger Counter by 2^n. + 3 + 3 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_4 + Multiply the Trigger Counter by 2^n. + 4 + 4 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + + + SUPPPORTEDTESTPATTERNMODES + The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. + 0x200 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + + + CURRENTTESTPATTERNMODES + Current_test_pattern_mode indicates the current test pattern or mode selected. + 0x204 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + + + TPRCR + The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. + 0x208 + read-write + 0x00000000 + 0x20 + + + PATTCOUNT + 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. + 0 + 7 + + + + + FFSR + The FFSR register indicates the current status of the formatter and flush features available in the TPIU. + 0x300 + read-write + 0x00000000 + 0x20 + + + FLINPROG + Flush in progress. + 0 + 0 + + + NotInProgress + A flush is not in progress. + 0x0 + + + InProgress + A flush is in progress. + 0x1 + + + + + FTSTOPPED + The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. + 1 + 1 + + + Running + Formatter has not stopped. + 0x0 + + + Stopped + Formatter has stopped. + 0x1 + + + + + TCPRESENT + Indicates whether the TRACECTL pin is available for use. + 2 + 2 + + + NotPresent + TRACECTL pin is not present. + 0x0 + + + Present + TRACECTL pin is present. + 0x1 + + + + + + + FFCR + The FFCR register controls the generation of stop, trigger, and flush events. + 0x304 + read-write + 0x00000000 + 0x20 + + + ENFTC + Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. + 0 + 0 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + ENFCONT + Is embedded in trigger packets and indicates that no cycle is using sync packets. + 1 + 1 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONFLIN + Enables the use of the flushin connection. + 4 + 4 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONTRIG + Initiates a manual flush of data in the system when a trigger event occurs. + 5 + 5 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANR + Generates a flush. This bit is set to 0 when this flush is serviced. + 6 + 6 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANW + Generates a flush. This bit is set to 1 when this flush is serviced. + 7 + 7 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGIN + Indicates a trigger when trigin is asserted. + 8 + 8 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGEVT + Indicates a trigger on a trigger event. + 9 + 9 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGFL + Indicates a trigger when flush completion on afreadys is returned. + 10 + 10 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPFL + Forces the FIFO to drain off any part-completed packets. + 12 + 12 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPTRIG + Stops the formatter after a trigger event is observed. Reset to disabled or 0. + 13 + 13 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + + + FSCR + The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. + 0x308 + read-write + 0x00000000 + 0x20 + + + CYCCOUNT + 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. + 0 + 11 + + + + + EXTCTLINPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. + 0x400 + read-write + 0x00000000 + 0x20 + + + EXTCTLIN_0 + EXTCTL inputs. + 0 + 0 + + + Low + Input EXTCTL0 is low. + 0x0 + + + High + Input EXTCTL0 is high. + 0x1 + + + + + EXTCTLIN_1 + EXTCTL inputs. + 1 + 1 + + + Low + Input EXTCTL1 is low. + 0x0 + + + High + Input EXTCTL1 is high. + 0x1 + + + + + EXTCTLIN_2 + EXTCTL inputs. + 2 + 2 + + + Low + Input EXTCTL2 is low. + 0x0 + + + High + Input EXTCTL2 is high. + 0x1 + + + + + EXTCTLIN_3 + EXTCTL inputs. + 3 + 3 + + + Low + Input EXTCTL3 is low. + 0x0 + + + High + Input EXTCTL3 is high. + 0x1 + + + + + EXTCTLIN_4 + EXTCTL inputs. + 4 + 4 + + + Low + Input EXTCTL4 is low. + 0x0 + + + High + Input EXTCTL4 is high. + 0x1 + + + + + EXTCTLIN_5 + EXTCTL inputs. + 5 + 5 + + + Low + Input EXTCTL5 is low. + 0x0 + + + High + Input EXTCTL5 is high. + 0x1 + + + + + EXTCTLIN_6 + EXTCTL inputs. + 6 + 6 + + + Low + Input EXTCTL6 is low. + 0x0 + + + High + Input EXTCTL6 is high. + 0x1 + + + + + EXTCTLIN_7 + EXTCTL inputs. + 7 + 7 + + + Low + Input EXTCTL7 is low. + 0x0 + + + High + Input EXTCTL7 is high. + 0x1 + + + + + + + EXTCTLOUTPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. + 0x404 + read-write + 0x00000000 + 0x20 + + + EXTCTLOUT_0 + EXTCTL outputs. + 0 + 0 + + + Low + Output EXTCTL0 is low. + 0x0 + + + High + Output EXTCTL0 is high. + 0x1 + + + + + EXTCTLOUT_1 + EXTCTL outputs. + 1 + 1 + + + Low + Output EXTCTL1 is low. + 0x0 + + + High + Output EXTCTL1 is high. + 0x1 + + + + + EXTCTLOUT_2 + EXTCTL outputs. + 2 + 2 + + + Low + Output EXTCTL2 is low. + 0x0 + + + High + Output EXTCTL2 is high. + 0x1 + + + + + EXTCTLOUT_3 + EXTCTL outputs. + 3 + 3 + + + Low + Output EXTCTL3 is low. + 0x0 + + + High + Output EXTCTL3 is high. + 0x1 + + + + + EXTCTLOUT_4 + EXTCTL outputs. + 4 + 4 + + + Low + Output EXTCTL4 is low. + 0x0 + + + High + Output EXTCTL4 is high. + 0x1 + + + + + EXTCTLOUT_5 + EXTCTL outputs. + 5 + 5 + + + Low + Output EXTCTL5 is low. + 0x0 + + + High + Output EXTCTL5 is high. + 0x1 + + + + + EXTCTLOUT_6 + EXTCTL outputs. + 6 + 6 + + + Low + Output EXTCTL6 is low. + 0x0 + + + High + Output EXTCTL6 is high. + 0x1 + + + + + EXTCTLOUT_7 + EXTCTL outputs. + 7 + 7 + + + Low + Output EXTCTL7 is low. + 0x0 + + + High + Output EXTCTL7 is high. + 0x1 + + + + + + + ITTRFLINACK + The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + TRIGINACK + Sets the value of triginack. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHINACK + Sets the value of flushinack. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITTRFLIN + The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. + 0xEE8 + read-write + 0x00000000 + 0x20 + + + TRIGIN + Reads the value of trigin. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHIN + Reads the value of flushin. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBDATA0 + The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + Enables control of the atreadys and afvalids outputs of the TPIU. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + Sets the value of afvalid. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + Sets the value of atready. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATID + Reads the value of atids. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. + To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + Reads the value of atvalids. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + Reads the value of afreadys. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + Reads the value of atbytess. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + MUXNUM + Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. + Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. + 0 + 4 + + + CLKRELAT + Indicates the relationship between atclk and traceclkin. + 5 + 5 + + + Synchronous + atclk and traceclkin are synchronous. + 0x0 + + + ASynchronous + atclk and traceclkin are asynchronous. + 0x1 + + + + + FIFOSIZE + FIFO size in powers of 2. + 6 + 8 + + + Entries4 + FIFO size of 4 entries, that is, 16 bytes. + 0x2 + + + + + TCLKDATA + Indicates whether trace clock plus data is supported. + 9 + 9 + + + Supported + Trace clock and data is supported. + 0x0 + + + NotSupported + Trace clock and data is not supported. + 0x1 + + + + + SWOMAN + Indicates whether Serial Wire Output, Manchester encoded format, is supported. + 10 + 10 + + + NotSupported + Serial Wire Output, Manchester encoded format, is not supported. + 0x0 + + + Supported + Serial Wire Output, Manchester encoded format, is supported. + 0x1 + + + + + SWOUARTNRZ + Indicates whether Serial Wire Output, UART or NRZ, is supported. + 11 + 11 + + + NotSupported + Serial Wire Output, UART or NRZ, is not supported. + 0x0 + + + Supported + Serial Wire Output, UART or NRZ, is supported. + 0x1 + + + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace sink. + 0x1 + + + + + SUB + The sub-type of the component + 4 + 7 + + + TracePort + Indicates that this component is a trace port component. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_CTI210 + Cross-Trigger Interface control 0 + 0xBF046000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + 0x20 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0x0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 0x1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + 0x20 + + + INTACK_0 + Acknowledges the ctitrigout 0 output. + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_1 + Acknowledges the ctitrigout 1 output. + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_2 + Acknowledges the ctitrigout 2 output. + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_3 + Acknowledges the ctitrigout 3 output. + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_4 + Acknowledges the ctitrigout 4 output. + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_5 + Acknowledges the ctitrigout 5 output. + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_6 + Acknowledges the ctitrigout 6 output. + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_7 + Acknowledges the ctitrigout 7 output. + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + 0x20 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0x0 + + + Active + Application trigger 0 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 0. + 0x1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0x0 + + + Active + Application trigger 1 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 1. + 0x1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0x0 + + + Active + Application trigger 2 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 2. + 0x1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0x0 + + + Active + Application trigger 3 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 3. + 0x1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + 0x20 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 0x1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 0x1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 0x1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 0x1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + 0x20 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 0x1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 0x1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 0x1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger to Channel Enable register + 0x020 + read-write + 0x00000000 + 0x20 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 0x1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 0x1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 0x1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Channel to Trigger Enable register + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + 0x20 + + + TRIGINSTATUS_0 + Shows the status of ctitrigin0 input. + 0 + 0 + + + Active + Ctitrigin 0 is active. + 0x1 + + + Inactive + Ctitrigin 0 is inactive. + 0x0 + + + + + TRIGINSTATUS_1 + Shows the status of ctitrigin1 input. + 1 + 1 + + + Active + Ctitrigin 1 is active. + 0x1 + + + Inactive + Ctitrigin 1 is inactive. + 0x0 + + + + + TRIGINSTATUS_2 + Shows the status of ctitrigin2 input. + 2 + 2 + + + Active + Ctitrigin 2 is active. + 0x1 + + + Inactive + Ctitrigin 2 is inactive. + 0x0 + + + + + TRIGINSTATUS_3 + Shows the status of ctitrigin3 input. + 3 + 3 + + + Active + Ctitrigin 3 is active. + 0x1 + + + Inactive + Ctitrigin 3 is inactive. + 0x0 + + + + + TRIGINSTATUS_4 + Shows the status of ctitrigin4 input. + 4 + 4 + + + Active + Ctitrigin 4 is active. + 0x1 + + + Inactive + Ctitrigin 4 is inactive. + 0x0 + + + + + TRIGINSTATUS_5 + Shows the status of ctitrigin5 input. + 5 + 5 + + + Active + Ctitrigin 5 is active. + 0x1 + + + Inactive + Ctitrigin 5 is inactive. + 0x0 + + + + + TRIGINSTATUS_6 + Shows the status of ctitrigin6 input. + 6 + 6 + + + Active + Ctitrigin 6 is active. + 0x1 + + + Inactive + Ctitrigin 6 is inactive. + 0x0 + + + + + TRIGINSTATUS_7 + Shows the status of ctitrigin7 input. + 7 + 7 + + + Active + Ctitrigin 7 is active. + 0x1 + + + Inactive + Ctitrigin 7 is inactive. + 0x0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + 0x20 + + + TRIGOUTSTATUS_0 + Shows the status of ctitrigout0 output. + 0 + 0 + + + Active + Ctitrigout 0 is active. + 0x1 + + + Inactive + Ctitrigout 0 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_1 + Shows the status of ctitrigout1 output. + 1 + 1 + + + Active + Ctitrigout 1 is active. + 0x1 + + + Inactive + Ctitrigout 1 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_2 + Shows the status of ctitrigout2 output. + 2 + 2 + + + Active + Ctitrigout 2 is active. + 0x1 + + + Inactive + Ctitrigout 2 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_3 + Shows the status of ctitrigout3 output. + 3 + 3 + + + Active + Ctitrigout 3 is active. + 0x1 + + + Inactive + Ctitrigout 3 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_4 + Shows the status of ctitrigout4 output. + 4 + 4 + + + Active + Ctitrigout 4 is active. + 0x1 + + + Inactive + Ctitrigout 4 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_5 + Shows the status of ctitrigout5 output. + 5 + 5 + + + Active + Ctitrigout 5 is active. + 0x1 + + + Inactive + Ctitrigout 5 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_6 + Shows the status of ctitrigout6 output. + 6 + 6 + + + Active + Ctitrigout 6 is active. + 0x1 + + + Inactive + Ctitrigout 6 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_7 + Shows the status of ctitrigout7 output. + 7 + 7 + + + Active + Ctitrigout 7 is active. + 0x1 + + + Inactive + Ctitrigout 7 is inactive. + 0x0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + 0x20 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 0x1 + + + Inactive + Ctichin 0 is inactive. + 0x0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 0x1 + + + Inactive + Ctichin 1 is inactive. + 0x0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 0x1 + + + Inactive + Ctichin 2 is inactive. + 0x0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 0x1 + + + Inactive + Ctichin 3 is inactive. + 0x0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + 0x20 + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 0x1 + + + Disabled + Disable ctichout channel 0 propagation. + 0x0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 0x1 + + + Disabled + Disable ctichout channel 1 propagation. + 0x0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 0x1 + + + Disabled + Disable ctichout channel 2 propagation. + 0x0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 0x1 + + + Disabled + Disable ctichout channel 3 propagation. + 0x0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + 0x20 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + 0x20 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + 0x20 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 0x4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 0x1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + 0x20 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 0x4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + 0x00000000 + 0x20 + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + 0x00000000 + 0x20 + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + 0x00000000 + 0x20 + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + 0x20 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + 0x20 + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 0xD + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 0xB + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + 0x20 + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 0x3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0x0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + 0x20 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0x0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0x0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + 0x20 + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + 0x20 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0x0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 0x9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + 0x20 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + 0x20 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + GLOBAL_CTI211 + Cross-Trigger Interface control 1 + 0xBF047000 + + + + + GLOBAL_ATBREPLICATOR210 + ATB Replicator module 0 + 0xBF048000 + ATBREPLICATOR + + + + 0 + 0x1000 + registers + + ATBREPLICATOR + 0x20 + + + IDFILTER0 + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ID0_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + IDFILTER1 + The IDFILTER1 register enables the programming of ID filtering for master port 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + ID1_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATREADYM0 + Reads the value of the atreadym0 input. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYM1 + Reads the value of the atreadym1 input. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDS + Reads the value of the atvalids input. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR0 + The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + Sets the value of the atvalidm0 output. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDM1 + Sets the value of the atvalidm1 output. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYS + Sets the value of the atreadys output. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTNUM + Indicates the number of master ports implemented. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + Indicates that this component replicates trace from a single source to multiple targets. + 0x2 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBREPLICATOR211 + ATB Replicator module 1 + 0xBF049000 + + + + + GLOBAL_ATBREPLICATOR212 + ATB Replicator module 2 + 0xBF04A000 + + + + + GLOBAL_ATBREPLICATOR213 + ATB Replicator module 3 + 0xBF04B000 + + + + + GLOBAL_ATBFUNNEL210 + ATB funnel module 0 + 0xBF04C000 + ATBFUNNEL + + + + 0 + 0x1000 + registers + + ATBFUNNEL + 0x20 + + + CTRLREG + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENS_0 + Enable slave port 0. + 0 + 0 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_1 + Enable slave port 1. + 1 + 1 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_2 + Enable slave port 2. + 2 + 2 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_3 + Enable slave port 3. + 3 + 3 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_4 + Enable slave port 4. + 4 + 4 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_5 + Enable slave port 5. + 5 + 5 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_6 + Enable slave port 6. + 6 + 6 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_7 + Enable slave port 7. + 7 + 7 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + HT + Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. + When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. + The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. + The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. + 8 + 11 + + + + + PRIORITYCTRLREG + The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. + 0x004 + read-write + 0x00000000 + 0x20 + + + PRIPORT0 + Priority value of port number 0. + 0 + 2 + + + PRIPORT1 + Priority value of port number 1. + 3 + 5 + + + PRIPORT2 + Priority value of port number 2. + 6 + 8 + + + PRIPORT3 + Priority value of port number 3. + 9 + 11 + + + PRIPORT4 + Priority value of port number 4. + 12 + 14 + + + PRIPORT5 + Priority value of port number 5. + 15 + 17 + + + PRIPORT6 + Priority value of port number 6. + 18 + 20 + + + PRIPORT7 + Priority value of port number 7. + 21 + 23 + + + + + ITATBDATA0 + The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_5 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 5 + 5 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_6 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 6 + 6 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_7 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 7 + 7 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_8 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 8 + 8 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_9 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 9 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_10 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 10 + 10 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_11 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 11 + 11 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_12 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 12 + 12 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_13 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 13 + 13 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_14 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 14 + 14 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_15 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 15 + 15 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_16 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 16 + 16 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + A read access returns the value of atreadym. + A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + A read access returns the value of afvalidm. + A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. +A write outputs the value to the atidm port. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. +A write outputs the value to atvalidm. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to afreadym. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to atbytesm. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTCOUNT + Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + This component arbitrates ATB inputs mapping to ATB outputs. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBFUNNEL211 + ATB funnel module 1 + 0xBF04D000 + + + + + GLOBAL_ATBFUNNEL212 + ATB funnel module 2 + 0xBF04E000 + + + + + GLOBAL_ATBFUNNEL213 + ATB funnel module 3 + 0xBF04F000 + + + + + VPRCLIC + VPR CLIC registers + 0x5F8D5000 + CLIC + + 0 + 0x3000 + registers + + + VPRCLIC_0 + 0 + + + VPRCLIC_1 + 1 + + + VPRCLIC_2 + 2 + + + VPRCLIC_3 + 3 + + + VPRCLIC_4 + 4 + + + VPRCLIC_5 + 5 + + + VPRCLIC_6 + 6 + + + VPRCLIC_7 + 7 + + + VPRCLIC_8 + 8 + + + VPRCLIC_9 + 9 + + + VPRCLIC_10 + 10 + + + VPRCLIC_11 + 11 + + + VPRCLIC_12 + 12 + + + VPRCLIC_13 + 13 + + + VPRCLIC_14 + 14 + + + VPRCLIC_15 + 15 + + + VPRCLIC_16 + 16 + + + VPRCLIC_17 + 17 + + + VPRCLIC_18 + 18 + + + VPRCLIC_19 + 19 + + + VPRCLIC_20 + 20 + + + VPRCLIC_21 + 21 + + + VPRCLIC_22 + 22 + + + VPRCLIC_23 + 23 + + + VPRCLIC_24 + 24 + + + VPRCLIC_25 + 25 + + + VPRCLIC_26 + 26 + + + VPRCLIC_27 + 27 + + + VPRCLIC_28 + 28 + + + VPRCLIC_29 + 29 + + + VPRCLIC_30 + 30 + + + VPRCLIC_31 + 31 + + CLIC + 0x20 + + + CLIC + Unspecified + CLIC_CLIC + read-write + 0x000 + + CLICCFG + CLIC configuration. + 0x0000 + read-only + 0x00000011 + 0x20 + + + NVBITS + Selective interrupt hardware vectoring. + 0 + 0 + + + Implemented + Selective interrupt hardware vectoring is implemented + 0x1 + + + + + NLBITS + Interrupt level encoding. + 1 + 4 + + + Eight + 8 bits = interrupt levels encoded in eight bits + 0x8 + + + + + NMBITS + Interrupt privilege mode. + 5 + 6 + + + ModeM + All interrupts are M-mode only + 0x0 + + + + + + + CLICINFO + CLIC information. + 0x0004 + read-only + 0x00401FFF + 0x20 + + + NUMINTERRUPTS + Maximum number of interrupts supported. + 0 + 12 + + + VERSION + Version + 13 + 20 + + + NUMTRIGGER + Number of maximum interrupt triggers supported + 25 + 30 + + + + + 0x1E0 + 0x4 + CLICINT[%s] + Description collection: Interrupt control register for IRQ number [n]. + 0x1000 + read-write + 0x3FC30000 + 0x20 + + + IP + Interrupt Pending bit. + 0 + 0 + + + NotPending + Interrupt not pending + 0x0 + + + Pending + Interrupt pending + 0x1 + + + + + READ1 + Read as 0, write ignored. + 1 + 7 + read-only + + + IE + Interrupt enable bit. + 8 + 8 + + + Disabled + Interrupt disabled + 0x0 + + + Enabled + Interrupt enabled + 0x1 + + + + + READ2 + Read as 0, write ignored. + 9 + 15 + read-only + + + SHV + Selective Hardware Vectoring. + 16 + 16 + read-only + + + Vectored + Hardware vectored + 0x1 + + + + + TRIG + Trigger type and polarity for each interrupt input. + 17 + 18 + read-only + + + EdgeTriggered + Interrupts are edge-triggered + 0x1 + + + + + MODE + Privilege mode. + 22 + 23 + read-only + + + MachineMode + Machine mode + 0x3 + + + + + PRIORITY + Interrupt priority level + 24 + 31 + + + PRIOLEVEL0 + Priority level 0 + 0x3F + + + PRIOLEVEL1 + Priority level 1 + 0x7F + + + PRIOLEVEL2 + Priority level 2 + 0xBF + + + PRIOLEVEL3 + Priority level 3 + 0xFF + + + + + + + + + + VPRTIM + VTIM CSR registers + 0x00000000 + + 0 + 0x1000 + registers + + + VPRTIM + 32 + + VTIM + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + GLOBAL_GPIOTE130 + GPIO Tasks and Events 0 + 0x5F934000 + GPIOTE + + + + + 0 + 0x1000 + registers + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 4 + 0x008 + EVENTS_PORT[%s] + Peripheral events. + GLOBAL_GPIOTE_EVENTS_PORT + read-write + 0x140 + + NONSECURE + Description cluster: Non-secure port event from owner n + 0x000 + read-write + 0x00000000 + 0x20 + + + + NONSECURE + Non-secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SECURE + Description cluster: Secure port event from owner n + 0x004 + read-write + 0x00000000 + 0x20 + + + + SECURE + Secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 4 + 0x008 + PUBLISH_PORT[%s] + Publish configuration for events + GLOBAL_GPIOTE_PUBLISH_PORT + read-write + 0x1C0 + + NONSECURE + Description cluster: Publish configuration for event PORT[n].NONSECURE + 0x000 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].NONSECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SECURE + Description cluster: Publish configuration for event PORT[n].SECURE + 0x004 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].SECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + 0x20 + + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting + 0x0 + + + LowLatency + Low latency setting + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + 0x20 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 4 + 8 + + + PORT + Port number + 9 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + GLOBAL_GPIOTE131 + GPIO Tasks and Events 1 + 0x5F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GRTC + Global Real-time counter + 0x5F99C000 + + + + + 0 + 0x1000 + registers + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + GRTC + 0x20 + + + 0x10 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture the counter value to CC[n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture the counter value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTART + Start the PWM + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTART + Start the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTOP + Stop the PWM + 0x070 + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTOP + Stop the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0x164 + read-write + 0x00000000 + 0x20 + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0x168 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0x16C + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN4 + Enable or disable interrupt + 0x340 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET4 + Enable interrupt + 0x344 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR4 + Disable interrupt + 0x348 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND4 + Pending interrupts + 0x34C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN5 + Enable or disable interrupt + 0x350 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET5 + Enable interrupt + 0x354 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR5 + Disable interrupt + 0x358 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND5 + Pending interrupts + 0x35C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN6 + Enable or disable interrupt + 0x360 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET6 + Enable interrupt + 0x364 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR6 + Disable interrupt + 0x368 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND6 + Pending interrupts + 0x36C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN7 + Enable or disable interrupt + 0x370 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET7 + Enable interrupt + 0x374 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR7 + Disable interrupt + 0x378 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND7 + Pending interrupts + 0x37C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN8 + Enable or disable interrupt + 0x380 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET8 + Enable interrupt + 0x384 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR8 + Disable interrupt + 0x388 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND8 + Pending interrupts + 0x38C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN9 + Enable or disable interrupt + 0x390 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET9 + Enable interrupt + 0x394 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR9 + Disable interrupt + 0x398 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND9 + Pending interrupts + 0x39C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN10 + Enable or disable interrupt + 0x3A0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x3A4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x3A8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND10 + Pending interrupts + 0x3AC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN11 + Enable or disable interrupt + 0x3B0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET11 + Enable interrupt + 0x3B4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x3B8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND11 + Pending interrupts + 0x3BC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN12 + Enable or disable interrupt + 0x3C0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET12 + Enable interrupt + 0x3C4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR12 + Disable interrupt + 0x3C8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND12 + Pending interrupts + 0x3CC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN13 + Enable or disable interrupt + 0x3D0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET13 + Enable interrupt + 0x3D4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR13 + Disable interrupt + 0x3D8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND13 + Pending interrupts + 0x3DC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN14 + Enable or disable interrupt + 0x3E0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET14 + Enable interrupt + 0x3E4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR14 + Disable interrupt + 0x3E8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND14 + Pending interrupts + 0x3EC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN15 + Enable or disable interrupt + 0x3F0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET15 + Enable interrupt + 0x3F4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR15 + Disable interrupt + 0x3F8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND15 + Pending interrupts + 0x3FC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x400 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Enable or disable event routing for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x404 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to enable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x408 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to disable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Counter mode selection + 0x510 + read-write + 0x00000000 + 0x20 + + + AUTOEN + Automatic enable to keep the SYSCOUNTER active. + 0 + 0 + + + Default + Default configuration to keep the SYSCOUNTER active. + 0x0 + + + CpuActive + In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. + 0x1 + + + + + SYSCOUNTEREN + Enable the SYSCOUNTER + 1 + 1 + + + Disabled + SYSCOUNTER disabled + 0x0 + + + Enabled + SYSCOUNTER enabled + 0x1 + + + + + + + 16 + 0x010 + CC[%s] + Unspecified + GRTC_CC + read-write + 0x520 + + CCL + Description cluster: The lower 32-bits of Capture/Compare register CC[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CCL + Capture/Compare low value in 1 us + 0 + 31 + + + + + CCH + Description cluster: The higher 32-bits of Capture/Compare register CC[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + CCH + Capture/Compare high value in 1 us + 0 + 19 + + + + + CCADD + Description cluster: Count to add to CC[n] when this register is written. + 0x008 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[n] + 0 + 30 + + + REFERENCE + Configure the Capture/Compare register + 31 + 31 + + + SYSCOUNTER + Adds SYSCOUNTER value. + 0x0 + + + CC + Adds CC value. + 0x1 + + + + + + + CCEN + Description cluster: Configure Capture/Compare register CC[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + ACTIVE + Configure the Capture/Compare register + 0 + 0 + + + Disable + Capture/Compare register CC[n] Disabled. + 0x0 + + + Enable + Capture/Compare register CC[n] enabled. + 0x1 + + + + + + + + KEEPRUNNING + Request to keep the SYSCOUNTER in the active state and prevent going to sleep + 0x6A0 + read-write + 0x00000000 + 0x20 + + + REQUEST_0 + Request from index [0] + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_1 + Request from index [1] + 1 + 1 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_2 + Request from index [2] + 2 + 2 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_3 + Request from index [3] + 3 + 3 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_4 + Request from index [4] + 4 + 4 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_5 + Request from index [5] + 5 + 5 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_6 + Request from index [6] + 6 + 6 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_7 + Request from index [7] + 7 + 7 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_8 + Request from index [8] + 8 + 8 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_9 + Request from index [9] + 9 + 9 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_10 + Request from index [10] + 10 + 10 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_11 + Request from index [11] + 11 + 11 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_12 + Request from index [12] + 12 + 12 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_13 + Request from index [13] + 13 + 13 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_14 + Request from index [14] + 14 + 14 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_15 + Request from index [15] + 15 + 15 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + TIMEOUT + Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER + 0x6A4 + read-write + 0x00000000 + 0x20 + + + VALUE + Number of 32Ki cycles + 0 + 15 + + + + + INTERVAL + Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. + 0x6A8 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[0] + 0 + 15 + + + + + PWMCONFIG + PWM configuration. + 0x710 + read-write + 0x00000000 + 0x20 + + + COMPAREVALUE + The PWM compare value + 0 + 7 + + + + + CLKOUT + Configuration of clock output + 0x714 + read-write + 0x00000000 + 0x20 + + + CLKOUT32K + Enable 32Ki clock output on pin + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + CLKOUTFAST + Enable fast clock output on pin + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + CLKCFG + Clock Configuration + 0x718 + read-write + 0x00010001 + 0x20 + + + CLKFASTDIV + Fast clock divisor value of clock output + 0 + 7 + + + CLKSEL + GRTC LFCLK clock source selection + 16 + 17 + + + LFXO + GRTC LFCLK clock source is LFXO + 0x0 + + + SystemLFCLK + GRTC LFCLK clock source is system LFCLK + 0x1 + + + + + + + 16 + 0x010 + SYSCOUNTER[%s] + Unspecified + GRTC_SYSCOUNTER + read-write + 0x720 + + SYSCOUNTERL + Description cluster: The lower 32-bits of the SYSCOUNTER for index [n] + 0x000 + read-only + 0x00000000 + 0x20 + + + VALUE + The lower 32-bits of the SYSCOUNTER value. + 0 + 31 + + + + + SYSCOUNTERH + Description cluster: The higher 20-bits of the SYSCOUNTER for index [n] + 0x004 + read-only + 0x40000000 + 0x20 + + + VALUE + The higher 20-bits of the SYSCOUNTER value. + 0 + 19 + + + BUSY + SYSCOUNTER busy status + 30 + 30 + + + Ready + SYSCOUNTER is ready for read + 0x0 + + + Busy + SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this register is not valid) + 0x1 + + + + + OVERFLOW + The SYSCOUNTERL overflow indication after reading it. + 31 + 31 + + + NoOverflow + SYSCOUNTERL is not overflown + 0x0 + + + Overflow + SYSCOUNTERL overflown + 0x1 + + + + + + + ACTIVE + Description cluster: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] + 0x008 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Keep SYSCOUNTER in active state + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + + + + GLOBAL_TBM + Trace buffer monitor + 0xBF003000 + + + + 0 + 0x1000 + registers + + + TBM + 127 + + TBM + 0x20 + + + TASKS_START + Start counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop counter, clear counter value + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop counter, clear counter value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_HALFFULL + Counter value equals half-full + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_HALFFULL + Counter value equals half-full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FULL + Counter value equals full + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FULL + Counter value equals full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Enable or disable interrupt for event HALFFULL + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FULL + Enable or disable interrupt for event FULL + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FLUSH + Enable or disable interrupt for event FLUSH + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to enable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FULL + Write '1' to enable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FLUSH + Write '1' to enable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to disable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FULL + Write '1' to disable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FLUSH + Write '1' to disable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + HALFFULL + Read pending status of interrupt for event HALFFULL + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FULL + Read pending status of interrupt for event FULL + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FLUSH + Read pending status of interrupt for event FLUSH + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + BUFFERSIZE + System RAM trace buffer total size in bytes + 0x400 + read-write + 0x00000400 + 0x20 + + + BUFFERSIZE + Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to make + half-buffer size always 64 bit word aligned. Typical minimum BUFFERSIZE value 0x010 i.e. 16 bytes, typical + maximum value 0x1000 i.e. 4096 bytes. + 0 + 12 + + + Zero + 0 bytes + 0x0000 + + + Min + 16 bytes + 0x0010 + + + Max + 4096 bytes + 0x1000 + + + + + + + COUNT + Counter current value + 0x404 + read-write + 0x00000000 + 0x20 + + + COUNT + Counter current value. Only writable when counter is in stopped state. Writing when not in stopped + state will generate a bus fault. + 0 + 12 + + + + + COUNTSNAPSHOT + Copy of the current COUNT value + 0x408 + read-only + 0x00000000 + 0x20 + + + COUNTSNAPSHOT + TASKS_FLUSH will copy the current COUNT value to this register. + 0 + 12 + + + + + + + GLOBAL_USBHS + USBHS + 0x5F086000 + + + + 0 + 0x1000 + registers + + + USBHS + 134 + + USBHS + 0x20 + + + TASKS_START + Start the USB peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the USB peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable USB peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + CORE + Enable USB Controller + 0 + 0 + + + Disabled + USB Controller disabled. + 0x0 + + + Enabled + USB Controller enabled. + 0x1 + + + + + PHY + Enable USB PHY + 1 + 1 + + + Disabled + USB PHY disabled. + 0x0 + + + Enabled + USB PHY enabled. + 0x1 + + + + + + + + + GLOBAL_EXMIF + External Memory Interface + 0x5F095000 + + + + 0 + 0x1000 + registers + + + EXMIF + 149 + + EXMIF + 0x20 + + + TASKS_START + Start operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + LOCKEDACCESS + Enable or disable locked APB access to serial memory controller. + 0x14 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable locked APB access to SSI. + 0 + 0 + + + Disabled + Disable locked APB access. + 0x0 + + + Enabled + Enable locked APB access. + 0x1 + + + + + + + RESET + Reset the external memory. + 0x1C + read-write + 0x00000000 + 0x20 + + + RESET + 0 + 0 + + + Clear + Reset is cleared. + 0x0 + + + Set + Reset is set. + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EXTCONF1 + Configuration for external memory device 1. + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 1. + 0x0 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 1. + 0x4 + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x10 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + EXTCONF2 + Configuration for external memory device 2. + EXTCONF2 + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 2. + 0x8 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 2. + 0xC + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x20 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + CORE + Unspecified + GLOBAL_EXMIF_CORE + read-write + 0x500 + + SSICADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICADDRESS + read-write + 0x000 + + CTRLR0 + This register controls the serial data transfer. + 0x000 + read-write + 0x00004007 + 0x20 + + + DFS + Data Frame Size. + 0 + 4 + + + DFS_01_BIT + Unspecified + 0x00 + + + DFS_02_BIT + Unspecified + 0x01 + + + DFS_03_BIT + Unspecified + 0x02 + + + DFS_04_BIT + Unspecified + 0x03 + + + DFS_05_BIT + Unspecified + 0x04 + + + DFS_06_BIT + Unspecified + 0x05 + + + DFS_07_BIT + Unspecified + 0x06 + + + DFS_08_BIT + Unspecified + 0x07 + + + DFS_09_BIT + Unspecified + 0x08 + + + DFS_10_BIT + Unspecified + 0x09 + + + DFS_11_BIT + Unspecified + 0x0A + + + DFS_12_BIT + Unspecified + 0x0B + + + DFS_13_BIT + Unspecified + 0x0C + + + DFS_14_BIT + Unspecified + 0x0D + + + DFS_15_BIT + Unspecified + 0x0E + + + DFS_16_BIT + Unspecified + 0x0F + + + DFS_17_BIT + Unspecified + 0x10 + + + DFS_18_BIT + Unspecified + 0x11 + + + DFS_19_BIT + Unspecified + 0x12 + + + DFS_20_BIT + Unspecified + 0x13 + + + DFS_21_BIT + Unspecified + 0x14 + + + DFS_22_BIT + Unspecified + 0x15 + + + DFS_23_BIT + Unspecified + 0x16 + + + DFS_24_BIT + Unspecified + 0x17 + + + DFS_25_BIT + Unspecified + 0x18 + + + DFS_26_BIT + Unspecified + 0x19 + + + DFS_27_BIT + Unspecified + 0x1A + + + DFS_28_BIT + Unspecified + 0x1B + + + DFS_29_BIT + Unspecified + 0x1C + + + DFS_30_BIT + Unspecified + 0x1D + + + DFS_31_BIT + Unspecified + 0x1E + + + DFS_32_BIT + Unspecified + 0x1F + + + + + FRF + Frame Format. + 6 + 7 + + + SPI + Unspecified + 0x0 + + + SSP + Unspecified + 0x1 + + + MICROWIRE + Unspecified + 0x2 + + + + + SCPH + Serial Clock Phase. + 8 + 8 + + + MIDDLE_BIT + Unspecified + 0x0 + + + START_BIT + Unspecified + 0x1 + + + + + SCPOL + Serial Clock Polarity. + 9 + 9 + + + INACTIVE_HIGH + Unspecified + 0x0 + + + INACTIVE_LOW + Unspecified + 0x1 + + + + + TMOD + Transfer Mode. + 10 + 11 + + + TX_AND_RX + Unspecified + 0x0 + + + TX_ONLY + Unspecified + 0x1 + + + RX_ONLY + Unspecified + 0x2 + + + EEPROM_READ + Unspecified + 0x3 + + + + + SLVOE + Slave Output Enable. + 12 + 12 + + + ENABLED + Unspecified + 0x0 + + + DISABLED + Unspecified + 0x1 + + + + + SRL + Shift Register Loop. + 13 + 13 + + + NORMAL_MODE + Unspecified + 0x0 + + + TESTING_MODE + Unspecified + 0x1 + + + + + SSTE + Slave Select Toggle Enable. + 14 + 14 + + + TOGGLE_DISABLE + Unspecified + 0x0 + + + TOGGLE_EN + Unspecified + 0x1 + + + + + CFS + Control Frame Size. + 16 + 19 + + + SIZE_01_BIT + Unspecified + 0x0 + + + SIZE_02_BIT + Unspecified + 0x1 + + + SIZE_03_BIT + Unspecified + 0x2 + + + SIZE_04_BIT + Unspecified + 0x3 + + + SIZE_05_BIT + Unspecified + 0x4 + + + SIZE_06_BIT + Unspecified + 0x5 + + + SIZE_07_BIT + Unspecified + 0x6 + + + SIZE_08_BIT + Unspecified + 0x7 + + + SIZE_09_BIT + Unspecified + 0x8 + + + SIZE_10_BIT + Unspecified + 0x9 + + + SIZE_11_BIT + Unspecified + 0xA + + + SIZE_12_BIT + Unspecified + 0xB + + + SIZE_13_BIT + Unspecified + 0xC + + + SIZE_14_BIT + Unspecified + 0xD + + + SIZE_15_BIT + Unspecified + 0xE + + + SIZE_16_BIT + Unspecified + 0xF + + + + + SPIFRF + SPI Frame Format + 22 + 23 + + + SPI_STANDARD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + SPIHYPERBUSEN + SPI Hyperbus Frame format enable. + 24 + 24 + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SPIDWSEN + Enable Dynamic wait states in SPI mode of operation. + 25 + 25 + read-only + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SSIISMST + This field selects if DWC_ssi is working in Master or Slave mode + 31 + 31 + read-only + + + SLAVE + Unspecified + 0x0 + + + MASTER + Unspecified + 0x1 + + + + + + + CTRLR1 + This register exists only when the DWC_ssi is configured as a master device. + 0x004 + read-write + 0x00000000 + 0x20 + + + NDF + Number of Data Frames. + 0 + 15 + + + + + SSIENR + This register enables and disables the DWC_ssi. + 0x008 + read-write + 0x00000000 + 0x20 + + + SSICEN + SSI Enable. + 0 + 0 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MWCR + This register controls the direction of the data word for the half-duplex Microwire serial protocol. + 0x00C + read-write + 0x00000000 + 0x20 + + + MWMOD + Microwire Transfer Mode. + 0 + 0 + + + NON_SEQUENTIAL + Unspecified + 0x0 + + + SEQUENTIAL + Unspecified + 0x1 + + + + + MDD + Microwire Control. + 1 + 1 + + + RECEIVE + Unspecified + 0x0 + + + TRANSMIT + Unspecified + 0x1 + + + + + MHS + Microwire Handshaking. + 2 + 2 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SER + This register is valid only when the DWC_ssi is configured as a master device. + 0x010 + read-write + 0x00000000 + 0x20 + + + SER + Slave Select Enable Flag. + 0 + 1 + + + NOTSELECTED + Unspecified + 0x0 + + + SELECTED + Unspecified + 0x1 + + + + + + + BAUDR + This register is valid only when the DWC_ssi is configured as a master device. + 0x014 + read-write + 0x00000000 + 0x20 + + + SCKDV + SSI Clock Divider. + 1 + 15 + + + + + TXFTLR + This register controls the threshold value for the transmit FIFO memory.. + 0x018 + read-write + 0x00000000 + 0x20 + + + TFT + Transmit FIFO Threshold. + 0 + 4 + + + TXFTHR + Transfer start FIFO level. + 16 + 20 + + + + + RXFTLR + This register controls the threshold value for the receive FIFO memory.. + 0x01C + read-write + 0x00000000 + 0x20 + + + RFT + Receive FIFO Threshold. + 0 + 4 + + + + + TXFLR + This register contains the number of valid data entries in the transmit FIFO memory. + 0x020 + read-write + 0x00000000 + 0x20 + + + TXTFL + Transmit FIFO Level. + 0 + 5 + read-only + + + + + RXFLR + This register contains the number of valid data entries in the receive FIFO memory. + 0x024 + read-write + 0x00000000 + 0x20 + + + RXTFL + Receive FIFO Level. + 0 + 5 + read-only + + + + + SR + This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. + 0x028 + read-write + 0x00000006 + 0x20 + + + BUSY + SSI Busy Flag. + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TFNF + Transmit FIFO Not Full. + 1 + 1 + read-only + + + FULL + Unspecified + 0x0 + + + NOT_FULL + Unspecified + 0x1 + + + + + TFE + Transmit FIFO Empty. + 2 + 2 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + RFNE + Receive FIFO Not Empty. + 3 + 3 + read-only + + + EMPTY + Unspecified + 0x0 + + + NOT_EMPTY + Unspecified + 0x1 + + + + + RFF + Receive FIFO Full. + 4 + 4 + read-only + + + NOT_FULL + Unspecified + 0x0 + + + FULL + Unspecified + 0x1 + + + + + TXE + Transmission Error. + 5 + 5 + read-only + + + NO_ERROR + Unspecified + 0x0 + + + TX_ERROR + Unspecified + 0x1 + + + + + DCOL + Data Collision Error. + 6 + 6 + read-only + + + NO_ERROR_CONDITION + Unspecified + 0x0 + + + TX_COLLISION_ERROR + Unspecified + 0x1 + + + + + + + IMR + This read/write register masks or enables all interrupts generated by the DWC_ssi. + 0x02C + read-write + 0x000000FF + 0x20 + + + TXEIM + Transmit FIFO Empty Interrupt Mask + 0 + 0 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXOIM + Transmit FIFO Overflow Interrupt Mask + 1 + 1 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXUIM + Receive FIFO Underflow Interrupt Mask + 2 + 2 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXOIM + Receive FIFO Overflow Interrupt Mask + 3 + 3 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXFIM + Receive FIFO Full Interrupt Mask + 4 + 4 + + + MASKED + ssi_rxf_intr interrupt is masked + 0x0 + + + UNMASKED + ssi_rxf_intr interrupt is not masked + 0x1 + + + + + MSTIM + Multi-Master Contention Interrupt Mask. + 5 + 5 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + XRXOIM + XIP Receive FIFO Overflow Interrupt Mask + 6 + 6 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXUIM + Transmit FIFO Underflow Interrupt Mask + 7 + 7 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + DONEM + SSI Done Interrupt Mask + 11 + 11 + read-only + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + + + ISR + This register reports the status of the DWC_ssi interrupts after they have been masked. + 0x030 + read-write + 0x00000000 + 0x20 + + + TXEIS + Transmit FIFO Empty Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIS + Transmit FIFO Overflow Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIS + Receive FIFO Underflow Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIS + Receive FIFO Overflow Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIS + Receive FIFO Full Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIS + Multi-Master Contention Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIS + XIP Receive FIFO Overflow Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIS + Transmit FIFO Underflow Interrupt Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONES + SSI Done Interrupt Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RISR + Raw Interrupt Status Register + 0x034 + read-write + 0x00000000 + 0x20 + + + TXEIR + Transmit FIFO Empty Raw Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIR + Transmit FIFO Overflow Raw Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIR + Receive FIFO Underflow Raw Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIR + Receive FIFO Overflow Raw Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIR + Receive FIFO Full Raw Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIR + Multi-Master Contention Raw Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIR + XIP Receive FIFO Overflow Raw Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIR + Transmit FIFO Underflow Interrupt Raw Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONER + SSI Done Interrupt Raw Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + TXEICR + Transmit FIFO Error Interrupt Clear Register + 0x038 + read-write + 0x00000000 + 0x20 + + + TXEICR + Clear Transmit FIFO Overflow/Underflow Interrupt. + 0 + 0 + read-only + + + + + RXOICR + Receive FIFO Overflow Interrupt Clear Register + 0x03C + read-write + 0x00000000 + 0x20 + + + RXOICR + Clear Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + RXUICR + Receive FIFO Underflow Interrupt Clear Register + 0x040 + read-write + 0x00000000 + 0x20 + + + RXUICR + Clear Receive FIFO Underflow Interrupt. + 0 + 0 + read-only + + + + + MSTICR + Multi-Master Interrupt Clear Register + 0x044 + read-write + 0x00000000 + 0x20 + + + MSTICR + Clear Multi-Master Contention Interrupt. + 0 + 0 + read-only + + + + + ICR + Interrupt Clear Register + 0x048 + read-write + 0x00000000 + 0x20 + + + ICR + Clear Interrupts. + 0 + 0 + read-only + + + + + IDR + This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. + 0x058 + read-write + 0x00010003 + 0x20 + + + IDCODE + Identification code. + 0 + 31 + read-only + + + + + SSICVERSIONID + This read-only register stores the specific DWC_ssi component version. + 0x05C + read-write + 0x3130332A + 0x20 + + + SSICCOMPVERSION + Contains the hex representation of the Synopsys component version. + 0 + 31 + read-only + + + + + 0x24 + 0x4 + DR[%s] + Description collection: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. + 0x060 + read-write + 0x00000000 + 0x20 + + + DR + Data Register. + 0 + 31 + + + + + RXSAMPLEDELAY + This register is only valid when the DWC_ssi is configured with rxd sample delay logic (SSIC_HAS_RX_SAMPLE_DELAY==1). + 0x0F0 + read-write + 0x00000000 + 0x20 + + + RSD + Receive Data (rxd) Sample Delay. + 0 + 7 + + + SE + Receive Data (rxd) Sampling Edge. + 16 + 16 + + + + + SPICTRLR0 + This register is used to control the serial data transfer in enhanced SPI mode of operation. + 0x0F4 + read-write + 0x00000A00 + 0x20 + + + TRANSTYPE + Address and instruction transfer format. + 0 + 1 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 2 + 5 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + XIPMDBITEN + Mode bits enable in XIP mode. + 7 + 7 + read-only + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 11 + 15 + + + SPIDDREN + SPI DDR Enable bit. + 16 + 16 + + + INSTDDREN + Instruction DDR Enable bit. + 17 + 17 + + + SPIRXDSEN + Read data strobe enable bit. + 18 + 18 + + + XIPDFSHC + Fix DFS for XIP transfers. + 19 + 19 + read-only + + + XIPINSTEN + XIP instruction enable bit. + 20 + 20 + read-only + + + SSICXIPCONTXFEREN + Enable continuous transfer in XIP mode. + 21 + 21 + read-only + + + SPIDMEN + SPI data mask enable bit. + 24 + 24 + + + SPIRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + read-only + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + read-only + + + CLKSTRETCHEN + Enables clock stretching capability in SPI transfers. + 30 + 30 + + + + + DDRDRIVEEDGE + This Register is valid only when SSIC_HAS_DDR is equal to 1. + 0x0F8 + read-write + 0x00000000 + 0x20 + + + TDE + TXD Drive edge register which decided the driving edge of transmit data. + 0 + 7 + + + + + XIPMODEBITS + This register carries the mode bits which are sent in the XIP mode of operation after address phase. + 0x0FC + read-write + 0x00000000 + 0x20 + + + XIPMDBITS + XIP mode bits to be sent after address phase of XIP transfer. + 0 + 15 + + + + + + SSICXIPADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICXIPADDRESS + read-write + 0x100 + + XIPINCRINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x000 + read-write + 0x00000000 + 0x20 + + + INCRINST + XIP INCR transfer opcode. + 0 + 15 + + + + + XIPWRAPINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + WRAPINST + XIP WRAP transfer opcode. + 0 + 15 + + + + + XIPCTRL + This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. + 0x008 + read-write + 0x08000401 + 0x20 + + + FRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + TRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 9 + 10 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + MDBITSEN + Mode bits enable in XIP mode. + 12 + 12 + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 13 + 17 + + + DFSHC + Fix DFS for XIP transfers. + 18 + 18 + + + DDREN + SPI DDR Enable bit. + 19 + 19 + + + INSTDDREN + Instruction DDR Enable bit. + 20 + 20 + + + RXDSEN + Read data strobe enable bit. + 21 + 21 + + + INSTEN + XIP instruction enable bit. + 22 + 22 + + + CONTXFEREN + Enable continuous transfer in XIP mode. + 23 + 23 + read-only + + + XIPHYPERBUSEN + SPI Hyperbus Frame format enable for XIP transfers. + 24 + 24 + + + RXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + + + + + XRXOICR + XIP Receive FIFO Overflow Interrupt Clear Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XRXOICR + Clear XIP Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + XIPWRITEINCRINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x040 + read-write + 0x00000000 + 0x20 + + + INCRWRITEINST + XIP Write INCR transfer opcode. + 0 + 15 + + + RSVDINCRINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITEWRAPINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x044 + read-write + 0x00000000 + 0x20 + + + WRAPWRITEINST + XIP Write WRAP transfer opcode. + 0 + 15 + + + RSVDWRAPINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITECTRL + This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. + 0x048 + read-write + 0x00000002 + 0x20 + + + WRFRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + WRTRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + WRADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + + + WRINSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WRSPIDDREN + SPI DDR Enable bit. + 10 + 10 + + + WRINSTDDREN + Instruction DDR Enable bit. + 11 + 11 + + + XIPWRHYPERBUSEN + SPI Hyperbus Frame format enable for XIP Write transfers. + 12 + 12 + + + XIPWRRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 13 + 13 + + + RSVDXIPWRITECTRL14TO15 + Reserved bits - Read Only + 14 + 15 + read-only + + + XIPWRWAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 16 + 20 + + + RSVDXIPWRITECTRL21TO31 + Reserved bits - Read Only + 21 + 31 + read-only + + + + + + + + + GLOBAL_SECDOMBELLBOARD + BELLBOARD public registers + 0x5F099000 + BELLBOARDPUBLIC + + + + + 0 + 0x1000 + registers + + BELLBOARDPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_VPR120 + VPR peripheral registers + 0x5F8C8000 + VPRPUBLIC + + + + 0 + 0x1000 + registers + + VPRPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_IPCT120 + IPCT APB registers 0 + 0x5F8D1000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT120_0 + 209 + + IPCT + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE4_FLUSH4 + Shortcut between event RECEIVE[4] and task FLUSH[4] + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE5_FLUSH5 + Shortcut between event RECEIVE[5] and task FLUSH[5] + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE6_FLUSH6 + Shortcut between event RECEIVE[6] and task FLUSH[6] + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE7_FLUSH7 + Shortcut between event RECEIVE[7] and task FLUSH[7] + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + GLOBAL_IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_4 + Overflow status for SEND[4] task + 4 + 4 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_5 + Overflow status for SEND[5] task + 5 + 5 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_6 + Overflow status for SEND[6] task + 6 + 6 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_7 + Overflow status for SEND[7] task + 7 + 7 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + GLOBAL_MUTEX120 + MUTEX 0 + 0x4F8D2000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x20 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + 0x00000000 + 0x20 + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0x0 + + + Locked + Mutex n is in locked state + 0x1 + + + + + + + + + GLOBAL_I3C120 + I3C 0 + 0x5F8D3000 + I3C + + + + 0 + 0x1000 + registers + + + I3C120 + 211 + + I3C + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable I3C peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + EN + Enable + 0 + 0 + + + Disabled + I3C peripheral disabled. + 0x0 + + + Enabled + I3C peripheral enabled. + 0x1 + + + + + + + CDR + Unspecified + I3C_CDR + read-write + 0x404 + + STARTOFFSET + Start offset of recovered clock + 0x000 + read-write + 0x00000004 + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXCYCLERATIO + Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock + 0x004 + read-write + 0x0000001C + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXSKEW + Maximum skew between SCL and SCL in CDR clock cycles + 0x008 + read-write + 0x00000005 + 0x20 + + + VAL + Value + 0 + 7 + + + + + + SLAVEIF0 + I3C slave interface 0 + 0x410 + read-write + 0x00000000 + 0x20 + + + MODEI2C + I2C or I3C mode select signal + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + ACTMODE + Slave activity mode for GETSTATUS CCC + 1 + 2 + + + PENDINGINT + Pending interrupt information for GETSTATUS CCC + 3 + 6 + + + STATICADDREN + Slave static address valid + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + STATICADDR + Slave static address + 8 + 14 + + + SLAVEMAXRDSPEED + Slave maximum read data rate + 15 + 17 + + + SLAVEMAXWRSPEED + Slave maximum write write rate + 18 + 20 + + + SLAVECLKDATATURNTIME + Slave maximum clock data turnaround time + 21 + 23 + + + SLAVEDCR + Device Characteristic Register value + 24 + 31 + + + + + SLAVEIF1 + I3C slave interface 1 + 0x414 + read-write + 0x00000000 + 0x20 + + + WAKEUP + Slave wakeup signal + 0 + 0 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SLAVEPID0 + Slave Device Provisioned ID 0 + 0x418 + read-write + 0x00000000 + 0x20 + + + ADDMEANING + Additional Meaning + 0 + 11 + + + INSTANCEID + Instance ID + 12 + 15 + + + PARTID + Part ID + 16 + 31 + + + + + SLAVEPID1 + Slave Device Provisioned ID 1 + 0x41C + read-write + 0x00000000 + 0x20 + + + PROVID + Provisional ID Type Selector + 0 + 0 + + + MIPIMID + MIPI Manufacturer ID + 1 + 15 + + + + + KEEPSDA + Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x420 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SDA high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + KEEPSCL + Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x424 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SCL high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + + + GLOBAL_VPR121 + VPR peripheral registers 0 + 0x5F8D4000 + VPR + + + + 0 + 0x1000 + registers + + + VPR121 + 212 + + VPR + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TASKS_TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + EN + Subscription enable bit + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: VPR event [n] register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + VPR event [n] register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event EVENTS_TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + EN + Publication enable bit + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + DEBUGIF + Unspecified + VPR_DEBUGIF + read-write + 0x400 + + DATA0 + Abstract Data 0. Read/write data for argument 0 + 0x10 + read-write + 0x00000000 + 0x20 + + + DATA0 + Abstract Data 0 + 0 + 31 + + + + + DATA1 + Abstract Data 1. Read/write data for argument 1 + 0x14 + read-write + 0x00000000 + 0x20 + + + DATA1 + Abstract Data 1 + 0 + 31 + + + + + DMCONTROL + Debug Module Control + 0x40 + read-write + 0x00000000 + 0x20 + + + DMACTIVE + Reset signal for the debug module. + 0 + 0 + + + Disabled + Reset the debug module itself + 0x0 + + + Enabled + Normal operation + 0x1 + + + + + NDMRESET + Reset signal output from the debug module to the system. + 1 + 1 + + + Inactive + Reset inactive + 0x0 + + + Active + Reset active + 0x1 + + + + + CLRRESETHALTREQ + Clear the halt on reset request. + 2 + 2 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the halt on reset request + 0x1 + + + + + SETRESETHALTREQ + Set the halt on reset request. + 3 + 3 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Sets the halt on reset request + 0x1 + + + + + HARTSELHI + The high 10 bits of hartsel. + 6 + 15 + write-only + + + HARTSELLO + The low 10 bits of hartsel. + 16 + 25 + write-only + + + HASEL + Definition of currently selected harts. + 26 + 26 + write-only + + + Single + Single hart selected. + 0x0 + + + Multiple + Multiple harts selected + 0x1 + + + + + ACKHAVERESET + Clear the havereset. + 28 + 28 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the havereset for selected harts. + 0x1 + + + + + HARTRESET + Reset harts. + 29 + 29 + + + Deasserted + Reset de-asserted. + 0x0 + + + Asserted + Reset asserted. + 0x1 + + + + + RESUMEREQ + Resume currently selected harts. + 30 + 30 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Resumed + Currently selected harts resumed. + 0x1 + + + + + HALTREQ + Halt currently selected harts. + 31 + 31 + write-only + + + Clear + Clears halt request bit for all currently selected harts. + 0x0 + + + Halt + Currently selected harts halted. + 0x1 + + + + + + + DMSTATUS + Debug Module Status + 0x44 + read-only + 0x00400082 + 0x20 + + + VERSION + Version of the debug module. + 0 + 3 + + + NotPresent + Debug module not present. + 0x0 + + + V011 + There is a Debug Module and it conforms to version 0.11 of this specifcation. + 0x1 + + + V013 + There is a Debug Module and it conforms to version 0.13 of this specifcation. + 0x2 + + + NonConform + There is a Debug Module but it does not conform to any available version of the spec. + 0xF + + + + + CONFSTRPTRVALID + Configuration string. + 4 + 4 + + + NotRelevant + The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. + 0x0 + + + Address + The confstrptr0..confstrptr3 holds the address of the configuration string. + 0x1 + + + + + HASRESETHALTREQ + Halt-on-reset support status. + 5 + 5 + + + No + Halt-on-reset is supported. + 0x0 + + + Yes + Halt-on-reset is not supported. + 0x1 + + + + + AUTHBUSY + Authentication busy status. + 6 + 6 + + + No + The authentication module is ready. + 0x0 + + + Yes + The authentication module is busy. + 0x1 + + + + + AUTHENTICATED + Authentication status. + 7 + 7 + + + No + Authentication required before using the debug module. + 0x0 + + + Yes + Authentication passed. + 0x1 + + + + + ANYHALTED + Any currently selected harts halted status. + 8 + 8 + + + No + None of the currently selected harts halted. + 0x0 + + + Yes + Any of the currently selected harts halted. + 0x1 + + + + + ALLHALTED + All currently selected harts halted status. + 9 + 9 + + + No + Not all of the currently selected harts halted. + 0x0 + + + Yes + All of the currently selected harts halted. + 0x1 + + + + + ANYRUNNING + Any currently selected harts running status. + 10 + 10 + + + No + None of the currently selected harts running. + 0x0 + + + Yes + Any of the currently selected harts running. + 0x1 + + + + + ALLRUNNING + All currently selected harts running status. + 11 + 11 + + + No + Not all of the currently selected harts running. + 0x0 + + + Yes + All of the currently selected harts running. + 0x1 + + + + + ANYUNAVAIL + Any currently selected harts unavailable status. + 12 + 12 + + + No + None of the currently selected harts unavailable. + 0x0 + + + Yes + Any of the currently selected harts unavailable. + 0x1 + + + + + ALLUNAVAIL + All currently selected harts unavailable status. + 13 + 13 + + + No + Not all of the currently selected harts unavailable. + 0x0 + + + Yes + All of the currently selected harts unavailable. + 0x1 + + + + + ANYNONEXISTENT + Any currently selected harts nonexistent status. + 14 + 14 + + + No + None of the currently selected harts nonexistent. + 0x0 + + + Yes + Any of the currently selected harts nonexistent. + 0x1 + + + + + ALLNONEXISTENT + All currently selected harts nonexistent status. + 15 + 15 + + + No + Not all of the currently selected harts nonexistent. + 0x0 + + + Yes + All of the currently selected harts nonexistent. + 0x1 + + + + + ANYRESUMEACK + Any currently selected harts acknowledged last resume request. + 16 + 16 + + + No + None of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + Any of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ALLRESUMEACK + All currently selected harts acknowledged last resume + 17 + 17 + + + No + Not all of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + All of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ANYHAVERESET + Any currently selected harts have been reset and reset is not acknowledged. + 18 + 18 + + + No + None of the currently selected harts have been reset and reset is not acknowledget. + 0x0 + + + Yes + Any of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + ALLHAVERESET + All currently selected harts have been reset and reset is not acknowledge + 19 + 19 + + + No + Not all of the currently selected harts have been reset and reset is not acknowledge. + 0x0 + + + Yes + All of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + IMPEBREAK + Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. + 22 + 22 + + + No + No implicit ebreak instruction. + 0x0 + + + Yes + Implicit ebreak instruction. + 0x1 + + + + + + + HARTINFO + Hart Information + 0x48 + read-write + 0x00000000 + 0x20 + + + DATAADDR + Data Address + 0 + 11 + read-only + + + DATASIZE + Data Size + 12 + 15 + read-only + + + DATAACCESS + Data Access + 16 + 16 + read-only + + + No + The data registers are shadowed in the hart + by CSRs. Each CSR is DXLEN bits in size, and + corresponds to a single argument. + 0x0 + + + Yes + The data registers are shadowed in the hart's + memory map. Each register takes up 4 bytes in + the memory map. + 0x1 + + + + + NSCRATCH + Number of dscratch registers + 20 + 23 + read-only + + + + + HALTSUM1 + Halt Summary 1 + 0x4C + read-write + 0x00000000 + 0x20 + + + HALTSUM1 + Halt Summary 1 + 0 + 31 + read-only + + + + + HAWINDOWSEL + Hart Array Window Select + 0x50 + read-write + 0x00000000 + 0x20 + + + HAWINDOWSEL + The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. + 0 + 14 + read-only + + + + + HAWINDOW + Hart Array Window + 0x54 + read-write + 0x00000000 + 0x20 + + + MASKDATA + Mask data. + 0 + 31 + + + + + ABSTRACTCS + Abstract Control and Status + 0x58 + read-write + 0x01000002 + 0x20 + + + DATACOUNT + Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. + 0 + 3 + read-only + + + CMDERR + Command error when the abstract command fails. + 8 + 10 + + + NoError + No error. + 0x0 + + + Busy + An abstract command was executing while command, + abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read + or written. This status is only written if cmderr contains 0 + 0x1 + + + NotSupported + The requested command is notsupported, + regardless of whether the hart is running or not. + 0x2 + + + Exception + An exception occurred while executing the + command (e.g. while executing theProgram Buffer). + 0x3 + + + HaltResume + The abstract command couldn't execute + because the hart wasn't in the required state (running/halted). or unavailable. + 0x4 + + + Bus + The abstract command failed due to abus + error (e.g. alignment, access size, or timeout). + 0x5 + + + Other + The command failed for another reason. + 0x7 + + + + + BUSY + Abstract command execution status. + 12 + 12 + read-only + + + NotBusy + Not busy. + 0x0 + + + Busy + An abstract command is currently being executed. + This bit is set as soon as command is written, and is not cleared until that command has completed. + 0x1 + + + + + PROGBUFSIZE + Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. + 24 + 28 + read-only + + + + + ABSTRACTCMD + Abstract command + 0x5C + write-only + 0x00000000 + 0x20 + + + CONTROL + This Field is interpreted in a command specific manner, described for each abstract command. + 0 + 23 + + + CMDTYPE + The type determines the overall functionality of this abstract command. + 24 + 31 + + + REGACCESS + Register Access Command + 0x00 + + + QUICKACCESS + Quick Access Command + 0x01 + + + MEMACCESS + Memory Access Command + 0x02 + + + + + + + ABSTRACTAUTO + Abstract Command Autoexec + 0x60 + read-write + 0x00000000 + 0x20 + + + AUTOEXECDATA + When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. + 0 + 11 + read-only + + + AUTOEXECPROGBUF + When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. + 16 + 31 + read-only + + + + + 0x4 + 0x4 + CONFSTRPTR[%s] + Description collection: Configuration String Pointer [n] + 0x64 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + NEXTDM + Next Debug Module + 0x74 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + 0x10 + 0x4 + PROGBUF[%s] + Description collection: Program Buffer [n] + 0x80 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + AUTHDATA + Authentication Data + 0xC0 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + HALTSUM2 + Halt Summary 2 + 0xD0 + read-write + 0x00000000 + 0x20 + + + HALTSUM2 + Halt Summary 2 + 0 + 31 + read-only + + + + + HALTSUM3 + Halt Summary 3 + 0xD4 + read-write + 0x00000000 + 0x20 + + + HALTSUM3 + Halt Summary 3 + 0 + 31 + read-only + + + + + SBADDRESS3 + System Bus Addres 127:96 + 0xDC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 127:96 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBCS + System Bus Access Control and Status + 0xE0 + read-write + 0x20000000 + 0x20 + + + SBACCESS8 + 0 + 0 + read-only + + + sbaccess8 + 8-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS16 + 1 + 1 + read-only + + + sbaccess16 + 16-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS32 + 2 + 2 + read-only + + + sbaccess32 + 32-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS64 + 3 + 3 + read-only + + + sbaccess64 + 64-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS128 + 4 + 4 + read-only + + + sbaccess128 + 128-bit system bus accesses are supported. + 0x1 + + + + + SBASIZE + Width of system bus addresses in bits. (0 indicates there is no bus access support.) + 5 + 11 + read-only + + + SBERROR + 12 + 14 + read-only + + + Normal + There was no bus error. + 0x0 + + + Timeout + There was a timeout. + 0x1 + + + Address + A bad address was accessed. + 0x2 + + + Alignment + There was an alignment error. + 0x3 + + + Size + An access of unsupported size was requested. + 0x4 + + + Other + Other. + 0x7 + + + + + SBREADONDATA + 15 + 15 + read-only + + + sbreadondata + Every read from sbdata0 automatically + triggers a system bus read at the (possibly autoincremented) address. + 0x1 + + + + + SBAUTOINCREMENT + 16 + 16 + read-only + + + sbautoincrement + sbaddress is incremented by the access + size (in bytes) selected in sbaccess after every system bus access. + 0x1 + + + + + SBACCESS + 17 + 19 + read-only + + + size8 + 8-bit. + 0x0 + + + size16 + 16-bit. + 0x1 + + + size32 + 32-bit. + 0x2 + + + size64 + 64-bit. + 0x3 + + + size128 + 128-bit. + 0x4 + + + + + SBREADONADDR + 20 + 20 + read-only + + + sbreadonaddr + Every write to sbaddress0 automatically + triggers a system bus read at the new address. + 0x1 + + + + + SBBUSY + 21 + 21 + read-only + + + notbusy + System bus master is not busy. + 0x0 + + + busy + System bus master is busy. + 0x1 + + + + + SBBUSYERROR + 22 + 22 + read-only + + + noerror + No error. + 0x0 + + + error + Debugger access attempted while one in progress. + 0x1 + + + + + SBVERSION + 29 + 31 + read-only + + + version0 + The System Bus interface conforms to mainline + drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. + 0x0 + + + version1 + The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. + Other values are reserved for future versions. + 0x1 + + + + + + + SBADDRESS0 + System Bus Addres 31:0 + 0xE4 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 31:0 of the physical address in + sbaddress. + 0 + 31 + read-only + + + + + SBADDRESS1 + System Bus Addres 63:32 + 0xE8 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 63:32 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBADDRESS2 + System Bus Addres 95:64 + 0xEC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 95:64 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBDATA0 + System Bus Data 31:0 + 0xF0 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 31:0 of sbdata + 0 + 31 + read-only + + + + + SBDATA1 + System Bus Data 63:32 + 0xF4 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 63:32 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA2 + System Bus Data 95:64 + 0xF8 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 95:64 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA3 + System Bus Data 127:96 + 0xFC + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 127:96 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + HALTSUM0 + Halt summary 0 + 0x100 + read-write + 0x00000000 + 0x20 + + + HALTSUM0 + Halt summary 0 + 0 + 31 + read-only + + + + + + CPURUN + State of the CPU after a core reset + 0x800 + read-write + 0x00000000 + 0x20 + + + EN + Controls CPU running state after a core reset. + 0 + 0 + + + Stopped + CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. + 0x0 + + + Running + CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. + 0x1 + + + + + + + INITPC + Initial value of the PC at CPU start. + 0x808 + read-write + 0x00000000 + 0x20 + + + INITPC + Initial value of the PC at CPU start. + 0 + 31 + + + + + + + GLOBAL_CAN120 + Controller Area Network 0 + 0x5F8D8000 + CAN + + + + 0 + 0x1000 + registers + + + CAN120 + 216 + + CAN + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the CAN peripheral + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_CORE[%s] + Description collection: Event indicating that interrupt n triggered at CAN core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt n triggered at CAN core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READYFORSTOP_STOP + Shortcut between event READYFORSTOP and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE0 + Enable or disable interrupt for event CORE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CORE1 + Enable or disable interrupt for event CORE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMU + Enable or disable interrupt for event DMU + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READYFORSTOP + Enable or disable interrupt for event READYFORSTOP + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to enable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CORE1 + Write '1' to enable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMU + Write '1' to enable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READYFORSTOP + Write '1' to enable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to disable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CORE1 + Write '1' to disable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMU + Write '1' to disable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READYFORSTOP + Write '1' to disable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE0 + Read pending status of interrupt for event CORE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CORE1 + Read pending status of interrupt for event CORE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMU + Read pending status of interrupt for event DMU + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READYFORSTOP + Read pending status of interrupt for event READYFORSTOP + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_MVDMA120 + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x5F8D9000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA120 + 217 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + GLOBAL_MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + GLOBAL_MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + GLOBAL_MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + GLOBAL_MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + GLOBAL_MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + GLOBAL_MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + GLOBAL_RAMC122 + RAM Controller 0 + 0x5F8DA000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + + + GLOBAL_CAN121 + Controller Area Network 1 + 0x5F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_MVDMA121 + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x5F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_RAMC123 + RAM Controller 1 + 0x5F8DD000 + + + + + GLOBAL_I3C121 + I3C 1 + 0x5F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_DPPIC120 + Distributed programmable peripheral interconnect controller 0 + 0x5F8E1000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 4 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 4 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x4 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + 0x20 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + GLOBAL_TIMER120 + Timer/Counter 0 + 0x5F8E2000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER120 + 226 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + 0x20 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + 0x20 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + 0x20 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + 0x00000000 + 0x20 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + + + GLOBAL_TIMER121 + Timer/Counter 1 + 0x5F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_PWM120 + Pulse width modulation unit 0 + 0x5F8E4000 + PWM + + + + 0 + 0x1000 + registers + + + PWM120 + 228 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + PWM_TASKS_DMA + write-only + 0x010 + + 2 + 0x008 + SEQ[%s] + Peripheral tasks. + PWM_TASKS_DMA_SEQ + write-only + 0x000 + + START + Description cluster: Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA + read-write + 0x090 + + 2 + 0x008 + SEQ[%s] + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA_SEQ + read-write + 0x000 + + START + Description cluster: Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PWM_EVENTS_DMA + read-write + 0x124 + + 2 + 0x00C + SEQ[%s] + Peripheral events. + PWM_EVENTS_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + Description cluster: An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + 0x4 + 0x4 + EVENTS_COMPAREMATCH[%s] + Description collection: This event is generated when the compare matches for the compare channel [n]. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPAREMATCH + This event is generated when the compare matches for the compare channel [n]. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RAMUNDERFLOW + Publish configuration for event RAMUNDERFLOW + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RAMUNDERFLOW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PWM_PUBLISH_DMA + read-write + 0x1A4 + + 2 + 0x00C + SEQ[%s] + Publish configuration for events + PWM_PUBLISH_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Description cluster: Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Description cluster: Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + 0x4 + 0x4 + PUBLISH_COMPAREMATCH[%s] + Description collection: Publish configuration for event COMPAREMATCH[n] + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPAREMATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + SEQEND0_STOP + Shortcut between event SEQEND[n] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[n] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RAMUNDERFLOW_STOP + Shortcut between event RAMUNDERFLOW and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ0_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ1_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RAMUNDERFLOW + Enable or disable interrupt for event RAMUNDERFLOW + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0END + Enable or disable interrupt for event DMASEQ0END + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0READY + Enable or disable interrupt for event DMASEQ0READY + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Enable or disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1END + Enable or disable interrupt for event DMASEQ1END + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1READY + Enable or disable interrupt for event DMASEQ1READY + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Enable or disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH0 + Enable or disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH1 + Enable or disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH2 + Enable or disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH3 + Enable or disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to enable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0END + Write '1' to enable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0READY + Write '1' to enable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to enable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1END + Write '1' to enable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1READY + Write '1' to enable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to enable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to enable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to enable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to enable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to enable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to disable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0END + Write '1' to disable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0READY + Write '1' to disable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1END + Write '1' to disable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1READY + Write '1' to disable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED0 + Read pending status of interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED1 + Read pending status of interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND0 + Read pending status of interrupt for event SEQEND[0] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND1 + Read pending status of interrupt for event SEQEND[1] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LOOPSDONE + Read pending status of interrupt for event LOOPSDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RAMUNDERFLOW + Read pending status of interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0END + Read pending status of interrupt for event DMASEQ0END + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0READY + Read pending status of interrupt for event DMASEQ0READY + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0BUSERROR + Read pending status of interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1END + Read pending status of interrupt for event DMASEQ1END + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1READY + Read pending status of interrupt for event DMASEQ1READY + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1BUSERROR + Read pending status of interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH0 + Read pending status of interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH1 + Read pending status of interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH2 + Read pending status of interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH3 + Read pending status of interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + IDLEOUT + Configure the output value on the PWM channel during idle + 0x518 + read-write + 0x00000000 + 0x20 + + + VAL_0 + Idle output value for PWM channel [0] + 0 + 0 + + + VAL_1 + Idle output value for PWM channel [1] + 1 + 1 + + + VAL_2 + Idle output value for PWM channel [2] + 2 + 2 + + + VAL_3 + Idle output value for PWM channel [3] + 3 + 3 + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + PWM_DMA + read-write + 0x700 + + 2 + 0x024 + SEQ[%s] + Unspecified + PWM_DMA_SEQ + read-write + 0x000 + + PTR + Description cluster: RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Description cluster: Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIS120 + SPI Slave 0 + 0x5F8E5000 + SPIS + + + + 0 + 0x1000 + registers + + + SPIS120 + 229 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIS_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIS_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIS_DMA + read-write + 0x700 + + RX + Unspecified + SPIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM120 + Serial Peripheral Interface Master with EasyDMA 0 + 0x5F8E6000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIM_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STARTED + SPI transaction has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + SPI transaction has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PRESCALER + The prescaler is used to set the SPI frequency. + 0x52C + read-write + 0x00000040 + 0x20 + + + DIVISOR + Core clock to SCK divisor + 0 + 6 + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x5AC + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of SPIM core clock cycles. + 0 + 7 + + + + + + DCXCNT + DCX configuration + 0x5B4 + read-write + 0x00000000 + 0x20 + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + CSNPOL + Polarity of CSN output + 0x5B8 + read-write + 0x00000000 + 0x20 + + + CSNPOL_0 + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0x0 + + + HIGH + Active high (idle state low) + 0x1 + + + + + + + CSNCONTROL + Selects which CSN is used, only one CSN can be active at one time. This register can be safely written during an ongoing SPI transaction. + 0x5BC + read-write + 0x00000000 + 0x20 + + + CSN + CSN Number. + 0 + 0 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DCX + Pin select for DCX signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + 0x1 + 0x4 + CSN[%s] + Description collection: Pin select for CSN + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIM_DMA + read-write + 0x700 + + RX + Unspecified + SPIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE120 + UART with EasyDMA 0 + 0x5F8E6000 + GLOBAL_SPIM120 + UARTE + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + UARTE + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + UARTE_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + UARTE_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + UARTE_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x124 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + UARTE_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + UARTE_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + UARTE_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0x174 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + UARTE_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + UARTE_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + UARTE_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + PUBLISH_FRAMETIMEOUT + Publish configuration for event FRAMETIMEOUT + 0x1F4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMETIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + DMA_RX_END_DMA_RX_START + Shortcut between event DMA.RX.END and task DMA.RX.START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_END_DMA_RX_STOP + Shortcut between event DMA.RX.END and task DMA.RX.STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_TX_END_DMA_TX_STOP + Shortcut between event DMA.TX.END and task DMA.TX.STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMETIMEOUT_DMA_RX_STOP + Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP + 29 + 29 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMETIMEOUT + Enable or disable interrupt for event FRAMETIMEOUT + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to enable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to disable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + CONFIG + Configuration of parity, hardware flow control, framesize, and packet timeout. + 0x56C + read-write + 0x00001000 + 0x20 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0x0 + + + Odd + Odd parity + 0x1 + + + + + FRAMESIZE + Set the data frame size + 9 + 12 + + + 9bit + 9 bit data frame size. 9th bit is treated as address bit. + 0x9 + + + 8bit + 8 bit data frame size. + 0x8 + + + 7bit + 7 bit data frame size. + 0x7 + + + 6bit + 6 bit data frame size. + 0x6 + + + 5bit + 5 bit data frame size. + 0x5 + + + 4bit + 4 bit data frame size. + 0x4 + + + + + ENDIAN + Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. + 13 + 13 + + + MSB + Data is trimmed from MSB end. + 0x0 + + + LSB + Data is trimmed from LSB end. + 0x1 + + + + + FRAMETIMEOUT + Enable packet timeout. + 14 + 14 + + + DISABLED + Packet timeout is disabled. + 0x0 + + + ENABLED + Packet timeout is enabled. + 0x1 + + + + + + + ADDRESS + Set the address of the UARTE for RX when used in 9 bit data frame mode. + 0x574 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Set address + 0 + 7 + + + + + FRAMETIMEOUT + Set the number of UARTE bits to count before triggering packet timeout. + 0x578 + read-write + 0x00000010 + 0x20 + + + COUNTERTOP + Number of UARTE bits before timeout. + 0 + 9 + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x604 + + TXD + Pin select for TXD signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RTS + Pin select for RTS signal + 0x0C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + UARTE_DMA + read-write + 0x700 + + RX + Unspecified + UARTE_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + UARTE_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + UARTE_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM121 + Serial Peripheral Interface Master with EasyDMA 1 + 0x5F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_VPR130 + VPR peripheral registers 1 + 0x5F908000 + + + + VPR130 + 264 + + + + GLOBAL_IPCT130 + IPCT APB registers 1 + 0x5F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_DPPIC130 + Distributed programmable peripheral interconnect controller 1 + 0x5F922000 + + + + + + GLOBAL_MUTEX130 + MUTEX 1 + 0x4F927000 + + + + + GLOBAL_RTC130 + Real-time counter 0 + 0x5F928000 + RTC + + + + 0 + 0x1000 + registers + + + RTC130 + 296 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable event routing for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable event routing for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable event routing for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable event routing for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 31 + + + + + + + GLOBAL_RTC131 + Real-time counter 1 + 0x5F929000 + + + + RTC131 + 297 + + + + GLOBAL_WDT131 + Watchdog Timer 0 + 0x5F92B000 + WDT + + + + 0 + 0x1000 + registers + + + WDT131 + 299 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + 0x20 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0x0 + + + Run + Keep WDT running while the CPU is sleeping + 0x1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0x0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 0x1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0x0 + + + Enable + Allow stopping WDT + 0x1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + 0x20 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + GLOBAL_WDT132 + Watchdog Timer 1 + 0x5F92C000 + + + + WDT132 + 300 + + + + GLOBAL_EGU130 + Event generator unit + 0x5F92D000 + EGU + + + + 0 + 0x1000 + registers + + + EGU130 + 301 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_P0 + GPIO Port 0 + 0x5F938000 + GPIO + + + + + 0 + 0x200 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x000 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x004 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x00C + read-only + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x010 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x014 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x018 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + 0x20 + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x024 + read-write + 0x00000000 + 0x20 + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + RETAIN + Enable retention for those GPIO registers marked as retained + 0x028 + read-write + 0x0000000C + 0x20 + + + APPLICAION + Enable retention for GPIO registers for Application domain + 2 + 2 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + RADIOCORE + Enable retention for GPIO registers for Radio core + 3 + 3 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + + + PORTCNF + Unspecified + GPIO_PORTCNF + read-write + 0x030 + + DRIVECTRL + Drive control for impedance matching of the pins in this port + 0x00 + read-write + 0x00000000 + 0x20 + + + + IMPEDANCE50 + Enable 50 ohms impedance to the pins in this port + 0 + 0 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE100 + Enable 100 ohms impedance to the pins in this port + 1 + 1 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE200 + Enable 200 ohms impedance to the pins in this port + 2 + 2 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE400 + Enable 400 ohms impedance to the pins in this port + 3 + 3 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE800 + Enable 800 ohms impedance to the pins in this port + 4 + 4 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE1600 + Enable 1600 ohms impedance to the pins in this port + 5 + 5 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Pin n configuration of GPIO pin + 0x080 + read-write + 0x00000002 + 0x20 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE0 + Drive configuration for '0' + 8 + 9 + + + S0 + Standard '0' + 0x0 + + + H0 + High drive '0' + 0x1 + + + D0 + Disconnect '0'(normally used for wired-or connections) + 0x2 + + + E0 + Extra high drive '0' + 0x3 + + + + + DRIVE1 + Drive configuration for '1' + 10 + 11 + + + S1 + Standard '1' + 0x0 + + + H1 + High drive '1' + 0x1 + + + D1 + Disconnect '1'(normally used for wired-or connections) + 0x2 + + + E1 + Extra high drive '1' + 0x3 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + CLOCKPIN + Enable clock on the pin. + 31 + 31 + + + Disabled + Clock disabled + 0x0 + + + Enabled + Clock enabled + 0x1 + + + + + + + + + GLOBAL_P1 + GPIO Port 1 + 0x5F938200 + + + + + + GLOBAL_P2 + GPIO Port 2 + 0x5F938400 + + + + + + GLOBAL_P6 + GPIO Port 3 + 0x5F938C00 + + + + + + GLOBAL_P8 + GPIO Port 4 + 0x5F939000 + + + + + + GLOBAL_P9 + GPIO Port 5 + 0x5F939200 + + + + + + GLOBAL_P10 + GPIO Port 6 + 0x5F939400 + + + + + + GLOBAL_P11 + GPIO Port 7 + 0x5F939600 + + + + + + GLOBAL_P12 + GPIO Port 8 + 0x5F939800 + + + + + + GLOBAL_P13 + GPIO Port 9 + 0x5F939A00 + + + + + + GLOBAL_DPPIC131 + Distributed programmable peripheral interconnect controller 2 + 0x5F981000 + + + + + + GLOBAL_SAADC + Analog to Digital Converter + 0x5F982000 + + + + 0 + 0x1000 + registers + + + SAADC + 386 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + GLOBAL_SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + GLOBAL_SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + TRIM + Unspecified + GLOBAL_SAADC_TRIM + read-write + 0x440 + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Linearity calibration coefficient + 0x000 + read-write + 0x00000000 + 0x20 + + + VAL + value + 0 + 15 + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + GLOBAL_SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x0 + read-write + 0x00000000 + 0x20 + + + PIN + Analog positive input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x4 + read-write + 0x00000000 + 0x20 + + + PIN + Analog negative input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + GAIN + Gain control + 8 + 9 + + + Gain2_3 + 2/3 + 0x0 + + + Gain1 + 1 + 0x1 + + + Gain2 + 2 + 0x2 + + + Gain4 + 4 + 0x3 + + + + + BURST + Enable burst mode + 11 + 11 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (1.024 V) + 0x0 + + + External + External reference given at PADC_EXT_REF_1V2 + 0x1 + + + + + MODE + Enable differential mode + 15 + 15 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) + 16 + 24 + + + TCONV + Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) + 28 + 30 + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + 0x20 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + GLOBAL_SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of buffer bytes to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer bytes transferred since last START + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + GLOBAL_COMP + Comparator + 0x5F983000 + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (AVDD_AO_1V8 &gt;= 1.7 V) + 0x0 + + + AVDDAO1V8 + VREF = AVDD_AO_1V8 + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00002020 + 0x20 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 0 + + + Low + Low-power mode + 0x0 + + + High + High-speed mode + 0x1 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0x0 + + + Diff + Differential mode + 0x1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0x0 + + + Hyst40mV + Comparator hysteresis enabled + 0x1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + 0x00000000 + 0x20 + + + ISOURCE + Current source select on analog input + 0 + 1 + + + Off + Current source disabled + 0x0 + + + Ien2uA5 + Current source enabled (+/- 2.5 uA) + 0x1 + + + Ien5uA + Current source enabled (+/- 5 uA) + 0x2 + + + Ien10uA + Current source enabled (+/- 10 uA) + 0x3 + + + + + + + + + GLOBAL_LPCOMP + Low-power comparator + 0x5F983000 + GLOBAL_COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0x0 + + + Enabled + Comparator hysteresis enabled + 0x1 + + + + + + + + + GLOBAL_TEMP + Temperature Sensor + 0x5F984000 + + + + 0 + 0x1000 + registers + + + TEMP + 388 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DATARDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + 0x00000000 + int32_t + 0x20 + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000276 + 0x20 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000324 + 0x20 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AB + 0x20 + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000453 + 0x20 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000049B + 0x20 + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x00000550 + 0x20 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + A6 + Slope of 7th piece wise linear function + 0x538 + read-write + 0x0000067E + 0x20 + + + A6 + Slope of 7th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00000FA6 + 0x20 + + + B0 + y-intercept of 1st piece wise linear function + 0 + 11 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00000F35 + 0x20 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 11 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00000FAA + 0x20 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 11 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x0000007E + 0x20 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 11 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x000000EA + 0x20 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 11 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x000001ED + 0x20 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 11 + + + + + B6 + y-intercept of 7th piece wise linear function + 0x558 + read-write + 0x00000378 + 0x20 + + + B6 + y-intercept of 7th piece wise linear function + 0 + 11 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000ED + 0x20 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000013 + 0x20 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000029 + 0x20 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + 0x20 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000044 + 0x20 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + T5 + End point of 6th piece wise linear function + 0x574 + read-write + 0x00000053 + 0x20 + + + T5 + End point of 6th piece wise linear function + 0 + 7 + + + + + + + GLOBAL_DPPIC132 + Distributed programmable peripheral interconnect controller 3 + 0x5F991000 + + + + + + GLOBAL_I2S130 + Inter-IC Sound 0 + 0x5F992000 + I2S + + + + 0 + 0x1000 + registers + + + I2S130 + 402 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + GLOBAL_I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + 0x20 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + 0x20 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + 0x20 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + 0x20 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0x0 + + + 16Bit + 16 bit sample. + 0x1 + + + 24Bit + 24 bit sample. + 0x2 + + + 32Bit + 32 bit sample. + 0x3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 0x4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 0x5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 0x6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 0x7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + 0x20 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + 0x20 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + 0x20 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + 0x20 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0x0 + + + Enable + Enable bypass + 0x1 + + + + + + + + RXD + Unspecified + GLOBAL_I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + GLOBAL_I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + GLOBAL_I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + GLOBAL_I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + GLOBAL_PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x5F993000 + + + + 0 + 0x1000 + registers + + + PDM + 403 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STARTED + Read pending status of interrupt for event STARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + END + Read pending status of interrupt for event END + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + 0x20 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + 0x20 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled. + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + 0x20 + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate + 0 + 2 + + + Ratio64 + Ratio of 64 + 0x0 + + + Ratio80 + Ratio of 80 + 0x1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + 0x20 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + 0x20 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + 0x20 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + DMA + Unspecified + PDM_DMA + read-write + 0x700 + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x004 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_QDEC130 + Quadrature Decoder 0 + 0x5F994000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC130 + 404 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SAMPLERDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event REPORTRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACCOF will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DBLRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + 0x00000000 + 0x20 + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0x0 + + + ActiveHigh + Led active on output pin high + 0x1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0x0 + + + 256us + 256 us + 0x1 + + + 512us + 512 us + 0x2 + + + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0x0 + + + 40Smpl + 40 samples/report + 0x1 + + + 80Smpl + 80 samples/report + 0x2 + + + 120Smpl + 120 samples/report + 0x3 + + + 160Smpl + 160 samples/report + 0x4 + + + 200Smpl + 200 samples/report + 0x5 + + + 240Smpl + 240 samples/report + 0x6 + + + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0x0 + + + Enabled + Debounce input filters enabled + 0x1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + GLOBAL_QDEC131 + Quadrature Decoder 1 + 0x5F995000 + + + + QDEC131 + 405 + + + + GLOBAL_I2S131 + Inter-IC Sound 1 + 0x5F997000 + + + + I2S131 + 407 + + + + GLOBAL_DPPIC133 + Distributed programmable peripheral interconnect controller 4 + 0x5F9A1000 + + + + + + GLOBAL_TIMER130 + Timer/Counter 2 + 0x5F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER131 + Timer/Counter 3 + 0x5F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_PWM130 + Pulse width modulation unit 1 + 0x5F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_SPIM130 + Serial Peripheral Interface Master with EasyDMA 2 + 0x5F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130 + SPI Slave 1 + 0x5F9A5000 + GLOBAL_SPIM130 + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x5F9A5000 + GLOBAL_SPIM130 + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIM + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + TWIM_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + TWIM_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + LASTTX_DMA_RX_START + Shortcut between event LASTTX and task DMA.RX.START + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_DMA_TX_START + Shortcut between event LASTRX and task DMA.TX.START + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIM_DMA + read-write + 0x700 + + RX + Unspecified + TWIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_TWIS130 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x5F9A5000 + GLOBAL_SPIM130 + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIS_TASKS_DMA + write-only + 0x030 + + RX + Peripheral tasks. + TWIS_TASKS_DMA_RX + write-only + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA + read-write + 0x0B0 + + RX + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA_RX + read-write + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + 0x20 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + 0x20 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIS_DMA + read-write + 0x700 + + RX + Unspecified + TWIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE130 + UART with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM131 + Serial Peripheral Interface Master with EasyDMA 3 + 0x5F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131 + SPI Slave 2 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131 + UART with EasyDMA 2 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_DPPIC134 + Distributed programmable peripheral interconnect controller 5 + 0x5F9B1000 + + + + + + GLOBAL_TIMER132 + Timer/Counter 4 + 0x5F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER133 + Timer/Counter 5 + 0x5F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_PWM131 + Pulse width modulation unit 2 + 0x5F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_SPIM132 + Serial Peripheral Interface Master with EasyDMA 4 + 0x5F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132 + SPI Slave 3 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132 + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132 + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132 + UART with EasyDMA 3 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM133 + Serial Peripheral Interface Master with EasyDMA 5 + 0x5F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133 + SPI Slave 4 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133 + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133 + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133 + UART with EasyDMA 4 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_DPPIC135 + Distributed programmable peripheral interconnect controller 6 + 0x5F9C1000 + + + + + + GLOBAL_TIMER134 + Timer/Counter 6 + 0x5F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER135 + Timer/Counter 7 + 0x5F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_PWM132 + Pulse width modulation unit 3 + 0x5F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_SPIM134 + Serial Peripheral Interface Master with EasyDMA 6 + 0x5F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134 + SPI Slave 5 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134 + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134 + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134 + UART with EasyDMA 5 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM135 + Serial Peripheral Interface Master with EasyDMA 7 + 0x5F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135 + SPI Slave 6 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135 + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135 + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135 + UART with EasyDMA 6 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_DPPIC136 + Distributed programmable peripheral interconnect controller 7 + 0x5F9D1000 + + + + + + GLOBAL_TIMER136 + Timer/Counter 8 + 0x5F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER137 + Timer/Counter 9 + 0x5F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_PWM133 + Pulse width modulation unit 4 + 0x5F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_SPIM136 + Serial Peripheral Interface Master with EasyDMA 8 + 0x5F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136 + SPI Slave 7 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136 + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136 + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136 + UART with EasyDMA 7 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM137 + Serial Peripheral Interface Master with EasyDMA 9 + 0x5F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137 + SPI Slave 8 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137 + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137 + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137 + UART with EasyDMA 8 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + \ No newline at end of file diff --git a/mdk/nrf9230_enga_flpr_peripherals.h b/mdk/nrf9230_enga_flpr_peripherals.h new file mode 100644 index 000000000..3f45c161b --- /dev/null +++ b/mdk/nrf9230_enga_flpr_peripherals.h @@ -0,0 +1,1221 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_FLPR_PERIPHERALS_H +#define NRF9230_ENGA_FLPR_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +/*VPR CSR registers*/ +#define VPRCSR_PRESENT 1 +#define VPRCSR_COUNT 1 + +#define VPRCSR_HARTNUM 11 /*!< HARTNUM: 11 */ +#define VPRCSR_MCLICBASERESET 0x5F8D5000 /*!< MCLICBASE: 0x5F8D5000 */ +#define VPRCSR_MULDIV 1 /*!< MULDIV: 1 */ +#define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ +#define VPRCSR_DBG 1 /*!< DBG: 1 */ +#define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ +#define VPRCSR_BUSWIDTH 32 /*!< BUSWIDTH: 32 */ +#define VPRCSR_BKPT 1 /*!< BKPT: 1 */ +#define VPRCSR_VIOPINS 0x0000FFFF /*!< CSR VIOPINS value: 0x0000FFFF */ +#define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPRCSR_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPRCSR_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPRCSR_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPRCSR_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ +#define VPRCSR_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ +#define VPRCSR_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ +#define VPRCSR_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ +#define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ +#define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ +#define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ +#define VPRCSR_CACHE_EN 0 /*!< (unspecified) */ +#define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ +#define VPRCSR_VPR_BUS_PRIO 0 /*!< (unspecified) */ +#define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ + +/*VPR CLIC registers*/ +#define CLIC_PRESENT 1 +#define CLIC_COUNT 1 + +#define VPRCLIC_IRQ_COUNT 32 +#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPRCLIC_CLIC_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPRCLIC_CLIC_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPRCLIC_CLIC_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPRCLIC_COUNTER_IRQ_NUM 32 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 32 */ +#define VPRCLIC_CLIC_VPR_1_2 1 /*!< (unspecified) */ + +/*VTIM CSR registers*/ +#define VTIM_PRESENT 1 +#define VTIM_COUNT 1 + +/*Factory Information Configuration Registers*/ +#define FICR_PRESENT 1 +#define FICR_COUNT 1 + +/*USBHSCORE*/ +#define USBHSCORE_PRESENT 1 +#define USBHSCORE_COUNT 1 + +/*I3CCORE*/ +#define I3CCORE_PRESENT 1 +#define I3CCORE_COUNT 2 + +/*DMU*/ +#define DMU_PRESENT 1 +#define DMU_COUNT 2 + +/*MCAN*/ +#define MCAN_PRESENT 1 +#define MCAN_COUNT 2 + +/*System Trace Macrocell data buffer*/ +#define STMDATA_PRESENT 1 +#define STMDATA_COUNT 1 + +/*TDDCONF*/ +#define TDDCONF_PRESENT 1 +#define TDDCONF_COUNT 1 + +#define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 0 /*!< (unspecified) */ +#define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 1 /*!< (unspecified) */ + +/*System Trace Macrocell*/ +#define STM_PRESENT 1 +#define STM_COUNT 1 + +/*Trace Port Interface Unit*/ +#define TPIU_PRESENT 1 +#define TPIU_COUNT 1 + +/*Cross-Trigger Interface control*/ +#define CTI_PRESENT 1 +#define CTI_COUNT 2 + +/*ATB Replicator module*/ +#define ATBREPLICATOR_PRESENT 1 +#define ATBREPLICATOR_COUNT 4 + +/*ATB funnel module*/ +#define ATBFUNNEL_PRESENT 1 +#define ATBFUNNEL_COUNT 4 + +/*GPIO Tasks and Events*/ +#define GPIOTE_PRESENT 1 +#define GPIOTE_COUNT 2 + +#define GPIOTE130_IRQ_COUNT 2 +#define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +#define GPIOTE131_IRQ_COUNT 2 +#define GPIOTE131_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +/*Global Real-time counter*/ +#define GRTC_PRESENT 1 +#define GRTC_COUNT 1 + +#define GRTC_IRQ_COUNT 3 +#define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_PWMREGS 1 /*!< (unspecified) */ +#define GRTC_CLKOUTREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ + +/*Trace buffer monitor*/ +#define TBM_PRESENT 1 +#define TBM_COUNT 1 + +/*USBHS*/ +#define USBHS_PRESENT 1 +#define USBHS_COUNT 1 + +/*External Memory Interface*/ +#define EXMIF_PRESENT 1 +#define EXMIF_COUNT 1 + +/*BELLBOARD public registers*/ +#define BELLBOARDPUBLIC_PRESENT 1 +#define BELLBOARDPUBLIC_COUNT 1 + +/*VPR peripheral registers*/ +#define VPRPUBLIC_PRESENT 1 +#define VPRPUBLIC_COUNT 1 + +#define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ + +/*IPCT APB registers*/ +#define IPCT_PRESENT 1 +#define IPCT_COUNT 2 + +#define IPCT120_IRQ_COUNT 1 + +#define IPCT130_IRQ_COUNT 1 + +/*MUTEX*/ +#define MUTEX_PRESENT 1 +#define MUTEX_COUNT 2 + +/*I3C*/ +#define I3C_PRESENT 1 +#define I3C_COUNT 2 + +/*VPR peripheral registers*/ +#define VPR_PRESENT 1 +#define VPR_COUNT 2 + +#define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ +#define VPR121_RAM_SZ 15 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ +#define VPR121_RETAINED 0 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ +#define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ + +#define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ +#define VPR130_RAM_SZ 15 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ +#define VPR130_RETAINED 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ + +/*Controller Area Network*/ +#define CAN_PRESENT 1 +#define CAN_COUNT 2 + +/*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ + +#define MVDMA_PRESENT 1 +#define MVDMA_COUNT 2 + +#define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +#define MVDMA121_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA121_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA121_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +/*RAM Controller*/ +#define RAMC_PRESENT 1 +#define RAMC_COUNT 2 + +#define RAMC122_ECC 0 /*!< (unspecified) */ +#define RAMC122_SEC 0 /*!< (unspecified) */ + +#define RAMC123_ECC 0 /*!< (unspecified) */ +#define RAMC123_SEC 0 /*!< (unspecified) */ + +/*Distributed programmable peripheral interconnect controller*/ +#define DPPIC_PRESENT 1 +#define DPPIC_COUNT 8 + +#define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +/*Timer/Counter*/ +#define TIMER_PRESENT 1 +#define TIMER_COUNT 10 + +#define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ + +/*Pulse width modulation unit*/ +#define PWM_PRESENT 1 +#define PWM_COUNT 5 + +#define PWM120_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM120_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM130_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM130_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM131_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM131_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM132_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM132_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM133_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM133_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*SPI Slave*/ +#define SPIS_PRESENT 1 +#define SPIS_COUNT 9 + +#define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Serial Peripheral Interface Master with EasyDMA*/ +#define SPIM_PRESENT 1 +#define SPIM_COUNT 10 + +#define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +/*UART with EasyDMA*/ +#define UARTE_PRESENT 1 +#define UARTE_COUNT 9 + +#define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ +#define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ +#define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Real-time counter*/ +#define RTC_PRESENT 1 +#define RTC_COUNT 2 + +#define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ + +#define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ + +/*Watchdog Timer*/ +#define WDT_PRESENT 1 +#define WDT_COUNT 2 + +#define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT131_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT132_HAS_INTEN 0 /*!< (unspecified) */ + +/*Event generator unit*/ +#define EGU_PRESENT 1 +#define EGU_COUNT 1 + +#define EGU130_PEND 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ + +/*GPIO Port*/ +#define GPIO_PRESENT 1 +#define GPIO_COUNT 10 + +#define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MAX 12 /*!< (unspecified) */ +#define P0_PIN_NUM_SIZE 13 /*!< (unspecified) */ +#define P0_FEATURE_PINS_PRESENT 0x00001FFFUL /*!< (unspecified) */ +#define P0_DRIVECTRL 0 /*!< (unspecified) */ +#define P0_RETAIN 1 /*!< (unspecified) */ +#define P0_PWRCTRL 0 /*!< (unspecified) */ +#define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P0_BIASCTRL 0 /*!< (unspecified) */ + +#define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P1_DRIVECTRL 0 /*!< (unspecified) */ +#define P1_RETAIN 1 /*!< (unspecified) */ +#define P1_PWRCTRL 0 /*!< (unspecified) */ +#define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P1_BIASCTRL 0 /*!< (unspecified) */ + +#define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P2_DRIVECTRL 0 /*!< (unspecified) */ +#define P2_RETAIN 1 /*!< (unspecified) */ +#define P2_PWRCTRL 0 /*!< (unspecified) */ +#define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P2_BIASCTRL 0 /*!< (unspecified) */ + +#define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ +#define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ +#define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ +#define P6_DRIVECTRL 1 /*!< (unspecified) */ +#define P6_RETAIN 1 /*!< (unspecified) */ +#define P6_PWRCTRL 0 /*!< (unspecified) */ +#define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P6_BIASCTRL 0 /*!< (unspecified) */ + +#define P8_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MAX 4 /*!< (unspecified) */ +#define P8_PIN_NUM_SIZE 5 /*!< (unspecified) */ +#define P8_FEATURE_PINS_PRESENT 0x0000001FUL /*!< (unspecified) */ +#define P8_DRIVECTRL 1 /*!< (unspecified) */ +#define P8_RETAIN 1 /*!< (unspecified) */ +#define P8_PWRCTRL 0 /*!< (unspecified) */ +#define P8_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P8_BIASCTRL 0 /*!< (unspecified) */ + +#define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ +#define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ +#define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ +#define P9_DRIVECTRL 0 /*!< (unspecified) */ +#define P9_RETAIN 1 /*!< (unspecified) */ +#define P9_PWRCTRL 1 /*!< (unspecified) */ +#define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P9_BIASCTRL 0 /*!< (unspecified) */ + +#define P10_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P10_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P10_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P10_DRIVECTRL 0 /*!< (unspecified) */ +#define P10_RETAIN 1 /*!< (unspecified) */ +#define P10_PWRCTRL 0 /*!< (unspecified) */ +#define P10_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P10_BIASCTRL 0 /*!< (unspecified) */ + +#define P11_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P11_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P11_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P11_DRIVECTRL 0 /*!< (unspecified) */ +#define P11_RETAIN 1 /*!< (unspecified) */ +#define P11_PWRCTRL 0 /*!< (unspecified) */ +#define P11_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P11_BIASCTRL 0 /*!< (unspecified) */ + +#define P12_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MAX 2 /*!< (unspecified) */ +#define P12_PIN_NUM_SIZE 3 /*!< (unspecified) */ +#define P12_FEATURE_PINS_PRESENT 0x00000007UL /*!< (unspecified) */ +#define P12_DRIVECTRL 0 /*!< (unspecified) */ +#define P12_RETAIN 1 /*!< (unspecified) */ +#define P12_PWRCTRL 0 /*!< (unspecified) */ +#define P12_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P12_BIASCTRL 0 /*!< (unspecified) */ + +#define P13_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MAX 3 /*!< (unspecified) */ +#define P13_PIN_NUM_SIZE 4 /*!< (unspecified) */ +#define P13_FEATURE_PINS_PRESENT 0x0000000FUL /*!< (unspecified) */ +#define P13_DRIVECTRL 0 /*!< (unspecified) */ +#define P13_RETAIN 1 /*!< (unspecified) */ +#define P13_PWRCTRL 0 /*!< (unspecified) */ +#define P13_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P13_BIASCTRL 0 /*!< (unspecified) */ + +/*Analog to Digital Converter*/ +#define SAADC_PRESENT 1 +#define SAADC_COUNT 1 + +#define SAADC_PSEL_V2 1 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Comparator*/ +#define COMP_PRESENT 1 +#define COMP_COUNT 1 + +/*Low-power comparator*/ +#define LPCOMP_PRESENT 1 +#define LPCOMP_COUNT 1 + +/*Temperature Sensor*/ +#define TEMP_PRESENT 1 +#define TEMP_COUNT 1 + +/*Inter-IC Sound*/ +#define I2S_PRESENT 1 +#define I2S_COUNT 2 + +/*Pulse Density Modulation (Digital Microphone) Interface*/ +#define PDM_PRESENT 1 +#define PDM_COUNT 1 + +#define PDM_SAMPLE16 1 /*!< (unspecified) */ +#define PDM_SAMPLE48 0 /*!< (unspecified) */ +#define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Quadrature Decoder*/ +#define QDEC_PRESENT 1 +#define QDEC_COUNT 2 + +/*I2C compatible Two-Wire Master Interface with EasyDMA*/ +#define TWIM_PRESENT 1 +#define TWIM_COUNT 8 + +#define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*I2C compatible Two-Wire Slave Interface with EasyDMA*/ +#define TWIS_PRESENT 1 +#define TWIS_COUNT 8 + +#define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_FLPR_PERIPHERALS_H */ + diff --git a/mdk/nrf9230_enga_flpr_vectors.h b/mdk/nrf9230_enga_flpr_vectors.h new file mode 100644 index 000000000..703aaf5cb --- /dev/null +++ b/mdk/nrf9230_enga_flpr_vectors.h @@ -0,0 +1,719 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +__WEAK void UserSoftware_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorSoftware_Handler(void) +{ + while(1); +} + +__WEAK void MachineSoftware_Handler(void) +{ + while(1); +} + +__WEAK void UserTimer_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorTimer_Handler(void) +{ + while(1); +} + +__WEAK void MachineTimer_Handler(void) +{ + while(1); +} + +__WEAK void UserExternal_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorExternal_Handler(void) +{ + while(1); +} + +__WEAK void MachineExternal_Handler(void) +{ + while(1); +} + +__WEAK void CLICSoftware_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void VPRCLIC_0_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_1_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_2_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_3_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_4_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_5_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_6_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_7_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_8_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_9_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_10_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_11_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_12_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_13_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_14_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_15_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_16_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_17_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_18_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_19_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_20_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_21_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_22_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_23_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_24_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_25_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_26_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_27_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_28_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_29_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_30_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_31_IRQHandler (void); + __HANDLER("Default_Handler") void VPRTIM_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_0_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_2_IRQHandler (void); + __HANDLER("Default_Handler") void TBM_IRQHandler (void); + __HANDLER("Default_Handler") void USBHS_IRQHandler (void); + __HANDLER("Default_Handler") void EXMIF_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT120_0_IRQHandler (void); + __HANDLER("Default_Handler") void I3C120_IRQHandler (void); + __HANDLER("Default_Handler") void VPR121_IRQHandler (void); + __HANDLER("Default_Handler") void CAN120_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA120_IRQHandler (void); + __HANDLER("Default_Handler") void CAN121_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA121_IRQHandler (void); + __HANDLER("Default_Handler") void I3C121_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER120_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER121_IRQHandler (void); + __HANDLER("Default_Handler") void PWM120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIS120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM120_UARTE120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM121_IRQHandler (void); + __HANDLER("Default_Handler") void VPR130_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT130_0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC130_IRQHandler (void); + __HANDLER("Default_Handler") void RTC131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT132_IRQHandler (void); + __HANDLER("Default_Handler") void EGU130_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void I2S130_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC130_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC131_IRQHandler (void); + __HANDLER("Default_Handler") void I2S131_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER130_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER131_IRQHandler (void); + __HANDLER("Default_Handler") void PWM130_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER132_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER133_IRQHandler (void); + __HANDLER("Default_Handler") void PWM131_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL2_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER134_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER135_IRQHandler (void); + __HANDLER("Default_Handler") void PWM132_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL4_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER136_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER137_IRQHandler (void); + __HANDLER("Default_Handler") void PWM133_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL6_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL7_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + UserSoftware_Handler, + SuperVisorSoftware_Handler, + MachineSoftware_Handler, + 0, + UserTimer_Handler, + SuperVisorTimer_Handler, + 0, + MachineTimer_Handler, + UserExternal_Handler, + SuperVisorExternal_Handler, + 0, + MachineExternal_Handler, + CLICSoftware_Handler, + 0, + 0, + 0, +/* Device specific interrupt handlers */ + VPRCLIC_0_IRQHandler, + VPRCLIC_1_IRQHandler, + VPRCLIC_2_IRQHandler, + VPRCLIC_3_IRQHandler, + VPRCLIC_4_IRQHandler, + VPRCLIC_5_IRQHandler, + VPRCLIC_6_IRQHandler, + VPRCLIC_7_IRQHandler, + VPRCLIC_8_IRQHandler, + VPRCLIC_9_IRQHandler, + VPRCLIC_10_IRQHandler, + VPRCLIC_11_IRQHandler, + VPRCLIC_12_IRQHandler, + VPRCLIC_13_IRQHandler, + VPRCLIC_14_IRQHandler, + VPRCLIC_15_IRQHandler, + VPRCLIC_16_IRQHandler, + VPRCLIC_17_IRQHandler, + VPRCLIC_18_IRQHandler, + VPRCLIC_19_IRQHandler, + VPRCLIC_20_IRQHandler, + VPRCLIC_21_IRQHandler, + VPRCLIC_22_IRQHandler, + VPRCLIC_23_IRQHandler, + VPRCLIC_24_IRQHandler, + VPRCLIC_25_IRQHandler, + VPRCLIC_26_IRQHandler, + VPRCLIC_27_IRQHandler, + VPRCLIC_28_IRQHandler, + VPRCLIC_29_IRQHandler, + VPRCLIC_30_IRQHandler, + VPRCLIC_31_IRQHandler, + VPRTIM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + GPIOTE130_0_IRQHandler, + GPIOTE130_1_IRQHandler, + GPIOTE131_0_IRQHandler, + GPIOTE131_1_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TBM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + USBHS_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXMIF_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT120_0_IRQHandler, + 0, + I3C120_IRQHandler, + VPR121_IRQHandler, + 0, + 0, + 0, + CAN120_IRQHandler, + MVDMA120_IRQHandler, + 0, + CAN121_IRQHandler, + MVDMA121_IRQHandler, + 0, + I3C121_IRQHandler, + 0, + 0, + 0, + TIMER120_IRQHandler, + TIMER121_IRQHandler, + PWM120_IRQHandler, + SPIS120_IRQHandler, + SPIM120_UARTE120_IRQHandler, + SPIM121_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + VPR130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT130_0_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + RTC130_IRQHandler, + RTC131_IRQHandler, + 0, + WDT131_IRQHandler, + WDT132_IRQHandler, + EGU130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SAADC_IRQHandler, + COMP_LPCOMP_IRQHandler, + TEMP_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + I2S130_IRQHandler, + PDM_IRQHandler, + QDEC130_IRQHandler, + QDEC131_IRQHandler, + 0, + I2S131_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER130_IRQHandler, + TIMER131_IRQHandler, + PWM130_IRQHandler, + SERIAL0_IRQHandler, + SERIAL1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER132_IRQHandler, + TIMER133_IRQHandler, + PWM131_IRQHandler, + SERIAL2_IRQHandler, + SERIAL3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER134_IRQHandler, + TIMER135_IRQHandler, + PWM132_IRQHandler, + SERIAL4_IRQHandler, + SERIAL5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER136_IRQHandler, + TIMER137_IRQHandler, + PWM133_IRQHandler, + SERIAL6_IRQHandler, + SERIAL7_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + + +__attribute__((aligned(16), noreturn)) void Trap_Handler(void) +{ + __UNUSED uint32_t mcause = csr_read(CSR_MCAUSE); + while(1); +} + +__attribute__((used, section(".isr_return"), naked)) void isr_return(void) +{ + asm volatile ("mret"); +} + +#endif diff --git a/mdk/nrf9230_enga_global.h b/mdk/nrf9230_enga_global.h new file mode 100644 index 000000000..c19da26ea --- /dev/null +++ b/mdk/nrf9230_enga_global.h @@ -0,0 +1,879 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_GLOBAL_H +#define NRF9230_ENGA_GLOBAL_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_FICR_NS_BASE 0x0FFFE000UL +#define NRF_USBHSCORE0_NS_BASE 0x2F700000UL +#define NRF_USBHSCORE0_S_BASE 0x2F700000UL +#define NRF_I3CCORE120_NS_BASE 0x2FBE0000UL +#define NRF_I3CCORE121_NS_BASE 0x2FBE1000UL +#define NRF_DMU120_NS_BASE 0x2FBEF800UL +#define NRF_MCAN120_NS_BASE 0x2FBEF800UL +#define NRF_DMU121_NS_BASE 0x2FBF7800UL +#define NRF_MCAN121_NS_BASE 0x2FBF7800UL +#define NRF_STMDATA_NS_BASE 0xA0000000UL +#define NRF_STMDATA_S_BASE 0xA0000000UL +#define NRF_TDDCONF_NS_BASE 0xBF001000UL +#define NRF_TDDCONF_S_BASE 0xBF001000UL +#define NRF_STM_NS_BASE 0xBF042000UL +#define NRF_TPIU_NS_BASE 0xBF043000UL +#define NRF_CTI210_NS_BASE 0xBF046000UL +#define NRF_CTI211_NS_BASE 0xBF047000UL +#define NRF_ATBREPLICATOR210_NS_BASE 0xBF048000UL +#define NRF_ATBREPLICATOR211_NS_BASE 0xBF049000UL +#define NRF_ATBREPLICATOR212_NS_BASE 0xBF04A000UL +#define NRF_ATBREPLICATOR213_NS_BASE 0xBF04B000UL +#define NRF_ATBFUNNEL210_NS_BASE 0xBF04C000UL +#define NRF_ATBFUNNEL211_NS_BASE 0xBF04D000UL +#define NRF_ATBFUNNEL212_NS_BASE 0xBF04E000UL +#define NRF_ATBFUNNEL213_NS_BASE 0xBF04F000UL +#define NRF_GPIOTE130_NS_BASE 0x4F934000UL +#define NRF_GPIOTE130_S_BASE 0x5F934000UL +#define NRF_GPIOTE131_NS_BASE 0x4F935000UL +#define NRF_GPIOTE131_S_BASE 0x5F935000UL +#define NRF_GRTC_NS_BASE 0x4F99C000UL +#define NRF_GRTC_S_BASE 0x5F99C000UL +#define NRF_TBM_NS_BASE 0xBF003000UL +#define NRF_TBM_S_BASE 0xBF003000UL +#define NRF_USBHS_NS_BASE 0x4F086000UL +#define NRF_USBHS_S_BASE 0x5F086000UL +#define NRF_EXMIF_NS_BASE 0x4F095000UL +#define NRF_EXMIF_S_BASE 0x5F095000UL +#define NRF_SECDOMBELLBOARD_NS_BASE 0x4F099000UL +#define NRF_SECDOMBELLBOARD_S_BASE 0x5F099000UL +#define NRF_VPR120_NS_BASE 0x4F8C8000UL +#define NRF_VPR120_S_BASE 0x5F8C8000UL +#define NRF_IPCT120_NS_BASE 0x4F8D1000UL +#define NRF_IPCT120_S_BASE 0x5F8D1000UL +#define NRF_MUTEX120_NS_BASE 0x4F8D2000UL +#define NRF_I3C120_NS_BASE 0x4F8D3000UL +#define NRF_I3C120_S_BASE 0x5F8D3000UL +#define NRF_VPR121_NS_BASE 0x4F8D4000UL +#define NRF_VPR121_S_BASE 0x5F8D4000UL +#define NRF_CAN120_NS_BASE 0x4F8D8000UL +#define NRF_CAN120_S_BASE 0x5F8D8000UL +#define NRF_MVDMA120_NS_BASE 0x4F8D9000UL +#define NRF_MVDMA120_S_BASE 0x5F8D9000UL +#define NRF_RAMC122_NS_BASE 0x4F8DA000UL +#define NRF_RAMC122_S_BASE 0x5F8DA000UL +#define NRF_CAN121_NS_BASE 0x4F8DB000UL +#define NRF_CAN121_S_BASE 0x5F8DB000UL +#define NRF_MVDMA121_NS_BASE 0x4F8DC000UL +#define NRF_MVDMA121_S_BASE 0x5F8DC000UL +#define NRF_RAMC123_NS_BASE 0x4F8DD000UL +#define NRF_RAMC123_S_BASE 0x5F8DD000UL +#define NRF_I3C121_NS_BASE 0x4F8DE000UL +#define NRF_I3C121_S_BASE 0x5F8DE000UL +#define NRF_DPPIC120_NS_BASE 0x4F8E1000UL +#define NRF_DPPIC120_S_BASE 0x5F8E1000UL +#define NRF_TIMER120_NS_BASE 0x4F8E2000UL +#define NRF_TIMER120_S_BASE 0x5F8E2000UL +#define NRF_TIMER121_NS_BASE 0x4F8E3000UL +#define NRF_TIMER121_S_BASE 0x5F8E3000UL +#define NRF_PWM120_NS_BASE 0x4F8E4000UL +#define NRF_PWM120_S_BASE 0x5F8E4000UL +#define NRF_SPIS120_NS_BASE 0x4F8E5000UL +#define NRF_SPIS120_S_BASE 0x5F8E5000UL +#define NRF_SPIM120_NS_BASE 0x4F8E6000UL +#define NRF_UARTE120_NS_BASE 0x4F8E6000UL +#define NRF_SPIM120_S_BASE 0x5F8E6000UL +#define NRF_UARTE120_S_BASE 0x5F8E6000UL +#define NRF_SPIM121_NS_BASE 0x4F8E7000UL +#define NRF_SPIM121_S_BASE 0x5F8E7000UL +#define NRF_VPR130_NS_BASE 0x4F908000UL +#define NRF_VPR130_S_BASE 0x5F908000UL +#define NRF_IPCT130_NS_BASE 0x4F921000UL +#define NRF_IPCT130_S_BASE 0x5F921000UL +#define NRF_DPPIC130_NS_BASE 0x4F922000UL +#define NRF_DPPIC130_S_BASE 0x5F922000UL +#define NRF_MUTEX130_NS_BASE 0x4F927000UL +#define NRF_RTC130_NS_BASE 0x4F928000UL +#define NRF_RTC130_S_BASE 0x5F928000UL +#define NRF_RTC131_NS_BASE 0x4F929000UL +#define NRF_RTC131_S_BASE 0x5F929000UL +#define NRF_WDT131_NS_BASE 0x4F92B000UL +#define NRF_WDT131_S_BASE 0x5F92B000UL +#define NRF_WDT132_NS_BASE 0x4F92C000UL +#define NRF_WDT132_S_BASE 0x5F92C000UL +#define NRF_EGU130_NS_BASE 0x4F92D000UL +#define NRF_EGU130_S_BASE 0x5F92D000UL +#define NRF_P0_NS_BASE 0x4F938000UL +#define NRF_P1_NS_BASE 0x4F938200UL +#define NRF_P2_NS_BASE 0x4F938400UL +#define NRF_P6_NS_BASE 0x4F938C00UL +#define NRF_P0_S_BASE 0x5F938000UL +#define NRF_P1_S_BASE 0x5F938200UL +#define NRF_P2_S_BASE 0x5F938400UL +#define NRF_P6_S_BASE 0x5F938C00UL +#define NRF_P8_NS_BASE 0x4F939000UL +#define NRF_P9_NS_BASE 0x4F939200UL +#define NRF_P10_NS_BASE 0x4F939400UL +#define NRF_P11_NS_BASE 0x4F939600UL +#define NRF_P12_NS_BASE 0x4F939800UL +#define NRF_P13_NS_BASE 0x4F939A00UL +#define NRF_P8_S_BASE 0x5F939000UL +#define NRF_P9_S_BASE 0x5F939200UL +#define NRF_P10_S_BASE 0x5F939400UL +#define NRF_P11_S_BASE 0x5F939600UL +#define NRF_P12_S_BASE 0x5F939800UL +#define NRF_P13_S_BASE 0x5F939A00UL +#define NRF_DPPIC131_NS_BASE 0x4F981000UL +#define NRF_DPPIC131_S_BASE 0x5F981000UL +#define NRF_SAADC_NS_BASE 0x4F982000UL +#define NRF_SAADC_S_BASE 0x5F982000UL +#define NRF_COMP_NS_BASE 0x4F983000UL +#define NRF_LPCOMP_NS_BASE 0x4F983000UL +#define NRF_COMP_S_BASE 0x5F983000UL +#define NRF_LPCOMP_S_BASE 0x5F983000UL +#define NRF_TEMP_NS_BASE 0x4F984000UL +#define NRF_TEMP_S_BASE 0x5F984000UL +#define NRF_DPPIC132_NS_BASE 0x4F991000UL +#define NRF_DPPIC132_S_BASE 0x5F991000UL +#define NRF_I2S130_NS_BASE 0x4F992000UL +#define NRF_I2S130_S_BASE 0x5F992000UL +#define NRF_PDM_NS_BASE 0x4F993000UL +#define NRF_PDM_S_BASE 0x5F993000UL +#define NRF_QDEC130_NS_BASE 0x4F994000UL +#define NRF_QDEC130_S_BASE 0x5F994000UL +#define NRF_QDEC131_NS_BASE 0x4F995000UL +#define NRF_QDEC131_S_BASE 0x5F995000UL +#define NRF_I2S131_NS_BASE 0x4F997000UL +#define NRF_I2S131_S_BASE 0x5F997000UL +#define NRF_DPPIC133_NS_BASE 0x4F9A1000UL +#define NRF_DPPIC133_S_BASE 0x5F9A1000UL +#define NRF_TIMER130_NS_BASE 0x4F9A2000UL +#define NRF_TIMER130_S_BASE 0x5F9A2000UL +#define NRF_TIMER131_NS_BASE 0x4F9A3000UL +#define NRF_TIMER131_S_BASE 0x5F9A3000UL +#define NRF_PWM130_NS_BASE 0x4F9A4000UL +#define NRF_PWM130_S_BASE 0x5F9A4000UL +#define NRF_SPIM130_NS_BASE 0x4F9A5000UL +#define NRF_SPIS130_NS_BASE 0x4F9A5000UL +#define NRF_TWIM130_NS_BASE 0x4F9A5000UL +#define NRF_TWIS130_NS_BASE 0x4F9A5000UL +#define NRF_UARTE130_NS_BASE 0x4F9A5000UL +#define NRF_SPIM130_S_BASE 0x5F9A5000UL +#define NRF_SPIS130_S_BASE 0x5F9A5000UL +#define NRF_TWIM130_S_BASE 0x5F9A5000UL +#define NRF_TWIS130_S_BASE 0x5F9A5000UL +#define NRF_UARTE130_S_BASE 0x5F9A5000UL +#define NRF_SPIM131_NS_BASE 0x4F9A6000UL +#define NRF_SPIS131_NS_BASE 0x4F9A6000UL +#define NRF_TWIM131_NS_BASE 0x4F9A6000UL +#define NRF_TWIS131_NS_BASE 0x4F9A6000UL +#define NRF_UARTE131_NS_BASE 0x4F9A6000UL +#define NRF_SPIM131_S_BASE 0x5F9A6000UL +#define NRF_SPIS131_S_BASE 0x5F9A6000UL +#define NRF_TWIM131_S_BASE 0x5F9A6000UL +#define NRF_TWIS131_S_BASE 0x5F9A6000UL +#define NRF_UARTE131_S_BASE 0x5F9A6000UL +#define NRF_DPPIC134_NS_BASE 0x4F9B1000UL +#define NRF_DPPIC134_S_BASE 0x5F9B1000UL +#define NRF_TIMER132_NS_BASE 0x4F9B2000UL +#define NRF_TIMER132_S_BASE 0x5F9B2000UL +#define NRF_TIMER133_NS_BASE 0x4F9B3000UL +#define NRF_TIMER133_S_BASE 0x5F9B3000UL +#define NRF_PWM131_NS_BASE 0x4F9B4000UL +#define NRF_PWM131_S_BASE 0x5F9B4000UL +#define NRF_SPIM132_NS_BASE 0x4F9B5000UL +#define NRF_SPIS132_NS_BASE 0x4F9B5000UL +#define NRF_TWIM132_NS_BASE 0x4F9B5000UL +#define NRF_TWIS132_NS_BASE 0x4F9B5000UL +#define NRF_UARTE132_NS_BASE 0x4F9B5000UL +#define NRF_SPIM132_S_BASE 0x5F9B5000UL +#define NRF_SPIS132_S_BASE 0x5F9B5000UL +#define NRF_TWIM132_S_BASE 0x5F9B5000UL +#define NRF_TWIS132_S_BASE 0x5F9B5000UL +#define NRF_UARTE132_S_BASE 0x5F9B5000UL +#define NRF_SPIM133_NS_BASE 0x4F9B6000UL +#define NRF_SPIS133_NS_BASE 0x4F9B6000UL +#define NRF_TWIM133_NS_BASE 0x4F9B6000UL +#define NRF_TWIS133_NS_BASE 0x4F9B6000UL +#define NRF_UARTE133_NS_BASE 0x4F9B6000UL +#define NRF_SPIM133_S_BASE 0x5F9B6000UL +#define NRF_SPIS133_S_BASE 0x5F9B6000UL +#define NRF_TWIM133_S_BASE 0x5F9B6000UL +#define NRF_TWIS133_S_BASE 0x5F9B6000UL +#define NRF_UARTE133_S_BASE 0x5F9B6000UL +#define NRF_DPPIC135_NS_BASE 0x4F9C1000UL +#define NRF_DPPIC135_S_BASE 0x5F9C1000UL +#define NRF_TIMER134_NS_BASE 0x4F9C2000UL +#define NRF_TIMER134_S_BASE 0x5F9C2000UL +#define NRF_TIMER135_NS_BASE 0x4F9C3000UL +#define NRF_TIMER135_S_BASE 0x5F9C3000UL +#define NRF_PWM132_NS_BASE 0x4F9C4000UL +#define NRF_PWM132_S_BASE 0x5F9C4000UL +#define NRF_SPIM134_NS_BASE 0x4F9C5000UL +#define NRF_SPIS134_NS_BASE 0x4F9C5000UL +#define NRF_TWIM134_NS_BASE 0x4F9C5000UL +#define NRF_TWIS134_NS_BASE 0x4F9C5000UL +#define NRF_UARTE134_NS_BASE 0x4F9C5000UL +#define NRF_SPIM134_S_BASE 0x5F9C5000UL +#define NRF_SPIS134_S_BASE 0x5F9C5000UL +#define NRF_TWIM134_S_BASE 0x5F9C5000UL +#define NRF_TWIS134_S_BASE 0x5F9C5000UL +#define NRF_UARTE134_S_BASE 0x5F9C5000UL +#define NRF_SPIM135_NS_BASE 0x4F9C6000UL +#define NRF_SPIS135_NS_BASE 0x4F9C6000UL +#define NRF_TWIM135_NS_BASE 0x4F9C6000UL +#define NRF_TWIS135_NS_BASE 0x4F9C6000UL +#define NRF_UARTE135_NS_BASE 0x4F9C6000UL +#define NRF_SPIM135_S_BASE 0x5F9C6000UL +#define NRF_SPIS135_S_BASE 0x5F9C6000UL +#define NRF_TWIM135_S_BASE 0x5F9C6000UL +#define NRF_TWIS135_S_BASE 0x5F9C6000UL +#define NRF_UARTE135_S_BASE 0x5F9C6000UL +#define NRF_DPPIC136_NS_BASE 0x4F9D1000UL +#define NRF_DPPIC136_S_BASE 0x5F9D1000UL +#define NRF_TIMER136_NS_BASE 0x4F9D2000UL +#define NRF_TIMER136_S_BASE 0x5F9D2000UL +#define NRF_TIMER137_NS_BASE 0x4F9D3000UL +#define NRF_TIMER137_S_BASE 0x5F9D3000UL +#define NRF_PWM133_NS_BASE 0x4F9D4000UL +#define NRF_PWM133_S_BASE 0x5F9D4000UL +#define NRF_SPIM136_NS_BASE 0x4F9D5000UL +#define NRF_SPIS136_NS_BASE 0x4F9D5000UL +#define NRF_TWIM136_NS_BASE 0x4F9D5000UL +#define NRF_TWIS136_NS_BASE 0x4F9D5000UL +#define NRF_UARTE136_NS_BASE 0x4F9D5000UL +#define NRF_SPIM136_S_BASE 0x5F9D5000UL +#define NRF_SPIS136_S_BASE 0x5F9D5000UL +#define NRF_TWIM136_S_BASE 0x5F9D5000UL +#define NRF_TWIS136_S_BASE 0x5F9D5000UL +#define NRF_UARTE136_S_BASE 0x5F9D5000UL +#define NRF_SPIM137_NS_BASE 0x4F9D6000UL +#define NRF_SPIS137_NS_BASE 0x4F9D6000UL +#define NRF_TWIM137_NS_BASE 0x4F9D6000UL +#define NRF_TWIS137_NS_BASE 0x4F9D6000UL +#define NRF_UARTE137_NS_BASE 0x4F9D6000UL +#define NRF_SPIM137_S_BASE 0x5F9D6000UL +#define NRF_SPIS137_S_BASE 0x5F9D6000UL +#define NRF_TWIM137_S_BASE 0x5F9D6000UL +#define NRF_TWIS137_S_BASE 0x5F9D6000UL +#define NRF_UARTE137_S_BASE 0x5F9D6000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) +#define NRF_USBHSCORE0_NS ((NRF_USBHSCORE_Type*) NRF_USBHSCORE0_NS_BASE) +#define NRF_USBHSCORE0_S ((NRF_USBHSCORE_Type*) NRF_USBHSCORE0_S_BASE) +#define NRF_I3CCORE120_NS ((NRF_I3CCORE_Type*) NRF_I3CCORE120_NS_BASE) +#define NRF_I3CCORE121_NS ((NRF_I3CCORE_Type*) NRF_I3CCORE121_NS_BASE) +#define NRF_DMU120_NS ((NRF_DMU_Type*) NRF_DMU120_NS_BASE) +#define NRF_MCAN120_NS ((NRF_MCAN_Type*) NRF_MCAN120_NS_BASE) +#define NRF_DMU121_NS ((NRF_DMU_Type*) NRF_DMU121_NS_BASE) +#define NRF_MCAN121_NS ((NRF_MCAN_Type*) NRF_MCAN121_NS_BASE) +#define NRF_STMDATA_NS ((NRF_STMDATA_Type*) NRF_STMDATA_NS_BASE) +#define NRF_STMDATA_S ((NRF_STMDATA_Type*) NRF_STMDATA_S_BASE) +#define NRF_TDDCONF_NS ((NRF_TDDCONF_Type*) NRF_TDDCONF_NS_BASE) +#define NRF_TDDCONF_S ((NRF_TDDCONF_Type*) NRF_TDDCONF_S_BASE) +#define NRF_STM_NS ((NRF_STM_Type*) NRF_STM_NS_BASE) +#define NRF_TPIU_NS ((NRF_TPIU_Type*) NRF_TPIU_NS_BASE) +#define NRF_CTI210_NS ((NRF_CTI_Type*) NRF_CTI210_NS_BASE) +#define NRF_CTI211_NS ((NRF_CTI_Type*) NRF_CTI211_NS_BASE) +#define NRF_ATBREPLICATOR210_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR210_NS_BASE) +#define NRF_ATBREPLICATOR211_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR211_NS_BASE) +#define NRF_ATBREPLICATOR212_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR212_NS_BASE) +#define NRF_ATBREPLICATOR213_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR213_NS_BASE) +#define NRF_ATBFUNNEL210_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL210_NS_BASE) +#define NRF_ATBFUNNEL211_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL211_NS_BASE) +#define NRF_ATBFUNNEL212_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL212_NS_BASE) +#define NRF_ATBFUNNEL213_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL213_NS_BASE) +#define NRF_GPIOTE130_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE130_NS_BASE) +#define NRF_GPIOTE130_S ((NRF_GPIOTE_Type*) NRF_GPIOTE130_S_BASE) +#define NRF_GPIOTE131_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE131_NS_BASE) +#define NRF_GPIOTE131_S ((NRF_GPIOTE_Type*) NRF_GPIOTE131_S_BASE) +#define NRF_GRTC_NS ((NRF_GRTC_Type*) NRF_GRTC_NS_BASE) +#define NRF_GRTC_S ((NRF_GRTC_Type*) NRF_GRTC_S_BASE) +#define NRF_TBM_NS ((NRF_TBM_Type*) NRF_TBM_NS_BASE) +#define NRF_TBM_S ((NRF_TBM_Type*) NRF_TBM_S_BASE) +#define NRF_USBHS_NS ((NRF_USBHS_Type*) NRF_USBHS_NS_BASE) +#define NRF_USBHS_S ((NRF_USBHS_Type*) NRF_USBHS_S_BASE) +#define NRF_EXMIF_NS ((NRF_EXMIF_Type*) NRF_EXMIF_NS_BASE) +#define NRF_EXMIF_S ((NRF_EXMIF_Type*) NRF_EXMIF_S_BASE) +#define NRF_SECDOMBELLBOARD_NS ((NRF_BELLBOARDPUBLIC_Type*) NRF_SECDOMBELLBOARD_NS_BASE) +#define NRF_SECDOMBELLBOARD_S ((NRF_BELLBOARDPUBLIC_Type*) NRF_SECDOMBELLBOARD_S_BASE) +#define NRF_VPR120_NS ((NRF_VPRPUBLIC_Type*) NRF_VPR120_NS_BASE) +#define NRF_VPR120_S ((NRF_VPRPUBLIC_Type*) NRF_VPR120_S_BASE) +#define NRF_IPCT120_NS ((NRF_IPCT_Type*) NRF_IPCT120_NS_BASE) +#define NRF_IPCT120_S ((NRF_IPCT_Type*) NRF_IPCT120_S_BASE) +#define NRF_MUTEX120_NS ((NRF_MUTEX_Type*) NRF_MUTEX120_NS_BASE) +#define NRF_I3C120_NS ((NRF_I3C_Type*) NRF_I3C120_NS_BASE) +#define NRF_I3C120_S ((NRF_I3C_Type*) NRF_I3C120_S_BASE) +#define NRF_VPR121_NS ((NRF_VPR_Type*) NRF_VPR121_NS_BASE) +#define NRF_VPR121_S ((NRF_VPR_Type*) NRF_VPR121_S_BASE) +#define NRF_CAN120_NS ((NRF_CAN_Type*) NRF_CAN120_NS_BASE) +#define NRF_CAN120_S ((NRF_CAN_Type*) NRF_CAN120_S_BASE) +#define NRF_MVDMA120_NS ((NRF_MVDMA_Type*) NRF_MVDMA120_NS_BASE) +#define NRF_MVDMA120_S ((NRF_MVDMA_Type*) NRF_MVDMA120_S_BASE) +#define NRF_RAMC122_NS ((NRF_RAMC_Type*) NRF_RAMC122_NS_BASE) +#define NRF_RAMC122_S ((NRF_RAMC_Type*) NRF_RAMC122_S_BASE) +#define NRF_CAN121_NS ((NRF_CAN_Type*) NRF_CAN121_NS_BASE) +#define NRF_CAN121_S ((NRF_CAN_Type*) NRF_CAN121_S_BASE) +#define NRF_MVDMA121_NS ((NRF_MVDMA_Type*) NRF_MVDMA121_NS_BASE) +#define NRF_MVDMA121_S ((NRF_MVDMA_Type*) NRF_MVDMA121_S_BASE) +#define NRF_RAMC123_NS ((NRF_RAMC_Type*) NRF_RAMC123_NS_BASE) +#define NRF_RAMC123_S ((NRF_RAMC_Type*) NRF_RAMC123_S_BASE) +#define NRF_I3C121_NS ((NRF_I3C_Type*) NRF_I3C121_NS_BASE) +#define NRF_I3C121_S ((NRF_I3C_Type*) NRF_I3C121_S_BASE) +#define NRF_DPPIC120_NS ((NRF_DPPIC_Type*) NRF_DPPIC120_NS_BASE) +#define NRF_DPPIC120_S ((NRF_DPPIC_Type*) NRF_DPPIC120_S_BASE) +#define NRF_TIMER120_NS ((NRF_TIMER_Type*) NRF_TIMER120_NS_BASE) +#define NRF_TIMER120_S ((NRF_TIMER_Type*) NRF_TIMER120_S_BASE) +#define NRF_TIMER121_NS ((NRF_TIMER_Type*) NRF_TIMER121_NS_BASE) +#define NRF_TIMER121_S ((NRF_TIMER_Type*) NRF_TIMER121_S_BASE) +#define NRF_PWM120_NS ((NRF_PWM_Type*) NRF_PWM120_NS_BASE) +#define NRF_PWM120_S ((NRF_PWM_Type*) NRF_PWM120_S_BASE) +#define NRF_SPIS120_NS ((NRF_SPIS_Type*) NRF_SPIS120_NS_BASE) +#define NRF_SPIS120_S ((NRF_SPIS_Type*) NRF_SPIS120_S_BASE) +#define NRF_SPIM120_NS ((NRF_SPIM_Type*) NRF_SPIM120_NS_BASE) +#define NRF_UARTE120_NS ((NRF_UARTE_Type*) NRF_UARTE120_NS_BASE) +#define NRF_SPIM120_S ((NRF_SPIM_Type*) NRF_SPIM120_S_BASE) +#define NRF_UARTE120_S ((NRF_UARTE_Type*) NRF_UARTE120_S_BASE) +#define NRF_SPIM121_NS ((NRF_SPIM_Type*) NRF_SPIM121_NS_BASE) +#define NRF_SPIM121_S ((NRF_SPIM_Type*) NRF_SPIM121_S_BASE) +#define NRF_VPR130_NS ((NRF_VPR_Type*) NRF_VPR130_NS_BASE) +#define NRF_VPR130_S ((NRF_VPR_Type*) NRF_VPR130_S_BASE) +#define NRF_IPCT130_NS ((NRF_IPCT_Type*) NRF_IPCT130_NS_BASE) +#define NRF_IPCT130_S ((NRF_IPCT_Type*) NRF_IPCT130_S_BASE) +#define NRF_DPPIC130_NS ((NRF_DPPIC_Type*) NRF_DPPIC130_NS_BASE) +#define NRF_DPPIC130_S ((NRF_DPPIC_Type*) NRF_DPPIC130_S_BASE) +#define NRF_MUTEX130_NS ((NRF_MUTEX_Type*) NRF_MUTEX130_NS_BASE) +#define NRF_RTC130_NS ((NRF_RTC_Type*) NRF_RTC130_NS_BASE) +#define NRF_RTC130_S ((NRF_RTC_Type*) NRF_RTC130_S_BASE) +#define NRF_RTC131_NS ((NRF_RTC_Type*) NRF_RTC131_NS_BASE) +#define NRF_RTC131_S ((NRF_RTC_Type*) NRF_RTC131_S_BASE) +#define NRF_WDT131_NS ((NRF_WDT_Type*) NRF_WDT131_NS_BASE) +#define NRF_WDT131_S ((NRF_WDT_Type*) NRF_WDT131_S_BASE) +#define NRF_WDT132_NS ((NRF_WDT_Type*) NRF_WDT132_NS_BASE) +#define NRF_WDT132_S ((NRF_WDT_Type*) NRF_WDT132_S_BASE) +#define NRF_EGU130_NS ((NRF_EGU_Type*) NRF_EGU130_NS_BASE) +#define NRF_EGU130_S ((NRF_EGU_Type*) NRF_EGU130_S_BASE) +#define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) +#define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) +#define NRF_P2_NS ((NRF_GPIO_Type*) NRF_P2_NS_BASE) +#define NRF_P6_NS ((NRF_GPIO_Type*) NRF_P6_NS_BASE) +#define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) +#define NRF_P1_S ((NRF_GPIO_Type*) NRF_P1_S_BASE) +#define NRF_P2_S ((NRF_GPIO_Type*) NRF_P2_S_BASE) +#define NRF_P6_S ((NRF_GPIO_Type*) NRF_P6_S_BASE) +#define NRF_P8_NS ((NRF_GPIO_Type*) NRF_P8_NS_BASE) +#define NRF_P9_NS ((NRF_GPIO_Type*) NRF_P9_NS_BASE) +#define NRF_P10_NS ((NRF_GPIO_Type*) NRF_P10_NS_BASE) +#define NRF_P11_NS ((NRF_GPIO_Type*) NRF_P11_NS_BASE) +#define NRF_P12_NS ((NRF_GPIO_Type*) NRF_P12_NS_BASE) +#define NRF_P13_NS ((NRF_GPIO_Type*) NRF_P13_NS_BASE) +#define NRF_P8_S ((NRF_GPIO_Type*) NRF_P8_S_BASE) +#define NRF_P9_S ((NRF_GPIO_Type*) NRF_P9_S_BASE) +#define NRF_P10_S ((NRF_GPIO_Type*) NRF_P10_S_BASE) +#define NRF_P11_S ((NRF_GPIO_Type*) NRF_P11_S_BASE) +#define NRF_P12_S ((NRF_GPIO_Type*) NRF_P12_S_BASE) +#define NRF_P13_S ((NRF_GPIO_Type*) NRF_P13_S_BASE) +#define NRF_DPPIC131_NS ((NRF_DPPIC_Type*) NRF_DPPIC131_NS_BASE) +#define NRF_DPPIC131_S ((NRF_DPPIC_Type*) NRF_DPPIC131_S_BASE) +#define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) +#define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) +#define NRF_COMP_NS ((NRF_COMP_Type*) NRF_COMP_NS_BASE) +#define NRF_LPCOMP_NS ((NRF_LPCOMP_Type*) NRF_LPCOMP_NS_BASE) +#define NRF_COMP_S ((NRF_COMP_Type*) NRF_COMP_S_BASE) +#define NRF_LPCOMP_S ((NRF_LPCOMP_Type*) NRF_LPCOMP_S_BASE) +#define NRF_TEMP_NS ((NRF_TEMP_Type*) NRF_TEMP_NS_BASE) +#define NRF_TEMP_S ((NRF_TEMP_Type*) NRF_TEMP_S_BASE) +#define NRF_DPPIC132_NS ((NRF_DPPIC_Type*) NRF_DPPIC132_NS_BASE) +#define NRF_DPPIC132_S ((NRF_DPPIC_Type*) NRF_DPPIC132_S_BASE) +#define NRF_I2S130_NS ((NRF_I2S_Type*) NRF_I2S130_NS_BASE) +#define NRF_I2S130_S ((NRF_I2S_Type*) NRF_I2S130_S_BASE) +#define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) +#define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) +#define NRF_QDEC130_NS ((NRF_QDEC_Type*) NRF_QDEC130_NS_BASE) +#define NRF_QDEC130_S ((NRF_QDEC_Type*) NRF_QDEC130_S_BASE) +#define NRF_QDEC131_NS ((NRF_QDEC_Type*) NRF_QDEC131_NS_BASE) +#define NRF_QDEC131_S ((NRF_QDEC_Type*) NRF_QDEC131_S_BASE) +#define NRF_I2S131_NS ((NRF_I2S_Type*) NRF_I2S131_NS_BASE) +#define NRF_I2S131_S ((NRF_I2S_Type*) NRF_I2S131_S_BASE) +#define NRF_DPPIC133_NS ((NRF_DPPIC_Type*) NRF_DPPIC133_NS_BASE) +#define NRF_DPPIC133_S ((NRF_DPPIC_Type*) NRF_DPPIC133_S_BASE) +#define NRF_TIMER130_NS ((NRF_TIMER_Type*) NRF_TIMER130_NS_BASE) +#define NRF_TIMER130_S ((NRF_TIMER_Type*) NRF_TIMER130_S_BASE) +#define NRF_TIMER131_NS ((NRF_TIMER_Type*) NRF_TIMER131_NS_BASE) +#define NRF_TIMER131_S ((NRF_TIMER_Type*) NRF_TIMER131_S_BASE) +#define NRF_PWM130_NS ((NRF_PWM_Type*) NRF_PWM130_NS_BASE) +#define NRF_PWM130_S ((NRF_PWM_Type*) NRF_PWM130_S_BASE) +#define NRF_SPIM130_NS ((NRF_SPIM_Type*) NRF_SPIM130_NS_BASE) +#define NRF_SPIS130_NS ((NRF_SPIS_Type*) NRF_SPIS130_NS_BASE) +#define NRF_TWIM130_NS ((NRF_TWIM_Type*) NRF_TWIM130_NS_BASE) +#define NRF_TWIS130_NS ((NRF_TWIS_Type*) NRF_TWIS130_NS_BASE) +#define NRF_UARTE130_NS ((NRF_UARTE_Type*) NRF_UARTE130_NS_BASE) +#define NRF_SPIM130_S ((NRF_SPIM_Type*) NRF_SPIM130_S_BASE) +#define NRF_SPIS130_S ((NRF_SPIS_Type*) NRF_SPIS130_S_BASE) +#define NRF_TWIM130_S ((NRF_TWIM_Type*) NRF_TWIM130_S_BASE) +#define NRF_TWIS130_S ((NRF_TWIS_Type*) NRF_TWIS130_S_BASE) +#define NRF_UARTE130_S ((NRF_UARTE_Type*) NRF_UARTE130_S_BASE) +#define NRF_SPIM131_NS ((NRF_SPIM_Type*) NRF_SPIM131_NS_BASE) +#define NRF_SPIS131_NS ((NRF_SPIS_Type*) NRF_SPIS131_NS_BASE) +#define NRF_TWIM131_NS ((NRF_TWIM_Type*) NRF_TWIM131_NS_BASE) +#define NRF_TWIS131_NS ((NRF_TWIS_Type*) NRF_TWIS131_NS_BASE) +#define NRF_UARTE131_NS ((NRF_UARTE_Type*) NRF_UARTE131_NS_BASE) +#define NRF_SPIM131_S ((NRF_SPIM_Type*) NRF_SPIM131_S_BASE) +#define NRF_SPIS131_S ((NRF_SPIS_Type*) NRF_SPIS131_S_BASE) +#define NRF_TWIM131_S ((NRF_TWIM_Type*) NRF_TWIM131_S_BASE) +#define NRF_TWIS131_S ((NRF_TWIS_Type*) NRF_TWIS131_S_BASE) +#define NRF_UARTE131_S ((NRF_UARTE_Type*) NRF_UARTE131_S_BASE) +#define NRF_DPPIC134_NS ((NRF_DPPIC_Type*) NRF_DPPIC134_NS_BASE) +#define NRF_DPPIC134_S ((NRF_DPPIC_Type*) NRF_DPPIC134_S_BASE) +#define NRF_TIMER132_NS ((NRF_TIMER_Type*) NRF_TIMER132_NS_BASE) +#define NRF_TIMER132_S ((NRF_TIMER_Type*) NRF_TIMER132_S_BASE) +#define NRF_TIMER133_NS ((NRF_TIMER_Type*) NRF_TIMER133_NS_BASE) +#define NRF_TIMER133_S ((NRF_TIMER_Type*) NRF_TIMER133_S_BASE) +#define NRF_PWM131_NS ((NRF_PWM_Type*) NRF_PWM131_NS_BASE) +#define NRF_PWM131_S ((NRF_PWM_Type*) NRF_PWM131_S_BASE) +#define NRF_SPIM132_NS ((NRF_SPIM_Type*) NRF_SPIM132_NS_BASE) +#define NRF_SPIS132_NS ((NRF_SPIS_Type*) NRF_SPIS132_NS_BASE) +#define NRF_TWIM132_NS ((NRF_TWIM_Type*) NRF_TWIM132_NS_BASE) +#define NRF_TWIS132_NS ((NRF_TWIS_Type*) NRF_TWIS132_NS_BASE) +#define NRF_UARTE132_NS ((NRF_UARTE_Type*) NRF_UARTE132_NS_BASE) +#define NRF_SPIM132_S ((NRF_SPIM_Type*) NRF_SPIM132_S_BASE) +#define NRF_SPIS132_S ((NRF_SPIS_Type*) NRF_SPIS132_S_BASE) +#define NRF_TWIM132_S ((NRF_TWIM_Type*) NRF_TWIM132_S_BASE) +#define NRF_TWIS132_S ((NRF_TWIS_Type*) NRF_TWIS132_S_BASE) +#define NRF_UARTE132_S ((NRF_UARTE_Type*) NRF_UARTE132_S_BASE) +#define NRF_SPIM133_NS ((NRF_SPIM_Type*) NRF_SPIM133_NS_BASE) +#define NRF_SPIS133_NS ((NRF_SPIS_Type*) NRF_SPIS133_NS_BASE) +#define NRF_TWIM133_NS ((NRF_TWIM_Type*) NRF_TWIM133_NS_BASE) +#define NRF_TWIS133_NS ((NRF_TWIS_Type*) NRF_TWIS133_NS_BASE) +#define NRF_UARTE133_NS ((NRF_UARTE_Type*) NRF_UARTE133_NS_BASE) +#define NRF_SPIM133_S ((NRF_SPIM_Type*) NRF_SPIM133_S_BASE) +#define NRF_SPIS133_S ((NRF_SPIS_Type*) NRF_SPIS133_S_BASE) +#define NRF_TWIM133_S ((NRF_TWIM_Type*) NRF_TWIM133_S_BASE) +#define NRF_TWIS133_S ((NRF_TWIS_Type*) NRF_TWIS133_S_BASE) +#define NRF_UARTE133_S ((NRF_UARTE_Type*) NRF_UARTE133_S_BASE) +#define NRF_DPPIC135_NS ((NRF_DPPIC_Type*) NRF_DPPIC135_NS_BASE) +#define NRF_DPPIC135_S ((NRF_DPPIC_Type*) NRF_DPPIC135_S_BASE) +#define NRF_TIMER134_NS ((NRF_TIMER_Type*) NRF_TIMER134_NS_BASE) +#define NRF_TIMER134_S ((NRF_TIMER_Type*) NRF_TIMER134_S_BASE) +#define NRF_TIMER135_NS ((NRF_TIMER_Type*) NRF_TIMER135_NS_BASE) +#define NRF_TIMER135_S ((NRF_TIMER_Type*) NRF_TIMER135_S_BASE) +#define NRF_PWM132_NS ((NRF_PWM_Type*) NRF_PWM132_NS_BASE) +#define NRF_PWM132_S ((NRF_PWM_Type*) NRF_PWM132_S_BASE) +#define NRF_SPIM134_NS ((NRF_SPIM_Type*) NRF_SPIM134_NS_BASE) +#define NRF_SPIS134_NS ((NRF_SPIS_Type*) NRF_SPIS134_NS_BASE) +#define NRF_TWIM134_NS ((NRF_TWIM_Type*) NRF_TWIM134_NS_BASE) +#define NRF_TWIS134_NS ((NRF_TWIS_Type*) NRF_TWIS134_NS_BASE) +#define NRF_UARTE134_NS ((NRF_UARTE_Type*) NRF_UARTE134_NS_BASE) +#define NRF_SPIM134_S ((NRF_SPIM_Type*) NRF_SPIM134_S_BASE) +#define NRF_SPIS134_S ((NRF_SPIS_Type*) NRF_SPIS134_S_BASE) +#define NRF_TWIM134_S ((NRF_TWIM_Type*) NRF_TWIM134_S_BASE) +#define NRF_TWIS134_S ((NRF_TWIS_Type*) NRF_TWIS134_S_BASE) +#define NRF_UARTE134_S ((NRF_UARTE_Type*) NRF_UARTE134_S_BASE) +#define NRF_SPIM135_NS ((NRF_SPIM_Type*) NRF_SPIM135_NS_BASE) +#define NRF_SPIS135_NS ((NRF_SPIS_Type*) NRF_SPIS135_NS_BASE) +#define NRF_TWIM135_NS ((NRF_TWIM_Type*) NRF_TWIM135_NS_BASE) +#define NRF_TWIS135_NS ((NRF_TWIS_Type*) NRF_TWIS135_NS_BASE) +#define NRF_UARTE135_NS ((NRF_UARTE_Type*) NRF_UARTE135_NS_BASE) +#define NRF_SPIM135_S ((NRF_SPIM_Type*) NRF_SPIM135_S_BASE) +#define NRF_SPIS135_S ((NRF_SPIS_Type*) NRF_SPIS135_S_BASE) +#define NRF_TWIM135_S ((NRF_TWIM_Type*) NRF_TWIM135_S_BASE) +#define NRF_TWIS135_S ((NRF_TWIS_Type*) NRF_TWIS135_S_BASE) +#define NRF_UARTE135_S ((NRF_UARTE_Type*) NRF_UARTE135_S_BASE) +#define NRF_DPPIC136_NS ((NRF_DPPIC_Type*) NRF_DPPIC136_NS_BASE) +#define NRF_DPPIC136_S ((NRF_DPPIC_Type*) NRF_DPPIC136_S_BASE) +#define NRF_TIMER136_NS ((NRF_TIMER_Type*) NRF_TIMER136_NS_BASE) +#define NRF_TIMER136_S ((NRF_TIMER_Type*) NRF_TIMER136_S_BASE) +#define NRF_TIMER137_NS ((NRF_TIMER_Type*) NRF_TIMER137_NS_BASE) +#define NRF_TIMER137_S ((NRF_TIMER_Type*) NRF_TIMER137_S_BASE) +#define NRF_PWM133_NS ((NRF_PWM_Type*) NRF_PWM133_NS_BASE) +#define NRF_PWM133_S ((NRF_PWM_Type*) NRF_PWM133_S_BASE) +#define NRF_SPIM136_NS ((NRF_SPIM_Type*) NRF_SPIM136_NS_BASE) +#define NRF_SPIS136_NS ((NRF_SPIS_Type*) NRF_SPIS136_NS_BASE) +#define NRF_TWIM136_NS ((NRF_TWIM_Type*) NRF_TWIM136_NS_BASE) +#define NRF_TWIS136_NS ((NRF_TWIS_Type*) NRF_TWIS136_NS_BASE) +#define NRF_UARTE136_NS ((NRF_UARTE_Type*) NRF_UARTE136_NS_BASE) +#define NRF_SPIM136_S ((NRF_SPIM_Type*) NRF_SPIM136_S_BASE) +#define NRF_SPIS136_S ((NRF_SPIS_Type*) NRF_SPIS136_S_BASE) +#define NRF_TWIM136_S ((NRF_TWIM_Type*) NRF_TWIM136_S_BASE) +#define NRF_TWIS136_S ((NRF_TWIS_Type*) NRF_TWIS136_S_BASE) +#define NRF_UARTE136_S ((NRF_UARTE_Type*) NRF_UARTE136_S_BASE) +#define NRF_SPIM137_NS ((NRF_SPIM_Type*) NRF_SPIM137_NS_BASE) +#define NRF_SPIS137_NS ((NRF_SPIS_Type*) NRF_SPIS137_NS_BASE) +#define NRF_TWIM137_NS ((NRF_TWIM_Type*) NRF_TWIM137_NS_BASE) +#define NRF_TWIS137_NS ((NRF_TWIS_Type*) NRF_TWIS137_NS_BASE) +#define NRF_UARTE137_NS ((NRF_UARTE_Type*) NRF_UARTE137_NS_BASE) +#define NRF_SPIM137_S ((NRF_SPIM_Type*) NRF_SPIM137_S_BASE) +#define NRF_SPIS137_S ((NRF_SPIS_Type*) NRF_SPIS137_S_BASE) +#define NRF_TWIM137_S ((NRF_TWIM_Type*) NRF_TWIM137_S_BASE) +#define NRF_TWIS137_S ((NRF_TWIS_Type*) NRF_TWIS137_S_BASE) +#define NRF_UARTE137_S ((NRF_UARTE_Type*) NRF_UARTE137_S_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_FICR NRF_FICR_NS + #define NRF_USBHSCORE0 NRF_USBHSCORE0_NS + #define NRF_I3CCORE120 NRF_I3CCORE120_NS + #define NRF_I3CCORE121 NRF_I3CCORE121_NS + #define NRF_DMU120 NRF_DMU120_NS + #define NRF_MCAN120 NRF_MCAN120_NS + #define NRF_DMU121 NRF_DMU121_NS + #define NRF_MCAN121 NRF_MCAN121_NS + #define NRF_STMDATA NRF_STMDATA_NS + #define NRF_TDDCONF NRF_TDDCONF_NS + #define NRF_STM NRF_STM_NS + #define NRF_TPIU NRF_TPIU_NS + #define NRF_CTI210 NRF_CTI210_NS + #define NRF_CTI211 NRF_CTI211_NS + #define NRF_ATBREPLICATOR210 NRF_ATBREPLICATOR210_NS + #define NRF_ATBREPLICATOR211 NRF_ATBREPLICATOR211_NS + #define NRF_ATBREPLICATOR212 NRF_ATBREPLICATOR212_NS + #define NRF_ATBREPLICATOR213 NRF_ATBREPLICATOR213_NS + #define NRF_ATBFUNNEL210 NRF_ATBFUNNEL210_NS + #define NRF_ATBFUNNEL211 NRF_ATBFUNNEL211_NS + #define NRF_ATBFUNNEL212 NRF_ATBFUNNEL212_NS + #define NRF_ATBFUNNEL213 NRF_ATBFUNNEL213_NS + #define NRF_GPIOTE130 NRF_GPIOTE130_NS + #define NRF_GPIOTE131 NRF_GPIOTE131_NS + #define NRF_GRTC NRF_GRTC_NS + #define NRF_TBM NRF_TBM_NS + #define NRF_USBHS NRF_USBHS_NS + #define NRF_EXMIF NRF_EXMIF_NS + #define NRF_SECDOMBELLBOARD NRF_SECDOMBELLBOARD_NS + #define NRF_VPR120 NRF_VPR120_NS + #define NRF_IPCT120 NRF_IPCT120_NS + #define NRF_MUTEX120 NRF_MUTEX120_NS + #define NRF_I3C120 NRF_I3C120_NS + #define NRF_VPR121 NRF_VPR121_NS + #define NRF_CAN120 NRF_CAN120_NS + #define NRF_MVDMA120 NRF_MVDMA120_NS + #define NRF_RAMC122 NRF_RAMC122_NS + #define NRF_CAN121 NRF_CAN121_NS + #define NRF_MVDMA121 NRF_MVDMA121_NS + #define NRF_RAMC123 NRF_RAMC123_NS + #define NRF_I3C121 NRF_I3C121_NS + #define NRF_DPPIC120 NRF_DPPIC120_NS + #define NRF_TIMER120 NRF_TIMER120_NS + #define NRF_TIMER121 NRF_TIMER121_NS + #define NRF_PWM120 NRF_PWM120_NS + #define NRF_SPIS120 NRF_SPIS120_NS + #define NRF_SPIM120 NRF_SPIM120_NS + #define NRF_UARTE120 NRF_UARTE120_NS + #define NRF_SPIM121 NRF_SPIM121_NS + #define NRF_VPR130 NRF_VPR130_NS + #define NRF_IPCT130 NRF_IPCT130_NS + #define NRF_DPPIC130 NRF_DPPIC130_NS + #define NRF_MUTEX130 NRF_MUTEX130_NS + #define NRF_RTC130 NRF_RTC130_NS + #define NRF_RTC131 NRF_RTC131_NS + #define NRF_WDT131 NRF_WDT131_NS + #define NRF_WDT132 NRF_WDT132_NS + #define NRF_EGU130 NRF_EGU130_NS + #define NRF_P0 NRF_P0_NS + #define NRF_P1 NRF_P1_NS + #define NRF_P2 NRF_P2_NS + #define NRF_P6 NRF_P6_NS + #define NRF_P8 NRF_P8_NS + #define NRF_P9 NRF_P9_NS + #define NRF_P10 NRF_P10_NS + #define NRF_P11 NRF_P11_NS + #define NRF_P12 NRF_P12_NS + #define NRF_P13 NRF_P13_NS + #define NRF_DPPIC131 NRF_DPPIC131_NS + #define NRF_SAADC NRF_SAADC_NS + #define NRF_COMP NRF_COMP_NS + #define NRF_LPCOMP NRF_LPCOMP_NS + #define NRF_TEMP NRF_TEMP_NS + #define NRF_DPPIC132 NRF_DPPIC132_NS + #define NRF_I2S130 NRF_I2S130_NS + #define NRF_PDM NRF_PDM_NS + #define NRF_QDEC130 NRF_QDEC130_NS + #define NRF_QDEC131 NRF_QDEC131_NS + #define NRF_I2S131 NRF_I2S131_NS + #define NRF_DPPIC133 NRF_DPPIC133_NS + #define NRF_TIMER130 NRF_TIMER130_NS + #define NRF_TIMER131 NRF_TIMER131_NS + #define NRF_PWM130 NRF_PWM130_NS + #define NRF_SPIM130 NRF_SPIM130_NS + #define NRF_SPIS130 NRF_SPIS130_NS + #define NRF_TWIM130 NRF_TWIM130_NS + #define NRF_TWIS130 NRF_TWIS130_NS + #define NRF_UARTE130 NRF_UARTE130_NS + #define NRF_SPIM131 NRF_SPIM131_NS + #define NRF_SPIS131 NRF_SPIS131_NS + #define NRF_TWIM131 NRF_TWIM131_NS + #define NRF_TWIS131 NRF_TWIS131_NS + #define NRF_UARTE131 NRF_UARTE131_NS + #define NRF_DPPIC134 NRF_DPPIC134_NS + #define NRF_TIMER132 NRF_TIMER132_NS + #define NRF_TIMER133 NRF_TIMER133_NS + #define NRF_PWM131 NRF_PWM131_NS + #define NRF_SPIM132 NRF_SPIM132_NS + #define NRF_SPIS132 NRF_SPIS132_NS + #define NRF_TWIM132 NRF_TWIM132_NS + #define NRF_TWIS132 NRF_TWIS132_NS + #define NRF_UARTE132 NRF_UARTE132_NS + #define NRF_SPIM133 NRF_SPIM133_NS + #define NRF_SPIS133 NRF_SPIS133_NS + #define NRF_TWIM133 NRF_TWIM133_NS + #define NRF_TWIS133 NRF_TWIS133_NS + #define NRF_UARTE133 NRF_UARTE133_NS + #define NRF_DPPIC135 NRF_DPPIC135_NS + #define NRF_TIMER134 NRF_TIMER134_NS + #define NRF_TIMER135 NRF_TIMER135_NS + #define NRF_PWM132 NRF_PWM132_NS + #define NRF_SPIM134 NRF_SPIM134_NS + #define NRF_SPIS134 NRF_SPIS134_NS + #define NRF_TWIM134 NRF_TWIM134_NS + #define NRF_TWIS134 NRF_TWIS134_NS + #define NRF_UARTE134 NRF_UARTE134_NS + #define NRF_SPIM135 NRF_SPIM135_NS + #define NRF_SPIS135 NRF_SPIS135_NS + #define NRF_TWIM135 NRF_TWIM135_NS + #define NRF_TWIS135 NRF_TWIS135_NS + #define NRF_UARTE135 NRF_UARTE135_NS + #define NRF_DPPIC136 NRF_DPPIC136_NS + #define NRF_TIMER136 NRF_TIMER136_NS + #define NRF_TIMER137 NRF_TIMER137_NS + #define NRF_PWM133 NRF_PWM133_NS + #define NRF_SPIM136 NRF_SPIM136_NS + #define NRF_SPIS136 NRF_SPIS136_NS + #define NRF_TWIM136 NRF_TWIM136_NS + #define NRF_TWIS136 NRF_TWIS136_NS + #define NRF_UARTE136 NRF_UARTE136_NS + #define NRF_SPIM137 NRF_SPIM137_NS + #define NRF_SPIS137 NRF_SPIS137_NS + #define NRF_TWIM137 NRF_TWIM137_NS + #define NRF_TWIS137 NRF_TWIS137_NS + #define NRF_UARTE137 NRF_UARTE137_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_FICR NRF_FICR_NS + #define NRF_USBHSCORE0 NRF_USBHSCORE0_S + #define NRF_I3CCORE120 NRF_I3CCORE120_NS + #define NRF_I3CCORE121 NRF_I3CCORE121_NS + #define NRF_DMU120 NRF_DMU120_NS + #define NRF_MCAN120 NRF_MCAN120_NS + #define NRF_DMU121 NRF_DMU121_NS + #define NRF_MCAN121 NRF_MCAN121_NS + #define NRF_STMDATA NRF_STMDATA_S + #define NRF_TDDCONF NRF_TDDCONF_S + #define NRF_STM NRF_STM_NS + #define NRF_TPIU NRF_TPIU_NS + #define NRF_CTI210 NRF_CTI210_NS + #define NRF_CTI211 NRF_CTI211_NS + #define NRF_ATBREPLICATOR210 NRF_ATBREPLICATOR210_NS + #define NRF_ATBREPLICATOR211 NRF_ATBREPLICATOR211_NS + #define NRF_ATBREPLICATOR212 NRF_ATBREPLICATOR212_NS + #define NRF_ATBREPLICATOR213 NRF_ATBREPLICATOR213_NS + #define NRF_ATBFUNNEL210 NRF_ATBFUNNEL210_NS + #define NRF_ATBFUNNEL211 NRF_ATBFUNNEL211_NS + #define NRF_ATBFUNNEL212 NRF_ATBFUNNEL212_NS + #define NRF_ATBFUNNEL213 NRF_ATBFUNNEL213_NS + #define NRF_GPIOTE130 NRF_GPIOTE130_S + #define NRF_GPIOTE131 NRF_GPIOTE131_S + #define NRF_GRTC NRF_GRTC_S + #define NRF_TBM NRF_TBM_S + #define NRF_USBHS NRF_USBHS_S + #define NRF_EXMIF NRF_EXMIF_S + #define NRF_SECDOMBELLBOARD NRF_SECDOMBELLBOARD_S + #define NRF_VPR120 NRF_VPR120_S + #define NRF_IPCT120 NRF_IPCT120_S + #define NRF_MUTEX120 NRF_MUTEX120_NS + #define NRF_I3C120 NRF_I3C120_S + #define NRF_VPR121 NRF_VPR121_S + #define NRF_CAN120 NRF_CAN120_S + #define NRF_MVDMA120 NRF_MVDMA120_S + #define NRF_RAMC122 NRF_RAMC122_S + #define NRF_CAN121 NRF_CAN121_S + #define NRF_MVDMA121 NRF_MVDMA121_S + #define NRF_RAMC123 NRF_RAMC123_S + #define NRF_I3C121 NRF_I3C121_S + #define NRF_DPPIC120 NRF_DPPIC120_S + #define NRF_TIMER120 NRF_TIMER120_S + #define NRF_TIMER121 NRF_TIMER121_S + #define NRF_PWM120 NRF_PWM120_S + #define NRF_SPIS120 NRF_SPIS120_S + #define NRF_SPIM120 NRF_SPIM120_S + #define NRF_UARTE120 NRF_UARTE120_S + #define NRF_SPIM121 NRF_SPIM121_S + #define NRF_VPR130 NRF_VPR130_S + #define NRF_IPCT130 NRF_IPCT130_S + #define NRF_DPPIC130 NRF_DPPIC130_S + #define NRF_MUTEX130 NRF_MUTEX130_NS + #define NRF_RTC130 NRF_RTC130_S + #define NRF_RTC131 NRF_RTC131_S + #define NRF_WDT131 NRF_WDT131_S + #define NRF_WDT132 NRF_WDT132_S + #define NRF_EGU130 NRF_EGU130_S + #define NRF_P0 NRF_P0_S + #define NRF_P1 NRF_P1_S + #define NRF_P2 NRF_P2_S + #define NRF_P6 NRF_P6_S + #define NRF_P8 NRF_P8_S + #define NRF_P9 NRF_P9_S + #define NRF_P10 NRF_P10_S + #define NRF_P11 NRF_P11_S + #define NRF_P12 NRF_P12_S + #define NRF_P13 NRF_P13_S + #define NRF_DPPIC131 NRF_DPPIC131_S + #define NRF_SAADC NRF_SAADC_S + #define NRF_COMP NRF_COMP_S + #define NRF_LPCOMP NRF_LPCOMP_S + #define NRF_TEMP NRF_TEMP_S + #define NRF_DPPIC132 NRF_DPPIC132_S + #define NRF_I2S130 NRF_I2S130_S + #define NRF_PDM NRF_PDM_S + #define NRF_QDEC130 NRF_QDEC130_S + #define NRF_QDEC131 NRF_QDEC131_S + #define NRF_I2S131 NRF_I2S131_S + #define NRF_DPPIC133 NRF_DPPIC133_S + #define NRF_TIMER130 NRF_TIMER130_S + #define NRF_TIMER131 NRF_TIMER131_S + #define NRF_PWM130 NRF_PWM130_S + #define NRF_SPIM130 NRF_SPIM130_S + #define NRF_SPIS130 NRF_SPIS130_S + #define NRF_TWIM130 NRF_TWIM130_S + #define NRF_TWIS130 NRF_TWIS130_S + #define NRF_UARTE130 NRF_UARTE130_S + #define NRF_SPIM131 NRF_SPIM131_S + #define NRF_SPIS131 NRF_SPIS131_S + #define NRF_TWIM131 NRF_TWIM131_S + #define NRF_TWIS131 NRF_TWIS131_S + #define NRF_UARTE131 NRF_UARTE131_S + #define NRF_DPPIC134 NRF_DPPIC134_S + #define NRF_TIMER132 NRF_TIMER132_S + #define NRF_TIMER133 NRF_TIMER133_S + #define NRF_PWM131 NRF_PWM131_S + #define NRF_SPIM132 NRF_SPIM132_S + #define NRF_SPIS132 NRF_SPIS132_S + #define NRF_TWIM132 NRF_TWIM132_S + #define NRF_TWIS132 NRF_TWIS132_S + #define NRF_UARTE132 NRF_UARTE132_S + #define NRF_SPIM133 NRF_SPIM133_S + #define NRF_SPIS133 NRF_SPIS133_S + #define NRF_TWIM133 NRF_TWIM133_S + #define NRF_TWIS133 NRF_TWIS133_S + #define NRF_UARTE133 NRF_UARTE133_S + #define NRF_DPPIC135 NRF_DPPIC135_S + #define NRF_TIMER134 NRF_TIMER134_S + #define NRF_TIMER135 NRF_TIMER135_S + #define NRF_PWM132 NRF_PWM132_S + #define NRF_SPIM134 NRF_SPIM134_S + #define NRF_SPIS134 NRF_SPIS134_S + #define NRF_TWIM134 NRF_TWIM134_S + #define NRF_TWIS134 NRF_TWIS134_S + #define NRF_UARTE134 NRF_UARTE134_S + #define NRF_SPIM135 NRF_SPIM135_S + #define NRF_SPIS135 NRF_SPIS135_S + #define NRF_TWIM135 NRF_TWIM135_S + #define NRF_TWIS135 NRF_TWIS135_S + #define NRF_UARTE135 NRF_UARTE135_S + #define NRF_DPPIC136 NRF_DPPIC136_S + #define NRF_TIMER136 NRF_TIMER136_S + #define NRF_TIMER137 NRF_TIMER137_S + #define NRF_PWM133 NRF_PWM133_S + #define NRF_SPIM136 NRF_SPIM136_S + #define NRF_SPIS136 NRF_SPIS136_S + #define NRF_TWIM136 NRF_TWIM136_S + #define NRF_TWIS136 NRF_TWIS136_S + #define NRF_UARTE136 NRF_UARTE136_S + #define NRF_SPIM137 NRF_SPIM137_S + #define NRF_SPIS137 NRF_SPIS137_S + #define NRF_TWIM137 NRF_TWIM137_S + #define NRF_TWIS137 NRF_TWIS137_S + #define NRF_UARTE137 NRF_UARTE137_S +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_GLOBAL_H */ + diff --git a/mdk/nrf9230_enga_interim.h b/mdk/nrf9230_enga_interim.h new file mode 100644 index 000000000..eb9ef4cdc --- /dev/null +++ b/mdk/nrf9230_enga_interim.h @@ -0,0 +1,150 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_INTERIM_H__ +#define NRF9230_ENGA_INTERIM_H__ + +#include "haltium_interim.h" + +#if defined(NRF9230_ENGA_XXAA) + + #if defined(NRF_TRUSTZONE_NONSECURE) + #if defined(NRF_APPLICATION) + #define GRTC_IRQ_GROUP 2 + #define GPIOTE130_IRQ_GROUP 2 + #define GPIOTE131_IRQ_GROUP 1 + #elif defined(NRF_RADIOCORE) + #define GRTC_IRQ_GROUP 4 + #define GPIOTE130_IRQ_GROUP 4 + #else + #error Unknown core. + #endif + #elif defined(NRF_PPR) + #define GRTC_IRQ_GROUP 10 + #define GPIOTE130_IRQ_GROUP 2 + #elif defined(NRF_FLPR) + #define GRTC_IRQ_GROUP 11 + #define GPIOTE130_IRQ_GROUP 2 + #else + #if defined(NRF_APPLICATION) + #define GRTC_IRQ_GROUP 3 + #define GPIOTE130_IRQ_GROUP 3 + #define GPIOTE131_IRQ_GROUP 2 + #elif defined(NRF_RADIOCORE) + #define GRTC_IRQ_GROUP 5 + #define GPIOTE130_IRQ_GROUP 5 + #else + #error Unknown core. + #endif + #endif + + #define P0_PIN_NUM P0_PIN_NUM_SIZE + #define P1_PIN_NUM P1_PIN_NUM_SIZE + #define P2_PIN_NUM P2_PIN_NUM_SIZE + #define P6_PIN_NUM P6_PIN_NUM_SIZE + #define P8_PIN_NUM P8_PIN_NUM_SIZE + #define P9_PIN_NUM P9_PIN_NUM_SIZE + #define P10_PIN_NUM P10_PIN_NUM_SIZE + #define P11_PIN_NUM P11_PIN_NUM_SIZE + #define P12_PIN_NUM P12_PIN_NUM_SIZE + #define P13_PIN_NUM P13_PIN_NUM_SIZE + + #define DPPI_CH_NUM 8 + + #undef ETM_TRCRSCTLR_MaxCount + #undef RADIO_PENALTYREG_PCP_MaxCount + + #define ETM_TRCRSCTLR_MaxCount (32UL) /*!< Max size of TRCRSCTLR[32] array. */ + #define RADIO_PENALTYREG_PCP_MaxCount (5UL) /*!< Max size of PCP[5] array. */ + + #define EASYVDMA_PRESENT + + #define RTC_CC_NUM RTC_CC_NUM_SIZE + #define RTC130_CC_NUM RTC130_CC_NUM_SIZE + #define RTC131_CC_NUM RTC131_CC_NUM_SIZE + + #define TIMER020_MAX_SIZE TIMER020_MAX_SIZE_SIZE + #define TIMER021_MAX_SIZE TIMER021_MAX_SIZE_SIZE + #define TIMER022_MAX_SIZE TIMER022_MAX_SIZE_SIZE + #define TIMER120_MAX_SIZE TIMER120_MAX_SIZE_SIZE + #define TIMER121_MAX_SIZE TIMER121_MAX_SIZE_SIZE + #define TIMER130_MAX_SIZE TIMER130_MAX_SIZE_SIZE + #define TIMER131_MAX_SIZE TIMER131_MAX_SIZE_SIZE + #define TIMER132_MAX_SIZE TIMER132_MAX_SIZE_SIZE + #define TIMER133_MAX_SIZE TIMER133_MAX_SIZE_SIZE + #define TIMER134_MAX_SIZE TIMER134_MAX_SIZE_SIZE + #define TIMER135_MAX_SIZE TIMER135_MAX_SIZE_SIZE + #define TIMER136_MAX_SIZE TIMER136_MAX_SIZE_SIZE + #define TIMER137_MAX_SIZE TIMER137_MAX_SIZE_SIZE + + #define TIMER020_CC_NUM TIMER020_CC_NUM_SIZE + #define TIMER021_CC_NUM TIMER021_CC_NUM_SIZE + #define TIMER022_CC_NUM TIMER022_CC_NUM_SIZE + #define TIMER120_CC_NUM TIMER120_CC_NUM_SIZE + #define TIMER121_CC_NUM TIMER121_CC_NUM_SIZE + #define TIMER130_CC_NUM TIMER130_CC_NUM_SIZE + #define TIMER131_CC_NUM TIMER131_CC_NUM_SIZE + #define TIMER132_CC_NUM TIMER132_CC_NUM_SIZE + #define TIMER133_CC_NUM TIMER133_CC_NUM_SIZE + #define TIMER134_CC_NUM TIMER134_CC_NUM_SIZE + #define TIMER135_CC_NUM TIMER135_CC_NUM_SIZE + #define TIMER136_CC_NUM TIMER136_CC_NUM_SIZE + #define TIMER137_CC_NUM TIMER137_CC_NUM_SIZE + + #define DPPIC020_CH_NUM DPPIC020_CH_NUM_SIZE + #define DPPIC120_CH_NUM DPPIC120_CH_NUM_SIZE + #define DPPIC130_CH_NUM DPPIC130_CH_NUM_SIZE + #define DPPIC131_CH_NUM DPPIC131_CH_NUM_SIZE + #define DPPIC132_CH_NUM DPPIC132_CH_NUM_SIZE + #define DPPIC133_CH_NUM DPPIC133_CH_NUM_SIZE + #define DPPIC134_CH_NUM DPPIC134_CH_NUM_SIZE + #define DPPIC135_CH_NUM DPPIC135_CH_NUM_SIZE + #define DPPIC136_CH_NUM DPPIC136_CH_NUM_SIZE + + #define DPPIC020_GROUP_NUM DPPIC020_GROUP_NUM_SIZE + #define DPPIC120_GROUP_NUM DPPIC120_GROUP_NUM_SIZE + #define DPPIC130_GROUP_NUM DPPIC130_GROUP_NUM_SIZE + #define DPPIC131_GROUP_NUM DPPIC131_GROUP_NUM_SIZE + #define DPPIC132_GROUP_NUM DPPIC132_GROUP_NUM_SIZE + #define DPPIC133_GROUP_NUM DPPIC133_GROUP_NUM_SIZE + #define DPPIC134_GROUP_NUM DPPIC134_GROUP_NUM_SIZE + #define DPPIC135_GROUP_NUM DPPIC135_GROUP_NUM_SIZE + #define DPPIC136_GROUP_NUM DPPIC136_GROUP_NUM_SIZE + + #define EGU020_CH_NUM EGU020_CH_NUM_SIZE + #define EGU130_CH_NUM EGU130_CH_NUM_SIZE + +#endif + +#endif // NRF9230_ENGA_INTERIM_H__ diff --git a/mdk/nrf9230_enga_name_change.h b/mdk/nrf9230_enga_name_change.h new file mode 100644 index 000000000..7fd1ba6ee --- /dev/null +++ b/mdk/nrf9230_enga_name_change.h @@ -0,0 +1,49 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_NAME_CHANGE_H +#define NRF9230_ENGA_NAME_CHANGE_H + +#ifdef __cplusplus + extern "C" { +#endif + + + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_NAME_CHANGE_H */ + diff --git a/mdk/nrf9230_enga_peripherals.h b/mdk/nrf9230_enga_peripherals.h new file mode 100644 index 000000000..97a64171c --- /dev/null +++ b/mdk/nrf9230_enga_peripherals.h @@ -0,0 +1,58 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_PERIPHERALS_H +#define NRF9230_ENGA_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(NRF_APPLICATION) + #include "nrf9230_enga_application_peripherals.h" +#elif defined(NRF_FLPR) + #include "nrf9230_enga_flpr_peripherals.h" +#elif defined(NRF_PPR) + #include "nrf9230_enga_ppr_peripherals.h" +#elif defined(NRF_RADIOCORE) + #include "nrf9230_enga_radiocore_peripherals.h" +#else + #error No processor selected +#endif + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_PERIPHERALS_H */ + diff --git a/mdk/nrf9230_enga_ppr.h b/mdk/nrf9230_enga_ppr.h new file mode 100644 index 000000000..785b659a9 --- /dev/null +++ b/mdk/nrf9230_enga_ppr.h @@ -0,0 +1,326 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_PPR_H +#define NRF9230_ENGA_PPR_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_PPR /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ +/* ============================================== Processor Specific Interrupts ============================================== */ + VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ + VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ + VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ + VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ + VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ + VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ + VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ + VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ + VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ + VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ + VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ + VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ + VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ + VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ + VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ + VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ + VPRTIM_IRQn = 16, /*!< 16 VPRTIM */ + GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ + GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ + GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ + GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ + GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ + GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ + GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ + TBM_IRQn = 127, /*!< 127 TBM */ + USBHS_IRQn = 134, /*!< 134 USBHS */ + EXMIF_IRQn = 149, /*!< 149 EXMIF */ + IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ + I3C120_IRQn = 211, /*!< 211 I3C120 */ + VPR121_IRQn = 212, /*!< 212 VPR121 */ + CAN120_IRQn = 216, /*!< 216 CAN120 */ + MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ + CAN121_IRQn = 219, /*!< 219 CAN121 */ + MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ + I3C121_IRQn = 222, /*!< 222 I3C121 */ + TIMER120_IRQn = 226, /*!< 226 TIMER120 */ + TIMER121_IRQn = 227, /*!< 227 TIMER121 */ + PWM120_IRQn = 228, /*!< 228 PWM120 */ + SPIS120_IRQn = 229, /*!< 229 SPIS120 */ + SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ + SPIM121_IRQn = 231, /*!< 231 SPIM121 */ + VPR130_IRQn = 264, /*!< 264 VPR130 */ + IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ + RTC130_IRQn = 296, /*!< 296 RTC130 */ + RTC131_IRQn = 297, /*!< 297 RTC131 */ + WDT131_IRQn = 299, /*!< 299 WDT131 */ + WDT132_IRQn = 300, /*!< 300 WDT132 */ + EGU130_IRQn = 301, /*!< 301 EGU130 */ + SAADC_IRQn = 386, /*!< 386 SAADC */ + COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ + TEMP_IRQn = 388, /*!< 388 TEMP */ + I2S130_IRQn = 402, /*!< 402 I2S130 */ + PDM_IRQn = 403, /*!< 403 PDM */ + QDEC130_IRQn = 404, /*!< 404 QDEC130 */ + QDEC131_IRQn = 405, /*!< 405 QDEC131 */ + I2S131_IRQn = 407, /*!< 407 I2S131 */ + TIMER130_IRQn = 418, /*!< 418 TIMER130 */ + TIMER131_IRQn = 419, /*!< 419 TIMER131 */ + PWM130_IRQn = 420, /*!< 420 PWM130 */ + SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ + SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ + TIMER132_IRQn = 434, /*!< 434 TIMER132 */ + TIMER133_IRQn = 435, /*!< 435 TIMER133 */ + PWM131_IRQn = 436, /*!< 436 PWM131 */ + SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ + SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ + TIMER134_IRQn = 450, /*!< 450 TIMER134 */ + TIMER135_IRQn = 451, /*!< 451 TIMER135 */ + PWM132_IRQn = 452, /*!< 452 PWM132 */ + SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ + SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ + TIMER136_IRQn = 466, /*!< 466 TIMER136 */ + TIMER137_IRQn = 467, /*!< 467 TIMER137 */ + PWM133_IRQn = 468, /*!< 468 PWM133 */ + SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ + SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define SPIM120_IRQn SPIM120_UARTE120_IRQn +#define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler +#define UARTE120_IRQn SPIM120_UARTE120_IRQn +#define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SPIM130_IRQn SERIAL0_IRQn +#define SPIM130_IRQHandler SERIAL0_IRQHandler +#define SPIS130_IRQn SERIAL0_IRQn +#define SPIS130_IRQHandler SERIAL0_IRQHandler +#define TWIM130_IRQn SERIAL0_IRQn +#define TWIM130_IRQHandler SERIAL0_IRQHandler +#define TWIS130_IRQn SERIAL0_IRQn +#define TWIS130_IRQHandler SERIAL0_IRQHandler +#define UARTE130_IRQn SERIAL0_IRQn +#define UARTE130_IRQHandler SERIAL0_IRQHandler +#define SPIM131_IRQn SERIAL1_IRQn +#define SPIM131_IRQHandler SERIAL1_IRQHandler +#define SPIS131_IRQn SERIAL1_IRQn +#define SPIS131_IRQHandler SERIAL1_IRQHandler +#define TWIM131_IRQn SERIAL1_IRQn +#define TWIM131_IRQHandler SERIAL1_IRQHandler +#define TWIS131_IRQn SERIAL1_IRQn +#define TWIS131_IRQHandler SERIAL1_IRQHandler +#define UARTE131_IRQn SERIAL1_IRQn +#define UARTE131_IRQHandler SERIAL1_IRQHandler +#define SPIM132_IRQn SERIAL2_IRQn +#define SPIM132_IRQHandler SERIAL2_IRQHandler +#define SPIS132_IRQn SERIAL2_IRQn +#define SPIS132_IRQHandler SERIAL2_IRQHandler +#define TWIM132_IRQn SERIAL2_IRQn +#define TWIM132_IRQHandler SERIAL2_IRQHandler +#define TWIS132_IRQn SERIAL2_IRQn +#define TWIS132_IRQHandler SERIAL2_IRQHandler +#define UARTE132_IRQn SERIAL2_IRQn +#define UARTE132_IRQHandler SERIAL2_IRQHandler +#define SPIM133_IRQn SERIAL3_IRQn +#define SPIM133_IRQHandler SERIAL3_IRQHandler +#define SPIS133_IRQn SERIAL3_IRQn +#define SPIS133_IRQHandler SERIAL3_IRQHandler +#define TWIM133_IRQn SERIAL3_IRQn +#define TWIM133_IRQHandler SERIAL3_IRQHandler +#define TWIS133_IRQn SERIAL3_IRQn +#define TWIS133_IRQHandler SERIAL3_IRQHandler +#define UARTE133_IRQn SERIAL3_IRQn +#define UARTE133_IRQHandler SERIAL3_IRQHandler +#define SPIM134_IRQn SERIAL4_IRQn +#define SPIM134_IRQHandler SERIAL4_IRQHandler +#define SPIS134_IRQn SERIAL4_IRQn +#define SPIS134_IRQHandler SERIAL4_IRQHandler +#define TWIM134_IRQn SERIAL4_IRQn +#define TWIM134_IRQHandler SERIAL4_IRQHandler +#define TWIS134_IRQn SERIAL4_IRQn +#define TWIS134_IRQHandler SERIAL4_IRQHandler +#define UARTE134_IRQn SERIAL4_IRQn +#define UARTE134_IRQHandler SERIAL4_IRQHandler +#define SPIM135_IRQn SERIAL5_IRQn +#define SPIM135_IRQHandler SERIAL5_IRQHandler +#define SPIS135_IRQn SERIAL5_IRQn +#define SPIS135_IRQHandler SERIAL5_IRQHandler +#define TWIM135_IRQn SERIAL5_IRQn +#define TWIM135_IRQHandler SERIAL5_IRQHandler +#define TWIS135_IRQn SERIAL5_IRQn +#define TWIS135_IRQHandler SERIAL5_IRQHandler +#define UARTE135_IRQn SERIAL5_IRQn +#define UARTE135_IRQHandler SERIAL5_IRQHandler +#define SPIM136_IRQn SERIAL6_IRQn +#define SPIM136_IRQHandler SERIAL6_IRQHandler +#define SPIS136_IRQn SERIAL6_IRQn +#define SPIS136_IRQHandler SERIAL6_IRQHandler +#define TWIM136_IRQn SERIAL6_IRQn +#define TWIM136_IRQHandler SERIAL6_IRQHandler +#define TWIS136_IRQn SERIAL6_IRQn +#define TWIS136_IRQHandler SERIAL6_IRQHandler +#define UARTE136_IRQn SERIAL6_IRQn +#define UARTE136_IRQHandler SERIAL6_IRQHandler +#define SPIM137_IRQn SERIAL7_IRQn +#define SPIM137_IRQHandler SERIAL7_IRQHandler +#define SPIS137_IRQn SERIAL7_IRQn +#define SPIS137_IRQHandler SERIAL7_IRQHandler +#define TWIM137_IRQn SERIAL7_IRQn +#define TWIM137_IRQHandler SERIAL7_IRQHandler +#define TWIS137_IRQn SERIAL7_IRQn +#define TWIS137_IRQHandler SERIAL7_IRQHandler +#define UARTE137_IRQn SERIAL7_IRQn +#define UARTE137_IRQHandler SERIAL7_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ +#define __VPR_REV 1.1 /*!< VPR Core Revision */ +#define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ +#define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ +#define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ + +#define NRF_VPR NRF_VPR130 /*!< VPR instance name */ +#include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ +#include "system_nrf.h" /*!< nrf9230_enga_ppr System Library */ + +#endif /*!< NRF_PPR */ + + +#ifdef NRF_PPR + + #define NRF_DOMAIN NRF_DOMAIN_GLOBALSLOW + #define NRF_PROCESSOR NRF_PROCESSOR_PPR + #ifndef NRF_OWNER + #define NRF_OWNER NRF_OWNER_APPLICATION + #endif + +#endif /*!< NRF_PPR */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_PPR_VPRCLIC_BASE 0x5F909000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_PPR_VPRCLIC ((NRF_CLIC_Type*) NRF_PPR_VPRCLIC_BASE) + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_PPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #define NRF_VPRCLIC NRF_PPR_VPRCLIC +#endif /*!< NRF_PPR */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_PPR_H */ + diff --git a/mdk/nrf9230_enga_ppr.svd b/mdk/nrf9230_enga_ppr.svd new file mode 100644 index 000000000..88809b766 --- /dev/null +++ b/mdk/nrf9230_enga_ppr.svd @@ -0,0 +1,138921 @@ + + + + Nordic Semiconductor + Nordic + nrf9230_enga_ppr + nRF92 + 1 + nRF9230_enga reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + system_nrf9230_enga_ppr + + 480 + + + + GLOBAL_FICR + Factory Information Configuration Registers + 0x0FFFE000 + + + + 0 + 0xC00 + registers + + FICR + 0x20 + + + BLE + Unspecified + FICR_BLE + read-write + 0x00C + + ADDRTYPE + Device address type. + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + TYPE + Device address type. + 0 + 0 + + + Public + Public address. + 0x0 + + + Random + Random address. + 0x1 + + + + + + + 0x2 + 0x4 + ADDR[%s] + Description collection: 48 bit device address. + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + ADDR + Device address [n]. + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root. + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + ER + Encryption root word [n]. + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root. + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + IR + Identity root word [n]. + 0 + 31 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x050 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + HWID + Identification number for the HW + 0 + 15 + + + + + PART + Part code + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + PART + Part code + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x008 + read-only + 0xFFFFFFFF + 0x20 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + PACKAGE + Package option + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x010 + read-only + 0xFFFFFFFF + 0x20 + + + RAM + RAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + MRAM + MRAM variant + 0x014 + read-only + 0xFFFFFFFF + 0x20 + + + MRAM + MRAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x018 + read-only + 0x00001000 + 0x20 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODESIZE + Code memory size + 0x01C + read-only + 0x00000100 + 0x20 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + DEVICETYPE + Device type + 0x020 + read-only + 0x00000000 + 0x20 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x00000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x080 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + PARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0xFF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0xFF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + PMICVERSION + PMIC version + 0x00C + read-only + 0x00000000 + 0x20 + + + PMICVERSION + PMIC version, incremental code + 0 + 31 + + + + + 0x4 + 0x1 + TESTSITE[%s] + Description collection: Test site, in ascii + 0x010 + read-only + 0x00 + uint8_t + 0x8 + + + LOT + Lot number + test index in hex format (number digits 0-9). + 0x014 + read-only + 0x00000000 + 0x20 + + + LOTID + Lot number in hex format + 0 + 23 + + + TESTID + Test ID in hex format + 24 + 31 + + + + + 0x4 + 0x1 + TESTPROGRAMID[%s] + Description collection: Test program id, in ascii + 0x018 + read-only + 0x00 + uint8_t + 0x8 + + + OSATPARTNO + OSAT part number + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + OSATPARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWBUILDVERSION[%s] + Description collection: OSAT production build version + 0x020 + read-only + 0xFF + uint8_t + 0x8 + + + OVERRIDE + Unspecified + FICR_SIPINFO_OVERRIDE + read-write + 0x024 + + LFOSC + Unspecified + FICR_SIPINFO_OVERRIDE_LFOSC + read-write + 0x000 + + CONFIG + LF oscillator configuration. Note. This configuration overrides corresponding LF oscillator configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SRC + LF oscillator source. + 0 + 3 + + + Unconfigured + LF oscillator source is unconfigured. Default will be used. + 0xF + + + LFXO + Use LFXO as source for the LF oscillator. + 0x0 + + + LFRC + Use LFRC as source for the LF oscillator. + 0x1 + + + LFLPRC + Use LFLPRC as source for the LF oscillator. + 0x2 + + + Synth + Use LF Synth as source for the LF oscillator. + 0x3 + + + + + + + LFXOCONFIG + LFXO configuration. Note. This configuration overrides corresponding LFXO configuration in BICR when set. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + ACCURACY + LFXO crystal or external signal accuracy. + 0 + 3 + + + Unconfigured + The accuracy is unconfigured. + 0xF + + + 500ppm + LFXO crystal or external signal has an accuracy of 500 ppm. + 0x0 + + + 250ppm + LFXO crystal or external signal has an accuracy of 250 ppm. + 0x1 + + + 150ppm + LFXO crystal or external signal has an accuracy of 150 ppm. + 0x2 + + + 100ppm + LFXO crystal or external signal has an accuracy of 100 ppm. + 0x3 + + + 75ppm + LFXO crystal or external signal has an accuracy of 75 ppm. + 0x4 + + + 50ppm + LFXO crystal or external signal has an accuracy of 50 ppm. + 0x5 + + + 30ppm + LFXO crystal or external signal has an accuracy of 30 ppm. + 0x6 + + + 20ppm + LFXO crystal or external signal has an accuracy of 20 ppm. + 0x7 + + + + + MODE + LFXO mode. LFXO will not start unless MODE is configured. + 4 + 6 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Pierce + LFXO Pierce mode. + 0x0 + + + PIXO + LFXO PIXO mode. + 0x1 + + + ExtSine + LFXO in external sine wave mode. + 0x2 + + + ExtSquare + LFXO in external square wave mode. + 0x3 + + + + + LOADCAP + Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. + 8 + 15 + + + Unconfigured + The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is configured. + 0xFF + + + External + Do not use the built-in load capacitors, only external capacitors will be used. + 0x00 + + + + + TIME + LFXO startup time in ms. + 16 + 27 + + + Unconfigured + Startup time has not been configured. + 0xFFF + + + + + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. Note. This configuration overrides corresponding LFXO calibration in BICR when set. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0 + 31 + + + Calibrate + Calibrate the LFXO at startup. + 0xFFFFFFFF + + + + + + + LFRCAUTOCALCONFIG + LFRC autocalibration configuration. Note. This configuration overrides corresponding LFRC autocalibration configuration in BICR when set. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TEMPINTERVAL + Temperature measurement interval in 0.25 s steps. + 0 + 6 + + + TEMPDELTA + Temperature delta that should trigger a calibration in 0.25 degrees steps. + 8 + 13 + + + INTERVALMAXNO + Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature changes. + 16 + 20 + + + ENABLE + LFRC.AUTOCALCONFIG register enable. + 31 + 31 + + + Enabled + LFRC.AUTOCALCONFIG register has been configured and can be used. + 0x0 + + + Disabled + LFRC.AUTOCALCONFIG register has not been configured and cannot be used. + 0x1 + + + + + + + + HFXO64M + Unspecified + FICR_SIPINFO_OVERRIDE_HFXO64M + read-write + 0x010 + + CONFIG + HFXO64M configuration. Note. This configuration overrides corresponding XO configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MODE + HFXO64M mode. + 0 + 2 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Normal + Normal operating mode. + 0x0 + + + TCXO + TCXO/bypass mode + 0x1 + + + Crystal2 + Reserved value + 0x2 + + + Crystal3 + Reserved value + 0x3 + + + Crystal4 + Reserved value + 0x4 + + + Crystal5 + Reserved value + 0x5 + + + Crystal6 + Reserved value + 0x6 + + + + + + + + + + TRIM + Unspecified + FICR_TRIM + read-write + 0x100 + + GLOBAL + Unspecified + FICR_TRIM_GLOBAL + read-write + 0x244 + + SAADC + Unspecified + FICR_TRIM_GLOBAL_SAADC + read-write + 0x0 + + CALVREF + Trim value for GLOBAL.SAADC.CALVREF + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x3 + 0x4 + CALGAIN[%s] + Description collection: Trim value for GLOBAL.SAADC.CALGAIN + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALOFFSET + Trim value for GLOBAL.SAADC.CALOFFSET + 0x10 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF + 0x14 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALIREF + Trim value for GLOBAL.SAADC.CALIREF + 0x2C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALVREFTC + Trim value for GLOBAL.SAADC.CALVREFTC + 0x30 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + CANPLL + Unspecified + FICR_TRIM_GLOBAL_CANPLL + read-write + 0x3C + + TRIM + Unspecified + FICR_TRIM_GLOBAL_CANPLL_TRIM + read-write + 0x0 + + CTUNE + Trim value for GLOBAL.CANPLL.TRIM.CTUNE + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + COMP + Unspecified + FICR_TRIM_GLOBAL_COMP + read-write + 0x4C + + REFTRIM + Trim value for GLOBAL.COMP.REFTRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + APPLICATION + Unspecified + FICR_TRIM_APPLICATION + read-write + 0x298 + + HSFLL + Unspecified + FICR_TRIM_APPLICATION_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_APPLICATION_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for APPLICATION.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_APPLICATION_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + RADIOCORE + Unspecified + FICR_TRIM_RADIOCORE + read-write + 0x2DC + + HSFLL + Unspecified + FICR_TRIM_RADIOCORE_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_RADIOCORE_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for RADIOCORE.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + + + + GLOBAL_USBHSCORE0 + USBHSCORE + 0x2F700000 + USBHSCORE + + + + 0 + 0x24000 + registers + + USBHSCORE + 0x20 + + + GOTGCTL + Control and Status Register + 0x000 + read-write + 0x000D0000 + 0x20 + + + VBVALIDOVEN + Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) + 2 + 2 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller + 0x0 + + + ENABLED + The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal + 0x1 + + + + + VBVALIDOVVAL + Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) + 3 + 3 + + + SET0 + vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + 0x0 + + + SET1 + vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + 0x1 + + + + + AVALIDOVEN + Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) + 4 + 4 + + + DISABLED + Derive AValid from PHY + 0x0 + + + ENABLED + Derive Avalid from GOTGCTL.AvalidOvVal + 0x1 + + + + + AVALIDOVVAL + Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) + 5 + 5 + + + VALUE0 + Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + 0x0 + + + VALUE1 + Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + 0x1 + + + + + BVALIDOVEN + Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) + 6 + 6 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + ENABLED + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal + 0x1 + + + + + BVALIDOVVAL + Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) + 7 + 7 + + + VALUE0 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x0 + + + VALUE1 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x1 + + + + + DBNCEFLTRBYPASS + Mode: Host and Device. Debounce Filter Bypass + 15 + 15 + + + DISABLED + Debounce Filter Bypass is disabled. + 0x0 + + + ENABLED + Debounce Filter Bypass is enabled. + 0x1 + + + + + CONIDSTS + Mode: Host and Device. Connector ID Status (ConIDSts) + 16 + 16 + read-only + + + MODEA + The core is in A-Device mode. + 0x0 + + + MODEB + The core is in B-Device mode. + 0x1 + + + + + DBNCTIME + Mode: Host only. Long/Short Debounce Time (DbncTime) + 17 + 17 + read-only + + + LONG + Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + 0x0 + + + SHORT + Short debounce time, used for soft connections (2.5 micro-sec) + 0x1 + + + + + ASESVLD + Mode: Host only. A-Session Valid (ASesVld) + 18 + 18 + read-only + + + NOTVALID + A-session is not valid. + 0x0 + + + VALID + A-session is valid. + 0x1 + + + + + BSESVLD + Mode: Device only. B-Session Valid (BSesVld) + 19 + 19 + read-only + + + NOTVALID + B-session is not valid. + 0x0 + + + VALID + B-session is valid. + 0x1 + + + + + OTGVER + OTG Version (OTGVer) + 20 + 20 + + + VER13 + Supports OTG Version 1.3 + 0x0 + + + VER20 + Supports OTG Version 2.0 + 0x1 + + + + + CURMOD + Current Mode of Operation (CurMod) + 21 + 21 + read-only + + + DEVICEMODE + Current mode is device mode. + 0x0 + + + HOSTMODE + Current mode is host mode. + 0x1 + + + + + MULTVALIDBC + Mode: Host and Device. Multi Valued ID pin (MultValIdBC) + 22 + 26 + read-only + + + RID_C + B-Device connected to ACA. VBUS is on. + 0x01 + + + RID_B + B-Device connected to ACA. VBUS is off. + 0x02 + + + RID_A + A-Device connected to ACA + 0x04 + + + RID_GND + A-Device not connected to ACA + 0x08 + + + RID_FLOAT + B-Device not connected to ACA + 0x10 + + + + + CHIRPEN + Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used + 27 + 27 + + + CHIRP_DISABLE + The controller does not assert chirp_on before sending an actual Chirp 'K' signal on USB. + 0x0 + + + CHIRP_ENABLE + The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB. + 0x1 + + + + + + + GOTGINT + Interrupt Register + 0x004 + read-write + 0x00000000 + 0x20 + + + SESENDDET + Mode: Host and Device. Session End Detected (SesEndDet) + 2 + 2 + + + INACTIVE + Session is Active + 0x0 + + + ACTIVE + SessionEnd utmiotg_bvalid signal is deasserted + 0x1 + + + + + SESREQSUCSTSCHNG + Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) + 8 + 8 + + + INACTIVE + No Change in Session Request Status + 0x0 + + + ACTIVE + Session Request Status has changed + 0x1 + + + + + HSTNEGSUCSTSCHNG + Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) + 9 + 9 + + + INACTIVE + No Change + 0x0 + + + ACTIVE + Host Negotiation Status Change + 0x1 + + + + + HSTNEGDET + Mode:Host and Device. Host Negotiation Detected (HstNegDet) + 17 + 17 + + + INACTIVE + No Active HNP Request + 0x0 + + + ACTIVE + Active HNP request detected + 0x1 + + + + + ADEVTOUTCHG + Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) + 18 + 18 + + + INACTIVE + No A-Device Timeout + 0x0 + + + ACTIVE + A-Device Timeout + 0x1 + + + + + DBNCEDONE + Mode: Host only. Debounce Done (DbnceDone) + 19 + 19 + + + INACTIVE + After Connect waiting for Debounce to complete + 0x0 + + + ACTIVE + Debounce completed + 0x1 + + + + + MULTVALIPCHNG + This bit when set indicates that there is a change in the value of at least one ACA pin value. + 20 + 20 + + + NO_ACA_PIN_CHANGE + Indicates there is no change in ACA pin value + 0x0 + + + ACA_PIN_CHANGE + Indicates there is a change in ACA pin value + 0x1 + + + + + + + GAHBCFG + AHB Configuration Register + 0x008 + read-write + 0x00000000 + 0x20 + + + GLBLINTRMSK + Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) + 0 + 0 + + + MASK + Mask the interrupt assertion to the application + 0x0 + + + NOMASK + Unmask the interrupt assertion to the application. + 0x1 + + + + + HBSTLEN + Mode: Host and device. Burst Length/Type (HBstLen) + 1 + 4 + + + WORD1ORSINGLE + 1 word or single + 0x0 + + + WORD4ORINCR + 4 words or INCR + 0x1 + + + WORD8 + 8 words + 0x2 + + + WORD16ORINCR4 + 16 words or INCR4 + 0x3 + + + WORD32 + 32 words + 0x4 + + + WORD64ORINCR8 + 64 words or INCR8 + 0x5 + + + WORD128 + 128 words + 0x6 + + + WORD256ORINCR16 + 256 words or INCR16 + 0x7 + + + WORDX + Others reserved + 0x8 + + + + + DMAEN + Mode: Host and device. DMA Enable (DMAEn) + 5 + 5 + + + SLAVEMODE + Core operates in Slave mode + 0x0 + + + DMAMODE + Core operates in a DMA mode + 0x1 + + + + + NPTXFEMPLVL + Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + 7 + 7 + + + HALFEMPTY + DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or that the IN Endpoint TxFIFO is half empty. + 0x0 + + + EMPTY + GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty or that the IN Endpoint TxFIFO is completely empty. + 0x1 + + + + + REMMEMSUPP + Mode: Host and Device. Remote Memory Support (RemMemSupp) + 21 + 21 + + + DISABLED + Remote Memory Support Feature disabled + 0x0 + + + ENABLED + Remote Memory Support Feature enabled + 0x1 + + + + + NOTIALLDMAWRIT + Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) + 22 + 22 + + + LASTTRANS + Unspecified + 0x0 + + + ALLTRANS + The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint + 0x1 + + + + + AHBSINGLE + Mode: Host and Device. AHB Single Support (AHBSingle) + 23 + 23 + + + INCRBURST + The remaining data in the transfer is sent using INCR burst size + 0x0 + + + SINGLEBURST + The remaining data in the transfer is sent using Single burst size + 0x1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + read-write + 0x10001400 + 0x20 + + + TOUTCAL + Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) + 0 + 2 + + + ZERO + Add 0 PHY clocks + 0x0 + + + ONE + Add 1 PHY clocks + 0x1 + + + TWO + Add 2 PHY clocks + 0x2 + + + THREE + Add 3 PHY clocks + 0x3 + + + FOUR + Add 4 PHY clocks + 0x4 + + + FIVE + Add 5 PHY clocks + 0x5 + + + SIX + Add 6 PHY clocks + 0x6 + + + SEVEN + Add 7 PHY clocks + 0x7 + + + + + PHYIF + Mode: Host and Device. PHY Interface (PHYIf) + 3 + 3 + + + BITS8 + PHY 8bit Mode + 0x0 + + + BITS16 + PHY 16bit Mode + 0x1 + + + + + ULPIUTMISEL + Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) + 4 + 4 + read-only + + + UTMI + UTMI+ Interface + 0x0 + + + ULPI + ULPI Interface + 0x1 + + + + + FSINTF + Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) + 5 + 5 + read-only + + + FS6PIN + 6-pin unidirectional full-speed serial interface + 0x0 + + + FS3PIN + 3-pin bidirectional full-speed serial interface + 0x1 + + + + + PHYSEL + PHYSel + 6 + 6 + read-only + + + USB20 + USB 2.0 high-speed UTMI+ or ULPI PHY is selected + 0x0 + + + USB11 + USB 1.1 full-speed serial transceiver is selected + 0x1 + + + + + USBTRDTIM + Mode: Device only. USB Turnaround Time (USBTrdTim) + 10 + 13 + + + TURNTIME16BIT + MAC interface is 16-bit UTMI+. + 0x5 + + + TURNTIME8BIT + MAC interface is 8-bit UTMI+. + 0x9 + + + + + PHYLPWRCLKSEL + PHY Low-Power Clock Select (PhyLPwrClkSel) + 15 + 15 + + + INTPLLCLK + 480-MHz Internal PLL clock + 0x0 + + + EXTCLK + 48-MHz External Clock + 0x1 + + + + + TERMSELDLPULSE + Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) + 22 + 22 + + + TXVALID + Data line pulsing using utmi_txvalid + 0x0 + + + TERMSEL + Data line pulsing using utmi_termsel + 0x1 + + + + + ICUSBCAP + Mode: Host and Device. IC_USB-Capable (IC_USBCap) + 26 + 26 + read-only + + + NOTSELECTED + IC_USB PHY Interface is not selected + 0x0 + + + SELECTED + IC_USB PHY Interface is selected + 0x1 + + + + + TXENDDELAY + Mode: Device only. Tx End Delay (TxEndDelay) + 28 + 28 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Tx End delay + 0x1 + + + + + FORCEHSTMODE + Mode: Host and device. Force Host Mode (ForceHstMode) + 29 + 29 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Host Mode + 0x1 + + + + + FORCEDEVMODE + Mode:Host and device. Force Device Mode (ForceDevMode) + 30 + 30 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Device Mode + 0x1 + + + + + CORRUPTTXPKT + Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) + 31 + 31 + write-only + + + Disabled + Normal Mode + 0x0 + + + Enabled + Debug Mode + 0x1 + + + + + + + GRSTCTL + Reset Register + 0x010 + read-write + 0x80000000 + 0x20 + + + CSFTRST + Mode: Host and Device. Core Soft Reset (CSftRst) + 0 + 0 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Resets hclk and phy_clock domains + 0x1 + + + + + PIUFSSFTRST + Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + 1 + 1 + + + RESET_INACTIVE + No Reset + 0x0 + + + RESET_ACTIVE + PIU FS Dedicated Controller Soft Reset + 0x1 + + + + + FRMCNTRRST + Mode: Host only. Host Frame Counter Reset (FrmCntrRst) + 2 + 2 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Host Frame Counter Reset + 0x1 + + + + + RXFFLSH + Mode: Host and Device. RxFIFO Flush (RxFFlsh) + 4 + 4 + + + INACTIVE + Does not flush the entire RxFIFO + 0x0 + + + ACTIVE + Flushes the entire RxFIFO + 0x1 + + + + + TXFFLSH + Mode: Host and Device. TxFIFO Flush (TxFFlsh) + 5 + 5 + + + INACTIVE + No Flush + 0x0 + + + ACTIVE + Selectively flushes a single or all transmit FIFOs + 0x1 + + + + + TXFNUM + Mode: Host and Device. TxFIFO Number (TxFNum) + 6 + 10 + + + TXF0 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in shared FIFO operation -TXFIFO 0 flush in device mode when in dedicated FIFO mode + 0x00 + + + TXF1 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in shared FIFO operation -TXFIFO 1 flush in device mode when in dedicated FIFO mode + 0x01 + + + TXF2 + -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush in device mode when in dedicated FIFO mode + 0x02 + + + TXF3 + -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush in device mode when in dedicated FIFO mode + 0x03 + + + TXF4 + -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush in device mode when in dedicated FIFO mode + 0x04 + + + TXF5 + -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush in device mode when in dedicated FIFO mode + 0x05 + + + TXF6 + -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush in device mode when in dedicated FIFO mode + 0x06 + + + TXF7 + -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush in device mode when in dedicated FIFO mode + 0x07 + + + TXF8 + -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush in device mode when in dedicated FIFO mode + 0x08 + + + TXF9 + -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush in device mode when in dedicated FIFO mode + 0x09 + + + TXF10 + -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flush in device mode when in dedicated FIFO mode + 0x0A + + + TXF11 + -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flush in device mode when in dedicated FIFO mode + 0x0B + + + TXF12 + -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flush in device mode when in dedicated FIFO mode + 0x0C + + + TXF13 + -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flush in device mode when in dedicated FIFO mode + 0x0D + + + TXF14 + -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flush in device mode when in dedicated FIFO mode + 0x0E + + + TXF15 + -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flush in device mode when in dedicated FIFO mode + 0x0F + + + TXF16 + Flush all the transmit FIFOs in device or host mode + 0x10 + + + + + CSFTRSTDONE + Mode: Host and Device. Core Soft Reset Done (CSftRstDone) + 29 + 29 + + + INACTIVE + No reset + 0x0 + + + ACTIVE + Core Soft Reset is done + 0x1 + + + + + DMAREQ + Mode: Host and Device. DMA Request Signal (DMAReq) + 30 + 30 + read-only + + + INACTIVE + No DMA request + 0x0 + + + ACTIVE + DMA request is in progress + 0x1 + + + + + AHBIDLE + Mode: Host and Device. AHB Master Idle (AHBIdle) + 31 + 31 + read-only + + + INACTIVE + Not Idle + 0x0 + + + ACTIVE + AHB Master Idle + 0x1 + + + + + + + GINTSTS + Interrupt Register + 0x014 + read-write + 0x00000020 + 0x20 + + + CURMOD + Mode: Host and Device. Current Mode of Operation (CurMod) + 0 + 0 + read-only + + + DEVICE + Device mode + 0x0 + + + HOST + Host mode + 0x1 + + + + + MODEMIS + Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) + 1 + 1 + + + INACTIVE + No Mode Mismatch Interrupt + 0x0 + + + ACTIVE + Mode Mismatch Interrupt + 0x1 + + + + + OTGINT + Mode: Host and Device. OTG Interrupt (OTGInt) + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + OTG Interrupt + 0x1 + + + + + SOF + Mode: Host and Device. Start of (micro)Frame (Sof) + 3 + 3 + + + INTACTIVE + No Start of Frame + 0x0 + + + ACTIVE + Start of Frame + 0x1 + + + + + RXFLVL + Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) + 4 + 4 + read-only + + + INACTIVE + Rx Fifo is empty + 0x0 + + + ACTIVE + Rx Fifo is not empty + 0x1 + + + + + NPTXFEMP + Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) + 5 + 5 + read-only + + + INACTIVE + Non-periodic TxFIFO is not empty + 0x0 + + + ACTIVE + Non-periodic TxFIFO is empty + 0x1 + + + + + GINNAKEFF + Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) + 6 + 6 + read-only + + + INACTIVE + Global Non-periodic IN NAK not active + 0x0 + + + ACTIVE + Set Global Non-periodic IN NAK bit + 0x1 + + + + + GOUTNAKEFF + Mode: Device only. Global OUT NAK Effective (GOUTNakEff) + 7 + 7 + read-only + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Global OUT NAK Effective + 0x1 + + + + + ERLYSUSP + Mode: Device only. Early Suspend (ErlySusp) + 10 + 10 + + + INACTIVE + No Idle state detected + 0x0 + + + ACTIVE + 3ms of Idle state detected + 0x1 + + + + + USBSUSP + Mode: Device only. USB Suspend (USBSusp) + 11 + 11 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + USB Suspend + 0x1 + + + + + USBRST + Mode: Device only. USB Reset (USBRst) + 12 + 12 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + USB Reset + 0x1 + + + + + ENUMDONE + Mode: Device only. Enumeration Done (EnumDone) + 13 + 13 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Enumeration Done + 0x1 + + + + + ISOOUTDROP + Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + 14 + 14 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Isochronous OUT Packet Dropped Interrupt + 0x1 + + + + + EOPF + Mode: Device only. End of Periodic Frame Interrupt (EOPF) + 15 + 15 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + End of Periodic Frame Interrupt + 0x1 + + + + + RSTRDONEINT + Mode: Device only. Restore Done Interrupt (RstrDoneInt) + 16 + 16 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Restore Done Interrupt + 0x1 + + + + + EPMIS + Mode: Device only. Endpoint Mismatch Interrupt (EPMis) + 17 + 17 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Endpoint Mismatch Interrupt + 0x1 + + + + + IEPINT + Mode: Device only. IN Endpoints Interrupt (IEPInt) + 18 + 18 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + IN Endpoints Interrupt + 0x1 + + + + + OEPINT + Mode: Device only. OUT Endpoints Interrupt (OEPInt) + 19 + 19 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + OUT Endpoints Interrupt + 0x1 + + + + + INCOMPISOIN + Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) + 20 + 20 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Isochronous IN Transfer + 0x1 + + + + + INCOMPLP + Incomplete Periodic Transfer (incomplP) + 21 + 21 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Periodic Transfer + 0x1 + + + + + FETSUSP + Mode: Device only. Data Fetch Suspended (FetSusp) + 22 + 22 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Data Fetch Suspended + 0x1 + + + + + RESETDET + Mode: Device only. Reset detected Interrupt (ResetDet) + 23 + 23 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Reset detected Interrupt + 0x1 + + + + + PRTINT + Mode: Host only. Host Port Interrupt (PrtInt) + 24 + 24 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Port Interrupt + 0x1 + + + + + HCHINT + Mode: Host only. Host Channels Interrupt (HChInt) + 25 + 25 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Channels Interrupt + 0x1 + + + + + LPMINT + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). + 27 + 27 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + LPM Transaction Received Interrupt + 0x1 + + + + + CONIDSTSCHNG + Mode: Host and Device. Connector ID Status Change (ConIDStsChng) + 28 + 28 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Connector ID Status Change + 0x1 + + + + + DISCONNINT + Mode: Host only. Disconnect Detected Interrupt (DisconnInt) + 29 + 29 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Disconnect Detected Interrupt + 0x1 + + + + + SESSREQINT + Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) + 30 + 30 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Session Request New Session Detected Interrupt + 0x1 + + + + + WKUPINT + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) + 31 + 31 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Resume or Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GINTMSK + Interrupt Mask Register + 0x018 + read-write + 0x00000000 + 0x20 + + + MODEMISMSK + Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) + 1 + 1 + + + MASK + Mode Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Mode Mismatch Interrupt Mask + 0x1 + + + + + OTGINTMSK + Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) + 2 + 2 + + + MASK + OTG Interrupt Mask + 0x0 + + + NOMASK + No OTG Interrupt Mask + 0x1 + + + + + SOFMSK + Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) + 3 + 3 + + + MASK + Start of Frame Mask + 0x0 + + + NOMASK + No Start of Frame Mask + 0x1 + + + + + RXFLVLMSK + Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) + 4 + 4 + + + MASK + Receive FIFO Non-Empty Mask + 0x0 + + + NOMASK + No Receive FIFO Non-Empty Mask + 0x1 + + + + + NPTXFEMPMSK + Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + 5 + 5 + + + MASK + Non-periodic TxFIFO Empty Mask + 0x0 + + + NOMASK + No Non-periodic TxFIFO Empty Mask + 0x1 + + + + + GINNAKEFFMSK + Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + 6 + 6 + + + MASK + Global Non-periodic IN NAK Effective Mask + 0x0 + + + NOMASK + No Global Non-periodic IN NAK Effective Mask + 0x1 + + + + + GOUTNAKEFFMSK + Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) + 7 + 7 + + + MASK + Global OUT NAK Effective Mask + 0x0 + + + NOMASK + No Global OUT NAK Effective Mask + 0x1 + + + + + ERLYSUSPMSK + Mode: Device only. Early Suspend Mask (ErlySuspMsk) + 10 + 10 + + + MASK + Early Suspend Mask + 0x0 + + + NOMASK + No Early Suspend Mask + 0x1 + + + + + USBSUSPMSK + Mode: Device only. USB Suspend Mask (USBSuspMsk) + 11 + 11 + + + MASK + USB Suspend Mask + 0x0 + + + NOMASK + No USB Suspend Mask + 0x1 + + + + + USBRSTMSK + Mode: Device only. USB Reset Mask (USBRstMsk) + 12 + 12 + + + MASK + USB Reset Mask + 0x0 + + + NOMASK + No USB Reset Mask + 0x1 + + + + + ENUMDONEMSK + Mode: Device only. Enumeration Done Mask (EnumDoneMsk) + 13 + 13 + + + MASK + Enumeration Done Mask + 0x0 + + + NOMASK + No Enumeration Done Mask + 0x1 + + + + + ISOOUTDROPMSK + Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + 14 + 14 + + + MASK + Isochronous OUT Packet Dropped Interrupt Mask + 0x0 + + + NOMASK + No Isochronous OUT Packet Dropped Interrupt Mask + 0x1 + + + + + EOPFMSK + Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) + 15 + 15 + + + MASK + End of Periodic Frame Interrupt Mask + 0x0 + + + NOMASK + No End of Periodic Frame Interrupt Mask + 0x1 + + + + + RSTRDONEINTMSK + Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) + 16 + 16 + + + MASK + Restore Done Interrupt Mask + 0x0 + + + NOMASK + No Restore Done Interrupt Mask + 0x1 + + + + + EPMISMSK + Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) + 17 + 17 + + + MASK + Endpoint Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Endpoint Mismatch Interrupt Mask + 0x1 + + + + + IEPINTMSK + Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) + 18 + 18 + + + MASK + IN Endpoints Interrupt Mask + 0x0 + + + NOMASK + No IN Endpoints Interrupt Mask + 0x1 + + + + + OEPINTMSK + Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) + 19 + 19 + + + MASK + OUT Endpoints Interrupt Mask + 0x0 + + + NOMASK + No OUT Endpoints Interrupt Mask + 0x1 + + + + + INCOMPLPMSK + Incomplete Periodic Transfer Mask (incomplPMsk) + 21 + 21 + + + MASK + Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT Transfer Mask + 0x0 + + + NOMASK + Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous OUT Transfer Mask + 0x1 + + + + + FETSUSPMSK + Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) + 22 + 22 + + + MASK + Data Fetch Suspended Mask + 0x0 + + + NOMASK + No Data Fetch Suspended Mask + 0x1 + + + + + RESETDETMSK + Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) + 23 + 23 + + + MASK + Reset detected Interrupt Mask + 0x0 + + + NOMASK + No Reset detected Interrupt Mask + 0x1 + + + + + PRTINTMSK + Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) + 24 + 24 + + + MASK + Host Port Interrupt Mask + 0x0 + + + NOMASK + No Host Port Interrupt Mask + 0x1 + + + + + HCHINTMSK + Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) + 25 + 25 + + + MASK + Host Channels Interrupt Mask + 0x0 + + + NOMASK + No Host Channels Interrupt Mask + 0x1 + + + + + LPMINTMSK + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) + 27 + 27 + + + MASK + LPM Transaction received interrupt Mask + 0x0 + + + NOMASK + No LPM Transaction received interrupt Mask + 0x1 + + + + + CONIDSTSCHNGMSK + Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) + 28 + 28 + + + MASK + Connector ID Status Change Mask + 0x0 + + + NOMASK + No Connector ID Status Change Mask + 0x1 + + + + + DISCONNINTMSK + Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) + 29 + 29 + + + MASK + Disconnect Detected Interrupt Mask + 0x0 + + + NOMASK + No Disconnect Detected Interrupt Mask + 0x1 + + + + + SESSREQINTMSK + Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + 30 + 30 + + + MASK + Session Request or New Session Detected Interrupt Mask + 0x0 + + + NOMASK + No Session Request or New Session Detected Interrupt Mask + 0x1 + + + + + WKUPINTMSK + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + 31 + 31 + + + MASK + Resume or Remote Wakeup Detected Interrupt Mask + 0x0 + + + NOMASK + Unmask Resume Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GRXSTSR + Receive Status Debug Read Register + 0x01C + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + DSETUPRX + SETUP data packet received in device mode + 0x6 + + + CHHALT + Channel halted in host mode (triggers an interrupt) + 0x7 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXSTSP + Receive Status Read/Pop Register + 0x020 + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + read-write + 0x00000224 + 0x20 + + + RXFDEP + Mode: Host and Device. RxFIFO Depth (RxFDep) + 0 + 9 + + + + + GNPTXFSIZ + Non-periodic Transmit FIFO Size Register + 0x028 + read-write + 0x02000224 + 0x20 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start Address (NPTxFStAddr) + 0 + 9 + + + NPTXFDEP + Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) + 16 + 25 + + + + + GNPTXSTS + Non-periodic Transmit FIFO/Queue Status Register + 0x02C + read-write + 0x00080200 + 0x20 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + 0 + 15 + read-only + + + NPTXQSPCAVAIL + Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + 16 + 23 + read-only + + + FULL + Non-periodic Transmit Request Queue is full + 0x00 + + + QUE1 + 1 location available + 0x01 + + + QUE2 + 2 locations available + 0x02 + + + QUE3 + 3 locations available + 0x03 + + + QUE4 + 4 locations available + 0x04 + + + QUE5 + 5 locations available + 0x05 + + + QUE6 + 6 locations available + 0x06 + + + QUE7 + 7 locations available + 0x07 + + + QUE8 + 8 locations available + 0x08 + + + + + NPTXQTOP + Top of the Non-periodic Transmit Request Queue (NPTxQTop) + 24 + 30 + read-only + + + INOUTTK + IN/OUT token + 0x00 + + + ZEROTX + Zero-length transmit packet (device IN/host OUT) + 0x01 + + + PINGCSPLIT + PING/CSPLIT token + 0x02 + + + CHNHALT + Channel halt command + 0x03 + + + + + + + GGPIO + General Purpose Input/Output Register + 0x038 + read-write + 0x00000000 + 0x20 + + + GPI + 0 + 15 + read-only + + + GPO + 16 + 31 + + + + + GUID + User ID Register + 0x03C + read-write + 0x00000000 + 0x20 + + + GUID + User ID (UserID) Application-programmable ID field. + 0 + 31 + + + + + GSNPSID + Synopsys ID Register + 0x040 + read-write + 0x4F54430A + 0x20 + + + SYNOPSYSID + Release number of the controller being used currently. + 0 + 31 + read-only + + + + + GHWCFG1 + User Hardware Configuration 1 Register + 0x044 + read-write + 0xAA555000 + 0x20 + + + EPDIR + This 32-bit field uses two bits per + 0 + 31 + read-only + + + + + GHWCFG2 + User Hardware Configuration 2 Register + 0x048 + read-write + 0x228BFC72 + 0x20 + + + OTGMODE + Mode of Operation (OtgMode) + 0 + 2 + read-only + + + HNPSRP + HNP- and SRP-Capable OTG (Host and Device) + 0x0 + + + SRPOTG + SRP-Capable OTG (Host and Device) + 0x1 + + + NHNPNSRP + Non-HNP and Non-SRP Capable OTG (Host and Device) + 0x2 + + + SRPCAPD + SRP-Capable Device + 0x3 + + + NONOTGD + Non-OTG Device + 0x4 + + + SRPCAPH + SRP-Capable Host + 0x5 + + + NONOTGH + Non-OTG Host + 0x6 + + + + + OTGARCH + Architecture (OtgArch) + 3 + 4 + read-only + + + SLAVEMODE + Slave Mode + 0x0 + + + EXTERNALDMA + External DMA Mode + 0x1 + + + INTERNALDMA + Internal DMA Mode + 0x2 + + + + + SINGPNT + Point-to-Point (SingPnt) + 5 + 5 + read-only + + + MULTIPOINT + Multi-point application (hub and split support) + 0x0 + + + SINGLEPOINT + Single-point application (no hub and split support) + 0x1 + + + + + HSPHYTYPE + High-Speed PHY Interface Type (HSPhyType) + 6 + 7 + read-only + + + NOHS + High-Speed interface not supported + 0x0 + + + UTMIPLUS + High Speed Interface UTMI+ is supported + 0x1 + + + ULPI + High Speed Interface ULPI is supported + 0x2 + + + UTMIPUSULPI + High Speed Interfaces UTMI+ and ULPI is supported + 0x3 + + + + + FSPHYTYPE + Full-Speed PHY Interface Type (FSPhyType) + 8 + 9 + read-only + + + NO_FS + Full-speed interface not supported + 0x0 + + + FS + Dedicated full-speed interface is supported + 0x1 + + + FSPLUSUTMI + FS pins shared with UTMI+ pins is supported + 0x2 + + + FSPLUSULPI + FS pins shared with ULPI pins is supported + 0x3 + + + + + NUMDEVEPS + Number of Device Endpoints (NumDevEps) + 10 + 13 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + NUMHSTCHNL + Number of Host Channels (NumHstChnl) + 14 + 17 + read-only + + + HOSTCH0 + Host Channel 1 + 0x0 + + + HOSTCH1 + Host Channel 2 + 0x1 + + + HOSTCH2 + Host Channel 3 + 0x2 + + + HOSTCH3 + Host Channel 4 + 0x3 + + + HOSTCH4 + Host Channel 5 + 0x4 + + + HOSTCH5 + Host Channel 6 + 0x5 + + + HOSTCH6 + Host Channel 7 + 0x6 + + + HOSTCH7 + Host Channel 8 + 0x7 + + + HOSTCH8 + Host Channel 9 + 0x8 + + + HOSTCH9 + Host Channel 10 + 0x9 + + + HOSTCH10 + Host Channel 11 + 0xA + + + HOSTCH11 + Host Channel 12 + 0xB + + + HOSTCH12 + Host Channel 13 + 0xC + + + HOSTCH13 + Host Channel 14 + 0xD + + + HOSTCH14 + Host Channel 15 + 0xE + + + HOSTCH15 + Host Channel 16 + 0xF + + + + + PERIOSUPPORT + Periodic OUT Channels Supported in Host Mode (PerioSupport) + 18 + 18 + read-only + + + DISABLED + Periodic OUT Channels is not supported in Host Mode + 0x0 + + + ENABLED + Periodic OUT Channels Supported in Host Mode Supported + 0x1 + + + + + DYNFIFOSIZING + Dynamic FIFO Sizing Enabled (DynFifoSizing) + 19 + 19 + read-only + + + DISABLED + Dynamic FIFO Sizing Disabled + 0x0 + + + ENABLED + Dynamic FIFO Sizing Enabled + 0x1 + + + + + MULTIPROCINTRPT + Multi Processor Interrupt Enabled (MultiProcIntrpt) + 20 + 20 + read-only + + + DISABLED + No Multi Processor Interrupt Enabled + 0x0 + + + ENABLED + Multi Processor Interrupt Enabled + 0x1 + + + + + NPTXQDEPTH + Non-periodic Request Queue Depth (NPTxQDepth) + 22 + 23 + read-only + + + TWO + Queue size 2 + 0x0 + + + FOUR + Queue size 4 + 0x1 + + + EIGHT + Queue size 8 + 0x2 + + + + + PTXQDEPTH + Host Mode Periodic Request Queue Depth (PTxQDepth) + 24 + 25 + read-only + + + QUE2 + Queue Depth 2 + 0x0 + + + QUE4 + Queue Depth 4 + 0x1 + + + QUE8 + Queue Depth 8 + 0x2 + + + QUE16 + Queue Depth 16 + 0x3 + + + + + TKNQDEPTH + Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + 26 + 30 + read-only + + + + + GHWCFG3 + User Hardware Configuration 3 Register + 0x04C + read-write + 0x0BEAC0E8 + 0x20 + + + XFERSIZEWIDTH + Width of Transfer Size Counters (XferSizeWidth) + 0 + 3 + read-only + + + WIDTH11 + Width of Transfer Size Counter 11 bits + 0x0 + + + WIDTH12 + Width of Transfer Size Counter 12 bits + 0x1 + + + WIDTH13 + Width of Transfer Size Counter 13 bits + 0x2 + + + WIDTH14 + Width of Transfer Size Counter 14 bits + 0x3 + + + WIDTH15 + Width of Transfer Size Counter 15 bits + 0x4 + + + WIDTH16 + Width of Transfer Size Counter 16 bits + 0x5 + + + WIDTH17 + Width of Transfer Size Counter 17 bits + 0x6 + + + WIDTH18 + Width of Transfer Size Counter 18 bits + 0x7 + + + WIDTH19 + Width of Transfer Size Counter 19 bits + 0x8 + + + + + PKTSIZEWIDTH + Width of Packet Size Counters (PktSizeWidth) + 4 + 6 + read-only + + + BITS4 + Width of Packet Size Counter 4 + 0x0 + + + BITS5 + Width of Packet Size Counter 5 + 0x1 + + + BITS6 + Width of Packet Size Counter 6 + 0x2 + + + BITS7 + Width of Packet Size Counter 7 + 0x3 + + + BITS8 + Width of Packet Size Counter 8 + 0x4 + + + BITS9 + Width of Packet Size Counter 9 + 0x5 + + + BITS10 + Width of Packet Size Counter 10 + 0x6 + + + + + OTGEN + OTG Function Enabled (OtgEn) + 7 + 7 + read-only + + + DISABLED + Not OTG Capable + 0x0 + + + ENABLED + OTG Capable + 0x1 + + + + + I2CINTSEL + I2C Selection (I2CIntSel) + 8 + 8 + read-only + + + DISABLED + I2C Interface is not available + 0x0 + + + ENABLED + I2C Interface is available + 0x1 + + + + + VNDCTLSUPT + Vendor Control Interface Support (VndctlSupt) + 9 + 9 + read-only + + + DISABLED + Vendor Control Interface is not available. + 0x0 + + + ENABLED + Vendor Control Interface is available. + 0x1 + + + + + OPTFEATURE + Optional Features Removed (OptFeature) + 10 + 10 + read-only + + + DISABLED + Optional features were not Removed + 0x0 + + + ENABLED + Optional Features have been Removed + 0x1 + + + + + RSTTYPE + Reset Style for Clocked always Blocks in RTL (RstType) + 11 + 11 + read-only + + + ASYNCRST + Asynchronous reset is used in the core + 0x0 + + + SYNCRST + Synchronous reset is used in the core + 0x1 + + + + + ADPSUPPORT + This bit indicates whether ADP logic is present within or external to the controller + 12 + 12 + read-only + + + DISABLED + ADP logic is not present along with the controller + 0x0 + + + ENABLED + ADP logic is present along with the controller + 0x1 + + + + + HSICMODE + HSIC mode specified for Mode of Operation + 13 + 13 + read-only + + + DISABLED + No HSIC capability + 0x0 + + + ENABLED + HSIC-capable with shared UTMI PHY interface + 0x1 + + + + + BCSUPPORT + This bit indicates the controller support for Battery Charger. + 14 + 14 + read-only + + + DISABLED + No Battery Charger Support + 0x0 + + + ENABLED + Battery Charger Support present + 0x1 + + + + + LPMMODE + LPM mode specified for Mode of Operation. + 15 + 15 + read-only + + + DISABLED + LPM disabled + 0x0 + + + ENABLED + LPM enabled + 0x1 + + + + + DFIFODEPTH + DFIFO Depth (DfifoDepth - EP_LOC_CNT) + 16 + 31 + read-only + + + + + GHWCFG4 + User Hardware Configuration 4 Register + 0x050 + read-write + 0x1E10AA60 + 0x20 + + + NUMDEVPERIOEPS + Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + 0 + 3 + read-only + + + Value0 + Number of Periodic IN EPs is 0 + 0x0 + + + Value1 + Number of Periodic IN EPs is 1 + 0x1 + + + Value2 + Number of Periodic IN EPs is 2 + 0x2 + + + Value3 + Number of Periodic IN EPs is 3 + 0x3 + + + Value4 + Number of Periodic IN EPs is 4 + 0x4 + + + Value5 + Number of Periodic IN EPs is 5 + 0x5 + + + Value6 + Number of Periodic IN EPs is 6 + 0x6 + + + Value7 + Number of Periodic IN EPs is 7 + 0x7 + + + Value8 + Number of Periodic IN EPs is 8 + 0x8 + + + Value9 + Number of Periodic IN EPs is 9 + 0x9 + + + Value10 + Number of Periodic IN EPs is 10 + 0xA + + + Value11 + Number of Periodic IN EPs is 11 + 0xB + + + Value12 + Number of Periodic IN EPs is 12 + 0xC + + + Value13 + Number of Periodic IN EPs is 13 + 0xD + + + Value14 + Number of Periodic IN EPs is 14 + 0xE + + + Value15 + Number of Periodic IN EPs is 15 + 0xF + + + + + PARTIALPWRDN + Enable Partial Power Down (PartialPwrDn) + 4 + 4 + read-only + + + DISABLED + Partial Power Down disabled + 0x0 + + + ENABLED + Partial Power Down enabled + 0x1 + + + + + AHBFREQ + Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + 5 + 5 + read-only + + + DISABLED + Minimum AHB Frequency More Than 60 MHz + 0x0 + + + ENABLED + Minimum AHB Frequency Less Than 60 MHz + 0x1 + + + + + HIBERNATION + Enable Hibernation (Hibernation) + 6 + 6 + read-only + + + DISABLED + Hibernation feature disabled + 0x0 + + + ENABLED + Hibernation feature enabled + 0x1 + + + + + EXTENDEDHIBERNATION + Enable Hibernation + 7 + 7 + read-only + + + DISABLED + Extended Hibernation feature not enabled + 0x0 + + + ENABLED + Extended Hibernation feature enabled + 0x1 + + + + + ENHANCEDLPMSUPT1 + Enhanced LPM Support1 (EnhancedLPMSupt1) + 9 + 9 + read-only + + + DISABLED + Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty. + 0x0 + + + ENABLED + Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty + 0x1 + + + + + SERVINTFLOW + Service Interval Flow + 10 + 10 + read-only + + + DISABLED + Service Interval Flow not supported + 0x0 + + + ENABLED + Service Interval Flow supported + 0x1 + + + + + IPGISOCSUPT + Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) + 11 + 11 + read-only + + + DISABLED + Interpacket Gap ISOC OUT Worst-case Support is Disabled + 0x0 + + + ENABLED + Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) + 0x1 + + + + + ACGSUPT + Active Clock Gating Support + 12 + 12 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Active Clock Gating Support + 0x1 + + + + + ENHANCEDLPMSUPT + Enhanced LPM Support (EnhancedLPMSupt) + 13 + 13 + read-only + + + ENABLED + Enhanced LPM Support is enabled + 0x1 + + + + + PHYDATAWIDTH + UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + 14 + 15 + read-only + + + WIDTH1 + 8 bits + 0x0 + + + WIDTH2 + 16 bits + 0x1 + + + WIDTH3 + 8/16 bits, software selectable + 0x2 + + + + + NUMCTLEPS + Number of Device Mode Control Endpoints in Addition to + 16 + 19 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + IDDGFLTR + IDDIG Filter Enable (IddgFltr) + 20 + 20 + read-only + + + DISABLED + Iddig Filter Disabled + 0x0 + + + ENABLED + Iddig Filter Enabled + 0x1 + + + + + VBUSVALIDFLTR + VBUS Valid Filter Enabled (VBusValidFltr) + 21 + 21 + read-only + + + DISABLED + Vbus Valid Filter Disabled + 0x0 + + + ENABLED + Vbus Valid Filter Enabled + 0x1 + + + + + AVALIDFLTR + a_valid Filter Enabled (AValidFltr) + 22 + 22 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + BVALIDFLTR + b_valid Filter Enabled (BValidFltr) + 23 + 23 + read-only + + + DISABLED + No Filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + SESSENDFLTR + session_end Filter Enabled (SessEndFltr) + 24 + 24 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + DEDFIFOMODE + Enable Dedicated Transmit FIFO for device IN Endpoints + 25 + 25 + read-only + + + DISABLED + Dedicated Transmit FIFO Operation not enabled + 0x0 + + + ENABLED + Dedicated Transmit FIFO Operation enabled + 0x1 + + + + + INEPS + Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + 26 + 29 + read-only + + + ENDPT1 + 1 IN Endpoint + 0x0 + + + ENDPT2 + 2 IN Endpoints + 0x1 + + + ENDPT3 + 3 IN Endpoints + 0x2 + + + ENDPT4 + 4 IN Endpoints + 0x3 + + + ENDPT5 + 5 IN Endpoints + 0x4 + + + ENDPT6 + 6 IN Endpoints + 0x5 + + + ENDPT7 + 7 IN Endpoints + 0x6 + + + ENDPT8 + 8 IN Endpoints + 0x7 + + + ENDPT9 + 9 IN Endpoints + 0x8 + + + ENDPT10 + 10 IN Endpoints + 0x9 + + + ENDPT11 + 11 IN Endpoints + 0xA + + + ENDPT12 + 12 IN Endpoints + 0xB + + + ENDPT13 + 13 IN Endpoints + 0xC + + + ENDPT14 + 14 IN Endpoints + 0xD + + + ENDPT15 + 15 IN Endpoints + 0xE + + + ENDPT16 + 16 IN Endpoints + 0xF + + + + + DESCDMAENABLED + Scatter/Gather DMA configuration + 30 + 30 + read-only + + + DISABLE + Non-Scatter/Gather DMA configuration + 0x0 + + + ENABLE + Scatter/Gather DMA configuration + 0x1 + + + + + DESCDMA + Scatter/Gather DMA configuration + 31 + 31 + read-only + + + CONFIG1 + Non Dynamic configuration + 0x0 + + + CONFIG2 + Dynamic configuration + 0x1 + + + + + + + GLPMCFG + LPM Config Register + 0x054 + read-write + 0x00000000 + 0x20 + + + LPMCAP + LPM-Capable (LPMCap) + 0 + 0 + + + DISABLED + LPM capability is not enabled + 0x0 + + + ENABLED + LPM capability is enabled + 0x1 + + + + + APPL1RES + Mode: Device only. LPM response programmed by application (AppL1Res) + 1 + 1 + + + NYET_RESP + The core responds with a NYET when an error is detected in either of the LPM token packets due to corruption + 0x0 + + + ACK_RESP + The core responds with an ACK only on a successful LPM transaction + 0x1 + + + + + HIRD + Host-Initiated Resume Duration (HIRD) + 2 + 5 + + + BREMOTEWAKE + RemoteWakeEnable (bRemoteWake) + 6 + 6 + + + DISABLED + Remote Wakeup is disabled + 0x0 + + + ENABLED + In Host or device mode, this field takes the value of remote wake up + 0x1 + + + + + ENBLSLPM + Enable utmi_sleep_n (EnblSlpM) + 7 + 7 + + + DISABLED + utmi_sleep_n assertion from the core is not transferred to the external PHY + 0x0 + + + ENABLED + utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted + 0x1 + + + + + HIRDTHRES + BESL/HIRD Threshold (HIRD_Thres) + 8 + 12 + + + COREL1RES + LPM Response (CoreL1Res) + 13 + 14 + read-only + + + LPMRESP1 + ERROR : No handshake response + 0x0 + + + LPMRESP2 + STALL response + 0x1 + + + LPMRESP3 + NYET response + 0x2 + + + LPMRESP4 + ACK response + 0x3 + + + + + SLPSTS + Port Sleep Status (SlpSts) + 15 + 15 + read-only + + + CORE_NOT_IN_L1 + In Host or Device mode, this bit indicates core is not in L1 + 0x0 + + + CORE_IN_L1 + In Host mode, this bit indicates the core transitions to Sleep state as a successful LPM transaction. In Device mode, the core enters the Sleep state when an ACK response is sent to an LPM transaction + 0x1 + + + + + L1RESUMEOK + Sleep State Resume OK (L1ResumeOK) + 16 + 16 + read-only + + + NOTOK + The application/core cannot start Resume from Sleep state + 0x0 + + + OK + The application/core can start Resume from Sleep state + 0x1 + + + + + LPMCHNLINDX + LPM Channel Index + 17 + 20 + + + CH0 + Channel 0 + 0x0 + + + CH1 + Channel 1 + 0x1 + + + CH2 + Channel 2 + 0x2 + + + CH3 + Channel 3 + 0x3 + + + CH4 + Channel 4 + 0x4 + + + CH5 + Channel 5 + 0x5 + + + CH6 + Channel 6 + 0x6 + + + CH7 + Channel 7 + 0x7 + + + CH8 + Channel 8 + 0x8 + + + CH9 + Channel 9 + 0x9 + + + CH10 + Channel 10 + 0xA + + + CH11 + Channel 11 + 0xB + + + CH12 + Channel 12 + 0xC + + + CH13 + Channel 13 + 0xD + + + CH14 + Channel 14 + 0xE + + + CH15 + Channel15 + 0xF + + + + + LPMRETRYCNT + LPM Retry Count (LPM_Retry_Cnt) + 21 + 23 + + + RETRY0 + Zero LPM retries + 0x0 + + + RETRY1 + One LPM retry + 0x1 + + + RETRY2 + Two LPM retries + 0x2 + + + RETRY3 + Three LPM retries + 0x3 + + + RETRY4 + Four LPM retries + 0x4 + + + RETRY5 + Five LPM retries + 0x5 + + + RETRY6 + Six LPM retries + 0x6 + + + RETRY7 + Seven LPM retries + 0x7 + + + + + SNDLPM + Send LPM Transaction (SndLPM) + 24 + 24 + + + DISABLED + In host-only mode: Received the response from the device for the LPM transaction + 0x0 + + + ENABLED + In host-only mode: Sending LPM transaction containing EXT and LPM tokens + 0x1 + + + + + LPMRETRYCNTSTS + LPM Retry Count Status (LPM_RetryCnt_Sts) + 25 + 27 + read-only + + + RETRY_REM0 + Zero LPM retries remaining + 0x0 + + + RETRY_REM1 + One LPM retry remaining + 0x1 + + + RETRY_REM2 + Two LPM retries remaining + 0x2 + + + RETRY_REM3 + Three LPM retries remaining + 0x3 + + + RETRY_REM4 + Four LPM retries remaining + 0x4 + + + RETRY_REM5 + Five LPM retries remaining + 0x5 + + + RETRY_REM6 + Six LPM retries remaining + 0x6 + + + RETRY_REM7 + Seven LPM retries remaining + 0x7 + + + + + LPMENBESL + LPM Enable BESL (LPM_EnBESL) + 28 + 28 + + + DISABLED + BESL is disabled + 0x0 + + + ENABLED + BESL is enabled as defined in LPM Errata + 0x1 + + + + + LPMRESTORESLPSTS + LPM Restore Sleep Status (LPM_RestoreSlpSts) + 29 + 29 + + + DISABLED + Puts the core in Shallow Sleep mode based on the BESL value from the Host + 0x0 + + + ENABLED + Puts the core in Deep Sleep mode based on the BESL value from the Host + 0x1 + + + + + + + GPWRDN + Global Power Down Register + 0x058 + read-write + 0x00000010 + 0x20 + + + PMUINTSEL + PMU Interrupt Select (PMUIntSel) + 0 + 0 + + + DISABLE + Internal DWC_otg_core interrupt is selected + 0x0 + + + ENABLE + External DWC_otg_pmu interrupt is selected + 0x1 + + + + + PMUACTV + PMU Active (PMUActv) + 1 + 1 + + + DISABLE + Disable PMU module + 0x0 + + + ENABLE + Enable PMU module + 0x1 + + + + + RESTORE + Restore + 2 + 2 + + + DISABLE + The controller in normal mode of operation + 0x0 + + + ENABLE + The controller in Restore mode + 0x1 + + + + + PWRDNCLMP + Power Down Clamp (PwrDnClmp) + 3 + 3 + + + DISABLE + Disable PMU power clamp + 0x0 + + + ENABLE + Enable PMU power clamp + 0x1 + + + + + PWRDNRSTN + Power Down ResetN (PwrDnRst_n) + 4 + 4 + + + DISABLE + Reset the controller + 0x0 + + + ENABLE + The controller is in normal operation + 0x1 + + + + + PWRDNSWTCH + Power Down Switch (PwrDnSwtch) + 5 + 5 + + + ON + The controller is in ON state + 0x0 + + + OFF + The controller is in OFF state + 0x1 + + + + + DISABLEVBUS + DisableVBUS + 6 + 6 + + + DISABLED + Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid + 0x0 + + + ENABLED + Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End + 0x1 + + + + + LNSTSCHNG + Line State Change (LnStsChng) + 7 + 7 + + + DISABLED + No LineState change on USB + 0x0 + + + ENABLED + LineState change on USB + 0x1 + + + + + LINESTAGECHANGEMSK + LineStageChangeMsk + 8 + 8 + + + NOMASK + No LineStateChange Interrupt Mask + 0x0 + + + MASK + Mask for LineStateChange Interrupt + 0x1 + + + + + RESETDETECTED + ResetDetected + 9 + 9 + + + DISABLED + Reset not detected + 0x0 + + + ENABLED + Reset detected + 0x1 + + + + + RESETDETMSK + ResetDetMsk + 10 + 10 + + + NOMASK + No ResetDetect Interrupt Mask + 0x0 + + + MASK + Mask for ResetDetect Interrupt + 0x1 + + + + + DISCONNECTDETECT + DisconnectDetect + 11 + 11 + + + DISABLED + Disconnect not detected + 0x0 + + + ENABLED + Disconnect detected + 0x1 + + + + + DISCONNECTDETECTMSK + DisconnectDetectMsk + 12 + 12 + + + NOMASK + No DisconnectDetect Interrupt Mask + 0x0 + + + MASK + Mask for DisconnectDetect Interrupt + 0x1 + + + + + CONNECTDET + ConnectDet + 13 + 13 + + + DISABLED + Connect not detected + 0x0 + + + ENABLED + Connect detected + 0x1 + + + + + CONNDETMSK + ConnDetMsk + 14 + 14 + + + NOMASK + No ConnectDet Interrupt Mask + 0x0 + + + MASK + Mask for ConnectDet Interrupt + 0x1 + + + + + SRPDETECT + SRPDetect + 15 + 15 + + + DISABLED + SRP not detected + 0x0 + + + ENABLED + SRP detected + 0x1 + + + + + SRPDETECTMSK + SRPDetectMsk + 16 + 16 + + + NOMASK + No SRPDetect Interrupt Mask + 0x0 + + + MASK + Mask for SRPDetect Interrupt + 0x1 + + + + + STSCHNGINT + Status Change Interrupt (StsChngInt) + 17 + 17 + + + DISABLED + No Status change + 0x0 + + + ENABLED + Status change detected + 0x1 + + + + + STSCHNGINTMSK + StsChngIntMsk + 18 + 18 + + + NOMASK + No Status Change Interrupt Mask + 0x0 + + + MASK + Mask for Status Change Interrupt + 0x1 + + + + + LINESTATE + LineState + 19 + 20 + read-only + + + LS1 + Linestate on USB: DM = 0, DP = 0 + 0x0 + + + LS2 + Linestate on USB: DM = 0, DP = 1 + 0x1 + + + LS3 + Linestate on USB: DM = 1, DP = 0 + 0x2 + + + LS4 + Linestate on USB: Not-defined + 0x3 + + + + + IDDIG + This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application. + 21 + 21 + read-only + + + DISABLED + Host Mode + 0x0 + + + ENABLED + Device Mode + 0x1 + + + + + BSESSVLD + B Session Valid (BSessVld) + 22 + 22 + read-only + + + NOTVALID + B_Valid is 0 + 0x0 + + + VALID + B_Valid is 1 + 0x1 + + + + + MULTVALIDBC + MultValIdBC + 24 + 28 + read-only + + + RID_0 + OTG device as B-device + 0x00 + + + RID_C + OTG device as B-device, can connect + 0x01 + + + RID_B + OTG device as B-device, cannot connect + 0x02 + + + RID_A + OTG device as A-device + 0x04 + + + RID_GND + ID_OTG pin is grounded + 0x08 + + + RID_A_RID_GND + OTG device as A-device, RID_A=1 and RID_GND=1 + 0x0C + + + RID_FLOAT + ID pull down when ID_OTG is floating + 0x10 + + + RID_C_RID_FLOAT + OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1 + 0x11 + + + RID_B_RID_FLOAT + OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1 + 0x12 + + + RID_1 + OTG device as A-device + 0x1F + + + + + + + GDFIFOCFG + Global DFIFO Configuration Register + 0x05C + read-write + 0x0BEA0C00 + 0x20 + + + GDFIFOCFG + GDFIFOCfg + 0 + 15 + + + EPINFOBASEADDR + This field provides the start address of the EP info controller. + 16 + 31 + + + + + GINTMSK2 + Interrupt Mask Register 2 + 0x068 + read-write + 0x00000000 + 0x20 + + + GINTMSK2 + 0 + 31 + + + + + GINTSTS2 + Interrupt Register 2 + 0x06C + read-write + 0x00000000 + 0x20 + + + GINTSTS2 + 0 + 31 + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + read-write + 0x04000424 + 0x20 + + + PTXFSTADDR + Host Periodic TxFIFO Start Address (PTxFStAddr) + 0 + 10 + + + PTXFSIZE + Host Periodic TxFIFO Depth (PTxFSize) + 16 + 26 + + + + + 0x7 + 0x4 + DIEPTXF[%s] + Description collection: Device IN Endpoint Transmit FIFO Size Register + 0x104 + read-write + 0x02000424 + 0x20 + + + INEPNTXFSTADDR + IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + 0 + 10 + + + INEPNTXFDEP + IN Endpoint TxFIFO Depth (INEPnTxFDep) + 16 + 25 + + + + + HCFG + Host Configuration Register + 0x400 + read-write + 0x00000200 + 0x20 + + + FSLSPCLKSEL + FS/LS PHY Clock Select (FSLSPclkSel) + 0 + 1 + + + CLK3060 + PHY clock is running at 30/60 MHz + 0x0 + + + CLK48 + PHY clock is running at 48 MHz + 0x1 + + + CLK6 + PHY clock is running at 6 MHz + 0x2 + + + + + FSLSSUPP + FS- and LS-Only Support (FSLSSupp) + 2 + 2 + + + HSFSLS + HS/FS/LS, based on the maximum speed supported by the connected device + 0x0 + + + FSLS + FS/LS-only, even if the connected device can support HS + 0x1 + + + + + ENA32KHZS + Enable 32 KHz Suspend mode (Ena32KHzS) + 7 + 7 + + + DISABLED + 32 KHz Suspend mode disabled + 0x0 + + + ENABLED + 32 KHz Suspend mode enabled + 0x1 + + + + + RESVALID + Resume Validation Period (ResValid) + 8 + 15 + + + MODECHTIMEN + Mode Change Ready Timer Enable (ModeChTimEn) + 31 + 31 + + + ENABLED + The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x0 + + + DISABLED + The Host core waits only for a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x1 + + + + + + + HFIR + Host Frame Interval Register + 0x404 + read-write + 0x0000EA60 + 0x20 + + + FRINT + Frame Interval (FrInt) + 0 + 15 + + + HFIRRLDCTRL + Reload Control (HFIRRldCtrl) + 16 + 16 + + + DISABLED + The HFIR cannot be reloaded dynamically + 0x0 + + + ENABLED + The HFIR can be dynamically reloaded during runtime + 0x1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + read-write + 0x00003FFF + 0x20 + + + FRNUM + Frame Number (FrNum) + 0 + 15 + read-only + + + INACTIVE + No SOF is transmitted + 0x0000 + + + ACTIVE + SOF is transmitted + 0x0001 + + + + + FRREM + Frame Time Remaining (FrRem) + 16 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + read-write + 0x00000000 + 0x20 + + + HAINT + 0 + 15 + read-only + + + INACTIVE + Not active + 0x0000 + + + ACTIVE + Host Channel Interrupt + 0x0001 + + + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + read-write + 0x00000000 + 0x20 + + + HAINTMSK + Channel Interrupt Mask (HAINTMsk) + 0 + 15 + + + UNMASK + Unmask Channel interrupt + 0x0000 + + + MASK + Mask Channel interrupt + 0x0001 + + + + + + + HPRT + Host Port Control and Status Register + 0x440 + read-write + 0x00000000 + 0x20 + + + PRTCONNSTS + Port Connect Status (PrtConnSts) + 0 + 0 + read-only + + + NOTATTACHED + No device is attached to the port + 0x0 + + + ATTACHED + A device is attached to the port + 0x1 + + + + + PRTCONNDET + Port Connect Detected (PrtConnDet) + 1 + 1 + + + INACTIVE + No device connection detected + 0x0 + + + ACTIVE + Device connection detected + 0x1 + + + + + PRTENA + Port Enable (PrtEna) + 2 + 2 + + + DISABLED + Port disabled + 0x0 + + + ENABLED + Port enabled + 0x1 + + + + + PRTENCHNG + Port Enable/Disable Change (PrtEnChng) + 3 + 3 + + + INACTIVE + Port Enable bit 2 has not changed + 0x0 + + + ACTIVE + Port Enable bit 2 changed + 0x1 + + + + + PRTOVRCURRACT + Port Overcurrent Active (PrtOvrCurrAct) + 4 + 4 + read-only + + + INACTIVE + No overcurrent condition + 0x0 + + + ACTIVE + Overcurrent condition + 0x1 + + + + + PRTOVRCURRCHNG + Port Overcurrent Change (PrtOvrCurrChng) + 5 + 5 + + + INACTIVE + Status of port overcurrent status is not changed + 0x0 + + + ACTIVE + Status of port overcurrent changed + 0x1 + + + + + PRTRES + Port Resume (PrtRes) + 6 + 6 + + + NORESUME + No resume driven + 0x0 + + + RESUME + Resume driven + 0x1 + + + + + PRTSUSP + Port Suspend (PrtSusp) + 7 + 7 + + + INACTIVE + Port not in Suspend mode + 0x0 + + + ACTIVE + Port in Suspend mode + 0x1 + + + + + PRTRST + Port Reset (PrtRst) + 8 + 8 + + + DISABLED + Port not in reset + 0x0 + + + ENABLED + Port in reset + 0x1 + + + + + PRTLNSTS + Port Line Status (PrtLnSts) + 10 + 11 + read-only + + + PLUSD + Logic level of D+ + 0x1 + + + MINUSD + Logic level of D- + 0x2 + + + + + PRTPWR + Port Power (PrtPwr) + 12 + 12 + + + OFF + Power off + 0x0 + + + ON + Power on + 0x1 + + + + + PRTTSTCTL + Port Test Control (PrtTstCtl) + 13 + 16 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFENB + Test_force_Enable + 0x5 + + + + + PRTSPD + Port Speed (PrtSpd) + 17 + 18 + read-only + + + HIGHSPD + High speed + 0x0 + + + FULLSPD + Full speed + 0x1 + + + LOWSPD + Low speed + 0x2 + + + + + + + 16 + 0x018 + HC[%s] + Unspecified + USBHSCORE_HC + read-write + 0x500 + + CHAR + Description cluster: Host Channel Characteristics Register + 0x000 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + EPNUM + Endpoint Number (EPNum) + 11 + 14 + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + EPDIR + Endpoint Direction (EPDir) + 15 + 15 + + + OUT + OUT Direction + 0x0 + + + IN + IN Direction + 0x1 + + + + + LSPDDEV + Low-Speed Device (LSpdDev) + 17 + 17 + + + DISABLED + Not Communicating with low speed device + 0x0 + + + ENABLED + Communicating with low speed device + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CTRL + Control + 0x0 + + + ISOC + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERR + Interrupt + 0x3 + + + + + EC + Multi Count (MC) / Error Count (EC) + 20 + 21 + + + TRANSONE + 1 transaction + 0x1 + + + TRANSTWO + 2 transactions to be issued for this endpoint per microframe + 0x2 + + + TRANSTHREE + 3 transactions to be issued for this endpoint per microframe + 0x3 + + + + + DEVADDR + Device Address (DevAddr) + 22 + 28 + + + ODDFRM + Odd Frame (OddFrm) + 29 + 29 + + + EFRAME + Even Frame Transfer + 0x0 + + + OFRAME + Odd Frame Transfer + 0x1 + + + + + CHDIS + Channel Disable (ChDis) + 30 + 30 + + + INACTIVE + Transmit/Recieve normal + 0x0 + + + ACTIVE + Stop transmitting/receiving data on channel + 0x1 + + + + + CHENA + Channel Enable (ChEna) + 31 + 31 + + + DISABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is disabled. + 0x0 + + + ENABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure and data buffer with data is set up and this channel can access the descriptor. If Scatter/Gather mode is disabled, indicates that the channel is enabled. + 0x1 + + + + + + + INT + Description cluster: Host Channel Interrupt Register + 0x008 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed (XferCompl) + 0 + 0 + + + INACTIVE + Transfer in progress or No Active Transfer + 0x0 + + + ACTIVE + Transfer completed normally without any errors + 0x1 + + + + + CHHLTD + Channel Halted (ChHltd) + 1 + 1 + + + INACTIVE + Channel not halted + 0x0 + + + ACTIVE + Channel Halted + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB error + 0x0 + + + ACTIVE + AHB error during AHB read/write + 0x1 + + + + + STALL + STALL Response Received Interrupt (STALL) + 3 + 3 + + + INACTIVE + No Stall Response Received Interrupt + 0x0 + + + ACTIVE + Stall Response Received Interrupt + 0x1 + + + + + NAK + NAK Response Received Interrupt (NAK) + 4 + 4 + + + INACTIVE + No NAK Response Received Interrupt + 0x0 + + + ACTIVE + NAK Response Received Interrupt + 0x1 + + + + + ACK + ACK Response Received/Transmitted Interrupt (ACK) + 5 + 5 + + + INACTIVE + No ACK Response Received or Transmitted Interrupt + 0x0 + + + ACTIVE + ACK Response Received or Transmitted Interrup + 0x1 + + + + + NYET + NYET Response Received Interrupt (NYET) + 6 + 6 + + + INACTIVE + No NYET Response Received Interrupt + 0x0 + + + ACTIVE + NYET Response Received Interrupt + 0x1 + + + + + XACTERR + Transaction Error (XactErr) + 7 + 7 + + + INACTIVE + No Transaction Error + 0x0 + + + ACTIVE + Transaction Error + 0x1 + + + + + BBLERR + Babble Error (BblErr) + 8 + 8 + + + INACTIVE + No Babble Error + 0x0 + + + ACTIVE + Babble Error + 0x1 + + + + + FRMOVRUN + Frame Overrun (FrmOvrun). + 9 + 9 + + + INACTIVE + No Frame Overrun + 0x0 + + + ACTIVE + Frame Overrun + 0x1 + + + + + DATATGLERR + 10 + 10 + + + INACTIVE + No Data Toggle Error + 0x0 + + + ACTIVE + Data Toggle Error + 0x1 + + + + + + + INTMSK + Description cluster: Host Channel Interrupt Mask Register + 0x00C + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + 0 + 0 + + + MASK + Transfer Completed Mask + 0x0 + + + NOMASK + No Transfer Completed Mask + 0x1 + + + + + CHHLTDMSK + 1 + 1 + + + MASK + Channel Halted Mask + 0x0 + + + NOMASK + No Channel Halted Mask + 0x1 + + + + + AHBERRMSK + 2 + 2 + + + MASK + AHB Error Mask + 0x0 + + + NOMASK + No AHB Error Mask + 0x1 + + + + + STALLMSK + 3 + 3 + + + MASK + Mask STALL Response Received Interrupt + 0x0 + + + NOMASK + No STALL Response Received Interrupt Mask + 0x1 + + + + + NAKMSK + 4 + 4 + + + MASK + Mask NAK Response Received Interrupt + 0x0 + + + NOMASK + No NAK Response Received Interrupt Mask + 0x1 + + + + + ACKMSK + 5 + 5 + + + MASK + Mask ACK Response Received/Transmitted Interrupt + 0x0 + + + NOMASK + No ACK Response Received/Transmitted Interrupt Mask + 0x1 + + + + + NYETMSK + 6 + 6 + + + MASK + Mask NYET Response Received Interrupt + 0x0 + + + NOMASK + No NYET Response Received Interrupt Mask + 0x1 + + + + + XACTERRMSK + 7 + 7 + + + MASK + Mask Transaction Error + 0x0 + + + NOMASK + No Transaction Error Mask + 0x1 + + + + + BBLERRMSK + 8 + 8 + + + MASK + Mask Babble Error + 0x0 + + + NOMASK + No Babble Error Mask + 0x1 + + + + + FRMOVRUNMSK + 9 + 9 + + + MASK + Mask Overrun Mask + 0x0 + + + NOMASK + No Frame Overrun Mask + 0x1 + + + + + DATATGLERRMSK + 10 + 10 + + + MASK + Mask Data Toggle Error + 0x0 + + + NOMASK + No Data Toggle Error Mask + 0x1 + + + + + + + TSIZ + Description cluster: Host Channel Transfer Size Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Non-Scatter/Gather DMA Mode: + 0 + 18 + + + PKTCNT + Non-Scatter/Gather DMA Mode: + 19 + 28 + + + PID + PID (Pid) + 29 + 30 + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA (non-control)/SETUP (control) + 0x3 + + + + + DOPNG + Do Ping (DoPng) + 31 + 31 + + + NOPING + No ping protocol + 0x0 + + + PING + Ping protocol + 0x1 + + + + + + + DMA + Description cluster: Host Channel DMA Address Register + 0x014 + read-write + 0x00000000 + 0x20 + + + DMAADDR + In Buffer DMA Mode: + 0 + 31 + + + + + + DCFG + Device Configuration Register + 0x800 + read-write + 0x08020000 + 0x20 + + + DEVSPD + Device Speed (DevSpd) + 0 + 1 + + + USBHS20 + High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x0 + + + USBFS20 + Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x1 + + + USBLS116 + Low speed USB 1.1 transceiver clock is 6 MHz + 0x2 + + + USBFS1148 + Full speed USB 1.1 transceiver clock is 48 MHz + 0x3 + + + + + NZSTSOUTHSHK + Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + 2 + 2 + + + SENDOUT + Send the received OUT packet to the application (zero-length or non-zero length) and send a handshake based on NAK and STALL bits for the endpoint in the Devce Endpoint Control Register + 0x0 + + + SENDSTALL + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application + 0x1 + + + + + ENA32KHZSUSP + Enable 32 KHz Suspend mode (Ena32KHzSusp) + 3 + 3 + + + DISABLED + USB 1.1 Full-Speed Serial Transceiver not selected + 0x0 + + + ENABLED + USB 1.1 Full-Speed Serial Transceiver Interface selected + 0x1 + + + + + DEVADDR + Device Address (DevAddr) + 4 + 10 + + + PERFRINT + Periodic Frame Interval (PerFrInt) + 11 + 12 + + + EOPF80 + 80 percent of the (micro)Frame interval + 0x0 + + + EOPF85 + 85 percent of the (micro)Frame interval + 0x1 + + + EOPF90 + 90 percent of the (micro)Frame interval + 0x2 + + + EOPF95 + 95 percent of the (micro)Frame interval + 0x3 + + + + + XCVRDLY + XCVRDLY + 14 + 14 + + + DISABLE + No delay between xcvr_sel and txvalid during Device chirp + 0x0 + + + ENABLE + Enable delay between xcvr_sel and txvalid during Device chirp + 0x1 + + + + + ERRATICINTMSK + Erratic Error Interrupt Mask + 15 + 15 + + + NOMASK + Early suspend interrupt is generated on erratic error + 0x0 + + + MASK + Mask early suspend interrupt on erratic error + 0x1 + + + + + IPGISOCSUPT + Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) + 17 + 17 + + + DISABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is disabled + 0x0 + + + ENABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is enabled + 0x1 + + + + + PERSCHINTVL + Periodic Scheduling Interval (PerSchIntvl) + 24 + 25 + + + MF25 + 25 percent of (micro)Frame + 0x0 + + + MF50 + 50 percent of (micro)Frame + 0x1 + + + MF75 + 75 percent of (micro)Frame + 0x2 + + + + + RESVALID + Resume Validation Period (ResValid) + 26 + 31 + + + + + DCTL + Device Control Register + 0x804 + read-write + 0x00000002 + 0x20 + + + RMTWKUPSIG + Remote Wakeup Signaling (RmtWkUpSig) + 0 + 0 + + + DISABLEDRMWKUP + Core does not send Remote Wakeup Signaling + 0x0 + + + ENABLERMWKUP + Core sends Remote Wakeup Signaling + 0x1 + + + + + SFTDISCON + Soft Disconnect (SftDiscon) + 1 + 1 + + + NODISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + 0x0 + + + DISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host + 0x1 + + + + + GNPINNAKSTS + Global Non-periodic IN NAK Status (GNPINNakSts) + 2 + 2 + read-only + + + INACTIVE + A handshake is sent out based on the data availability in the transmit FIFO + 0x0 + + + ACTIVE + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + 0x1 + + + + + GOUTNAKSTS + Global OUT NAK Status (GOUTNakSts) + 3 + 3 + read-only + + + INACTIVE + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + 0x0 + + + ACTIVE + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + 0x1 + + + + + TSTCTL + Test Control (TstCtl) + 4 + 6 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFE + Test_force_Enable + 0x5 + + + + + SGNPINNAK + Set Global Non-periodic IN NAK (SGNPInNak) + 7 + 7 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Set Global Non-periodic IN NAK + 0x1 + + + + + CGNPINNAK + Clear Global Non-periodic IN NAK (CGNPInNak) + 8 + 8 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Clear Global Non-periodic IN NAK + 0x1 + + + + + SGOUTNAK + Set Global OUT NAK (SGOUTNak) + 9 + 9 + write-only + + + DISABLED + Disable Global OUT NAK + 0x0 + + + ENABLED + Set Global OUT NAK + 0x1 + + + + + CGOUTNAK + Clear Global OUT NAK (CGOUTNak) + 10 + 10 + write-only + + + DISABLED + Disable Clear Global OUT NAK + 0x0 + + + ENABLED + Clear Global OUT NAK + 0x1 + + + + + PWRONPRGDONE + Power-On Programming Done (PWROnPrgDone) + 11 + 11 + + + NOTDONE + Power-On Programming not done + 0x0 + + + DONE + Power-On Programming Done + 0x1 + + + + + IGNRFRMNUM + Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + 15 + 15 + + + DISABLED + Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in which they are intended to be transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is disabled. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediately as the packets are ready.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is enabled. + 0x1 + + + + + NAKONBBLE + NAK on Babble Error (NakOnBble) + 16 + 16 + + + DISABLED + Disable NAK on Babble Error + 0x0 + + + ENABLED + NAK on Babble Error + 0x1 + + + + + DEEPSLEEPBESLREJECT + DeepSleepBESLReject + 18 + 18 + + + DISABLED + Deep Sleep BESL Reject feature is disabled + 0x0 + + + ENABLED + Deep Sleep BESL Reject feature is enabled + 0x1 + + + + + SERVINT + Service Interval based scheduling for Isochronous IN Endpoints + 19 + 19 + + + DISABLED + The controller behavior depends on DCTL.IgnrFrmNum field. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the service interval. + 0x1 + + + + + UTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface. + 30 + 30 + + + DISABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW (1'b0)on soft disconnect. + 0x0 + + + ENABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft disconnect. + 0x1 + + + + + UTMITERMSELCORRDIS + Disable the correction of TermSel on UTMI Interface. + 31 + 31 + + + DISABLED + Valid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x0 + + + ENABLED + Invalid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x1 + + + + + + + DSTS + Device Status Register + 0x808 + read-write + 0x00000002 + 0x20 + + + SUSPSTS + Suspend Status (SuspSts) + 0 + 0 + read-only + + + INACTIVE + No suspend state + 0x0 + + + ACTIVE + Suspend state + 0x1 + + + + + ENUMSPD + Enumerated Speed (EnumSpd) + 1 + 2 + read-only + + + HS3060 + High speed (PHY clock is running at 30 or 60 MHz) + 0x0 + + + FS3060 + Full speed (PHY clock is running at 30 or 60 MHz) + 0x1 + + + LS6 + Low speed (PHY clock is running at 6 MHz) + 0x2 + + + FS48 + Full speed (PHY clock is running at 48 MHz) + 0x3 + + + + + ERRTICERR + Erratic Error (ErrticErr) + 3 + 3 + read-only + + + INACTIVE + No Erratic Error + 0x0 + + + ACTIVE + Erratic Error + 0x1 + + + + + SOFFN + Frame or Microframe Number of the Received SOF (SOFFN) + 8 + 21 + read-only + + + DEVLNSTS + Device Line Status (DevLnSts) + 22 + 23 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error Mask (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + TIMEOUTMSK + Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + 3 + 3 + + + MASK + Mask Timeout Condition Interrupt + 0x0 + + + NOMASK + No Timeout Condition Interrupt Mask + 0x1 + + + + + INTKNTXFEMPMSK + IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + 4 + 4 + + + MASK + Mask IN Token Received When TxFIFO Empty Interrupt + 0x0 + + + NOMASK + No IN Token Received When TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMISMSK + IN Token received with EP Mismatch Mask (INTknEPMisMsk) + 5 + 5 + + + MASK + Mask IN Token received with EP Mismatch Interrupt + 0x0 + + + NOMASK + No Mask IN Token received with EP Mismatch Interrupt + 0x1 + + + + + INEPNAKEFFMSK + IN Endpoint NAK Effective Mask (INEPNakEffMsk) + 6 + 6 + + + MASK + Mask IN Endpoint NAK Effective Interrupt + 0x0 + + + NOMASK + No IN Endpoint NAK Effective Interrupt Mask + 0x1 + + + + + TXFIFOUNDRNMSK + Fifo Underrun Mask (TxfifoUndrnMsk) + 8 + 8 + + + MASK + Mask Fifo Underrun Interrupt + 0x0 + + + NOMASK + No Fifo Underrun Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No Mask NAK Interrupt + 0x1 + + + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + SETUPMSK + SETUP Phase Done Mask (SetUPMsk) + 3 + 3 + + + MASK + Mask SETUP Phase Done Interrupt + 0x0 + + + NOMASK + No SETUP Phase Done Interrupt Mask + 0x1 + + + + + OUTTKNEPDISMSK + OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + 4 + 4 + + + MASK + Mask OUT Token Received when Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No OUT Token Received when Endpoint Disabled Interrupt Mask + 0x1 + + + + + STSPHSERCVDMSK + Status Phase Received Mask (StsPhseRcvdMsk) + 5 + 5 + + + MASK + Status Phase Received Mask + 0x0 + + + NOMASK + No Status Phase Received Mask + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + 6 + 6 + + + MASK + Mask Back-to-Back SETUP Packets Received Interrupt + 0x0 + + + NOMASK + No Back-to-Back SETUP Packets Received Interrupt Mask + 0x1 + + + + + OUTPKTERRMSK + OUT Packet Error Mask (OutPktErrMsk) + 8 + 8 + + + MASK + Mask OUT Packet Error Interrupt + 0x0 + + + NOMASK + No OUT Packet Error Interrupt Mask + 0x1 + + + + + BBLEERRMSK + Babble Error interrupt Mask (BbleErrMsk) + 12 + 12 + + + MASK + Mask Babble Error Interrupt + 0x0 + + + NOMASK + No Babble Error Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No NAK Interrupt Mask + 0x1 + + + + + NYETMSK + NYET interrupt Mask (NYETMsk) + 14 + 14 + + + MASK + Mask NYET Interrupt + 0x0 + + + NOMASK + No NYET Interrupt Mask + 0x1 + + + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + read-write + 0x00000000 + 0x20 + + + INEPINT0 + IN Endpoint 0 Interrupt Bit + 0 + 0 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for IN EP0 + 0x1 + + + + + INEPINT1 + IN Endpoint 1 Interrupt Bit + 1 + 1 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT2 + IN Endpoint 2 Interrupt Bit + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT3 + IN Endpoint 3 Interrupt Bit + 3 + 3 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT4 + IN Endpoint 4 Interrupt Bit + 4 + 4 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT5 + IN Endpoint 5 Interrupt Bit + 5 + 5 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT6 + IN Endpoint 6 Interrupt Bit + 6 + 6 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT7 + IN Endpoint 7 Interrupt Bit + 7 + 7 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT8 + IN Endpoint 8 Interrupt Bit + 8 + 8 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT9 + IN Endpoint 9 Interrupt Bit + 9 + 9 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT10 + IN Endpoint 10 Interrupt Bit + 10 + 10 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT11 + IN Endpoint 11 Interrupt Bit + 11 + 11 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + OUTEPINT0 + OUT Endpoint 0 Interrupt Bit + 16 + 16 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for OUT EP0 + 0x1 + + + + + OUTEPINT1 + OUT Endpoint 1 Interrupt Bit + 17 + 17 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT2 + OUT Endpoint 2 Interrupt Bit + 18 + 18 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT3 + OUT Endpoint 3 Interrupt Bit + 19 + 19 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT4 + OUT Endpoint 4 Interrupt Bit + 20 + 20 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT5 + OUT Endpoint 5 Interrupt Bit + 21 + 21 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT12 + OUT Endpoint 12 Interrupt Bit + 28 + 28 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT13 + OUT Endpoint 13 Interrupt Bit + 29 + 29 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT14 + OUT Endpoint 14 Interrupt Bit + 30 + 30 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT15 + OUT Endpoint 15 Interrupt Bit + 31 + 31 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + read-write + 0x00000000 + 0x20 + + + INEPMSK0 + IN Endpoint 0 Interrupt mask Bit + 0 + 0 + + + MASK + Mask IN Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK1 + IN Endpoint 1 Interrupt mask Bit + 1 + 1 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK2 + IN Endpoint 2 Interrupt mask Bit + 2 + 2 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK3 + IN Endpoint 3 Interrupt mask Bit + 3 + 3 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK4 + IN Endpoint 4 Interrupt mask Bit + 4 + 4 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK5 + IN Endpoint 5 Interrupt mask Bit + 5 + 5 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK6 + IN Endpoint 6 Interrupt mask Bit + 6 + 6 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK7 + IN Endpoint 7 Interrupt mask Bit + 7 + 7 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK8 + IN Endpoint 8 Interrupt mask Bit + 8 + 8 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK9 + IN Endpoint 9 Interrupt mask Bit + 9 + 9 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK10 + IN Endpoint 10 Interrupt mask Bit + 10 + 10 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK11 + IN Endpoint 11 Interrupt mask Bit + 11 + 11 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK0 + OUT Endpoint 0 Interrupt mask Bit + 16 + 16 + + + MASK + Mask OUT Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK1 + OUT Endpoint 1 Interrupt mask Bit + 17 + 17 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK2 + OUT Endpoint 2 Interrupt mask Bit + 18 + 18 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK3 + OUT Endpoint 3 Interrupt mask Bit + 19 + 19 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK4 + OUT Endpoint 4 Interrupt mask Bit + 20 + 20 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK5 + OUT Endpoint 5 Interrupt mask Bit + 21 + 21 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK12 + OUT Endpoint 12 Interrupt mask Bit + 28 + 28 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK13 + OUT Endpoint 13 Interrupt mask Bit + 29 + 29 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK14 + OUT Endpoint 14 Interrupt mask Bit + 30 + 30 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK15 + OUT Endpoint 15 Interrupt mask Bit + 31 + 31 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + read-write + 0x000017D7 + 0x20 + + + DVBUSDIS + Device VBUS Discharge Time (DVBUSDis) + 0 + 15 + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + read-write + 0x000005B8 + 0x20 + + + DVBUSPULSE + Device VBUS Pulsing Time (DVBUSPulse) + 0 + 11 + + + + + DTHRCTL + Device Threshold Control Register + 0x830 + read-write + 0x08100020 + 0x20 + + + NONISOTHREN + Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + 0 + 0 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enable thresholding for non-isochronous IN endpoints + 0x1 + + + + + ISOTHREN + 1 + 1 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enables thresholding for isochronous IN endpoints + 0x1 + + + + + TXTHRLEN + Transmit Threshold Length (TxThrLen) + 2 + 10 + + + AHBTHRRATIO + AHB Threshold Ratio (AHBThrRatio) + 11 + 12 + + + THRESZERO + AHB threshold = MAC threshold + 0x0 + + + THRESONE + AHB threshold = MAC threshold /2 + 0x1 + + + THRESTWO + AHB threshold = MAC threshold /4 + 0x2 + + + THRESTHREE + AHB threshold = MAC threshold /8 + 0x3 + + + + + RXTHREN + Receive Threshold Enable (RxThrEn) + 16 + 16 + + + DISABLED + Disable thresholding + 0x0 + + + ENABLED + Enable thresholding in the receive direction + 0x1 + + + + + RXTHRLEN + Receive Threshold Length (RxThrLen) + 17 + 25 + + + ARBPRKEN + Arbiter Parking Enable (ArbPrkEn) + 27 + 27 + + + DISABLED + Disable DMA arbiter parking + 0x0 + + + ENABLED + Enable DMA arbiter parking for IN endpoints + 0x1 + + + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + read-write + 0x00000000 + 0x20 + + + INEPTXFEMPMSK + IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + 0 + 15 + + + EP0_MASK + Mask IN EP0 Tx FIFO Empty Interrupt + 0x0001 + + + EP1_MASK + Mask IN EP1 Tx FIFO Empty Interrupt + 0x0002 + + + EP2_MASK + Mask IN EP2 Tx FIFO Empty Interrupt + 0x0004 + + + EP3_MASK + Mask IN EP3 Tx FIFO Empty Interrupt + 0x0008 + + + EP4_MASK + Mask IN EP4 Tx FIFO Empty Interrupt + 0x0010 + + + EP5_MASK + Mask IN EP5 Tx FIFO Empty Interrupt + 0x0020 + + + EP6_MASK + Mask IN EP6 Tx FIFO Empty Interrupt + 0x0040 + + + EP7_MASK + Mask IN EP7 Tx FIFO Empty Interrupt + 0x0080 + + + EP8_MASK + Mask IN EP8 Tx FIFO Empty Interrupt + 0x0100 + + + EP9_MASK + Mask IN EP9 Tx FIFO Empty Interrupt + 0x0200 + + + EP10_MASK + Mask IN EP10 Tx FIFO Empty Interrupt + 0x0400 + + + EP11_MASK + Mask IN EP11 Tx FIFO Empty Interrupt + 0x0800 + + + EP12_MASK + Mask IN EP12 Tx FIFO Empty Interrupt + 0x1000 + + + EP13_MASK + Mask IN EP13 Tx FIFO Empty Interrupt + 0x2000 + + + EP14_MASK + Mask IN EP14 Tx FIFO Empty Interrupt + 0x4000 + + + EP15_MASK + Mask IN EP15 Tx FIFO Empty Interrupt + 0x8000 + + + + + + + DIEPCTL0 + Device Control IN Endpoint 0 Control Register + 0x900 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + + + BYTES64 + 64 bytes + 0x0 + + + BYTES32 + 32 bytes + 0x1 + + + BYTES16 + 16 bytes + 0x2 + + + BYTES8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE0 + Control endpoint is always active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Disabled Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT0 + Device IN Endpoint 0 Interrupt Register + 0x908 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Completed Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received when TxFIFO Empty interrupt + 0x0 + + + ACTIVE + IN Token Received when TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No IN Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Fifo Underrun interrupt + 0x0 + + + ACTIVE + Fifo Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ0 + Device IN Endpoint 0 Transfer Size Register + 0x910 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 20 + + + + + DIEPDMA0 + Device IN Endpoint 0 DMA Address Register + 0x914 + read-write + 0x00000000 + 0x20 + + + DMAADDR + DMAAddr + 0 + 31 + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register 0 + 0x918 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL1 + Device Control IN Endpoint Control Register + 0x920 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT1 + Device IN Endpoint Interrupt Register + 0x928 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ1 + Device IN Endpoint Transfer Size Register + 0x930 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA1 + Device IN Endpoint DMA Address Register + 0x934 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS1 + Device IN Endpoint Transmit FIFO Status Register + 0x938 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL2 + Device Control IN Endpoint Control Register + 0x940 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT2 + Device IN Endpoint Interrupt Register + 0x948 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ2 + Device IN Endpoint Transfer Size Register + 0x950 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA2 + Device IN Endpoint DMA Address Register + 0x954 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS2 + Device IN Endpoint Transmit FIFO Status Register + 0x958 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL3 + Device Control IN Endpoint Control Register + 0x960 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT3 + Device IN Endpoint Interrupt Register + 0x968 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ3 + Device IN Endpoint Transfer Size Register + 0x970 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA3 + Device IN Endpoint DMA Address Register + 0x974 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS3 + Device IN Endpoint Transmit FIFO Status Register + 0x978 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL4 + Device Control IN Endpoint Control Register + 0x980 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT4 + Device IN Endpoint Interrupt Register + 0x988 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ4 + Device IN Endpoint Transfer Size Register + 0x990 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA4 + Device IN Endpoint DMA Address Register + 0x994 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS4 + Device IN Endpoint Transmit FIFO Status Register + 0x998 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL5 + Device Control IN Endpoint Control Register + 0x9A0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT5 + Device IN Endpoint Interrupt Register + 0x9A8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ5 + Device IN Endpoint Transfer Size Register + 0x9B0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA5 + Device IN Endpoint DMA Address Register + 0x9B4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS5 + Device IN Endpoint Transmit FIFO Status Register + 0x9B8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL6 + Device Control IN Endpoint Control Register + 0x9C0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT6 + Device IN Endpoint Interrupt Register + 0x9C8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ6 + Device IN Endpoint Transfer Size Register + 0x9D0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA6 + Device IN Endpoint DMA Address Register + 0x9D4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS6 + Device IN Endpoint Transmit FIFO Status Register + 0x9D8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL7 + Device Control IN Endpoint Control Register + 0x9E0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT7 + Device IN Endpoint Interrupt Register + 0x9E8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ7 + Device IN Endpoint Transfer Size Register + 0x9F0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA7 + Device IN Endpoint DMA Address Register + 0x9F4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS7 + Device IN Endpoint Transmit FIFO Status Register + 0x9F8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL8 + Device Control IN Endpoint Control Register + 0xA00 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT8 + Device IN Endpoint Interrupt Register + 0xA08 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ8 + Device IN Endpoint Transfer Size Register + 0xA10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA8 + Device IN Endpoint DMA Address Register + 0xA14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS8 + Device IN Endpoint Transmit FIFO Status Register + 0xA18 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL9 + Device Control IN Endpoint Control Register + 0xA20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT9 + Device IN Endpoint Interrupt Register + 0xA28 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ9 + Device IN Endpoint Transfer Size Register + 0xA30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA9 + Device IN Endpoint DMA Address Register + 0xA34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS9 + Device IN Endpoint Transmit FIFO Status Register + 0xA38 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL10 + Device Control IN Endpoint Control Register + 0xA40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT10 + Device IN Endpoint Interrupt Register + 0xA48 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ10 + Device IN Endpoint Transfer Size Register + 0xA50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA10 + Device IN Endpoint DMA Address Register + 0xA54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS10 + Device IN Endpoint Transmit FIFO Status Register + 0xA58 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL11 + Device Control IN Endpoint Control Register + 0xA60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT11 + Device IN Endpoint Interrupt Register + 0xA68 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ11 + Device IN Endpoint Transfer Size Register + 0xA70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA11 + Device IN Endpoint DMA Address Register + 0xA74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS11 + Device IN Endpoint Transmit FIFO Status Register + 0xA78 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint 0 Control Register + 0xB00 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + read-only + + + BYTE64 + 64 bytes + 0x0 + + + BYTE32 + 32 bytes + 0x1 + + + BYTE16 + 16 bytes + 0x2 + + + BYTE8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE + USB Active Endpoint 0 + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + read-only + + + INACTIVE + No Endpoint disable + 0x0 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT0 + Device OUT Endpoint 0 Interrupt Register + 0xB08 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ0 + Device OUT Endpoint 0 Transfer Size Register + 0xB10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 19 + + + SUPCNT + SETUP Packet Count (SUPCnt) + 29 + 30 + + + ONEPACKET + 1 packet + 0x1 + + + TWOPACKET + 2 packets + 0x2 + + + THREEPACKET + 3 packets + 0x3 + + + + + + + DOEPDMA0 + Device OUT Endpoint 0 DMA Address Register + 0xB14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL1 + Device Control OUT Endpoint Control Register + 0xB20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT1 + Device OUT Endpoint Interrupt Register + 0xB28 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ1 + Device OUT Endpoint Transfer Size Register + 0xB30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA1 + Device OUT Endpoint DMA Address Register + 0xB34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL2 + Device Control OUT Endpoint Control Register + 0xB40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT2 + Device OUT Endpoint Interrupt Register + 0xB48 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ2 + Device OUT Endpoint Transfer Size Register + 0xB50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA2 + Device OUT Endpoint DMA Address Register + 0xB54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL3 + Device Control OUT Endpoint Control Register + 0xB60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT3 + Device OUT Endpoint Interrupt Register + 0xB68 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ3 + Device OUT Endpoint Transfer Size Register + 0xB70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA3 + Device OUT Endpoint DMA Address Register + 0xB74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL4 + Device Control OUT Endpoint Control Register + 0xB80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT4 + Device OUT Endpoint Interrupt Register + 0xB88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ4 + Device OUT Endpoint Transfer Size Register + 0xB90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA4 + Device OUT Endpoint DMA Address Register + 0xB94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL5 + Device Control OUT Endpoint Control Register + 0xBA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT5 + Device OUT Endpoint Interrupt Register + 0xBA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ5 + Device OUT Endpoint Transfer Size Register + 0xBB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA5 + Device OUT Endpoint DMA Address Register + 0xBB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL12 + Device Control OUT Endpoint Control Register + 0xC80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT12 + Device OUT Endpoint Interrupt Register + 0xC88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ12 + Device OUT Endpoint Transfer Size Register + 0xC90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA12 + Device OUT Endpoint DMA Address Register + 0xC94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL13 + Device Control OUT Endpoint Control Register + 0xCA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT13 + Device OUT Endpoint Interrupt Register + 0xCA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ13 + Device OUT Endpoint Transfer Size Register + 0xCB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA13 + Device OUT Endpoint DMA Address Register + 0xCB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL14 + Device Control OUT Endpoint Control Register + 0xCC0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT14 + Device OUT Endpoint Interrupt Register + 0xCC8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ14 + Device OUT Endpoint Transfer Size Register + 0xCD0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA14 + Device OUT Endpoint DMA Address Register + 0xCD4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL15 + Device Control OUT Endpoint Control Register + 0xCE0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT15 + Device OUT Endpoint Interrupt Register + 0xCE8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ15 + Device OUT Endpoint Transfer Size Register + 0xCF0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA15 + Device OUT Endpoint DMA Address Register + 0xCF4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + read-write + 0x880A0000 + 0x20 + + + STOPPCLK + Stop Pclk (StopPclk) + 0 + 0 + + + DISABLED + Disable Stop Pclk + 0x0 + + + ENABLED + Enable Stop Pclk + 0x1 + + + + + GATEHCLK + Gate Hclk (GateHclk) + 1 + 1 + + + DISABLED + Clears this bit when the USB is resumed or a new session starts + 0x0 + + + ENABLED + Sets this bit to gate hclk to modules when the USB is suspended or the session is not valid + 0x1 + + + + + RSTPDWNMODULE + Reset Power-Down Modules (RstPdwnModule) + 3 + 3 + + + ON + Power is turned on + 0x0 + + + OFF + Power is turned off + 0x1 + + + + + ENBLL1GATING + Enable Sleep Clock Gating + 5 + 5 + + + DISABLED + The PHY clock is not gated in Sleep state + 0x0 + + + ENABLED + The Core internal clock gating is enabled in Sleep state + 0x1 + + + + + PHYSLEEP + PHY In Sleep + 6 + 6 + read-only + + + INACTIVE + Phy not in Sleep state + 0x0 + + + ACTIVE + Phy in Sleep state + 0x1 + + + + + L1SUSPENDED + L1 Deep Sleep + 7 + 7 + read-only + + + INACTIVE + Non Deep Sleep + 0x0 + + + ACTIVE + Deep Sleep + 0x1 + + + + + RESTOREMODE + Restore Mode (RestoreMode) + 9 + 9 + + + DISABLED + In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this bit indicates Device-initiated Remote Wakeup + 0x0 + + + ENABLED + In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this bit indicates Host-initiated Resume and Reset + 0x1 + + + + + ESSREGRESTORED + Essential Register Values Restored (EssRegRestored) + 13 + 13 + write-only + + + NOT_RESTORED + Register values of essential registers are not restored + 0x0 + + + RESTORED + Register values of essential registers have been restored + 0x1 + + + + + RESTOREVALUE + Restore Value (RestoreValue) + 14 + 31 + + + + + GSTARFXDIS + Global STAR Fix Disable Register + 0xF00 + read-write + 0x00002200 + 0x20 + + + HOSTIGNORESRMTWKUPDIS + Disable the STAR fix added for Device controller to go back to low power mode when Host ignores Remote wakeup + 0 + 0 + + + ENABLE_FIX + Device controller goes back into SUSPENDED state when host ignores Remote Wakeup + 0x0 + + + DISABLE_FIX + Device controller waits indefinitely without entering SUSPENDED state when host ignores the Remote Wakeup + 0x1 + + + + + RESUMEFRMCHKBUSDIS + Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after the 50us pull-up delay ends + 1 + 1 + + + ENABLE_FIX + Device controller detects line K and resumes + 0x0 + + + DISABLE_FIX + Device controller does not detect line K and resume + 0x1 + + + + + IGNORECTLOUTDATA0DIS + Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data Phase and Control Status OUT Phase + 2 + 2 + + + ENABLE_FIX + Transaction Error reported when host sends DATA0 PID + 0x0 + + + DISABLE_FIX + Transaction Error not reported when host sends DATA0 PID + 0x1 + + + + + SSPLITSTALLNYETERRDIS + Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET + 3 + 3 + + + ENABLE_FIX + Transaction Error reported when device sends STALL/NYET for SSPLIT + 0x0 + + + DISABLE_FIX + Transaction Error not reported when device sends STALL/NYET for SSPLIT + 0x1 + + + + + ACCEPTISOCSPLITDATA1DIS + Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC Split transfers + 4 + 4 + + + ENABLE_FIX + Transaction Error not reported when device sends DATA1 PID for ISOC Split + 0x0 + + + DISABLE_FIX + Transaction Error reported when device sends DATA1 PID for ISOC Split + 0x1 + + + + + HANDLEFAULTYCABLEDIS + Disable the STAR fix added for Host controller to handle Faulty cable scenarios + 5 + 5 + + + ENABLE_FIX + Fix for handling faulty cable enabled + 0x0 + + + DISABLE_FIX + Fix for handling faulty cable disabled + 0x1 + + + + + LSIPGINCRDIS + Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit times + 6 + 6 + + + ENABLE_FIX + Host LS mode IPG is 3 LS bit times + 0x0 + + + DISABLE_FIX + Host LS mode IPG is 2 LS bit times + 0x1 + + + + + FSDISCIDLEDIS + Disable the STAR fix added for Device controller to transition to IDLE state during FS device disconnect + 7 + 7 + + + ENABLE_FIX + Device controller transitions to IDLE state during FS device disconnect + 0x0 + + + DISABLE_FIX + Device controller does not transition to IDLE state during FS device disconnect + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEDIS + Disable the STAR fix added for Device controller to not start Remote Wakeup signalling when USB resume has already started + 8 + 8 + + + ENABLE_FIX + Device controller does not start remote wakeup signalling when host resume has already started + 0x0 + + + DISABLE_FIX + Device controller is allowed to start remote wakeup signalling when host resume has already started + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEHIBDIS + Disable the STAR fix added for Device controller to not hang when Remote Wakeup signalling clashes with Host resume + 9 + 9 + + + ENABLE_FIX + Device controller does not hang when remote wakeup signalling clashes with host resume during Hibernation exit + 0x0 + + + DISABLE_FIX + Device controller hangs when remote wakeup signalling clashes with host resume during Hibernation exit + 0x1 + + + + + LSIPGCHKAFTERNAKSTALLFORINDIS + Disable the STAR fix added for Host controller to wait for IPG duration to send next token after receiving NAK/STALL for previous IN token with FS/LS device + 10 + 10 + + + ENABLE_FIX + Host controller checks IPG after NAK/STALL for IN token + 0x0 + + + DISABLE_FIX + Host controller does not check IPG after NAK/STALL for IN token + 0x1 + + + + + PHYIOPXCVRSELTXVLDCORRDIS + Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode + 11 + 11 + + + ENABLE_FIX + Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect switching + 0x0 + + + DISABLE_FIX + Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect switching + 0x1 + + + + + ULPIXCVRSELSWITCHCORRDIS + Disable the STAR fix added for Host controller to increase the preamble transceiver select switch delay to accommodate time taken for ULPI function control write + 12 + 12 + + + ENABLE_FIX + Host controller waits for previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x0 + + + DISABLE_FIX + Host controller does not wait for the previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x1 + + + + + XACTERRDATA0CTRLSTSINDIS + Disable the STAR fix added for Host controller to report transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 13 + 13 + + + ENABLE_FIX + Host controller reports transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x0 + + + DISABLE_FIX + Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x1 + + + + + HOSTUTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. + 16 + 16 + + + ENABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1'b0) + 0x0 + + + DISABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxValid to go LOW (1'b0) during SOF transmission + 0x1 + + + + + OPMODEXCVRSELCHIRPENCORRDIS + Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when reset is detected in suspend state. + 17 + 17 + + + ENABLE_FIX + Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x0 + + + DISABLE_FIX + Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x1 + + + + + TXVALIDDEASSERTIONCORRDIS + Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft disconnect is done. + 18 + 18 + + + ENABLE_FIX + Txvalid is deasserted during soft disconnect after receiving Txready from the PHY + 0x0 + + + DISABLE_FIX + Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY + 0x1 + + + + + HOSTNOXFERAFTERPRTDISFIXDIS + Disable the STAR fix added for correcting Host behavior when port is disabled. + 19 + 19 + + + ENABLE_FIX + Txvalid is not asserted when port is disabled + 0x0 + + + DISABLE_FIX + Txvalid can be asserted when port is disabled + 0x1 + + + + + + + 16 + 0x1000 + DWCOTGDFIFO[%s] + Unspecified + USBHSCORE_DWCOTGDFIFO + read-write + 0x1000 + + 0x400 + 0x4 + DATA[%s] + Description collection: Data FIFO Access Register Map 0 + 0x0000 + read-write + 0x00000000 + 0x20 + + + + DWCOTGDFIFODIRECTACCESS + Unspecified + USBHSCORE_DWCOTGDFIFODIRECTACCESS + read-write + 0x20000 + + 0x8000 + 0x4 + DATA[%s] + Description collection: Data FIFO Direct Access Register Map + 0x00000 + read-write + 0x00000000 + 0x20 + + + + + + GLOBAL_I3CCORE120 + I3CCORE 0 + 0x2FBE0000 + I3CCORE + + + + 0 + 0x1000 + registers + + I3CCORE + 0x20 + + + CORE + Unspecified + I3CCORE_CORE + read-write + 0x000 + + DEVICECTRL + DWC_mipi_i3c control Register + 0x000 + read-write + 0x00000000 + 0x20 + + + IBAINCLUDE + I3C Broadcast Address include + 0 + 0 + + + NOT_INCLUDED + Unspecified + 0x0 + + + INCLUDED + Unspecified + 0x1 + + + + + I2CSLAVEPRESENT + I2C Slave Present + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + HOTJOINCTRL + Hot-Join ACK/NACK Control + 8 + 8 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + IDLECNTMULTPLIER + Idle Count Multiplier + 24 + 25 + + + MultiplyBy1 + Unspecified + 0x0 + + + MultiplyBy2 + Unspecified + 0x1 + + + MultiplyBy4 + Unspecified + 0x2 + + + MultiplyBy8 + Unspecified + 0x3 + + + + + ADAPTIVEI2CI3C + This field is used in Slave mode of operation. + 27 + 27 + + + DMAENABLE + DMA Handshake Interface Enable + 28 + 28 + + + DISABLE + The DMA handshake control has no significance. + 0x0 + + + ENABLE + Enables the DMA handshake control to interact with external DMA. + 0x1 + + + + + ABORT + DWC_mipi_i3c Abort + 29 + 29 + + + RESUME + DWC_mipi_i3c Resume + 30 + 30 + + + ENABLE + Controls whether or not DWC_mipi_i3c is enabled. + 31 + 31 + + + DISABLE + Disables the DWC_mipi_i3c controller + 0x0 + + + ENABLE + Enables the DWC_mipi_i3c controller. + 0x1 + + + + + + + DEVICEADDR + In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit. + 0x004 + read-write + 0x80000000 + 0x20 + + + STATICADDR + Device Static Address. + 0 + 6 + + + STATICADDRVALID + Static Address Valid. + 15 + 15 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + DYNAMICADDR + Device Dynamic Address. + 16 + 22 + + + DYNAMICADDRVALID + Dynamic Address Valid + 31 + 31 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + + + HWCAPABILITY + Hardware Capability register + 0x008 + read-write + 0x000E187B + 0x20 + + + DEVICEROLECONFIG + Reflects the IC_DEVICE_ROLE Configurable Parameter. + 0 + 2 + read-only + + + MASTER + Master Only + 0x1 + + + PMASTERSLAVE + Programmable Master-Slave + 0x2 + + + SECONDARYMASTER + Secondary Master + 0x3 + + + SLAVE + Slave Only + 0x4 + + + + + HDRDDREN + Reflects the IC_SPEED_HDR_DDR Configurable Parameter. + 3 + 3 + read-only + + + NOTSUPPORTED + HDR-DDR not supported + 0x0 + + + SUPPORTED + HDR-DDR supported + 0x1 + + + + + HDRTSEN + Reflects the IC_SPEED_HDR_TS Configurable Parameter. + 4 + 4 + read-only + + + NOTSUPPORTED + HDR-TS not supported + 0x0 + + + SUPPORTED + HDR-TS supported + 0x1 + + + + + CLOCKPERIOD + Reflects the IC_CLK_PERIOD Configurable Parameter + 5 + 10 + read-only + + + HDRTXCLOCKPERIOD + Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. + 11 + 16 + read-only + + + DMAEN + Reflects the IC_HAS_DMA Configurable Parameter. + 17 + 17 + read-only + + + SLVHJCAP + Reflects the IC_SLV_HJ Configurable Parameter. + 18 + 18 + read-only + + + SLVIBICAP + Reflects the IC_SLV_IBI Configurable Parameter. + 19 + 19 + read-only + + + + + COMMANDQUEUEPORT + Command Queue Port. + 0x00C + read-write + 0x00000000 + 0x20 + + + COMMAND + 32 bit command + 0 + 31 + write-only + + + + + RESPONSEQUEUEPORT + Response Queue Port + 0x010 + read-write + 0x00000000 + 0x20 + + + RESPONSE + 32 bit Response + 0 + 31 + read-only + + + + + RXDATAPORT + Receive Data Port Register + 0x014 + read-write + 0x00000000 + 0x20 + + + RXDATAPORT + Receive Data Port. + 0 + 31 + read-only + + + + + TXDATAPORT + Transmit Data Port Register + 0x014 + read-write + 0x00000000 + RXDATAPORT + 0x20 + + + TXDATAPORT + Transmit Data Port + 0 + 31 + write-only + + + + + IBIQUEUEDATA + In-Band Interrupt Queue Data Register + 0x018 + read-write + 0x00000000 + 0x20 + + + IBIDATA + In-Band Interrupt Data + 0 + 31 + read-only + + + + + IBIQUEUESTATUS + In-Band Interrupt Queue Status Register + 0x018 + read-write + 0x00000000 + IBIQUEUEDATA + 0x20 + + + DATALENGTH + In-Band Interrupt data length. + 0 + 7 + read-only + + + IBIID + IBI Identifier. + 8 + 15 + read-only + + + IBIACK + The acknowledge bit of the IBI Received Status (IBISTS) bitfield. + 31 + 31 + read-only + + + ACK + Responded with ACK + 0x0 + + + NACK + Responded with NACK + 0x1 + + + + + + + QUEUETHLDCTRL + Queue Threshold Control Register + 0x01C + read-write + 0x01000101 + 0x20 + + + CMDEMPTYBUFTHLD + Command Buffer Empty Threshold Value. + 0 + 7 + + + RESPBUFTHLD + Response Buffer Threshold Value. + 8 + 15 + + + IBISTATUSTHLD + In-Band Interrupt Status Threshold Value. + 24 + 31 + + + + + DATABUFFERTHLDCTRL + Data Buffer Threshold Control Register + 0x020 + read-write + 0x01010101 + 0x20 + + + TXEMPTYBUFTHLD + Transmit Buffer Threshold Value + 0 + 2 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD14 + Unspecified + 0x1 + + + THRESHOLD18 + Unspecified + 0x2 + + + THRESHOLD116 + Unspecified + 0x3 + + + THRESHOLD132 + Unspecified + 0x4 + + + THRESHOLD164 + Unspecified + 0x5 + + + + + RXBUFTHLD + Receive Buffer Threshold Value + 8 + 10 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + TXSTARTTHLD + Transfer Start Threshold Value + 16 + 18 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + RXSTARTTHLD + Receive Start Threshold Value + 24 + 26 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + + + IBIQUEUECTRL + This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked). + 0x024 + read-write + 0x00000000 + 0x20 + + + NOTIFYHJREJECTED + Notify Rejected Hot-Join Control. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + NOTIFYMRREJECTED + Notify Rejected Master Request Control. + 1 + 1 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x1 + + + + + NOTIFYSIRREJECTED + Notify Rejected Slave Interrupt Request Control. + 3 + 3 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x1 + + + + + + + IBIMRREQREJECT + IBI Master Request Rejection Control Register. + 0x02C + read-write + 0x00000000 + 0x20 + + + MRREQREJECT + In-band Master Request Reject. + 0 + 31 + + + ACK + ACK Master Request. + 0x00000000 + + + NACK + NACK and send Directed DISEC CCC to disable the interrupting slave. + 0x00000001 + + + + + + + IBISIRREQREJECT + IBI SIR Request Rejection Control + 0x030 + read-write + 0x00000000 + 0x20 + + + SIRREQREJECT + In-band Slave Interrupt Request Reject + 0 + 31 + + + ACK + ACK the SIR Request. + 0x00000000 + + + NACK + NACK and send directed auto disable CCC. + 0x00000001 + + + + + + + RESETCTRL + This Register is used for general software reset and for individual buffer reset. + 0x034 + read-write + 0x00000000 + 0x20 + + + SOFTRST + Core Software Reset. + 0 + 0 + + + CMDQUEUERST + Command Queue Software Reset + 1 + 1 + + + RESPQUEUERST + Response Queue Software Reset + 2 + 2 + + + TXFIFORST + Transmit Buffer Software Reset + 3 + 3 + + + RXFIFORST + Receive Buffer Software Reset. + 4 + 4 + + + IBIQUEUERST + IBI Queue Software Reset. + 5 + 5 + + + BUSRESETTYPE + Bus Reset type + 29 + 30 + + + EXIT + Exit Pattern. + 0x0 + + + SCL_LOW_RESET + SCL_LOW_RESET Pattern. + 0x3 + + + + + BUSRESET + Bus Reset. + 31 + 31 + + + + + SLVEVENTSTATUS + This register indicates the status/values of some events/controls that are relavant to slave mode of operation. + 0x038 + read-write + 0x0000000B + 0x20 + + + SIREN + Slave Interrupt Request Enable. + 0 + 0 + read-only + + + MREN + Master Request Enable. + 1 + 1 + read-only + + + HJEN + Hot-Join Interrupt Enable + 3 + 3 + + + ACTIVITYSTATE + Activity State Status. + 4 + 5 + read-only + + + ENTAS0 + Unspecified + 0x0 + + + ENTAS1 + Unspecified + 0x1 + + + ENTAS2 + Unspecified + 0x2 + + + ENTAS3 + Unspecified + 0x3 + + + + + MRLUPDATED + MRL Updated Status. + 6 + 6 + + + MWLUPDATED + MWL Updated Status. + 7 + 7 + + + + + INTRSTATUS + Interrupt Status Register + 0x03C + read-write + 0x00000000 + 0x20 + + + TXTHLDSTS + Transmit Buffer Threshold Status + 0 + 0 + read-only + + + RXTHLDSTS + Receive Buffer Threshold Status. + 1 + 1 + read-only + + + IBITHLDSTS + IBI Buffer Threshold Status. + 2 + 2 + read-only + + + CMDQUEUEREADYSTS + Command Queue Ready. + 3 + 3 + read-only + + + RESPREADYSTS + Response Queue Ready Status. + 4 + 4 + read-only + + + TRANSFERABORTSTS + Transfer Abort Status. + 5 + 5 + + + CCCUPDATEDSTS + CCC Table Updated Status. + 6 + 6 + + + DYNADDRASSGNSTS + Dynamic Address Assigned Status. + 8 + 8 + + + TRANSFERERRSTS + Transfer Error Status. + 9 + 9 + + + DEFSLVSTS + Define Slave CCC Received Status. + 10 + 10 + + + READREQRECVSTS + Read Request Received. + 11 + 11 + + + IBIUPDATEDSTS + IBI status is updated. + 12 + 12 + + + BUSOWNERUPDATEDSTS + This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa. + 13 + 13 + + + BUSRESETDONESTS + Bus Reset Pattern Generation Done Status. + 15 + 15 + + + + + INTRSTATUSEN + Interrupt Status Enable Register. + 0x040 + read-write + 0x00000000 + 0x20 + + + TXTHLDSTSEN + Transmit Buffer Threshold Status Enable. + 0 + 0 + + + RXTHLDSTSEN + Receive Buffer Threshold Status Enable + 1 + 1 + + + IBITHLDSTSEN + IBI Buffer Threshold Status Enable. + 2 + 2 + + + CMDQUEUEREADYSTSEN + Command Queue Ready Status Enable + 3 + 3 + + + RESPREADYSTSEN + Response Queue Ready Status Enable + 4 + 4 + + + TRANSFERABORTSTSEN + Transfer Abort Status Enable. + 5 + 5 + + + CCCUPDATEDSTSEN + CCC Table Updated Status Enable. + 6 + 6 + + + DYNADDRASSGNSTSEN + Dynamic Address Assigned Status Enable + 8 + 8 + + + TRANSFERERRSTSEN + Transfer Error Status Enable + 9 + 9 + + + DEFSLVSTSEN + Define Slave CCC Received Status Enable + 10 + 10 + + + READREQRECVSTSEN + Read Request Received Status Enable + 11 + 11 + + + IBIUPDATEDSTSEN + IBI Updated Status Enable + 12 + 12 + + + BUSOWNERUPDATEDSTSEN + Bus owner Updated Status Enable + 13 + 13 + + + BUSRESETDONESTSEN + Bus Reset Pattern Generation Done Status Enable. + 15 + 15 + + + + + INTRSIGNALEN + Interrupt Signal Enable Register + 0x044 + read-write + 0x00000000 + 0x20 + + + TXTHLDSIGNALEN + Transmit Buffer Threshold Signal Enable + 0 + 0 + + + RXTHLDSIGNALEN + Receive Buffer Threshold Signal Enable + 1 + 1 + + + IBITHLDSIGNALEN + IBI Buffer Threshold Signal Enable + 2 + 2 + + + CMDQUEUEREADYSIGNALEN + Command Queue Ready Signal Enable + 3 + 3 + + + RESPREADYSIGNALEN + Response Queue Ready Signal Enable + 4 + 4 + + + TRANSFERABORTSIGNALEN + Transfer Abort Signal Enable + 5 + 5 + + + CCCUPDATEDSIGNALEN + CCC Table Updated Signal Enable + 6 + 6 + + + DYNADDRASSGNSIGNALEN + Dynamic Address Assigned Signal Enable + 8 + 8 + + + TRANSFERERRSIGNALEN + Transfer Error Signal Enable + 9 + 9 + + + DEFSLVSIGNALEN + Define Slave CCC Received Signal Enable + 10 + 10 + + + READREQRECVSIGNALEN + Read Request Received Signal Enable + 11 + 11 + + + IBIUPDATEDSIGNALEN + IBI Updated Signal Enable + 12 + 12 + + + BUSOWNERUPDATEDSIGNALEN + Bus owner Updated Signal Enable + 13 + 13 + + + BUSRESETDONESIGNALEN + Bus Reset Pattern Generation Done Signal Enable. + 15 + 15 + + + + + INTRFORCE + Interrupt Force Enable Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TXTHLDFORCEEN + Transmit Buffer Threshold Force Enable + 0 + 0 + write-only + + + RXTHLDFORCEEN + Receive Buffer Threshold Force Enable + 1 + 1 + write-only + + + IBITHLDFORCEEN + IBI Buffer Threshold Force Enable + 2 + 2 + write-only + + + CMDQUEUEREADYFORCEEN + Command Queue Ready Force Enable + 3 + 3 + write-only + + + RESPREADYFORCEEN + Response Queue Ready Force Enable + 4 + 4 + write-only + + + TRANSFERABORTFORCEEN + Transfer Abort Force Enable + 5 + 5 + write-only + + + CCCUPDATEDFORCEEN + CCC Table Updated Force Enable + 6 + 6 + write-only + + + DYNADDRASSGNFORCEEN + Dynamic Address Assigned Force Enable + 8 + 8 + write-only + + + TRANSFERERRFORCEEN + Transfer Error Force Enable + 9 + 9 + write-only + + + DEFSLVFORCEEN + Define Slave CCC Received Force Enable + 10 + 10 + write-only + + + READREQFORCEEN + Read Request Received Force Enable + 11 + 11 + write-only + + + IBIUPDATEDFORCEEN + IBI Updated Force Enable + 12 + 12 + write-only + + + BUSOWNERUPDATEDFORCEEN + Bus owner Updated Force Enable + 13 + 13 + write-only + + + BUSRESETDONEFORCEEN + Bus Reset Pattern Generation Done Force Enable. + 15 + 15 + write-only + + + + + QUEUESTATUSLEVEL + Queue Status Level Register. + 0x04C + read-write + 0x00000010 + 0x20 + + + CMDQUEUEEMPTYLOC + Command Queue Empty Locations. + 0 + 7 + read-only + + + RESPBUFBLR + Response Buffer Level Value. + 8 + 15 + read-only + + + IBIBUFBLR + IBI Buffer Level Value. + 16 + 23 + read-only + + + IBISTSCNT + IBI Buffer Status Count. + 24 + 28 + read-only + + + + + DATABUFFERSTATUSLEVEL + Data Buffer Status Level Register. + 0x050 + read-write + 0x00000040 + 0x20 + + + TXBUFEMPTYLOC + Transmit Buffer Empty Level Value. + 0 + 7 + read-only + + + RXBUFBLR + Receive Buffer Level Value. + 16 + 23 + read-only + + + + + PRESENTSTATEM + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Master). + 0x054 + read-write + 0x10000003 + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + IDLE + Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + BCCCWTRANSFER + Broadcast CCC Write Transfer. + 0x01 + + + DCCCWTRANSFER + Directed CCC Write Transfer. + 0x02 + + + DCCCRTRANSFER + Directed CCC Read Transfer. + 0x03 + + + ENTDAATRANSFER + ENTDAA Address Assignment Transfer. + 0x04 + + + SETDASATRANSFER + SETDASA Address Assignment Transfer. + 0x05 + + + SDRWTRANSFER + Private I3C SDR Write Transfer. + 0x06 + + + SDRRTRANSFER + Private I3C SDR Read Transfer. + 0x07 + + + SDRWTRANSFERI2C + Private I2C SDR Write Transfer. + 0x08 + + + SDRRTRANSFERI2C + Private I2C SDR Read Transfer. + 0x09 + + + TSWTRANSFER + Private HDR Ternary Symbol(TS) Write Transfer. + 0x0A + + + TSRTRANSFER + Private HDR Ternary Symbol(TS) Read Transfer. + 0x0B + + + DDRWTRANSFER + Private HDR Double-Data Rate(DDR) Write Transfer. + 0x0C + + + DDRRTRANSFER + Private HDR Double-Data Rate(DDR) Read Transfer. + 0x0D + + + IBITRANSFER + Servicing In-Band Interrupt Transfer. + 0x0E + + + HALT + Halt state. Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register. + 0x0F + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + IDLE + Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + START + START Generation State. + 0x01 + + + RESTART + RESTART Generation State. + 0x02 + + + STOP + STOP Genration State. + 0x03 + + + STARTH + START Hold Generation for the Slave Initiated START State. + 0x04 + + + BWADDRGEN + Broadcast Write Address Header(7h7E,W) Generation State. + 0x05 + + + BRADDRGEN + Broadcast Read Address Header(7h7E,R) Generation State. + 0x06 + + + DAA + Dynamic Address Assignment State. + 0x07 + + + ADDRGEN + Slave Address Generation State. + 0x08 + + + CCCBYTEGEN + CCC Byte Generation State. + 0x0B + + + HDRCMDGEN + HDR Command Generation State. + 0x0C + + + WTRANSFER + Write Data Transfer State. + 0x0D + + + RTRANSFER + Read Data Transfer State. + 0x0E + + + RIBI + In-Band Interrupt(SIR) Read Data State. + 0x0F + + + IBIAUTODISABLE + In-Band Interrupt Auto-Disable State + 0x10 + + + DDRCRCGEN + HDR-DDR CRC Data Generation/Receive State. + 0x11 + + + CLKEXTEND + Clock Extension State. + 0x12 + + + HALT + Halt State. + 0x13 + + + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + PRESENTSTATES + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Slave). + 0x054 + read-write + 0x10000003 + PRESENTSTATEM + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + SLAVEIDLE + Controller is in Idle state. + 0x00 + + + SLAVEHOTJOIN + Hot-Join transfer state. + 0x01 + + + SLAVEIBITRANSFER + IBI transfer state. + 0x02 + + + SLAVEWTRANSFER + Master write transfer ongoing. + 0x03 + + + SLAVERPREFETCH + Read data prefetch state. + 0x04 + + + SLAVERTRANSFER + Master read transfer ongoing. + 0x05 + + + SLAVEHALT + Slave controller in Halt State waiting for resume from application. + 0x06 + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + CCCDEVICESTATUS + Device Operating Status Register. + 0x058 + read-write + 0x00000000 + 0x20 + + + PENDINGINTR + Pending Interrupt + 0 + 3 + read-only + + + PROTOCOLERR + Protocol Error + 5 + 5 + read-only + + + ACTIVITYMODE + Activity Mode + 6 + 7 + read-only + + + UNDERFLOWERR + Underflow error + 8 + 8 + read-only + + + SLAVEBUSY + Slave Busy + 9 + 9 + read-only + + + OVERFLOWERR + Overflow Error + 10 + 10 + read-only + + + DATANOTREADY + Data not ready + 11 + 11 + read-only + + + BUFFERNOTAVAIL + Buffer not available + 12 + 12 + read-only + + + FRAMEERROR + Frame Error + 13 + 13 + read-only + + + + + DEVICEADDRTABLEPOINTER + Pointer for Device Address Table + 0x05C + read-write + 0x000A02C0 + 0x20 + + + PDEVADDRTABLESTARTADDR + Start Address of Device Address Table. + 0 + 15 + read-only + + + DEVADDRTABLEDEPTH + Depth of Device Address Table + 16 + 31 + read-only + + + + + DEVCHARTABLEPOINTER + Pointer for Device Characteristics Table + 0x060 + read-write + 0x00028200 + 0x20 + + + PDEVCHARTABLESTARTADDR + Start Address of Device Characteristics Table. + 0 + 11 + read-only + + + DEVCHARTABLEDEPTH + Depth of Device Characteristics Table + 12 + 18 + read-only + + + PRESENTDEVCHARTABLEINDX + Current index of Device Characteristics Table. + 19 + 22 + + + + + VENDORSPECIFICREGPOINTER + Pointer for Vendor Specific Registers. + 0x06C + read-write + 0x000000B0 + 0x20 + + + PVENDORREGSTARTADDR + Start Address of Vendor specific registers. + 0 + 15 + read-only + + + + + SLVMIPIIDVALUE + I3C MIPI Manufacturer ID Register. + 0x070 + read-write + 0x00000000 + 0x20 + + + SLVPROVIDSEL + Specifies the Provisional ID Type Selector (PID[32]). + 0 + 0 + + + SLVMIPIMFGID + Specifies the MIPI Manufacturer ID. + 1 + 15 + + + + + SLVPIDVALUE + I3C Normal Provisional ID Register. + 0x074 + read-write + 0x00000000 + 0x20 + + + SLVPIDDCR + Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). + 0 + 11 + + + SLVINSTID + This field is used to program the instance ID of the Slave. + 12 + 15 + + + SLVPARTID + Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) + 16 + 31 + + + + + SLVCHARCTRL + I3C Slave Characteristic Register. + 0x078 + read-write + 0x00070062 + 0x20 + + + MAXDATASPEEDLIMIT + Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). + 0 + 0 + + + IBIREQUESTCAPABLE + IBI Request Capable field in Bus Characteristic Register (BCR[1]). + 1 + 1 + read-only + + + IBIPAYLOAD + IBI Payload field in Bus Characteristic Register (BCR[2]). + 2 + 2 + read-only + + + OFFLINECAPABLE + Offline Capable field in Bus Characteristic Register (BCR[3]). + 3 + 3 + read-only + + + BRIDGEIDENTIFIER + Bridge Identifier field in Bus Characteristic Register (BCR[4]). + 4 + 4 + read-only + + + HDRCAPABLE + SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). + 5 + 5 + + + DEVICEROLE + Device Role field in Bus Characteristic Register (BCR[7:6]). + 6 + 7 + + + DCR + I3C Device Characteristic Value. + 8 + 15 + + + HDRCAP + I3C Device HDR Capability Register Value. + 16 + 23 + read-only + + + + + SLVMAXLEN + I3C Max Write/Read Length Register. + 0x07C + read-write + 0x00FF00FF + 0x20 + + + MWL + I3C Device Max Write Length + 0 + 15 + read-only + + + MRL + I3C Device Max Read Length. + 16 + 31 + read-only + + + + + MAXREADTURNAROUND + MXDS Maximum Read Turnaround Time. + 0x080 + read-write + 0x00000000 + 0x20 + + + MXDSMAXRDTURN + Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. + 0 + 23 + read-only + + + + + MAXDATASPEED + The values in this register are returned by the slave as GETACCMST CCC data. + 0x084 + read-write + 0x00000000 + 0x20 + + + MXDSMAXWRSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device + 0 + 2 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSMAXRDSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device + 8 + 10 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSCLKDATATURN + Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device + 16 + 18 + + + 8NS + 8ns + 0x0 + + + 9NS + 9ns + 0x1 + + + 10NS + 10ns + 0x2 + + + 11NS + 11ns + 0x3 + + + 12NS + 12ns + 0x4 + + + + + + + SLVINTRREQ + This register is used in slave mode of operation. + 0x08C + read-write + 0x00000000 + 0x20 + + + SIR + Slave Interrupt Request + 0 + 0 + + + SIRCTRL + Slave Interrupt Request Control + 1 + 2 + + + SEND + Send the Assigned Dynamic Address + 0x0 + + + + + MR + Master Request + 3 + 3 + + + IBISTS + IBI Completion Status + 8 + 9 + read-only + + + ACCEPTED + IBI accepted by the Master (ACK response received) + 0x1 + + + NOATTEMPT + IBI Not Attempted + 0x3 + + + + + + + SLVTSXSYMBLTIMING + TSP/TSL Symbol Timing Register + 0x090 + read-write + 0x0000003F + 0x20 + + + SLVTSXSYMBLCNT + TSP/TSL Symbol Count Value. + 0 + 5 + + + + + DEVICECTRLEXTENDED + Device Control Extended register. + 0x0B0 + read-write + 0x00000000 + 0x20 + + + DEVOPERATIONMODE + This bit is used to select the Device Operation Mode before the controller is enabled. + 0 + 1 + + + MASTER + Unspecified + 0x0 + + + SLAVE + Unspecified + 0x1 + + + + + REQMSTACKCTRL + In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current master. + 3 + 3 + + + ACK + ACK GETACCMST CCC + 0x0 + + + NACK + NACK GETACCMST CCC + 0x1 + + + + + + + SCLI3CODTIMING + SCL I3C Open Drain Timing Register + 0x0B4 + read-write + 0x000A0010 + 0x20 + + + I3CODLCNT + I3C Open Drain Low Count. + 0 + 7 + + + I3CODHCNT + I3C Open Drain High Count. + 16 + 23 + + + + + SCLI3CPPTIMING + SCL I3C Push Pull Timing Register + 0x0B8 + read-write + 0x000A000A + 0x20 + + + I3CPPLCNT + I3C Push Pull Low Count. + 0 + 7 + + + I3CPPHCNT + I3C Push Pull High Count. + 16 + 23 + + + + + SCLI2CFMTIMING + SCL I2C Fast Mode Timing Register + 0x0BC + read-write + 0x00100010 + 0x20 + + + I2CFMLCNT + I2C Fast Mode Low Count + 0 + 15 + + + I2CFMHCNT + I2C Fast Mode High Count + 16 + 31 + + + + + SCLI2CFMPTIMING + SCL I2C Fast Mode Plus Timing Register + 0x0C0 + read-write + 0x00100010 + 0x20 + + + I2CFMPLCNT + I2C Fast Mode Plus Low Count + 0 + 15 + + + I2CFMPHCNT + I2C Fast Mode Plus High Count + 16 + 23 + + + + + SCLEXTLCNTTIMING + SCL Extended Low Count Timing Register. + 0x0C8 + read-write + 0x20202020 + 0x20 + + + I3CEXTLCNT1 + I3C Extended Low Count Register 1 + 0 + 7 + + + I3CEXTLCNT2 + I3C Extended Low Count Register 2 + 8 + 15 + + + I3CEXTLCNT3 + I3C Extended Low Count Register 3 + 16 + 23 + + + I3CEXTLCNT4 + I3C Extended Low Count Register 4 + 24 + 31 + + + + + SCLEXTTERMNLCNTTIMING + SCL Termination Bit Low Count Timing Register + 0x0CC + read-write + 0x00030000 + 0x20 + + + I3CEXTTERMNLCNT + I3C Read Termination Bit Low count. + 0 + 3 + + + I3CTSSKEWCNT + I3C HDR Ternary Skew Count. + 16 + 19 + + + + + SDAHOLDSWITCHDLYTIMING + SDA Hold and Mode Switch Delay Timing Register + 0x0D0 + read-write + 0x00010000 + 0x20 + + + SDATXHOLD + This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with + 16 + 18 + + + + + BUSFREEAVAILTIMING + Bus Free and Available Timing Register + 0x0D4 + read-write + 0x00200020 + 0x20 + + + BUSFREETIME + This register field is used only in Master mode of operation + 0 + 15 + + + BUSAVAILABLETIME + This register field is used only in Slave mode of operation + 16 + 31 + + + + + BUSIDLETIMING + Bus Idle Timing Register + 0x0D8 + read-write + 0x00000020 + 0x20 + + + BUSIDLETIME + Bus Idle Count Value. + 0 + 19 + + + + + SCLLOWMSTEXTTIMEOUT + The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low Bus Reset Pattern. + 0x0DC + read-write + 0x003567E0 + 0x20 + + + SCLLOWMSTTIMEOUTCOUNT + This count defines the number of core clock periods to count for generation of the SCL Low Bus Reset Pattern. + 0 + 25 + + + + + I3CVERID + This register reflects the current release number of DWC_mipi_i3c + 0x0E0 + read-write + 0x3130302A + 0x20 + + + I3CVERID + Current release number + 0 + 31 + read-only + + + + + I3CVERTYPE + This register reflects the current release type of DWC_mipi_i3c. + 0x0E4 + read-write + 0x6C633033 + 0x20 + + + I3CVERTYPE + Current release type + 0 + 31 + read-only + + + + + QUEUESIZECAPABILITY + This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. + 0x0E8 + read-write + 0x00022355 + 0x20 + + + TXBUFSIZE + Transmit Data Buffer Size + 0 + 3 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + RXBUFSIZE + Receive Data Buffer Size + 4 + 7 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + CMDBUFSIZE + Command Queue Size + 8 + 11 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + RESPBUFSIZE + Response Queue Size + 12 + 15 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + IBIBUFSIZE + IBI Queue Size + 16 + 19 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + + + 10 + 0x010 + DEVCHARTABLE[%s] + Unspecified + DEVCHARTABLE + read-write + 0x200 + + LOC1 + Description cluster: Device Characteristic Table Location-1 of Device [n] + 0x0 + read-write + 0x00000000 + 0x20 + + + LSBPROVISIONALID + The LSB 32-bit value of Provisional-ID + 0 + 31 + read-only + + + + + LOC2 + Description cluster: Device Characteristic Table Location-2 of Device [n] + 0x4 + read-write + 0x00000000 + 0x20 + + + MSBPROVISIONALID + The MSB 16-bit value of Provisional-ID + 0 + 15 + read-only + + + + + LOC3 + Description cluster: Device Characteristic Table Location-3 of Device [n] + 0x8 + read-write + 0x00000000 + 0x20 + + + DCR + Device Characteristic Value + 0 + 7 + read-only + + + BCR + Bus Characteristic Value + 8 + 15 + read-only + + + + + LOC4 + Description cluster: Device Characteristic Table Location-4 of Device [n] + 0xC + read-write + 0x00000000 + 0x20 + + + DEVDYNAMICADDR + Device Dynamic Address assigned. + 0 + 7 + read-only + + + + + + 0x20 + 0x4 + SECDEVCHARTABLE[%s] + Description collection: Secondary Master Device Characteristic Table Location of Device [n] + 0x200 + read-write + 0x00000000 + 0x20 + + + DYNAMICADDR + The Dynamic Addr of Device [n] + 0 + 7 + read-only + + + DCRTYPE + The DCR TYPE of Device [n] + 8 + 15 + read-only + + + BCRTYPE + The BCR TYPE of Device [n] + 16 + 23 + read-only + + + STATICADDR + The Static Addr of Device [n] + 24 + 31 + read-only + + + + + 0xA + 0x4 + DEVADDRTABLELOC[%s] + Description collection: Device Address Table of Device [n] + 0x2C0 + read-write + 0x00000000 + 0x20 + + + DEVSTATICADDR + Device Static Address. + 0 + 6 + + + DEVDYNAMICADDR + Device Dynamic Address with parity. + 16 + 23 + + + DEVNACKRETRYCNT + This field is used to set the Device NACK Retry count for the particular device. + 29 + 30 + + + LEGACYI2CDEVICE + Legacy I2C device or not. + 31 + 31 + + + + + + DMA + Unspecified + I3CCORE_DMA + read-write + 0x900 + + CH0 + Unspecified + I3CCORE_DMA_CH0 + read-write + 0x000 + + SAR0 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR0 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL00 + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x02504821 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + DSTTRWIDTH + Destination Transfer Width. + 1 + 3 + + + DST_TR_WIDTH_0 + Unspecified + 0x0 + + + DST_TR_WIDTH_1 + Unspecified + 0x1 + + + DST_TR_WIDTH_2 + Unspecified + 0x2 + + + DST_TR_WIDTH_3 + Unspecified + 0x3 + + + DST_TR_WIDTH_4 + Unspecified + 0x4 + + + DST_TR_WIDTH_5 + Unspecified + 0x5 + + + DST_TR_WIDTH_6 + Unspecified + 0x6 + + + DST_TR_WIDTH_7 + Unspecified + 0x7 + + + + + RSVDSRCTRWIDTH + Reserved field - read-only + 4 + 6 + read-only + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + RSVDSRCGATHEREN + Reserved field - read-only + 17 + 17 + read-only + + + DSTSCATTEREN + Destination scatter enable. + 18 + 18 + + + DST_SCATTER_DISABLE + Unspecified + 0x0 + + + DST_SCATTER_ENABLE + Unspecified + 0x1 + + + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL01 + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG0L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E00 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG0H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + RSVD2CFG + Reserved field - read-only + 12 + 14 + read-only + + + RSVD3CFG + Reserved field - read-only + 15 + 31 + read-only + + + + + DSR0 + Destination Scatter register. + 0x050 + read-write + 0x00000000 + 0x20 + + + DSI + Destination Scatter Interval. + 0 + 19 + + + DSC + Destination Scatter Count. + 20 + 24 + + + + + + CH1 + Unspecified + I3CCORE_DMA_CH1 + read-write + 0x058 + + SAR1 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR1 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL1L + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x00F04805 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTTRWIDTH + Reserved field - read-only + 1 + 3 + read-only + + + SRCTRWIDTH + Source Transfer Width. + 4 + 6 + + + SRC_TR_WIDTH_0 + Unspecified + 0x0 + + + SRC_TR_WIDTH_1 + Unspecified + 0x1 + + + SRC_TR_WIDTH_2 + Unspecified + 0x2 + + + SRC_TR_WIDTH_3 + Unspecified + 0x3 + + + SRC_TR_WIDTH_4 + Unspecified + 0x4 + + + SRC_TR_WIDTH_5 + Unspecified + 0x5 + + + SRC_TR_WIDTH_6 + Unspecified + 0x6 + + + SRC_TR_WIDTH_7 + Unspecified + 0x7 + + + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + SRCGATHEREN + Source gather enable. + 17 + 17 + + + SRC_GATHER_DISABLE + Unspecified + 0x0 + + + SRC_GATHER_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTSCATTEREN + Reserved field - read-only + 18 + 18 + read-only + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL1H + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG1L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E20 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG1H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + + + SGR1 + Source Gather register + 0x048 + read-write + 0x00000000 + 0x20 + + + SGI + Source Gather Interval. + 0 + 19 + + + SGC + Source Gather Count. + 20 + 24 + + + + + + INT + Unspecified + I3CCORE_DMA_INT + read-write + 0x2C0 + + RAWTFR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x000 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntTfr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWBLOCK + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x008 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntBlock Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWSRCTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x010 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntSrcTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWDSTTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x018 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntDstTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWERR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x020 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntErr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSTFR + Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x028 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntTfr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSBLOCK + Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x030 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntBlock Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSSRCTRAN + Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x038 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntSrcTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSDSTTRAN + Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x040 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntDstTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSERR + Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x048 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntErr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + MASKTFR + The contents of the Raw Status register RawTfr is masked with the contents of the Mask register MaskTfr. + 0x050 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntTfr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKTFR + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKBLOCK + The contents of the Raw Status register RawBlock is masked with the contents of the Mask register MaskBlock. + 0x058 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntBlock Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKBLOCK + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKSRCTRAN + The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask register MaskSrcTran. + 0x060 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntSrcTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKSRCTRAN + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKDSTTRAN + The contents of the Raw Status register RawDstTran is masked with the contents of the Mask register MaskDstTran. + 0x068 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntDstTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKDSTTRAN + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKERR + The contents of the Raw Status register RawErr is masked with the contents of the Mask register MaskErr. + 0x070 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntErr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKERR + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CLEARTFR + Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x078 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntTfr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARBLOCK + Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x080 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntBlock Interrupt + 0 + 1 + write-only + + + + + CLEARSRCTRAN + Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x088 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntSrcTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARDSTTRAN + Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x090 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntDstTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARERR + Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x098 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntErr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + STATUSINT + The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TFR + OR of the contents of StatusTfr register + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + BLOCK + OR of the contents of StatusBlock register + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + SRCT + OR of the contents of StatusSrcTran + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DSTT + OR of the contents of StatusDstTran + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + ERR + OR of the contents of StatusErr + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + + SWHANDSHAKE + Unspecified + I3CCORE_DMA_SWHANDSHAKE + read-write + 0x368 + + REQSRCREG + A bit is assigned for each channel in this register. + 0x000 + read-write + 0x00000000 + 0x20 + + + SRCREQ + Source Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCREQWE + Source Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + REQDSTREG + A bit is assigned for each channel in this register. + 0x008 + read-write + 0x00000000 + 0x20 + + + DSTREQ + Destination Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTREQWE + Destination Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQSRCREG + A bit is assigned for each channel in this register. + 0x010 + read-write + 0x00000000 + 0x20 + + + SRCSGLREQ + Source Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCSGLREQWE + Source Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQDSTREG + A bit is assigned for each channel in this register. + 0x018 + read-write + 0x00000000 + 0x20 + + + DSTSGLREQ + Destination Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTSGLREQWE + Destination Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTSRCREG + A bit is assigned for each channel in this register. + 0x020 + read-write + 0x00000000 + 0x20 + + + LSTSRC + Source Last Transaction Request register + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTSRCREG + Reserved field- read-only + 2 + 7 + read-only + + + LSTSRCWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTDSTREG + A bit is assigned for each channel in this register. + 0x028 + read-write + 0x00000000 + 0x20 + + + LSTDST + Destination Last Transaction Request + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + LSTDSTWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + + MISC + Unspecified + I3CCORE_DMA_MISC + read-write + 0x398 + + DMACFGREG + This register is used to enable the DW_ahb_dmac, which must be done before any channel activity can begin. + 0x000 + read-write + 0x00000000 + 0x20 + + + DMAEN + DW_ahb_dmac Enable bit. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CHENREG + This is the DW_ahb_dmac Channel Enable Register. + 0x008 + read-write + 0x00000000 + 0x20 + + + CHEN + Channel Enable. + 0 + 1 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + RSVDCHENREG + Reserved field - read-only + 2 + 7 + read-only + + + CHENWE + Channel enable register + 8 + 9 + write-only + + + + + DMAIDREG + This is the DW_ahb_dmac ID register, which is a read-only register that reads back the coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. + 0x010 + read-write + 0x00000000 + 0x20 + + + DMAID + Hardcoded DW_ahb_dmac peripheral ID. + 0 + 31 + read-only + + + + + DMATESTREG + This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written, assuming the DW_ahb_dmac configuration has not optimized the same registers. + 0x018 + read-write + 0x00000000 + 0x20 + + + TESTSLVIF + DMA Test register + 0 + 0 + + + NORMAL_MODE + Unspecified + 0x0 + + + TEST_MODE + Unspecified + 0x1 + + + + + + + DMALPTIMEOUTREG + This register holds the timeout value of Low Power Counter. + 0x020 + read-write + 0x00000008 + 0x20 + + + DMALPTIMEOUT + This field holds timeout value of low power counter register. + 0 + 3 + + + + + DMACOMPPARAMS6L + DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about the component parameter settings for Channel 7. + 0x034 + read-write + 0x00000000 + 0x20 + + + CH7DTW + The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. + 0 + 2 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + DTW_8 + Unspecified + 0x1 + + + DTW_16 + Unspecified + 0x2 + + + DTW_32 + Unspecified + 0x3 + + + DTW_64 + Unspecified + 0x4 + + + DTW_128 + Unspecified + 0x5 + + + DTW_256 + Unspecified + 0x6 + + + + + CH7STW + The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. + 3 + 5 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + STW_8 + Unspecified + 0x1 + + + STW_16 + Unspecified + 0x2 + + + STW_32 + Unspecified + 0x3 + + + STW_64 + Unspecified + 0x4 + + + STW_128 + Unspecified + 0x5 + + + STW_256 + Unspecified + 0x6 + + + + + CH7STATDST + The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7STATSRC + The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7DSTSCAEN + The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7SRCGATEN + The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7LOCKEN + The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7MULTIBLKEN + The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7CTLWBEN + The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7HCLLP + The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH7FC + The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH7MAXMULTSIZE + The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH7DMS + The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7LMS + The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7SMS + The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7FIFODEPTH + The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5L + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x038 + read-write + 0x00000000 + 0x20 + + + CH6DTW + The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STW + The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STATDST + The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6STATSRC + The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6DSTSCAEN + The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6SRCGATEN + The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6LOCKEN + The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6MULTIBLKEN + The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6CTLWBEN + The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6HCLLP + The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH6FC + The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH6MAXMULTSIZE + The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH6DMS + The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6LMS + The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6SMS + The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6FIFODEPTH + The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + IFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5H + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x03C + read-write + 0x00000000 + 0x20 + + + CH5DTW + The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STW + The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STATDST + The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5STATSRC + The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5DSTSCAEN + The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5SRCGATEN + The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5LOCKEN + The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5MULTIBLKEN + The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5CTLWBEN + The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5HCLLP + The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH5FC + The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH5MAXMULTSIZE + The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH5DMS + The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5LMS + The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5SMS + The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5FIFODEPTH + The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4L + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x040 + read-write + 0x00000000 + 0x20 + + + CH4DTW + The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STW + The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STATDST + The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4STATSRC + The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4DSTSCAEN + The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4SRCGATEN + The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4LOCKEN + The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4MULTIBLKEN + The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4CTLWBEN + The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4HCLLP + The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH4FC + The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH4MAXMULTSIZE + The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH4DMS + The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4LMS + The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4SMS + The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4FIFODEPTH + The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4H + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x044 + read-write + 0x00000000 + 0x20 + + + CH3DTW + The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STW + The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STATDST + The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3STATSRC + The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3DSTSCAEN + The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3SRCGATEN + The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3LOCKEN + The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3MULTIBLKEN + The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3CTLWBEN + The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3HCLLP + The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH3FC + The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH3MAXMULTSIZE + The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH3DMS + The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3LMS + The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3SMS + The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3FIFODEPTH + The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3L + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x048 + read-write + 0x00000000 + 0x20 + + + CH2DTW + The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STW + The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STATDST + The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2STATSRC + The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2DSTSCAEN + The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2SRCGATEN + The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2LOCKEN + The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2MULTIBLKEN + The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2CTLWBEN + The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2HCLLP + The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH2FC + The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH2MAXMULTSIZE + The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH2DMS + The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH2LMS + The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2SMS + The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2FIFODEPTH + The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3H + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x04C + read-write + 0x1109A203 + 0x20 + + + CH1DTW + The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STW + The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STATDST + The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1STATSRC + The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1DSTSCAEN + The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1SRCGATEN + The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1LOCKEN + The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1MULTIBLKEN + The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1CTLWBEN + The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1HCLLP + The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH1FC + The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH1MAXMULTSIZE + The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH1DMS + The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1LMS + The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1SMS + The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1FIFODEPTH + The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2L + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x050 + read-write + 0x13016118 + 0x20 + + + CH0DTW + The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STW + The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STATDST + The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0STATSRC + The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0DSTSCAEN + The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0SRCGATEN + The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0LOCKEN + The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0MULTIBLKEN + The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0CTLWBEN + The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0HCLLP + The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH0FC + The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH0MAXMULTSIZE + The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH0DMS + The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0LMS + The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0SMS + The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0FIFODEPTH + The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2H + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x054 + read-write + 0x00000000 + 0x20 + + + CHOMULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant parameter. + 0 + 3 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH1MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant parameter. + 4 + 7 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH2MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant parameter. + 8 + 11 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH3MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant parameter. + 12 + 15 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH4MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant parameter. + 16 + 19 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH5MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant parameter. + 20 + 23 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH6MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant parameter. + 24 + 27 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH7MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant parameter. + 28 + 31 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + + + DMACOMPPARAMS1L + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x058 + read-write + 0x33333333 + 0x20 + + + CHOMAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant parameter. + 0 + 3 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH1MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant parameter. + 4 + 7 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH2MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant parameter. + 8 + 11 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH3MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant parameter. + 12 + 15 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH4MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant parameter. + 16 + 19 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH5MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant parameter. + 20 + 23 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH6MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant parameter. + 24 + 27 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH7MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant parameter. + 28 + 31 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + + + DMACOMPPARAMS1H + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x05C + read-write + 0x3120090C + 0x20 + + + BIGENDIAN + The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. + 0 + 0 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + INTRIO + The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. + 1 + 2 + read-only + + + ALL_INT + Unspecified + 0x0 + + + TYPE_INT + Unspecified + 0x1 + + + COMBINED_INT + Unspecified + 0x2 + + + + + MAXABRST + The value of this register is derived from the DMAH_MABRST coreConsultant parameter. + 3 + 3 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + RSVDDMACOMPPARAMS1 + Reserved field- read-only + 4 + 7 + read-only + + + NUMCHANNELS + The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. + 8 + 10 + read-only + + + NUM_CHANNEL_1 + Unspecified + 0x0 + + + NUM_CHANNEL_2 + Unspecified + 0x1 + + + NUM_CHANNEL_3 + Unspecified + 0x2 + + + NUM_CHANNEL_4 + Unspecified + 0x3 + + + NUM_CHANNEL_5 + Unspecified + 0x4 + + + NUM_CHANNEL_6 + Unspecified + 0x5 + + + NUM_CHANNEL_7 + Unspecified + 0x6 + + + NUM_CHANNEL_8 + Unspecified + 0x7 + + + + + NUMMASTERINT + The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. + 11 + 12 + read-only + + + NUM_MST_INTERFACE_1 + Unspecified + 0x0 + + + NUM_MST_INTERFACE_2 + Unspecified + 0x1 + + + NUM_MST_INTERFACE_3 + Unspecified + 0x2 + + + NUM_MST_INTERFACE_4 + Unspecified + 0x3 + + + + + SHDATAWIDTH + The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. + 13 + 14 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M4HDATAWIDTH + The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. + 15 + 16 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M3HDATAWIDTH + The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. + 17 + 18 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M2HDATAWIDTH + The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. + 19 + 20 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M1HDATAWIDTH + The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. + 21 + 22 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + NUMHSINT + The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. + 23 + 27 + read-only + + + HS_INTERFACE_0 + Unspecified + 0x00 + + + HS_INTERFACE_1 + Unspecified + 0x01 + + + HS_INTERFACE_2 + Unspecified + 0x02 + + + HS_INTERFACE_3 + Unspecified + 0x03 + + + HS_INTERFACE_4 + Unspecified + 0x04 + + + HS_INTERFACE_5 + Unspecified + 0x05 + + + HS_INTERFACE_6 + Unspecified + 0x06 + + + HS_INTERFACE_7 + Unspecified + 0x07 + + + HS_INTERFACE_8 + Unspecified + 0x08 + + + HS_INTERFACE_9 + Unspecified + 0x09 + + + HS_INTERFACE_a + Unspecified + 0x0A + + + HS_INTERFACE_b + Unspecified + 0x0B + + + HS_INTERFACE_c + Unspecified + 0x0C + + + HS_INTERFACE_d + Unspecified + 0x0D + + + HS_INTERFACE_e + Unspecified + 0x0E + + + HS_INTERFACE_f + Unspecified + 0x0F + + + HS_INTERFACE_10 + Unspecified + 0x10 + + + + + ADDENCODEDPARAMS + The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. + 28 + 28 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + STATICENDIANSELECT + The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant parameter. + 29 + 29 + read-only + + + + + DMACOMPSID0 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the component type. + 0x060 + read-write + 0x44571110 + 0x20 + + + DMACOMPTYPE + DMA Component Type Number = `h44571110. + 0 + 31 + read-only + + + + + DMACOMPSID1 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the version of the packaged component. + 0x064 + read-write + 0x3232322A + 0x20 + + + DMACOMPVERSION + DMA Component Version. + 0 + 31 + read-only + + + + + + + + + GLOBAL_I3CCORE121 + I3CCORE 1 + 0x2FBE1000 + + + + + GLOBAL_DMU120 + DMU 0 + 0x2FBEF800 + DMU + + + + 0 + 0x1000 + registers + + DMU + 0x20 + + + DMUCR + DMU Core Release + 0x3C0 + read-only + 0x00000000 + 0x20 + + + REL + Core Release + 1 + 1 + + + STEP + Step of Core Release + 2 + 2 + + + SUBSTEP + Sub-step of Core Release + 3 + 3 + + + YEAR + Time Stamp Year + 4 + 4 + + + MON + Time Stamp Month + 6 + 6 + + + DAY + Time Stamp Day + 8 + 8 + + + + + DMUI + DMU Internals + 0x3C4 + read-write + 0x00070000 + 0x20 + + + TXR + TX Service Request line of DMU + 0 + 0 + + + NotRequested + No TX DMA service requested + 0x0 + + + Requested + TX DMA Service requested + 0x1 + + + + + RX0R + RX0 Service Request line of DMU + 1 + 1 + + + NotRequested + No RX0 DMA service requested + 0x0 + + + Requested + RX0 DMA Service requested + 0x1 + + + + + RX1R + RX1 Service Request line of DMU + 2 + 2 + + + NotRequested + No RX1 DMA service requested + 0x0 + + + Requested + RX1 DMA Service requested + 0x1 + + + + + TXER + TX Event Service Request line of DMU + 3 + 3 + + + NotRequested + No TX Event DMA service requested + 0x0 + + + Requested + TX Event DMA Service requested + 0x1 + + + + + TFQPIP + TX FIFO/Queue Put Index Previous + 8 + 12 + + + ENA + DMU is enabled + 15 + 15 + + + Disabled + DMU is disabled + 0x0 + + + Enabled + DMU is enabled and can process DMA data + 0x1 + + + + + DEHS + Detect Element Handler State + 16 + 18 + + + DTX + Detect DMU Element Service + 20 + 20 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX0 + Detect DMU Element Service + 21 + 21 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX1 + Detect DMU Element Service + 22 + 22 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DTXE + Detect DMU Element Service + 23 + 23 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + EHS + Element Handler State + 24 + 26 + + + wait4cce + wait for bit MCAN:CCCR.CCE getting zero + 0x0 + + + wait4sa + wait for Start Address + 0x1 + + + wait4ta + wait for Trigger Address + 0x2 + + + transfer + wait for transfer of Element word + 0x3 + + + ack2mcan + acknowledge to MCAN + 0x4 + + + recovery + exception recovery + 0x5 + + + + + TX + Actual DMU Element Service + 28 + 28 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX0 + Actual DMU Element Service + 29 + 29 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX1 + Actual DMU Element Service + 30 + 30 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + TXE + Actual DMU Element Service + 31 + 31 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + + + DMUQC + DMU Queueing Counter + 0x3C8 + read-write + 0x00000000 + 0x20 + + + TXEEC + TX Element Enqueueing Counter + 0 + 7 + + + RX0EDC + RX0 Element Dequeueing Counter + 8 + 15 + + + RX1EDC + RX1 Element Dequeueing Counter + 16 + 23 + + + TXEEDC + TX Event Element Dequeueing Counter + 24 + 31 + + + + + DMUIR + DMU Interrupt Register + 0x3CC + read-write + 0x00000000 + 0x20 + + + TXENSA + TX Element Not Start Address + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal write access + 0x0 + + + Generated + Write to TX Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEIE + TX Element Illegal Enqueueing + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal enqueueing + 0x0 + + + Generated + Start of enqueueing without request detected, exception recovery started. + 0x1 + + + + + TXEIAS + TX Element Illegal Access Sequence + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEIDLC + TX Element Illegal DLC + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal DLC detected + 0x0 + + + Generated + DLC exceeds Tx Buffer element size of MCAN, exception recovery started. + 0x1 + + + + + TXEWATA + TX Element Write After Trigger Address + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write after Trigger Address + 0x0 + + + Generated + Write after Trigger address detected + 0x1 + + + + + TXEIR + TX Element Illegal Read + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read access + 0x0 + + + Generated + Illegal read access to DMU TX Element section detected, exception recovery started. + 0x1 + + + + + TXEE + A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx message enqueued + 0x0 + + + Generated + Tx message successfully enqueued + 0x1 + + + + + RX0ENSA + RX0 Element Not Start Address + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX0 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX0EID + RX0 Element Illegal Dequeueing + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX0EIAS + RX0 Element Illegal Access Sequence + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX0EIW + RX0 Element Illegal Write + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX0 Element detected, exception recovery started. + 0x1 + + + + + RX0ED + RX0 Element Dequeued + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX0EIO + RX0 Element Illegal Overwrite by timestamp + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + BEU + Bus Error Uncorrected + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + RX1ENSA + RX1 Element Not Start Address + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX1 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX1EID + RX1 Element Illegal Dequeueing + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX1EIAS + RX0 Element Illegal Access Sequence + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX1EIW + RX1 Element Illegal Write + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX1 Element detected, exception recovery started. + 0x1 + + + + + RX1ED + RX0 Element Dequeued + 20 + 20 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX1EIO + RX1 Element Illegal Overwrite by timestamp + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + TXEENSA + TX Event Element Not Start Address + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from TX Event Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEEID + TX Event Element Illegal Dequeueing + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started. + 0x1 + + + + + TXEEIAS + TX Event Element Illegal Access Sequence + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEEIW + TX Event Element Illegal Write + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU TX Event Element detected, exception recovery started. + 0x1 + + + + + TXEED + TX Event Element Dequeued + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No TX Event Element dequeued + 0x0 + + + Generated + TX Event Element successfully dequeued + 0x1 + + + + + DT + Debug Trigger + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Debug point not reached + 0x0 + + + Generated + Debug point reached + 0x1 + + + + + IAC + Illegal Access while in Configuration mode + 30 + 30 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Illegal Access while CCE mode + 0x0 + + + Generated + Illegal Access while CCE mode + 0x1 + + + + + + + DMUIE + DMU Interrupt Enable + 0x3D0 + read-write + 0x00000000 + 0x20 + + + TXENSAE + TX Element Not Start Address Enable + 0 + 0 + + + Disabled + Flag does not activate the interrupt line DMU + 0x0 + + + Enabled + the interrupt line DMU will be activated + 0x1 + + + + + + + DMUC + DMU Configuration + 0x3D4 + read-write + 0x00000000 + 0x20 + + + TTS + Transfer Timestamp + 0 + 0 + + + Disabled + No timestamp will be transferred via DMU Virtual Buffer + 0x0 + + + Enabled + Timestamp of message will be transferred from TSU via DMU Virtual Buffer + 0x1 + + + + + + + + + GLOBAL_MCAN120 + MCAN 0 + 0x2FBEF800 + GLOBAL_DMU120 + MCAN + + + + 0 + 0x1000 + registers + + MCAN + 0x20 + + + ENDN + Endian Register + 0x004 + read-only + 0x00000000 + 0x20 + + + ETV + Endianness Test Value + 0 + 31 + + + + + DBTP + Data Bit Timing and Prescaler Register + 0x00C + read-write + 0x00000000 + 0x20 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 3 + + + DTSEG2 + Data time segment after sample point + 4 + 7 + + + DTSEG1 + Data time segment before sample point + 8 + 12 + + + DBRP + Data Bit Rate Prescaler + 16 + 20 + + + TDC + Transmitter Delay Compensation + 23 + 23 + + + Disabled + Unspecified + 0x0 + + + Enabled + Unspecified + 0x1 + + + + + + + TEST + Test Register + 0x010 + read-write + 0x00000000 + 0x20 + + + LBCK + Loop Back Mode + 4 + 4 + + + Disabled + Loop Back Mode is disabled + 0x0 + + + Enabled + Loop Back Mode is enabled + 0x1 + + + + + TX + Control of Transmit Pin + 5 + 6 + + + CanCore + controlled by the CAN Core, updated at the end of the CAN bit time + 0x0 + + + Monitored + Sample Point can be monitored at pin m_can_tx + 0x1 + + + Dominant + Dominant (0) level at pin m_can_tx + 0x2 + + + Recessive + Recessive (1) at pin m_can_tx + 0x3 + + + + + RX + Receive Pin + 7 + 7 + + + Dominant + The CAN bus is dominant (m_can_rx = 0) + 0x0 + + + Recessive + The CAN bus is recessive (m_can_rx = '1') + 0x1 + + + + + TXBNP + Tx Buffer Number Prepared + 8 + 12 + + + PVAL + Prepared Valid + 13 + 13 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + TXBNS + Tx Buffer Number Started + 16 + 20 + + + SVAL + Started Valid + 21 + 21 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + + + RWD + RAM Watchdog + 0x014 + read-write + 0x00000000 + 0x20 + + + WDC + Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is + disabled. + 0 + 7 + + + WDV + Actual Message RAM Watchdog Counter Value. + 8 + 15 + + + + + CCCR + CC Control Register + 0x018 + read-write + 0x00000000 + 0x20 + + + INIT + Initialization + 0 + 0 + + + Normal + Normal Operation + 0x0 + + + Initialization + Initialization is started + 0x1 + + + + + CCE + Configuration Change Enable + 1 + 1 + + + Disabled + The CPU has no write access to the protected configuration registers + 0x0 + + + Enabled + The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + 0x1 + + + + + ASM + Restricted Operation Mode + 2 + 2 + + + Disabled + Normal CAN operation + 0x0 + + + Enabled + Restricted Operation Mode active + 0x1 + + + + + CSA + Clock Stop Acknowledge + 3 + 3 + + + Disabled + No clock stop acknowledged + 0x0 + + + Enabled + MCAN may be set in power down by stopping m_can_hclk and m_can_cclk + 0x1 + + + + + CSR + Clock Stop Request + 4 + 4 + + + Disabled + No clock stop is requested + 0x0 + + + Enabled + Clock stop requested. + 0x1 + + + + + MON + Bus Monitoring Mode + 5 + 5 + + + Disabled + Bus Monitoring Mode is disabled + 0x0 + + + Enabled + Bus Monitoring Mode is enabled + 0x1 + + + + + DAR + Disable Automatic Retransmission + 6 + 6 + + + Enabled + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + Disabled + Automatic retransmission disabled + 0x1 + + + + + TEST + Test Mode Enable + 7 + 7 + + + Disabled + Normal operation, register TEST holds reset values + 0x0 + + + Enabled + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD Operation Enable + 8 + 8 + + + Disabled + FD operation disabled + 0x0 + + + Enabled + FD operation enabled + 0x1 + + + + + BRSE + Bit Rate Switch Enable + 9 + 9 + + + Disabled + Bit rate switching for transmissions disabled + 0x0 + + + Enabled + Bit rate switching for transmissions enabled + 0x1 + + + + + WMM + Wide Message Marker + 11 + 11 + + + Disabled + 8-bit Message Marker used + 0x0 + + + Enabled + 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 0x1 + + + + + PXHD + Protocol Exception Handling Disable + 12 + 12 + + + Enabled + Protocol exception handling enabled + 0x0 + + + Disabled + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge Filtering during Bus Integration + 13 + 13 + + + Disabled + Edge filtering disabled + 0x0 + + + Enabled + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + Transmit Pause + 14 + 14 + + + Disabled + Transmit pause disabled + 0x0 + + + Enabled + Transmit pause enabled + 0x1 + + + + + NISO + Non ISO Operation + 15 + 15 + + + Disabled + CAN FD frame format according to ISO 11898-1:2015 + 0x0 + + + Enabled + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + NBTP + Nominal Bit Timing and Prescaler Register + 0x01C + read-write + 0x00000000 + 0x20 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 6 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 15 + + + NBRP + Nominal Bit Rate Prescaler + 16 + 24 + + + NSJW + Nominal (Re)Synchronization Jump Width + 25 + 31 + + + + + TSCC + Timestamp Counter Configuration + 0x020 + read-write + 0x00000000 + 0x20 + + + TSS + Timestamp Select + 0 + 1 + + + Zero + Timestamp counter value always 0x0000 + 0x0 + + + Increment + Timestamp counter value incremented according to TCP + 0x1 + + + External + External timestamp counter value used + 0x2 + + + Zero0 + Same as Zero + 0x3 + + + + + TCP + Timestamp Counter Prescaler + 16 + 19 + + + + + TSCV + Timestamp Counter Value + 0x024 + read-write + 0x00000000 + 0x20 + + + TSC + Timestamp Counter + 0 + 15 + + + + + TOCC + Timeout Counter Configuration + 0x028 + read-write + 0x00000000 + 0x20 + + + ETOC + Enable Timeout Counter + 0 + 0 + + + Disabled + Timeout Counter disabled + 0x0 + + + Enabled + Timeout Counter enabled + 0x1 + + + + + TOS + Timeout Select + 1 + 2 + + + Continuous + Continuous operation + 0x0 + + + TxEvent + Timeout controlled by Tx Event FIFO + 0x1 + + + RxFifo0 + Timeout controlled by Rx FIFO 0 + 0x2 + + + RxFifo1 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout Period + 16 + 31 + + + + + TOCV + Timeout Counter Value + 0x02C + read-write + 0x00000000 + 0x20 + + + TOC + Timeout Counter + 0 + 15 + + + + + ECR + Error Counter Register + 0x040 + read-write + 0x00000000 + 0x20 + + + TEC + Transmit Error Counter + 0 + 7 + + + REC + Receive Error Counter + 8 + 14 + + + RP + Receive Error Passive + 15 + 15 + + + Below + The Receive Error Counter is below the error passive level of 128 + 0x0 + + + Reached + The Receive Error Counter has reached the error passive level of 128 + 0x1 + + + + + CEL + CAN Error Logging + 16 + 23 + + + + + PSR + Protocol Status Register + 0x044 + read-write + 0x00000000 + 0x20 + + + LEC + Last Error Code + 0 + 2 + + + NoError + No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + StuffError + More than 5 equal bits in a sequence have occurred in a part of a received message + where this is not allowed. + 0x1 + + + FormError + A fixed format part of a received frame has the wrong format. + 0x2 + + + AckError + The message transmitted by the MCAN was not acknowledged by another node. + 0x3 + + + Bit1Error + During the transmission of a message (with the exception of the arbitration field), + the device wanted to send a recessive level (bit of logical value 1), but the monitored bus + value was dominant. + 0x4 + + + Bit0Error + During the transmission of a message (or acknowledge bit, or active error flag, or + overload flag), the device wanted to send a dominant level (data or identifier bit logical value + '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set + each time a sequence of 11 recessive bits has been monitored. This enables the CPU to + monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + dominant or continuously disturbed). + 0x5 + + + CRCError + The CRC check sum of a received message was incorrect. The CRC of an incoming + message does not match with the CRC calculated from the received data. + 0x6 + + + NoChange + Any read access to the Protocol Status Register re-initializes the LEC to '7'. + When the LEC shows the value '7', no CAN bus event was detected since the last CPU read + access to the Protocol Status Register. + 0x7 + + + + + ACT + Activity + 3 + 4 + + + Synchronizing + Node is synchronizing on CAN communication + 0x0 + + + Idle + Node is neither receiver nor tr ansmitter + 0x1 + + + Receiver + Node is operating as receiver + 0x2 + + + Transmitter + Node is operating as transmitter + 0x3 + + + + + EP + Error Passive + 5 + 5 + + + Active + The MCAN is in the Error_Active state. It normally takes part in bus communication and + sends an active error flag when an error has been detected + 0x0 + + + Passive + The MCAN is in the Error_Passive state + 0x1 + + + + + EW + Warning Status + 6 + 6 + + + Below + Both error counters are below the Error_Warning limit of 96 + 0x0 + + + Reached + At least one of error counter has reached the Error_Warning limit of 96 + 0x1 + + + + + BO + Bus_Off Status + 7 + 7 + + + On + The MCAN is not Bus_Off + 0x0 + + + Off + The MCAN is in Bus_Off state + 0x1 + + + + + DLEC + Data Phase Last Error Code + 8 + 10 + + + RESI + ESI flag of last received CAN FD Message + 11 + 11 + + + NotReceived + Last received CAN FD message did not ha ve its ESI flag set + 0x0 + + + Received + Last received CAN FD message had its ESI flag set + 0x1 + + + + + RBRS + BRS flag of last received CAN FD Message + 12 + 12 + + + NotReceived + Last received CAN FD message did not ha ve its BRS flag set + 0x0 + + + Received + Last received CAN FD message had its BRS flag set + 0x1 + + + + + RFDF + Received a CAN FD Message + 13 + 13 + + + NotReceived + Since this bit was reset by the CPU, no CAN FD message has been received + 0x0 + + + Received + Message in CAN FD format with FDF flag set has been received + 0x1 + + + + + PXE + Protocol Exception Event + 14 + 14 + + + NotTriggered + No protocol exception event occurred since last read access + 0x0 + + + Triggered + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter Delay Compensation Value + 16 + 22 + + + + + TDCR + Transmitter Delay Compensation Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TDCF + Transmitter Delay Compensation Filter Window Length + 0 + 6 + + + TDCO + Transmitter Delay Compensation SSP Offset + 8 + 14 + + + + + IR + Interrupt Register + 0x050 + read-write + 0x00000000 + 0x20 + + + RF0N + Rx FIFO 0 New Message + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 0 + 0x0 + + + Generated + New message written to Rx FIFO 0 + 0x1 + + + + + RF0W + Rx FIFO 0 Watermark Reached + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 fill level below watermark + 0x0 + + + Generated + Rx FIFO 0 fill level reached watermark + 0x1 + + + + + RF0F + Rx FIFO 0 Full + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 not full + 0x0 + + + Generated + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 0 message lost + 0x0 + + + Generated + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 0x1 + + + + + RF1N + Rx FIFO 1 New Message + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 1 + 0x0 + + + Generated + New message written to Rx FIFO 1 + 0x1 + + + + + RF1W + Rx FIFO 1 Watermark Reached + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 fill level below watermark + 0x0 + + + Generated + Rx FIFO 1 fill level reached watermark + 0x1 + + + + + RF1F + Rx FIFO 1 Full + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 not full + 0x0 + + + Generated + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 1 message lost + 0x0 + + + Generated + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + HPM + High Priority Message + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No high priority message received + 0x0 + + + Generated + High priority message received + 0x1 + + + + + TC + Transmission Completed + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission completed + 0x0 + + + Generated + Transmission completed + 0x1 + + + + + TCF + Transmission Cancellation Finished + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission cancellation finished + 0x0 + + + Generated + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO Empty + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx FIFO non-empty + 0x0 + + + Generated + Tx FIFO empty + 0x1 + + + + + TEFN + Tx Event FIFO New Entry + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO unchanged + 0x0 + + + Generated + Tx Handler wrote Tx Event FIFO element + 0x1 + + + + + TEFW + Tx Event FIFO Watermark Reached + 13 + 13 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO fill level below watermark + 0x0 + + + Generated + Tx Event FIFO fill level reached watermark + 0x1 + + + + + TEFF + Tx Event FIFO Full + 14 + 14 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO not full + 0x0 + + + Generated + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx Event FIFO element lost + 0x0 + + + Generated + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero + 0x1 + + + + + TSW + Timestamp Wraparound + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timestamp counter wrap-around + 0x0 + + + Generated + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM Access Failure + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM access failure occurred + 0x0 + + + Generated + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout Occurred + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timeout + 0x0 + + + Generated + Timeout reached + 0x1 + + + + + DRX + Message stored to Dedicated Rx Buffer + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx Buffer updated + 0x0 + + + Generated + At least one received message stored into an Rx Buff er + 0x1 + + + + + BEU + Bus Error Uncorrected + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + ELO + Error Logging Overflow + 22 + 22 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + CAN Error Logging Counter did not overflow + 0x0 + + + Generated + Overflow of CAN Error Logging Counter occurred + 0x1 + + + + + EP + Error Passive + 23 + 23 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Passive status unchanged + 0x0 + + + Generated + Error_Passive status changed + 0x1 + + + + + EW + Warning Status + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Warning status unchanged + 0x0 + + + Generated + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off Status + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Bus_Off status unchanged + 0x0 + + + Generated + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog Interrupt + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM Watchdog event occurred + 0x0 + + + Generated + Message RAM Watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in arbitration phase + 0x0 + + + Generated + Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 0x1 + + + + + PED + Protocol Error in Data Phase (Data Bit Time is used) + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in data phase + 0x0 + + + Generated + Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 0x1 + + + + + ARA + Access to Reserved Address + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No access to reserved address occurred + 0x0 + + + Generated + Access to reserved address occurred + 0x1 + + + + + + + IE + Interrupt Enable + 0x054 + read-write + 0x00000000 + 0x20 + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 0 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 2 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 3 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 4 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 5 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 6 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 7 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + HPME + High Priority Message Interrupt Enable + 8 + 8 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCE + Transmission Completed Interrupt Enable + 9 + 9 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 10 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 11 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 12 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 13 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 14 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 15 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 16 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 17 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 18 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 19 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BEUE + Bus Error Uncorrected Interrupt Enable + 21 + 21 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 22 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EPE + Error Passive Interrupt Enable + 23 + 23 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EWE + Warning Status Interrupt Enable + 24 + 24 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BOE + Bus_Off Status Interrupt Enable + 25 + 25 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + WDIE + Watchdog Interrupt Enable + 26 + 26 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 27 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEDE + Protocol Error in Data Phase Enable + 28 + 28 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ARAE + Access to Reserved Address Enable + 29 + 29 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + + + ILS + Interrupt Line Select + 0x058 + read-write + 0x00000000 + 0x20 + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 0 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 2 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 3 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 4 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 5 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 6 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 7 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + HPML + High Priority Message Interrupt Line + 8 + 8 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCL + Transmission Completed Interrupt Line + 9 + 9 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 10 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 11 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 12 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 13 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 14 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 15 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 16 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 17 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TOOL + Timeout Occurred Interrupt Line + 18 + 18 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 19 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BEUL + Bus Error Uncorrected Interrupt Line + 21 + 21 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 22 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EPL + Error Passive Interrupt Line + 23 + 23 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EWL + Warning Status Interrupt Line + 24 + 24 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BOL + Bus_Off Status Interrupt Line + 25 + 25 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + WDIL + Watchdog Interrupt Line + 26 + 26 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 27 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEDL + Protocol Error in Data Phase Line + 28 + 28 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ARAL + Access to Reserved Address Line + 29 + 29 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + + + ILE + Interrupt Line Enable + 0x05C + read-write + 0x00000000 + 0x20 + + + EINT0 + Enable Interrupt Line 0 + 0 + 0 + + + Disable + Interrupt line CORE0 disabled. + 0x0 + + + Enable + Interrupt line CORE0 enabled. + 0x1 + + + + + EINT1 + Enable Interrupt Line 1 + 1 + 1 + + + Disable + Interrupt line CORE1 disabled. + 0x0 + + + Enable + Interrupt line CORE1 enabled. + 0x1 + + + + + + + GFC + Global Filter Configuration + 0x080 + read-write + 0x00000000 + 0x20 + + + RRFE + Reject Remote Frames Extended + 0 + 0 + + + Filter + Filter remote frames with 29-bit extended IDs. + 0x0 + + + Reject + Reject all remote frames with 29-bit extended IDs. + 0x1 + + + + + RRFS + Reject Remote Frames Standard + 1 + 1 + + + Filter + Filter remote frames with 11-bit standard IDs. + 0x0 + + + Reject + Reject all remote frames with 11-bit standard IDs. + 0x1 + + + + + ANFE + Accept Non-matching Frames Extended + 2 + 3 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + ANFS + 4 + 5 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + + + SIDFC + Standard ID Filter Configuration + 0x084 + read-write + 0x00000000 + 0x20 + + + FLSSA + Filter List Standard Start Address + 2 + 15 + + + LSS + List Size Standard + 16 + 23 + + + + + XIDFC + Extended ID Filter Configuration + 0x088 + read-write + 0x00000000 + 0x20 + + + FLESA + Filter List Extended Start Address + 2 + 15 + + + LSE + List Size Extended + 16 + 22 + + + + + XIDAM + Extended ID AND Mask + 0x090 + read-write + 0x00000000 + 0x20 + + + EIDM + Extended ID Mask + 0 + 28 + + + + + HPMS + High Priority Message Status + 0x094 + read-only + 0x00000000 + 0x20 + + + BIDX + Buffer Index + 0 + 5 + + + MSI + Message Storage Indicator + 6 + 7 + + + NotSelected + No FIFO selected. + 0x0 + + + Lost + FIFO message lost. + 0x1 + + + Stored0 + Message stored in FIFO 0. + 0x2 + + + Stored1 + Message stored in FIFO 1. + 0x3 + + + + + FIDX + Filter Index + 8 + 14 + + + FLST + Filter List + 15 + 15 + + + Standard + Standard Filter List. + 0x0 + + + Extended + Extended Filter List. + 0x1 + + + + + + + NDAT1 + New Data 1 + 0x098 + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + NDAT2 + New Data 2 + 0x09C + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + RXF0C + Rx FIFO 0 Configuration + 0x0A0 + read-write + 0x00000000 + 0x20 + + + F0SA + Rx FIFO 0 Start Address + 2 + 15 + + + F0S + Rx FIFO 0 Size + 16 + 22 + + + F0WM + Rx FIFO 0 Watermark + 24 + 30 + + + F0OM + FIFO 0 Operation Mode + 31 + 31 + + + Blocking + FIFO 0 blocking mode. + 0x0 + + + Overwrite + FIFO 0 overwrite mode. + 0x1 + + + + + + + RXF0S + Rx FIFO 0 Status + 0x0A4 + read-only + 0x00000000 + 0x20 + + + F0FL + Rx FIFO 0 Fill Leve + 0 + 6 + + + F0GI + Rx FIFO 0 Get Index + 8 + 13 + + + F0PI + Rx FIFO 0 Put Index + 16 + 21 + + + F0F + Rx FIFO 0 Full + 24 + 24 + + + NotFull + Rx FIFO 0 not full. + 0x0 + + + Full + Rx FIFO 0 full. + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 25 + 25 + + + NotLost + No Rx FIFO 0 message lost. + 0x0 + + + Lost + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + 0x1 + + + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0x0A8 + read-write + 0x00000000 + 0x20 + + + F0AI + Rx FIFO 0 Acknowledge Index + 0 + 5 + + + + + RXBC + Rx Buffer Configuration + 0x0AC + read-write + 0x00000000 + 0x20 + + + RBSA + Rx Buffer Start Address + 2 + 15 + + + + + RXF1C + Rx FIFO 1 Configuration + 0x0B0 + read-write + 0x00000000 + 0x20 + + + F1SA + Rx FIFO 1 Start Address + 2 + 15 + + + F1S + Rx FIFO 1 Size + 16 + 22 + + + F1WM + Rx FIFO 1 Watermark + 24 + 30 + + + F1OM + FIFO 1 Operation Mode + 31 + 31 + + + BlockingMode + FIFO 1 blocking mode + 0x0 + + + OwerwriteMode + FIFO 1 overwrite mode + 0x1 + + + + + + + RXF1S + Rx FIFO 1 Status + 0x0B4 + read-only + 0x00000000 + 0x20 + + + F1FL + Rx FIFO 1 Fill Level + 0 + 6 + + + F1GI + Rx FIFO 1 Get Index + 8 + 13 + + + F1PI + Rx FIFO 1 Put Index + 16 + 21 + + + F1F + Rx FIFO 1 Full + 24 + 24 + + + NotFull + Rx FIFO 1 not full + 0x0 + + + Full + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 25 + 25 + + + NoMessageLost + No Rx FIFO 1 message lost + 0x0 + + + MessageLost + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + DMS + Debug Message Status + 30 + 31 + + + Idle + Idle state, wait for reception of debug messages, DMA request is cleared + 0x0 + + + ReceivedMesA + Debug message A received + 0x1 + + + ReceivedMesAB + Debug messages A, B received + 0x2 + + + ReceivedMesABC + Debug messages A, B, C received, DMA request is set + 0x3 + + + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0x0B8 + read-write + 0x00000000 + 0x20 + + + F1AI + Rx FIFO 1 Acknowledge Index + 0 + 5 + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0x0BC + read-write + 0x00000000 + 0x20 + + + F0DS + Rx FIFO 0 Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + F1DS + Rx FIFO 1 Data Field Size + 4 + 6 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + RBDS + Rx Buffer Data Field Size + 8 + 10 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBC + Tx Buffer Configuration + 0x0C0 + read-write + 0x00000000 + 0x20 + + + TBSA + Tx Buffers Start Address + 2 + 15 + + + NDTB + Number of Dedicated Transmit Buffers + 16 + 21 + + + TFQS + Transmit FIFO/Queue Size + 24 + 29 + + + TFQM + Tx FIFO/Queue Mode + 30 + 30 + + + TxFIFO + Tx FIFO operation + 0x0 + + + TxQueue + Tx Queue operation + 0x1 + + + + + + + TXFQS + Tx FIFO/Queue Status + 0x0C4 + read-only + 0x00000000 + 0x20 + + + TFFL + Tx FIFO Free Level + 0 + 5 + + + TFGI + Tx FIFO Get Index + 8 + 12 + + + TFQPI + Tx FIFO/Queue Put Index + 16 + 20 + + + TFQF + Tx FIFO/Queue Full + 21 + 21 + + + NotFull + Tx FIFO/Queue not full + 0x0 + + + Full + Tx FIFO/Queue full + 0x1 + + + + + + + TXESC + Tx Buffer Element Size Configuration + 0x0C8 + read-write + 0x00000000 + 0x20 + + + TBDS + Tx Buffer Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBRP + Tx Buffer Request Pending + 0x0CC + read-only + 0x00000000 + 0x20 + + + TRP + Transmission Request Pending + 0 + 31 + + + NoRequest + No transmission request pending + 0x00000000 + + + Request + Transmission request pending + 0x00000001 + + + + + + + TXBAR + Tx Buffer Add Request + 0x0D0 + read-write + 0x00000000 + 0x20 + + + AR + Add Request + 0 + 31 + + + NoRequest + No transmission request added + 0x00000000 + + + Request + Transmission requested added + 0x00000001 + + + + + + + TXBCR + Tx Buffer Cancellation Request + 0x0D4 + read-write + 0x00000000 + 0x20 + + + CR + Cancellation Request + 0 + 31 + + + NoCancellation + No cancellation pending + 0x00000000 + + + Cancellation + Cancellation pending + 0x00000001 + + + + + + + TXBTO + Tx Buffer Transmission Occurred + 0x0D8 + read-only + 0x00000000 + 0x20 + + + TO + Transmission Occurred + 0 + 31 + + + NoTransmittion + No transmission occurred + 0x00000000 + + + Transmittion + Transmission occurred + 0x00000001 + + + + + + + TXBCF + Tx Buffer Cancellation Finished + 0x0DC + read-only + 0x00000000 + 0x20 + + + CF + Cancellation Finished + 0 + 31 + + + NoCancellation + No transmit buffer cancellation + 0x00000000 + + + CancellationFinished + Transmit buffer cancellation finished + 0x00000001 + + + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0x0E0 + read-write + 0x00000000 + 0x20 + + + TIE + Transmission Interrupt Enable + 0 + 31 + + + Disable + Transmission interrupt disabled + 0x00000000 + + + Enable + Transmission interrupt enable + 0x00000001 + + + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0x0E4 + read-write + 0x00000000 + 0x20 + + + CFIE + Cancellation Finished Interrupt Enable + 0 + 31 + + + Disable + Cancellation finished interrupt disabled + 0x00000000 + + + Enable + Cancellation finished interrupt enabled + 0x00000001 + + + + + + + TXEFC + Tx Event FIFO Configuration + 0x0F0 + read-write + 0x00000000 + 0x20 + + + EFSA + Event FIFO Start Address + 2 + 15 + + + EFS + Event FIFO Size + 16 + 21 + + + EFWM + Event FIFO Watermark + 24 + 29 + + + + + TXEFS + Tx Event FIFO Status + 0x0F4 + read-only + 0x00000000 + 0x20 + + + EFFL + Event FIFO Fill Level + 0 + 5 + + + EFGI + Event FIFO Get Index + 8 + 12 + + + EFPI + Event FIFO Put Index + 16 + 20 + + + EFF + Event FIFO Full + 24 + 24 + + + NotFull + Tx Event FIFO not full + 0x0 + + + Full + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 25 + 25 + + + NotLost + No Tx Event FIFO element lost + 0x0 + + + Lost + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero. + 0x1 + + + + + + + TXEFA + Tx Event FIFO Acknowledge + 0x0F8 + read-write + 0x00000000 + 0x20 + + + EFAI + Event FIFO Acknowledge Index + 0 + 4 + + + + + + + GLOBAL_DMU121 + DMU 1 + 0x2FBF7800 + + + + + GLOBAL_MCAN121 + MCAN 1 + 0x2FBF7800 + GLOBAL_DMU121 + + + + + GLOBAL_STMDATA + System Trace Macrocell data buffer + 0xA0000000 + + + + + 0 + 0x10000000 + registers + + STMDATA + 0x20 + + + 16 + 0x1000000 + DOMAIN[%s] + Unspecified + STMDATA_DOMAIN + read-write + 0x000 + + 0x1000000 + 0x1 + DATA[%s] + Description collection: STM extended stimulus port data buffer area for domain n. NonSecure writes to this region generates trace packets with id n+96. Secure writes to this region generates trace packets with id n+32. + 0x000 + read-write + 0x00 + uint8_t + 0x8 + + + + + + + GLOBAL_TDDCONF + TDDCONF + 0xBF001000 + + + + 0 + 0x1000 + registers + + TDDCONF + 0x20 + + + SYSPWRUPREQ + System power-up request + 0x400 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + DBGPWRUPREQ + Debug power-up request + 0x404 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + TRACEPORTSPEED + Trace port trace clock speed + 0x408 + read-write + 0x00000000 + 0x20 + + + SPEED + Trace clock speed + 0 + 1 + + + Speed100MHz + Speed 100MHz + 0x0 + + + Speed50MHz + Speed 50MHz + 0x1 + + + Speed25MHz + Speed 25MHz + 0x2 + + + Speed12500KHz + Speed 12.5MHz + 0x3 + + + + + + + DEBUGPOWERREQSTATUS + Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests + 0x40C + read-only + 0x00000000 + 0x20 + + + SYSPWRUPREQUESTED + System powerup request status + 0 + 0 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + DBGPWRUPREQUESTED + Debug domain powerup request status + 1 + 1 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + + + + + GLOBAL_STM + System Trace Macrocell + 0xBF042000 + + + + 0 + 0x1000 + registers + + STM + 0x20 + + + DMACTLR + Controls the DMA transfer request mechanism. + 0xC10 + read-write + 0x00000000 + 0x20 + + + SENS + Determines the sensitivity of the DMA request to the current buffer level in the STM + 2 + 3 + + + LT25 + Buffer is &lt;25 percent full. + 0x0 + + + LT50 + Buffer is &lt;50 percent full. + 0x1 + + + LT75 + Buffer is &lt;75 percent full. + 0x2 + + + LT100 + Buffer is &lt;100 percent full. + 0x3 + + + + + + + HEMASTR + Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. + 0xDF4 + read-only + 0x00000000 + 0x20 + + + MASTER + The STPv2 master number that hardware event traces should be associated with. + 0 + 16 + + + + + HEFEAT1R + Indicates the features of the STM. + 0xDF8 + read-only + 0x00000000 + 0x20 + + + HETER + STMHETER support + 0 + 0 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEERR + Hardware event error detection support + 2 + 2 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEMASTR + STMHEMASTR support + 3 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NUMHE + The number of hardware events supported by the STM + 15 + 23 + + + + + HEIDR + Indicates the features of hardware event tracing in the STM. + 0xDFC + read-only + 0x00000000 + 0x20 + + + CLASS + The CLASS field identifies the programmers model + 0 + 3 + + + HardwareEventControl + Hardware Event Control programmers model + 0x1 + + + + + CLASSREV + The CLASSREV field identifies the revision of the programmers model + 4 + 7 + + + VENDSPEC + The VENDSPEC field identifies any vendor specific modifications or mappings + 8 + 11 + + + + + TCSR + Controls the STM settings. + 0xE80 + read-write + 0x00000000 + 0x20 + + + EN + Global STM enable + 0 + 0 + + + Disabled + The STM is disabled. + 0x0 + + + Enabled + The STM is enabled. + 0x1 + + + + + TSEN + Enable or disable timestamp bundling. + 1 + 1 + + + Disabled + Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected. + 0x0 + + + Enabled + Time stamps are enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2. + 0x1 + + + + + SYNCEN + STMSYNCR is implemented so this value is Read As One. + 2 + 2 + + + Disabled + The STM Sync feature is disabled. + 0x0 + + + Enabled + The STM Sync feature is enabled. + 0x1 + + + + + COMPEN + Compression Enable for Stimulus Ports. + 5 + 5 + + + Disabled + Compression disabled, data transfers are transmitted at the size of the transaction. + 0x0 + + + Enabled + Compression enabled, data transfers are compressed to save bandwidth. + 0x1 + + + + + TRACEID + ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. + 16 + 22 + + + BUSY + STM is busy, for example the STM trace FIFO is not empty. + 23 + 23 + + + Ready + STM is not busy. + 0x0 + + + Busy + STM is busy. + 0x1 + + + + + + + AUXCR + Used for implementation defined STM controls. + 0xE94 + read-write + 0x00000000 + 0x20 + + + FIFOAF + FIFO Auto-flush. + 0 + 0 + + + Disabled + Auto-flush is disabled. + 0x0 + + + Enabled + Auto-flush is enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized. + 0x1 + + + + + ASYNCPE + Is ASYNC priority higher than trace? + 1 + 1 + + + Lower + ASYNC priority is always lower than trace. + 0x0 + + + Escalate + ASYNC priority escalates on second synchronization request. + 0x1 + + + + + PRIORINVDIS + Controls arbitration between AXI and HW during flush. + 2 + 2 + + + Enabled + Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done. + 0x0 + + + Disabled + Priority inversion disabled, AXI always has priority over HW. + 0x1 + + + + + CLKON + Provides override control for architectural clock gate enable. + 3 + 3 + + + Disabled + No override, clock gate is controlled by the state of STM. + 0x0 + + + Enabled + Override, clock is enabled. + 0x1 + + + + + AFREADYHIGH + Provides override control for the AFREADY output + 4 + 4 + + + Disabled + No override, AFREADY is controlled by the state of STM. + 0x0 + + + Enabled + Override, AFREADY is driven HIGH. + 0x1 + + + + + + + SPFEAT1R + Indicates the features of the STM. + 0xEA0 + read-write + 0x00000000 + 0x20 + + + PROT + Indicates the implemented STM protocol. + 0 + 3 + + + STPV2 + STM implements the STPV2 protocol. + 0x1 + + + + + TS + Timestamp support. + 4 + 5 + + + Absolute + Absolute timestamps implemented. + 0x1 + + + + + TSFREQ + Timestamp frequency indication configuration. + 6 + 6 + + + NotImplemented + STMTSFREQR is read-only. + 0x0 + + + Implemented + STMTSFREQR is read-write. + 0x1 + + + + + FORCETS + Timestamp force configuration. + 7 + 7 + + + NotImplemented + STMTSSTIMR bit 0 is read-only. + 0x0 + + + Implemented + STMTSSTIMR bit 0 is read-write. + 0x1 + + + + + TRACEBUS + Trace bus support. + 10 + 13 + + + TRIGCTL + Trigger control support. + 14 + 15 + + + TSPRESCALE + Timestamp prescale support + 16 + 17 + + + NotImplemented + Timestamp prescale is not implemented. + 0x0 + + + Implemented + Timestamp prescale is implemented. + 0x1 + + + + + HWTEN + STMTCSR.HWTEN support + 18 + 19 + + + NotImplemented + STMTCSR.HWTEN is not implemented + 0x1 + + + + + SYNCEN + STMTCSR.SYNCEN support + 20 + 21 + + + ReadAsOne + STMTCSR.SYNCEN implemented but always reads as b1 + 0x2 + + + + + SWOEN + STMTCSR.SWOEN support + 22 + 23 + + + NotImplemented + STMTCSR.SWOEN not implemented + 0x1 + + + + + + + SPFEAT2R + Indicates the features of the STM. + 0xEA4 + read-write + 0x00000000 + 0x20 + + + SPTER + STMSPTER support. + 0 + 1 + + + Implemented + STMSPTER is implemented. + 0x2 + + + + + SPER + STMSPER presence. + 2 + 2 + + + Implemented + STMSPER is implemented. + 0x0 + + + NotImplemented + STMSPER is not implemented. + 0x1 + + + + + SPCOMP + Data compression on stimulus ports support. + 4 + 5 + + + Programmable + Data compression support is programmable. STMTCSR.COMPEN is implemented. + 0x3 + + + + + SPOVERRIDE + Timestamp force configuration. + 6 + 6 + + + NotImplemented + STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. + 0x0 + + + Implemented + STMSPOVERRIDER and STMSPMOVERRIDER is implemented. + 0x1 + + + + + PRIVMASK + STMPRIVMASKR support. + 7 + 8 + + + NotImplemented + STMPRIVMASKR is not implemented. + 0x1 + + + + + SPTRTYPE + Stimulus port transaction type support. + 9 + 10 + + + InvariantAndGuaranteed + Both invariant timing and guaranteed transactions are supported. + 0x2 + + + + + DSIZE + Fundamental data size. + 12 + 15 + + + Bits32 + 32-bit data. + 0x0 + + + + + SPTYPE + Stimulus port type support + 18 + 19 + + + OnlyExtended + Only extended stimulus ports are implemented. + 0x1 + + + + + + + SPFEAT3R + Indicates the features of the STM. + 0xEA8 + read-write + 0x00000000 + 0x20 + + + NUMMAST + The number of stimulus ports masters implemented, minus 1. + 0 + 6 + + + Masters128 + Example: 128 masters implemented. + 0x3F + + + + + + + ITTRIGGER + Integration Test for Cross-Trigger Outputs Register. + 0xEE8 + write-only + 0x00000000 + 0x20 + + + TRIGOUTSPTE_W + Sets the value of the TRIGOUTSPTE output in integration mode. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTSW_W + Sets the value of the TRIGOUTSW output in integration mode. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTHETE_W + Sets the value of the TRIGOUTHETE output in integration mode. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ASYNCOUT_W + Sets the value of the ASYNCOUT output in integration mode. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBDATA0 + Controls the value of the ATDATAM output in integration mode. + 0xEEC + write-only + 0x00000000 + 0x20 + + + ATDATAM0_W + Sets the value of the ATDATAM[0]. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM7_W + Sets the value of the ATDATAM[7] output. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM15_W + Sets the value of the ATDATAM[15]. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM23_W + Sets the value of the ATDATAM[23]. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM31_W + Sets the value of the ATDATAM[31]. + 4 + 4 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBCTR2 + Controls the value of the ATDATAM output in integration mode. + 0xEF0 + write-only + 0x00000000 + 0x20 + + + ATREADYM_R + Reads the value of the ATREADYM input. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFVALIDM_R + Reads the value of the AFVALIDM input. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBID + Controls the value of the ATIDM output in integration mode. + 0xEF4 + write-only + 0x00000000 + 0x20 + + + ATIDM_W_0 + Sets the value of pin 0 of the ATIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_1 + Sets the value of pin 1 of the ATIDM output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_2 + Sets the value of pin 2 of the ATIDM output. + 2 + 2 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_3 + Sets the value of pin 3 of the ATIDM output. + 3 + 3 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_4 + Sets the value of pin 4 of the ATIDM output. + 4 + 4 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_5 + Sets the value of pin 5 of the ATIDM output. + 5 + 5 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_6 + Sets the value of pin 6 of the ATIDM output. + 6 + 6 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBCTR0 + Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. + 0xEF8 + write-only + 0x00000000 + 0x20 + + + ATVALIDM_W + Sets the value of the ATVALIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFREADYM_W + Sets the value of the AFREADYM_W output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_0 + Sets the value of pin 0 of the ATBYTESM output. + 8 + 8 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_1 + Sets the value of pin 1 of the ATBYTESM output. + 9 + 9 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the STM. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + NUMSP + This value indicates the number of stimulus ports implemented. + 0 + 16 + + + Max + Maximum 65,536 stimulus ports can be implemented. + 0x10000 + + + + + + + DEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + StimulusTrace + Peripheral is a stimulus trace source. + 0x6 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_TPIU + Trace Port Interface Unit + 0xBF043000 + + + + 0 + 0x1000 + registers + + TPIU + 0x20 + + + SUPPORTEDPORTSIZES + Each bit location is a single port size that is supported on the device. + 0x000 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates whether the TPIU supports port size of 1-bit. + 0 + 0 + + + NotSupported + Port size 1 is not supported. + 0x0 + + + Supported + Port size 1 is supported. + 0x1 + + + + + PORT_SIZE_2 + Indicates whether the TPIU supports port size of 2-bit. + 1 + 1 + + + NotSupported + Port size 2 is not supported. + 0x0 + + + Supported + Port size 2 is supported. + 0x1 + + + + + PORT_SIZE_3 + Indicates whether the TPIU supports port size of 3-bit. + 2 + 2 + + + NotSupported + Port size 3 is not supported. + 0x0 + + + Supported + Port size 3 is supported. + 0x1 + + + + + PORT_SIZE_4 + Indicates whether the TPIU supports port size of 4-bit. + 3 + 3 + + + NotSupported + Port size 4 is not supported. + 0x0 + + + Supported + Port size 4 is supported. + 0x1 + + + + + PORT_SIZE_5 + Indicates whether the TPIU supports port size of 5-bit. + 4 + 4 + + + NotSupported + Port size 5 is not supported. + 0x0 + + + Supported + Port size 5 is supported. + 0x1 + + + + + PORT_SIZE_6 + Indicates whether the TPIU supports port size of 6-bit. + 5 + 5 + + + NotSupported + Port size 6 is not supported. + 0x0 + + + Supported + Port size 6 is supported. + 0x1 + + + + + PORT_SIZE_7 + Indicates whether the TPIU supports port size of 7-bit. + 6 + 6 + + + NotSupported + Port size 7 is not supported. + 0x0 + + + Supported + Port size 7 is supported. + 0x1 + + + + + PORT_SIZE_8 + Indicates whether the TPIU supports port size of 8-bit. + 7 + 7 + + + NotSupported + Port size 8 is not supported. + 0x0 + + + Supported + Port size 8 is supported. + 0x1 + + + + + PORT_SIZE_9 + Indicates whether the TPIU supports port size of 9-bit. + 8 + 8 + + + NotSupported + Port size 9 is not supported. + 0x0 + + + Supported + Port size 9 is supported. + 0x1 + + + + + PORT_SIZE_10 + Indicates whether the TPIU supports port size of 10-bit. + 9 + 9 + + + NotSupported + Port size 10 is not supported. + 0x0 + + + Supported + Port size 10 is supported. + 0x1 + + + + + PORT_SIZE_11 + Indicates whether the TPIU supports port size of 11-bit. + 10 + 10 + + + NotSupported + Port size 11 is not supported. + 0x0 + + + Supported + Port size 11 is supported. + 0x1 + + + + + PORT_SIZE_12 + Indicates whether the TPIU supports port size of 12-bit. + 11 + 11 + + + NotSupported + Port size 12 is not supported. + 0x0 + + + Supported + Port size 12 is supported. + 0x1 + + + + + PORT_SIZE_13 + Indicates whether the TPIU supports port size of 13-bit. + 12 + 12 + + + NotSupported + Port size 13 is not supported. + 0x0 + + + Supported + Port size 13 is supported. + 0x1 + + + + + PORT_SIZE_14 + Indicates whether the TPIU supports port size of 14-bit. + 13 + 13 + + + NotSupported + Port size 14 is not supported. + 0x0 + + + Supported + Port size 14 is supported. + 0x1 + + + + + PORT_SIZE_15 + Indicates whether the TPIU supports port size of 15-bit. + 14 + 14 + + + NotSupported + Port size 15 is not supported. + 0x0 + + + Supported + Port size 15 is supported. + 0x1 + + + + + PORT_SIZE_16 + Indicates whether the TPIU supports port size of 16-bit. + 15 + 15 + + + NotSupported + Port size 16 is not supported. + 0x0 + + + Supported + Port size 16 is supported. + 0x1 + + + + + PORT_SIZE_17 + Indicates whether the TPIU supports port size of 17-bit. + 16 + 16 + + + NotSupported + Port size 17 is not supported. + 0x0 + + + Supported + Port size 17 is supported. + 0x1 + + + + + PORT_SIZE_18 + Indicates whether the TPIU supports port size of 18-bit. + 17 + 17 + + + NotSupported + Port size 18 is not supported. + 0x0 + + + Supported + Port size 18 is supported. + 0x1 + + + + + PORT_SIZE_19 + Indicates whether the TPIU supports port size of 19-bit. + 18 + 18 + + + NotSupported + Port size 19 is not supported. + 0x0 + + + Supported + Port size 19 is supported. + 0x1 + + + + + PORT_SIZE_20 + Indicates whether the TPIU supports port size of 20-bit. + 19 + 19 + + + NotSupported + Port size 20 is not supported. + 0x0 + + + Supported + Port size 20 is supported. + 0x1 + + + + + PORT_SIZE_21 + Indicates whether the TPIU supports port size of 21-bit. + 20 + 20 + + + NotSupported + Port size 21 is not supported. + 0x0 + + + Supported + Port size 21 is supported. + 0x1 + + + + + PORT_SIZE_22 + Indicates whether the TPIU supports port size of 22-bit. + 21 + 21 + + + NotSupported + Port size 22 is not supported. + 0x0 + + + Supported + Port size 22 is supported. + 0x1 + + + + + PORT_SIZE_23 + Indicates whether the TPIU supports port size of 23-bit. + 22 + 22 + + + NotSupported + Port size 23 is not supported. + 0x0 + + + Supported + Port size 23 is supported. + 0x1 + + + + + PORT_SIZE_24 + Indicates whether the TPIU supports port size of 24-bit. + 23 + 23 + + + NotSupported + Port size 24 is not supported. + 0x0 + + + Supported + Port size 24 is supported. + 0x1 + + + + + PORT_SIZE_25 + Indicates whether the TPIU supports port size of 25-bit. + 24 + 24 + + + NotSupported + Port size 25 is not supported. + 0x0 + + + Supported + Port size 25 is supported. + 0x1 + + + + + PORT_SIZE_26 + Indicates whether the TPIU supports port size of 26-bit. + 25 + 25 + + + NotSupported + Port size 26 is not supported. + 0x0 + + + Supported + Port size 26 is supported. + 0x1 + + + + + PORT_SIZE_27 + Indicates whether the TPIU supports port size of 27-bit. + 26 + 26 + + + NotSupported + Port size 27 is not supported. + 0x0 + + + Supported + Port size 27 is supported. + 0x1 + + + + + PORT_SIZE_28 + Indicates whether the TPIU supports port size of 28-bit. + 27 + 27 + + + NotSupported + Port size 28 is not supported. + 0x0 + + + Supported + Port size 28 is supported. + 0x1 + + + + + PORT_SIZE_29 + Indicates whether the TPIU supports port size of 29-bit. + 28 + 28 + + + NotSupported + Port size 29 is not supported. + 0x0 + + + Supported + Port size 29 is supported. + 0x1 + + + + + PORT_SIZE_30 + Indicates whether the TPIU supports port size of 30-bit. + 29 + 29 + + + NotSupported + Port size 30 is not supported. + 0x0 + + + Supported + Port size 30 is supported. + 0x1 + + + + + PORT_SIZE_31 + Indicates whether the TPIU supports port size of 31-bit. + 30 + 30 + + + NotSupported + Port size 31 is not supported. + 0x0 + + + Supported + Port size 31 is supported. + 0x1 + + + + + PORT_SIZE_32 + Indicates whether the TPIU supports port size of 32-bit. + 31 + 31 + + + NotSupported + Port size 32 is not supported. + 0x0 + + + Supported + Port size 32 is supported. + 0x1 + + + + + + + CURRENTPORTSIZE + Each bit location is a single port size. One bit can be set, and indicates the current port size. + 0x004 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates which port size is currently selected. + 0 + 0 + + + NotSelected + Port size 1 is not selected. + 0x0 + + + Selected + Port size 1 is selected. + 0x1 + + + + + PORT_SIZE_2 + Indicates which port size is currently selected. + 1 + 1 + + + NotSelected + Port size 2 is not selected. + 0x0 + + + Selected + Port size 2 is selected. + 0x1 + + + + + PORT_SIZE_3 + Indicates which port size is currently selected. + 2 + 2 + + + NotSelected + Port size 3 is not selected. + 0x0 + + + Selected + Port size 3 is selected. + 0x1 + + + + + PORT_SIZE_4 + Indicates which port size is currently selected. + 3 + 3 + + + NotSelected + Port size 4 is not selected. + 0x0 + + + Selected + Port size 4 is selected. + 0x1 + + + + + PORT_SIZE_5 + Indicates which port size is currently selected. + 4 + 4 + + + NotSelected + Port size 5 is not selected. + 0x0 + + + Selected + Port size 5 is selected. + 0x1 + + + + + PORT_SIZE_6 + Indicates which port size is currently selected. + 5 + 5 + + + NotSelected + Port size 6 is not selected. + 0x0 + + + Selected + Port size 6 is selected. + 0x1 + + + + + PORT_SIZE_7 + Indicates which port size is currently selected. + 6 + 6 + + + NotSelected + Port size 7 is not selected. + 0x0 + + + Selected + Port size 7 is selected. + 0x1 + + + + + PORT_SIZE_8 + Indicates which port size is currently selected. + 7 + 7 + + + NotSelected + Port size 8 is not selected. + 0x0 + + + Selected + Port size 8 is selected. + 0x1 + + + + + PORT_SIZE_9 + Indicates which port size is currently selected. + 8 + 8 + + + NotSelected + Port size 9 is not selected. + 0x0 + + + Selected + Port size 9 is selected. + 0x1 + + + + + PORT_SIZE_10 + Indicates which port size is currently selected. + 9 + 9 + + + NotSelected + Port size 10 is not selected. + 0x0 + + + Selected + Port size 10 is selected. + 0x1 + + + + + PORT_SIZE_11 + Indicates which port size is currently selected. + 10 + 10 + + + NotSelected + Port size 11 is not selected. + 0x0 + + + Selected + Port size 11 is selected. + 0x1 + + + + + PORT_SIZE_12 + Indicates which port size is currently selected. + 11 + 11 + + + NotSelected + Port size 12 is not selected. + 0x0 + + + Selected + Port size 12 is selected. + 0x1 + + + + + PORT_SIZE_13 + Indicates which port size is currently selected. + 12 + 12 + + + NotSelected + Port size 13 is not selected. + 0x0 + + + Selected + Port size 13 is selected. + 0x1 + + + + + PORT_SIZE_14 + Indicates which port size is currently selected. + 13 + 13 + + + NotSelected + Port size 14 is not selected. + 0x0 + + + Selected + Port size 14 is selected. + 0x1 + + + + + PORT_SIZE_15 + Indicates which port size is currently selected. + 14 + 14 + + + NotSelected + Port size 15 is not selected. + 0x0 + + + Selected + Port size 15 is selected. + 0x1 + + + + + PORT_SIZE_16 + Indicates which port size is currently selected. + 15 + 15 + + + NotSelected + Port size 16 is not selected. + 0x0 + + + Selected + Port size 16 is selected. + 0x1 + + + + + PORT_SIZE_17 + Indicates which port size is currently selected. + 16 + 16 + + + NotSelected + Port size 17 is not selected. + 0x0 + + + Selected + Port size 17 is selected. + 0x1 + + + + + PORT_SIZE_18 + Indicates which port size is currently selected. + 17 + 17 + + + NotSelected + Port size 18 is not selected. + 0x0 + + + Selected + Port size 18 is selected. + 0x1 + + + + + PORT_SIZE_19 + Indicates which port size is currently selected. + 18 + 18 + + + NotSelected + Port size 19 is not selected. + 0x0 + + + Selected + Port size 19 is selected. + 0x1 + + + + + PORT_SIZE_20 + Indicates which port size is currently selected. + 19 + 19 + + + NotSelected + Port size 20 is not selected. + 0x0 + + + Selected + Port size 20 is selected. + 0x1 + + + + + PORT_SIZE_21 + Indicates which port size is currently selected. + 20 + 20 + + + NotSelected + Port size 21 is not selected. + 0x0 + + + Selected + Port size 21 is selected. + 0x1 + + + + + PORT_SIZE_22 + Indicates which port size is currently selected. + 21 + 21 + + + NotSelected + Port size 22 is not selected. + 0x0 + + + Selected + Port size 22 is selected. + 0x1 + + + + + PORT_SIZE_23 + Indicates which port size is currently selected. + 22 + 22 + + + NotSelected + Port size 23 is not selected. + 0x0 + + + Selected + Port size 23 is selected. + 0x1 + + + + + PORT_SIZE_24 + Indicates which port size is currently selected. + 23 + 23 + + + NotSelected + Port size 24 is not selected. + 0x0 + + + Selected + Port size 24 is selected. + 0x1 + + + + + PORT_SIZE_25 + Indicates which port size is currently selected. + 24 + 24 + + + NotSelected + Port size 25 is not selected. + 0x0 + + + Selected + Port size 25 is selected. + 0x1 + + + + + PORT_SIZE_26 + Indicates which port size is currently selected. + 25 + 25 + + + NotSelected + Port size 26 is not selected. + 0x0 + + + Selected + Port size 26 is selected. + 0x1 + + + + + PORT_SIZE_27 + Indicates which port size is currently selected. + 26 + 26 + + + NotSelected + Port size 27 is not selected. + 0x0 + + + Selected + Port size 27 is selected. + 0x1 + + + + + PORT_SIZE_28 + Indicates which port size is currently selected. + 27 + 27 + + + NotSelected + Port size 28 is not selected. + 0x0 + + + Selected + Port size 28 is selected. + 0x1 + + + + + PORT_SIZE_29 + Indicates which port size is currently selected. + 28 + 28 + + + NotSelected + Port size 29 is not selected. + 0x0 + + + Selected + Port size 29 is selected. + 0x1 + + + + + PORT_SIZE_30 + Indicates which port size is currently selected. + 29 + 29 + + + NotSelected + Port size 30 is not selected. + 0x0 + + + Selected + Port size 30 is selected. + 0x1 + + + + + PORT_SIZE_31 + Indicates which port size is currently selected. + 30 + 30 + + + NotSelected + Port size 31 is not selected. + 0x0 + + + Selected + Port size 31 is selected. + 0x1 + + + + + PORT_SIZE_32 + Indicates which port size is currently selected. + 31 + 31 + + + NotSelected + Port size 32 is not selected. + 0x0 + + + Selected + Port size 32 is selected. + 0x1 + + + + + + + SUPPORTEDTRIGGERMODES + The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. + 0x100 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Indicates whether multiplying the trigger counter by 2^(0+1) is supported. + 0 + 0 + + + NotSelected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x1 + + + + + MULT_1 + Indicates whether multiplying the trigger counter by 2^(1+1) is supported. + 1 + 1 + + + NotSelected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x1 + + + + + MULT_2 + Indicates whether multiplying the trigger counter by 2^(2+1) is supported. + 2 + 2 + + + NotSelected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x1 + + + + + MULT_3 + Indicates whether multiplying the trigger counter by 2^(3+1) is supported. + 3 + 3 + + + NotSelected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x1 + + + + + MULT_4 + Indicates whether multiplying the trigger counter by 2^(4+1) is supported. + 4 + 4 + + + NotSelected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x1 + + + + + TCOUNT8 + Indicates whether an 8-bit wide counter register is implemented. + 8 + 8 + + + NotImplemented + An 8-bit wide counter register is implemented. + 0x0 + + + Implemented + An 8-bit wide counter register is implemented. + 0x1 + + + + + TRIGGERED + A trigger has occurred and the counter has reached 0. + 16 + 16 + + + NotOccured + Trigger has not occurred. + 0x0 + + + Occured + Trigger has occurred. + 0x1 + + + + + TRGRUN + A trigger has occurred but the counter is not at 0. + 17 + 17 + + + NotOccured + Either a trigger has not occurred or the counter is at 0. + 0x0 + + + Occured + A trigger has occurred but the counter is not at 0. + 0x1 + + + + + + + TRIGGERCOUNTERVALUE + The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. + 0x104 + read-write + 0x00000000 + 0x20 + + + TrigCount + 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. + 0 + 7 + + + + + TRIGGERMULTIPLIER + The Trigger_multiplier register contains the selectors for the trigger counter multiplier. + 0x108 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Multiply the Trigger Counter by 2^n. + 0 + 0 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_1 + Multiply the Trigger Counter by 2^n. + 1 + 1 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_2 + Multiply the Trigger Counter by 2^n. + 2 + 2 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_3 + Multiply the Trigger Counter by 2^n. + 3 + 3 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_4 + Multiply the Trigger Counter by 2^n. + 4 + 4 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + + + SUPPPORTEDTESTPATTERNMODES + The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. + 0x200 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + + + CURRENTTESTPATTERNMODES + Current_test_pattern_mode indicates the current test pattern or mode selected. + 0x204 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + + + TPRCR + The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. + 0x208 + read-write + 0x00000000 + 0x20 + + + PATTCOUNT + 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. + 0 + 7 + + + + + FFSR + The FFSR register indicates the current status of the formatter and flush features available in the TPIU. + 0x300 + read-write + 0x00000000 + 0x20 + + + FLINPROG + Flush in progress. + 0 + 0 + + + NotInProgress + A flush is not in progress. + 0x0 + + + InProgress + A flush is in progress. + 0x1 + + + + + FTSTOPPED + The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. + 1 + 1 + + + Running + Formatter has not stopped. + 0x0 + + + Stopped + Formatter has stopped. + 0x1 + + + + + TCPRESENT + Indicates whether the TRACECTL pin is available for use. + 2 + 2 + + + NotPresent + TRACECTL pin is not present. + 0x0 + + + Present + TRACECTL pin is present. + 0x1 + + + + + + + FFCR + The FFCR register controls the generation of stop, trigger, and flush events. + 0x304 + read-write + 0x00000000 + 0x20 + + + ENFTC + Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. + 0 + 0 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + ENFCONT + Is embedded in trigger packets and indicates that no cycle is using sync packets. + 1 + 1 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONFLIN + Enables the use of the flushin connection. + 4 + 4 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONTRIG + Initiates a manual flush of data in the system when a trigger event occurs. + 5 + 5 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANR + Generates a flush. This bit is set to 0 when this flush is serviced. + 6 + 6 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANW + Generates a flush. This bit is set to 1 when this flush is serviced. + 7 + 7 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGIN + Indicates a trigger when trigin is asserted. + 8 + 8 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGEVT + Indicates a trigger on a trigger event. + 9 + 9 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGFL + Indicates a trigger when flush completion on afreadys is returned. + 10 + 10 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPFL + Forces the FIFO to drain off any part-completed packets. + 12 + 12 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPTRIG + Stops the formatter after a trigger event is observed. Reset to disabled or 0. + 13 + 13 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + + + FSCR + The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. + 0x308 + read-write + 0x00000000 + 0x20 + + + CYCCOUNT + 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. + 0 + 11 + + + + + EXTCTLINPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. + 0x400 + read-write + 0x00000000 + 0x20 + + + EXTCTLIN_0 + EXTCTL inputs. + 0 + 0 + + + Low + Input EXTCTL0 is low. + 0x0 + + + High + Input EXTCTL0 is high. + 0x1 + + + + + EXTCTLIN_1 + EXTCTL inputs. + 1 + 1 + + + Low + Input EXTCTL1 is low. + 0x0 + + + High + Input EXTCTL1 is high. + 0x1 + + + + + EXTCTLIN_2 + EXTCTL inputs. + 2 + 2 + + + Low + Input EXTCTL2 is low. + 0x0 + + + High + Input EXTCTL2 is high. + 0x1 + + + + + EXTCTLIN_3 + EXTCTL inputs. + 3 + 3 + + + Low + Input EXTCTL3 is low. + 0x0 + + + High + Input EXTCTL3 is high. + 0x1 + + + + + EXTCTLIN_4 + EXTCTL inputs. + 4 + 4 + + + Low + Input EXTCTL4 is low. + 0x0 + + + High + Input EXTCTL4 is high. + 0x1 + + + + + EXTCTLIN_5 + EXTCTL inputs. + 5 + 5 + + + Low + Input EXTCTL5 is low. + 0x0 + + + High + Input EXTCTL5 is high. + 0x1 + + + + + EXTCTLIN_6 + EXTCTL inputs. + 6 + 6 + + + Low + Input EXTCTL6 is low. + 0x0 + + + High + Input EXTCTL6 is high. + 0x1 + + + + + EXTCTLIN_7 + EXTCTL inputs. + 7 + 7 + + + Low + Input EXTCTL7 is low. + 0x0 + + + High + Input EXTCTL7 is high. + 0x1 + + + + + + + EXTCTLOUTPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. + 0x404 + read-write + 0x00000000 + 0x20 + + + EXTCTLOUT_0 + EXTCTL outputs. + 0 + 0 + + + Low + Output EXTCTL0 is low. + 0x0 + + + High + Output EXTCTL0 is high. + 0x1 + + + + + EXTCTLOUT_1 + EXTCTL outputs. + 1 + 1 + + + Low + Output EXTCTL1 is low. + 0x0 + + + High + Output EXTCTL1 is high. + 0x1 + + + + + EXTCTLOUT_2 + EXTCTL outputs. + 2 + 2 + + + Low + Output EXTCTL2 is low. + 0x0 + + + High + Output EXTCTL2 is high. + 0x1 + + + + + EXTCTLOUT_3 + EXTCTL outputs. + 3 + 3 + + + Low + Output EXTCTL3 is low. + 0x0 + + + High + Output EXTCTL3 is high. + 0x1 + + + + + EXTCTLOUT_4 + EXTCTL outputs. + 4 + 4 + + + Low + Output EXTCTL4 is low. + 0x0 + + + High + Output EXTCTL4 is high. + 0x1 + + + + + EXTCTLOUT_5 + EXTCTL outputs. + 5 + 5 + + + Low + Output EXTCTL5 is low. + 0x0 + + + High + Output EXTCTL5 is high. + 0x1 + + + + + EXTCTLOUT_6 + EXTCTL outputs. + 6 + 6 + + + Low + Output EXTCTL6 is low. + 0x0 + + + High + Output EXTCTL6 is high. + 0x1 + + + + + EXTCTLOUT_7 + EXTCTL outputs. + 7 + 7 + + + Low + Output EXTCTL7 is low. + 0x0 + + + High + Output EXTCTL7 is high. + 0x1 + + + + + + + ITTRFLINACK + The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + TRIGINACK + Sets the value of triginack. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHINACK + Sets the value of flushinack. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITTRFLIN + The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. + 0xEE8 + read-write + 0x00000000 + 0x20 + + + TRIGIN + Reads the value of trigin. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHIN + Reads the value of flushin. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBDATA0 + The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + Enables control of the atreadys and afvalids outputs of the TPIU. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + Sets the value of afvalid. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + Sets the value of atready. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATID + Reads the value of atids. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. + To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + Reads the value of atvalids. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + Reads the value of afreadys. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + Reads the value of atbytess. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + MUXNUM + Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. + Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. + 0 + 4 + + + CLKRELAT + Indicates the relationship between atclk and traceclkin. + 5 + 5 + + + Synchronous + atclk and traceclkin are synchronous. + 0x0 + + + ASynchronous + atclk and traceclkin are asynchronous. + 0x1 + + + + + FIFOSIZE + FIFO size in powers of 2. + 6 + 8 + + + Entries4 + FIFO size of 4 entries, that is, 16 bytes. + 0x2 + + + + + TCLKDATA + Indicates whether trace clock plus data is supported. + 9 + 9 + + + Supported + Trace clock and data is supported. + 0x0 + + + NotSupported + Trace clock and data is not supported. + 0x1 + + + + + SWOMAN + Indicates whether Serial Wire Output, Manchester encoded format, is supported. + 10 + 10 + + + NotSupported + Serial Wire Output, Manchester encoded format, is not supported. + 0x0 + + + Supported + Serial Wire Output, Manchester encoded format, is supported. + 0x1 + + + + + SWOUARTNRZ + Indicates whether Serial Wire Output, UART or NRZ, is supported. + 11 + 11 + + + NotSupported + Serial Wire Output, UART or NRZ, is not supported. + 0x0 + + + Supported + Serial Wire Output, UART or NRZ, is supported. + 0x1 + + + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace sink. + 0x1 + + + + + SUB + The sub-type of the component + 4 + 7 + + + TracePort + Indicates that this component is a trace port component. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_CTI210 + Cross-Trigger Interface control 0 + 0xBF046000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + 0x20 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0x0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 0x1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + 0x20 + + + INTACK_0 + Acknowledges the ctitrigout 0 output. + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_1 + Acknowledges the ctitrigout 1 output. + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_2 + Acknowledges the ctitrigout 2 output. + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_3 + Acknowledges the ctitrigout 3 output. + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_4 + Acknowledges the ctitrigout 4 output. + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_5 + Acknowledges the ctitrigout 5 output. + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_6 + Acknowledges the ctitrigout 6 output. + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_7 + Acknowledges the ctitrigout 7 output. + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + 0x20 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0x0 + + + Active + Application trigger 0 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 0. + 0x1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0x0 + + + Active + Application trigger 1 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 1. + 0x1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0x0 + + + Active + Application trigger 2 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 2. + 0x1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0x0 + + + Active + Application trigger 3 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 3. + 0x1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + 0x20 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 0x1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 0x1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 0x1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 0x1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + 0x20 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 0x1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 0x1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 0x1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger to Channel Enable register + 0x020 + read-write + 0x00000000 + 0x20 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 0x1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 0x1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 0x1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Channel to Trigger Enable register + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + 0x20 + + + TRIGINSTATUS_0 + Shows the status of ctitrigin0 input. + 0 + 0 + + + Active + Ctitrigin 0 is active. + 0x1 + + + Inactive + Ctitrigin 0 is inactive. + 0x0 + + + + + TRIGINSTATUS_1 + Shows the status of ctitrigin1 input. + 1 + 1 + + + Active + Ctitrigin 1 is active. + 0x1 + + + Inactive + Ctitrigin 1 is inactive. + 0x0 + + + + + TRIGINSTATUS_2 + Shows the status of ctitrigin2 input. + 2 + 2 + + + Active + Ctitrigin 2 is active. + 0x1 + + + Inactive + Ctitrigin 2 is inactive. + 0x0 + + + + + TRIGINSTATUS_3 + Shows the status of ctitrigin3 input. + 3 + 3 + + + Active + Ctitrigin 3 is active. + 0x1 + + + Inactive + Ctitrigin 3 is inactive. + 0x0 + + + + + TRIGINSTATUS_4 + Shows the status of ctitrigin4 input. + 4 + 4 + + + Active + Ctitrigin 4 is active. + 0x1 + + + Inactive + Ctitrigin 4 is inactive. + 0x0 + + + + + TRIGINSTATUS_5 + Shows the status of ctitrigin5 input. + 5 + 5 + + + Active + Ctitrigin 5 is active. + 0x1 + + + Inactive + Ctitrigin 5 is inactive. + 0x0 + + + + + TRIGINSTATUS_6 + Shows the status of ctitrigin6 input. + 6 + 6 + + + Active + Ctitrigin 6 is active. + 0x1 + + + Inactive + Ctitrigin 6 is inactive. + 0x0 + + + + + TRIGINSTATUS_7 + Shows the status of ctitrigin7 input. + 7 + 7 + + + Active + Ctitrigin 7 is active. + 0x1 + + + Inactive + Ctitrigin 7 is inactive. + 0x0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + 0x20 + + + TRIGOUTSTATUS_0 + Shows the status of ctitrigout0 output. + 0 + 0 + + + Active + Ctitrigout 0 is active. + 0x1 + + + Inactive + Ctitrigout 0 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_1 + Shows the status of ctitrigout1 output. + 1 + 1 + + + Active + Ctitrigout 1 is active. + 0x1 + + + Inactive + Ctitrigout 1 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_2 + Shows the status of ctitrigout2 output. + 2 + 2 + + + Active + Ctitrigout 2 is active. + 0x1 + + + Inactive + Ctitrigout 2 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_3 + Shows the status of ctitrigout3 output. + 3 + 3 + + + Active + Ctitrigout 3 is active. + 0x1 + + + Inactive + Ctitrigout 3 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_4 + Shows the status of ctitrigout4 output. + 4 + 4 + + + Active + Ctitrigout 4 is active. + 0x1 + + + Inactive + Ctitrigout 4 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_5 + Shows the status of ctitrigout5 output. + 5 + 5 + + + Active + Ctitrigout 5 is active. + 0x1 + + + Inactive + Ctitrigout 5 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_6 + Shows the status of ctitrigout6 output. + 6 + 6 + + + Active + Ctitrigout 6 is active. + 0x1 + + + Inactive + Ctitrigout 6 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_7 + Shows the status of ctitrigout7 output. + 7 + 7 + + + Active + Ctitrigout 7 is active. + 0x1 + + + Inactive + Ctitrigout 7 is inactive. + 0x0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + 0x20 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 0x1 + + + Inactive + Ctichin 0 is inactive. + 0x0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 0x1 + + + Inactive + Ctichin 1 is inactive. + 0x0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 0x1 + + + Inactive + Ctichin 2 is inactive. + 0x0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 0x1 + + + Inactive + Ctichin 3 is inactive. + 0x0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + 0x20 + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 0x1 + + + Disabled + Disable ctichout channel 0 propagation. + 0x0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 0x1 + + + Disabled + Disable ctichout channel 1 propagation. + 0x0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 0x1 + + + Disabled + Disable ctichout channel 2 propagation. + 0x0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 0x1 + + + Disabled + Disable ctichout channel 3 propagation. + 0x0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + 0x20 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + 0x20 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + 0x20 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 0x4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 0x1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + 0x20 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 0x4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + 0x00000000 + 0x20 + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + 0x00000000 + 0x20 + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + 0x00000000 + 0x20 + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + 0x20 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + 0x20 + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 0xD + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 0xB + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + 0x20 + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 0x3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0x0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + 0x20 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0x0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0x0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + 0x20 + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + 0x20 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0x0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 0x9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + 0x20 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + 0x20 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + GLOBAL_CTI211 + Cross-Trigger Interface control 1 + 0xBF047000 + + + + + GLOBAL_ATBREPLICATOR210 + ATB Replicator module 0 + 0xBF048000 + ATBREPLICATOR + + + + 0 + 0x1000 + registers + + ATBREPLICATOR + 0x20 + + + IDFILTER0 + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ID0_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + IDFILTER1 + The IDFILTER1 register enables the programming of ID filtering for master port 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + ID1_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATREADYM0 + Reads the value of the atreadym0 input. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYM1 + Reads the value of the atreadym1 input. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDS + Reads the value of the atvalids input. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR0 + The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + Sets the value of the atvalidm0 output. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDM1 + Sets the value of the atvalidm1 output. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYS + Sets the value of the atreadys output. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTNUM + Indicates the number of master ports implemented. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + Indicates that this component replicates trace from a single source to multiple targets. + 0x2 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBREPLICATOR211 + ATB Replicator module 1 + 0xBF049000 + + + + + GLOBAL_ATBREPLICATOR212 + ATB Replicator module 2 + 0xBF04A000 + + + + + GLOBAL_ATBREPLICATOR213 + ATB Replicator module 3 + 0xBF04B000 + + + + + GLOBAL_ATBFUNNEL210 + ATB funnel module 0 + 0xBF04C000 + ATBFUNNEL + + + + 0 + 0x1000 + registers + + ATBFUNNEL + 0x20 + + + CTRLREG + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENS_0 + Enable slave port 0. + 0 + 0 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_1 + Enable slave port 1. + 1 + 1 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_2 + Enable slave port 2. + 2 + 2 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_3 + Enable slave port 3. + 3 + 3 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_4 + Enable slave port 4. + 4 + 4 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_5 + Enable slave port 5. + 5 + 5 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_6 + Enable slave port 6. + 6 + 6 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_7 + Enable slave port 7. + 7 + 7 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + HT + Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. + When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. + The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. + The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. + 8 + 11 + + + + + PRIORITYCTRLREG + The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. + 0x004 + read-write + 0x00000000 + 0x20 + + + PRIPORT0 + Priority value of port number 0. + 0 + 2 + + + PRIPORT1 + Priority value of port number 1. + 3 + 5 + + + PRIPORT2 + Priority value of port number 2. + 6 + 8 + + + PRIPORT3 + Priority value of port number 3. + 9 + 11 + + + PRIPORT4 + Priority value of port number 4. + 12 + 14 + + + PRIPORT5 + Priority value of port number 5. + 15 + 17 + + + PRIPORT6 + Priority value of port number 6. + 18 + 20 + + + PRIPORT7 + Priority value of port number 7. + 21 + 23 + + + + + ITATBDATA0 + The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_5 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 5 + 5 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_6 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 6 + 6 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_7 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 7 + 7 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_8 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 8 + 8 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_9 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 9 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_10 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 10 + 10 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_11 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 11 + 11 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_12 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 12 + 12 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_13 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 13 + 13 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_14 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 14 + 14 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_15 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 15 + 15 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_16 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 16 + 16 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + A read access returns the value of atreadym. + A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + A read access returns the value of afvalidm. + A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. +A write outputs the value to the atidm port. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. +A write outputs the value to atvalidm. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to afreadym. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to atbytesm. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTCOUNT + Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + This component arbitrates ATB inputs mapping to ATB outputs. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBFUNNEL211 + ATB funnel module 1 + 0xBF04D000 + + + + + GLOBAL_ATBFUNNEL212 + ATB funnel module 2 + 0xBF04E000 + + + + + GLOBAL_ATBFUNNEL213 + ATB funnel module 3 + 0xBF04F000 + + + + + VPRCLIC + VPR CLIC registers + 0x5F909000 + CLIC + + 0 + 0x3000 + registers + + + VPRCLIC_0 + 0 + + + VPRCLIC_1 + 1 + + + VPRCLIC_2 + 2 + + + VPRCLIC_3 + 3 + + + VPRCLIC_4 + 4 + + + VPRCLIC_5 + 5 + + + VPRCLIC_6 + 6 + + + VPRCLIC_7 + 7 + + + VPRCLIC_8 + 8 + + + VPRCLIC_9 + 9 + + + VPRCLIC_10 + 10 + + + VPRCLIC_11 + 11 + + + VPRCLIC_12 + 12 + + + VPRCLIC_13 + 13 + + + VPRCLIC_14 + 14 + + + VPRCLIC_15 + 15 + + CLIC + 0x20 + + + CLIC + Unspecified + CLIC_CLIC + read-write + 0x000 + + CLICCFG + CLIC configuration. + 0x0000 + read-only + 0x00000011 + 0x20 + + + NVBITS + Selective interrupt hardware vectoring. + 0 + 0 + + + Implemented + Selective interrupt hardware vectoring is implemented + 0x1 + + + + + NLBITS + Interrupt level encoding. + 1 + 4 + + + Eight + 8 bits = interrupt levels encoded in eight bits + 0x8 + + + + + NMBITS + Interrupt privilege mode. + 5 + 6 + + + ModeM + All interrupts are M-mode only + 0x0 + + + + + + + CLICINFO + CLIC information. + 0x0004 + read-only + 0x00401FFF + 0x20 + + + NUMINTERRUPTS + Maximum number of interrupts supported. + 0 + 12 + + + VERSION + Version + 13 + 20 + + + NUMTRIGGER + Number of maximum interrupt triggers supported + 25 + 30 + + + + + 0x1E0 + 0x4 + CLICINT[%s] + Description collection: Interrupt control register for IRQ number [n]. + 0x1000 + read-write + 0x3FC30000 + 0x20 + + + IP + Interrupt Pending bit. + 0 + 0 + + + NotPending + Interrupt not pending + 0x0 + + + Pending + Interrupt pending + 0x1 + + + + + READ1 + Read as 0, write ignored. + 1 + 7 + read-only + + + IE + Interrupt enable bit. + 8 + 8 + + + Disabled + Interrupt disabled + 0x0 + + + Enabled + Interrupt enabled + 0x1 + + + + + READ2 + Read as 0, write ignored. + 9 + 15 + read-only + + + SHV + Selective Hardware Vectoring. + 16 + 16 + read-only + + + Vectored + Hardware vectored + 0x1 + + + + + TRIG + Trigger type and polarity for each interrupt input. + 17 + 18 + read-only + + + EdgeTriggered + Interrupts are edge-triggered + 0x1 + + + + + MODE + Privilege mode. + 22 + 23 + read-only + + + MachineMode + Machine mode + 0x3 + + + + + PRIORITY + Interrupt priority level + 24 + 31 + + + PRIOLEVEL0 + Priority level 0 + 0x3F + + + PRIOLEVEL1 + Priority level 1 + 0x7F + + + PRIOLEVEL2 + Priority level 2 + 0xBF + + + PRIOLEVEL3 + Priority level 3 + 0xFF + + + + + + + + + + VPRTIM + VTIM CSR registers + 0x00000000 + + 0 + 0x1000 + registers + + + VPRTIM + 16 + + VTIM + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + GLOBAL_GPIOTE130 + GPIO Tasks and Events 0 + 0x5F934000 + GPIOTE + + + + + 0 + 0x1000 + registers + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 4 + 0x008 + EVENTS_PORT[%s] + Peripheral events. + GLOBAL_GPIOTE_EVENTS_PORT + read-write + 0x140 + + NONSECURE + Description cluster: Non-secure port event from owner n + 0x000 + read-write + 0x00000000 + 0x20 + + + + NONSECURE + Non-secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SECURE + Description cluster: Secure port event from owner n + 0x004 + read-write + 0x00000000 + 0x20 + + + + SECURE + Secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 4 + 0x008 + PUBLISH_PORT[%s] + Publish configuration for events + GLOBAL_GPIOTE_PUBLISH_PORT + read-write + 0x1C0 + + NONSECURE + Description cluster: Publish configuration for event PORT[n].NONSECURE + 0x000 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].NONSECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SECURE + Description cluster: Publish configuration for event PORT[n].SECURE + 0x004 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].SECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + 0x20 + + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting + 0x0 + + + LowLatency + Low latency setting + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + 0x20 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 4 + 8 + + + PORT + Port number + 9 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + GLOBAL_GPIOTE131 + GPIO Tasks and Events 1 + 0x5F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GRTC + Global Real-time counter + 0x5F99C000 + + + + + 0 + 0x1000 + registers + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + GRTC + 0x20 + + + 0x10 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture the counter value to CC[n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture the counter value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTART + Start the PWM + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTART + Start the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTOP + Stop the PWM + 0x070 + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTOP + Stop the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0x164 + read-write + 0x00000000 + 0x20 + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0x168 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0x16C + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN4 + Enable or disable interrupt + 0x340 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET4 + Enable interrupt + 0x344 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR4 + Disable interrupt + 0x348 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND4 + Pending interrupts + 0x34C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN5 + Enable or disable interrupt + 0x350 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET5 + Enable interrupt + 0x354 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR5 + Disable interrupt + 0x358 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND5 + Pending interrupts + 0x35C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN6 + Enable or disable interrupt + 0x360 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET6 + Enable interrupt + 0x364 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR6 + Disable interrupt + 0x368 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND6 + Pending interrupts + 0x36C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN7 + Enable or disable interrupt + 0x370 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET7 + Enable interrupt + 0x374 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR7 + Disable interrupt + 0x378 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND7 + Pending interrupts + 0x37C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN8 + Enable or disable interrupt + 0x380 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET8 + Enable interrupt + 0x384 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR8 + Disable interrupt + 0x388 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND8 + Pending interrupts + 0x38C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN9 + Enable or disable interrupt + 0x390 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET9 + Enable interrupt + 0x394 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR9 + Disable interrupt + 0x398 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND9 + Pending interrupts + 0x39C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN10 + Enable or disable interrupt + 0x3A0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x3A4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x3A8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND10 + Pending interrupts + 0x3AC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN11 + Enable or disable interrupt + 0x3B0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET11 + Enable interrupt + 0x3B4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x3B8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND11 + Pending interrupts + 0x3BC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN12 + Enable or disable interrupt + 0x3C0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET12 + Enable interrupt + 0x3C4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR12 + Disable interrupt + 0x3C8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND12 + Pending interrupts + 0x3CC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN13 + Enable or disable interrupt + 0x3D0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET13 + Enable interrupt + 0x3D4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR13 + Disable interrupt + 0x3D8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND13 + Pending interrupts + 0x3DC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN14 + Enable or disable interrupt + 0x3E0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET14 + Enable interrupt + 0x3E4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR14 + Disable interrupt + 0x3E8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND14 + Pending interrupts + 0x3EC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN15 + Enable or disable interrupt + 0x3F0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET15 + Enable interrupt + 0x3F4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR15 + Disable interrupt + 0x3F8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND15 + Pending interrupts + 0x3FC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x400 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Enable or disable event routing for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x404 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to enable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x408 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to disable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Counter mode selection + 0x510 + read-write + 0x00000000 + 0x20 + + + AUTOEN + Automatic enable to keep the SYSCOUNTER active. + 0 + 0 + + + Default + Default configuration to keep the SYSCOUNTER active. + 0x0 + + + CpuActive + In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. + 0x1 + + + + + SYSCOUNTEREN + Enable the SYSCOUNTER + 1 + 1 + + + Disabled + SYSCOUNTER disabled + 0x0 + + + Enabled + SYSCOUNTER enabled + 0x1 + + + + + + + 16 + 0x010 + CC[%s] + Unspecified + GRTC_CC + read-write + 0x520 + + CCL + Description cluster: The lower 32-bits of Capture/Compare register CC[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CCL + Capture/Compare low value in 1 us + 0 + 31 + + + + + CCH + Description cluster: The higher 32-bits of Capture/Compare register CC[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + CCH + Capture/Compare high value in 1 us + 0 + 19 + + + + + CCADD + Description cluster: Count to add to CC[n] when this register is written. + 0x008 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[n] + 0 + 30 + + + REFERENCE + Configure the Capture/Compare register + 31 + 31 + + + SYSCOUNTER + Adds SYSCOUNTER value. + 0x0 + + + CC + Adds CC value. + 0x1 + + + + + + + CCEN + Description cluster: Configure Capture/Compare register CC[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + ACTIVE + Configure the Capture/Compare register + 0 + 0 + + + Disable + Capture/Compare register CC[n] Disabled. + 0x0 + + + Enable + Capture/Compare register CC[n] enabled. + 0x1 + + + + + + + + KEEPRUNNING + Request to keep the SYSCOUNTER in the active state and prevent going to sleep + 0x6A0 + read-write + 0x00000000 + 0x20 + + + REQUEST_0 + Request from index [0] + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_1 + Request from index [1] + 1 + 1 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_2 + Request from index [2] + 2 + 2 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_3 + Request from index [3] + 3 + 3 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_4 + Request from index [4] + 4 + 4 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_5 + Request from index [5] + 5 + 5 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_6 + Request from index [6] + 6 + 6 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_7 + Request from index [7] + 7 + 7 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_8 + Request from index [8] + 8 + 8 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_9 + Request from index [9] + 9 + 9 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_10 + Request from index [10] + 10 + 10 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_11 + Request from index [11] + 11 + 11 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_12 + Request from index [12] + 12 + 12 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_13 + Request from index [13] + 13 + 13 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_14 + Request from index [14] + 14 + 14 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_15 + Request from index [15] + 15 + 15 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + TIMEOUT + Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER + 0x6A4 + read-write + 0x00000000 + 0x20 + + + VALUE + Number of 32Ki cycles + 0 + 15 + + + + + INTERVAL + Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. + 0x6A8 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[0] + 0 + 15 + + + + + PWMCONFIG + PWM configuration. + 0x710 + read-write + 0x00000000 + 0x20 + + + COMPAREVALUE + The PWM compare value + 0 + 7 + + + + + CLKOUT + Configuration of clock output + 0x714 + read-write + 0x00000000 + 0x20 + + + CLKOUT32K + Enable 32Ki clock output on pin + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + CLKOUTFAST + Enable fast clock output on pin + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + CLKCFG + Clock Configuration + 0x718 + read-write + 0x00010001 + 0x20 + + + CLKFASTDIV + Fast clock divisor value of clock output + 0 + 7 + + + CLKSEL + GRTC LFCLK clock source selection + 16 + 17 + + + LFXO + GRTC LFCLK clock source is LFXO + 0x0 + + + SystemLFCLK + GRTC LFCLK clock source is system LFCLK + 0x1 + + + + + + + 16 + 0x010 + SYSCOUNTER[%s] + Unspecified + GRTC_SYSCOUNTER + read-write + 0x720 + + SYSCOUNTERL + Description cluster: The lower 32-bits of the SYSCOUNTER for index [n] + 0x000 + read-only + 0x00000000 + 0x20 + + + VALUE + The lower 32-bits of the SYSCOUNTER value. + 0 + 31 + + + + + SYSCOUNTERH + Description cluster: The higher 20-bits of the SYSCOUNTER for index [n] + 0x004 + read-only + 0x40000000 + 0x20 + + + VALUE + The higher 20-bits of the SYSCOUNTER value. + 0 + 19 + + + BUSY + SYSCOUNTER busy status + 30 + 30 + + + Ready + SYSCOUNTER is ready for read + 0x0 + + + Busy + SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this register is not valid) + 0x1 + + + + + OVERFLOW + The SYSCOUNTERL overflow indication after reading it. + 31 + 31 + + + NoOverflow + SYSCOUNTERL is not overflown + 0x0 + + + Overflow + SYSCOUNTERL overflown + 0x1 + + + + + + + ACTIVE + Description cluster: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] + 0x008 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Keep SYSCOUNTER in active state + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + + + + GLOBAL_TBM + Trace buffer monitor + 0xBF003000 + + + + 0 + 0x1000 + registers + + + TBM + 127 + + TBM + 0x20 + + + TASKS_START + Start counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop counter, clear counter value + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop counter, clear counter value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_HALFFULL + Counter value equals half-full + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_HALFFULL + Counter value equals half-full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FULL + Counter value equals full + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FULL + Counter value equals full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Enable or disable interrupt for event HALFFULL + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FULL + Enable or disable interrupt for event FULL + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FLUSH + Enable or disable interrupt for event FLUSH + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to enable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FULL + Write '1' to enable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FLUSH + Write '1' to enable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to disable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FULL + Write '1' to disable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FLUSH + Write '1' to disable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + HALFFULL + Read pending status of interrupt for event HALFFULL + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FULL + Read pending status of interrupt for event FULL + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FLUSH + Read pending status of interrupt for event FLUSH + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + BUFFERSIZE + System RAM trace buffer total size in bytes + 0x400 + read-write + 0x00000400 + 0x20 + + + BUFFERSIZE + Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to make + half-buffer size always 64 bit word aligned. Typical minimum BUFFERSIZE value 0x010 i.e. 16 bytes, typical + maximum value 0x1000 i.e. 4096 bytes. + 0 + 12 + + + Zero + 0 bytes + 0x0000 + + + Min + 16 bytes + 0x0010 + + + Max + 4096 bytes + 0x1000 + + + + + + + COUNT + Counter current value + 0x404 + read-write + 0x00000000 + 0x20 + + + COUNT + Counter current value. Only writable when counter is in stopped state. Writing when not in stopped + state will generate a bus fault. + 0 + 12 + + + + + COUNTSNAPSHOT + Copy of the current COUNT value + 0x408 + read-only + 0x00000000 + 0x20 + + + COUNTSNAPSHOT + TASKS_FLUSH will copy the current COUNT value to this register. + 0 + 12 + + + + + + + GLOBAL_USBHS + USBHS + 0x5F086000 + + + + 0 + 0x1000 + registers + + + USBHS + 134 + + USBHS + 0x20 + + + TASKS_START + Start the USB peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the USB peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable USB peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + CORE + Enable USB Controller + 0 + 0 + + + Disabled + USB Controller disabled. + 0x0 + + + Enabled + USB Controller enabled. + 0x1 + + + + + PHY + Enable USB PHY + 1 + 1 + + + Disabled + USB PHY disabled. + 0x0 + + + Enabled + USB PHY enabled. + 0x1 + + + + + + + + + GLOBAL_EXMIF + External Memory Interface + 0x5F095000 + + + + 0 + 0x1000 + registers + + + EXMIF + 149 + + EXMIF + 0x20 + + + TASKS_START + Start operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + LOCKEDACCESS + Enable or disable locked APB access to serial memory controller. + 0x14 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable locked APB access to SSI. + 0 + 0 + + + Disabled + Disable locked APB access. + 0x0 + + + Enabled + Enable locked APB access. + 0x1 + + + + + + + RESET + Reset the external memory. + 0x1C + read-write + 0x00000000 + 0x20 + + + RESET + 0 + 0 + + + Clear + Reset is cleared. + 0x0 + + + Set + Reset is set. + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EXTCONF1 + Configuration for external memory device 1. + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 1. + 0x0 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 1. + 0x4 + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x10 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + EXTCONF2 + Configuration for external memory device 2. + EXTCONF2 + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 2. + 0x8 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 2. + 0xC + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x20 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + CORE + Unspecified + GLOBAL_EXMIF_CORE + read-write + 0x500 + + SSICADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICADDRESS + read-write + 0x000 + + CTRLR0 + This register controls the serial data transfer. + 0x000 + read-write + 0x00004007 + 0x20 + + + DFS + Data Frame Size. + 0 + 4 + + + DFS_01_BIT + Unspecified + 0x00 + + + DFS_02_BIT + Unspecified + 0x01 + + + DFS_03_BIT + Unspecified + 0x02 + + + DFS_04_BIT + Unspecified + 0x03 + + + DFS_05_BIT + Unspecified + 0x04 + + + DFS_06_BIT + Unspecified + 0x05 + + + DFS_07_BIT + Unspecified + 0x06 + + + DFS_08_BIT + Unspecified + 0x07 + + + DFS_09_BIT + Unspecified + 0x08 + + + DFS_10_BIT + Unspecified + 0x09 + + + DFS_11_BIT + Unspecified + 0x0A + + + DFS_12_BIT + Unspecified + 0x0B + + + DFS_13_BIT + Unspecified + 0x0C + + + DFS_14_BIT + Unspecified + 0x0D + + + DFS_15_BIT + Unspecified + 0x0E + + + DFS_16_BIT + Unspecified + 0x0F + + + DFS_17_BIT + Unspecified + 0x10 + + + DFS_18_BIT + Unspecified + 0x11 + + + DFS_19_BIT + Unspecified + 0x12 + + + DFS_20_BIT + Unspecified + 0x13 + + + DFS_21_BIT + Unspecified + 0x14 + + + DFS_22_BIT + Unspecified + 0x15 + + + DFS_23_BIT + Unspecified + 0x16 + + + DFS_24_BIT + Unspecified + 0x17 + + + DFS_25_BIT + Unspecified + 0x18 + + + DFS_26_BIT + Unspecified + 0x19 + + + DFS_27_BIT + Unspecified + 0x1A + + + DFS_28_BIT + Unspecified + 0x1B + + + DFS_29_BIT + Unspecified + 0x1C + + + DFS_30_BIT + Unspecified + 0x1D + + + DFS_31_BIT + Unspecified + 0x1E + + + DFS_32_BIT + Unspecified + 0x1F + + + + + FRF + Frame Format. + 6 + 7 + + + SPI + Unspecified + 0x0 + + + SSP + Unspecified + 0x1 + + + MICROWIRE + Unspecified + 0x2 + + + + + SCPH + Serial Clock Phase. + 8 + 8 + + + MIDDLE_BIT + Unspecified + 0x0 + + + START_BIT + Unspecified + 0x1 + + + + + SCPOL + Serial Clock Polarity. + 9 + 9 + + + INACTIVE_HIGH + Unspecified + 0x0 + + + INACTIVE_LOW + Unspecified + 0x1 + + + + + TMOD + Transfer Mode. + 10 + 11 + + + TX_AND_RX + Unspecified + 0x0 + + + TX_ONLY + Unspecified + 0x1 + + + RX_ONLY + Unspecified + 0x2 + + + EEPROM_READ + Unspecified + 0x3 + + + + + SLVOE + Slave Output Enable. + 12 + 12 + + + ENABLED + Unspecified + 0x0 + + + DISABLED + Unspecified + 0x1 + + + + + SRL + Shift Register Loop. + 13 + 13 + + + NORMAL_MODE + Unspecified + 0x0 + + + TESTING_MODE + Unspecified + 0x1 + + + + + SSTE + Slave Select Toggle Enable. + 14 + 14 + + + TOGGLE_DISABLE + Unspecified + 0x0 + + + TOGGLE_EN + Unspecified + 0x1 + + + + + CFS + Control Frame Size. + 16 + 19 + + + SIZE_01_BIT + Unspecified + 0x0 + + + SIZE_02_BIT + Unspecified + 0x1 + + + SIZE_03_BIT + Unspecified + 0x2 + + + SIZE_04_BIT + Unspecified + 0x3 + + + SIZE_05_BIT + Unspecified + 0x4 + + + SIZE_06_BIT + Unspecified + 0x5 + + + SIZE_07_BIT + Unspecified + 0x6 + + + SIZE_08_BIT + Unspecified + 0x7 + + + SIZE_09_BIT + Unspecified + 0x8 + + + SIZE_10_BIT + Unspecified + 0x9 + + + SIZE_11_BIT + Unspecified + 0xA + + + SIZE_12_BIT + Unspecified + 0xB + + + SIZE_13_BIT + Unspecified + 0xC + + + SIZE_14_BIT + Unspecified + 0xD + + + SIZE_15_BIT + Unspecified + 0xE + + + SIZE_16_BIT + Unspecified + 0xF + + + + + SPIFRF + SPI Frame Format + 22 + 23 + + + SPI_STANDARD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + SPIHYPERBUSEN + SPI Hyperbus Frame format enable. + 24 + 24 + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SPIDWSEN + Enable Dynamic wait states in SPI mode of operation. + 25 + 25 + read-only + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SSIISMST + This field selects if DWC_ssi is working in Master or Slave mode + 31 + 31 + read-only + + + SLAVE + Unspecified + 0x0 + + + MASTER + Unspecified + 0x1 + + + + + + + CTRLR1 + This register exists only when the DWC_ssi is configured as a master device. + 0x004 + read-write + 0x00000000 + 0x20 + + + NDF + Number of Data Frames. + 0 + 15 + + + + + SSIENR + This register enables and disables the DWC_ssi. + 0x008 + read-write + 0x00000000 + 0x20 + + + SSICEN + SSI Enable. + 0 + 0 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MWCR + This register controls the direction of the data word for the half-duplex Microwire serial protocol. + 0x00C + read-write + 0x00000000 + 0x20 + + + MWMOD + Microwire Transfer Mode. + 0 + 0 + + + NON_SEQUENTIAL + Unspecified + 0x0 + + + SEQUENTIAL + Unspecified + 0x1 + + + + + MDD + Microwire Control. + 1 + 1 + + + RECEIVE + Unspecified + 0x0 + + + TRANSMIT + Unspecified + 0x1 + + + + + MHS + Microwire Handshaking. + 2 + 2 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SER + This register is valid only when the DWC_ssi is configured as a master device. + 0x010 + read-write + 0x00000000 + 0x20 + + + SER + Slave Select Enable Flag. + 0 + 1 + + + NOTSELECTED + Unspecified + 0x0 + + + SELECTED + Unspecified + 0x1 + + + + + + + BAUDR + This register is valid only when the DWC_ssi is configured as a master device. + 0x014 + read-write + 0x00000000 + 0x20 + + + SCKDV + SSI Clock Divider. + 1 + 15 + + + + + TXFTLR + This register controls the threshold value for the transmit FIFO memory.. + 0x018 + read-write + 0x00000000 + 0x20 + + + TFT + Transmit FIFO Threshold. + 0 + 4 + + + TXFTHR + Transfer start FIFO level. + 16 + 20 + + + + + RXFTLR + This register controls the threshold value for the receive FIFO memory.. + 0x01C + read-write + 0x00000000 + 0x20 + + + RFT + Receive FIFO Threshold. + 0 + 4 + + + + + TXFLR + This register contains the number of valid data entries in the transmit FIFO memory. + 0x020 + read-write + 0x00000000 + 0x20 + + + TXTFL + Transmit FIFO Level. + 0 + 5 + read-only + + + + + RXFLR + This register contains the number of valid data entries in the receive FIFO memory. + 0x024 + read-write + 0x00000000 + 0x20 + + + RXTFL + Receive FIFO Level. + 0 + 5 + read-only + + + + + SR + This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. + 0x028 + read-write + 0x00000006 + 0x20 + + + BUSY + SSI Busy Flag. + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TFNF + Transmit FIFO Not Full. + 1 + 1 + read-only + + + FULL + Unspecified + 0x0 + + + NOT_FULL + Unspecified + 0x1 + + + + + TFE + Transmit FIFO Empty. + 2 + 2 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + RFNE + Receive FIFO Not Empty. + 3 + 3 + read-only + + + EMPTY + Unspecified + 0x0 + + + NOT_EMPTY + Unspecified + 0x1 + + + + + RFF + Receive FIFO Full. + 4 + 4 + read-only + + + NOT_FULL + Unspecified + 0x0 + + + FULL + Unspecified + 0x1 + + + + + TXE + Transmission Error. + 5 + 5 + read-only + + + NO_ERROR + Unspecified + 0x0 + + + TX_ERROR + Unspecified + 0x1 + + + + + DCOL + Data Collision Error. + 6 + 6 + read-only + + + NO_ERROR_CONDITION + Unspecified + 0x0 + + + TX_COLLISION_ERROR + Unspecified + 0x1 + + + + + + + IMR + This read/write register masks or enables all interrupts generated by the DWC_ssi. + 0x02C + read-write + 0x000000FF + 0x20 + + + TXEIM + Transmit FIFO Empty Interrupt Mask + 0 + 0 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXOIM + Transmit FIFO Overflow Interrupt Mask + 1 + 1 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXUIM + Receive FIFO Underflow Interrupt Mask + 2 + 2 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXOIM + Receive FIFO Overflow Interrupt Mask + 3 + 3 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXFIM + Receive FIFO Full Interrupt Mask + 4 + 4 + + + MASKED + ssi_rxf_intr interrupt is masked + 0x0 + + + UNMASKED + ssi_rxf_intr interrupt is not masked + 0x1 + + + + + MSTIM + Multi-Master Contention Interrupt Mask. + 5 + 5 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + XRXOIM + XIP Receive FIFO Overflow Interrupt Mask + 6 + 6 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXUIM + Transmit FIFO Underflow Interrupt Mask + 7 + 7 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + DONEM + SSI Done Interrupt Mask + 11 + 11 + read-only + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + + + ISR + This register reports the status of the DWC_ssi interrupts after they have been masked. + 0x030 + read-write + 0x00000000 + 0x20 + + + TXEIS + Transmit FIFO Empty Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIS + Transmit FIFO Overflow Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIS + Receive FIFO Underflow Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIS + Receive FIFO Overflow Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIS + Receive FIFO Full Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIS + Multi-Master Contention Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIS + XIP Receive FIFO Overflow Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIS + Transmit FIFO Underflow Interrupt Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONES + SSI Done Interrupt Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RISR + Raw Interrupt Status Register + 0x034 + read-write + 0x00000000 + 0x20 + + + TXEIR + Transmit FIFO Empty Raw Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIR + Transmit FIFO Overflow Raw Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIR + Receive FIFO Underflow Raw Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIR + Receive FIFO Overflow Raw Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIR + Receive FIFO Full Raw Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIR + Multi-Master Contention Raw Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIR + XIP Receive FIFO Overflow Raw Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIR + Transmit FIFO Underflow Interrupt Raw Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONER + SSI Done Interrupt Raw Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + TXEICR + Transmit FIFO Error Interrupt Clear Register + 0x038 + read-write + 0x00000000 + 0x20 + + + TXEICR + Clear Transmit FIFO Overflow/Underflow Interrupt. + 0 + 0 + read-only + + + + + RXOICR + Receive FIFO Overflow Interrupt Clear Register + 0x03C + read-write + 0x00000000 + 0x20 + + + RXOICR + Clear Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + RXUICR + Receive FIFO Underflow Interrupt Clear Register + 0x040 + read-write + 0x00000000 + 0x20 + + + RXUICR + Clear Receive FIFO Underflow Interrupt. + 0 + 0 + read-only + + + + + MSTICR + Multi-Master Interrupt Clear Register + 0x044 + read-write + 0x00000000 + 0x20 + + + MSTICR + Clear Multi-Master Contention Interrupt. + 0 + 0 + read-only + + + + + ICR + Interrupt Clear Register + 0x048 + read-write + 0x00000000 + 0x20 + + + ICR + Clear Interrupts. + 0 + 0 + read-only + + + + + IDR + This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. + 0x058 + read-write + 0x00010003 + 0x20 + + + IDCODE + Identification code. + 0 + 31 + read-only + + + + + SSICVERSIONID + This read-only register stores the specific DWC_ssi component version. + 0x05C + read-write + 0x3130332A + 0x20 + + + SSICCOMPVERSION + Contains the hex representation of the Synopsys component version. + 0 + 31 + read-only + + + + + 0x24 + 0x4 + DR[%s] + Description collection: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. + 0x060 + read-write + 0x00000000 + 0x20 + + + DR + Data Register. + 0 + 31 + + + + + RXSAMPLEDELAY + This register is only valid when the DWC_ssi is configured with rxd sample delay logic (SSIC_HAS_RX_SAMPLE_DELAY==1). + 0x0F0 + read-write + 0x00000000 + 0x20 + + + RSD + Receive Data (rxd) Sample Delay. + 0 + 7 + + + SE + Receive Data (rxd) Sampling Edge. + 16 + 16 + + + + + SPICTRLR0 + This register is used to control the serial data transfer in enhanced SPI mode of operation. + 0x0F4 + read-write + 0x00000A00 + 0x20 + + + TRANSTYPE + Address and instruction transfer format. + 0 + 1 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 2 + 5 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + XIPMDBITEN + Mode bits enable in XIP mode. + 7 + 7 + read-only + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 11 + 15 + + + SPIDDREN + SPI DDR Enable bit. + 16 + 16 + + + INSTDDREN + Instruction DDR Enable bit. + 17 + 17 + + + SPIRXDSEN + Read data strobe enable bit. + 18 + 18 + + + XIPDFSHC + Fix DFS for XIP transfers. + 19 + 19 + read-only + + + XIPINSTEN + XIP instruction enable bit. + 20 + 20 + read-only + + + SSICXIPCONTXFEREN + Enable continuous transfer in XIP mode. + 21 + 21 + read-only + + + SPIDMEN + SPI data mask enable bit. + 24 + 24 + + + SPIRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + read-only + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + read-only + + + CLKSTRETCHEN + Enables clock stretching capability in SPI transfers. + 30 + 30 + + + + + DDRDRIVEEDGE + This Register is valid only when SSIC_HAS_DDR is equal to 1. + 0x0F8 + read-write + 0x00000000 + 0x20 + + + TDE + TXD Drive edge register which decided the driving edge of transmit data. + 0 + 7 + + + + + XIPMODEBITS + This register carries the mode bits which are sent in the XIP mode of operation after address phase. + 0x0FC + read-write + 0x00000000 + 0x20 + + + XIPMDBITS + XIP mode bits to be sent after address phase of XIP transfer. + 0 + 15 + + + + + + SSICXIPADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICXIPADDRESS + read-write + 0x100 + + XIPINCRINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x000 + read-write + 0x00000000 + 0x20 + + + INCRINST + XIP INCR transfer opcode. + 0 + 15 + + + + + XIPWRAPINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + WRAPINST + XIP WRAP transfer opcode. + 0 + 15 + + + + + XIPCTRL + This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. + 0x008 + read-write + 0x08000401 + 0x20 + + + FRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + TRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 9 + 10 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + MDBITSEN + Mode bits enable in XIP mode. + 12 + 12 + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 13 + 17 + + + DFSHC + Fix DFS for XIP transfers. + 18 + 18 + + + DDREN + SPI DDR Enable bit. + 19 + 19 + + + INSTDDREN + Instruction DDR Enable bit. + 20 + 20 + + + RXDSEN + Read data strobe enable bit. + 21 + 21 + + + INSTEN + XIP instruction enable bit. + 22 + 22 + + + CONTXFEREN + Enable continuous transfer in XIP mode. + 23 + 23 + read-only + + + XIPHYPERBUSEN + SPI Hyperbus Frame format enable for XIP transfers. + 24 + 24 + + + RXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + + + + + XRXOICR + XIP Receive FIFO Overflow Interrupt Clear Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XRXOICR + Clear XIP Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + XIPWRITEINCRINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x040 + read-write + 0x00000000 + 0x20 + + + INCRWRITEINST + XIP Write INCR transfer opcode. + 0 + 15 + + + RSVDINCRINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITEWRAPINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x044 + read-write + 0x00000000 + 0x20 + + + WRAPWRITEINST + XIP Write WRAP transfer opcode. + 0 + 15 + + + RSVDWRAPINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITECTRL + This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. + 0x048 + read-write + 0x00000002 + 0x20 + + + WRFRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + WRTRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + WRADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + + + WRINSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WRSPIDDREN + SPI DDR Enable bit. + 10 + 10 + + + WRINSTDDREN + Instruction DDR Enable bit. + 11 + 11 + + + XIPWRHYPERBUSEN + SPI Hyperbus Frame format enable for XIP Write transfers. + 12 + 12 + + + XIPWRRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 13 + 13 + + + RSVDXIPWRITECTRL14TO15 + Reserved bits - Read Only + 14 + 15 + read-only + + + XIPWRWAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 16 + 20 + + + RSVDXIPWRITECTRL21TO31 + Reserved bits - Read Only + 21 + 31 + read-only + + + + + + + + + GLOBAL_SECDOMBELLBOARD + BELLBOARD public registers + 0x5F099000 + BELLBOARDPUBLIC + + + + + 0 + 0x1000 + registers + + BELLBOARDPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_VPR120 + VPR peripheral registers + 0x5F8C8000 + VPRPUBLIC + + + + 0 + 0x1000 + registers + + VPRPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_IPCT120 + IPCT APB registers 0 + 0x5F8D1000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT120_0 + 209 + + IPCT + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE4_FLUSH4 + Shortcut between event RECEIVE[4] and task FLUSH[4] + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE5_FLUSH5 + Shortcut between event RECEIVE[5] and task FLUSH[5] + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE6_FLUSH6 + Shortcut between event RECEIVE[6] and task FLUSH[6] + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE7_FLUSH7 + Shortcut between event RECEIVE[7] and task FLUSH[7] + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + GLOBAL_IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_4 + Overflow status for SEND[4] task + 4 + 4 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_5 + Overflow status for SEND[5] task + 5 + 5 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_6 + Overflow status for SEND[6] task + 6 + 6 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_7 + Overflow status for SEND[7] task + 7 + 7 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + GLOBAL_MUTEX120 + MUTEX 0 + 0x4F8D2000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x20 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + 0x00000000 + 0x20 + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0x0 + + + Locked + Mutex n is in locked state + 0x1 + + + + + + + + + GLOBAL_I3C120 + I3C 0 + 0x5F8D3000 + I3C + + + + 0 + 0x1000 + registers + + + I3C120 + 211 + + I3C + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable I3C peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + EN + Enable + 0 + 0 + + + Disabled + I3C peripheral disabled. + 0x0 + + + Enabled + I3C peripheral enabled. + 0x1 + + + + + + + CDR + Unspecified + I3C_CDR + read-write + 0x404 + + STARTOFFSET + Start offset of recovered clock + 0x000 + read-write + 0x00000004 + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXCYCLERATIO + Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock + 0x004 + read-write + 0x0000001C + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXSKEW + Maximum skew between SCL and SCL in CDR clock cycles + 0x008 + read-write + 0x00000005 + 0x20 + + + VAL + Value + 0 + 7 + + + + + + SLAVEIF0 + I3C slave interface 0 + 0x410 + read-write + 0x00000000 + 0x20 + + + MODEI2C + I2C or I3C mode select signal + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + ACTMODE + Slave activity mode for GETSTATUS CCC + 1 + 2 + + + PENDINGINT + Pending interrupt information for GETSTATUS CCC + 3 + 6 + + + STATICADDREN + Slave static address valid + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + STATICADDR + Slave static address + 8 + 14 + + + SLAVEMAXRDSPEED + Slave maximum read data rate + 15 + 17 + + + SLAVEMAXWRSPEED + Slave maximum write write rate + 18 + 20 + + + SLAVECLKDATATURNTIME + Slave maximum clock data turnaround time + 21 + 23 + + + SLAVEDCR + Device Characteristic Register value + 24 + 31 + + + + + SLAVEIF1 + I3C slave interface 1 + 0x414 + read-write + 0x00000000 + 0x20 + + + WAKEUP + Slave wakeup signal + 0 + 0 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SLAVEPID0 + Slave Device Provisioned ID 0 + 0x418 + read-write + 0x00000000 + 0x20 + + + ADDMEANING + Additional Meaning + 0 + 11 + + + INSTANCEID + Instance ID + 12 + 15 + + + PARTID + Part ID + 16 + 31 + + + + + SLAVEPID1 + Slave Device Provisioned ID 1 + 0x41C + read-write + 0x00000000 + 0x20 + + + PROVID + Provisional ID Type Selector + 0 + 0 + + + MIPIMID + MIPI Manufacturer ID + 1 + 15 + + + + + KEEPSDA + Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x420 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SDA high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + KEEPSCL + Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x424 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SCL high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + + + GLOBAL_VPR121 + VPR peripheral registers 0 + 0x5F8D4000 + VPR + + + + 0 + 0x1000 + registers + + + VPR121 + 212 + + VPR + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TASKS_TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + EN + Subscription enable bit + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: VPR event [n] register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + VPR event [n] register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event EVENTS_TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + EN + Publication enable bit + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + DEBUGIF + Unspecified + VPR_DEBUGIF + read-write + 0x400 + + DATA0 + Abstract Data 0. Read/write data for argument 0 + 0x10 + read-write + 0x00000000 + 0x20 + + + DATA0 + Abstract Data 0 + 0 + 31 + + + + + DATA1 + Abstract Data 1. Read/write data for argument 1 + 0x14 + read-write + 0x00000000 + 0x20 + + + DATA1 + Abstract Data 1 + 0 + 31 + + + + + DMCONTROL + Debug Module Control + 0x40 + read-write + 0x00000000 + 0x20 + + + DMACTIVE + Reset signal for the debug module. + 0 + 0 + + + Disabled + Reset the debug module itself + 0x0 + + + Enabled + Normal operation + 0x1 + + + + + NDMRESET + Reset signal output from the debug module to the system. + 1 + 1 + + + Inactive + Reset inactive + 0x0 + + + Active + Reset active + 0x1 + + + + + CLRRESETHALTREQ + Clear the halt on reset request. + 2 + 2 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the halt on reset request + 0x1 + + + + + SETRESETHALTREQ + Set the halt on reset request. + 3 + 3 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Sets the halt on reset request + 0x1 + + + + + HARTSELHI + The high 10 bits of hartsel. + 6 + 15 + write-only + + + HARTSELLO + The low 10 bits of hartsel. + 16 + 25 + write-only + + + HASEL + Definition of currently selected harts. + 26 + 26 + write-only + + + Single + Single hart selected. + 0x0 + + + Multiple + Multiple harts selected + 0x1 + + + + + ACKHAVERESET + Clear the havereset. + 28 + 28 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the havereset for selected harts. + 0x1 + + + + + HARTRESET + Reset harts. + 29 + 29 + + + Deasserted + Reset de-asserted. + 0x0 + + + Asserted + Reset asserted. + 0x1 + + + + + RESUMEREQ + Resume currently selected harts. + 30 + 30 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Resumed + Currently selected harts resumed. + 0x1 + + + + + HALTREQ + Halt currently selected harts. + 31 + 31 + write-only + + + Clear + Clears halt request bit for all currently selected harts. + 0x0 + + + Halt + Currently selected harts halted. + 0x1 + + + + + + + DMSTATUS + Debug Module Status + 0x44 + read-only + 0x00400082 + 0x20 + + + VERSION + Version of the debug module. + 0 + 3 + + + NotPresent + Debug module not present. + 0x0 + + + V011 + There is a Debug Module and it conforms to version 0.11 of this specifcation. + 0x1 + + + V013 + There is a Debug Module and it conforms to version 0.13 of this specifcation. + 0x2 + + + NonConform + There is a Debug Module but it does not conform to any available version of the spec. + 0xF + + + + + CONFSTRPTRVALID + Configuration string. + 4 + 4 + + + NotRelevant + The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. + 0x0 + + + Address + The confstrptr0..confstrptr3 holds the address of the configuration string. + 0x1 + + + + + HASRESETHALTREQ + Halt-on-reset support status. + 5 + 5 + + + No + Halt-on-reset is supported. + 0x0 + + + Yes + Halt-on-reset is not supported. + 0x1 + + + + + AUTHBUSY + Authentication busy status. + 6 + 6 + + + No + The authentication module is ready. + 0x0 + + + Yes + The authentication module is busy. + 0x1 + + + + + AUTHENTICATED + Authentication status. + 7 + 7 + + + No + Authentication required before using the debug module. + 0x0 + + + Yes + Authentication passed. + 0x1 + + + + + ANYHALTED + Any currently selected harts halted status. + 8 + 8 + + + No + None of the currently selected harts halted. + 0x0 + + + Yes + Any of the currently selected harts halted. + 0x1 + + + + + ALLHALTED + All currently selected harts halted status. + 9 + 9 + + + No + Not all of the currently selected harts halted. + 0x0 + + + Yes + All of the currently selected harts halted. + 0x1 + + + + + ANYRUNNING + Any currently selected harts running status. + 10 + 10 + + + No + None of the currently selected harts running. + 0x0 + + + Yes + Any of the currently selected harts running. + 0x1 + + + + + ALLRUNNING + All currently selected harts running status. + 11 + 11 + + + No + Not all of the currently selected harts running. + 0x0 + + + Yes + All of the currently selected harts running. + 0x1 + + + + + ANYUNAVAIL + Any currently selected harts unavailable status. + 12 + 12 + + + No + None of the currently selected harts unavailable. + 0x0 + + + Yes + Any of the currently selected harts unavailable. + 0x1 + + + + + ALLUNAVAIL + All currently selected harts unavailable status. + 13 + 13 + + + No + Not all of the currently selected harts unavailable. + 0x0 + + + Yes + All of the currently selected harts unavailable. + 0x1 + + + + + ANYNONEXISTENT + Any currently selected harts nonexistent status. + 14 + 14 + + + No + None of the currently selected harts nonexistent. + 0x0 + + + Yes + Any of the currently selected harts nonexistent. + 0x1 + + + + + ALLNONEXISTENT + All currently selected harts nonexistent status. + 15 + 15 + + + No + Not all of the currently selected harts nonexistent. + 0x0 + + + Yes + All of the currently selected harts nonexistent. + 0x1 + + + + + ANYRESUMEACK + Any currently selected harts acknowledged last resume request. + 16 + 16 + + + No + None of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + Any of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ALLRESUMEACK + All currently selected harts acknowledged last resume + 17 + 17 + + + No + Not all of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + All of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ANYHAVERESET + Any currently selected harts have been reset and reset is not acknowledged. + 18 + 18 + + + No + None of the currently selected harts have been reset and reset is not acknowledget. + 0x0 + + + Yes + Any of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + ALLHAVERESET + All currently selected harts have been reset and reset is not acknowledge + 19 + 19 + + + No + Not all of the currently selected harts have been reset and reset is not acknowledge. + 0x0 + + + Yes + All of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + IMPEBREAK + Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. + 22 + 22 + + + No + No implicit ebreak instruction. + 0x0 + + + Yes + Implicit ebreak instruction. + 0x1 + + + + + + + HARTINFO + Hart Information + 0x48 + read-write + 0x00000000 + 0x20 + + + DATAADDR + Data Address + 0 + 11 + read-only + + + DATASIZE + Data Size + 12 + 15 + read-only + + + DATAACCESS + Data Access + 16 + 16 + read-only + + + No + The data registers are shadowed in the hart + by CSRs. Each CSR is DXLEN bits in size, and + corresponds to a single argument. + 0x0 + + + Yes + The data registers are shadowed in the hart's + memory map. Each register takes up 4 bytes in + the memory map. + 0x1 + + + + + NSCRATCH + Number of dscratch registers + 20 + 23 + read-only + + + + + HALTSUM1 + Halt Summary 1 + 0x4C + read-write + 0x00000000 + 0x20 + + + HALTSUM1 + Halt Summary 1 + 0 + 31 + read-only + + + + + HAWINDOWSEL + Hart Array Window Select + 0x50 + read-write + 0x00000000 + 0x20 + + + HAWINDOWSEL + The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. + 0 + 14 + read-only + + + + + HAWINDOW + Hart Array Window + 0x54 + read-write + 0x00000000 + 0x20 + + + MASKDATA + Mask data. + 0 + 31 + + + + + ABSTRACTCS + Abstract Control and Status + 0x58 + read-write + 0x01000002 + 0x20 + + + DATACOUNT + Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. + 0 + 3 + read-only + + + CMDERR + Command error when the abstract command fails. + 8 + 10 + + + NoError + No error. + 0x0 + + + Busy + An abstract command was executing while command, + abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read + or written. This status is only written if cmderr contains 0 + 0x1 + + + NotSupported + The requested command is notsupported, + regardless of whether the hart is running or not. + 0x2 + + + Exception + An exception occurred while executing the + command (e.g. while executing theProgram Buffer). + 0x3 + + + HaltResume + The abstract command couldn't execute + because the hart wasn't in the required state (running/halted). or unavailable. + 0x4 + + + Bus + The abstract command failed due to abus + error (e.g. alignment, access size, or timeout). + 0x5 + + + Other + The command failed for another reason. + 0x7 + + + + + BUSY + Abstract command execution status. + 12 + 12 + read-only + + + NotBusy + Not busy. + 0x0 + + + Busy + An abstract command is currently being executed. + This bit is set as soon as command is written, and is not cleared until that command has completed. + 0x1 + + + + + PROGBUFSIZE + Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. + 24 + 28 + read-only + + + + + ABSTRACTCMD + Abstract command + 0x5C + write-only + 0x00000000 + 0x20 + + + CONTROL + This Field is interpreted in a command specific manner, described for each abstract command. + 0 + 23 + + + CMDTYPE + The type determines the overall functionality of this abstract command. + 24 + 31 + + + REGACCESS + Register Access Command + 0x00 + + + QUICKACCESS + Quick Access Command + 0x01 + + + MEMACCESS + Memory Access Command + 0x02 + + + + + + + ABSTRACTAUTO + Abstract Command Autoexec + 0x60 + read-write + 0x00000000 + 0x20 + + + AUTOEXECDATA + When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. + 0 + 11 + read-only + + + AUTOEXECPROGBUF + When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. + 16 + 31 + read-only + + + + + 0x4 + 0x4 + CONFSTRPTR[%s] + Description collection: Configuration String Pointer [n] + 0x64 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + NEXTDM + Next Debug Module + 0x74 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + 0x10 + 0x4 + PROGBUF[%s] + Description collection: Program Buffer [n] + 0x80 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + AUTHDATA + Authentication Data + 0xC0 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + HALTSUM2 + Halt Summary 2 + 0xD0 + read-write + 0x00000000 + 0x20 + + + HALTSUM2 + Halt Summary 2 + 0 + 31 + read-only + + + + + HALTSUM3 + Halt Summary 3 + 0xD4 + read-write + 0x00000000 + 0x20 + + + HALTSUM3 + Halt Summary 3 + 0 + 31 + read-only + + + + + SBADDRESS3 + System Bus Addres 127:96 + 0xDC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 127:96 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBCS + System Bus Access Control and Status + 0xE0 + read-write + 0x20000000 + 0x20 + + + SBACCESS8 + 0 + 0 + read-only + + + sbaccess8 + 8-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS16 + 1 + 1 + read-only + + + sbaccess16 + 16-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS32 + 2 + 2 + read-only + + + sbaccess32 + 32-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS64 + 3 + 3 + read-only + + + sbaccess64 + 64-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS128 + 4 + 4 + read-only + + + sbaccess128 + 128-bit system bus accesses are supported. + 0x1 + + + + + SBASIZE + Width of system bus addresses in bits. (0 indicates there is no bus access support.) + 5 + 11 + read-only + + + SBERROR + 12 + 14 + read-only + + + Normal + There was no bus error. + 0x0 + + + Timeout + There was a timeout. + 0x1 + + + Address + A bad address was accessed. + 0x2 + + + Alignment + There was an alignment error. + 0x3 + + + Size + An access of unsupported size was requested. + 0x4 + + + Other + Other. + 0x7 + + + + + SBREADONDATA + 15 + 15 + read-only + + + sbreadondata + Every read from sbdata0 automatically + triggers a system bus read at the (possibly autoincremented) address. + 0x1 + + + + + SBAUTOINCREMENT + 16 + 16 + read-only + + + sbautoincrement + sbaddress is incremented by the access + size (in bytes) selected in sbaccess after every system bus access. + 0x1 + + + + + SBACCESS + 17 + 19 + read-only + + + size8 + 8-bit. + 0x0 + + + size16 + 16-bit. + 0x1 + + + size32 + 32-bit. + 0x2 + + + size64 + 64-bit. + 0x3 + + + size128 + 128-bit. + 0x4 + + + + + SBREADONADDR + 20 + 20 + read-only + + + sbreadonaddr + Every write to sbaddress0 automatically + triggers a system bus read at the new address. + 0x1 + + + + + SBBUSY + 21 + 21 + read-only + + + notbusy + System bus master is not busy. + 0x0 + + + busy + System bus master is busy. + 0x1 + + + + + SBBUSYERROR + 22 + 22 + read-only + + + noerror + No error. + 0x0 + + + error + Debugger access attempted while one in progress. + 0x1 + + + + + SBVERSION + 29 + 31 + read-only + + + version0 + The System Bus interface conforms to mainline + drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. + 0x0 + + + version1 + The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. + Other values are reserved for future versions. + 0x1 + + + + + + + SBADDRESS0 + System Bus Addres 31:0 + 0xE4 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 31:0 of the physical address in + sbaddress. + 0 + 31 + read-only + + + + + SBADDRESS1 + System Bus Addres 63:32 + 0xE8 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 63:32 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBADDRESS2 + System Bus Addres 95:64 + 0xEC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 95:64 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBDATA0 + System Bus Data 31:0 + 0xF0 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 31:0 of sbdata + 0 + 31 + read-only + + + + + SBDATA1 + System Bus Data 63:32 + 0xF4 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 63:32 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA2 + System Bus Data 95:64 + 0xF8 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 95:64 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA3 + System Bus Data 127:96 + 0xFC + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 127:96 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + HALTSUM0 + Halt summary 0 + 0x100 + read-write + 0x00000000 + 0x20 + + + HALTSUM0 + Halt summary 0 + 0 + 31 + read-only + + + + + + CPURUN + State of the CPU after a core reset + 0x800 + read-write + 0x00000000 + 0x20 + + + EN + Controls CPU running state after a core reset. + 0 + 0 + + + Stopped + CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. + 0x0 + + + Running + CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. + 0x1 + + + + + + + INITPC + Initial value of the PC at CPU start. + 0x808 + read-write + 0x00000000 + 0x20 + + + INITPC + Initial value of the PC at CPU start. + 0 + 31 + + + + + + + GLOBAL_CAN120 + Controller Area Network 0 + 0x5F8D8000 + CAN + + + + 0 + 0x1000 + registers + + + CAN120 + 216 + + CAN + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the CAN peripheral + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_CORE[%s] + Description collection: Event indicating that interrupt n triggered at CAN core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt n triggered at CAN core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READYFORSTOP_STOP + Shortcut between event READYFORSTOP and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE0 + Enable or disable interrupt for event CORE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CORE1 + Enable or disable interrupt for event CORE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMU + Enable or disable interrupt for event DMU + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READYFORSTOP + Enable or disable interrupt for event READYFORSTOP + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to enable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CORE1 + Write '1' to enable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMU + Write '1' to enable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READYFORSTOP + Write '1' to enable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to disable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CORE1 + Write '1' to disable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMU + Write '1' to disable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READYFORSTOP + Write '1' to disable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE0 + Read pending status of interrupt for event CORE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CORE1 + Read pending status of interrupt for event CORE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMU + Read pending status of interrupt for event DMU + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READYFORSTOP + Read pending status of interrupt for event READYFORSTOP + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_MVDMA120 + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x5F8D9000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA120 + 217 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + GLOBAL_MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + GLOBAL_MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + GLOBAL_MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + GLOBAL_MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + GLOBAL_MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + GLOBAL_MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + GLOBAL_RAMC122 + RAM Controller 0 + 0x5F8DA000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + + + GLOBAL_CAN121 + Controller Area Network 1 + 0x5F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_MVDMA121 + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x5F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_RAMC123 + RAM Controller 1 + 0x5F8DD000 + + + + + GLOBAL_I3C121 + I3C 1 + 0x5F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_DPPIC120 + Distributed programmable peripheral interconnect controller 0 + 0x5F8E1000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 4 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 4 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x4 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + 0x20 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + GLOBAL_TIMER120 + Timer/Counter 0 + 0x5F8E2000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER120 + 226 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + 0x20 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + 0x20 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + 0x20 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + 0x00000000 + 0x20 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + + + GLOBAL_TIMER121 + Timer/Counter 1 + 0x5F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_PWM120 + Pulse width modulation unit 0 + 0x5F8E4000 + PWM + + + + 0 + 0x1000 + registers + + + PWM120 + 228 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + PWM_TASKS_DMA + write-only + 0x010 + + 2 + 0x008 + SEQ[%s] + Peripheral tasks. + PWM_TASKS_DMA_SEQ + write-only + 0x000 + + START + Description cluster: Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA + read-write + 0x090 + + 2 + 0x008 + SEQ[%s] + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA_SEQ + read-write + 0x000 + + START + Description cluster: Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PWM_EVENTS_DMA + read-write + 0x124 + + 2 + 0x00C + SEQ[%s] + Peripheral events. + PWM_EVENTS_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + Description cluster: An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + 0x4 + 0x4 + EVENTS_COMPAREMATCH[%s] + Description collection: This event is generated when the compare matches for the compare channel [n]. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPAREMATCH + This event is generated when the compare matches for the compare channel [n]. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RAMUNDERFLOW + Publish configuration for event RAMUNDERFLOW + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RAMUNDERFLOW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PWM_PUBLISH_DMA + read-write + 0x1A4 + + 2 + 0x00C + SEQ[%s] + Publish configuration for events + PWM_PUBLISH_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Description cluster: Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Description cluster: Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + 0x4 + 0x4 + PUBLISH_COMPAREMATCH[%s] + Description collection: Publish configuration for event COMPAREMATCH[n] + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPAREMATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + SEQEND0_STOP + Shortcut between event SEQEND[n] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[n] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RAMUNDERFLOW_STOP + Shortcut between event RAMUNDERFLOW and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ0_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ1_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RAMUNDERFLOW + Enable or disable interrupt for event RAMUNDERFLOW + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0END + Enable or disable interrupt for event DMASEQ0END + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0READY + Enable or disable interrupt for event DMASEQ0READY + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Enable or disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1END + Enable or disable interrupt for event DMASEQ1END + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1READY + Enable or disable interrupt for event DMASEQ1READY + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Enable or disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH0 + Enable or disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH1 + Enable or disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH2 + Enable or disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH3 + Enable or disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to enable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0END + Write '1' to enable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0READY + Write '1' to enable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to enable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1END + Write '1' to enable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1READY + Write '1' to enable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to enable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to enable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to enable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to enable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to enable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to disable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0END + Write '1' to disable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0READY + Write '1' to disable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1END + Write '1' to disable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1READY + Write '1' to disable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED0 + Read pending status of interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED1 + Read pending status of interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND0 + Read pending status of interrupt for event SEQEND[0] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND1 + Read pending status of interrupt for event SEQEND[1] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LOOPSDONE + Read pending status of interrupt for event LOOPSDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RAMUNDERFLOW + Read pending status of interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0END + Read pending status of interrupt for event DMASEQ0END + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0READY + Read pending status of interrupt for event DMASEQ0READY + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0BUSERROR + Read pending status of interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1END + Read pending status of interrupt for event DMASEQ1END + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1READY + Read pending status of interrupt for event DMASEQ1READY + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1BUSERROR + Read pending status of interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH0 + Read pending status of interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH1 + Read pending status of interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH2 + Read pending status of interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH3 + Read pending status of interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + IDLEOUT + Configure the output value on the PWM channel during idle + 0x518 + read-write + 0x00000000 + 0x20 + + + VAL_0 + Idle output value for PWM channel [0] + 0 + 0 + + + VAL_1 + Idle output value for PWM channel [1] + 1 + 1 + + + VAL_2 + Idle output value for PWM channel [2] + 2 + 2 + + + VAL_3 + Idle output value for PWM channel [3] + 3 + 3 + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + PWM_DMA + read-write + 0x700 + + 2 + 0x024 + SEQ[%s] + Unspecified + PWM_DMA_SEQ + read-write + 0x000 + + PTR + Description cluster: RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Description cluster: Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIS120 + SPI Slave 0 + 0x5F8E5000 + SPIS + + + + 0 + 0x1000 + registers + + + SPIS120 + 229 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIS_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIS_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIS_DMA + read-write + 0x700 + + RX + Unspecified + SPIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM120 + Serial Peripheral Interface Master with EasyDMA 0 + 0x5F8E6000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIM_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STARTED + SPI transaction has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + SPI transaction has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PRESCALER + The prescaler is used to set the SPI frequency. + 0x52C + read-write + 0x00000040 + 0x20 + + + DIVISOR + Core clock to SCK divisor + 0 + 6 + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x5AC + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of SPIM core clock cycles. + 0 + 7 + + + + + + DCXCNT + DCX configuration + 0x5B4 + read-write + 0x00000000 + 0x20 + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + CSNPOL + Polarity of CSN output + 0x5B8 + read-write + 0x00000000 + 0x20 + + + CSNPOL_0 + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0x0 + + + HIGH + Active high (idle state low) + 0x1 + + + + + + + CSNCONTROL + Selects which CSN is used, only one CSN can be active at one time. This register can be safely written during an ongoing SPI transaction. + 0x5BC + read-write + 0x00000000 + 0x20 + + + CSN + CSN Number. + 0 + 0 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DCX + Pin select for DCX signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + 0x1 + 0x4 + CSN[%s] + Description collection: Pin select for CSN + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIM_DMA + read-write + 0x700 + + RX + Unspecified + SPIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE120 + UART with EasyDMA 0 + 0x5F8E6000 + GLOBAL_SPIM120 + UARTE + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + UARTE + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + UARTE_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + UARTE_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + UARTE_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x124 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + UARTE_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + UARTE_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + UARTE_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0x174 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + UARTE_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + UARTE_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + UARTE_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + PUBLISH_FRAMETIMEOUT + Publish configuration for event FRAMETIMEOUT + 0x1F4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMETIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + DMA_RX_END_DMA_RX_START + Shortcut between event DMA.RX.END and task DMA.RX.START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_END_DMA_RX_STOP + Shortcut between event DMA.RX.END and task DMA.RX.STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_TX_END_DMA_TX_STOP + Shortcut between event DMA.TX.END and task DMA.TX.STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMETIMEOUT_DMA_RX_STOP + Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP + 29 + 29 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMETIMEOUT + Enable or disable interrupt for event FRAMETIMEOUT + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to enable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to disable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + CONFIG + Configuration of parity, hardware flow control, framesize, and packet timeout. + 0x56C + read-write + 0x00001000 + 0x20 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0x0 + + + Odd + Odd parity + 0x1 + + + + + FRAMESIZE + Set the data frame size + 9 + 12 + + + 9bit + 9 bit data frame size. 9th bit is treated as address bit. + 0x9 + + + 8bit + 8 bit data frame size. + 0x8 + + + 7bit + 7 bit data frame size. + 0x7 + + + 6bit + 6 bit data frame size. + 0x6 + + + 5bit + 5 bit data frame size. + 0x5 + + + 4bit + 4 bit data frame size. + 0x4 + + + + + ENDIAN + Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. + 13 + 13 + + + MSB + Data is trimmed from MSB end. + 0x0 + + + LSB + Data is trimmed from LSB end. + 0x1 + + + + + FRAMETIMEOUT + Enable packet timeout. + 14 + 14 + + + DISABLED + Packet timeout is disabled. + 0x0 + + + ENABLED + Packet timeout is enabled. + 0x1 + + + + + + + ADDRESS + Set the address of the UARTE for RX when used in 9 bit data frame mode. + 0x574 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Set address + 0 + 7 + + + + + FRAMETIMEOUT + Set the number of UARTE bits to count before triggering packet timeout. + 0x578 + read-write + 0x00000010 + 0x20 + + + COUNTERTOP + Number of UARTE bits before timeout. + 0 + 9 + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x604 + + TXD + Pin select for TXD signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RTS + Pin select for RTS signal + 0x0C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + UARTE_DMA + read-write + 0x700 + + RX + Unspecified + UARTE_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + UARTE_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + UARTE_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM121 + Serial Peripheral Interface Master with EasyDMA 1 + 0x5F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_VPR130 + VPR peripheral registers 1 + 0x5F908000 + + + + VPR130 + 264 + + + + GLOBAL_IPCT130 + IPCT APB registers 1 + 0x5F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_DPPIC130 + Distributed programmable peripheral interconnect controller 1 + 0x5F922000 + + + + + + GLOBAL_MUTEX130 + MUTEX 1 + 0x4F927000 + + + + + GLOBAL_RTC130 + Real-time counter 0 + 0x5F928000 + RTC + + + + 0 + 0x1000 + registers + + + RTC130 + 296 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable event routing for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable event routing for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable event routing for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable event routing for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 31 + + + + + + + GLOBAL_RTC131 + Real-time counter 1 + 0x5F929000 + + + + RTC131 + 297 + + + + GLOBAL_WDT131 + Watchdog Timer 0 + 0x5F92B000 + WDT + + + + 0 + 0x1000 + registers + + + WDT131 + 299 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + 0x20 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0x0 + + + Run + Keep WDT running while the CPU is sleeping + 0x1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0x0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 0x1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0x0 + + + Enable + Allow stopping WDT + 0x1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + 0x20 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + GLOBAL_WDT132 + Watchdog Timer 1 + 0x5F92C000 + + + + WDT132 + 300 + + + + GLOBAL_EGU130 + Event generator unit + 0x5F92D000 + EGU + + + + 0 + 0x1000 + registers + + + EGU130 + 301 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_P0 + GPIO Port 0 + 0x5F938000 + GPIO + + + + + 0 + 0x200 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x000 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x004 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x00C + read-only + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x010 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x014 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x018 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + 0x20 + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x024 + read-write + 0x00000000 + 0x20 + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + RETAIN + Enable retention for those GPIO registers marked as retained + 0x028 + read-write + 0x0000000C + 0x20 + + + APPLICAION + Enable retention for GPIO registers for Application domain + 2 + 2 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + RADIOCORE + Enable retention for GPIO registers for Radio core + 3 + 3 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + + + PORTCNF + Unspecified + GPIO_PORTCNF + read-write + 0x030 + + DRIVECTRL + Drive control for impedance matching of the pins in this port + 0x00 + read-write + 0x00000000 + 0x20 + + + + IMPEDANCE50 + Enable 50 ohms impedance to the pins in this port + 0 + 0 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE100 + Enable 100 ohms impedance to the pins in this port + 1 + 1 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE200 + Enable 200 ohms impedance to the pins in this port + 2 + 2 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE400 + Enable 400 ohms impedance to the pins in this port + 3 + 3 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE800 + Enable 800 ohms impedance to the pins in this port + 4 + 4 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE1600 + Enable 1600 ohms impedance to the pins in this port + 5 + 5 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Pin n configuration of GPIO pin + 0x080 + read-write + 0x00000002 + 0x20 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE0 + Drive configuration for '0' + 8 + 9 + + + S0 + Standard '0' + 0x0 + + + H0 + High drive '0' + 0x1 + + + D0 + Disconnect '0'(normally used for wired-or connections) + 0x2 + + + E0 + Extra high drive '0' + 0x3 + + + + + DRIVE1 + Drive configuration for '1' + 10 + 11 + + + S1 + Standard '1' + 0x0 + + + H1 + High drive '1' + 0x1 + + + D1 + Disconnect '1'(normally used for wired-or connections) + 0x2 + + + E1 + Extra high drive '1' + 0x3 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + CLOCKPIN + Enable clock on the pin. + 31 + 31 + + + Disabled + Clock disabled + 0x0 + + + Enabled + Clock enabled + 0x1 + + + + + + + + + GLOBAL_P1 + GPIO Port 1 + 0x5F938200 + + + + + + GLOBAL_P2 + GPIO Port 2 + 0x5F938400 + + + + + + GLOBAL_P6 + GPIO Port 3 + 0x5F938C00 + + + + + + GLOBAL_P8 + GPIO Port 4 + 0x5F939000 + + + + + + GLOBAL_P9 + GPIO Port 5 + 0x5F939200 + + + + + + GLOBAL_P10 + GPIO Port 6 + 0x5F939400 + + + + + + GLOBAL_P11 + GPIO Port 7 + 0x5F939600 + + + + + + GLOBAL_P12 + GPIO Port 8 + 0x5F939800 + + + + + + GLOBAL_P13 + GPIO Port 9 + 0x5F939A00 + + + + + + GLOBAL_DPPIC131 + Distributed programmable peripheral interconnect controller 2 + 0x5F981000 + + + + + + GLOBAL_SAADC + Analog to Digital Converter + 0x5F982000 + + + + 0 + 0x1000 + registers + + + SAADC + 386 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + GLOBAL_SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + GLOBAL_SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + TRIM + Unspecified + GLOBAL_SAADC_TRIM + read-write + 0x440 + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Linearity calibration coefficient + 0x000 + read-write + 0x00000000 + 0x20 + + + VAL + value + 0 + 15 + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + GLOBAL_SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x0 + read-write + 0x00000000 + 0x20 + + + PIN + Analog positive input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x4 + read-write + 0x00000000 + 0x20 + + + PIN + Analog negative input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + GAIN + Gain control + 8 + 9 + + + Gain2_3 + 2/3 + 0x0 + + + Gain1 + 1 + 0x1 + + + Gain2 + 2 + 0x2 + + + Gain4 + 4 + 0x3 + + + + + BURST + Enable burst mode + 11 + 11 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (1.024 V) + 0x0 + + + External + External reference given at PADC_EXT_REF_1V2 + 0x1 + + + + + MODE + Enable differential mode + 15 + 15 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) + 16 + 24 + + + TCONV + Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) + 28 + 30 + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + 0x20 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + GLOBAL_SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of buffer bytes to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer bytes transferred since last START + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + GLOBAL_COMP + Comparator + 0x5F983000 + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (AVDD_AO_1V8 &gt;= 1.7 V) + 0x0 + + + AVDDAO1V8 + VREF = AVDD_AO_1V8 + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00002020 + 0x20 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 0 + + + Low + Low-power mode + 0x0 + + + High + High-speed mode + 0x1 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0x0 + + + Diff + Differential mode + 0x1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0x0 + + + Hyst40mV + Comparator hysteresis enabled + 0x1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + 0x00000000 + 0x20 + + + ISOURCE + Current source select on analog input + 0 + 1 + + + Off + Current source disabled + 0x0 + + + Ien2uA5 + Current source enabled (+/- 2.5 uA) + 0x1 + + + Ien5uA + Current source enabled (+/- 5 uA) + 0x2 + + + Ien10uA + Current source enabled (+/- 10 uA) + 0x3 + + + + + + + + + GLOBAL_LPCOMP + Low-power comparator + 0x5F983000 + GLOBAL_COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0x0 + + + Enabled + Comparator hysteresis enabled + 0x1 + + + + + + + + + GLOBAL_TEMP + Temperature Sensor + 0x5F984000 + + + + 0 + 0x1000 + registers + + + TEMP + 388 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DATARDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + 0x00000000 + int32_t + 0x20 + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000276 + 0x20 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000324 + 0x20 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AB + 0x20 + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000453 + 0x20 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000049B + 0x20 + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x00000550 + 0x20 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + A6 + Slope of 7th piece wise linear function + 0x538 + read-write + 0x0000067E + 0x20 + + + A6 + Slope of 7th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00000FA6 + 0x20 + + + B0 + y-intercept of 1st piece wise linear function + 0 + 11 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00000F35 + 0x20 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 11 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00000FAA + 0x20 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 11 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x0000007E + 0x20 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 11 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x000000EA + 0x20 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 11 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x000001ED + 0x20 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 11 + + + + + B6 + y-intercept of 7th piece wise linear function + 0x558 + read-write + 0x00000378 + 0x20 + + + B6 + y-intercept of 7th piece wise linear function + 0 + 11 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000ED + 0x20 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000013 + 0x20 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000029 + 0x20 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + 0x20 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000044 + 0x20 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + T5 + End point of 6th piece wise linear function + 0x574 + read-write + 0x00000053 + 0x20 + + + T5 + End point of 6th piece wise linear function + 0 + 7 + + + + + + + GLOBAL_DPPIC132 + Distributed programmable peripheral interconnect controller 3 + 0x5F991000 + + + + + + GLOBAL_I2S130 + Inter-IC Sound 0 + 0x5F992000 + I2S + + + + 0 + 0x1000 + registers + + + I2S130 + 402 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + GLOBAL_I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + 0x20 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + 0x20 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + 0x20 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + 0x20 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0x0 + + + 16Bit + 16 bit sample. + 0x1 + + + 24Bit + 24 bit sample. + 0x2 + + + 32Bit + 32 bit sample. + 0x3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 0x4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 0x5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 0x6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 0x7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + 0x20 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + 0x20 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + 0x20 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + 0x20 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0x0 + + + Enable + Enable bypass + 0x1 + + + + + + + + RXD + Unspecified + GLOBAL_I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + GLOBAL_I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + GLOBAL_I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + GLOBAL_I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + GLOBAL_PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x5F993000 + + + + 0 + 0x1000 + registers + + + PDM + 403 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STARTED + Read pending status of interrupt for event STARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + END + Read pending status of interrupt for event END + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + 0x20 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + 0x20 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled. + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + 0x20 + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate + 0 + 2 + + + Ratio64 + Ratio of 64 + 0x0 + + + Ratio80 + Ratio of 80 + 0x1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + 0x20 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + 0x20 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + 0x20 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + DMA + Unspecified + PDM_DMA + read-write + 0x700 + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x004 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_QDEC130 + Quadrature Decoder 0 + 0x5F994000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC130 + 404 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SAMPLERDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event REPORTRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACCOF will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DBLRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + 0x00000000 + 0x20 + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0x0 + + + ActiveHigh + Led active on output pin high + 0x1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0x0 + + + 256us + 256 us + 0x1 + + + 512us + 512 us + 0x2 + + + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0x0 + + + 40Smpl + 40 samples/report + 0x1 + + + 80Smpl + 80 samples/report + 0x2 + + + 120Smpl + 120 samples/report + 0x3 + + + 160Smpl + 160 samples/report + 0x4 + + + 200Smpl + 200 samples/report + 0x5 + + + 240Smpl + 240 samples/report + 0x6 + + + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0x0 + + + Enabled + Debounce input filters enabled + 0x1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + GLOBAL_QDEC131 + Quadrature Decoder 1 + 0x5F995000 + + + + QDEC131 + 405 + + + + GLOBAL_I2S131 + Inter-IC Sound 1 + 0x5F997000 + + + + I2S131 + 407 + + + + GLOBAL_DPPIC133 + Distributed programmable peripheral interconnect controller 4 + 0x5F9A1000 + + + + + + GLOBAL_TIMER130 + Timer/Counter 2 + 0x5F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER131 + Timer/Counter 3 + 0x5F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_PWM130 + Pulse width modulation unit 1 + 0x5F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_SPIM130 + Serial Peripheral Interface Master with EasyDMA 2 + 0x5F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130 + SPI Slave 1 + 0x5F9A5000 + GLOBAL_SPIM130 + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x5F9A5000 + GLOBAL_SPIM130 + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIM + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + TWIM_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + TWIM_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + LASTTX_DMA_RX_START + Shortcut between event LASTTX and task DMA.RX.START + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_DMA_TX_START + Shortcut between event LASTRX and task DMA.TX.START + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIM_DMA + read-write + 0x700 + + RX + Unspecified + TWIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_TWIS130 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x5F9A5000 + GLOBAL_SPIM130 + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIS_TASKS_DMA + write-only + 0x030 + + RX + Peripheral tasks. + TWIS_TASKS_DMA_RX + write-only + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA + read-write + 0x0B0 + + RX + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA_RX + read-write + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + 0x20 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + 0x20 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIS_DMA + read-write + 0x700 + + RX + Unspecified + TWIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE130 + UART with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM131 + Serial Peripheral Interface Master with EasyDMA 3 + 0x5F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131 + SPI Slave 2 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131 + UART with EasyDMA 2 + 0x5F9A6000 + GLOBAL_SPIM131 + + + + SERIAL1 + 422 + + + + GLOBAL_DPPIC134 + Distributed programmable peripheral interconnect controller 5 + 0x5F9B1000 + + + + + + GLOBAL_TIMER132 + Timer/Counter 4 + 0x5F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER133 + Timer/Counter 5 + 0x5F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_PWM131 + Pulse width modulation unit 2 + 0x5F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_SPIM132 + Serial Peripheral Interface Master with EasyDMA 4 + 0x5F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132 + SPI Slave 3 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132 + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132 + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132 + UART with EasyDMA 3 + 0x5F9B5000 + GLOBAL_SPIM132 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM133 + Serial Peripheral Interface Master with EasyDMA 5 + 0x5F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133 + SPI Slave 4 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133 + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133 + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133 + UART with EasyDMA 4 + 0x5F9B6000 + GLOBAL_SPIM133 + + + + SERIAL3 + 438 + + + + GLOBAL_DPPIC135 + Distributed programmable peripheral interconnect controller 6 + 0x5F9C1000 + + + + + + GLOBAL_TIMER134 + Timer/Counter 6 + 0x5F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER135 + Timer/Counter 7 + 0x5F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_PWM132 + Pulse width modulation unit 3 + 0x5F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_SPIM134 + Serial Peripheral Interface Master with EasyDMA 6 + 0x5F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134 + SPI Slave 5 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134 + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134 + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134 + UART with EasyDMA 5 + 0x5F9C5000 + GLOBAL_SPIM134 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM135 + Serial Peripheral Interface Master with EasyDMA 7 + 0x5F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135 + SPI Slave 6 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135 + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135 + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135 + UART with EasyDMA 6 + 0x5F9C6000 + GLOBAL_SPIM135 + + + + SERIAL5 + 454 + + + + GLOBAL_DPPIC136 + Distributed programmable peripheral interconnect controller 7 + 0x5F9D1000 + + + + + + GLOBAL_TIMER136 + Timer/Counter 8 + 0x5F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER137 + Timer/Counter 9 + 0x5F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_PWM133 + Pulse width modulation unit 4 + 0x5F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_SPIM136 + Serial Peripheral Interface Master with EasyDMA 8 + 0x5F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136 + SPI Slave 7 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136 + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136 + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136 + UART with EasyDMA 7 + 0x5F9D5000 + GLOBAL_SPIM136 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM137 + Serial Peripheral Interface Master with EasyDMA 9 + 0x5F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137 + SPI Slave 8 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137 + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137 + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137 + UART with EasyDMA 8 + 0x5F9D6000 + GLOBAL_SPIM137 + + + + SERIAL7 + 470 + + + + \ No newline at end of file diff --git a/mdk/nrf9230_enga_ppr_peripherals.h b/mdk/nrf9230_enga_ppr_peripherals.h new file mode 100644 index 000000000..ad33bac48 --- /dev/null +++ b/mdk/nrf9230_enga_ppr_peripherals.h @@ -0,0 +1,1221 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_PPR_PERIPHERALS_H +#define NRF9230_ENGA_PPR_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +/*VPR CSR registers*/ +#define VPRCSR_PRESENT 1 +#define VPRCSR_COUNT 1 + +#define VPRCSR_HARTNUM 11 /*!< HARTNUM: 11 */ +#define VPRCSR_MCLICBASERESET 0x5F909000 /*!< MCLICBASE: 0x5F909000 */ +#define VPRCSR_MULDIV 1 /*!< MULDIV: 1 */ +#define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ +#define VPRCSR_DBG 1 /*!< DBG: 1 */ +#define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ +#define VPRCSR_BUSWIDTH 32 /*!< BUSWIDTH: 32 */ +#define VPRCSR_BKPT 1 /*!< BKPT: 1 */ +#define VPRCSR_VIOPINS 0x0000000F /*!< CSR VIOPINS value: 0x0000000F */ +#define VPRCSR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPRCSR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPRCSR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPRCSR_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPRCSR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ +#define VPRCSR_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ +#define VPRCSR_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ +#define VPRCSR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPRCSR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPRCSR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPRCSR_BEXT 0 /*!< Bit-Manipulation extension: 0 */ +#define VPRCSR_CACHE_EN 0 /*!< (unspecified) */ +#define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ +#define VPRCSR_VPR_BUS_PRIO 0 /*!< (unspecified) */ +#define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ + +/*VPR CLIC registers*/ +#define CLIC_PRESENT 1 +#define CLIC_COUNT 1 + +#define VPRCLIC_IRQ_COUNT 16 +#define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_MAX 479 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_IRQNUM_SIZE 480 /*!< Supported interrupts (IRQNUM): 0..479 */ +#define VPRCLIC_CLIC_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPRCLIC_CLIC_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPRCLIC_CLIC_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPRCLIC_CLIC_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPRCLIC_COUNTER_IRQ_NUM 16 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 16 */ +#define VPRCLIC_CLIC_VPR_1_2 1 /*!< (unspecified) */ + +/*VTIM CSR registers*/ +#define VTIM_PRESENT 1 +#define VTIM_COUNT 1 + +/*Factory Information Configuration Registers*/ +#define FICR_PRESENT 1 +#define FICR_COUNT 1 + +/*USBHSCORE*/ +#define USBHSCORE_PRESENT 1 +#define USBHSCORE_COUNT 1 + +/*I3CCORE*/ +#define I3CCORE_PRESENT 1 +#define I3CCORE_COUNT 2 + +/*DMU*/ +#define DMU_PRESENT 1 +#define DMU_COUNT 2 + +/*MCAN*/ +#define MCAN_PRESENT 1 +#define MCAN_COUNT 2 + +/*System Trace Macrocell data buffer*/ +#define STMDATA_PRESENT 1 +#define STMDATA_COUNT 1 + +/*TDDCONF*/ +#define TDDCONF_PRESENT 1 +#define TDDCONF_COUNT 1 + +#define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 0 /*!< (unspecified) */ +#define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 1 /*!< (unspecified) */ + +/*System Trace Macrocell*/ +#define STM_PRESENT 1 +#define STM_COUNT 1 + +/*Trace Port Interface Unit*/ +#define TPIU_PRESENT 1 +#define TPIU_COUNT 1 + +/*Cross-Trigger Interface control*/ +#define CTI_PRESENT 1 +#define CTI_COUNT 2 + +/*ATB Replicator module*/ +#define ATBREPLICATOR_PRESENT 1 +#define ATBREPLICATOR_COUNT 4 + +/*ATB funnel module*/ +#define ATBFUNNEL_PRESENT 1 +#define ATBFUNNEL_COUNT 4 + +/*GPIO Tasks and Events*/ +#define GPIOTE_PRESENT 1 +#define GPIOTE_COUNT 2 + +#define GPIOTE130_IRQ_COUNT 2 +#define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +#define GPIOTE131_IRQ_COUNT 2 +#define GPIOTE131_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +/*Global Real-time counter*/ +#define GRTC_PRESENT 1 +#define GRTC_COUNT 1 + +#define GRTC_IRQ_COUNT 3 +#define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_PWMREGS 1 /*!< (unspecified) */ +#define GRTC_CLKOUTREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ + +/*Trace buffer monitor*/ +#define TBM_PRESENT 1 +#define TBM_COUNT 1 + +/*USBHS*/ +#define USBHS_PRESENT 1 +#define USBHS_COUNT 1 + +/*External Memory Interface*/ +#define EXMIF_PRESENT 1 +#define EXMIF_COUNT 1 + +/*BELLBOARD public registers*/ +#define BELLBOARDPUBLIC_PRESENT 1 +#define BELLBOARDPUBLIC_COUNT 1 + +/*VPR peripheral registers*/ +#define VPRPUBLIC_PRESENT 1 +#define VPRPUBLIC_COUNT 1 + +#define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ + +/*IPCT APB registers*/ +#define IPCT_PRESENT 1 +#define IPCT_COUNT 2 + +#define IPCT120_IRQ_COUNT 1 + +#define IPCT130_IRQ_COUNT 1 + +/*MUTEX*/ +#define MUTEX_PRESENT 1 +#define MUTEX_COUNT 2 + +/*I3C*/ +#define I3C_PRESENT 1 +#define I3C_COUNT 2 + +/*VPR peripheral registers*/ +#define VPR_PRESENT 1 +#define VPR_COUNT 2 + +#define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ +#define VPR121_RAM_SZ 15 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ +#define VPR121_RETAINED 0 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ +#define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ + +#define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ +#define VPR130_RAM_SZ 15 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ +#define VPR130_RETAINED 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ + +/*Controller Area Network*/ +#define CAN_PRESENT 1 +#define CAN_COUNT 2 + +/*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ + +#define MVDMA_PRESENT 1 +#define MVDMA_COUNT 2 + +#define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +#define MVDMA121_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA121_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA121_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +/*RAM Controller*/ +#define RAMC_PRESENT 1 +#define RAMC_COUNT 2 + +#define RAMC122_ECC 0 /*!< (unspecified) */ +#define RAMC122_SEC 0 /*!< (unspecified) */ + +#define RAMC123_ECC 0 /*!< (unspecified) */ +#define RAMC123_SEC 0 /*!< (unspecified) */ + +/*Distributed programmable peripheral interconnect controller*/ +#define DPPIC_PRESENT 1 +#define DPPIC_COUNT 8 + +#define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +/*Timer/Counter*/ +#define TIMER_PRESENT 1 +#define TIMER_COUNT 10 + +#define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ + +/*Pulse width modulation unit*/ +#define PWM_PRESENT 1 +#define PWM_COUNT 5 + +#define PWM120_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM120_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM130_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM130_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM131_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM131_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM132_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM132_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM133_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM133_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*SPI Slave*/ +#define SPIS_PRESENT 1 +#define SPIS_COUNT 9 + +#define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Serial Peripheral Interface Master with EasyDMA*/ +#define SPIM_PRESENT 1 +#define SPIM_COUNT 10 + +#define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +/*UART with EasyDMA*/ +#define UARTE_PRESENT 1 +#define UARTE_COUNT 9 + +#define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ +#define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ +#define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Real-time counter*/ +#define RTC_PRESENT 1 +#define RTC_COUNT 2 + +#define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ + +#define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ + +/*Watchdog Timer*/ +#define WDT_PRESENT 1 +#define WDT_COUNT 2 + +#define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT131_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT132_HAS_INTEN 0 /*!< (unspecified) */ + +/*Event generator unit*/ +#define EGU_PRESENT 1 +#define EGU_COUNT 1 + +#define EGU130_PEND 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ + +/*GPIO Port*/ +#define GPIO_PRESENT 1 +#define GPIO_COUNT 10 + +#define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MAX 12 /*!< (unspecified) */ +#define P0_PIN_NUM_SIZE 13 /*!< (unspecified) */ +#define P0_FEATURE_PINS_PRESENT 0x00001FFFUL /*!< (unspecified) */ +#define P0_DRIVECTRL 0 /*!< (unspecified) */ +#define P0_RETAIN 1 /*!< (unspecified) */ +#define P0_PWRCTRL 0 /*!< (unspecified) */ +#define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P0_BIASCTRL 0 /*!< (unspecified) */ + +#define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P1_DRIVECTRL 0 /*!< (unspecified) */ +#define P1_RETAIN 1 /*!< (unspecified) */ +#define P1_PWRCTRL 0 /*!< (unspecified) */ +#define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P1_BIASCTRL 0 /*!< (unspecified) */ + +#define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P2_DRIVECTRL 0 /*!< (unspecified) */ +#define P2_RETAIN 1 /*!< (unspecified) */ +#define P2_PWRCTRL 0 /*!< (unspecified) */ +#define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P2_BIASCTRL 0 /*!< (unspecified) */ + +#define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ +#define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ +#define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ +#define P6_DRIVECTRL 1 /*!< (unspecified) */ +#define P6_RETAIN 1 /*!< (unspecified) */ +#define P6_PWRCTRL 0 /*!< (unspecified) */ +#define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P6_BIASCTRL 0 /*!< (unspecified) */ + +#define P8_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MAX 4 /*!< (unspecified) */ +#define P8_PIN_NUM_SIZE 5 /*!< (unspecified) */ +#define P8_FEATURE_PINS_PRESENT 0x0000001FUL /*!< (unspecified) */ +#define P8_DRIVECTRL 1 /*!< (unspecified) */ +#define P8_RETAIN 1 /*!< (unspecified) */ +#define P8_PWRCTRL 0 /*!< (unspecified) */ +#define P8_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P8_BIASCTRL 0 /*!< (unspecified) */ + +#define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ +#define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ +#define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ +#define P9_DRIVECTRL 0 /*!< (unspecified) */ +#define P9_RETAIN 1 /*!< (unspecified) */ +#define P9_PWRCTRL 1 /*!< (unspecified) */ +#define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P9_BIASCTRL 0 /*!< (unspecified) */ + +#define P10_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P10_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P10_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P10_DRIVECTRL 0 /*!< (unspecified) */ +#define P10_RETAIN 1 /*!< (unspecified) */ +#define P10_PWRCTRL 0 /*!< (unspecified) */ +#define P10_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P10_BIASCTRL 0 /*!< (unspecified) */ + +#define P11_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P11_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P11_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P11_DRIVECTRL 0 /*!< (unspecified) */ +#define P11_RETAIN 1 /*!< (unspecified) */ +#define P11_PWRCTRL 0 /*!< (unspecified) */ +#define P11_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P11_BIASCTRL 0 /*!< (unspecified) */ + +#define P12_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MAX 2 /*!< (unspecified) */ +#define P12_PIN_NUM_SIZE 3 /*!< (unspecified) */ +#define P12_FEATURE_PINS_PRESENT 0x00000007UL /*!< (unspecified) */ +#define P12_DRIVECTRL 0 /*!< (unspecified) */ +#define P12_RETAIN 1 /*!< (unspecified) */ +#define P12_PWRCTRL 0 /*!< (unspecified) */ +#define P12_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P12_BIASCTRL 0 /*!< (unspecified) */ + +#define P13_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MAX 3 /*!< (unspecified) */ +#define P13_PIN_NUM_SIZE 4 /*!< (unspecified) */ +#define P13_FEATURE_PINS_PRESENT 0x0000000FUL /*!< (unspecified) */ +#define P13_DRIVECTRL 0 /*!< (unspecified) */ +#define P13_RETAIN 1 /*!< (unspecified) */ +#define P13_PWRCTRL 0 /*!< (unspecified) */ +#define P13_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P13_BIASCTRL 0 /*!< (unspecified) */ + +/*Analog to Digital Converter*/ +#define SAADC_PRESENT 1 +#define SAADC_COUNT 1 + +#define SAADC_PSEL_V2 1 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Comparator*/ +#define COMP_PRESENT 1 +#define COMP_COUNT 1 + +/*Low-power comparator*/ +#define LPCOMP_PRESENT 1 +#define LPCOMP_COUNT 1 + +/*Temperature Sensor*/ +#define TEMP_PRESENT 1 +#define TEMP_COUNT 1 + +/*Inter-IC Sound*/ +#define I2S_PRESENT 1 +#define I2S_COUNT 2 + +/*Pulse Density Modulation (Digital Microphone) Interface*/ +#define PDM_PRESENT 1 +#define PDM_COUNT 1 + +#define PDM_SAMPLE16 1 /*!< (unspecified) */ +#define PDM_SAMPLE48 0 /*!< (unspecified) */ +#define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Quadrature Decoder*/ +#define QDEC_PRESENT 1 +#define QDEC_COUNT 2 + +/*I2C compatible Two-Wire Master Interface with EasyDMA*/ +#define TWIM_PRESENT 1 +#define TWIM_COUNT 8 + +#define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*I2C compatible Two-Wire Slave Interface with EasyDMA*/ +#define TWIS_PRESENT 1 +#define TWIS_COUNT 8 + +#define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_PPR_PERIPHERALS_H */ + diff --git a/mdk/nrf9230_enga_ppr_vectors.h b/mdk/nrf9230_enga_ppr_vectors.h new file mode 100644 index 000000000..f5d031635 --- /dev/null +++ b/mdk/nrf9230_enga_ppr_vectors.h @@ -0,0 +1,703 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +__WEAK void UserSoftware_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorSoftware_Handler(void) +{ + while(1); +} + +__WEAK void MachineSoftware_Handler(void) +{ + while(1); +} + +__WEAK void UserTimer_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorTimer_Handler(void) +{ + while(1); +} + +__WEAK void MachineTimer_Handler(void) +{ + while(1); +} + +__WEAK void UserExternal_Handler(void) +{ + while(1); +} + +__WEAK void SuperVisorExternal_Handler(void) +{ + while(1); +} + +__WEAK void MachineExternal_Handler(void) +{ + while(1); +} + +__WEAK void CLICSoftware_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void VPRCLIC_0_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_1_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_2_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_3_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_4_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_5_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_6_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_7_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_8_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_9_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_10_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_11_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_12_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_13_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_14_IRQHandler (void); + __HANDLER("Default_Handler") void VPRCLIC_15_IRQHandler (void); + __HANDLER("Default_Handler") void VPRTIM_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_0_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_2_IRQHandler (void); + __HANDLER("Default_Handler") void TBM_IRQHandler (void); + __HANDLER("Default_Handler") void USBHS_IRQHandler (void); + __HANDLER("Default_Handler") void EXMIF_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT120_0_IRQHandler (void); + __HANDLER("Default_Handler") void I3C120_IRQHandler (void); + __HANDLER("Default_Handler") void VPR121_IRQHandler (void); + __HANDLER("Default_Handler") void CAN120_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA120_IRQHandler (void); + __HANDLER("Default_Handler") void CAN121_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA121_IRQHandler (void); + __HANDLER("Default_Handler") void I3C121_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER120_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER121_IRQHandler (void); + __HANDLER("Default_Handler") void PWM120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIS120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM120_UARTE120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM121_IRQHandler (void); + __HANDLER("Default_Handler") void VPR130_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT130_0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC130_IRQHandler (void); + __HANDLER("Default_Handler") void RTC131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT132_IRQHandler (void); + __HANDLER("Default_Handler") void EGU130_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void I2S130_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC130_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC131_IRQHandler (void); + __HANDLER("Default_Handler") void I2S131_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER130_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER131_IRQHandler (void); + __HANDLER("Default_Handler") void PWM130_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER132_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER133_IRQHandler (void); + __HANDLER("Default_Handler") void PWM131_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL2_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER134_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER135_IRQHandler (void); + __HANDLER("Default_Handler") void PWM132_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL4_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER136_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER137_IRQHandler (void); + __HANDLER("Default_Handler") void PWM133_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL6_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL7_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + UserSoftware_Handler, + SuperVisorSoftware_Handler, + MachineSoftware_Handler, + 0, + UserTimer_Handler, + SuperVisorTimer_Handler, + 0, + MachineTimer_Handler, + UserExternal_Handler, + SuperVisorExternal_Handler, + 0, + MachineExternal_Handler, + CLICSoftware_Handler, + 0, + 0, + 0, +/* Device specific interrupt handlers */ + VPRCLIC_0_IRQHandler, + VPRCLIC_1_IRQHandler, + VPRCLIC_2_IRQHandler, + VPRCLIC_3_IRQHandler, + VPRCLIC_4_IRQHandler, + VPRCLIC_5_IRQHandler, + VPRCLIC_6_IRQHandler, + VPRCLIC_7_IRQHandler, + VPRCLIC_8_IRQHandler, + VPRCLIC_9_IRQHandler, + VPRCLIC_10_IRQHandler, + VPRCLIC_11_IRQHandler, + VPRCLIC_12_IRQHandler, + VPRCLIC_13_IRQHandler, + VPRCLIC_14_IRQHandler, + VPRCLIC_15_IRQHandler, + VPRTIM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + GPIOTE130_0_IRQHandler, + GPIOTE130_1_IRQHandler, + GPIOTE131_0_IRQHandler, + GPIOTE131_1_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TBM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + USBHS_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXMIF_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT120_0_IRQHandler, + 0, + I3C120_IRQHandler, + VPR121_IRQHandler, + 0, + 0, + 0, + CAN120_IRQHandler, + MVDMA120_IRQHandler, + 0, + CAN121_IRQHandler, + MVDMA121_IRQHandler, + 0, + I3C121_IRQHandler, + 0, + 0, + 0, + TIMER120_IRQHandler, + TIMER121_IRQHandler, + PWM120_IRQHandler, + SPIS120_IRQHandler, + SPIM120_UARTE120_IRQHandler, + SPIM121_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + VPR130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT130_0_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + RTC130_IRQHandler, + RTC131_IRQHandler, + 0, + WDT131_IRQHandler, + WDT132_IRQHandler, + EGU130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SAADC_IRQHandler, + COMP_LPCOMP_IRQHandler, + TEMP_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + I2S130_IRQHandler, + PDM_IRQHandler, + QDEC130_IRQHandler, + QDEC131_IRQHandler, + 0, + I2S131_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER130_IRQHandler, + TIMER131_IRQHandler, + PWM130_IRQHandler, + SERIAL0_IRQHandler, + SERIAL1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER132_IRQHandler, + TIMER133_IRQHandler, + PWM131_IRQHandler, + SERIAL2_IRQHandler, + SERIAL3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER134_IRQHandler, + TIMER135_IRQHandler, + PWM132_IRQHandler, + SERIAL4_IRQHandler, + SERIAL5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER136_IRQHandler, + TIMER137_IRQHandler, + PWM133_IRQHandler, + SERIAL6_IRQHandler, + SERIAL7_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + + +__attribute__((aligned(16), noreturn)) void Trap_Handler(void) +{ + __UNUSED uint32_t mcause = csr_read(CSR_MCAUSE); + while(1); +} + +__attribute__((used, section(".isr_return"), naked)) void isr_return(void) +{ + asm volatile ("mret"); +} + +#endif diff --git a/mdk/nrf9230_enga_radiocore.h b/mdk/nrf9230_enga_radiocore.h new file mode 100644 index 000000000..ed05a91ca --- /dev/null +++ b/mdk/nrf9230_enga_radiocore.h @@ -0,0 +1,685 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_RADIOCORE_H +#define NRF9230_ENGA_RADIOCORE_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#ifdef NRF_RADIOCORE /*!< Processor information is domain local. */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ===================================================== Core Interrupts ===================================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No + Match*/ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault*/ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ============================================== Processor Specific Interrupts ============================================== */ + SPU000_IRQn = 0, /*!< 0 SPU000 */ + MPC_IRQn = 1, /*!< 1 MPC */ + MVDMA_IRQn = 3, /*!< 3 MVDMA */ + SPU010_IRQn = 16, /*!< 16 SPU010 */ + WDT010_IRQn = 19, /*!< 19 WDT010 */ + WDT011_IRQn = 20, /*!< 20 WDT011 */ + SPU020_IRQn = 32, /*!< 32 SPU020 */ + EGU020_IRQn = 37, /*!< 37 EGU020 */ + TIMER020_IRQn = 40, /*!< 40 TIMER020 */ + TIMER021_IRQn = 41, /*!< 41 TIMER021 */ + TIMER022_IRQn = 42, /*!< 42 TIMER022 */ + RTC_IRQn = 43, /*!< 43 RTC */ + RADIO_0_IRQn = 44, /*!< 44 RADIO_0 */ + RADIO_1_IRQn = 45, /*!< 45 RADIO_1 */ + SPU030_IRQn = 48, /*!< 48 SPU030 */ + VPR_IRQn = 52, /*!< 52 VPR */ + AAR030_CCM030_IRQn = 58, /*!< 58 AAR030_CCM030 */ + ECB030_IRQn = 59, /*!< 59 ECB030 */ + AAR031_CCM031_IRQn = 60, /*!< 60 AAR031_CCM031 */ + ECB031_IRQn = 61, /*!< 61 ECB031 */ + IPCT_0_IRQn = 64, /*!< 64 IPCT_0 */ + IPCT_1_IRQn = 65, /*!< 65 IPCT_1 */ + SWI0_IRQn = 88, /*!< 88 SWI0 */ + SWI1_IRQn = 89, /*!< 89 SWI1 */ + SWI2_IRQn = 90, /*!< 90 SWI2 */ + SWI3_IRQn = 91, /*!< 91 SWI3 */ + SWI4_IRQn = 92, /*!< 92 SWI4 */ + SWI5_IRQn = 93, /*!< 93 SWI5 */ + SWI6_IRQn = 94, /*!< 94 SWI6 */ + SWI7_IRQn = 95, /*!< 95 SWI7 */ + BELLBOARD_0_IRQn = 96, /*!< 96 BELLBOARD_0 */ + BELLBOARD_1_IRQn = 97, /*!< 97 BELLBOARD_1 */ + BELLBOARD_2_IRQn = 98, /*!< 98 BELLBOARD_2 */ + BELLBOARD_3_IRQn = 99, /*!< 99 BELLBOARD_3 */ + GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ + GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ + GPIOTE131_0_IRQn = 106, /*!< 106 GPIOTE131_0 */ + GPIOTE131_1_IRQn = 107, /*!< 107 GPIOTE131_1 */ + GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ + GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ + GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ + TBM_IRQn = 127, /*!< 127 TBM */ + USBHS_IRQn = 134, /*!< 134 USBHS */ + EXMIF_IRQn = 149, /*!< 149 EXMIF */ + IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ + I3C120_IRQn = 211, /*!< 211 I3C120 */ + VPR121_IRQn = 212, /*!< 212 VPR121 */ + CAN120_IRQn = 216, /*!< 216 CAN120 */ + MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ + CAN121_IRQn = 219, /*!< 219 CAN121 */ + MVDMA121_IRQn = 220, /*!< 220 MVDMA121 */ + I3C121_IRQn = 222, /*!< 222 I3C121 */ + TIMER120_IRQn = 226, /*!< 226 TIMER120 */ + TIMER121_IRQn = 227, /*!< 227 TIMER121 */ + PWM120_IRQn = 228, /*!< 228 PWM120 */ + SPIS120_IRQn = 229, /*!< 229 SPIS120 */ + SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ + SPIM121_IRQn = 231, /*!< 231 SPIM121 */ + VPR130_IRQn = 264, /*!< 264 VPR130 */ + IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ + RTC130_IRQn = 296, /*!< 296 RTC130 */ + RTC131_IRQn = 297, /*!< 297 RTC131 */ + WDT131_IRQn = 299, /*!< 299 WDT131 */ + WDT132_IRQn = 300, /*!< 300 WDT132 */ + EGU130_IRQn = 301, /*!< 301 EGU130 */ + SAADC_IRQn = 386, /*!< 386 SAADC */ + COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ + TEMP_IRQn = 388, /*!< 388 TEMP */ + I2S130_IRQn = 402, /*!< 402 I2S130 */ + PDM_IRQn = 403, /*!< 403 PDM */ + QDEC130_IRQn = 404, /*!< 404 QDEC130 */ + QDEC131_IRQn = 405, /*!< 405 QDEC131 */ + I2S131_IRQn = 407, /*!< 407 I2S131 */ + TIMER130_IRQn = 418, /*!< 418 TIMER130 */ + TIMER131_IRQn = 419, /*!< 419 TIMER131 */ + PWM130_IRQn = 420, /*!< 420 PWM130 */ + SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ + SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ + TIMER132_IRQn = 434, /*!< 434 TIMER132 */ + TIMER133_IRQn = 435, /*!< 435 TIMER133 */ + PWM131_IRQn = 436, /*!< 436 PWM131 */ + SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ + SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ + TIMER134_IRQn = 450, /*!< 450 TIMER134 */ + TIMER135_IRQn = 451, /*!< 451 TIMER135 */ + PWM132_IRQn = 452, /*!< 452 PWM132 */ + SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ + SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ + TIMER136_IRQn = 466, /*!< 466 TIMER136 */ + TIMER137_IRQn = 467, /*!< 467 TIMER137 */ + PWM133_IRQn = 468, /*!< 468 PWM133 */ + SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ + SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ +} IRQn_Type; + +/* ==================================================== Interrupt Aliases ==================================================== */ +#define AAR030_IRQn AAR030_CCM030_IRQn +#define AAR030_IRQHandler AAR030_CCM030_IRQHandler +#define CCM030_IRQn AAR030_CCM030_IRQn +#define CCM030_IRQHandler AAR030_CCM030_IRQHandler +#define AAR031_IRQn AAR031_CCM031_IRQn +#define AAR031_IRQHandler AAR031_CCM031_IRQHandler +#define CCM031_IRQn AAR031_CCM031_IRQn +#define CCM031_IRQHandler AAR031_CCM031_IRQHandler +#define SPIM120_IRQn SPIM120_UARTE120_IRQn +#define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler +#define UARTE120_IRQn SPIM120_UARTE120_IRQn +#define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler +#define COMP_IRQn COMP_LPCOMP_IRQn +#define COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SPIM130_IRQn SERIAL0_IRQn +#define SPIM130_IRQHandler SERIAL0_IRQHandler +#define SPIS130_IRQn SERIAL0_IRQn +#define SPIS130_IRQHandler SERIAL0_IRQHandler +#define TWIM130_IRQn SERIAL0_IRQn +#define TWIM130_IRQHandler SERIAL0_IRQHandler +#define TWIS130_IRQn SERIAL0_IRQn +#define TWIS130_IRQHandler SERIAL0_IRQHandler +#define UARTE130_IRQn SERIAL0_IRQn +#define UARTE130_IRQHandler SERIAL0_IRQHandler +#define SPIM131_IRQn SERIAL1_IRQn +#define SPIM131_IRQHandler SERIAL1_IRQHandler +#define SPIS131_IRQn SERIAL1_IRQn +#define SPIS131_IRQHandler SERIAL1_IRQHandler +#define TWIM131_IRQn SERIAL1_IRQn +#define TWIM131_IRQHandler SERIAL1_IRQHandler +#define TWIS131_IRQn SERIAL1_IRQn +#define TWIS131_IRQHandler SERIAL1_IRQHandler +#define UARTE131_IRQn SERIAL1_IRQn +#define UARTE131_IRQHandler SERIAL1_IRQHandler +#define SPIM132_IRQn SERIAL2_IRQn +#define SPIM132_IRQHandler SERIAL2_IRQHandler +#define SPIS132_IRQn SERIAL2_IRQn +#define SPIS132_IRQHandler SERIAL2_IRQHandler +#define TWIM132_IRQn SERIAL2_IRQn +#define TWIM132_IRQHandler SERIAL2_IRQHandler +#define TWIS132_IRQn SERIAL2_IRQn +#define TWIS132_IRQHandler SERIAL2_IRQHandler +#define UARTE132_IRQn SERIAL2_IRQn +#define UARTE132_IRQHandler SERIAL2_IRQHandler +#define SPIM133_IRQn SERIAL3_IRQn +#define SPIM133_IRQHandler SERIAL3_IRQHandler +#define SPIS133_IRQn SERIAL3_IRQn +#define SPIS133_IRQHandler SERIAL3_IRQHandler +#define TWIM133_IRQn SERIAL3_IRQn +#define TWIM133_IRQHandler SERIAL3_IRQHandler +#define TWIS133_IRQn SERIAL3_IRQn +#define TWIS133_IRQHandler SERIAL3_IRQHandler +#define UARTE133_IRQn SERIAL3_IRQn +#define UARTE133_IRQHandler SERIAL3_IRQHandler +#define SPIM134_IRQn SERIAL4_IRQn +#define SPIM134_IRQHandler SERIAL4_IRQHandler +#define SPIS134_IRQn SERIAL4_IRQn +#define SPIS134_IRQHandler SERIAL4_IRQHandler +#define TWIM134_IRQn SERIAL4_IRQn +#define TWIM134_IRQHandler SERIAL4_IRQHandler +#define TWIS134_IRQn SERIAL4_IRQn +#define TWIS134_IRQHandler SERIAL4_IRQHandler +#define UARTE134_IRQn SERIAL4_IRQn +#define UARTE134_IRQHandler SERIAL4_IRQHandler +#define SPIM135_IRQn SERIAL5_IRQn +#define SPIM135_IRQHandler SERIAL5_IRQHandler +#define SPIS135_IRQn SERIAL5_IRQn +#define SPIS135_IRQHandler SERIAL5_IRQHandler +#define TWIM135_IRQn SERIAL5_IRQn +#define TWIM135_IRQHandler SERIAL5_IRQHandler +#define TWIS135_IRQn SERIAL5_IRQn +#define TWIS135_IRQHandler SERIAL5_IRQHandler +#define UARTE135_IRQn SERIAL5_IRQn +#define UARTE135_IRQHandler SERIAL5_IRQHandler +#define SPIM136_IRQn SERIAL6_IRQn +#define SPIM136_IRQHandler SERIAL6_IRQHandler +#define SPIS136_IRQn SERIAL6_IRQn +#define SPIS136_IRQHandler SERIAL6_IRQHandler +#define TWIM136_IRQn SERIAL6_IRQn +#define TWIM136_IRQHandler SERIAL6_IRQHandler +#define TWIS136_IRQn SERIAL6_IRQn +#define TWIS136_IRQHandler SERIAL6_IRQHandler +#define UARTE136_IRQn SERIAL6_IRQn +#define UARTE136_IRQHandler SERIAL6_IRQHandler +#define SPIM137_IRQn SERIAL7_IRQn +#define SPIM137_IRQHandler SERIAL7_IRQHandler +#define SPIS137_IRQn SERIAL7_IRQn +#define SPIS137_IRQHandler SERIAL7_IRQHandler +#define TWIM137_IRQn SERIAL7_IRQn +#define TWIM137_IRQHandler SERIAL7_IRQHandler +#define TWIS137_IRQn SERIAL7_IRQn +#define TWIS137_IRQHandler SERIAL7_IRQHandler +#define UARTE137_IRQn SERIAL7_IRQn +#define UARTE137_IRQHandler SERIAL7_IRQHandler + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals ============================ */ +#define __CM33_REV r0p4 /*!< CM33 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< CPU supports alternate Vector Table address */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ +#define __Vendor_SysTickConfig 0 /*!< Vendor SysTick Config implementation is used */ +#define __SAUREGION_PRESENT 1 /*!< SAU present */ +#define __NUM_SAUREGIONS 4 /*!< Number of regions */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_nrf.h" /*!< nrf9230_enga_radiocore System Library */ + +#endif /*!< NRF_RADIOCORE */ + + +#ifdef NRF_RADIOCORE + + #define NRF_DOMAIN NRF_DOMAIN_RADIOCORE + #define NRF_PROCESSOR NRF_PROCESSOR_RADIOCORE + #define NRF_OWNER NRF_OWNER_RADIOCORE + +#endif /*!< NRF_RADIOCORE */ + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +#define NRF_RADIOCORE_ICACHEDATA_S_BASE 0x03F00000UL +#define NRF_RADIOCORE_ICACHEINFO_S_BASE 0x03F10000UL +#define NRF_RADIOCORE_UICR_NS_BASE 0x0FFFA000UL +#define NRF_RADIOCORE_DCACHEDATA_S_BASE 0x23F00000UL +#define NRF_RADIOCORE_DCACHEINFO_S_BASE 0x23F10000UL +#define NRF_RADIOCORE_ETM_NS_BASE 0xE0041000UL +#define NRF_RADIOCORE_CTI_S_BASE 0xE0042000UL +#define NRF_RADIOCORE_CPUC_S_BASE 0xE0080000UL +#define NRF_RADIOCORE_ICACHE_S_BASE 0xE0082000UL +#define NRF_RADIOCORE_DCACHE_S_BASE 0xE0083000UL +#define NRF_RADIOCORE_SPU000_S_BASE 0x53000000UL +#define NRF_RADIOCORE_MPC_S_BASE 0x53001000UL +#define NRF_RADIOCORE_MVDMA_NS_BASE 0x43003000UL +#define NRF_RADIOCORE_MVDMA_S_BASE 0x53003000UL +#define NRF_RADIOCORE_RAMC000_NS_BASE 0x43004000UL +#define NRF_RADIOCORE_RAMC000_S_BASE 0x53004000UL +#define NRF_RADIOCORE_HSFLL_S_BASE 0x5300D000UL +#define NRF_RADIOCORE_LRCCONF000_S_BASE 0x5300E000UL +#define NRF_RADIOCORE_SPU010_S_BASE 0x53010000UL +#define NRF_RADIOCORE_MEMCONF_NS_BASE 0x43012000UL +#define NRF_RADIOCORE_MEMCONF_S_BASE 0x53012000UL +#define NRF_RADIOCORE_WDT010_NS_BASE 0x43013000UL +#define NRF_RADIOCORE_WDT010_S_BASE 0x53013000UL +#define NRF_RADIOCORE_WDT011_NS_BASE 0x43014000UL +#define NRF_RADIOCORE_WDT011_S_BASE 0x53014000UL +#define NRF_RADIOCORE_LRCCONF010_S_BASE 0x5301E000UL +#define NRF_RADIOCORE_RESETINFO_S_BASE 0x5301E000UL +#define NRF_RADIOCORE_SPU020_S_BASE 0x53020000UL +#define NRF_RADIOCORE_DPPIC020_NS_BASE 0x43022000UL +#define NRF_RADIOCORE_DPPIC020_S_BASE 0x53022000UL +#define NRF_RADIOCORE_PPIB020_S_BASE 0x53023000UL +#define NRF_RADIOCORE_EGU020_NS_BASE 0x43025000UL +#define NRF_RADIOCORE_EGU020_S_BASE 0x53025000UL +#define NRF_RADIOCORE_TIMER020_NS_BASE 0x43028000UL +#define NRF_RADIOCORE_TIMER020_S_BASE 0x53028000UL +#define NRF_RADIOCORE_TIMER021_NS_BASE 0x43029000UL +#define NRF_RADIOCORE_TIMER021_S_BASE 0x53029000UL +#define NRF_RADIOCORE_TIMER022_NS_BASE 0x4302A000UL +#define NRF_RADIOCORE_TIMER022_S_BASE 0x5302A000UL +#define NRF_RADIOCORE_RTC_NS_BASE 0x4302B000UL +#define NRF_RADIOCORE_RTC_S_BASE 0x5302B000UL +#define NRF_RADIOCORE_RADIO_NS_BASE 0x4302C000UL +#define NRF_RADIOCORE_RADIO_S_BASE 0x5302C000UL +#define NRF_RADIOCORE_LRCCONF020_S_BASE 0x5302E000UL +#define NRF_RADIOCORE_SPU030_S_BASE 0x53030000UL +#define NRF_RADIOCORE_PPIB030_S_BASE 0x53031000UL +#define NRF_RADIOCORE_VPR_NS_BASE 0x43034000UL +#define NRF_RADIOCORE_VPR_S_BASE 0x53034000UL +#define NRF_RADIOCORE_RAMC001_NS_BASE 0x43038000UL +#define NRF_RADIOCORE_RAMC001_S_BASE 0x53038000UL +#define NRF_RADIOCORE_AAR030_NS_BASE 0x4303A000UL +#define NRF_RADIOCORE_CCM030_NS_BASE 0x4303A000UL +#define NRF_RADIOCORE_AAR030_S_BASE 0x5303A000UL +#define NRF_RADIOCORE_CCM030_S_BASE 0x5303A000UL +#define NRF_RADIOCORE_ECB030_NS_BASE 0x4303B000UL +#define NRF_RADIOCORE_ECB030_S_BASE 0x5303B000UL +#define NRF_RADIOCORE_AAR031_NS_BASE 0x4303C000UL +#define NRF_RADIOCORE_CCM031_NS_BASE 0x4303C000UL +#define NRF_RADIOCORE_AAR031_S_BASE 0x5303C000UL +#define NRF_RADIOCORE_CCM031_S_BASE 0x5303C000UL +#define NRF_RADIOCORE_ECB031_NS_BASE 0x4303D000UL +#define NRF_RADIOCORE_ECB031_S_BASE 0x5303D000UL +#define NRF_RADIOCORE_IPCT_NS_BASE 0x43024000UL +#define NRF_RADIOCORE_IPCT_S_BASE 0x53024000UL +#define NRF_RADIOCORE_SWI0_NS_BASE 0x42058000UL +#define NRF_RADIOCORE_SWI1_NS_BASE 0x42059000UL +#define NRF_RADIOCORE_SWI2_NS_BASE 0x4205A000UL +#define NRF_RADIOCORE_SWI3_NS_BASE 0x4205B000UL +#define NRF_RADIOCORE_SWI4_NS_BASE 0x4205C000UL +#define NRF_RADIOCORE_SWI5_NS_BASE 0x4205D000UL +#define NRF_RADIOCORE_SWI6_NS_BASE 0x4205E000UL +#define NRF_RADIOCORE_SWI7_NS_BASE 0x4205F000UL +#define NRF_RADIOCORE_BELLBOARD_NS_BASE 0x4F09B000UL +#define NRF_RADIOCORE_BELLBOARD_S_BASE 0x5F09B000UL + +/* =========================================================================================================================== */ +/* ================ Peripheral Declaration ================ */ +/* =========================================================================================================================== */ + +#define NRF_RADIOCORE_ICACHEDATA_S ((NRF_ICACHEDATA_Type*) NRF_RADIOCORE_ICACHEDATA_S_BASE) +#define NRF_RADIOCORE_ICACHEINFO_S ((NRF_ICACHEINFO_Type*) NRF_RADIOCORE_ICACHEINFO_S_BASE) +#define NRF_RADIOCORE_UICR_NS ((NRF_UICR_Type*) NRF_RADIOCORE_UICR_NS_BASE) +#define NRF_RADIOCORE_DCACHEDATA_S ((NRF_DCACHEDATA_Type*) NRF_RADIOCORE_DCACHEDATA_S_BASE) +#define NRF_RADIOCORE_DCACHEINFO_S ((NRF_DCACHEINFO_Type*) NRF_RADIOCORE_DCACHEINFO_S_BASE) +#define NRF_RADIOCORE_ETM_NS ((NRF_ETM_Type*) NRF_RADIOCORE_ETM_NS_BASE) +#define NRF_RADIOCORE_CTI_S ((NRF_CTI_Type*) NRF_RADIOCORE_CTI_S_BASE) +#define NRF_RADIOCORE_CPUC_S ((NRF_CM33SS_Type*) NRF_RADIOCORE_CPUC_S_BASE) +#define NRF_RADIOCORE_ICACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_ICACHE_S_BASE) +#define NRF_RADIOCORE_DCACHE_S ((NRF_CACHE_Type*) NRF_RADIOCORE_DCACHE_S_BASE) +#define NRF_RADIOCORE_SPU000_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU000_S_BASE) +#define NRF_RADIOCORE_MPC_S ((NRF_MPC_Type*) NRF_RADIOCORE_MPC_S_BASE) +#define NRF_RADIOCORE_MVDMA_NS ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_NS_BASE) +#define NRF_RADIOCORE_MVDMA_S ((NRF_MVDMA_Type*) NRF_RADIOCORE_MVDMA_S_BASE) +#define NRF_RADIOCORE_RAMC000_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_NS_BASE) +#define NRF_RADIOCORE_RAMC000_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC000_S_BASE) +#define NRF_RADIOCORE_HSFLL_S ((NRF_HSFLL_Type*) NRF_RADIOCORE_HSFLL_S_BASE) +#define NRF_RADIOCORE_LRCCONF000_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF000_S_BASE) +#define NRF_RADIOCORE_SPU010_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU010_S_BASE) +#define NRF_RADIOCORE_MEMCONF_NS ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_NS_BASE) +#define NRF_RADIOCORE_MEMCONF_S ((NRF_MEMCONF_Type*) NRF_RADIOCORE_MEMCONF_S_BASE) +#define NRF_RADIOCORE_WDT010_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_NS_BASE) +#define NRF_RADIOCORE_WDT010_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT010_S_BASE) +#define NRF_RADIOCORE_WDT011_NS ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_NS_BASE) +#define NRF_RADIOCORE_WDT011_S ((NRF_WDT_Type*) NRF_RADIOCORE_WDT011_S_BASE) +#define NRF_RADIOCORE_LRCCONF010_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF010_S_BASE) +#define NRF_RADIOCORE_RESETINFO_S ((NRF_RESETINFO_Type*) NRF_RADIOCORE_RESETINFO_S_BASE) +#define NRF_RADIOCORE_SPU020_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU020_S_BASE) +#define NRF_RADIOCORE_DPPIC020_NS ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_NS_BASE) +#define NRF_RADIOCORE_DPPIC020_S ((NRF_DPPIC_Type*) NRF_RADIOCORE_DPPIC020_S_BASE) +#define NRF_RADIOCORE_PPIB020_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB020_S_BASE) +#define NRF_RADIOCORE_EGU020_NS ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_NS_BASE) +#define NRF_RADIOCORE_EGU020_S ((NRF_EGU_Type*) NRF_RADIOCORE_EGU020_S_BASE) +#define NRF_RADIOCORE_TIMER020_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_NS_BASE) +#define NRF_RADIOCORE_TIMER020_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER020_S_BASE) +#define NRF_RADIOCORE_TIMER021_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_NS_BASE) +#define NRF_RADIOCORE_TIMER021_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER021_S_BASE) +#define NRF_RADIOCORE_TIMER022_NS ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_NS_BASE) +#define NRF_RADIOCORE_TIMER022_S ((NRF_TIMER_Type*) NRF_RADIOCORE_TIMER022_S_BASE) +#define NRF_RADIOCORE_RTC_NS ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_NS_BASE) +#define NRF_RADIOCORE_RTC_S ((NRF_RTC_Type*) NRF_RADIOCORE_RTC_S_BASE) +#define NRF_RADIOCORE_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_NS_BASE) +#define NRF_RADIOCORE_RADIO_S ((NRF_RADIO_Type*) NRF_RADIOCORE_RADIO_S_BASE) +#define NRF_RADIOCORE_LRCCONF020_S ((NRF_LRCCONF_Type*) NRF_RADIOCORE_LRCCONF020_S_BASE) +#define NRF_RADIOCORE_SPU030_S ((NRF_SPU_Type*) NRF_RADIOCORE_SPU030_S_BASE) +#define NRF_RADIOCORE_PPIB030_S ((NRF_PPIB_Type*) NRF_RADIOCORE_PPIB030_S_BASE) +#define NRF_RADIOCORE_VPR_NS ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_NS_BASE) +#define NRF_RADIOCORE_VPR_S ((NRF_VPR_Type*) NRF_RADIOCORE_VPR_S_BASE) +#define NRF_RADIOCORE_RAMC001_NS ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_NS_BASE) +#define NRF_RADIOCORE_RAMC001_S ((NRF_RAMC_Type*) NRF_RADIOCORE_RAMC001_S_BASE) +#define NRF_RADIOCORE_AAR030_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_NS_BASE) +#define NRF_RADIOCORE_CCM030_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_NS_BASE) +#define NRF_RADIOCORE_AAR030_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR030_S_BASE) +#define NRF_RADIOCORE_CCM030_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM030_S_BASE) +#define NRF_RADIOCORE_ECB030_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_NS_BASE) +#define NRF_RADIOCORE_ECB030_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB030_S_BASE) +#define NRF_RADIOCORE_AAR031_NS ((NRF_AAR_Type*) NRF_RADIOCORE_AAR031_NS_BASE) +#define NRF_RADIOCORE_CCM031_NS ((NRF_CCM_Type*) NRF_RADIOCORE_CCM031_NS_BASE) +#define NRF_RADIOCORE_AAR031_S ((NRF_AAR_Type*) NRF_RADIOCORE_AAR031_S_BASE) +#define NRF_RADIOCORE_CCM031_S ((NRF_CCM_Type*) NRF_RADIOCORE_CCM031_S_BASE) +#define NRF_RADIOCORE_ECB031_NS ((NRF_ECB_Type*) NRF_RADIOCORE_ECB031_NS_BASE) +#define NRF_RADIOCORE_ECB031_S ((NRF_ECB_Type*) NRF_RADIOCORE_ECB031_S_BASE) +#define NRF_RADIOCORE_IPCT_NS ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_NS_BASE) +#define NRF_RADIOCORE_IPCT_S ((NRF_IPCT_Type*) NRF_RADIOCORE_IPCT_S_BASE) +#define NRF_RADIOCORE_SWI0_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI0_NS_BASE) +#define NRF_RADIOCORE_SWI1_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI1_NS_BASE) +#define NRF_RADIOCORE_SWI2_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI2_NS_BASE) +#define NRF_RADIOCORE_SWI3_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI3_NS_BASE) +#define NRF_RADIOCORE_SWI4_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI4_NS_BASE) +#define NRF_RADIOCORE_SWI5_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI5_NS_BASE) +#define NRF_RADIOCORE_SWI6_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI6_NS_BASE) +#define NRF_RADIOCORE_SWI7_NS ((NRF_SWI_Type*) NRF_RADIOCORE_SWI7_NS_BASE) +#define NRF_RADIOCORE_BELLBOARD_NS ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_NS_BASE) +#define NRF_RADIOCORE_BELLBOARD_S ((NRF_BELLBOARD_Type*) NRF_RADIOCORE_BELLBOARD_S_BASE) + +/* =========================================================================================================================== */ +/* ================ TrustZone Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ + #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS + #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS + #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_NS + #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_NS + #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_NS + #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_NS + #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_NS + #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_NS + #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_NS + #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_NS + #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_NS + #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_NS + #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_NS + #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_NS + #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_NS + #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_NS + #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_NS + #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_NS + #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_NS + #define NRF_RADIOCORE_AAR031 NRF_RADIOCORE_AAR031_NS + #define NRF_RADIOCORE_CCM031 NRF_RADIOCORE_CCM031_NS + #define NRF_RADIOCORE_ECB031 NRF_RADIOCORE_ECB031_NS + #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_NS + #define NRF_RADIOCORE_SWI0 NRF_RADIOCORE_SWI0_NS + #define NRF_RADIOCORE_SWI1 NRF_RADIOCORE_SWI1_NS + #define NRF_RADIOCORE_SWI2 NRF_RADIOCORE_SWI2_NS + #define NRF_RADIOCORE_SWI3 NRF_RADIOCORE_SWI3_NS + #define NRF_RADIOCORE_SWI4 NRF_RADIOCORE_SWI4_NS + #define NRF_RADIOCORE_SWI5 NRF_RADIOCORE_SWI5_NS + #define NRF_RADIOCORE_SWI6 NRF_RADIOCORE_SWI6_NS + #define NRF_RADIOCORE_SWI7 NRF_RADIOCORE_SWI7_NS + #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_NS +#else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ + #define NRF_RADIOCORE_ICACHEDATA NRF_RADIOCORE_ICACHEDATA_S + #define NRF_RADIOCORE_ICACHEINFO NRF_RADIOCORE_ICACHEINFO_S + #define NRF_RADIOCORE_UICR NRF_RADIOCORE_UICR_NS + #define NRF_RADIOCORE_DCACHEDATA NRF_RADIOCORE_DCACHEDATA_S + #define NRF_RADIOCORE_DCACHEINFO NRF_RADIOCORE_DCACHEINFO_S + #define NRF_RADIOCORE_ETM NRF_RADIOCORE_ETM_NS + #define NRF_RADIOCORE_CTI NRF_RADIOCORE_CTI_S + #define NRF_RADIOCORE_CPUC NRF_RADIOCORE_CPUC_S + #define NRF_RADIOCORE_ICACHE NRF_RADIOCORE_ICACHE_S + #define NRF_RADIOCORE_DCACHE NRF_RADIOCORE_DCACHE_S + #define NRF_RADIOCORE_SPU000 NRF_RADIOCORE_SPU000_S + #define NRF_RADIOCORE_MPC NRF_RADIOCORE_MPC_S + #define NRF_RADIOCORE_MVDMA NRF_RADIOCORE_MVDMA_S + #define NRF_RADIOCORE_RAMC000 NRF_RADIOCORE_RAMC000_S + #define NRF_RADIOCORE_HSFLL NRF_RADIOCORE_HSFLL_S + #define NRF_RADIOCORE_LRCCONF000 NRF_RADIOCORE_LRCCONF000_S + #define NRF_RADIOCORE_SPU010 NRF_RADIOCORE_SPU010_S + #define NRF_RADIOCORE_MEMCONF NRF_RADIOCORE_MEMCONF_S + #define NRF_RADIOCORE_WDT010 NRF_RADIOCORE_WDT010_S + #define NRF_RADIOCORE_WDT011 NRF_RADIOCORE_WDT011_S + #define NRF_RADIOCORE_LRCCONF010 NRF_RADIOCORE_LRCCONF010_S + #define NRF_RADIOCORE_RESETINFO NRF_RADIOCORE_RESETINFO_S + #define NRF_RADIOCORE_SPU020 NRF_RADIOCORE_SPU020_S + #define NRF_RADIOCORE_DPPIC020 NRF_RADIOCORE_DPPIC020_S + #define NRF_RADIOCORE_PPIB020 NRF_RADIOCORE_PPIB020_S + #define NRF_RADIOCORE_EGU020 NRF_RADIOCORE_EGU020_S + #define NRF_RADIOCORE_TIMER020 NRF_RADIOCORE_TIMER020_S + #define NRF_RADIOCORE_TIMER021 NRF_RADIOCORE_TIMER021_S + #define NRF_RADIOCORE_TIMER022 NRF_RADIOCORE_TIMER022_S + #define NRF_RADIOCORE_RTC NRF_RADIOCORE_RTC_S + #define NRF_RADIOCORE_RADIO NRF_RADIOCORE_RADIO_S + #define NRF_RADIOCORE_LRCCONF020 NRF_RADIOCORE_LRCCONF020_S + #define NRF_RADIOCORE_SPU030 NRF_RADIOCORE_SPU030_S + #define NRF_RADIOCORE_PPIB030 NRF_RADIOCORE_PPIB030_S + #define NRF_RADIOCORE_VPR NRF_RADIOCORE_VPR_S + #define NRF_RADIOCORE_RAMC001 NRF_RADIOCORE_RAMC001_S + #define NRF_RADIOCORE_AAR030 NRF_RADIOCORE_AAR030_S + #define NRF_RADIOCORE_CCM030 NRF_RADIOCORE_CCM030_S + #define NRF_RADIOCORE_ECB030 NRF_RADIOCORE_ECB030_S + #define NRF_RADIOCORE_AAR031 NRF_RADIOCORE_AAR031_S + #define NRF_RADIOCORE_CCM031 NRF_RADIOCORE_CCM031_S + #define NRF_RADIOCORE_ECB031 NRF_RADIOCORE_ECB031_S + #define NRF_RADIOCORE_IPCT NRF_RADIOCORE_IPCT_S + #define NRF_RADIOCORE_SWI0 NRF_RADIOCORE_SWI0_NS + #define NRF_RADIOCORE_SWI1 NRF_RADIOCORE_SWI1_NS + #define NRF_RADIOCORE_SWI2 NRF_RADIOCORE_SWI2_NS + #define NRF_RADIOCORE_SWI3 NRF_RADIOCORE_SWI3_NS + #define NRF_RADIOCORE_SWI4 NRF_RADIOCORE_SWI4_NS + #define NRF_RADIOCORE_SWI5 NRF_RADIOCORE_SWI5_NS + #define NRF_RADIOCORE_SWI6 NRF_RADIOCORE_SWI6_NS + #define NRF_RADIOCORE_SWI7 NRF_RADIOCORE_SWI7_NS + #define NRF_RADIOCORE_BELLBOARD NRF_RADIOCORE_BELLBOARD_S +#endif /*!< NRF_TRUSTZONE_NONSECURE */ + +/* =========================================================================================================================== */ +/* ================ Local Domain Remapping ================ */ +/* =========================================================================================================================== */ + +#ifdef NRF_RADIOCORE /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ + #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ + #define NRF_UICR NRF_RADIOCORE_UICR + #define NRF_ETM NRF_RADIOCORE_ETM + #define NRF_MVDMA NRF_RADIOCORE_MVDMA + #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 + #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF + #define NRF_WDT010 NRF_RADIOCORE_WDT010 + #define NRF_WDT011 NRF_RADIOCORE_WDT011 + #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 + #define NRF_EGU020 NRF_RADIOCORE_EGU020 + #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 + #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 + #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 + #define NRF_RTC NRF_RADIOCORE_RTC + #define NRF_RADIO NRF_RADIOCORE_RADIO + #define NRF_VPR NRF_RADIOCORE_VPR + #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 + #define NRF_AAR030 NRF_RADIOCORE_AAR030 + #define NRF_CCM030 NRF_RADIOCORE_CCM030 + #define NRF_ECB030 NRF_RADIOCORE_ECB030 + #define NRF_AAR031 NRF_RADIOCORE_AAR031 + #define NRF_CCM031 NRF_RADIOCORE_CCM031 + #define NRF_ECB031 NRF_RADIOCORE_ECB031 + #define NRF_IPCT NRF_RADIOCORE_IPCT + #define NRF_SWI0 NRF_RADIOCORE_SWI0 + #define NRF_SWI1 NRF_RADIOCORE_SWI1 + #define NRF_SWI2 NRF_RADIOCORE_SWI2 + #define NRF_SWI3 NRF_RADIOCORE_SWI3 + #define NRF_SWI4 NRF_RADIOCORE_SWI4 + #define NRF_SWI5 NRF_RADIOCORE_SWI5 + #define NRF_SWI6 NRF_RADIOCORE_SWI6 + #define NRF_SWI7 NRF_RADIOCORE_SWI7 + #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD + #else /*!< Remap all instances. */ + #define NRF_ICACHEDATA NRF_RADIOCORE_ICACHEDATA + #define NRF_ICACHEINFO NRF_RADIOCORE_ICACHEINFO + #define NRF_UICR NRF_RADIOCORE_UICR + #define NRF_DCACHEDATA NRF_RADIOCORE_DCACHEDATA + #define NRF_DCACHEINFO NRF_RADIOCORE_DCACHEINFO + #define NRF_ETM NRF_RADIOCORE_ETM + #define NRF_CTI NRF_RADIOCORE_CTI + #define NRF_CPUC NRF_RADIOCORE_CPUC + #define NRF_ICACHE NRF_RADIOCORE_ICACHE + #define NRF_DCACHE NRF_RADIOCORE_DCACHE + #define NRF_SPU000 NRF_RADIOCORE_SPU000 + #define NRF_MPC NRF_RADIOCORE_MPC + #define NRF_MVDMA NRF_RADIOCORE_MVDMA + #define NRF_RAMC000 NRF_RADIOCORE_RAMC000 + #define NRF_HSFLL NRF_RADIOCORE_HSFLL + #define NRF_LRCCONF000 NRF_RADIOCORE_LRCCONF000 + #define NRF_SPU010 NRF_RADIOCORE_SPU010 + #define NRF_MEMCONF NRF_RADIOCORE_MEMCONF + #define NRF_WDT010 NRF_RADIOCORE_WDT010 + #define NRF_WDT011 NRF_RADIOCORE_WDT011 + #define NRF_LRCCONF010 NRF_RADIOCORE_LRCCONF010 + #define NRF_RESETINFO NRF_RADIOCORE_RESETINFO + #define NRF_SPU020 NRF_RADIOCORE_SPU020 + #define NRF_DPPIC020 NRF_RADIOCORE_DPPIC020 + #define NRF_PPIB020 NRF_RADIOCORE_PPIB020 + #define NRF_EGU020 NRF_RADIOCORE_EGU020 + #define NRF_TIMER020 NRF_RADIOCORE_TIMER020 + #define NRF_TIMER021 NRF_RADIOCORE_TIMER021 + #define NRF_TIMER022 NRF_RADIOCORE_TIMER022 + #define NRF_RTC NRF_RADIOCORE_RTC + #define NRF_RADIO NRF_RADIOCORE_RADIO + #define NRF_LRCCONF020 NRF_RADIOCORE_LRCCONF020 + #define NRF_SPU030 NRF_RADIOCORE_SPU030 + #define NRF_PPIB030 NRF_RADIOCORE_PPIB030 + #define NRF_VPR NRF_RADIOCORE_VPR + #define NRF_RAMC001 NRF_RADIOCORE_RAMC001 + #define NRF_AAR030 NRF_RADIOCORE_AAR030 + #define NRF_CCM030 NRF_RADIOCORE_CCM030 + #define NRF_ECB030 NRF_RADIOCORE_ECB030 + #define NRF_AAR031 NRF_RADIOCORE_AAR031 + #define NRF_CCM031 NRF_RADIOCORE_CCM031 + #define NRF_ECB031 NRF_RADIOCORE_ECB031 + #define NRF_IPCT NRF_RADIOCORE_IPCT + #define NRF_SWI0 NRF_RADIOCORE_SWI0 + #define NRF_SWI1 NRF_RADIOCORE_SWI1 + #define NRF_SWI2 NRF_RADIOCORE_SWI2 + #define NRF_SWI3 NRF_RADIOCORE_SWI3 + #define NRF_SWI4 NRF_RADIOCORE_SWI4 + #define NRF_SWI5 NRF_RADIOCORE_SWI5 + #define NRF_SWI6 NRF_RADIOCORE_SWI6 + #define NRF_SWI7 NRF_RADIOCORE_SWI7 + #define NRF_BELLBOARD NRF_RADIOCORE_BELLBOARD + #endif /*!< NRF_TRUSTZONE_NONSECURE */ +#endif /*!< NRF_RADIOCORE */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_RADIOCORE_H */ + diff --git a/mdk/nrf9230_enga_radiocore.svd b/mdk/nrf9230_enga_radiocore.svd new file mode 100644 index 000000000..9312d67aa --- /dev/null +++ b/mdk/nrf9230_enga_radiocore.svd @@ -0,0 +1,198206 @@ + + + + Nordic Semiconductor + Nordic + nrf9230_enga_radiocore + nRF92 + 1 + nRF9230_enga reference description for system-on-chip with many ARM 32-bit Cortex-M33 microcontrollers + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + NRF_ + + CM33 + r0p4 + little + 1 + 1 + 3 + 0 + 480 + 4 + + system_nrf9230_enga_radiocore + + 480 + + + + ICACHEDATA_S + CACHEDATA + 0x03F00000 + ICACHEDATA + + + + 0 + 0x1000 + registers + + ICACHEDATA + 0x20 + + + 1024 + 0x040 + SET[%s] + Unspecified + ICACHEDATA_SET + read-write + 0x0 + + 2 + 0x020 + WAY[%s] + Unspecified + ICACHEDATA_SET_WAY + read-write + 0x0 + + 4 + 0x008 + DU[%s] + Unspecified + ICACHEDATA_SET_WAY_DU + read-write + 0x0 + + 0x2 + 0x4 + DATA[%s] + Description collection: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + Data + Data + 0 + 31 + read-only + + + + + + + + + + ICACHEINFO_S + CACHEINFO + 0x03F10000 + ICACHEINFO + + + + 0 + 0x1000 + registers + + ICACHEINFO + 0x20 + + + 1024 + 0x008 + SET[%s] + Unspecified + ICACHEINFO_SET + read-write + 0x0 + + 2 + 0x004 + WAY[%s] + Unspecified + ICACHEINFO_SET_WAY + read-write + 0x0 + + INFO + Description cluster: Cache information for SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + TAG + Cache tag. + 0 + 19 + read-only + + + DUV_0 + Data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_1 + Data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_2 + Data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_3 + Data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + D0 + Dirty status of combined data unit 0 and 1. + 28 + 28 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D1 + Dirty status of combined data unit 2 and 3. + 29 + 29 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + V + Line valid bit. + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0x0 + + + Valid + Valid cache line + 0x1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0x0 + + + Way1 + Way1 was most recently used + 0x1 + + + + + + + + + + + UICR_NS + User information configuration registers + 0x0FFFA000 + UICR + + + + 0 + 0x800 + registers + + UICR + 0x20 + + + 16 + 0x008 + MEM[%s] + Unspecified + UICR_MEM + read-write + 0x000 + + CONFIG + Description cluster: Memory configuration of the memory region + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + READ + 0 + 0 + + + NotAllowed + Read access to MEM[n] is not allowed + 0x1 + + + Allowed + Read access to MEM[n] is allowed + 0x0 + + + + + WRITE + 1 + 1 + + + NotAllowed + Write access to MEM[n] is not allowed + 0x1 + + + Allowed + Write access to MEM[n] is allowed + 0x0 + + + + + EXECUTE + 2 + 2 + + + NotAllowed + SW execution from MEM[n] is not allowed + 0x1 + + + Allowed + SW execution from MEM[n] is allowed + 0x0 + + + + + SECURE + 3 + 3 + + + Secure + Non-secure access to MEM[n] is not allowed + 0x1 + + + NonSecure + Non-secure access to MEM[n] is allowed + 0x0 + + + + + NSC + 4 + 4 + + + Disabled + Memory region is not non-secure callable + 0x1 + + + Enabled + Memory region is non-secure callable + 0x0 + + + + + OWNERID + Memory owner identification + 8 + 11 + + + ADDRESS + Memory region start address, bits [31:12] + 12 + 31 + + + + + SIZE + Description cluster: Size of the memory region + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + SIZE + Memory size in bytes + 0 + 31 + + + + + + 192 + 0x004 + PERIPH[%s] + Unspecified + UICR_PERIPH + read-write + 0x100 + + CONFIG + Description cluster: Peripheral configuration + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SECURE + Peripheral security mapping + 3 + 3 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + Peripheral is mapped in non-secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + PROCESSOR + Processor ID of the processor that will receive the peripheral IRQ + 8 + 11 + + + ADDRESS + Peripheral address, bits [31:12] + 12 + 31 + + + + + + 4 + 0x00C + GPIOTE[%s] + Unspecified + UICR_GPIOTE + read-write + 0x480 + + INSTANCE + Description cluster: Address of the GPIOTE instance associated with GPIOTE[n] + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_GPIOTE_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of GPIOTE[n] + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of GPIOTE[n] + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + + IPCT + Unspecified + UICR_IPCT + read-write + 0x4B0 + + LOCAL + Unspecified + UICR_IPCT_LOCAL + read-write + 0x000 + + CH + Unspecified + UICR_IPCT_LOCAL_CH + read-write + 0x000 + + SECURE + Request permission for the channels of IPCT in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + INTERRUPT + Unspecified + UICR_IPCT_LOCAL_INTERRUPT + read-write + 0x004 + + SECURE + Request permission for the interrupts of IPCT in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + Secure + The interrupt 0 is secure + 0x1 + + + NonSecure + The interrupt 0 is non-secure + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + Secure + The interrupt 1 is secure + 0x1 + + + NonSecure + The interrupt 1 is non-secure + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + Secure + The interrupt 2 is secure + 0x1 + + + NonSecure + The interrupt 2 is non-secure + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + Secure + The interrupt 3 is secure + 0x1 + + + NonSecure + The interrupt 3 is non-secure + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + Secure + The interrupt 4 is secure + 0x1 + + + NonSecure + The interrupt 4 is non-secure + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + Secure + The interrupt 5 is secure + 0x1 + + + NonSecure + The interrupt 5 is non-secure + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + Secure + The interrupt 6 is secure + 0x1 + + + NonSecure + The interrupt 6 is non-secure + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + Secure + The interrupt 7 is secure + 0x1 + + + NonSecure + The interrupt 7 is non-secure + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + Secure + The interrupt 8 is secure + 0x1 + + + NonSecure + The interrupt 8 is non-secure + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + Secure + The interrupt 9 is secure + 0x1 + + + NonSecure + The interrupt 9 is non-secure + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + Secure + The interrupt 10 is secure + 0x1 + + + NonSecure + The interrupt 10 is non-secure + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + Secure + The interrupt 11 is secure + 0x1 + + + NonSecure + The interrupt 11 is non-secure + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + Secure + The interrupt 12 is secure + 0x1 + + + NonSecure + The interrupt 12 is non-secure + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + Secure + The interrupt 13 is secure + 0x1 + + + NonSecure + The interrupt 13 is non-secure + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + Secure + The interrupt 14 is secure + 0x1 + + + NonSecure + The interrupt 14 is non-secure + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + Secure + The interrupt 15 is secure + 0x1 + + + NonSecure + The interrupt 15 is non-secure + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + Secure + The interrupt 16 is secure + 0x1 + + + NonSecure + The interrupt 16 is non-secure + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + Secure + The interrupt 17 is secure + 0x1 + + + NonSecure + The interrupt 17 is non-secure + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + Secure + The interrupt 18 is secure + 0x1 + + + NonSecure + The interrupt 18 is non-secure + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + Secure + The interrupt 19 is secure + 0x1 + + + NonSecure + The interrupt 19 is non-secure + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + Secure + The interrupt 20 is secure + 0x1 + + + NonSecure + The interrupt 20 is non-secure + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + Secure + The interrupt 21 is secure + 0x1 + + + NonSecure + The interrupt 21 is non-secure + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + Secure + The interrupt 22 is secure + 0x1 + + + NonSecure + The interrupt 22 is non-secure + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + Secure + The interrupt 23 is secure + 0x1 + + + NonSecure + The interrupt 23 is non-secure + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + Secure + The interrupt 24 is secure + 0x1 + + + NonSecure + The interrupt 24 is non-secure + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + Secure + The interrupt 25 is secure + 0x1 + + + NonSecure + The interrupt 25 is non-secure + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + Secure + The interrupt 26 is secure + 0x1 + + + NonSecure + The interrupt 26 is non-secure + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + Secure + The interrupt 27 is secure + 0x1 + + + NonSecure + The interrupt 27 is non-secure + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + Secure + The interrupt 28 is secure + 0x1 + + + NonSecure + The interrupt 28 is non-secure + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + Secure + The interrupt 29 is secure + 0x1 + + + NonSecure + The interrupt 29 is non-secure + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + Secure + The interrupt 30 is secure + 0x1 + + + NonSecure + The interrupt 30 is non-secure + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + Secure + The interrupt 31 is secure + 0x1 + + + NonSecure + The interrupt 31 is non-secure + 0x0 + + + + + + + + + 2 + 0x014 + GLOBAL[%s] + Unspecified + UICR_IPCT_GLOBAL + read-write + 0x008 + + INSTANCE + Description cluster: Address of the IPCT instance associated with IPCT[n].GLOBAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_IPCT_GLOBAL_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of IPCT[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of IPCT[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + + INTERRUPT + Unspecified + UICR_IPCT_GLOBAL_INTERRUPT + read-write + 0x00C + + OWN + Description cluster: Request ownership of the interrupts of IPCT[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + NotOwn + Do not own the interrupt 0 + 0x1 + + + Own + Own the interrupt 0 + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + NotOwn + Do not own the interrupt 1 + 0x1 + + + Own + Own the interrupt 1 + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + NotOwn + Do not own the interrupt 2 + 0x1 + + + Own + Own the interrupt 2 + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + NotOwn + Do not own the interrupt 3 + 0x1 + + + Own + Own the interrupt 3 + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + NotOwn + Do not own the interrupt 4 + 0x1 + + + Own + Own the interrupt 4 + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + NotOwn + Do not own the interrupt 5 + 0x1 + + + Own + Own the interrupt 5 + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + NotOwn + Do not own the interrupt 6 + 0x1 + + + Own + Own the interrupt 6 + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + NotOwn + Do not own the interrupt 7 + 0x1 + + + Own + Own the interrupt 7 + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + NotOwn + Do not own the interrupt 8 + 0x1 + + + Own + Own the interrupt 8 + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + NotOwn + Do not own the interrupt 9 + 0x1 + + + Own + Own the interrupt 9 + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + NotOwn + Do not own the interrupt 10 + 0x1 + + + Own + Own the interrupt 10 + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + NotOwn + Do not own the interrupt 11 + 0x1 + + + Own + Own the interrupt 11 + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + NotOwn + Do not own the interrupt 12 + 0x1 + + + Own + Own the interrupt 12 + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + NotOwn + Do not own the interrupt 13 + 0x1 + + + Own + Own the interrupt 13 + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + NotOwn + Do not own the interrupt 14 + 0x1 + + + Own + Own the interrupt 14 + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + NotOwn + Do not own the interrupt 15 + 0x1 + + + Own + Own the interrupt 15 + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + NotOwn + Do not own the interrupt 16 + 0x1 + + + Own + Own the interrupt 16 + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + NotOwn + Do not own the interrupt 17 + 0x1 + + + Own + Own the interrupt 17 + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + NotOwn + Do not own the interrupt 18 + 0x1 + + + Own + Own the interrupt 18 + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + NotOwn + Do not own the interrupt 19 + 0x1 + + + Own + Own the interrupt 19 + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + NotOwn + Do not own the interrupt 20 + 0x1 + + + Own + Own the interrupt 20 + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + NotOwn + Do not own the interrupt 21 + 0x1 + + + Own + Own the interrupt 21 + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + NotOwn + Do not own the interrupt 22 + 0x1 + + + Own + Own the interrupt 22 + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + NotOwn + Do not own the interrupt 23 + 0x1 + + + Own + Own the interrupt 23 + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + NotOwn + Do not own the interrupt 24 + 0x1 + + + Own + Own the interrupt 24 + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + NotOwn + Do not own the interrupt 25 + 0x1 + + + Own + Own the interrupt 25 + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + NotOwn + Do not own the interrupt 26 + 0x1 + + + Own + Own the interrupt 26 + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + NotOwn + Do not own the interrupt 27 + 0x1 + + + Own + Own the interrupt 27 + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + NotOwn + Do not own the interrupt 28 + 0x1 + + + Own + Own the interrupt 28 + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + NotOwn + Do not own the interrupt 29 + 0x1 + + + Own + Own the interrupt 29 + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + NotOwn + Do not own the interrupt 30 + 0x1 + + + Own + Own the interrupt 30 + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + NotOwn + Do not own the interrupt 31 + 0x1 + + + Own + Own the interrupt 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the interrupts of IPCT[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + INT_0 + Interrupt number + 0 + 0 + + + Secure + The interrupt 0 is secure + 0x1 + + + NonSecure + The interrupt 0 is non-secure + 0x0 + + + + + INT_1 + Interrupt number + 1 + 1 + + + Secure + The interrupt 1 is secure + 0x1 + + + NonSecure + The interrupt 1 is non-secure + 0x0 + + + + + INT_2 + Interrupt number + 2 + 2 + + + Secure + The interrupt 2 is secure + 0x1 + + + NonSecure + The interrupt 2 is non-secure + 0x0 + + + + + INT_3 + Interrupt number + 3 + 3 + + + Secure + The interrupt 3 is secure + 0x1 + + + NonSecure + The interrupt 3 is non-secure + 0x0 + + + + + INT_4 + Interrupt number + 4 + 4 + + + Secure + The interrupt 4 is secure + 0x1 + + + NonSecure + The interrupt 4 is non-secure + 0x0 + + + + + INT_5 + Interrupt number + 5 + 5 + + + Secure + The interrupt 5 is secure + 0x1 + + + NonSecure + The interrupt 5 is non-secure + 0x0 + + + + + INT_6 + Interrupt number + 6 + 6 + + + Secure + The interrupt 6 is secure + 0x1 + + + NonSecure + The interrupt 6 is non-secure + 0x0 + + + + + INT_7 + Interrupt number + 7 + 7 + + + Secure + The interrupt 7 is secure + 0x1 + + + NonSecure + The interrupt 7 is non-secure + 0x0 + + + + + INT_8 + Interrupt number + 8 + 8 + + + Secure + The interrupt 8 is secure + 0x1 + + + NonSecure + The interrupt 8 is non-secure + 0x0 + + + + + INT_9 + Interrupt number + 9 + 9 + + + Secure + The interrupt 9 is secure + 0x1 + + + NonSecure + The interrupt 9 is non-secure + 0x0 + + + + + INT_10 + Interrupt number + 10 + 10 + + + Secure + The interrupt 10 is secure + 0x1 + + + NonSecure + The interrupt 10 is non-secure + 0x0 + + + + + INT_11 + Interrupt number + 11 + 11 + + + Secure + The interrupt 11 is secure + 0x1 + + + NonSecure + The interrupt 11 is non-secure + 0x0 + + + + + INT_12 + Interrupt number + 12 + 12 + + + Secure + The interrupt 12 is secure + 0x1 + + + NonSecure + The interrupt 12 is non-secure + 0x0 + + + + + INT_13 + Interrupt number + 13 + 13 + + + Secure + The interrupt 13 is secure + 0x1 + + + NonSecure + The interrupt 13 is non-secure + 0x0 + + + + + INT_14 + Interrupt number + 14 + 14 + + + Secure + The interrupt 14 is secure + 0x1 + + + NonSecure + The interrupt 14 is non-secure + 0x0 + + + + + INT_15 + Interrupt number + 15 + 15 + + + Secure + The interrupt 15 is secure + 0x1 + + + NonSecure + The interrupt 15 is non-secure + 0x0 + + + + + INT_16 + Interrupt number + 16 + 16 + + + Secure + The interrupt 16 is secure + 0x1 + + + NonSecure + The interrupt 16 is non-secure + 0x0 + + + + + INT_17 + Interrupt number + 17 + 17 + + + Secure + The interrupt 17 is secure + 0x1 + + + NonSecure + The interrupt 17 is non-secure + 0x0 + + + + + INT_18 + Interrupt number + 18 + 18 + + + Secure + The interrupt 18 is secure + 0x1 + + + NonSecure + The interrupt 18 is non-secure + 0x0 + + + + + INT_19 + Interrupt number + 19 + 19 + + + Secure + The interrupt 19 is secure + 0x1 + + + NonSecure + The interrupt 19 is non-secure + 0x0 + + + + + INT_20 + Interrupt number + 20 + 20 + + + Secure + The interrupt 20 is secure + 0x1 + + + NonSecure + The interrupt 20 is non-secure + 0x0 + + + + + INT_21 + Interrupt number + 21 + 21 + + + Secure + The interrupt 21 is secure + 0x1 + + + NonSecure + The interrupt 21 is non-secure + 0x0 + + + + + INT_22 + Interrupt number + 22 + 22 + + + Secure + The interrupt 22 is secure + 0x1 + + + NonSecure + The interrupt 22 is non-secure + 0x0 + + + + + INT_23 + Interrupt number + 23 + 23 + + + Secure + The interrupt 23 is secure + 0x1 + + + NonSecure + The interrupt 23 is non-secure + 0x0 + + + + + INT_24 + Interrupt number + 24 + 24 + + + Secure + The interrupt 24 is secure + 0x1 + + + NonSecure + The interrupt 24 is non-secure + 0x0 + + + + + INT_25 + Interrupt number + 25 + 25 + + + Secure + The interrupt 25 is secure + 0x1 + + + NonSecure + The interrupt 25 is non-secure + 0x0 + + + + + INT_26 + Interrupt number + 26 + 26 + + + Secure + The interrupt 26 is secure + 0x1 + + + NonSecure + The interrupt 26 is non-secure + 0x0 + + + + + INT_27 + Interrupt number + 27 + 27 + + + Secure + The interrupt 27 is secure + 0x1 + + + NonSecure + The interrupt 27 is non-secure + 0x0 + + + + + INT_28 + Interrupt number + 28 + 28 + + + Secure + The interrupt 28 is secure + 0x1 + + + NonSecure + The interrupt 28 is non-secure + 0x0 + + + + + INT_29 + Interrupt number + 29 + 29 + + + Secure + The interrupt 29 is secure + 0x1 + + + NonSecure + The interrupt 29 is non-secure + 0x0 + + + + + INT_30 + Interrupt number + 30 + 30 + + + Secure + The interrupt 30 is secure + 0x1 + + + NonSecure + The interrupt 30 is non-secure + 0x0 + + + + + INT_31 + Interrupt number + 31 + 31 + + + Secure + The interrupt 31 is secure + 0x1 + + + NonSecure + The interrupt 31 is non-secure + 0x0 + + + + + + + + + + DPPI + Unspecified + UICR_DPPI + read-write + 0x4E0 + + 2 + 0x014 + LOCAL[%s] + Unspecified + UICR_DPPI_LOCAL + read-write + 0x000 + + INSTANCE + Description cluster: Address of the DPPI instance associated with DPPI[n].LOCAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_DPPI_LOCAL_CH + read-write + 0x004 + + SECURE + Description cluster: Request permission for the channels of DPPI[n] in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + LINK + Unspecified + UICR_DPPI_LOCAL_CH_LINK + read-write + 0x004 + + DIR + Description cluster: Request linking the channels of DPPI[n] in local domain as source or sink + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link direction + 0 + 0 + + + Source + The channel 0 is linked as source + 0x1 + + + Sink + The channel 0 is linked as sink + 0x0 + + + + + CH_1 + Link direction + 1 + 1 + + + Source + The channel 1 is linked as source + 0x1 + + + Sink + The channel 1 is linked as sink + 0x0 + + + + + CH_2 + Link direction + 2 + 2 + + + Source + The channel 2 is linked as source + 0x1 + + + Sink + The channel 2 is linked as sink + 0x0 + + + + + CH_3 + Link direction + 3 + 3 + + + Source + The channel 3 is linked as source + 0x1 + + + Sink + The channel 3 is linked as sink + 0x0 + + + + + CH_4 + Link direction + 4 + 4 + + + Source + The channel 4 is linked as source + 0x1 + + + Sink + The channel 4 is linked as sink + 0x0 + + + + + CH_5 + Link direction + 5 + 5 + + + Source + The channel 5 is linked as source + 0x1 + + + Sink + The channel 5 is linked as sink + 0x0 + + + + + CH_6 + Link direction + 6 + 6 + + + Source + The channel 6 is linked as source + 0x1 + + + Sink + The channel 6 is linked as sink + 0x0 + + + + + CH_7 + Link direction + 7 + 7 + + + Source + The channel 7 is linked as source + 0x1 + + + Sink + The channel 7 is linked as sink + 0x0 + + + + + CH_8 + Link direction + 8 + 8 + + + Source + The channel 8 is linked as source + 0x1 + + + Sink + The channel 8 is linked as sink + 0x0 + + + + + CH_9 + Link direction + 9 + 9 + + + Source + The channel 9 is linked as source + 0x1 + + + Sink + The channel 9 is linked as sink + 0x0 + + + + + CH_10 + Link direction + 10 + 10 + + + Source + The channel 10 is linked as source + 0x1 + + + Sink + The channel 10 is linked as sink + 0x0 + + + + + CH_11 + Link direction + 11 + 11 + + + Source + The channel 11 is linked as source + 0x1 + + + Sink + The channel 11 is linked as sink + 0x0 + + + + + CH_12 + Link direction + 12 + 12 + + + Source + The channel 12 is linked as source + 0x1 + + + Sink + The channel 12 is linked as sink + 0x0 + + + + + CH_13 + Link direction + 13 + 13 + + + Source + The channel 13 is linked as source + 0x1 + + + Sink + The channel 13 is linked as sink + 0x0 + + + + + CH_14 + Link direction + 14 + 14 + + + Source + The channel 14 is linked as source + 0x1 + + + Sink + The channel 14 is linked as sink + 0x0 + + + + + CH_15 + Link direction + 15 + 15 + + + Source + The channel 15 is linked as source + 0x1 + + + Sink + The channel 15 is linked as sink + 0x0 + + + + + CH_16 + Link direction + 16 + 16 + + + Source + The channel 16 is linked as source + 0x1 + + + Sink + The channel 16 is linked as sink + 0x0 + + + + + CH_17 + Link direction + 17 + 17 + + + Source + The channel 17 is linked as source + 0x1 + + + Sink + The channel 17 is linked as sink + 0x0 + + + + + CH_18 + Link direction + 18 + 18 + + + Source + The channel 18 is linked as source + 0x1 + + + Sink + The channel 18 is linked as sink + 0x0 + + + + + CH_19 + Link direction + 19 + 19 + + + Source + The channel 19 is linked as source + 0x1 + + + Sink + The channel 19 is linked as sink + 0x0 + + + + + CH_20 + Link direction + 20 + 20 + + + Source + The channel 20 is linked as source + 0x1 + + + Sink + The channel 20 is linked as sink + 0x0 + + + + + CH_21 + Link direction + 21 + 21 + + + Source + The channel 21 is linked as source + 0x1 + + + Sink + The channel 21 is linked as sink + 0x0 + + + + + CH_22 + Link direction + 22 + 22 + + + Source + The channel 22 is linked as source + 0x1 + + + Sink + The channel 22 is linked as sink + 0x0 + + + + + CH_23 + Link direction + 23 + 23 + + + Source + The channel 23 is linked as source + 0x1 + + + Sink + The channel 23 is linked as sink + 0x0 + + + + + CH_24 + Link direction + 24 + 24 + + + Source + The channel 24 is linked as source + 0x1 + + + Sink + The channel 24 is linked as sink + 0x0 + + + + + CH_25 + Link direction + 25 + 25 + + + Source + The channel 25 is linked as source + 0x1 + + + Sink + The channel 25 is linked as sink + 0x0 + + + + + CH_26 + Link direction + 26 + 26 + + + Source + The channel 26 is linked as source + 0x1 + + + Sink + The channel 26 is linked as sink + 0x0 + + + + + CH_27 + Link direction + 27 + 27 + + + Source + The channel 27 is linked as source + 0x1 + + + Sink + The channel 27 is linked as sink + 0x0 + + + + + CH_28 + Link direction + 28 + 28 + + + Source + The channel 28 is linked as source + 0x1 + + + Sink + The channel 28 is linked as sink + 0x0 + + + + + CH_29 + Link direction + 29 + 29 + + + Source + The channel 29 is linked as source + 0x1 + + + Sink + The channel 29 is linked as sink + 0x0 + + + + + CH_30 + Link direction + 30 + 30 + + + Source + The channel 30 is linked as source + 0x1 + + + Sink + The channel 30 is linked as sink + 0x0 + + + + + CH_31 + Link direction + 31 + 31 + + + Source + The channel 31 is linked as source + 0x1 + + + Sink + The channel 31 is linked as sink + 0x0 + + + + + + + EN + Description cluster: Request linking of the channels of DPPI[n] in the local domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link enable + 0 + 0 + + + Disabled + The channel 0 is disabled + 0x1 + + + Enabled + The channel 0 is enabled + 0x0 + + + + + CH_1 + Link enable + 1 + 1 + + + Disabled + The channel 1 is disabled + 0x1 + + + Enabled + The channel 1 is enabled + 0x0 + + + + + CH_2 + Link enable + 2 + 2 + + + Disabled + The channel 2 is disabled + 0x1 + + + Enabled + The channel 2 is enabled + 0x0 + + + + + CH_3 + Link enable + 3 + 3 + + + Disabled + The channel 3 is disabled + 0x1 + + + Enabled + The channel 3 is enabled + 0x0 + + + + + CH_4 + Link enable + 4 + 4 + + + Disabled + The channel 4 is disabled + 0x1 + + + Enabled + The channel 4 is enabled + 0x0 + + + + + CH_5 + Link enable + 5 + 5 + + + Disabled + The channel 5 is disabled + 0x1 + + + Enabled + The channel 5 is enabled + 0x0 + + + + + CH_6 + Link enable + 6 + 6 + + + Disabled + The channel 6 is disabled + 0x1 + + + Enabled + The channel 6 is enabled + 0x0 + + + + + CH_7 + Link enable + 7 + 7 + + + Disabled + The channel 7 is disabled + 0x1 + + + Enabled + The channel 7 is enabled + 0x0 + + + + + CH_8 + Link enable + 8 + 8 + + + Disabled + The channel 8 is disabled + 0x1 + + + Enabled + The channel 8 is enabled + 0x0 + + + + + CH_9 + Link enable + 9 + 9 + + + Disabled + The channel 9 is disabled + 0x1 + + + Enabled + The channel 9 is enabled + 0x0 + + + + + CH_10 + Link enable + 10 + 10 + + + Disabled + The channel 10 is disabled + 0x1 + + + Enabled + The channel 10 is enabled + 0x0 + + + + + CH_11 + Link enable + 11 + 11 + + + Disabled + The channel 11 is disabled + 0x1 + + + Enabled + The channel 11 is enabled + 0x0 + + + + + CH_12 + Link enable + 12 + 12 + + + Disabled + The channel 12 is disabled + 0x1 + + + Enabled + The channel 12 is enabled + 0x0 + + + + + CH_13 + Link enable + 13 + 13 + + + Disabled + The channel 13 is disabled + 0x1 + + + Enabled + The channel 13 is enabled + 0x0 + + + + + CH_14 + Link enable + 14 + 14 + + + Disabled + The channel 14 is disabled + 0x1 + + + Enabled + The channel 14 is enabled + 0x0 + + + + + CH_15 + Link enable + 15 + 15 + + + Disabled + The channel 15 is disabled + 0x1 + + + Enabled + The channel 15 is enabled + 0x0 + + + + + CH_16 + Link enable + 16 + 16 + + + Disabled + The channel 16 is disabled + 0x1 + + + Enabled + The channel 16 is enabled + 0x0 + + + + + CH_17 + Link enable + 17 + 17 + + + Disabled + The channel 17 is disabled + 0x1 + + + Enabled + The channel 17 is enabled + 0x0 + + + + + CH_18 + Link enable + 18 + 18 + + + Disabled + The channel 18 is disabled + 0x1 + + + Enabled + The channel 18 is enabled + 0x0 + + + + + CH_19 + Link enable + 19 + 19 + + + Disabled + The channel 19 is disabled + 0x1 + + + Enabled + The channel 19 is enabled + 0x0 + + + + + CH_20 + Link enable + 20 + 20 + + + Disabled + The channel 20 is disabled + 0x1 + + + Enabled + The channel 20 is enabled + 0x0 + + + + + CH_21 + Link enable + 21 + 21 + + + Disabled + The channel 21 is disabled + 0x1 + + + Enabled + The channel 21 is enabled + 0x0 + + + + + CH_22 + Link enable + 22 + 22 + + + Disabled + The channel 22 is disabled + 0x1 + + + Enabled + The channel 22 is enabled + 0x0 + + + + + CH_23 + Link enable + 23 + 23 + + + Disabled + The channel 23 is disabled + 0x1 + + + Enabled + The channel 23 is enabled + 0x0 + + + + + CH_24 + Link enable + 24 + 24 + + + Disabled + The channel 24 is disabled + 0x1 + + + Enabled + The channel 24 is enabled + 0x0 + + + + + CH_25 + Link enable + 25 + 25 + + + Disabled + The channel 25 is disabled + 0x1 + + + Enabled + The channel 25 is enabled + 0x0 + + + + + CH_26 + Link enable + 26 + 26 + + + Disabled + The channel 26 is disabled + 0x1 + + + Enabled + The channel 26 is enabled + 0x0 + + + + + CH_27 + Link enable + 27 + 27 + + + Disabled + The channel 27 is disabled + 0x1 + + + Enabled + The channel 27 is enabled + 0x0 + + + + + CH_28 + Link enable + 28 + 28 + + + Disabled + The channel 28 is disabled + 0x1 + + + Enabled + The channel 28 is enabled + 0x0 + + + + + CH_29 + Link enable + 29 + 29 + + + Disabled + The channel 29 is disabled + 0x1 + + + Enabled + The channel 29 is enabled + 0x0 + + + + + CH_30 + Link enable + 30 + 30 + + + Disabled + The channel 30 is disabled + 0x1 + + + Enabled + The channel 30 is enabled + 0x0 + + + + + CH_31 + Link enable + 31 + 31 + + + Disabled + The channel 31 is disabled + 0x1 + + + Enabled + The channel 31 is enabled + 0x0 + + + + + + + + + CHG + Unspecified + UICR_DPPI_LOCAL_CHG + read-write + 0x010 + + SECURE + Description cluster: Request permission for the channel groups of DPPI[n] in the local domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + Secure + The channel group 0 is secure + 0x1 + + + NonSecure + The channel group 0 is non-secure + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + Secure + The channel group 1 is secure + 0x1 + + + NonSecure + The channel group 1 is non-secure + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + Secure + The channel group 2 is secure + 0x1 + + + NonSecure + The channel group 2 is non-secure + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + Secure + The channel group 3 is secure + 0x1 + + + NonSecure + The channel group 3 is non-secure + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + Secure + The channel group 4 is secure + 0x1 + + + NonSecure + The channel group 4 is non-secure + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + Secure + The channel group 5 is secure + 0x1 + + + NonSecure + The channel group 5 is non-secure + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + Secure + The channel group 6 is secure + 0x1 + + + NonSecure + The channel group 6 is non-secure + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + Secure + The channel group 7 is secure + 0x1 + + + NonSecure + The channel group 7 is non-secure + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + Secure + The channel group 8 is secure + 0x1 + + + NonSecure + The channel group 8 is non-secure + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + Secure + The channel group 9 is secure + 0x1 + + + NonSecure + The channel group 9 is non-secure + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + Secure + The channel group 10 is secure + 0x1 + + + NonSecure + The channel group 10 is non-secure + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + Secure + The channel group 11 is secure + 0x1 + + + NonSecure + The channel group 11 is non-secure + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + Secure + The channel group 12 is secure + 0x1 + + + NonSecure + The channel group 12 is non-secure + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + Secure + The channel group 13 is secure + 0x1 + + + NonSecure + The channel group 13 is non-secure + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + Secure + The channel group 14 is secure + 0x1 + + + NonSecure + The channel group 14 is non-secure + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + Secure + The channel group 15 is secure + 0x1 + + + NonSecure + The channel group 15 is non-secure + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + Secure + The channel group 16 is secure + 0x1 + + + NonSecure + The channel group 16 is non-secure + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + Secure + The channel group 17 is secure + 0x1 + + + NonSecure + The channel group 17 is non-secure + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + Secure + The channel group 18 is secure + 0x1 + + + NonSecure + The channel group 18 is non-secure + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + Secure + The channel group 19 is secure + 0x1 + + + NonSecure + The channel group 19 is non-secure + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + Secure + The channel group 20 is secure + 0x1 + + + NonSecure + The channel group 20 is non-secure + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + Secure + The channel group 21 is secure + 0x1 + + + NonSecure + The channel group 21 is non-secure + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + Secure + The channel group 22 is secure + 0x1 + + + NonSecure + The channel group 22 is non-secure + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + Secure + The channel group 23 is secure + 0x1 + + + NonSecure + The channel group 23 is non-secure + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + Secure + The channel group 24 is secure + 0x1 + + + NonSecure + The channel group 24 is non-secure + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + Secure + The channel group 25 is secure + 0x1 + + + NonSecure + The channel group 25 is non-secure + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + Secure + The channel group 26 is secure + 0x1 + + + NonSecure + The channel group 26 is non-secure + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + Secure + The channel group 27 is secure + 0x1 + + + NonSecure + The channel group 27 is non-secure + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + Secure + The channel group 28 is secure + 0x1 + + + NonSecure + The channel group 28 is non-secure + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + Secure + The channel group 29 is secure + 0x1 + + + NonSecure + The channel group 29 is non-secure + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + Secure + The channel group 30 is secure + 0x1 + + + NonSecure + The channel group 30 is non-secure + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + Secure + The channel group 31 is secure + 0x1 + + + NonSecure + The channel group 31 is non-secure + 0x0 + + + + + + + + + 12 + 0x01C + GLOBAL[%s] + Unspecified + UICR_DPPI_GLOBAL + read-write + 0x028 + + INSTANCE + Description cluster: Address of the DPPI instance associated with DPPI[n].GLOBAL + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Instance address + 0 + 31 + + + + + CH + Unspecified + UICR_DPPI_GLOBAL_CH + read-write + 0x004 + + OWN + Description cluster: Request ownership of the channels of DPPI[n] in Global Domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + NotOwn + Do not own the channel 0 + 0x1 + + + Own + Own the channel 0 + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + NotOwn + Do not own the channel 1 + 0x1 + + + Own + Own the channel 1 + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + NotOwn + Do not own the channel 2 + 0x1 + + + Own + Own the channel 2 + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + NotOwn + Do not own the channel 3 + 0x1 + + + Own + Own the channel 3 + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + NotOwn + Do not own the channel 4 + 0x1 + + + Own + Own the channel 4 + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + NotOwn + Do not own the channel 5 + 0x1 + + + Own + Own the channel 5 + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + NotOwn + Do not own the channel 6 + 0x1 + + + Own + Own the channel 6 + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + NotOwn + Do not own the channel 7 + 0x1 + + + Own + Own the channel 7 + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + NotOwn + Do not own the channel 8 + 0x1 + + + Own + Own the channel 8 + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + NotOwn + Do not own the channel 9 + 0x1 + + + Own + Own the channel 9 + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + NotOwn + Do not own the channel 10 + 0x1 + + + Own + Own the channel 10 + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + NotOwn + Do not own the channel 11 + 0x1 + + + Own + Own the channel 11 + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + NotOwn + Do not own the channel 12 + 0x1 + + + Own + Own the channel 12 + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + NotOwn + Do not own the channel 13 + 0x1 + + + Own + Own the channel 13 + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + NotOwn + Do not own the channel 14 + 0x1 + + + Own + Own the channel 14 + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + NotOwn + Do not own the channel 15 + 0x1 + + + Own + Own the channel 15 + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + NotOwn + Do not own the channel 16 + 0x1 + + + Own + Own the channel 16 + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + NotOwn + Do not own the channel 17 + 0x1 + + + Own + Own the channel 17 + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + NotOwn + Do not own the channel 18 + 0x1 + + + Own + Own the channel 18 + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + NotOwn + Do not own the channel 19 + 0x1 + + + Own + Own the channel 19 + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + NotOwn + Do not own the channel 20 + 0x1 + + + Own + Own the channel 20 + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + NotOwn + Do not own the channel 21 + 0x1 + + + Own + Own the channel 21 + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + NotOwn + Do not own the channel 22 + 0x1 + + + Own + Own the channel 22 + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + NotOwn + Do not own the channel 23 + 0x1 + + + Own + Own the channel 23 + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + NotOwn + Do not own the channel 24 + 0x1 + + + Own + Own the channel 24 + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + NotOwn + Do not own the channel 25 + 0x1 + + + Own + Own the channel 25 + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + NotOwn + Do not own the channel 26 + 0x1 + + + Own + Own the channel 26 + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + NotOwn + Do not own the channel 27 + 0x1 + + + Own + Own the channel 27 + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + NotOwn + Do not own the channel 28 + 0x1 + + + Own + Own the channel 28 + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + NotOwn + Do not own the channel 29 + 0x1 + + + Own + Own the channel 29 + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + NotOwn + Do not own the channel 30 + 0x1 + + + Own + Own the channel 30 + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + NotOwn + Do not own the channel 31 + 0x1 + + + Own + Own the channel 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channels of DPPI[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Channel number + 0 + 0 + + + Secure + The channel 0 is secure + 0x1 + + + NonSecure + The channel 0 is non-secure + 0x0 + + + + + CH_1 + Channel number + 1 + 1 + + + Secure + The channel 1 is secure + 0x1 + + + NonSecure + The channel 1 is non-secure + 0x0 + + + + + CH_2 + Channel number + 2 + 2 + + + Secure + The channel 2 is secure + 0x1 + + + NonSecure + The channel 2 is non-secure + 0x0 + + + + + CH_3 + Channel number + 3 + 3 + + + Secure + The channel 3 is secure + 0x1 + + + NonSecure + The channel 3 is non-secure + 0x0 + + + + + CH_4 + Channel number + 4 + 4 + + + Secure + The channel 4 is secure + 0x1 + + + NonSecure + The channel 4 is non-secure + 0x0 + + + + + CH_5 + Channel number + 5 + 5 + + + Secure + The channel 5 is secure + 0x1 + + + NonSecure + The channel 5 is non-secure + 0x0 + + + + + CH_6 + Channel number + 6 + 6 + + + Secure + The channel 6 is secure + 0x1 + + + NonSecure + The channel 6 is non-secure + 0x0 + + + + + CH_7 + Channel number + 7 + 7 + + + Secure + The channel 7 is secure + 0x1 + + + NonSecure + The channel 7 is non-secure + 0x0 + + + + + CH_8 + Channel number + 8 + 8 + + + Secure + The channel 8 is secure + 0x1 + + + NonSecure + The channel 8 is non-secure + 0x0 + + + + + CH_9 + Channel number + 9 + 9 + + + Secure + The channel 9 is secure + 0x1 + + + NonSecure + The channel 9 is non-secure + 0x0 + + + + + CH_10 + Channel number + 10 + 10 + + + Secure + The channel 10 is secure + 0x1 + + + NonSecure + The channel 10 is non-secure + 0x0 + + + + + CH_11 + Channel number + 11 + 11 + + + Secure + The channel 11 is secure + 0x1 + + + NonSecure + The channel 11 is non-secure + 0x0 + + + + + CH_12 + Channel number + 12 + 12 + + + Secure + The channel 12 is secure + 0x1 + + + NonSecure + The channel 12 is non-secure + 0x0 + + + + + CH_13 + Channel number + 13 + 13 + + + Secure + The channel 13 is secure + 0x1 + + + NonSecure + The channel 13 is non-secure + 0x0 + + + + + CH_14 + Channel number + 14 + 14 + + + Secure + The channel 14 is secure + 0x1 + + + NonSecure + The channel 14 is non-secure + 0x0 + + + + + CH_15 + Channel number + 15 + 15 + + + Secure + The channel 15 is secure + 0x1 + + + NonSecure + The channel 15 is non-secure + 0x0 + + + + + CH_16 + Channel number + 16 + 16 + + + Secure + The channel 16 is secure + 0x1 + + + NonSecure + The channel 16 is non-secure + 0x0 + + + + + CH_17 + Channel number + 17 + 17 + + + Secure + The channel 17 is secure + 0x1 + + + NonSecure + The channel 17 is non-secure + 0x0 + + + + + CH_18 + Channel number + 18 + 18 + + + Secure + The channel 18 is secure + 0x1 + + + NonSecure + The channel 18 is non-secure + 0x0 + + + + + CH_19 + Channel number + 19 + 19 + + + Secure + The channel 19 is secure + 0x1 + + + NonSecure + The channel 19 is non-secure + 0x0 + + + + + CH_20 + Channel number + 20 + 20 + + + Secure + The channel 20 is secure + 0x1 + + + NonSecure + The channel 20 is non-secure + 0x0 + + + + + CH_21 + Channel number + 21 + 21 + + + Secure + The channel 21 is secure + 0x1 + + + NonSecure + The channel 21 is non-secure + 0x0 + + + + + CH_22 + Channel number + 22 + 22 + + + Secure + The channel 22 is secure + 0x1 + + + NonSecure + The channel 22 is non-secure + 0x0 + + + + + CH_23 + Channel number + 23 + 23 + + + Secure + The channel 23 is secure + 0x1 + + + NonSecure + The channel 23 is non-secure + 0x0 + + + + + CH_24 + Channel number + 24 + 24 + + + Secure + The channel 24 is secure + 0x1 + + + NonSecure + The channel 24 is non-secure + 0x0 + + + + + CH_25 + Channel number + 25 + 25 + + + Secure + The channel 25 is secure + 0x1 + + + NonSecure + The channel 25 is non-secure + 0x0 + + + + + CH_26 + Channel number + 26 + 26 + + + Secure + The channel 26 is secure + 0x1 + + + NonSecure + The channel 26 is non-secure + 0x0 + + + + + CH_27 + Channel number + 27 + 27 + + + Secure + The channel 27 is secure + 0x1 + + + NonSecure + The channel 27 is non-secure + 0x0 + + + + + CH_28 + Channel number + 28 + 28 + + + Secure + The channel 28 is secure + 0x1 + + + NonSecure + The channel 28 is non-secure + 0x0 + + + + + CH_29 + Channel number + 29 + 29 + + + Secure + The channel 29 is secure + 0x1 + + + NonSecure + The channel 29 is non-secure + 0x0 + + + + + CH_30 + Channel number + 30 + 30 + + + Secure + The channel 30 is secure + 0x1 + + + NonSecure + The channel 30 is non-secure + 0x0 + + + + + CH_31 + Channel number + 31 + 31 + + + Secure + The channel 31 is secure + 0x1 + + + NonSecure + The channel 31 is non-secure + 0x0 + + + + + + + LINK + Unspecified + UICR_DPPI_GLOBAL_CH_LINK + read-write + 0x008 + + DIR + Description cluster: Request linking the channels of DPPI[n] in Global domain as source or sink + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link direction + 0 + 0 + + + Source + The channel 0 is linked as source + 0x1 + + + Sink + The channel 0 is linked as sink + 0x0 + + + + + CH_1 + Link direction + 1 + 1 + + + Source + The channel 1 is linked as source + 0x1 + + + Sink + The channel 1 is linked as sink + 0x0 + + + + + CH_2 + Link direction + 2 + 2 + + + Source + The channel 2 is linked as source + 0x1 + + + Sink + The channel 2 is linked as sink + 0x0 + + + + + CH_3 + Link direction + 3 + 3 + + + Source + The channel 3 is linked as source + 0x1 + + + Sink + The channel 3 is linked as sink + 0x0 + + + + + CH_4 + Link direction + 4 + 4 + + + Source + The channel 4 is linked as source + 0x1 + + + Sink + The channel 4 is linked as sink + 0x0 + + + + + CH_5 + Link direction + 5 + 5 + + + Source + The channel 5 is linked as source + 0x1 + + + Sink + The channel 5 is linked as sink + 0x0 + + + + + CH_6 + Link direction + 6 + 6 + + + Source + The channel 6 is linked as source + 0x1 + + + Sink + The channel 6 is linked as sink + 0x0 + + + + + CH_7 + Link direction + 7 + 7 + + + Source + The channel 7 is linked as source + 0x1 + + + Sink + The channel 7 is linked as sink + 0x0 + + + + + CH_8 + Link direction + 8 + 8 + + + Source + The channel 8 is linked as source + 0x1 + + + Sink + The channel 8 is linked as sink + 0x0 + + + + + CH_9 + Link direction + 9 + 9 + + + Source + The channel 9 is linked as source + 0x1 + + + Sink + The channel 9 is linked as sink + 0x0 + + + + + CH_10 + Link direction + 10 + 10 + + + Source + The channel 10 is linked as source + 0x1 + + + Sink + The channel 10 is linked as sink + 0x0 + + + + + CH_11 + Link direction + 11 + 11 + + + Source + The channel 11 is linked as source + 0x1 + + + Sink + The channel 11 is linked as sink + 0x0 + + + + + CH_12 + Link direction + 12 + 12 + + + Source + The channel 12 is linked as source + 0x1 + + + Sink + The channel 12 is linked as sink + 0x0 + + + + + CH_13 + Link direction + 13 + 13 + + + Source + The channel 13 is linked as source + 0x1 + + + Sink + The channel 13 is linked as sink + 0x0 + + + + + CH_14 + Link direction + 14 + 14 + + + Source + The channel 14 is linked as source + 0x1 + + + Sink + The channel 14 is linked as sink + 0x0 + + + + + CH_15 + Link direction + 15 + 15 + + + Source + The channel 15 is linked as source + 0x1 + + + Sink + The channel 15 is linked as sink + 0x0 + + + + + CH_16 + Link direction + 16 + 16 + + + Source + The channel 16 is linked as source + 0x1 + + + Sink + The channel 16 is linked as sink + 0x0 + + + + + CH_17 + Link direction + 17 + 17 + + + Source + The channel 17 is linked as source + 0x1 + + + Sink + The channel 17 is linked as sink + 0x0 + + + + + CH_18 + Link direction + 18 + 18 + + + Source + The channel 18 is linked as source + 0x1 + + + Sink + The channel 18 is linked as sink + 0x0 + + + + + CH_19 + Link direction + 19 + 19 + + + Source + The channel 19 is linked as source + 0x1 + + + Sink + The channel 19 is linked as sink + 0x0 + + + + + CH_20 + Link direction + 20 + 20 + + + Source + The channel 20 is linked as source + 0x1 + + + Sink + The channel 20 is linked as sink + 0x0 + + + + + CH_21 + Link direction + 21 + 21 + + + Source + The channel 21 is linked as source + 0x1 + + + Sink + The channel 21 is linked as sink + 0x0 + + + + + CH_22 + Link direction + 22 + 22 + + + Source + The channel 22 is linked as source + 0x1 + + + Sink + The channel 22 is linked as sink + 0x0 + + + + + CH_23 + Link direction + 23 + 23 + + + Source + The channel 23 is linked as source + 0x1 + + + Sink + The channel 23 is linked as sink + 0x0 + + + + + CH_24 + Link direction + 24 + 24 + + + Source + The channel 24 is linked as source + 0x1 + + + Sink + The channel 24 is linked as sink + 0x0 + + + + + CH_25 + Link direction + 25 + 25 + + + Source + The channel 25 is linked as source + 0x1 + + + Sink + The channel 25 is linked as sink + 0x0 + + + + + CH_26 + Link direction + 26 + 26 + + + Source + The channel 26 is linked as source + 0x1 + + + Sink + The channel 26 is linked as sink + 0x0 + + + + + CH_27 + Link direction + 27 + 27 + + + Source + The channel 27 is linked as source + 0x1 + + + Sink + The channel 27 is linked as sink + 0x0 + + + + + CH_28 + Link direction + 28 + 28 + + + Source + The channel 28 is linked as source + 0x1 + + + Sink + The channel 28 is linked as sink + 0x0 + + + + + CH_29 + Link direction + 29 + 29 + + + Source + The channel 29 is linked as source + 0x1 + + + Sink + The channel 29 is linked as sink + 0x0 + + + + + CH_30 + Link direction + 30 + 30 + + + Source + The channel 30 is linked as source + 0x1 + + + Sink + The channel 30 is linked as sink + 0x0 + + + + + CH_31 + Link direction + 31 + 31 + + + Source + The channel 31 is linked as source + 0x1 + + + Sink + The channel 31 is linked as sink + 0x0 + + + + + + + EN + Description cluster: Request linking of the channels of DPPI[n] in the Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CH_0 + Link enable + 0 + 0 + + + Disabled + The channel 0 is disabled + 0x1 + + + Enabled + The channel 0 is enabled + 0x0 + + + + + CH_1 + Link enable + 1 + 1 + + + Disabled + The channel 1 is disabled + 0x1 + + + Enabled + The channel 1 is enabled + 0x0 + + + + + CH_2 + Link enable + 2 + 2 + + + Disabled + The channel 2 is disabled + 0x1 + + + Enabled + The channel 2 is enabled + 0x0 + + + + + CH_3 + Link enable + 3 + 3 + + + Disabled + The channel 3 is disabled + 0x1 + + + Enabled + The channel 3 is enabled + 0x0 + + + + + CH_4 + Link enable + 4 + 4 + + + Disabled + The channel 4 is disabled + 0x1 + + + Enabled + The channel 4 is enabled + 0x0 + + + + + CH_5 + Link enable + 5 + 5 + + + Disabled + The channel 5 is disabled + 0x1 + + + Enabled + The channel 5 is enabled + 0x0 + + + + + CH_6 + Link enable + 6 + 6 + + + Disabled + The channel 6 is disabled + 0x1 + + + Enabled + The channel 6 is enabled + 0x0 + + + + + CH_7 + Link enable + 7 + 7 + + + Disabled + The channel 7 is disabled + 0x1 + + + Enabled + The channel 7 is enabled + 0x0 + + + + + CH_8 + Link enable + 8 + 8 + + + Disabled + The channel 8 is disabled + 0x1 + + + Enabled + The channel 8 is enabled + 0x0 + + + + + CH_9 + Link enable + 9 + 9 + + + Disabled + The channel 9 is disabled + 0x1 + + + Enabled + The channel 9 is enabled + 0x0 + + + + + CH_10 + Link enable + 10 + 10 + + + Disabled + The channel 10 is disabled + 0x1 + + + Enabled + The channel 10 is enabled + 0x0 + + + + + CH_11 + Link enable + 11 + 11 + + + Disabled + The channel 11 is disabled + 0x1 + + + Enabled + The channel 11 is enabled + 0x0 + + + + + CH_12 + Link enable + 12 + 12 + + + Disabled + The channel 12 is disabled + 0x1 + + + Enabled + The channel 12 is enabled + 0x0 + + + + + CH_13 + Link enable + 13 + 13 + + + Disabled + The channel 13 is disabled + 0x1 + + + Enabled + The channel 13 is enabled + 0x0 + + + + + CH_14 + Link enable + 14 + 14 + + + Disabled + The channel 14 is disabled + 0x1 + + + Enabled + The channel 14 is enabled + 0x0 + + + + + CH_15 + Link enable + 15 + 15 + + + Disabled + The channel 15 is disabled + 0x1 + + + Enabled + The channel 15 is enabled + 0x0 + + + + + CH_16 + Link enable + 16 + 16 + + + Disabled + The channel 16 is disabled + 0x1 + + + Enabled + The channel 16 is enabled + 0x0 + + + + + CH_17 + Link enable + 17 + 17 + + + Disabled + The channel 17 is disabled + 0x1 + + + Enabled + The channel 17 is enabled + 0x0 + + + + + CH_18 + Link enable + 18 + 18 + + + Disabled + The channel 18 is disabled + 0x1 + + + Enabled + The channel 18 is enabled + 0x0 + + + + + CH_19 + Link enable + 19 + 19 + + + Disabled + The channel 19 is disabled + 0x1 + + + Enabled + The channel 19 is enabled + 0x0 + + + + + CH_20 + Link enable + 20 + 20 + + + Disabled + The channel 20 is disabled + 0x1 + + + Enabled + The channel 20 is enabled + 0x0 + + + + + CH_21 + Link enable + 21 + 21 + + + Disabled + The channel 21 is disabled + 0x1 + + + Enabled + The channel 21 is enabled + 0x0 + + + + + CH_22 + Link enable + 22 + 22 + + + Disabled + The channel 22 is disabled + 0x1 + + + Enabled + The channel 22 is enabled + 0x0 + + + + + CH_23 + Link enable + 23 + 23 + + + Disabled + The channel 23 is disabled + 0x1 + + + Enabled + The channel 23 is enabled + 0x0 + + + + + CH_24 + Link enable + 24 + 24 + + + Disabled + The channel 24 is disabled + 0x1 + + + Enabled + The channel 24 is enabled + 0x0 + + + + + CH_25 + Link enable + 25 + 25 + + + Disabled + The channel 25 is disabled + 0x1 + + + Enabled + The channel 25 is enabled + 0x0 + + + + + CH_26 + Link enable + 26 + 26 + + + Disabled + The channel 26 is disabled + 0x1 + + + Enabled + The channel 26 is enabled + 0x0 + + + + + CH_27 + Link enable + 27 + 27 + + + Disabled + The channel 27 is disabled + 0x1 + + + Enabled + The channel 27 is enabled + 0x0 + + + + + CH_28 + Link enable + 28 + 28 + + + Disabled + The channel 28 is disabled + 0x1 + + + Enabled + The channel 28 is enabled + 0x0 + + + + + CH_29 + Link enable + 29 + 29 + + + Disabled + The channel 29 is disabled + 0x1 + + + Enabled + The channel 29 is enabled + 0x0 + + + + + CH_30 + Link enable + 30 + 30 + + + Disabled + The channel 30 is disabled + 0x1 + + + Enabled + The channel 30 is enabled + 0x0 + + + + + CH_31 + Link enable + 31 + 31 + + + Disabled + The channel 31 is disabled + 0x1 + + + Enabled + The channel 31 is enabled + 0x0 + + + + + + + + + CHG + Unspecified + UICR_DPPI_GLOBAL_CHG + read-write + 0x014 + + OWN + Description cluster: Request ownership of the channel groups of DPPI[n] in Global domain + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + NotOwn + Do not own the channel group 0 + 0x1 + + + Own + Own the channel group 0 + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + NotOwn + Do not own the channel group 1 + 0x1 + + + Own + Own the channel group 1 + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + NotOwn + Do not own the channel group 2 + 0x1 + + + Own + Own the channel group 2 + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + NotOwn + Do not own the channel group 3 + 0x1 + + + Own + Own the channel group 3 + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + NotOwn + Do not own the channel group 4 + 0x1 + + + Own + Own the channel group 4 + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + NotOwn + Do not own the channel group 5 + 0x1 + + + Own + Own the channel group 5 + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + NotOwn + Do not own the channel group 6 + 0x1 + + + Own + Own the channel group 6 + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + NotOwn + Do not own the channel group 7 + 0x1 + + + Own + Own the channel group 7 + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + NotOwn + Do not own the channel group 8 + 0x1 + + + Own + Own the channel group 8 + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + NotOwn + Do not own the channel group 9 + 0x1 + + + Own + Own the channel group 9 + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + NotOwn + Do not own the channel group 10 + 0x1 + + + Own + Own the channel group 10 + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + NotOwn + Do not own the channel group 11 + 0x1 + + + Own + Own the channel group 11 + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + NotOwn + Do not own the channel group 12 + 0x1 + + + Own + Own the channel group 12 + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + NotOwn + Do not own the channel group 13 + 0x1 + + + Own + Own the channel group 13 + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + NotOwn + Do not own the channel group 14 + 0x1 + + + Own + Own the channel group 14 + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + NotOwn + Do not own the channel group 15 + 0x1 + + + Own + Own the channel group 15 + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + NotOwn + Do not own the channel group 16 + 0x1 + + + Own + Own the channel group 16 + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + NotOwn + Do not own the channel group 17 + 0x1 + + + Own + Own the channel group 17 + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + NotOwn + Do not own the channel group 18 + 0x1 + + + Own + Own the channel group 18 + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + NotOwn + Do not own the channel group 19 + 0x1 + + + Own + Own the channel group 19 + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + NotOwn + Do not own the channel group 20 + 0x1 + + + Own + Own the channel group 20 + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + NotOwn + Do not own the channel group 21 + 0x1 + + + Own + Own the channel group 21 + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + NotOwn + Do not own the channel group 22 + 0x1 + + + Own + Own the channel group 22 + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + NotOwn + Do not own the channel group 23 + 0x1 + + + Own + Own the channel group 23 + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + NotOwn + Do not own the channel group 24 + 0x1 + + + Own + Own the channel group 24 + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + NotOwn + Do not own the channel group 25 + 0x1 + + + Own + Own the channel group 25 + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + NotOwn + Do not own the channel group 26 + 0x1 + + + Own + Own the channel group 26 + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + NotOwn + Do not own the channel group 27 + 0x1 + + + Own + Own the channel group 27 + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + NotOwn + Do not own the channel group 28 + 0x1 + + + Own + Own the channel group 28 + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + NotOwn + Do not own the channel group 29 + 0x1 + + + Own + Own the channel group 29 + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + NotOwn + Do not own the channel group 30 + 0x1 + + + Own + Own the channel group 30 + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + NotOwn + Do not own the channel group 31 + 0x1 + + + Own + Own the channel group 31 + 0x0 + + + + + + + SECURE + Description cluster: Request permission for the channel groups of DPPI[n] in Global domain + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CHG_0 + Channel group number + 0 + 0 + + + Secure + The channel group 0 is secure + 0x1 + + + NonSecure + The channel group 0 is non-secure + 0x0 + + + + + CHG_1 + Channel group number + 1 + 1 + + + Secure + The channel group 1 is secure + 0x1 + + + NonSecure + The channel group 1 is non-secure + 0x0 + + + + + CHG_2 + Channel group number + 2 + 2 + + + Secure + The channel group 2 is secure + 0x1 + + + NonSecure + The channel group 2 is non-secure + 0x0 + + + + + CHG_3 + Channel group number + 3 + 3 + + + Secure + The channel group 3 is secure + 0x1 + + + NonSecure + The channel group 3 is non-secure + 0x0 + + + + + CHG_4 + Channel group number + 4 + 4 + + + Secure + The channel group 4 is secure + 0x1 + + + NonSecure + The channel group 4 is non-secure + 0x0 + + + + + CHG_5 + Channel group number + 5 + 5 + + + Secure + The channel group 5 is secure + 0x1 + + + NonSecure + The channel group 5 is non-secure + 0x0 + + + + + CHG_6 + Channel group number + 6 + 6 + + + Secure + The channel group 6 is secure + 0x1 + + + NonSecure + The channel group 6 is non-secure + 0x0 + + + + + CHG_7 + Channel group number + 7 + 7 + + + Secure + The channel group 7 is secure + 0x1 + + + NonSecure + The channel group 7 is non-secure + 0x0 + + + + + CHG_8 + Channel group number + 8 + 8 + + + Secure + The channel group 8 is secure + 0x1 + + + NonSecure + The channel group 8 is non-secure + 0x0 + + + + + CHG_9 + Channel group number + 9 + 9 + + + Secure + The channel group 9 is secure + 0x1 + + + NonSecure + The channel group 9 is non-secure + 0x0 + + + + + CHG_10 + Channel group number + 10 + 10 + + + Secure + The channel group 10 is secure + 0x1 + + + NonSecure + The channel group 10 is non-secure + 0x0 + + + + + CHG_11 + Channel group number + 11 + 11 + + + Secure + The channel group 11 is secure + 0x1 + + + NonSecure + The channel group 11 is non-secure + 0x0 + + + + + CHG_12 + Channel group number + 12 + 12 + + + Secure + The channel group 12 is secure + 0x1 + + + NonSecure + The channel group 12 is non-secure + 0x0 + + + + + CHG_13 + Channel group number + 13 + 13 + + + Secure + The channel group 13 is secure + 0x1 + + + NonSecure + The channel group 13 is non-secure + 0x0 + + + + + CHG_14 + Channel group number + 14 + 14 + + + Secure + The channel group 14 is secure + 0x1 + + + NonSecure + The channel group 14 is non-secure + 0x0 + + + + + CHG_15 + Channel group number + 15 + 15 + + + Secure + The channel group 15 is secure + 0x1 + + + NonSecure + The channel group 15 is non-secure + 0x0 + + + + + CHG_16 + Channel group number + 16 + 16 + + + Secure + The channel group 16 is secure + 0x1 + + + NonSecure + The channel group 16 is non-secure + 0x0 + + + + + CHG_17 + Channel group number + 17 + 17 + + + Secure + The channel group 17 is secure + 0x1 + + + NonSecure + The channel group 17 is non-secure + 0x0 + + + + + CHG_18 + Channel group number + 18 + 18 + + + Secure + The channel group 18 is secure + 0x1 + + + NonSecure + The channel group 18 is non-secure + 0x0 + + + + + CHG_19 + Channel group number + 19 + 19 + + + Secure + The channel group 19 is secure + 0x1 + + + NonSecure + The channel group 19 is non-secure + 0x0 + + + + + CHG_20 + Channel group number + 20 + 20 + + + Secure + The channel group 20 is secure + 0x1 + + + NonSecure + The channel group 20 is non-secure + 0x0 + + + + + CHG_21 + Channel group number + 21 + 21 + + + Secure + The channel group 21 is secure + 0x1 + + + NonSecure + The channel group 21 is non-secure + 0x0 + + + + + CHG_22 + Channel group number + 22 + 22 + + + Secure + The channel group 22 is secure + 0x1 + + + NonSecure + The channel group 22 is non-secure + 0x0 + + + + + CHG_23 + Channel group number + 23 + 23 + + + Secure + The channel group 23 is secure + 0x1 + + + NonSecure + The channel group 23 is non-secure + 0x0 + + + + + CHG_24 + Channel group number + 24 + 24 + + + Secure + The channel group 24 is secure + 0x1 + + + NonSecure + The channel group 24 is non-secure + 0x0 + + + + + CHG_25 + Channel group number + 25 + 25 + + + Secure + The channel group 25 is secure + 0x1 + + + NonSecure + The channel group 25 is non-secure + 0x0 + + + + + CHG_26 + Channel group number + 26 + 26 + + + Secure + The channel group 26 is secure + 0x1 + + + NonSecure + The channel group 26 is non-secure + 0x0 + + + + + CHG_27 + Channel group number + 27 + 27 + + + Secure + The channel group 27 is secure + 0x1 + + + NonSecure + The channel group 27 is non-secure + 0x0 + + + + + CHG_28 + Channel group number + 28 + 28 + + + Secure + The channel group 28 is secure + 0x1 + + + NonSecure + The channel group 28 is non-secure + 0x0 + + + + + CHG_29 + Channel group number + 29 + 29 + + + Secure + The channel group 29 is secure + 0x1 + + + NonSecure + The channel group 29 is non-secure + 0x0 + + + + + CHG_30 + Channel group number + 30 + 30 + + + Secure + The channel group 30 is secure + 0x1 + + + NonSecure + The channel group 30 is non-secure + 0x0 + + + + + CHG_31 + Channel group number + 31 + 31 + + + Secure + The channel group 31 is secure + 0x1 + + + NonSecure + The channel group 31 is non-secure + 0x0 + + + + + + + + + + GRTC + Unspecified + UICR_GRTC + read-write + 0x660 + + CC + Unspecified + UICR_GRTC_CC + read-write + 0x000 + + OWN + Request ownership of the CCs of GRTCGRTC + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + CC_0 + Capture/compare register number + 0 + 0 + + + NotOwn + Do not own the CC register 0 + 0x1 + + + Own + Own the CC register 0 + 0x0 + + + + + CC_1 + Capture/compare register number + 1 + 1 + + + NotOwn + Do not own the CC register 1 + 0x1 + + + Own + Own the CC register 1 + 0x0 + + + + + CC_2 + Capture/compare register number + 2 + 2 + + + NotOwn + Do not own the CC register 2 + 0x1 + + + Own + Own the CC register 2 + 0x0 + + + + + CC_3 + Capture/compare register number + 3 + 3 + + + NotOwn + Do not own the CC register 3 + 0x1 + + + Own + Own the CC register 3 + 0x0 + + + + + CC_4 + Capture/compare register number + 4 + 4 + + + NotOwn + Do not own the CC register 4 + 0x1 + + + Own + Own the CC register 4 + 0x0 + + + + + CC_5 + Capture/compare register number + 5 + 5 + + + NotOwn + Do not own the CC register 5 + 0x1 + + + Own + Own the CC register 5 + 0x0 + + + + + CC_6 + Capture/compare register number + 6 + 6 + + + NotOwn + Do not own the CC register 6 + 0x1 + + + Own + Own the CC register 6 + 0x0 + + + + + CC_7 + Capture/compare register number + 7 + 7 + + + NotOwn + Do not own the CC register 7 + 0x1 + + + Own + Own the CC register 7 + 0x0 + + + + + CC_8 + Capture/compare register number + 8 + 8 + + + NotOwn + Do not own the CC register 8 + 0x1 + + + Own + Own the CC register 8 + 0x0 + + + + + CC_9 + Capture/compare register number + 9 + 9 + + + NotOwn + Do not own the CC register 9 + 0x1 + + + Own + Own the CC register 9 + 0x0 + + + + + CC_10 + Capture/compare register number + 10 + 10 + + + NotOwn + Do not own the CC register 10 + 0x1 + + + Own + Own the CC register 10 + 0x0 + + + + + CC_11 + Capture/compare register number + 11 + 11 + + + NotOwn + Do not own the CC register 11 + 0x1 + + + Own + Own the CC register 11 + 0x0 + + + + + CC_12 + Capture/compare register number + 12 + 12 + + + NotOwn + Do not own the CC register 12 + 0x1 + + + Own + Own the CC register 12 + 0x0 + + + + + CC_13 + Capture/compare register number + 13 + 13 + + + NotOwn + Do not own the CC register 13 + 0x1 + + + Own + Own the CC register 13 + 0x0 + + + + + CC_14 + Capture/compare register number + 14 + 14 + + + NotOwn + Do not own the CC register 14 + 0x1 + + + Own + Own the CC register 14 + 0x0 + + + + + CC_15 + Capture/compare register number + 15 + 15 + + + NotOwn + Do not own the CC register 15 + 0x1 + + + Own + Own the CC register 15 + 0x0 + + + + + + + SECURE + Request permission for the CCs of GRTC + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + CC_0 + Capture/compare register number + 0 + 0 + + + Secure + The CC register 0 is secure + 0x1 + + + NonSecure + The CC register 0 is non-secure + 0x0 + + + + + CC_1 + Capture/compare register number + 1 + 1 + + + Secure + The CC register 1 is secure + 0x1 + + + NonSecure + The CC register 1 is non-secure + 0x0 + + + + + CC_2 + Capture/compare register number + 2 + 2 + + + Secure + The CC register 2 is secure + 0x1 + + + NonSecure + The CC register 2 is non-secure + 0x0 + + + + + CC_3 + Capture/compare register number + 3 + 3 + + + Secure + The CC register 3 is secure + 0x1 + + + NonSecure + The CC register 3 is non-secure + 0x0 + + + + + CC_4 + Capture/compare register number + 4 + 4 + + + Secure + The CC register 4 is secure + 0x1 + + + NonSecure + The CC register 4 is non-secure + 0x0 + + + + + CC_5 + Capture/compare register number + 5 + 5 + + + Secure + The CC register 5 is secure + 0x1 + + + NonSecure + The CC register 5 is non-secure + 0x0 + + + + + CC_6 + Capture/compare register number + 6 + 6 + + + Secure + The CC register 6 is secure + 0x1 + + + NonSecure + The CC register 6 is non-secure + 0x0 + + + + + CC_7 + Capture/compare register number + 7 + 7 + + + Secure + The CC register 7 is secure + 0x1 + + + NonSecure + The CC register 7 is non-secure + 0x0 + + + + + CC_8 + Capture/compare register number + 8 + 8 + + + Secure + The CC register 8 is secure + 0x1 + + + NonSecure + The CC register 8 is non-secure + 0x0 + + + + + CC_9 + Capture/compare register number + 9 + 9 + + + Secure + The CC register 9 is secure + 0x1 + + + NonSecure + The CC register 9 is non-secure + 0x0 + + + + + CC_10 + Capture/compare register number + 10 + 10 + + + Secure + The CC register 10 is secure + 0x1 + + + NonSecure + The CC register 10 is non-secure + 0x0 + + + + + CC_11 + Capture/compare register number + 11 + 11 + + + Secure + The CC register 11 is secure + 0x1 + + + NonSecure + The CC register 11 is non-secure + 0x0 + + + + + CC_12 + Capture/compare register number + 12 + 12 + + + Secure + The CC register 12 is secure + 0x1 + + + NonSecure + The CC register 12 is non-secure + 0x0 + + + + + CC_13 + Capture/compare register number + 13 + 13 + + + Secure + The CC register 13 is secure + 0x1 + + + NonSecure + The CC register 13 is non-secure + 0x0 + + + + + CC_14 + Capture/compare register number + 14 + 14 + + + Secure + The CC register 14 is secure + 0x1 + + + NonSecure + The CC register 14 is non-secure + 0x0 + + + + + CC_15 + Capture/compare register number + 15 + 15 + + + Secure + The CC register 15 is secure + 0x1 + + + NonSecure + The CC register 15 is non-secure + 0x0 + + + + + + + + + 0x10 + 0x4 + IPCMAP[%s] + Description collection: Request configuration for the channel n of IPCMAP + 0x680 + read-write + 0xFFFFFFFF + 0x20 + + + IPCTCHSINK + IPCT channel number (sink side) + 0 + 7 + + + DOMAINIDSINK + Domain ID (sink side) + 8 + 11 + + + IPCTCHSOURCE + IPCT channel number (source side) + 16 + 23 + + + DOMAINIDSOURCE + Domain ID (source side) + 24 + 27 + + + + + 8 + 0x008 + MAILBOX[%s] + Unspecified + UICR_MAILBOX + read-write + 0x700 + + ADDRESS + Description cluster: Memory start address of mailbox n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + ADDRESS + Memory address + 0 + 31 + + + + + CONFIG + Description cluster: Configuration of mailbox n + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + SECURE + Permission + 3 + 3 + + + Secure + The mailbox memory is secure + 0x1 + + + NonSecure + The mailbox memory is non-secure + 0x0 + + + + + OWNERID + Remote owner identification + 8 + 11 + + + SIZE + Memory size + 16 + 31 + + + + + + TRACE + Unspecified + UICR_TRACE + read-write + 0x740 + + ETBSINK + Unspecified + UICR_TRACE_ETBSINK + read-write + 0x000 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + TPIUSINK + Unspecified + UICR_TRACE_TPIUSINK + read-write + 0x004 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + ETRSINK + Unspecified + UICR_TRACE_ETRSINK + read-write + 0x008 + + SOURCES + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + STMMAINCORE + STM trace from the domain main CPU + 0 + 0 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + ETMMAINCORE + ETM trace from the domain main CPU + 1 + 1 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMHWEVENTS + STM HW events trace + 2 + 2 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMPPR + STM trace from PPR CPU + 3 + 3 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + STMFLPR + STM trace from FLPR CPU + 4 + 4 + + + NotRequested + Not Requested + 0x1 + + + Requested + Requested + 0x0 + + + + + + + + PORTCONFIG + Trace port speed configuration + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PORTCONFIG + 0 + 1 + + + FullSpeed + Full speed + 0x3 + + + HalfSpeed + Half speed + 0x2 + + + QuarterSpeed + One quarter speed + 0x1 + + + EightSpeed + One eigth speed + 0x0 + + + + + + + + TAMPER + Unspecified + UICR_TAMPER + read-write + 0x760 + + DETECTION + Tamper policy configuration for detected security events. + UICR_TAMPER_DETECTION + read-write + 0x000 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + GlobalEnable + Enable tamper detection. When disabled all tamper enable and policy switches are ignored. + 0 + 0 + + + Enable + Enable tamper detection. + 0x0 + + + Disable + Disable tamper detection. + 0x1 + + + + + VoltageLevel + Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when voltage on the corresponding supply line is too low. + 1 + 1 + + + Enable + Enable voltage level detectors. + 0x0 + + + Disable + Disable voltage level detectors. + 0x1 + + + + + ExternalActiveShield + Enable external active shield detector. + 4 + 4 + + + Enable + Enable external active shield detector. + 0x0 + + + Disable + Disable external active shield detector. + 0x1 + + + + + HardFault + Configure if tamper prevention should react on hard faults. + 7 + 7 + + + Enable + Enable hard fault detector. + 0x0 + + + Disable + Disable hard fault detector. + 0x1 + + + + + ApiFault + Configure if tamper prevention should react on invalid API usage. + 8 + 8 + + + Enable + Enable API fault detector. + 0x0 + + + Disable + Disable API fault detector. + 0x1 + + + + + AdacFault + Configure if tamper prevention should react on invalid ADAC usage. + 9 + 9 + + + Enable + Enable invalid ADAC usage detector. + 0x0 + + + Disable + Disable invalid ADAC usage detector. + 0x1 + + + + + StateFault + Configure if tamper prevention should react on invalid firmware execution state. + 10 + 10 + + + Enable + Enable invalid firmware execution state detector. + 0x0 + + + Disable + Disable invalid firmware execution state detector. + 0x1 + + + + + TemperatureFault + Configure if tamper prevention should react when on-die temperature exceeds a valid range. + 11 + 11 + + + Enable + Enable invalid out-of-range temperature detector. + 0x0 + + + Disable + Disable invalid out-of-range temperature detector. + 0x1 + + + + + + + RESPONSE0 + Unspecified + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + VoltageLevel + Configure tamper policy for invalid voltage level on supply lines. + 0 + 3 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + Watchdog + Configure tamper policy for watchdog timer. + 4 + 7 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ExternalActiveShield + Configure tamper policy for external active shield. BICR is used to specify which channels (GPIOs) are enabled. + 12 + 15 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + InternalDetectors + Configure tamper policy for internal detectors including glitch detector, signal protector and CRACEN detector. See for more information. An automatic reset is issued upon detection. + 20 + 23 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + HardFault + Configure tamper policy for hard fault. + 24 + 27 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + ApiFault + Configure tamper policy for invalid API usage. + 28 + 31 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + RESPONSE1 + Unspecified + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + AdacFault + Configure tamper policy for invalid ADAC usage. + 0 + 3 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + StateFault + Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure domain before secure services are permitted again. + 4 + 7 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + TemperatureFault + Configure out-of-range on-die temperature tamper policy. A reset is required to continue providing secure services once the on-temperature is within valid operating conditions again. This reset is automatically triggered by the secure domain. + 8 + 11 + + + Manual + Block secure services until requested to unblock secure services. Allows user application to take required actions. + 0x1 + + + PowerCycle + Block secure services until power cycling the device. + 0x2 + + + 15Minutes + Block secure services until device has been powered and idle for 15 minutes. + 0x3 + + + 1Hour + Block secure services until device has been powered and idle for one hour. + 0x4 + + + LCSDiscarded + Transition to LCS Discarded. Warning, this bricks the device permanently. + 0xA + + + ResetOnly + No addition penalty besides the automatic reset. + 0xF + + + + + + + TEMPDETECTORCONFIG + Unspecified + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TemperatureDetectionStrategy + Configure when on-die temperature sensor should check the temperature. + 0 + 1 + + + Periodically + On-die temperature sensor is read periodically with selected interval. + 0x1 + + + OnServiceCallAndPeriodically + On-die temperature sensor is read before each secure service call and periodically with selected interval. + 0x2 + + + OnServiceCallOnly + On-die temperature sensor is read before each secure service call. + 0x3 + + + + + TemperatureDetectionInterval + Configure interval for on-die temperature reading if periodic reading is enabled. + 2 + 3 + + + 1Minute + On-die temperature sensor is read with one minute intervals. + 0x0 + + + 15Minutes + On-die temperature sensor is read with 15 minutes intervals. + 0x2 + + + 1Hour + On-die temperature sensor is read with one hour intervals. + 0x3 + + + + + LowTemperatureThresholdShift + Low temperature detection threshold shift in degrees Celsius. The low temperature threshold is calculated by adding the threshold shift to the minimum operating temperature of the SoC. + 4 + 11 + + + HighTemperatureThresholdShift + High temperature detection threshold shift in degrees Celsius. The high temperature threshold is calculated by subtracting the threshold shift from the maximum operating temperature of the SoC. + 12 + 19 + + + + + + COUNTERMEASURES + Configuration of countermeasures. + UICR_TAMPER_COUNTERMEASURES + read-write + 0x010 + + ENABLE + Unspecified + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + DPAAES + Configure Differential Power Analysis countermeasure for CRACEN AES. + 0 + 0 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + DPAPK + Configure Differential Power Analysis countermeasure for CRACEN PK. + 1 + 1 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + ClockDithering + Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on TRNG. + 9 + 9 + + + Enable + Enable countermeasure. + 0x0 + + + Disable + Disable countermeasure. + 0x1 + + + + + + + + + INITSVTOR + Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. + 0x780 + read-write + 0xFFFFFFFF + 0x20 + + + INITSVTOR + Initial value of the VTOR. + 0 + 31 + + + + + INITNSVTOR + Initial value of the non-secure VTOR (Vector Table Offset Register). + 0x784 + read-write + 0xFFFFFFFF + 0x20 + + + INITNSVTOR + Initial value of the VTOR. + 0 + 31 + + + + + PTREXTUICR + Pointer to extended UICR. + 0x7FC + read-write + 0xFFFFFFFF + 0x20 + + + PTREXTUICR + Pointer to extended UICR. + 0 + 31 + + + + + + + GLOBAL_FICR_NS + Factory Information Configuration Registers + 0x0FFFE000 + FICR + + + + 0 + 0xC00 + registers + + FICR + 0x20 + + + BLE + Unspecified + FICR_BLE + read-write + 0x00C + + ADDRTYPE + Device address type. + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + TYPE + Device address type. + 0 + 0 + + + Public + Public address. + 0x0 + + + Random + Random address. + 0x1 + + + + + + + 0x2 + 0x4 + ADDR[%s] + Description collection: 48 bit device address. + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + ADDR + Device address [n]. + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption Root. + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + ER + Encryption root word [n]. + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity Root. + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + IR + Identity root word [n]. + 0 + 31 + + + + + + INFO + Device info + FICR_INFO + read-write + 0x050 + + CONFIGID + Configuration identifier + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + HWID + Identification number for the HW + 0 + 15 + + + + + PART + Part code + 0x004 + read-only + 0xFFFFFFFF + 0x20 + + + PART + Part code + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part Variant, Hardware version and Production configuration + 0x008 + read-only + 0xFFFFFFFF + 0x20 + + + VARIANT + Part Variant, Hardware version and Production configuration, encoded as ASCII + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x00C + read-only + 0xFFFFFFFF + 0x20 + + + PACKAGE + Package option + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x010 + read-only + 0xFFFFFFFF + 0x20 + + + RAM + RAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + MRAM + MRAM variant + 0x014 + read-only + 0xFFFFFFFF + 0x20 + + + MRAM + MRAM variant + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODEPAGESIZE + Code memory page size in bytes + 0x018 + read-only + 0x00001000 + 0x20 + + + CODEPAGESIZE + Code memory page size in bytes + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + CODESIZE + Code memory size + 0x01C + read-only + 0x00000100 + 0x20 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + DEVICETYPE + Device type + 0x020 + read-only + 0x00000000 + 0x20 + + + DEVICETYPE + Device type + 0 + 31 + + + Die + Device is an physical DIE + 0x00000000 + + + FPGA + Device is an FPGA + 0xFFFFFFFF + + + + + + + + SIPINFO + SIP-specific device info + FICR_SIPINFO + read-write + 0x080 + + PARTNO + SIP part number + 0x000 + read-only + 0xFFFFFFFF + 0x20 + + + PARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWREVISION[%s] + Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A + 0x004 + read-only + 0xFF + uint8_t + 0x8 + + + HWREVISION + 0 + 7 + + + + + 0x4 + 0x1 + VARIANT[%s] + Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA + 0x008 + read-only + 0xFF + uint8_t + 0x8 + + + VARIANT + 0 + 7 + + + + + PMICVERSION + PMIC version + 0x00C + read-only + 0x00000000 + 0x20 + + + PMICVERSION + PMIC version, incremental code + 0 + 31 + + + + + 0x4 + 0x1 + TESTSITE[%s] + Description collection: Test site, in ascii + 0x010 + read-only + 0x00 + uint8_t + 0x8 + + + LOT + Lot number + test index in hex format (number digits 0-9). + 0x014 + read-only + 0x00000000 + 0x20 + + + LOTID + Lot number in hex format + 0 + 23 + + + TESTID + Test ID in hex format + 24 + 31 + + + + + 0x4 + 0x1 + TESTPROGRAMID[%s] + Description collection: Test program id, in ascii + 0x018 + read-only + 0x00 + uint8_t + 0x8 + + + OSATPARTNO + OSAT part number + 0x01C + read-only + 0xFFFFFFFF + 0x20 + + + OSATPARTNO + 0 + 31 + + + + + 0x4 + 0x1 + HWBUILDVERSION[%s] + Description collection: OSAT production build version + 0x020 + read-only + 0xFF + uint8_t + 0x8 + + + OVERRIDE + Unspecified + FICR_SIPINFO_OVERRIDE + read-write + 0x024 + + LFOSC + Unspecified + FICR_SIPINFO_OVERRIDE_LFOSC + read-write + 0x000 + + CONFIG + LF oscillator configuration. Note. This configuration overrides corresponding LF oscillator configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + SRC + LF oscillator source. + 0 + 3 + + + Unconfigured + LF oscillator source is unconfigured. Default will be used. + 0xF + + + LFXO + Use LFXO as source for the LF oscillator. + 0x0 + + + LFRC + Use LFRC as source for the LF oscillator. + 0x1 + + + LFLPRC + Use LFLPRC as source for the LF oscillator. + 0x2 + + + Synth + Use LF Synth as source for the LF oscillator. + 0x3 + + + + + + + LFXOCONFIG + LFXO configuration. Note. This configuration overrides corresponding LFXO configuration in BICR when set. + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + ACCURACY + LFXO crystal or external signal accuracy. + 0 + 3 + + + Unconfigured + The accuracy is unconfigured. + 0xF + + + 500ppm + LFXO crystal or external signal has an accuracy of 500 ppm. + 0x0 + + + 250ppm + LFXO crystal or external signal has an accuracy of 250 ppm. + 0x1 + + + 150ppm + LFXO crystal or external signal has an accuracy of 150 ppm. + 0x2 + + + 100ppm + LFXO crystal or external signal has an accuracy of 100 ppm. + 0x3 + + + 75ppm + LFXO crystal or external signal has an accuracy of 75 ppm. + 0x4 + + + 50ppm + LFXO crystal or external signal has an accuracy of 50 ppm. + 0x5 + + + 30ppm + LFXO crystal or external signal has an accuracy of 30 ppm. + 0x6 + + + 20ppm + LFXO crystal or external signal has an accuracy of 20 ppm. + 0x7 + + + + + MODE + LFXO mode. LFXO will not start unless MODE is configured. + 4 + 6 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Pierce + LFXO Pierce mode. + 0x0 + + + PIXO + LFXO PIXO mode. + 0x1 + + + ExtSine + LFXO in external sine wave mode. + 0x2 + + + ExtSquare + LFXO in external square wave mode. + 0x3 + + + + + LOADCAP + Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. + 8 + 15 + + + Unconfigured + The built-in load capacitors is unconfigured. LFXO will not start unless LOADCAP is configured. + 0xFF + + + External + Do not use the built-in load capacitors, only external capacitors will be used. + 0x00 + + + + + TIME + LFXO startup time in ms. + 16 + 27 + + + Unconfigured + Startup time has not been configured. + 0xFFF + + + + + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. Note. This configuration overrides corresponding LFXO calibration in BICR when set. + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + LFXOCAL + LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, load capacitance, or crystal swap. + 0 + 31 + + + Calibrate + Calibrate the LFXO at startup. + 0xFFFFFFFF + + + + + + + LFRCAUTOCALCONFIG + LFRC autocalibration configuration. Note. This configuration overrides corresponding LFRC autocalibration configuration in BICR when set. + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + TEMPINTERVAL + Temperature measurement interval in 0.25 s steps. + 0 + 6 + + + TEMPDELTA + Temperature delta that should trigger a calibration in 0.25 degrees steps. + 8 + 13 + + + INTERVALMAXNO + Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature changes. + 16 + 20 + + + ENABLE + LFRC.AUTOCALCONFIG register enable. + 31 + 31 + + + Enabled + LFRC.AUTOCALCONFIG register has been configured and can be used. + 0x0 + + + Disabled + LFRC.AUTOCALCONFIG register has not been configured and cannot be used. + 0x1 + + + + + + + + HFXO64M + Unspecified + FICR_SIPINFO_OVERRIDE_HFXO64M + read-write + 0x010 + + CONFIG + HFXO64M configuration. Note. This configuration overrides corresponding XO configuration in BICR when set. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MODE + HFXO64M mode. + 0 + 2 + + + Unconfigured + The mode is unconfigured. + 0x7 + + + Normal + Normal operating mode. + 0x0 + + + TCXO + TCXO/bypass mode + 0x1 + + + Crystal2 + Reserved value + 0x2 + + + Crystal3 + Reserved value + 0x3 + + + Crystal4 + Reserved value + 0x4 + + + Crystal5 + Reserved value + 0x5 + + + Crystal6 + Reserved value + 0x6 + + + + + + + + + + TRIM + Unspecified + FICR_TRIM + read-write + 0x100 + + GLOBAL + Unspecified + FICR_TRIM_GLOBAL + read-write + 0x244 + + SAADC + Unspecified + FICR_TRIM_GLOBAL_SAADC + read-write + 0x0 + + CALVREF + Trim value for GLOBAL.SAADC.CALVREF + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x3 + 0x4 + CALGAIN[%s] + Description collection: Trim value for GLOBAL.SAADC.CALGAIN + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALOFFSET + Trim value for GLOBAL.SAADC.CALOFFSET + 0x10 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Trim value for GLOBAL.SAADC.LINCALCOEFF + 0x14 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALIREF + Trim value for GLOBAL.SAADC.CALIREF + 0x2C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + CALVREFTC + Trim value for GLOBAL.SAADC.CALVREFTC + 0x30 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + CANPLL + Unspecified + FICR_TRIM_GLOBAL_CANPLL + read-write + 0x3C + + TRIM + Unspecified + FICR_TRIM_GLOBAL_CANPLL_TRIM + read-write + 0x0 + + CTUNE + Trim value for GLOBAL.CANPLL.TRIM.CTUNE + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + COMP + Unspecified + FICR_TRIM_GLOBAL_COMP + read-write + 0x4C + + REFTRIM + Trim value for GLOBAL.COMP.REFTRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + APPLICATION + Unspecified + FICR_TRIM_APPLICATION + read-write + 0x298 + + HSFLL + Unspecified + FICR_TRIM_APPLICATION_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_APPLICATION_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for APPLICATION.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for APPLICATION.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_APPLICATION_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + RADIOCORE + Unspecified + FICR_TRIM_RADIOCORE + read-write + 0x2DC + + HSFLL + Unspecified + FICR_TRIM_RADIOCORE_HSFLL + read-write + 0x0 + + TRIM + Unspecified + FICR_TRIM_RADIOCORE_HSFLL_TRIM + read-write + 0x0 + + VSUP + Trim value for RADIOCORE.HSFLL.TRIM.VSUP + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + COARSE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.COARSE + 0x4 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + 0x6 + 0x4 + FINE[%s] + Description collection: Trim value for RADIOCORE.HSFLL.TRIM.FINE + 0x1C + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + MEMCONF + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF + read-write + 0x34 + + 4 + 0x004 + BLOCKTYPE[%s] + Unspecified + FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE + read-write + 0x0 + + TRIM + Description cluster: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM + 0x0 + read-only + 0xFFFFFFFF + 0x20 + + + VALUE + Trim value + 0 + 31 + + + + + + + + + + + DCACHEDATA_S + CACHEDATA + 0x23F00000 + DCACHEDATA + + + + 0 + 0x1000 + registers + + DCACHEDATA + 0x20 + + + 256 + 0x040 + SET[%s] + Unspecified + DCACHEDATA_SET + read-write + 0x0 + + 2 + 0x020 + WAY[%s] + Unspecified + DCACHEDATA_SET_WAY + read-write + 0x0 + + 8 + 0x004 + DU[%s] + Unspecified + DCACHEDATA_SET_WAY_DU + read-write + 0x0 + + 0x1 + 0x4 + DATA[%s] + Description collection: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + Data + Data + 0 + 31 + read-only + + + + + + + + + + DCACHEINFO_S + CACHEINFO + 0x23F10000 + DCACHEINFO + + + + 0 + 0x1000 + registers + + DCACHEINFO + 0x20 + + + 256 + 0x010 + SET[%s] + Unspecified + DCACHEINFO_SET + read-write + 0x0 + + 2 + 0x008 + WAY[%s] + Unspecified + DCACHEINFO_SET_WAY + read-write + 0x0 + + INFO + Description cluster: Cache information for SET[n], WAY[o]. + 0x0 + read-write + 0x00000000 + 0x20 + + + TAG + Cache tag. + 0 + 19 + read-only + + + DUV_0 + Data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_1 + Data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_2 + Data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUV_3 + Data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + D0 + Dirty status of combined data unit 0 and 1. + 28 + 28 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D1 + Dirty status of combined data unit 2 and 3. + 29 + 29 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + V + Line valid bit. + 30 + 30 + read-only + + + Invalid + Invalid cache line + 0x0 + + + Valid + Valid cache line + 0x1 + + + + + MRU + Most recently used way. + 31 + 31 + read-only + + + Way0 + Way0 was most recently used + 0x0 + + + Way1 + Way1 was most recently used + 0x1 + + + + + + + INFOEXT + Description cluster: Extended cache information for SET[n], WAY[o]. + 0x4 + read-write + 0x00000000 + 0x20 + + + D_0 + Dirty status. + 16 + 16 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_1 + Dirty status. + 17 + 17 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_2 + Dirty status. + 18 + 18 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_3 + Dirty status. + 19 + 19 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_4 + Dirty status. + 20 + 20 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_5 + Dirty status. + 21 + 21 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_6 + Dirty status. + 22 + 22 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + D_7 + Dirty status. + 23 + 23 + read-only + + + Clean + Clean data unit + 0x0 + + + Dirty + Dirty data unit + 0x1 + + + + + DUVEXT_0 + Extended data unit valid info. + 24 + 24 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_1 + Extended data unit valid info. + 25 + 25 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_2 + Extended data unit valid info. + 26 + 26 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + DUVEXT_3 + Extended data unit valid info. + 27 + 27 + read-only + + + Invalid + Invalid data unit + 0x0 + + + Valid + Valid data unit + 0x1 + + + + + + + + + + + GLOBAL_USBHSCORE0_NS + USBHSCORE 0 + 0x2F700000 + USBHSCORE + + + + 0 + 0x24000 + registers + + USBHSCORE + 0x20 + + + GOTGCTL + Control and Status Register + 0x000 + read-write + 0x000D0000 + 0x20 + + + VBVALIDOVEN + Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) + 2 + 2 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller + 0x0 + + + ENABLED + The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal + 0x1 + + + + + VBVALIDOVVAL + Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) + 3 + 3 + + + SET0 + vbusvalid value when GOTGCTL.VbvalidOvEn = 1 + 0x0 + + + SET1 + vbusvalid value when GOTGCTL.VbvalidOvEn is 1 + 0x1 + + + + + AVALIDOVEN + Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) + 4 + 4 + + + DISABLED + Derive AValid from PHY + 0x0 + + + ENABLED + Derive Avalid from GOTGCTL.AvalidOvVal + 0x1 + + + + + AVALIDOVVAL + Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) + 5 + 5 + + + VALUE0 + Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 + 0x0 + + + VALUE1 + Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 + 0x1 + + + + + BVALIDOVEN + Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) + 6 + 6 + + + DISABLED + Override is disabled and bvalid signal from the respective PHY selected is used internally by the core + 0x0 + + + ENABLED + Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal + 0x1 + + + + + BVALIDOVVAL + Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) + 7 + 7 + + + VALUE0 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x0 + + + VALUE1 + Bvalid value when GOTGCTL.BvalidOvEn =1 + 0x1 + + + + + DBNCEFLTRBYPASS + Mode: Host and Device. Debounce Filter Bypass + 15 + 15 + + + DISABLED + Debounce Filter Bypass is disabled. + 0x0 + + + ENABLED + Debounce Filter Bypass is enabled. + 0x1 + + + + + CONIDSTS + Mode: Host and Device. Connector ID Status (ConIDSts) + 16 + 16 + read-only + + + MODEA + The core is in A-Device mode. + 0x0 + + + MODEB + The core is in B-Device mode. + 0x1 + + + + + DBNCTIME + Mode: Host only. Long/Short Debounce Time (DbncTime) + 17 + 17 + read-only + + + LONG + Long debounce time, used for physical connections (100 ms + 2.5 micro-sec) + 0x0 + + + SHORT + Short debounce time, used for soft connections (2.5 micro-sec) + 0x1 + + + + + ASESVLD + Mode: Host only. A-Session Valid (ASesVld) + 18 + 18 + read-only + + + NOTVALID + A-session is not valid. + 0x0 + + + VALID + A-session is valid. + 0x1 + + + + + BSESVLD + Mode: Device only. B-Session Valid (BSesVld) + 19 + 19 + read-only + + + NOTVALID + B-session is not valid. + 0x0 + + + VALID + B-session is valid. + 0x1 + + + + + OTGVER + OTG Version (OTGVer) + 20 + 20 + + + VER13 + Supports OTG Version 1.3 + 0x0 + + + VER20 + Supports OTG Version 2.0 + 0x1 + + + + + CURMOD + Current Mode of Operation (CurMod) + 21 + 21 + read-only + + + DEVICEMODE + Current mode is device mode. + 0x0 + + + HOSTMODE + Current mode is host mode. + 0x1 + + + + + MULTVALIDBC + Mode: Host and Device. Multi Valued ID pin (MultValIdBC) + 22 + 26 + read-only + + + RID_C + B-Device connected to ACA. VBUS is on. + 0x01 + + + RID_B + B-Device connected to ACA. VBUS is off. + 0x02 + + + RID_A + A-Device connected to ACA + 0x04 + + + RID_GND + A-Device not connected to ACA + 0x08 + + + RID_FLOAT + B-Device not connected to ACA + 0x10 + + + + + CHIRPEN + Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used + 27 + 27 + + + CHIRP_DISABLE + The controller does not assert chirp_on before sending an actual Chirp 'K' signal on USB. + 0x0 + + + CHIRP_ENABLE + The controller asserts chirp_on before sending an actual Chirp 'K' signal on USB. + 0x1 + + + + + + + GOTGINT + Interrupt Register + 0x004 + read-write + 0x00000000 + 0x20 + + + SESENDDET + Mode: Host and Device. Session End Detected (SesEndDet) + 2 + 2 + + + INACTIVE + Session is Active + 0x0 + + + ACTIVE + SessionEnd utmiotg_bvalid signal is deasserted + 0x1 + + + + + SESREQSUCSTSCHNG + Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) + 8 + 8 + + + INACTIVE + No Change in Session Request Status + 0x0 + + + ACTIVE + Session Request Status has changed + 0x1 + + + + + HSTNEGSUCSTSCHNG + Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) + 9 + 9 + + + INACTIVE + No Change + 0x0 + + + ACTIVE + Host Negotiation Status Change + 0x1 + + + + + HSTNEGDET + Mode:Host and Device. Host Negotiation Detected (HstNegDet) + 17 + 17 + + + INACTIVE + No Active HNP Request + 0x0 + + + ACTIVE + Active HNP request detected + 0x1 + + + + + ADEVTOUTCHG + Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) + 18 + 18 + + + INACTIVE + No A-Device Timeout + 0x0 + + + ACTIVE + A-Device Timeout + 0x1 + + + + + DBNCEDONE + Mode: Host only. Debounce Done (DbnceDone) + 19 + 19 + + + INACTIVE + After Connect waiting for Debounce to complete + 0x0 + + + ACTIVE + Debounce completed + 0x1 + + + + + MULTVALIPCHNG + This bit when set indicates that there is a change in the value of at least one ACA pin value. + 20 + 20 + + + NO_ACA_PIN_CHANGE + Indicates there is no change in ACA pin value + 0x0 + + + ACA_PIN_CHANGE + Indicates there is a change in ACA pin value + 0x1 + + + + + + + GAHBCFG + AHB Configuration Register + 0x008 + read-write + 0x00000000 + 0x20 + + + GLBLINTRMSK + Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) + 0 + 0 + + + MASK + Mask the interrupt assertion to the application + 0x0 + + + NOMASK + Unmask the interrupt assertion to the application. + 0x1 + + + + + HBSTLEN + Mode: Host and device. Burst Length/Type (HBstLen) + 1 + 4 + + + WORD1ORSINGLE + 1 word or single + 0x0 + + + WORD4ORINCR + 4 words or INCR + 0x1 + + + WORD8 + 8 words + 0x2 + + + WORD16ORINCR4 + 16 words or INCR4 + 0x3 + + + WORD32 + 32 words + 0x4 + + + WORD64ORINCR8 + 64 words or INCR8 + 0x5 + + + WORD128 + 128 words + 0x6 + + + WORD256ORINCR16 + 256 words or INCR16 + 0x7 + + + WORDX + Others reserved + 0x8 + + + + + DMAEN + Mode: Host and device. DMA Enable (DMAEn) + 5 + 5 + + + SLAVEMODE + Core operates in Slave mode + 0x0 + + + DMAMODE + Core operates in a DMA mode + 0x1 + + + + + NPTXFEMPLVL + Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) + 7 + 7 + + + HALFEMPTY + DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty or that the IN Endpoint TxFIFO is half empty. + 0x0 + + + EMPTY + GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty or that the IN Endpoint TxFIFO is completely empty. + 0x1 + + + + + REMMEMSUPP + Mode: Host and Device. Remote Memory Support (RemMemSupp) + 21 + 21 + + + DISABLED + Remote Memory Support Feature disabled + 0x0 + + + ENABLED + Remote Memory Support Feature enabled + 0x1 + + + + + NOTIALLDMAWRIT + Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) + 22 + 22 + + + LASTTRANS + Unspecified + 0x0 + + + ALLTRANS + The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint + 0x1 + + + + + AHBSINGLE + Mode: Host and Device. AHB Single Support (AHBSingle) + 23 + 23 + + + INCRBURST + The remaining data in the transfer is sent using INCR burst size + 0x0 + + + SINGLEBURST + The remaining data in the transfer is sent using Single burst size + 0x1 + + + + + + + GUSBCFG + USB Configuration Register + 0x00C + read-write + 0x10001400 + 0x20 + + + TOUTCAL + Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) + 0 + 2 + + + ZERO + Add 0 PHY clocks + 0x0 + + + ONE + Add 1 PHY clocks + 0x1 + + + TWO + Add 2 PHY clocks + 0x2 + + + THREE + Add 3 PHY clocks + 0x3 + + + FOUR + Add 4 PHY clocks + 0x4 + + + FIVE + Add 5 PHY clocks + 0x5 + + + SIX + Add 6 PHY clocks + 0x6 + + + SEVEN + Add 7 PHY clocks + 0x7 + + + + + PHYIF + Mode: Host and Device. PHY Interface (PHYIf) + 3 + 3 + + + BITS8 + PHY 8bit Mode + 0x0 + + + BITS16 + PHY 16bit Mode + 0x1 + + + + + ULPIUTMISEL + Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) + 4 + 4 + read-only + + + UTMI + UTMI+ Interface + 0x0 + + + ULPI + ULPI Interface + 0x1 + + + + + FSINTF + Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) + 5 + 5 + read-only + + + FS6PIN + 6-pin unidirectional full-speed serial interface + 0x0 + + + FS3PIN + 3-pin bidirectional full-speed serial interface + 0x1 + + + + + PHYSEL + PHYSel + 6 + 6 + read-only + + + USB20 + USB 2.0 high-speed UTMI+ or ULPI PHY is selected + 0x0 + + + USB11 + USB 1.1 full-speed serial transceiver is selected + 0x1 + + + + + USBTRDTIM + Mode: Device only. USB Turnaround Time (USBTrdTim) + 10 + 13 + + + TURNTIME16BIT + MAC interface is 16-bit UTMI+. + 0x5 + + + TURNTIME8BIT + MAC interface is 8-bit UTMI+. + 0x9 + + + + + PHYLPWRCLKSEL + PHY Low-Power Clock Select (PhyLPwrClkSel) + 15 + 15 + + + INTPLLCLK + 480-MHz Internal PLL clock + 0x0 + + + EXTCLK + 48-MHz External Clock + 0x1 + + + + + TERMSELDLPULSE + Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) + 22 + 22 + + + TXVALID + Data line pulsing using utmi_txvalid + 0x0 + + + TERMSEL + Data line pulsing using utmi_termsel + 0x1 + + + + + ICUSBCAP + Mode: Host and Device. IC_USB-Capable (IC_USBCap) + 26 + 26 + read-only + + + NOTSELECTED + IC_USB PHY Interface is not selected + 0x0 + + + SELECTED + IC_USB PHY Interface is selected + 0x1 + + + + + TXENDDELAY + Mode: Device only. Tx End Delay (TxEndDelay) + 28 + 28 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Tx End delay + 0x1 + + + + + FORCEHSTMODE + Mode: Host and device. Force Host Mode (ForceHstMode) + 29 + 29 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Host Mode + 0x1 + + + + + FORCEDEVMODE + Mode:Host and device. Force Device Mode (ForceDevMode) + 30 + 30 + + + DISABLED + Normal Mode + 0x0 + + + ENABLED + Force Device Mode + 0x1 + + + + + CORRUPTTXPKT + Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) + 31 + 31 + write-only + + + Disabled + Normal Mode + 0x0 + + + Enabled + Debug Mode + 0x1 + + + + + + + GRSTCTL + Reset Register + 0x010 + read-write + 0x80000000 + 0x20 + + + CSFTRST + Mode: Host and Device. Core Soft Reset (CSftRst) + 0 + 0 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Resets hclk and phy_clock domains + 0x1 + + + + + PIUFSSFTRST + Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + 1 + 1 + + + RESET_INACTIVE + No Reset + 0x0 + + + RESET_ACTIVE + PIU FS Dedicated Controller Soft Reset + 0x1 + + + + + FRMCNTRRST + Mode: Host only. Host Frame Counter Reset (FrmCntrRst) + 2 + 2 + + + NOTACTIVE + No reset + 0x0 + + + ACTIVE + Host Frame Counter Reset + 0x1 + + + + + RXFFLSH + Mode: Host and Device. RxFIFO Flush (RxFFlsh) + 4 + 4 + + + INACTIVE + Does not flush the entire RxFIFO + 0x0 + + + ACTIVE + Flushes the entire RxFIFO + 0x1 + + + + + TXFFLSH + Mode: Host and Device. TxFIFO Flush (TxFFlsh) + 5 + 5 + + + INACTIVE + No Flush + 0x0 + + + ACTIVE + Selectively flushes a single or all transmit FIFOs + 0x1 + + + + + TXFNUM + Mode: Host and Device. TxFIFO Number (TxFNum) + 6 + 10 + + + TXF0 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device mode when in shared FIFO operation -TXFIFO 0 flush in device mode when in dedicated FIFO mode + 0x00 + + + TXF1 + -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device mode when in shared FIFO operation -TXFIFO 1 flush in device mode when in dedicated FIFO mode + 0x01 + + + TXF2 + -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation -TXFIFO 2 flush in device mode when in dedicated FIFO mode + 0x02 + + + TXF3 + -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation -TXFIFO 3 flush in device mode when in dedicated FIFO mode + 0x03 + + + TXF4 + -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation -TXFIFO 4 flush in device mode when in dedicated FIFO mode + 0x04 + + + TXF5 + -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation -TXFIFO 5 flush in device mode when in dedicated FIFO mode + 0x05 + + + TXF6 + -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation -TXFIFO 6 flush in device mode when in dedicated FIFO mode + 0x06 + + + TXF7 + -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation -TXFIFO 7 flush in device mode when in dedicated FIFO mode + 0x07 + + + TXF8 + -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation -TXFIFO 8 flush in device mode when in dedicated FIFO mode + 0x08 + + + TXF9 + -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation -TXFIFO 9 flush in device mode when in dedicated FIFO mode + 0x09 + + + TXF10 + -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation -TXFIFO 10 flush in device mode when in dedicated FIFO mode + 0x0A + + + TXF11 + -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation -TXFIFO 11 flush in device mode when in dedicated FIFO mode + 0x0B + + + TXF12 + -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation -TXFIFO 12 flush in device mode when in dedicated FIFO mode + 0x0C + + + TXF13 + -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation -TXFIFO 13 flush in device mode when in dedicated FIFO mode + 0x0D + + + TXF14 + -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation -TXFIFO 14 flush in device mode when in dedicated FIFO mode + 0x0E + + + TXF15 + -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flush in device mode when in dedicated FIFO mode + 0x0F + + + TXF16 + Flush all the transmit FIFOs in device or host mode + 0x10 + + + + + CSFTRSTDONE + Mode: Host and Device. Core Soft Reset Done (CSftRstDone) + 29 + 29 + + + INACTIVE + No reset + 0x0 + + + ACTIVE + Core Soft Reset is done + 0x1 + + + + + DMAREQ + Mode: Host and Device. DMA Request Signal (DMAReq) + 30 + 30 + read-only + + + INACTIVE + No DMA request + 0x0 + + + ACTIVE + DMA request is in progress + 0x1 + + + + + AHBIDLE + Mode: Host and Device. AHB Master Idle (AHBIdle) + 31 + 31 + read-only + + + INACTIVE + Not Idle + 0x0 + + + ACTIVE + AHB Master Idle + 0x1 + + + + + + + GINTSTS + Interrupt Register + 0x014 + read-write + 0x00000020 + 0x20 + + + CURMOD + Mode: Host and Device. Current Mode of Operation (CurMod) + 0 + 0 + read-only + + + DEVICE + Device mode + 0x0 + + + HOST + Host mode + 0x1 + + + + + MODEMIS + Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) + 1 + 1 + + + INACTIVE + No Mode Mismatch Interrupt + 0x0 + + + ACTIVE + Mode Mismatch Interrupt + 0x1 + + + + + OTGINT + Mode: Host and Device. OTG Interrupt (OTGInt) + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + OTG Interrupt + 0x1 + + + + + SOF + Mode: Host and Device. Start of (micro)Frame (Sof) + 3 + 3 + + + INTACTIVE + No Start of Frame + 0x0 + + + ACTIVE + Start of Frame + 0x1 + + + + + RXFLVL + Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) + 4 + 4 + read-only + + + INACTIVE + Rx Fifo is empty + 0x0 + + + ACTIVE + Rx Fifo is not empty + 0x1 + + + + + NPTXFEMP + Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) + 5 + 5 + read-only + + + INACTIVE + Non-periodic TxFIFO is not empty + 0x0 + + + ACTIVE + Non-periodic TxFIFO is empty + 0x1 + + + + + GINNAKEFF + Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) + 6 + 6 + read-only + + + INACTIVE + Global Non-periodic IN NAK not active + 0x0 + + + ACTIVE + Set Global Non-periodic IN NAK bit + 0x1 + + + + + GOUTNAKEFF + Mode: Device only. Global OUT NAK Effective (GOUTNakEff) + 7 + 7 + read-only + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Global OUT NAK Effective + 0x1 + + + + + ERLYSUSP + Mode: Device only. Early Suspend (ErlySusp) + 10 + 10 + + + INACTIVE + No Idle state detected + 0x0 + + + ACTIVE + 3ms of Idle state detected + 0x1 + + + + + USBSUSP + Mode: Device only. USB Suspend (USBSusp) + 11 + 11 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + USB Suspend + 0x1 + + + + + USBRST + Mode: Device only. USB Reset (USBRst) + 12 + 12 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + USB Reset + 0x1 + + + + + ENUMDONE + Mode: Device only. Enumeration Done (EnumDone) + 13 + 13 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Enumeration Done + 0x1 + + + + + ISOOUTDROP + Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + 14 + 14 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Isochronous OUT Packet Dropped Interrupt + 0x1 + + + + + EOPF + Mode: Device only. End of Periodic Frame Interrupt (EOPF) + 15 + 15 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + End of Periodic Frame Interrupt + 0x1 + + + + + RSTRDONEINT + Mode: Device only. Restore Done Interrupt (RstrDoneInt) + 16 + 16 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Restore Done Interrupt + 0x1 + + + + + EPMIS + Mode: Device only. Endpoint Mismatch Interrupt (EPMis) + 17 + 17 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Endpoint Mismatch Interrupt + 0x1 + + + + + IEPINT + Mode: Device only. IN Endpoints Interrupt (IEPInt) + 18 + 18 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + IN Endpoints Interrupt + 0x1 + + + + + OEPINT + Mode: Device only. OUT Endpoints Interrupt (OEPInt) + 19 + 19 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + OUT Endpoints Interrupt + 0x1 + + + + + INCOMPISOIN + Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) + 20 + 20 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Isochronous IN Transfer + 0x1 + + + + + INCOMPLP + Incomplete Periodic Transfer (incomplP) + 21 + 21 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Incomplete Periodic Transfer + 0x1 + + + + + FETSUSP + Mode: Device only. Data Fetch Suspended (FetSusp) + 22 + 22 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Data Fetch Suspended + 0x1 + + + + + RESETDET + Mode: Device only. Reset detected Interrupt (ResetDet) + 23 + 23 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Reset detected Interrupt + 0x1 + + + + + PRTINT + Mode: Host only. Host Port Interrupt (PrtInt) + 24 + 24 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Port Interrupt + 0x1 + + + + + HCHINT + Mode: Host only. Host Channels Interrupt (HChInt) + 25 + 25 + read-only + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Host Channels Interrupt + 0x1 + + + + + LPMINT + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). + 27 + 27 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + LPM Transaction Received Interrupt + 0x1 + + + + + CONIDSTSCHNG + Mode: Host and Device. Connector ID Status Change (ConIDStsChng) + 28 + 28 + + + INACTIVE + Not Active + 0x0 + + + ACTIVE + Connector ID Status Change + 0x1 + + + + + DISCONNINT + Mode: Host only. Disconnect Detected Interrupt (DisconnInt) + 29 + 29 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Disconnect Detected Interrupt + 0x1 + + + + + SESSREQINT + Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) + 30 + 30 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Session Request New Session Detected Interrupt + 0x1 + + + + + WKUPINT + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) + 31 + 31 + + + INACTIVE + Not active + 0x0 + + + ACTIVE + Resume or Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GINTMSK + Interrupt Mask Register + 0x018 + read-write + 0x00000000 + 0x20 + + + MODEMISMSK + Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) + 1 + 1 + + + MASK + Mode Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Mode Mismatch Interrupt Mask + 0x1 + + + + + OTGINTMSK + Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) + 2 + 2 + + + MASK + OTG Interrupt Mask + 0x0 + + + NOMASK + No OTG Interrupt Mask + 0x1 + + + + + SOFMSK + Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) + 3 + 3 + + + MASK + Start of Frame Mask + 0x0 + + + NOMASK + No Start of Frame Mask + 0x1 + + + + + RXFLVLMSK + Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) + 4 + 4 + + + MASK + Receive FIFO Non-Empty Mask + 0x0 + + + NOMASK + No Receive FIFO Non-Empty Mask + 0x1 + + + + + NPTXFEMPMSK + Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) + 5 + 5 + + + MASK + Non-periodic TxFIFO Empty Mask + 0x0 + + + NOMASK + No Non-periodic TxFIFO Empty Mask + 0x1 + + + + + GINNAKEFFMSK + Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + 6 + 6 + + + MASK + Global Non-periodic IN NAK Effective Mask + 0x0 + + + NOMASK + No Global Non-periodic IN NAK Effective Mask + 0x1 + + + + + GOUTNAKEFFMSK + Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) + 7 + 7 + + + MASK + Global OUT NAK Effective Mask + 0x0 + + + NOMASK + No Global OUT NAK Effective Mask + 0x1 + + + + + ERLYSUSPMSK + Mode: Device only. Early Suspend Mask (ErlySuspMsk) + 10 + 10 + + + MASK + Early Suspend Mask + 0x0 + + + NOMASK + No Early Suspend Mask + 0x1 + + + + + USBSUSPMSK + Mode: Device only. USB Suspend Mask (USBSuspMsk) + 11 + 11 + + + MASK + USB Suspend Mask + 0x0 + + + NOMASK + No USB Suspend Mask + 0x1 + + + + + USBRSTMSK + Mode: Device only. USB Reset Mask (USBRstMsk) + 12 + 12 + + + MASK + USB Reset Mask + 0x0 + + + NOMASK + No USB Reset Mask + 0x1 + + + + + ENUMDONEMSK + Mode: Device only. Enumeration Done Mask (EnumDoneMsk) + 13 + 13 + + + MASK + Enumeration Done Mask + 0x0 + + + NOMASK + No Enumeration Done Mask + 0x1 + + + + + ISOOUTDROPMSK + Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + 14 + 14 + + + MASK + Isochronous OUT Packet Dropped Interrupt Mask + 0x0 + + + NOMASK + No Isochronous OUT Packet Dropped Interrupt Mask + 0x1 + + + + + EOPFMSK + Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) + 15 + 15 + + + MASK + End of Periodic Frame Interrupt Mask + 0x0 + + + NOMASK + No End of Periodic Frame Interrupt Mask + 0x1 + + + + + RSTRDONEINTMSK + Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) + 16 + 16 + + + MASK + Restore Done Interrupt Mask + 0x0 + + + NOMASK + No Restore Done Interrupt Mask + 0x1 + + + + + EPMISMSK + Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) + 17 + 17 + + + MASK + Endpoint Mismatch Interrupt Mask + 0x0 + + + NOMASK + No Endpoint Mismatch Interrupt Mask + 0x1 + + + + + IEPINTMSK + Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) + 18 + 18 + + + MASK + IN Endpoints Interrupt Mask + 0x0 + + + NOMASK + No IN Endpoints Interrupt Mask + 0x1 + + + + + OEPINTMSK + Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) + 19 + 19 + + + MASK + OUT Endpoints Interrupt Mask + 0x0 + + + NOMASK + No OUT Endpoints Interrupt Mask + 0x1 + + + + + INCOMPLPMSK + Incomplete Periodic Transfer Mask (incomplPMsk) + 21 + 21 + + + MASK + Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete Isochronous OUT Transfer Mask + 0x0 + + + NOMASK + Host mode: No Incomplete Periodic Transfer MaskDevice mode: No Incomplete Isochronous OUT Transfer Mask + 0x1 + + + + + FETSUSPMSK + Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) + 22 + 22 + + + MASK + Data Fetch Suspended Mask + 0x0 + + + NOMASK + No Data Fetch Suspended Mask + 0x1 + + + + + RESETDETMSK + Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) + 23 + 23 + + + MASK + Reset detected Interrupt Mask + 0x0 + + + NOMASK + No Reset detected Interrupt Mask + 0x1 + + + + + PRTINTMSK + Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) + 24 + 24 + + + MASK + Host Port Interrupt Mask + 0x0 + + + NOMASK + No Host Port Interrupt Mask + 0x1 + + + + + HCHINTMSK + Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) + 25 + 25 + + + MASK + Host Channels Interrupt Mask + 0x0 + + + NOMASK + No Host Channels Interrupt Mask + 0x1 + + + + + LPMINTMSK + Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) + 27 + 27 + + + MASK + LPM Transaction received interrupt Mask + 0x0 + + + NOMASK + No LPM Transaction received interrupt Mask + 0x1 + + + + + CONIDSTSCHNGMSK + Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) + 28 + 28 + + + MASK + Connector ID Status Change Mask + 0x0 + + + NOMASK + No Connector ID Status Change Mask + 0x1 + + + + + DISCONNINTMSK + Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) + 29 + 29 + + + MASK + Disconnect Detected Interrupt Mask + 0x0 + + + NOMASK + No Disconnect Detected Interrupt Mask + 0x1 + + + + + SESSREQINTMSK + Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) + 30 + 30 + + + MASK + Session Request or New Session Detected Interrupt Mask + 0x0 + + + NOMASK + No Session Request or New Session Detected Interrupt Mask + 0x1 + + + + + WKUPINTMSK + Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + 31 + 31 + + + MASK + Resume or Remote Wakeup Detected Interrupt Mask + 0x0 + + + NOMASK + Unmask Resume Remote Wakeup Detected Interrupt + 0x1 + + + + + + + GRXSTSR + Receive Status Debug Read Register + 0x01C + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + DSETUPRX + SETUP data packet received in device mode + 0x6 + + + CHHALT + Channel halted in host mode (triggers an interrupt) + 0x7 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXSTSP + Receive Status Read/Pop Register + 0x020 + read-write + 0x00000000 + 0x20 + + + CHNUM + Channel Number (ChNum) + 0 + 3 + read-only + + + CHEP0 + Channel or EndPoint 0 + 0x0 + + + CHEP1 + Channel or EndPoint 1 + 0x1 + + + CHEP2 + Channel or EndPoint 2 + 0x2 + + + CHEP3 + Channel or EndPoint 3 + 0x3 + + + CHEP4 + Channel or EndPoint 4 + 0x4 + + + CHEP5 + Channel or EndPoint 5 + 0x5 + + + CHEP6 + Channel or EndPoint 6 + 0x6 + + + CHEP7 + Channel or EndPoint 7 + 0x7 + + + CHEP8 + Channel or EndPoint 8 + 0x8 + + + CHEP9 + Channel or EndPoint 9 + 0x9 + + + CHEP10 + Channel or EndPoint 10 + 0xA + + + CHEP11 + Channel or EndPoint 11 + 0xB + + + CHEP12 + Channel or EndPoint 12 + 0xC + + + CHEP13 + Channel or EndPoint 13 + 0xD + + + CHEP14 + Channel or EndPoint 14 + 0xE + + + CHEP15 + Channel or EndPoint 15 + 0xF + + + + + BCNT + Byte Count (BCnt) + 4 + 14 + read-only + + + DPID + Data PID (DPID) + 15 + 16 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA + 0x3 + + + + + PKTSTS + Packet Status (PktSts) indicates the status of the received packet. + 17 + 20 + read-only + + + OUTNAK + Global OUT NAK in device mode (triggers an interrupt) + 0x1 + + + INOUTDPRX + IN data packet received in host mode and OUT data packet received in device mode + 0x2 + + + INOUTTRCOM + IN or OUT transfer completed in both host and device mode (triggers an interrupt) + 0x3 + + + DSETUPCOM + SETUP transaction completed in device mode (triggers an interrupt) + 0x4 + + + DTTOG + Data toggle error (triggers an interrupt) in host mode + 0x5 + + + + + FN + Mode: Device only. Frame Number (FN) + 21 + 24 + read-only + + + + + GRXFSIZ + Receive FIFO Size Register + 0x024 + read-write + 0x00000224 + 0x20 + + + RXFDEP + Mode: Host and Device. RxFIFO Depth (RxFDep) + 0 + 9 + + + + + GNPTXFSIZ + Non-periodic Transmit FIFO Size Register + 0x028 + read-write + 0x02000224 + 0x20 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start Address (NPTxFStAddr) + 0 + 9 + + + NPTXFDEP + Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) + 16 + 25 + + + + + GNPTXSTS + Non-periodic Transmit FIFO/Queue Status Register + 0x02C + read-write + 0x00080200 + 0x20 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) + 0 + 15 + read-only + + + NPTXQSPCAVAIL + Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) + 16 + 23 + read-only + + + FULL + Non-periodic Transmit Request Queue is full + 0x00 + + + QUE1 + 1 location available + 0x01 + + + QUE2 + 2 locations available + 0x02 + + + QUE3 + 3 locations available + 0x03 + + + QUE4 + 4 locations available + 0x04 + + + QUE5 + 5 locations available + 0x05 + + + QUE6 + 6 locations available + 0x06 + + + QUE7 + 7 locations available + 0x07 + + + QUE8 + 8 locations available + 0x08 + + + + + NPTXQTOP + Top of the Non-periodic Transmit Request Queue (NPTxQTop) + 24 + 30 + read-only + + + INOUTTK + IN/OUT token + 0x00 + + + ZEROTX + Zero-length transmit packet (device IN/host OUT) + 0x01 + + + PINGCSPLIT + PING/CSPLIT token + 0x02 + + + CHNHALT + Channel halt command + 0x03 + + + + + + + GGPIO + General Purpose Input/Output Register + 0x038 + read-write + 0x00000000 + 0x20 + + + GPI + 0 + 15 + read-only + + + GPO + 16 + 31 + + + + + GUID + User ID Register + 0x03C + read-write + 0x00000000 + 0x20 + + + GUID + User ID (UserID) Application-programmable ID field. + 0 + 31 + + + + + GSNPSID + Synopsys ID Register + 0x040 + read-write + 0x4F54430A + 0x20 + + + SYNOPSYSID + Release number of the controller being used currently. + 0 + 31 + read-only + + + + + GHWCFG1 + User Hardware Configuration 1 Register + 0x044 + read-write + 0xAA555000 + 0x20 + + + EPDIR + This 32-bit field uses two bits per + 0 + 31 + read-only + + + + + GHWCFG2 + User Hardware Configuration 2 Register + 0x048 + read-write + 0x228BFC72 + 0x20 + + + OTGMODE + Mode of Operation (OtgMode) + 0 + 2 + read-only + + + HNPSRP + HNP- and SRP-Capable OTG (Host and Device) + 0x0 + + + SRPOTG + SRP-Capable OTG (Host and Device) + 0x1 + + + NHNPNSRP + Non-HNP and Non-SRP Capable OTG (Host and Device) + 0x2 + + + SRPCAPD + SRP-Capable Device + 0x3 + + + NONOTGD + Non-OTG Device + 0x4 + + + SRPCAPH + SRP-Capable Host + 0x5 + + + NONOTGH + Non-OTG Host + 0x6 + + + + + OTGARCH + Architecture (OtgArch) + 3 + 4 + read-only + + + SLAVEMODE + Slave Mode + 0x0 + + + EXTERNALDMA + External DMA Mode + 0x1 + + + INTERNALDMA + Internal DMA Mode + 0x2 + + + + + SINGPNT + Point-to-Point (SingPnt) + 5 + 5 + read-only + + + MULTIPOINT + Multi-point application (hub and split support) + 0x0 + + + SINGLEPOINT + Single-point application (no hub and split support) + 0x1 + + + + + HSPHYTYPE + High-Speed PHY Interface Type (HSPhyType) + 6 + 7 + read-only + + + NOHS + High-Speed interface not supported + 0x0 + + + UTMIPLUS + High Speed Interface UTMI+ is supported + 0x1 + + + ULPI + High Speed Interface ULPI is supported + 0x2 + + + UTMIPUSULPI + High Speed Interfaces UTMI+ and ULPI is supported + 0x3 + + + + + FSPHYTYPE + Full-Speed PHY Interface Type (FSPhyType) + 8 + 9 + read-only + + + NO_FS + Full-speed interface not supported + 0x0 + + + FS + Dedicated full-speed interface is supported + 0x1 + + + FSPLUSUTMI + FS pins shared with UTMI+ pins is supported + 0x2 + + + FSPLUSULPI + FS pins shared with ULPI pins is supported + 0x3 + + + + + NUMDEVEPS + Number of Device Endpoints (NumDevEps) + 10 + 13 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + NUMHSTCHNL + Number of Host Channels (NumHstChnl) + 14 + 17 + read-only + + + HOSTCH0 + Host Channel 1 + 0x0 + + + HOSTCH1 + Host Channel 2 + 0x1 + + + HOSTCH2 + Host Channel 3 + 0x2 + + + HOSTCH3 + Host Channel 4 + 0x3 + + + HOSTCH4 + Host Channel 5 + 0x4 + + + HOSTCH5 + Host Channel 6 + 0x5 + + + HOSTCH6 + Host Channel 7 + 0x6 + + + HOSTCH7 + Host Channel 8 + 0x7 + + + HOSTCH8 + Host Channel 9 + 0x8 + + + HOSTCH9 + Host Channel 10 + 0x9 + + + HOSTCH10 + Host Channel 11 + 0xA + + + HOSTCH11 + Host Channel 12 + 0xB + + + HOSTCH12 + Host Channel 13 + 0xC + + + HOSTCH13 + Host Channel 14 + 0xD + + + HOSTCH14 + Host Channel 15 + 0xE + + + HOSTCH15 + Host Channel 16 + 0xF + + + + + PERIOSUPPORT + Periodic OUT Channels Supported in Host Mode (PerioSupport) + 18 + 18 + read-only + + + DISABLED + Periodic OUT Channels is not supported in Host Mode + 0x0 + + + ENABLED + Periodic OUT Channels Supported in Host Mode Supported + 0x1 + + + + + DYNFIFOSIZING + Dynamic FIFO Sizing Enabled (DynFifoSizing) + 19 + 19 + read-only + + + DISABLED + Dynamic FIFO Sizing Disabled + 0x0 + + + ENABLED + Dynamic FIFO Sizing Enabled + 0x1 + + + + + MULTIPROCINTRPT + Multi Processor Interrupt Enabled (MultiProcIntrpt) + 20 + 20 + read-only + + + DISABLED + No Multi Processor Interrupt Enabled + 0x0 + + + ENABLED + Multi Processor Interrupt Enabled + 0x1 + + + + + NPTXQDEPTH + Non-periodic Request Queue Depth (NPTxQDepth) + 22 + 23 + read-only + + + TWO + Queue size 2 + 0x0 + + + FOUR + Queue size 4 + 0x1 + + + EIGHT + Queue size 8 + 0x2 + + + + + PTXQDEPTH + Host Mode Periodic Request Queue Depth (PTxQDepth) + 24 + 25 + read-only + + + QUE2 + Queue Depth 2 + 0x0 + + + QUE4 + Queue Depth 4 + 0x1 + + + QUE8 + Queue Depth 8 + 0x2 + + + QUE16 + Queue Depth 16 + 0x3 + + + + + TKNQDEPTH + Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) + 26 + 30 + read-only + + + + + GHWCFG3 + User Hardware Configuration 3 Register + 0x04C + read-write + 0x0BEAC0E8 + 0x20 + + + XFERSIZEWIDTH + Width of Transfer Size Counters (XferSizeWidth) + 0 + 3 + read-only + + + WIDTH11 + Width of Transfer Size Counter 11 bits + 0x0 + + + WIDTH12 + Width of Transfer Size Counter 12 bits + 0x1 + + + WIDTH13 + Width of Transfer Size Counter 13 bits + 0x2 + + + WIDTH14 + Width of Transfer Size Counter 14 bits + 0x3 + + + WIDTH15 + Width of Transfer Size Counter 15 bits + 0x4 + + + WIDTH16 + Width of Transfer Size Counter 16 bits + 0x5 + + + WIDTH17 + Width of Transfer Size Counter 17 bits + 0x6 + + + WIDTH18 + Width of Transfer Size Counter 18 bits + 0x7 + + + WIDTH19 + Width of Transfer Size Counter 19 bits + 0x8 + + + + + PKTSIZEWIDTH + Width of Packet Size Counters (PktSizeWidth) + 4 + 6 + read-only + + + BITS4 + Width of Packet Size Counter 4 + 0x0 + + + BITS5 + Width of Packet Size Counter 5 + 0x1 + + + BITS6 + Width of Packet Size Counter 6 + 0x2 + + + BITS7 + Width of Packet Size Counter 7 + 0x3 + + + BITS8 + Width of Packet Size Counter 8 + 0x4 + + + BITS9 + Width of Packet Size Counter 9 + 0x5 + + + BITS10 + Width of Packet Size Counter 10 + 0x6 + + + + + OTGEN + OTG Function Enabled (OtgEn) + 7 + 7 + read-only + + + DISABLED + Not OTG Capable + 0x0 + + + ENABLED + OTG Capable + 0x1 + + + + + I2CINTSEL + I2C Selection (I2CIntSel) + 8 + 8 + read-only + + + DISABLED + I2C Interface is not available + 0x0 + + + ENABLED + I2C Interface is available + 0x1 + + + + + VNDCTLSUPT + Vendor Control Interface Support (VndctlSupt) + 9 + 9 + read-only + + + DISABLED + Vendor Control Interface is not available. + 0x0 + + + ENABLED + Vendor Control Interface is available. + 0x1 + + + + + OPTFEATURE + Optional Features Removed (OptFeature) + 10 + 10 + read-only + + + DISABLED + Optional features were not Removed + 0x0 + + + ENABLED + Optional Features have been Removed + 0x1 + + + + + RSTTYPE + Reset Style for Clocked always Blocks in RTL (RstType) + 11 + 11 + read-only + + + ASYNCRST + Asynchronous reset is used in the core + 0x0 + + + SYNCRST + Synchronous reset is used in the core + 0x1 + + + + + ADPSUPPORT + This bit indicates whether ADP logic is present within or external to the controller + 12 + 12 + read-only + + + DISABLED + ADP logic is not present along with the controller + 0x0 + + + ENABLED + ADP logic is present along with the controller + 0x1 + + + + + HSICMODE + HSIC mode specified for Mode of Operation + 13 + 13 + read-only + + + DISABLED + No HSIC capability + 0x0 + + + ENABLED + HSIC-capable with shared UTMI PHY interface + 0x1 + + + + + BCSUPPORT + This bit indicates the controller support for Battery Charger. + 14 + 14 + read-only + + + DISABLED + No Battery Charger Support + 0x0 + + + ENABLED + Battery Charger Support present + 0x1 + + + + + LPMMODE + LPM mode specified for Mode of Operation. + 15 + 15 + read-only + + + DISABLED + LPM disabled + 0x0 + + + ENABLED + LPM enabled + 0x1 + + + + + DFIFODEPTH + DFIFO Depth (DfifoDepth - EP_LOC_CNT) + 16 + 31 + read-only + + + + + GHWCFG4 + User Hardware Configuration 4 Register + 0x050 + read-write + 0x1E10AA60 + 0x20 + + + NUMDEVPERIOEPS + Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) + 0 + 3 + read-only + + + Value0 + Number of Periodic IN EPs is 0 + 0x0 + + + Value1 + Number of Periodic IN EPs is 1 + 0x1 + + + Value2 + Number of Periodic IN EPs is 2 + 0x2 + + + Value3 + Number of Periodic IN EPs is 3 + 0x3 + + + Value4 + Number of Periodic IN EPs is 4 + 0x4 + + + Value5 + Number of Periodic IN EPs is 5 + 0x5 + + + Value6 + Number of Periodic IN EPs is 6 + 0x6 + + + Value7 + Number of Periodic IN EPs is 7 + 0x7 + + + Value8 + Number of Periodic IN EPs is 8 + 0x8 + + + Value9 + Number of Periodic IN EPs is 9 + 0x9 + + + Value10 + Number of Periodic IN EPs is 10 + 0xA + + + Value11 + Number of Periodic IN EPs is 11 + 0xB + + + Value12 + Number of Periodic IN EPs is 12 + 0xC + + + Value13 + Number of Periodic IN EPs is 13 + 0xD + + + Value14 + Number of Periodic IN EPs is 14 + 0xE + + + Value15 + Number of Periodic IN EPs is 15 + 0xF + + + + + PARTIALPWRDN + Enable Partial Power Down (PartialPwrDn) + 4 + 4 + read-only + + + DISABLED + Partial Power Down disabled + 0x0 + + + ENABLED + Partial Power Down enabled + 0x1 + + + + + AHBFREQ + Minimum AHB Frequency Less Than 60 MHz (AhbFreq) + 5 + 5 + read-only + + + DISABLED + Minimum AHB Frequency More Than 60 MHz + 0x0 + + + ENABLED + Minimum AHB Frequency Less Than 60 MHz + 0x1 + + + + + HIBERNATION + Enable Hibernation (Hibernation) + 6 + 6 + read-only + + + DISABLED + Hibernation feature disabled + 0x0 + + + ENABLED + Hibernation feature enabled + 0x1 + + + + + EXTENDEDHIBERNATION + Enable Hibernation + 7 + 7 + read-only + + + DISABLED + Extended Hibernation feature not enabled + 0x0 + + + ENABLED + Extended Hibernation feature enabled + 0x1 + + + + + ENHANCEDLPMSUPT1 + Enhanced LPM Support1 (EnhancedLPMSupt1) + 9 + 9 + read-only + + + DISABLED + Reject L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty. + 0x0 + + + ENABLED + Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO is not empty + 0x1 + + + + + SERVINTFLOW + Service Interval Flow + 10 + 10 + read-only + + + DISABLED + Service Interval Flow not supported + 0x0 + + + ENABLED + Service Interval Flow supported + 0x1 + + + + + IPGISOCSUPT + Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) + 11 + 11 + read-only + + + DISABLED + Interpacket Gap ISOC OUT Worst-case Support is Disabled + 0x0 + + + ENABLED + Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) + 0x1 + + + + + ACGSUPT + Active Clock Gating Support + 12 + 12 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Active Clock Gating Support + 0x1 + + + + + ENHANCEDLPMSUPT + Enhanced LPM Support (EnhancedLPMSupt) + 13 + 13 + read-only + + + ENABLED + Enhanced LPM Support is enabled + 0x1 + + + + + PHYDATAWIDTH + UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width + 14 + 15 + read-only + + + WIDTH1 + 8 bits + 0x0 + + + WIDTH2 + 16 bits + 0x1 + + + WIDTH3 + 8/16 bits, software selectable + 0x2 + + + + + NUMCTLEPS + Number of Device Mode Control Endpoints in Addition to + 16 + 19 + read-only + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + IDDGFLTR + IDDIG Filter Enable (IddgFltr) + 20 + 20 + read-only + + + DISABLED + Iddig Filter Disabled + 0x0 + + + ENABLED + Iddig Filter Enabled + 0x1 + + + + + VBUSVALIDFLTR + VBUS Valid Filter Enabled (VBusValidFltr) + 21 + 21 + read-only + + + DISABLED + Vbus Valid Filter Disabled + 0x0 + + + ENABLED + Vbus Valid Filter Enabled + 0x1 + + + + + AVALIDFLTR + a_valid Filter Enabled (AValidFltr) + 22 + 22 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + BVALIDFLTR + b_valid Filter Enabled (BValidFltr) + 23 + 23 + read-only + + + DISABLED + No Filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + SESSENDFLTR + session_end Filter Enabled (SessEndFltr) + 24 + 24 + read-only + + + DISABLED + No filter + 0x0 + + + ENABLED + Filter + 0x1 + + + + + DEDFIFOMODE + Enable Dedicated Transmit FIFO for device IN Endpoints + 25 + 25 + read-only + + + DISABLED + Dedicated Transmit FIFO Operation not enabled + 0x0 + + + ENABLED + Dedicated Transmit FIFO Operation enabled + 0x1 + + + + + INEPS + Number of Device Mode IN Endpoints Including Control Endpoints (INEps) + 26 + 29 + read-only + + + ENDPT1 + 1 IN Endpoint + 0x0 + + + ENDPT2 + 2 IN Endpoints + 0x1 + + + ENDPT3 + 3 IN Endpoints + 0x2 + + + ENDPT4 + 4 IN Endpoints + 0x3 + + + ENDPT5 + 5 IN Endpoints + 0x4 + + + ENDPT6 + 6 IN Endpoints + 0x5 + + + ENDPT7 + 7 IN Endpoints + 0x6 + + + ENDPT8 + 8 IN Endpoints + 0x7 + + + ENDPT9 + 9 IN Endpoints + 0x8 + + + ENDPT10 + 10 IN Endpoints + 0x9 + + + ENDPT11 + 11 IN Endpoints + 0xA + + + ENDPT12 + 12 IN Endpoints + 0xB + + + ENDPT13 + 13 IN Endpoints + 0xC + + + ENDPT14 + 14 IN Endpoints + 0xD + + + ENDPT15 + 15 IN Endpoints + 0xE + + + ENDPT16 + 16 IN Endpoints + 0xF + + + + + DESCDMAENABLED + Scatter/Gather DMA configuration + 30 + 30 + read-only + + + DISABLE + Non-Scatter/Gather DMA configuration + 0x0 + + + ENABLE + Scatter/Gather DMA configuration + 0x1 + + + + + DESCDMA + Scatter/Gather DMA configuration + 31 + 31 + read-only + + + CONFIG1 + Non Dynamic configuration + 0x0 + + + CONFIG2 + Dynamic configuration + 0x1 + + + + + + + GLPMCFG + LPM Config Register + 0x054 + read-write + 0x00000000 + 0x20 + + + LPMCAP + LPM-Capable (LPMCap) + 0 + 0 + + + DISABLED + LPM capability is not enabled + 0x0 + + + ENABLED + LPM capability is enabled + 0x1 + + + + + APPL1RES + Mode: Device only. LPM response programmed by application (AppL1Res) + 1 + 1 + + + NYET_RESP + The core responds with a NYET when an error is detected in either of the LPM token packets due to corruption + 0x0 + + + ACK_RESP + The core responds with an ACK only on a successful LPM transaction + 0x1 + + + + + HIRD + Host-Initiated Resume Duration (HIRD) + 2 + 5 + + + BREMOTEWAKE + RemoteWakeEnable (bRemoteWake) + 6 + 6 + + + DISABLED + Remote Wakeup is disabled + 0x0 + + + ENABLED + In Host or device mode, this field takes the value of remote wake up + 0x1 + + + + + ENBLSLPM + Enable utmi_sleep_n (EnblSlpM) + 7 + 7 + + + DISABLED + utmi_sleep_n assertion from the core is not transferred to the external PHY + 0x0 + + + ENABLED + utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted + 0x1 + + + + + HIRDTHRES + BESL/HIRD Threshold (HIRD_Thres) + 8 + 12 + + + COREL1RES + LPM Response (CoreL1Res) + 13 + 14 + read-only + + + LPMRESP1 + ERROR : No handshake response + 0x0 + + + LPMRESP2 + STALL response + 0x1 + + + LPMRESP3 + NYET response + 0x2 + + + LPMRESP4 + ACK response + 0x3 + + + + + SLPSTS + Port Sleep Status (SlpSts) + 15 + 15 + read-only + + + CORE_NOT_IN_L1 + In Host or Device mode, this bit indicates core is not in L1 + 0x0 + + + CORE_IN_L1 + In Host mode, this bit indicates the core transitions to Sleep state as a successful LPM transaction. In Device mode, the core enters the Sleep state when an ACK response is sent to an LPM transaction + 0x1 + + + + + L1RESUMEOK + Sleep State Resume OK (L1ResumeOK) + 16 + 16 + read-only + + + NOTOK + The application/core cannot start Resume from Sleep state + 0x0 + + + OK + The application/core can start Resume from Sleep state + 0x1 + + + + + LPMCHNLINDX + LPM Channel Index + 17 + 20 + + + CH0 + Channel 0 + 0x0 + + + CH1 + Channel 1 + 0x1 + + + CH2 + Channel 2 + 0x2 + + + CH3 + Channel 3 + 0x3 + + + CH4 + Channel 4 + 0x4 + + + CH5 + Channel 5 + 0x5 + + + CH6 + Channel 6 + 0x6 + + + CH7 + Channel 7 + 0x7 + + + CH8 + Channel 8 + 0x8 + + + CH9 + Channel 9 + 0x9 + + + CH10 + Channel 10 + 0xA + + + CH11 + Channel 11 + 0xB + + + CH12 + Channel 12 + 0xC + + + CH13 + Channel 13 + 0xD + + + CH14 + Channel 14 + 0xE + + + CH15 + Channel15 + 0xF + + + + + LPMRETRYCNT + LPM Retry Count (LPM_Retry_Cnt) + 21 + 23 + + + RETRY0 + Zero LPM retries + 0x0 + + + RETRY1 + One LPM retry + 0x1 + + + RETRY2 + Two LPM retries + 0x2 + + + RETRY3 + Three LPM retries + 0x3 + + + RETRY4 + Four LPM retries + 0x4 + + + RETRY5 + Five LPM retries + 0x5 + + + RETRY6 + Six LPM retries + 0x6 + + + RETRY7 + Seven LPM retries + 0x7 + + + + + SNDLPM + Send LPM Transaction (SndLPM) + 24 + 24 + + + DISABLED + In host-only mode: Received the response from the device for the LPM transaction + 0x0 + + + ENABLED + In host-only mode: Sending LPM transaction containing EXT and LPM tokens + 0x1 + + + + + LPMRETRYCNTSTS + LPM Retry Count Status (LPM_RetryCnt_Sts) + 25 + 27 + read-only + + + RETRY_REM0 + Zero LPM retries remaining + 0x0 + + + RETRY_REM1 + One LPM retry remaining + 0x1 + + + RETRY_REM2 + Two LPM retries remaining + 0x2 + + + RETRY_REM3 + Three LPM retries remaining + 0x3 + + + RETRY_REM4 + Four LPM retries remaining + 0x4 + + + RETRY_REM5 + Five LPM retries remaining + 0x5 + + + RETRY_REM6 + Six LPM retries remaining + 0x6 + + + RETRY_REM7 + Seven LPM retries remaining + 0x7 + + + + + LPMENBESL + LPM Enable BESL (LPM_EnBESL) + 28 + 28 + + + DISABLED + BESL is disabled + 0x0 + + + ENABLED + BESL is enabled as defined in LPM Errata + 0x1 + + + + + LPMRESTORESLPSTS + LPM Restore Sleep Status (LPM_RestoreSlpSts) + 29 + 29 + + + DISABLED + Puts the core in Shallow Sleep mode based on the BESL value from the Host + 0x0 + + + ENABLED + Puts the core in Deep Sleep mode based on the BESL value from the Host + 0x1 + + + + + + + GPWRDN + Global Power Down Register + 0x058 + read-write + 0x00000010 + 0x20 + + + PMUINTSEL + PMU Interrupt Select (PMUIntSel) + 0 + 0 + + + DISABLE + Internal DWC_otg_core interrupt is selected + 0x0 + + + ENABLE + External DWC_otg_pmu interrupt is selected + 0x1 + + + + + PMUACTV + PMU Active (PMUActv) + 1 + 1 + + + DISABLE + Disable PMU module + 0x0 + + + ENABLE + Enable PMU module + 0x1 + + + + + RESTORE + Restore + 2 + 2 + + + DISABLE + The controller in normal mode of operation + 0x0 + + + ENABLE + The controller in Restore mode + 0x1 + + + + + PWRDNCLMP + Power Down Clamp (PwrDnClmp) + 3 + 3 + + + DISABLE + Disable PMU power clamp + 0x0 + + + ENABLE + Enable PMU power clamp + 0x1 + + + + + PWRDNRSTN + Power Down ResetN (PwrDnRst_n) + 4 + 4 + + + DISABLE + Reset the controller + 0x0 + + + ENABLE + The controller is in normal operation + 0x1 + + + + + PWRDNSWTCH + Power Down Switch (PwrDnSwtch) + 5 + 5 + + + ON + The controller is in ON state + 0x0 + + + OFF + The controller is in OFF state + 0x1 + + + + + DISABLEVBUS + DisableVBUS + 6 + 6 + + + DISABLED + Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device mode:Session Valid + 0x0 + + + ENABLED + Host mode:HPRT0.PrtPwr was programmed to 0 and in Device mode:Session End + 0x1 + + + + + LNSTSCHNG + Line State Change (LnStsChng) + 7 + 7 + + + DISABLED + No LineState change on USB + 0x0 + + + ENABLED + LineState change on USB + 0x1 + + + + + LINESTAGECHANGEMSK + LineStageChangeMsk + 8 + 8 + + + NOMASK + No LineStateChange Interrupt Mask + 0x0 + + + MASK + Mask for LineStateChange Interrupt + 0x1 + + + + + RESETDETECTED + ResetDetected + 9 + 9 + + + DISABLED + Reset not detected + 0x0 + + + ENABLED + Reset detected + 0x1 + + + + + RESETDETMSK + ResetDetMsk + 10 + 10 + + + NOMASK + No ResetDetect Interrupt Mask + 0x0 + + + MASK + Mask for ResetDetect Interrupt + 0x1 + + + + + DISCONNECTDETECT + DisconnectDetect + 11 + 11 + + + DISABLED + Disconnect not detected + 0x0 + + + ENABLED + Disconnect detected + 0x1 + + + + + DISCONNECTDETECTMSK + DisconnectDetectMsk + 12 + 12 + + + NOMASK + No DisconnectDetect Interrupt Mask + 0x0 + + + MASK + Mask for DisconnectDetect Interrupt + 0x1 + + + + + CONNECTDET + ConnectDet + 13 + 13 + + + DISABLED + Connect not detected + 0x0 + + + ENABLED + Connect detected + 0x1 + + + + + CONNDETMSK + ConnDetMsk + 14 + 14 + + + NOMASK + No ConnectDet Interrupt Mask + 0x0 + + + MASK + Mask for ConnectDet Interrupt + 0x1 + + + + + SRPDETECT + SRPDetect + 15 + 15 + + + DISABLED + SRP not detected + 0x0 + + + ENABLED + SRP detected + 0x1 + + + + + SRPDETECTMSK + SRPDetectMsk + 16 + 16 + + + NOMASK + No SRPDetect Interrupt Mask + 0x0 + + + MASK + Mask for SRPDetect Interrupt + 0x1 + + + + + STSCHNGINT + Status Change Interrupt (StsChngInt) + 17 + 17 + + + DISABLED + No Status change + 0x0 + + + ENABLED + Status change detected + 0x1 + + + + + STSCHNGINTMSK + StsChngIntMsk + 18 + 18 + + + NOMASK + No Status Change Interrupt Mask + 0x0 + + + MASK + Mask for Status Change Interrupt + 0x1 + + + + + LINESTATE + LineState + 19 + 20 + read-only + + + LS1 + Linestate on USB: DM = 0, DP = 0 + 0x0 + + + LS2 + Linestate on USB: DM = 0, DP = 1 + 0x1 + + + LS3 + Linestate on USB: DM = 1, DP = 0 + 0x2 + + + LS4 + Linestate on USB: Not-defined + 0x3 + + + + + IDDIG + This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application. + 21 + 21 + read-only + + + DISABLED + Host Mode + 0x0 + + + ENABLED + Device Mode + 0x1 + + + + + BSESSVLD + B Session Valid (BSessVld) + 22 + 22 + read-only + + + NOTVALID + B_Valid is 0 + 0x0 + + + VALID + B_Valid is 1 + 0x1 + + + + + MULTVALIDBC + MultValIdBC + 24 + 28 + read-only + + + RID_0 + OTG device as B-device + 0x00 + + + RID_C + OTG device as B-device, can connect + 0x01 + + + RID_B + OTG device as B-device, cannot connect + 0x02 + + + RID_A + OTG device as A-device + 0x04 + + + RID_GND + ID_OTG pin is grounded + 0x08 + + + RID_A_RID_GND + OTG device as A-device, RID_A=1 and RID_GND=1 + 0x0C + + + RID_FLOAT + ID pull down when ID_OTG is floating + 0x10 + + + RID_C_RID_FLOAT + OTG device as B-device, can connect, RID_C=1 and RID_FLOAT=1 + 0x11 + + + RID_B_RID_FLOAT + OTG device as B-device, cannot connect, RID_B=1 and RID_FLOAT=1 + 0x12 + + + RID_1 + OTG device as A-device + 0x1F + + + + + + + GDFIFOCFG + Global DFIFO Configuration Register + 0x05C + read-write + 0x0BEA0C00 + 0x20 + + + GDFIFOCFG + GDFIFOCfg + 0 + 15 + + + EPINFOBASEADDR + This field provides the start address of the EP info controller. + 16 + 31 + + + + + GINTMSK2 + Interrupt Mask Register 2 + 0x068 + read-write + 0x00000000 + 0x20 + + + GINTMSK2 + 0 + 31 + + + + + GINTSTS2 + Interrupt Register 2 + 0x06C + read-write + 0x00000000 + 0x20 + + + GINTSTS2 + 0 + 31 + + + + + HPTXFSIZ + Host Periodic Transmit FIFO Size Register + 0x100 + read-write + 0x04000424 + 0x20 + + + PTXFSTADDR + Host Periodic TxFIFO Start Address (PTxFStAddr) + 0 + 10 + + + PTXFSIZE + Host Periodic TxFIFO Depth (PTxFSize) + 16 + 26 + + + + + 0x7 + 0x4 + DIEPTXF[%s] + Description collection: Device IN Endpoint Transmit FIFO Size Register + 0x104 + read-write + 0x02000424 + 0x20 + + + INEPNTXFSTADDR + IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + 0 + 10 + + + INEPNTXFDEP + IN Endpoint TxFIFO Depth (INEPnTxFDep) + 16 + 25 + + + + + HCFG + Host Configuration Register + 0x400 + read-write + 0x00000200 + 0x20 + + + FSLSPCLKSEL + FS/LS PHY Clock Select (FSLSPclkSel) + 0 + 1 + + + CLK3060 + PHY clock is running at 30/60 MHz + 0x0 + + + CLK48 + PHY clock is running at 48 MHz + 0x1 + + + CLK6 + PHY clock is running at 6 MHz + 0x2 + + + + + FSLSSUPP + FS- and LS-Only Support (FSLSSupp) + 2 + 2 + + + HSFSLS + HS/FS/LS, based on the maximum speed supported by the connected device + 0x0 + + + FSLS + FS/LS-only, even if the connected device can support HS + 0x1 + + + + + ENA32KHZS + Enable 32 KHz Suspend mode (Ena32KHzS) + 7 + 7 + + + DISABLED + 32 KHz Suspend mode disabled + 0x0 + + + ENABLED + 32 KHz Suspend mode enabled + 0x1 + + + + + RESVALID + Resume Validation Period (ResValid) + 8 + 15 + + + MODECHTIMEN + Mode Change Ready Timer Enable (ModeChTimEn) + 31 + 31 + + + ENABLED + The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x0 + + + DISABLED + The Host core waits only for a linestate of SE0 at the end of resume to change the opmode from 0x2 to 0x0 + 0x1 + + + + + + + HFIR + Host Frame Interval Register + 0x404 + read-write + 0x0000EA60 + 0x20 + + + FRINT + Frame Interval (FrInt) + 0 + 15 + + + HFIRRLDCTRL + Reload Control (HFIRRldCtrl) + 16 + 16 + + + DISABLED + The HFIR cannot be reloaded dynamically + 0x0 + + + ENABLED + The HFIR can be dynamically reloaded during runtime + 0x1 + + + + + + + HFNUM + Host Frame Number/Frame Time Remaining Register + 0x408 + read-write + 0x00003FFF + 0x20 + + + FRNUM + Frame Number (FrNum) + 0 + 15 + read-only + + + INACTIVE + No SOF is transmitted + 0x0000 + + + ACTIVE + SOF is transmitted + 0x0001 + + + + + FRREM + Frame Time Remaining (FrRem) + 16 + 31 + read-only + + + + + HAINT + Host All Channels Interrupt Register + 0x414 + read-write + 0x00000000 + 0x20 + + + HAINT + 0 + 15 + read-only + + + INACTIVE + Not active + 0x0000 + + + ACTIVE + Host Channel Interrupt + 0x0001 + + + + + + + HAINTMSK + Host All Channels Interrupt Mask Register + 0x418 + read-write + 0x00000000 + 0x20 + + + HAINTMSK + Channel Interrupt Mask (HAINTMsk) + 0 + 15 + + + UNMASK + Unmask Channel interrupt + 0x0000 + + + MASK + Mask Channel interrupt + 0x0001 + + + + + + + HPRT + Host Port Control and Status Register + 0x440 + read-write + 0x00000000 + 0x20 + + + PRTCONNSTS + Port Connect Status (PrtConnSts) + 0 + 0 + read-only + + + NOTATTACHED + No device is attached to the port + 0x0 + + + ATTACHED + A device is attached to the port + 0x1 + + + + + PRTCONNDET + Port Connect Detected (PrtConnDet) + 1 + 1 + + + INACTIVE + No device connection detected + 0x0 + + + ACTIVE + Device connection detected + 0x1 + + + + + PRTENA + Port Enable (PrtEna) + 2 + 2 + + + DISABLED + Port disabled + 0x0 + + + ENABLED + Port enabled + 0x1 + + + + + PRTENCHNG + Port Enable/Disable Change (PrtEnChng) + 3 + 3 + + + INACTIVE + Port Enable bit 2 has not changed + 0x0 + + + ACTIVE + Port Enable bit 2 changed + 0x1 + + + + + PRTOVRCURRACT + Port Overcurrent Active (PrtOvrCurrAct) + 4 + 4 + read-only + + + INACTIVE + No overcurrent condition + 0x0 + + + ACTIVE + Overcurrent condition + 0x1 + + + + + PRTOVRCURRCHNG + Port Overcurrent Change (PrtOvrCurrChng) + 5 + 5 + + + INACTIVE + Status of port overcurrent status is not changed + 0x0 + + + ACTIVE + Status of port overcurrent changed + 0x1 + + + + + PRTRES + Port Resume (PrtRes) + 6 + 6 + + + NORESUME + No resume driven + 0x0 + + + RESUME + Resume driven + 0x1 + + + + + PRTSUSP + Port Suspend (PrtSusp) + 7 + 7 + + + INACTIVE + Port not in Suspend mode + 0x0 + + + ACTIVE + Port in Suspend mode + 0x1 + + + + + PRTRST + Port Reset (PrtRst) + 8 + 8 + + + DISABLED + Port not in reset + 0x0 + + + ENABLED + Port in reset + 0x1 + + + + + PRTLNSTS + Port Line Status (PrtLnSts) + 10 + 11 + read-only + + + PLUSD + Logic level of D+ + 0x1 + + + MINUSD + Logic level of D- + 0x2 + + + + + PRTPWR + Port Power (PrtPwr) + 12 + 12 + + + OFF + Power off + 0x0 + + + ON + Power on + 0x1 + + + + + PRTTSTCTL + Port Test Control (PrtTstCtl) + 13 + 16 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFENB + Test_force_Enable + 0x5 + + + + + PRTSPD + Port Speed (PrtSpd) + 17 + 18 + read-only + + + HIGHSPD + High speed + 0x0 + + + FULLSPD + Full speed + 0x1 + + + LOWSPD + Low speed + 0x2 + + + + + + + 16 + 0x018 + HC[%s] + Unspecified + USBHSCORE_HC + read-write + 0x500 + + CHAR + Description cluster: Host Channel Characteristics Register + 0x000 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + EPNUM + Endpoint Number (EPNum) + 11 + 14 + + + ENDPT0 + End point 0 + 0x0 + + + ENDPT1 + End point 1 + 0x1 + + + ENDPT2 + End point 2 + 0x2 + + + ENDPT3 + End point 3 + 0x3 + + + ENDPT4 + End point 4 + 0x4 + + + ENDPT5 + End point 5 + 0x5 + + + ENDPT6 + End point 6 + 0x6 + + + ENDPT7 + End point 7 + 0x7 + + + ENDPT8 + End point 8 + 0x8 + + + ENDPT9 + End point 9 + 0x9 + + + ENDPT10 + End point 10 + 0xA + + + ENDPT11 + End point 11 + 0xB + + + ENDPT12 + End point 12 + 0xC + + + ENDPT13 + End point 13 + 0xD + + + ENDPT14 + End point 14 + 0xE + + + ENDPT15 + End point 15 + 0xF + + + + + EPDIR + Endpoint Direction (EPDir) + 15 + 15 + + + OUT + OUT Direction + 0x0 + + + IN + IN Direction + 0x1 + + + + + LSPDDEV + Low-Speed Device (LSpdDev) + 17 + 17 + + + DISABLED + Not Communicating with low speed device + 0x0 + + + ENABLED + Communicating with low speed device + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CTRL + Control + 0x0 + + + ISOC + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERR + Interrupt + 0x3 + + + + + EC + Multi Count (MC) / Error Count (EC) + 20 + 21 + + + TRANSONE + 1 transaction + 0x1 + + + TRANSTWO + 2 transactions to be issued for this endpoint per microframe + 0x2 + + + TRANSTHREE + 3 transactions to be issued for this endpoint per microframe + 0x3 + + + + + DEVADDR + Device Address (DevAddr) + 22 + 28 + + + ODDFRM + Odd Frame (OddFrm) + 29 + 29 + + + EFRAME + Even Frame Transfer + 0x0 + + + OFRAME + Odd Frame Transfer + 0x1 + + + + + CHDIS + Channel Disable (ChDis) + 30 + 30 + + + INACTIVE + Transmit/Recieve normal + 0x0 + + + ACTIVE + Stop transmitting/receiving data on channel + 0x1 + + + + + CHENA + Channel Enable (ChEna) + 31 + 31 + + + DISABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure is not yet ready. If Scatter/Gather mode is disabled, indicates that the channel is disabled. + 0x0 + + + ENABLED + If Scatter/Gather mode is enabled, indicates that the descriptor structure and data buffer with data is set up and this channel can access the descriptor. If Scatter/Gather mode is disabled, indicates that the channel is enabled. + 0x1 + + + + + + + INT + Description cluster: Host Channel Interrupt Register + 0x008 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed (XferCompl) + 0 + 0 + + + INACTIVE + Transfer in progress or No Active Transfer + 0x0 + + + ACTIVE + Transfer completed normally without any errors + 0x1 + + + + + CHHLTD + Channel Halted (ChHltd) + 1 + 1 + + + INACTIVE + Channel not halted + 0x0 + + + ACTIVE + Channel Halted + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB error + 0x0 + + + ACTIVE + AHB error during AHB read/write + 0x1 + + + + + STALL + STALL Response Received Interrupt (STALL) + 3 + 3 + + + INACTIVE + No Stall Response Received Interrupt + 0x0 + + + ACTIVE + Stall Response Received Interrupt + 0x1 + + + + + NAK + NAK Response Received Interrupt (NAK) + 4 + 4 + + + INACTIVE + No NAK Response Received Interrupt + 0x0 + + + ACTIVE + NAK Response Received Interrupt + 0x1 + + + + + ACK + ACK Response Received/Transmitted Interrupt (ACK) + 5 + 5 + + + INACTIVE + No ACK Response Received or Transmitted Interrupt + 0x0 + + + ACTIVE + ACK Response Received or Transmitted Interrup + 0x1 + + + + + NYET + NYET Response Received Interrupt (NYET) + 6 + 6 + + + INACTIVE + No NYET Response Received Interrupt + 0x0 + + + ACTIVE + NYET Response Received Interrupt + 0x1 + + + + + XACTERR + Transaction Error (XactErr) + 7 + 7 + + + INACTIVE + No Transaction Error + 0x0 + + + ACTIVE + Transaction Error + 0x1 + + + + + BBLERR + Babble Error (BblErr) + 8 + 8 + + + INACTIVE + No Babble Error + 0x0 + + + ACTIVE + Babble Error + 0x1 + + + + + FRMOVRUN + Frame Overrun (FrmOvrun). + 9 + 9 + + + INACTIVE + No Frame Overrun + 0x0 + + + ACTIVE + Frame Overrun + 0x1 + + + + + DATATGLERR + 10 + 10 + + + INACTIVE + No Data Toggle Error + 0x0 + + + ACTIVE + Data Toggle Error + 0x1 + + + + + + + INTMSK + Description cluster: Host Channel Interrupt Mask Register + 0x00C + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + 0 + 0 + + + MASK + Transfer Completed Mask + 0x0 + + + NOMASK + No Transfer Completed Mask + 0x1 + + + + + CHHLTDMSK + 1 + 1 + + + MASK + Channel Halted Mask + 0x0 + + + NOMASK + No Channel Halted Mask + 0x1 + + + + + AHBERRMSK + 2 + 2 + + + MASK + AHB Error Mask + 0x0 + + + NOMASK + No AHB Error Mask + 0x1 + + + + + STALLMSK + 3 + 3 + + + MASK + Mask STALL Response Received Interrupt + 0x0 + + + NOMASK + No STALL Response Received Interrupt Mask + 0x1 + + + + + NAKMSK + 4 + 4 + + + MASK + Mask NAK Response Received Interrupt + 0x0 + + + NOMASK + No NAK Response Received Interrupt Mask + 0x1 + + + + + ACKMSK + 5 + 5 + + + MASK + Mask ACK Response Received/Transmitted Interrupt + 0x0 + + + NOMASK + No ACK Response Received/Transmitted Interrupt Mask + 0x1 + + + + + NYETMSK + 6 + 6 + + + MASK + Mask NYET Response Received Interrupt + 0x0 + + + NOMASK + No NYET Response Received Interrupt Mask + 0x1 + + + + + XACTERRMSK + 7 + 7 + + + MASK + Mask Transaction Error + 0x0 + + + NOMASK + No Transaction Error Mask + 0x1 + + + + + BBLERRMSK + 8 + 8 + + + MASK + Mask Babble Error + 0x0 + + + NOMASK + No Babble Error Mask + 0x1 + + + + + FRMOVRUNMSK + 9 + 9 + + + MASK + Mask Overrun Mask + 0x0 + + + NOMASK + No Frame Overrun Mask + 0x1 + + + + + DATATGLERRMSK + 10 + 10 + + + MASK + Mask Data Toggle Error + 0x0 + + + NOMASK + No Data Toggle Error Mask + 0x1 + + + + + + + TSIZ + Description cluster: Host Channel Transfer Size Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Non-Scatter/Gather DMA Mode: + 0 + 18 + + + PKTCNT + Non-Scatter/Gather DMA Mode: + 19 + 28 + + + PID + PID (Pid) + 29 + 30 + + + DATA0 + DATA0 + 0x0 + + + DATA2 + DATA2 + 0x1 + + + DATA1 + DATA1 + 0x2 + + + MDATA + MDATA (non-control)/SETUP (control) + 0x3 + + + + + DOPNG + Do Ping (DoPng) + 31 + 31 + + + NOPING + No ping protocol + 0x0 + + + PING + Ping protocol + 0x1 + + + + + + + DMA + Description cluster: Host Channel DMA Address Register + 0x014 + read-write + 0x00000000 + 0x20 + + + DMAADDR + In Buffer DMA Mode: + 0 + 31 + + + + + + DCFG + Device Configuration Register + 0x800 + read-write + 0x08020000 + 0x20 + + + DEVSPD + Device Speed (DevSpd) + 0 + 1 + + + USBHS20 + High speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x0 + + + USBFS20 + Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz + 0x1 + + + USBLS116 + Low speed USB 1.1 transceiver clock is 6 MHz + 0x2 + + + USBFS1148 + Full speed USB 1.1 transceiver clock is 48 MHz + 0x3 + + + + + NZSTSOUTHSHK + Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + 2 + 2 + + + SENDOUT + Send the received OUT packet to the application (zero-length or non-zero length) and send a handshake based on NAK and STALL bits for the endpoint in the Devce Endpoint Control Register + 0x0 + + + SENDSTALL + Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application + 0x1 + + + + + ENA32KHZSUSP + Enable 32 KHz Suspend mode (Ena32KHzSusp) + 3 + 3 + + + DISABLED + USB 1.1 Full-Speed Serial Transceiver not selected + 0x0 + + + ENABLED + USB 1.1 Full-Speed Serial Transceiver Interface selected + 0x1 + + + + + DEVADDR + Device Address (DevAddr) + 4 + 10 + + + PERFRINT + Periodic Frame Interval (PerFrInt) + 11 + 12 + + + EOPF80 + 80 percent of the (micro)Frame interval + 0x0 + + + EOPF85 + 85 percent of the (micro)Frame interval + 0x1 + + + EOPF90 + 90 percent of the (micro)Frame interval + 0x2 + + + EOPF95 + 95 percent of the (micro)Frame interval + 0x3 + + + + + XCVRDLY + XCVRDLY + 14 + 14 + + + DISABLE + No delay between xcvr_sel and txvalid during Device chirp + 0x0 + + + ENABLE + Enable delay between xcvr_sel and txvalid during Device chirp + 0x1 + + + + + ERRATICINTMSK + Erratic Error Interrupt Mask + 15 + 15 + + + NOMASK + Early suspend interrupt is generated on erratic error + 0x0 + + + MASK + Mask early suspend interrupt on erratic error + 0x1 + + + + + IPGISOCSUPT + Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) + 17 + 17 + + + DISABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is disabled + 0x0 + + + ENABLED + Worst-Case Inter-Packet Gap ISOC OUT Support is enabled + 0x1 + + + + + PERSCHINTVL + Periodic Scheduling Interval (PerSchIntvl) + 24 + 25 + + + MF25 + 25 percent of (micro)Frame + 0x0 + + + MF50 + 50 percent of (micro)Frame + 0x1 + + + MF75 + 75 percent of (micro)Frame + 0x2 + + + + + RESVALID + Resume Validation Period (ResValid) + 26 + 31 + + + + + DCTL + Device Control Register + 0x804 + read-write + 0x00000002 + 0x20 + + + RMTWKUPSIG + Remote Wakeup Signaling (RmtWkUpSig) + 0 + 0 + + + DISABLEDRMWKUP + Core does not send Remote Wakeup Signaling + 0x0 + + + ENABLERMWKUP + Core sends Remote Wakeup Signaling + 0x1 + + + + + SFTDISCON + Soft Disconnect (SftDiscon) + 1 + 1 + + + NODISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + 0x0 + + + DISCONNECT + The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host + 0x1 + + + + + GNPINNAKSTS + Global Non-periodic IN NAK Status (GNPINNakSts) + 2 + 2 + read-only + + + INACTIVE + A handshake is sent out based on the data availability in the transmit FIFO + 0x0 + + + ACTIVE + A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + 0x1 + + + + + GOUTNAKSTS + Global OUT NAK Status (GOUTNakSts) + 3 + 3 + read-only + + + INACTIVE + A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + 0x0 + + + ACTIVE + No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. + 0x1 + + + + + TSTCTL + Test Control (TstCtl) + 4 + 6 + + + DISABLED + Test mode disabled + 0x0 + + + TESTJ + Test_J mode + 0x1 + + + TESTK + Test_K mode + 0x2 + + + TESTSN + Test_SE0_NAK mode + 0x3 + + + TESTPM + Test_Packet mode + 0x4 + + + TESTFE + Test_force_Enable + 0x5 + + + + + SGNPINNAK + Set Global Non-periodic IN NAK (SGNPInNak) + 7 + 7 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Set Global Non-periodic IN NAK + 0x1 + + + + + CGNPINNAK + Clear Global Non-periodic IN NAK (CGNPInNak) + 8 + 8 + write-only + + + DISABLE + Disable Global Non-periodic IN NAK + 0x0 + + + ENABLE + Clear Global Non-periodic IN NAK + 0x1 + + + + + SGOUTNAK + Set Global OUT NAK (SGOUTNak) + 9 + 9 + write-only + + + DISABLED + Disable Global OUT NAK + 0x0 + + + ENABLED + Set Global OUT NAK + 0x1 + + + + + CGOUTNAK + Clear Global OUT NAK (CGOUTNak) + 10 + 10 + write-only + + + DISABLED + Disable Clear Global OUT NAK + 0x0 + + + ENABLED + Clear Global OUT NAK + 0x1 + + + + + PWRONPRGDONE + Power-On Programming Done (PWROnPrgDone) + 11 + 11 + + + NOTDONE + Power-On Programming not done + 0x0 + + + DONE + Power-On Programming Done + 0x1 + + + + + IGNRFRMNUM + Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + 15 + 15 + + + DISABLED + Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in which they are intended to be transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is disabled. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediately as the packets are ready.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is enabled. + 0x1 + + + + + NAKONBBLE + NAK on Babble Error (NakOnBble) + 16 + 16 + + + DISABLED + Disable NAK on Babble Error + 0x0 + + + ENABLED + NAK on Babble Error + 0x1 + + + + + DEEPSLEEPBESLREJECT + DeepSleepBESLReject + 18 + 18 + + + DISABLED + Deep Sleep BESL Reject feature is disabled + 0x0 + + + ENABLED + Deep Sleep BESL Reject feature is enabled + 0x1 + + + + + SERVINT + Service Interval based scheduling for Isochronous IN Endpoints + 19 + 19 + + + DISABLED + The controller behavior depends on DCTL.IgnrFrmNum field. + 0x0 + + + ENABLED + Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the service interval. + 0x1 + + + + + UTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface. + 30 + 30 + + + DISABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller after TxValid goes LOW (1'b0)on soft disconnect. + 0x0 + + + ENABLED + Opmode, XcvrSel, TermSel are changed by the Device Controller immediately on soft disconnect. + 0x1 + + + + + UTMITERMSELCORRDIS + Disable the correction of TermSel on UTMI Interface. + 31 + 31 + + + DISABLED + Valid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x0 + + + ENABLED + Invalid Combination of XcvrSel and TermSel is driven by the Device Controller. + 0x1 + + + + + + + DSTS + Device Status Register + 0x808 + read-write + 0x00000002 + 0x20 + + + SUSPSTS + Suspend Status (SuspSts) + 0 + 0 + read-only + + + INACTIVE + No suspend state + 0x0 + + + ACTIVE + Suspend state + 0x1 + + + + + ENUMSPD + Enumerated Speed (EnumSpd) + 1 + 2 + read-only + + + HS3060 + High speed (PHY clock is running at 30 or 60 MHz) + 0x0 + + + FS3060 + Full speed (PHY clock is running at 30 or 60 MHz) + 0x1 + + + LS6 + Low speed (PHY clock is running at 6 MHz) + 0x2 + + + FS48 + Full speed (PHY clock is running at 48 MHz) + 0x3 + + + + + ERRTICERR + Erratic Error (ErrticErr) + 3 + 3 + read-only + + + INACTIVE + No Erratic Error + 0x0 + + + ACTIVE + Erratic Error + 0x1 + + + + + SOFFN + Frame or Microframe Number of the Received SOF (SOFFN) + 8 + 21 + read-only + + + DEVLNSTS + Device Line Status (DevLnSts) + 22 + 23 + read-only + + + + + DIEPMSK + Device IN Endpoint Common Interrupt Mask Register + 0x810 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error Mask (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + TIMEOUTMSK + Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + 3 + 3 + + + MASK + Mask Timeout Condition Interrupt + 0x0 + + + NOMASK + No Timeout Condition Interrupt Mask + 0x1 + + + + + INTKNTXFEMPMSK + IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + 4 + 4 + + + MASK + Mask IN Token Received When TxFIFO Empty Interrupt + 0x0 + + + NOMASK + No IN Token Received When TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMISMSK + IN Token received with EP Mismatch Mask (INTknEPMisMsk) + 5 + 5 + + + MASK + Mask IN Token received with EP Mismatch Interrupt + 0x0 + + + NOMASK + No Mask IN Token received with EP Mismatch Interrupt + 0x1 + + + + + INEPNAKEFFMSK + IN Endpoint NAK Effective Mask (INEPNakEffMsk) + 6 + 6 + + + MASK + Mask IN Endpoint NAK Effective Interrupt + 0x0 + + + NOMASK + No IN Endpoint NAK Effective Interrupt Mask + 0x1 + + + + + TXFIFOUNDRNMSK + Fifo Underrun Mask (TxfifoUndrnMsk) + 8 + 8 + + + MASK + Mask Fifo Underrun Interrupt + 0x0 + + + NOMASK + No Fifo Underrun Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No Mask NAK Interrupt + 0x1 + + + + + + + DOEPMSK + Device OUT Endpoint Common Interrupt Mask Register + 0x814 + read-write + 0x00000000 + 0x20 + + + XFERCOMPLMSK + Transfer Completed Interrupt Mask (XferComplMsk) + 0 + 0 + + + MASK + Mask Transfer Completed Interrupt + 0x0 + + + NOMASK + No Transfer Completed Interrupt Mask + 0x1 + + + + + EPDISBLDMSK + Endpoint Disabled Interrupt Mask (EPDisbldMsk) + 1 + 1 + + + MASK + Mask Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No Endpoint Disabled Interrupt Mask + 0x1 + + + + + AHBERRMSK + AHB Error (AHBErrMsk) + 2 + 2 + + + MASK + Mask AHB Error Interrupt + 0x0 + + + NOMASK + No AHB Error Interrupt Mask + 0x1 + + + + + SETUPMSK + SETUP Phase Done Mask (SetUPMsk) + 3 + 3 + + + MASK + Mask SETUP Phase Done Interrupt + 0x0 + + + NOMASK + No SETUP Phase Done Interrupt Mask + 0x1 + + + + + OUTTKNEPDISMSK + OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + 4 + 4 + + + MASK + Mask OUT Token Received when Endpoint Disabled Interrupt + 0x0 + + + NOMASK + No OUT Token Received when Endpoint Disabled Interrupt Mask + 0x1 + + + + + STSPHSERCVDMSK + Status Phase Received Mask (StsPhseRcvdMsk) + 5 + 5 + + + MASK + Status Phase Received Mask + 0x0 + + + NOMASK + No Status Phase Received Mask + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + 6 + 6 + + + MASK + Mask Back-to-Back SETUP Packets Received Interrupt + 0x0 + + + NOMASK + No Back-to-Back SETUP Packets Received Interrupt Mask + 0x1 + + + + + OUTPKTERRMSK + OUT Packet Error Mask (OutPktErrMsk) + 8 + 8 + + + MASK + Mask OUT Packet Error Interrupt + 0x0 + + + NOMASK + No OUT Packet Error Interrupt Mask + 0x1 + + + + + BBLEERRMSK + Babble Error interrupt Mask (BbleErrMsk) + 12 + 12 + + + MASK + Mask Babble Error Interrupt + 0x0 + + + NOMASK + No Babble Error Interrupt Mask + 0x1 + + + + + NAKMSK + NAK interrupt Mask (NAKMsk) + 13 + 13 + + + MASK + Mask NAK Interrupt + 0x0 + + + NOMASK + No NAK Interrupt Mask + 0x1 + + + + + NYETMSK + NYET interrupt Mask (NYETMsk) + 14 + 14 + + + MASK + Mask NYET Interrupt + 0x0 + + + NOMASK + No NYET Interrupt Mask + 0x1 + + + + + + + DAINT + Device All Endpoints Interrupt Register + 0x818 + read-write + 0x00000000 + 0x20 + + + INEPINT0 + IN Endpoint 0 Interrupt Bit + 0 + 0 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for IN EP0 + 0x1 + + + + + INEPINT1 + IN Endpoint 1 Interrupt Bit + 1 + 1 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT2 + IN Endpoint 2 Interrupt Bit + 2 + 2 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT3 + IN Endpoint 3 Interrupt Bit + 3 + 3 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT4 + IN Endpoint 4 Interrupt Bit + 4 + 4 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT5 + IN Endpoint 5 Interrupt Bit + 5 + 5 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT6 + IN Endpoint 6 Interrupt Bit + 6 + 6 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT7 + IN Endpoint 7 Interrupt Bit + 7 + 7 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT8 + IN Endpoint 8 Interrupt Bit + 8 + 8 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT9 + IN Endpoint 9 Interrupt Bit + 9 + 9 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT10 + IN Endpoint 10 Interrupt Bit + 10 + 10 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + INEPINT11 + IN Endpoint 11 Interrupt Bit + 11 + 11 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the IN EP + 0x1 + + + + + OUTEPINT0 + OUT Endpoint 0 Interrupt Bit + 16 + 16 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for OUT EP0 + 0x1 + + + + + OUTEPINT1 + OUT Endpoint 1 Interrupt Bit + 17 + 17 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT2 + OUT Endpoint 2 Interrupt Bit + 18 + 18 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT3 + OUT Endpoint 3 Interrupt Bit + 19 + 19 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT4 + OUT Endpoint 4 Interrupt Bit + 20 + 20 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT5 + OUT Endpoint 5 Interrupt Bit + 21 + 21 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT12 + OUT Endpoint 12 Interrupt Bit + 28 + 28 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT13 + OUT Endpoint 13 Interrupt Bit + 29 + 29 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT14 + OUT Endpoint 14 Interrupt Bit + 30 + 30 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + OUTEPINT15 + OUT Endpoint 15 Interrupt Bit + 31 + 31 + read-only + + + INACTIVE + No Interrupt + 0x0 + + + ACTIVE + Interrupt is active for the OUT EP + 0x1 + + + + + + + DAINTMSK + Device All Endpoints Interrupt Mask Register + 0x81C + read-write + 0x00000000 + 0x20 + + + INEPMSK0 + IN Endpoint 0 Interrupt mask Bit + 0 + 0 + + + MASK + Mask IN Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK1 + IN Endpoint 1 Interrupt mask Bit + 1 + 1 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK2 + IN Endpoint 2 Interrupt mask Bit + 2 + 2 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK3 + IN Endpoint 3 Interrupt mask Bit + 3 + 3 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK4 + IN Endpoint 4 Interrupt mask Bit + 4 + 4 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK5 + IN Endpoint 5 Interrupt mask Bit + 5 + 5 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK6 + IN Endpoint 6 Interrupt mask Bit + 6 + 6 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK7 + IN Endpoint 7 Interrupt mask Bit + 7 + 7 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK8 + IN Endpoint 8 Interrupt mask Bit + 8 + 8 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK9 + IN Endpoint 9 Interrupt mask Bit + 9 + 9 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK10 + IN Endpoint 10 Interrupt mask Bit + 10 + 10 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + INEPMSK11 + IN Endpoint 11 Interrupt mask Bit + 11 + 11 + + + MASK + Mask IN Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK0 + OUT Endpoint 0 Interrupt mask Bit + 16 + 16 + + + MASK + Mask OUT Endpoint 0 Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK1 + OUT Endpoint 1 Interrupt mask Bit + 17 + 17 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK2 + OUT Endpoint 2 Interrupt mask Bit + 18 + 18 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK3 + OUT Endpoint 3 Interrupt mask Bit + 19 + 19 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK4 + OUT Endpoint 4 Interrupt mask Bit + 20 + 20 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK5 + OUT Endpoint 5 Interrupt mask Bit + 21 + 21 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK12 + OUT Endpoint 12 Interrupt mask Bit + 28 + 28 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK13 + OUT Endpoint 13 Interrupt mask Bit + 29 + 29 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK14 + OUT Endpoint 14 Interrupt mask Bit + 30 + 30 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + OUTEPMSK15 + OUT Endpoint 15 Interrupt mask Bit + 31 + 31 + + + MASK + Mask OUT Endpoint Interrupt + 0x0 + + + NOMASK + No Interrupt mask + 0x1 + + + + + + + DVBUSDIS + Device VBUS Discharge Time Register + 0x828 + read-write + 0x000017D7 + 0x20 + + + DVBUSDIS + Device VBUS Discharge Time (DVBUSDis) + 0 + 15 + + + + + DVBUSPULSE + Device VBUS Pulsing Time Register + 0x82C + read-write + 0x000005B8 + 0x20 + + + DVBUSPULSE + Device VBUS Pulsing Time (DVBUSPulse) + 0 + 11 + + + + + DTHRCTL + Device Threshold Control Register + 0x830 + read-write + 0x08100020 + 0x20 + + + NONISOTHREN + Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) + 0 + 0 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enable thresholding for non-isochronous IN endpoints + 0x1 + + + + + ISOTHREN + 1 + 1 + + + DISABLED + No thresholding + 0x0 + + + ENABLED + Enables thresholding for isochronous IN endpoints + 0x1 + + + + + TXTHRLEN + Transmit Threshold Length (TxThrLen) + 2 + 10 + + + AHBTHRRATIO + AHB Threshold Ratio (AHBThrRatio) + 11 + 12 + + + THRESZERO + AHB threshold = MAC threshold + 0x0 + + + THRESONE + AHB threshold = MAC threshold /2 + 0x1 + + + THRESTWO + AHB threshold = MAC threshold /4 + 0x2 + + + THRESTHREE + AHB threshold = MAC threshold /8 + 0x3 + + + + + RXTHREN + Receive Threshold Enable (RxThrEn) + 16 + 16 + + + DISABLED + Disable thresholding + 0x0 + + + ENABLED + Enable thresholding in the receive direction + 0x1 + + + + + RXTHRLEN + Receive Threshold Length (RxThrLen) + 17 + 25 + + + ARBPRKEN + Arbiter Parking Enable (ArbPrkEn) + 27 + 27 + + + DISABLED + Disable DMA arbiter parking + 0x0 + + + ENABLED + Enable DMA arbiter parking for IN endpoints + 0x1 + + + + + + + DIEPEMPMSK + Device IN Endpoint FIFO Empty Interrupt Mask Register + 0x834 + read-write + 0x00000000 + 0x20 + + + INEPTXFEMPMSK + IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + 0 + 15 + + + EP0_MASK + Mask IN EP0 Tx FIFO Empty Interrupt + 0x0001 + + + EP1_MASK + Mask IN EP1 Tx FIFO Empty Interrupt + 0x0002 + + + EP2_MASK + Mask IN EP2 Tx FIFO Empty Interrupt + 0x0004 + + + EP3_MASK + Mask IN EP3 Tx FIFO Empty Interrupt + 0x0008 + + + EP4_MASK + Mask IN EP4 Tx FIFO Empty Interrupt + 0x0010 + + + EP5_MASK + Mask IN EP5 Tx FIFO Empty Interrupt + 0x0020 + + + EP6_MASK + Mask IN EP6 Tx FIFO Empty Interrupt + 0x0040 + + + EP7_MASK + Mask IN EP7 Tx FIFO Empty Interrupt + 0x0080 + + + EP8_MASK + Mask IN EP8 Tx FIFO Empty Interrupt + 0x0100 + + + EP9_MASK + Mask IN EP9 Tx FIFO Empty Interrupt + 0x0200 + + + EP10_MASK + Mask IN EP10 Tx FIFO Empty Interrupt + 0x0400 + + + EP11_MASK + Mask IN EP11 Tx FIFO Empty Interrupt + 0x0800 + + + EP12_MASK + Mask IN EP12 Tx FIFO Empty Interrupt + 0x1000 + + + EP13_MASK + Mask IN EP13 Tx FIFO Empty Interrupt + 0x2000 + + + EP14_MASK + Mask IN EP14 Tx FIFO Empty Interrupt + 0x4000 + + + EP15_MASK + Mask IN EP15 Tx FIFO Empty Interrupt + 0x8000 + + + + + + + DIEPCTL0 + Device Control IN Endpoint 0 Control Register + 0x900 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + + + BYTES64 + 64 bytes + 0x0 + + + BYTES32 + 32 bytes + 0x1 + + + BYTES16 + 16 bytes + 0x2 + + + BYTES8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE0 + Control endpoint is always active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Disabled Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT0 + Device IN Endpoint 0 Interrupt Register + 0x908 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Completed Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received when TxFIFO Empty interrupt + 0x0 + + + ACTIVE + IN Token Received when TxFIFO Empty Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No IN Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Fifo Underrun interrupt + 0x0 + + + ACTIVE + Fifo Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ0 + Device IN Endpoint 0 Transfer Size Register + 0x910 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 20 + + + + + DIEPDMA0 + Device IN Endpoint 0 DMA Address Register + 0x914 + read-write + 0x00000000 + 0x20 + + + DMAADDR + DMAAddr + 0 + 31 + + + + + DTXFSTS0 + Device IN Endpoint Transmit FIFO Status Register 0 + 0x918 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL1 + Device Control IN Endpoint Control Register + 0x920 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT1 + Device IN Endpoint Interrupt Register + 0x928 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ1 + Device IN Endpoint Transfer Size Register + 0x930 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA1 + Device IN Endpoint DMA Address Register + 0x934 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS1 + Device IN Endpoint Transmit FIFO Status Register + 0x938 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL2 + Device Control IN Endpoint Control Register + 0x940 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT2 + Device IN Endpoint Interrupt Register + 0x948 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ2 + Device IN Endpoint Transfer Size Register + 0x950 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA2 + Device IN Endpoint DMA Address Register + 0x954 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS2 + Device IN Endpoint Transmit FIFO Status Register + 0x958 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL3 + Device Control IN Endpoint Control Register + 0x960 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT3 + Device IN Endpoint Interrupt Register + 0x968 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ3 + Device IN Endpoint Transfer Size Register + 0x970 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA3 + Device IN Endpoint DMA Address Register + 0x974 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS3 + Device IN Endpoint Transmit FIFO Status Register + 0x978 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL4 + Device Control IN Endpoint Control Register + 0x980 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT4 + Device IN Endpoint Interrupt Register + 0x988 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ4 + Device IN Endpoint Transfer Size Register + 0x990 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA4 + Device IN Endpoint DMA Address Register + 0x994 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS4 + Device IN Endpoint Transmit FIFO Status Register + 0x998 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL5 + Device Control IN Endpoint Control Register + 0x9A0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT5 + Device IN Endpoint Interrupt Register + 0x9A8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ5 + Device IN Endpoint Transfer Size Register + 0x9B0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA5 + Device IN Endpoint DMA Address Register + 0x9B4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS5 + Device IN Endpoint Transmit FIFO Status Register + 0x9B8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL6 + Device Control IN Endpoint Control Register + 0x9C0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT6 + Device IN Endpoint Interrupt Register + 0x9C8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ6 + Device IN Endpoint Transfer Size Register + 0x9D0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA6 + Device IN Endpoint DMA Address Register + 0x9D4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS6 + Device IN Endpoint Transmit FIFO Status Register + 0x9D8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL7 + Device Control IN Endpoint Control Register + 0x9E0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT7 + Device IN Endpoint Interrupt Register + 0x9E8 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ7 + Device IN Endpoint Transfer Size Register + 0x9F0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA7 + Device IN Endpoint DMA Address Register + 0x9F4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS7 + Device IN Endpoint Transmit FIFO Status Register + 0x9F8 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL8 + Device Control IN Endpoint Control Register + 0xA00 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT8 + Device IN Endpoint Interrupt Register + 0xA08 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ8 + Device IN Endpoint Transfer Size Register + 0xA10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA8 + Device IN Endpoint DMA Address Register + 0xA14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS8 + Device IN Endpoint Transmit FIFO Status Register + 0xA18 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL9 + Device Control IN Endpoint Control Register + 0xA20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT9 + Device IN Endpoint Interrupt Register + 0xA28 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ9 + Device IN Endpoint Transfer Size Register + 0xA30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA9 + Device IN Endpoint DMA Address Register + 0xA34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS9 + Device IN Endpoint Transmit FIFO Status Register + 0xA38 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL10 + Device Control IN Endpoint Control Register + 0xA40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT10 + Device IN Endpoint Interrupt Register + 0xA48 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ10 + Device IN Endpoint Transfer Size Register + 0xA50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA10 + Device IN Endpoint DMA Address Register + 0xA54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS10 + Device IN Endpoint Transmit FIFO Status Register + 0xA58 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DIEPCTL11 + Device Control IN Endpoint Control Register + 0xA60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + 16 + 16 + read-only + + + DATA0EVENFRM + DATA0 or Even Frame + 0x0 + + + DATA1ODDFRM + DATA1 or Odd Frame + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUP + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + TXFNUM + TxFIFO Number (TxFNum) + 22 + 25 + + + TXFIFO0 + Tx FIFO 0 + 0x0 + + + TXFIFO1 + Tx FIFO 1 + 0x1 + + + TXFIFO2 + Tx FIFO 2 + 0x2 + + + TXFIFO3 + Tx FIFO 3 + 0x3 + + + TXFIFO4 + Tx FIFO 4 + 0x4 + + + TXFIFO5 + Tx FIFO 5 + 0x5 + + + TXFIFO6 + Tx FIFO 6 + 0x6 + + + TXFIFO7 + Tx FIFO 7 + 0x7 + + + TXFIFO8 + Tx FIFO 8 + 0x8 + + + TXFIFO9 + Tx FIFO 9 + 0x9 + + + TXFIFO10 + Tx FIFO 10 + 0xA + + + TXFIFO11 + Tx FIFO 11 + 0xB + + + TXFIFO12 + Tx FIFO 12 + 0xC + + + TXFIFO13 + Tx FIFO 13 + 0xD + + + TXFIFO14 + Tx FIFO 14 + 0xE + + + TXFIFO15 + Tx FIFO 15 + 0xF + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd (micro)Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DIEPINT11 + Device IN Endpoint Interrupt Register + 0xA68 + read-write + 0x00000080 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + TIMEOUT + Timeout Condition (TimeOUT) + 3 + 3 + + + INACTIVE + No Timeout interrupt + 0x0 + + + ACTIVE + Timeout interrupt + 0x1 + + + + + INTKNTXFEMP + IN Token Received When TxFIFO is Empty (INTknTXFEmp) + 4 + 4 + + + INACTIVE + No IN Token Received interrupt + 0x0 + + + ACTIVE + IN Token Received Interrupt + 0x1 + + + + + INTKNEPMIS + IN Token Received with EP Mismatch (INTknEPMis) + 5 + 5 + + + INACTIVE + No IN Token Received with EP Mismatch interrupt + 0x0 + + + ACTIVE + IN Token Received with EP Mismatch interrupt + 0x1 + + + + + INEPNAKEFF + IN Endpoint NAK Effective (INEPNakEff) + 6 + 6 + + + INACTIVE + No Endpoint NAK Effective interrupt + 0x0 + + + ACTIVE + IN Endpoint NAK Effective interrupt + 0x1 + + + + + TXFEMP + Transmit FIFO Empty (TxFEmp) + 7 + 7 + read-only + + + INACTIVE + No Transmit FIFO Empty interrupt + 0x0 + + + ACTIVE + Transmit FIFO Empty interrupt + 0x1 + + + + + TXFIFOUNDRN + Fifo Underrun (TxfifoUndrn) + 8 + 8 + + + INACTIVE + No Tx FIFO Underrun interrupt + 0x0 + + + ACTIVE + TxFIFO Underrun interrupt + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + + + DIEPTSIZ11 + Device IN Endpoint Transfer Size Register + 0xA70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + MC + MC + 29 + 30 + + + PACKETONE + 1 packet + 0x1 + + + PACKETTWO + 2 packets + 0x2 + + + PACKETTHREE + 3 packets + 0x3 + + + + + + + DIEPDMA11 + Device IN Endpoint DMA Address Register + 0xA74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DTXFSTS11 + Device IN Endpoint Transmit FIFO Status Register + 0xA78 + read-write + 0x00000200 + 0x20 + + + INEPTXFSPCAVAIL + IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + 0 + 15 + read-only + + + + + DOEPCTL0 + Device Control OUT Endpoint 0 Control Register + 0xB00 + read-write + 0x00008000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 1 + read-only + + + BYTE64 + 64 bytes + 0x0 + + + BYTE32 + 32 bytes + 0x1 + + + BYTE16 + 16 bytes + 0x2 + + + BYTE8 + 8 bytes + 0x3 + + + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + read-only + + + ACTIVE + USB Active Endpoint 0 + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + INACTIVE + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + ACTIVE + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + read-only + + + ACTIVE + Endpoint Control 0 + 0x0 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + No Stall + 0x0 + + + ACTIVE + Stall Handshake + 0x1 + + + + + CNAK + Clear NAK (CNAK) + 26 + 26 + write-only + + + NOCLEAR + No action + 0x0 + + + CLEAR + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + NOSET + No action + 0x0 + + + SET + Set NAK + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + read-only + + + INACTIVE + No Endpoint disable + 0x0 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT0 + Device OUT Endpoint 0 Interrupt Register + 0xB08 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ0 + Device OUT Endpoint 0 Transfer Size Register + 0xB10 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 6 + + + PKTCNT + Packet Count (PktCnt) + 19 + 19 + + + SUPCNT + SETUP Packet Count (SUPCnt) + 29 + 30 + + + ONEPACKET + 1 packet + 0x1 + + + TWOPACKET + 2 packets + 0x2 + + + THREEPACKET + 3 packets + 0x3 + + + + + + + DOEPDMA0 + Device OUT Endpoint 0 DMA Address Register + 0xB14 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL1 + Device Control OUT Endpoint Control Register + 0xB20 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT1 + Device OUT Endpoint Interrupt Register + 0xB28 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ1 + Device OUT Endpoint Transfer Size Register + 0xB30 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA1 + Device OUT Endpoint DMA Address Register + 0xB34 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL2 + Device Control OUT Endpoint Control Register + 0xB40 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT2 + Device OUT Endpoint Interrupt Register + 0xB48 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ2 + Device OUT Endpoint Transfer Size Register + 0xB50 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA2 + Device OUT Endpoint DMA Address Register + 0xB54 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL3 + Device Control OUT Endpoint Control Register + 0xB60 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT3 + Device OUT Endpoint Interrupt Register + 0xB68 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ3 + Device OUT Endpoint Transfer Size Register + 0xB70 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA3 + Device OUT Endpoint DMA Address Register + 0xB74 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL4 + Device Control OUT Endpoint Control Register + 0xB80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT4 + Device OUT Endpoint Interrupt Register + 0xB88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ4 + Device OUT Endpoint Transfer Size Register + 0xB90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA4 + Device OUT Endpoint DMA Address Register + 0xB94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL5 + Device Control OUT Endpoint Control Register + 0xBA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT5 + Device OUT Endpoint Interrupt Register + 0xBA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ5 + Device OUT Endpoint Transfer Size Register + 0xBB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA5 + Device OUT Endpoint DMA Address Register + 0xBB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL12 + Device Control OUT Endpoint Control Register + 0xC80 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT12 + Device OUT Endpoint Interrupt Register + 0xC88 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ12 + Device OUT Endpoint Transfer Size Register + 0xC90 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA12 + Device OUT Endpoint DMA Address Register + 0xC94 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL13 + Device Control OUT Endpoint Control Register + 0xCA0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT13 + Device OUT Endpoint Interrupt Register + 0xCA8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ13 + Device OUT Endpoint Transfer Size Register + 0xCB0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA13 + Device OUT Endpoint DMA Address Register + 0xCB4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL14 + Device Control OUT Endpoint Control Register + 0xCC0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT14 + Device OUT Endpoint Interrupt Register + 0xCC8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ14 + Device OUT Endpoint Transfer Size Register + 0xCD0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA14 + Device OUT Endpoint DMA Address Register + 0xCD4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + DOEPCTL15 + Device Control OUT Endpoint Control Register + 0xCE0 + read-write + 0x00000000 + 0x20 + + + MPS + Maximum Packet Size (MPS) + 0 + 10 + + + USBACTEP + USB Active Endpoint (USBActEP) + 15 + 15 + + + DISABLED + Not Active + 0x0 + + + ENABLED + USB Active Endpoint + 0x1 + + + + + DPID + Endpoint Data PID (DPID) + 16 + 16 + read-only + + + INACTIVE + Endpoint Data PID not active + 0x0 + + + ACTIVE + Endpoint Data PID active + 0x1 + + + + + NAKSTS + NAK Status (NAKSts) + 17 + 17 + read-only + + + NONNAK + The core is transmitting non-NAK handshakes based on the FIFO status + 0x0 + + + NAK + The core is transmitting NAK handshakes on this endpoint + 0x1 + + + + + EPTYPE + Endpoint Type (EPType) + 18 + 19 + + + CONTROL + Control + 0x0 + + + ISOCHRONOUS + Isochronous + 0x1 + + + BULK + Bulk + 0x2 + + + INTERRUPT + Interrupt + 0x3 + + + + + STALL + STALL Handshake (Stall) + 21 + 21 + + + INACTIVE + STALL All non-active tokens + 0x0 + + + ACTIVE + STALL All Active Tokens + 0x1 + + + + + CNAK + 26 + 26 + write-only + + + INACTIVE + No Clear NAK + 0x0 + + + ACTIVE + Clear NAK + 0x1 + + + + + SNAK + Set NAK (SNAK) + 27 + 27 + write-only + + + INACTIVE + No Set NAK + 0x0 + + + ACTIVE + Set NAK + 0x1 + + + + + SETD0PID + Set DATA0 PID (SetD0PID) + 28 + 28 + write-only + + + DISABLED + Disables Set DATA0 PID or Do not force Even Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + SETD1PID + Set DATA1 PID (SetD1PID) + 29 + 29 + write-only + + + DISABLED + Disables Set DATA1 PID or Do not force Odd Frame + 0x0 + + + ENABLED + Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + 0x1 + + + + + EPDIS + Endpoint Disable (EPDis) + 30 + 30 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Disable Endpoint + 0x1 + + + + + EPENA + Endpoint Enable (EPEna) + 31 + 31 + + + INACTIVE + No Action + 0x0 + + + ACTIVE + Enable Endpoint + 0x1 + + + + + + + DOEPINT15 + Device OUT Endpoint Interrupt Register + 0xCE8 + read-write + 0x00000000 + 0x20 + + + XFERCOMPL + Transfer Completed Interrupt (XferCompl) + 0 + 0 + + + INACTIVE + No Transfer Complete Interrupt + 0x0 + + + ACTIVE + Transfer Complete Interrupt + 0x1 + + + + + EPDISBLD + Endpoint Disabled Interrupt (EPDisbld) + 1 + 1 + + + INACTIVE + No Endpoint Disabled Interrupt + 0x0 + + + ACTIVE + Endpoint Disabled Interrupt + 0x1 + + + + + AHBERR + AHB Error (AHBErr) + 2 + 2 + + + INACTIVE + No AHB Error Interrupt + 0x0 + + + ACTIVE + AHB Error interrupt + 0x1 + + + + + SETUP + SETUP Phase Done (SetUp) + 3 + 3 + + + INACTIVE + No SETUP Phase Done + 0x0 + + + ACTIVE + SETUP Phase Done + 0x1 + + + + + OUTTKNEPDIS + OUT Token Received When Endpoint Disabled (OUTTknEPdis) + 4 + 4 + + + INACTIVE + No OUT Token Received When Endpoint Disabled + 0x0 + + + ACTIVE + OUT Token Received When Endpoint Disabled + 0x1 + + + + + STSPHSERCVD + Status Phase Received for Control Write (StsPhseRcvd) + 5 + 5 + + + INACTIVE + No Status Phase Received for Control Write + 0x0 + + + ACTIVE + Status Phase Received for Control Write + 0x1 + + + + + BACK2BACKSETUP + Back-to-Back SETUP Packets Received (Back2BackSETup) + 6 + 6 + + + INACTIVE + No Back-to-Back SETUP Packets Received + 0x0 + + + ACTIVE + Back-to-Back SETUP Packets Received + 0x1 + + + + + OUTPKTERR + OUT Packet Error (OutPktErr) + 8 + 8 + + + INACTIVE + No OUT Packet Error + 0x0 + + + ACTIVE + OUT Packet Error + 0x1 + + + + + BNAINTR + BNA (Buffer Not Available) Interrupt (BNAIntr) + 9 + 9 + + + INACTIVE + No BNA interrupt + 0x0 + + + ACTIVE + BNA interrupt + 0x1 + + + + + PKTDRPSTS + Packet Drop Status (PktDrpSts) + 11 + 11 + + + INACTIVE + No interrupt + 0x0 + + + ACTIVE + Packet Drop Status interrupt + 0x1 + + + + + BBLEERR + NAK Interrupt (BbleErr) + 12 + 12 + + + INACTIVE + No BbleErr interrupt + 0x0 + + + ACTIVE + BbleErr interrupt + 0x1 + + + + + NAKINTRPT + NAK Interrupt (NAKInterrupt) + 13 + 13 + + + INACTIVE + No NAK interrupt + 0x0 + + + ACTIVE + NAK Interrupt + 0x1 + + + + + NYETINTRPT + NYET Interrupt (NYETIntrpt) + 14 + 14 + + + INACTIVE + No NYET interrupt + 0x0 + + + ACTIVE + NYET Interrupt + 0x1 + + + + + STUPPKTRCVD + Setup Packet Received + 15 + 15 + + + NOT_RCVD + No Setup packet received + 0x0 + + + RCVD + Setup packet received + 0x1 + + + + + + + DOEPTSIZ15 + Device OUT Endpoint Transfer Size Register + 0xCF0 + read-write + 0x00000000 + 0x20 + + + XFERSIZE + Transfer Size (XferSize) + 0 + 18 + + + PKTCNT + Packet Count (PktCnt) + 19 + 28 + + + RXDPID + RxDPID + 29 + 30 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA2PACKET1 + DATA2 or 1 packet + 0x1 + + + DATA1PACKET2 + DATA1 or 2 packets + 0x2 + + + MDATAPACKET3 + MDATA or 3 packets + 0x3 + + + + + + + DOEPDMA15 + Device OUT Endpoint DMA Address Register + 0xCF4 + read-write + 0x00000000 + 0x20 + + + DMAADDR + Holds the start address of the external memory for storing or fetching endpoint + 0 + 31 + + + + + PCGCCTL + Power and Clock Gating Control Register + 0xE00 + read-write + 0x880A0000 + 0x20 + + + STOPPCLK + Stop Pclk (StopPclk) + 0 + 0 + + + DISABLED + Disable Stop Pclk + 0x0 + + + ENABLED + Enable Stop Pclk + 0x1 + + + + + GATEHCLK + Gate Hclk (GateHclk) + 1 + 1 + + + DISABLED + Clears this bit when the USB is resumed or a new session starts + 0x0 + + + ENABLED + Sets this bit to gate hclk to modules when the USB is suspended or the session is not valid + 0x1 + + + + + RSTPDWNMODULE + Reset Power-Down Modules (RstPdwnModule) + 3 + 3 + + + ON + Power is turned on + 0x0 + + + OFF + Power is turned off + 0x1 + + + + + ENBLL1GATING + Enable Sleep Clock Gating + 5 + 5 + + + DISABLED + The PHY clock is not gated in Sleep state + 0x0 + + + ENABLED + The Core internal clock gating is enabled in Sleep state + 0x1 + + + + + PHYSLEEP + PHY In Sleep + 6 + 6 + read-only + + + INACTIVE + Phy not in Sleep state + 0x0 + + + ACTIVE + Phy in Sleep state + 0x1 + + + + + L1SUSPENDED + L1 Deep Sleep + 7 + 7 + read-only + + + INACTIVE + Non Deep Sleep + 0x0 + + + ACTIVE + Deep Sleep + 0x1 + + + + + RESTOREMODE + Restore Mode (RestoreMode) + 9 + 9 + + + DISABLED + In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this bit indicates Device-initiated Remote Wakeup + 0x0 + + + ENABLED + In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this bit indicates Host-initiated Resume and Reset + 0x1 + + + + + ESSREGRESTORED + Essential Register Values Restored (EssRegRestored) + 13 + 13 + write-only + + + NOT_RESTORED + Register values of essential registers are not restored + 0x0 + + + RESTORED + Register values of essential registers have been restored + 0x1 + + + + + RESTOREVALUE + Restore Value (RestoreValue) + 14 + 31 + + + + + GSTARFXDIS + Global STAR Fix Disable Register + 0xF00 + read-write + 0x00002200 + 0x20 + + + HOSTIGNORESRMTWKUPDIS + Disable the STAR fix added for Device controller to go back to low power mode when Host ignores Remote wakeup + 0 + 0 + + + ENABLE_FIX + Device controller goes back into SUSPENDED state when host ignores Remote Wakeup + 0x0 + + + DISABLE_FIX + Device controller waits indefinitely without entering SUSPENDED state when host ignores the Remote Wakeup + 0x1 + + + + + RESUMEFRMCHKBUSDIS + Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after the 50us pull-up delay ends + 1 + 1 + + + ENABLE_FIX + Device controller detects line K and resumes + 0x0 + + + DISABLE_FIX + Device controller does not detect line K and resume + 0x1 + + + + + IGNORECTLOUTDATA0DIS + Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data Phase and Control Status OUT Phase + 2 + 2 + + + ENABLE_FIX + Transaction Error reported when host sends DATA0 PID + 0x0 + + + DISABLE_FIX + Transaction Error not reported when host sends DATA0 PID + 0x1 + + + + + SSPLITSTALLNYETERRDIS + Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET + 3 + 3 + + + ENABLE_FIX + Transaction Error reported when device sends STALL/NYET for SSPLIT + 0x0 + + + DISABLE_FIX + Transaction Error not reported when device sends STALL/NYET for SSPLIT + 0x1 + + + + + ACCEPTISOCSPLITDATA1DIS + Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC Split transfers + 4 + 4 + + + ENABLE_FIX + Transaction Error not reported when device sends DATA1 PID for ISOC Split + 0x0 + + + DISABLE_FIX + Transaction Error reported when device sends DATA1 PID for ISOC Split + 0x1 + + + + + HANDLEFAULTYCABLEDIS + Disable the STAR fix added for Host controller to handle Faulty cable scenarios + 5 + 5 + + + ENABLE_FIX + Fix for handling faulty cable enabled + 0x0 + + + DISABLE_FIX + Fix for handling faulty cable disabled + 0x1 + + + + + LSIPGINCRDIS + Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit times + 6 + 6 + + + ENABLE_FIX + Host LS mode IPG is 3 LS bit times + 0x0 + + + DISABLE_FIX + Host LS mode IPG is 2 LS bit times + 0x1 + + + + + FSDISCIDLEDIS + Disable the STAR fix added for Device controller to transition to IDLE state during FS device disconnect + 7 + 7 + + + ENABLE_FIX + Device controller transitions to IDLE state during FS device disconnect + 0x0 + + + DISABLE_FIX + Device controller does not transition to IDLE state during FS device disconnect + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEDIS + Disable the STAR fix added for Device controller to not start Remote Wakeup signalling when USB resume has already started + 8 + 8 + + + ENABLE_FIX + Device controller does not start remote wakeup signalling when host resume has already started + 0x0 + + + DISABLE_FIX + Device controller is allowed to start remote wakeup signalling when host resume has already started + 0x1 + + + + + CONCURRENTRMTWKUPUSBRESUMEHIBDIS + Disable the STAR fix added for Device controller to not hang when Remote Wakeup signalling clashes with Host resume + 9 + 9 + + + ENABLE_FIX + Device controller does not hang when remote wakeup signalling clashes with host resume during Hibernation exit + 0x0 + + + DISABLE_FIX + Device controller hangs when remote wakeup signalling clashes with host resume during Hibernation exit + 0x1 + + + + + LSIPGCHKAFTERNAKSTALLFORINDIS + Disable the STAR fix added for Host controller to wait for IPG duration to send next token after receiving NAK/STALL for previous IN token with FS/LS device + 10 + 10 + + + ENABLE_FIX + Host controller checks IPG after NAK/STALL for IN token + 0x0 + + + DISABLE_FIX + Host controller does not check IPG after NAK/STALL for IN token + 0x1 + + + + + PHYIOPXCVRSELTXVLDCORRDIS + Disable the STAR fix added for Host controller to increase the gap between utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode + 11 + 11 + + + ENABLE_FIX + Host controller asserts utmi_txvalid at least 2 utmi_clk cycles after utmi_xcvrselect switching + 0x0 + + + DISABLE_FIX + Host controller can assert utmi_txvalid after 1 utmi_clk cycle of utmi_xcvrselect switching + 0x1 + + + + + ULPIXCVRSELSWITCHCORRDIS + Disable the STAR fix added for Host controller to increase the preamble transceiver select switch delay to accommodate time taken for ULPI function control write + 12 + 12 + + + ENABLE_FIX + Host controller waits for previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x0 + + + DISABLE_FIX + Host controller does not wait for the previous functional register update to complete before switching the transceiver select again or asserting txvalid + 0x1 + + + + + XACTERRDATA0CTRLSTSINDIS + Disable the STAR fix added for Host controller to report transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 13 + 13 + + + ENABLE_FIX + Host controller reports transaction error when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x0 + + + DISABLE_FIX + Host controller retries the transfer when DATA0 PID is received for CTRL STATUS IN transfer in DMA mode + 0x1 + + + + + HOSTUTMITXVLDCORRDIS + Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. + 16 + 16 + + + ENABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller after TxValid goes LOW (1'b0) + 0x0 + + + DISABLE_FIX + Opmode, XcvrSel, TermSel are changed by the Host Controller without waiting for TxValid to go LOW (1'b0) during SOF transmission + 0x1 + + + + + OPMODEXCVRSELCHIRPENCORRDIS + Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when reset is detected in suspend state. + 17 + 17 + + + ENABLE_FIX + Valid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x0 + + + DISABLE_FIX + Invalid Combination of Opmode and XcvrSel is driven when reset is detected in suspend state + 0x1 + + + + + TXVALIDDEASSERTIONCORRDIS + Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft disconnect is done. + 18 + 18 + + + ENABLE_FIX + Txvalid is deasserted during soft disconnect after receiving Txready from the PHY + 0x0 + + + DISABLE_FIX + Txvalid is deasserted during soft disconnect without waiting for Txready from the PHY + 0x1 + + + + + HOSTNOXFERAFTERPRTDISFIXDIS + Disable the STAR fix added for correcting Host behavior when port is disabled. + 19 + 19 + + + ENABLE_FIX + Txvalid is not asserted when port is disabled + 0x0 + + + DISABLE_FIX + Txvalid can be asserted when port is disabled + 0x1 + + + + + + + 16 + 0x1000 + DWCOTGDFIFO[%s] + Unspecified + USBHSCORE_DWCOTGDFIFO + read-write + 0x1000 + + 0x400 + 0x4 + DATA[%s] + Description collection: Data FIFO Access Register Map 0 + 0x0000 + read-write + 0x00000000 + 0x20 + + + + DWCOTGDFIFODIRECTACCESS + Unspecified + USBHSCORE_DWCOTGDFIFODIRECTACCESS + read-write + 0x20000 + + 0x8000 + 0x4 + DATA[%s] + Description collection: Data FIFO Direct Access Register Map + 0x00000 + read-write + 0x00000000 + 0x20 + + + + + + GLOBAL_USBHSCORE0_S + USBHSCORE 1 + 0x2F700000 + GLOBAL_USBHSCORE0_NS + + + + + GLOBAL_I3CCORE120_NS + I3CCORE 0 + 0x2FBE0000 + I3CCORE + + + + 0 + 0x1000 + registers + + I3CCORE + 0x20 + + + CORE + Unspecified + I3CCORE_CORE + read-write + 0x000 + + DEVICECTRL + DWC_mipi_i3c control Register + 0x000 + read-write + 0x00000000 + 0x20 + + + IBAINCLUDE + I3C Broadcast Address include + 0 + 0 + + + NOT_INCLUDED + Unspecified + 0x0 + + + INCLUDED + Unspecified + 0x1 + + + + + I2CSLAVEPRESENT + I2C Slave Present + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + HOTJOINCTRL + Hot-Join ACK/NACK Control + 8 + 8 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + IDLECNTMULTPLIER + Idle Count Multiplier + 24 + 25 + + + MultiplyBy1 + Unspecified + 0x0 + + + MultiplyBy2 + Unspecified + 0x1 + + + MultiplyBy4 + Unspecified + 0x2 + + + MultiplyBy8 + Unspecified + 0x3 + + + + + ADAPTIVEI2CI3C + This field is used in Slave mode of operation. + 27 + 27 + + + DMAENABLE + DMA Handshake Interface Enable + 28 + 28 + + + DISABLE + The DMA handshake control has no significance. + 0x0 + + + ENABLE + Enables the DMA handshake control to interact with external DMA. + 0x1 + + + + + ABORT + DWC_mipi_i3c Abort + 29 + 29 + + + RESUME + DWC_mipi_i3c Resume + 30 + 30 + + + ENABLE + Controls whether or not DWC_mipi_i3c is enabled. + 31 + 31 + + + DISABLE + Disables the DWC_mipi_i3c controller + 0x0 + + + ENABLE + Enables the DWC_mipi_i3c controller. + 0x1 + + + + + + + DEVICEADDR + In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit. + 0x004 + read-write + 0x80000000 + 0x20 + + + STATICADDR + Device Static Address. + 0 + 6 + + + STATICADDRVALID + Static Address Valid. + 15 + 15 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + DYNAMICADDR + Device Dynamic Address. + 16 + 22 + + + DYNAMICADDRVALID + Dynamic Address Valid + 31 + 31 + + + INVALID + Unspecified + 0x0 + + + VALID + Unspecified + 0x1 + + + + + + + HWCAPABILITY + Hardware Capability register + 0x008 + read-write + 0x000E187B + 0x20 + + + DEVICEROLECONFIG + Reflects the IC_DEVICE_ROLE Configurable Parameter. + 0 + 2 + read-only + + + MASTER + Master Only + 0x1 + + + PMASTERSLAVE + Programmable Master-Slave + 0x2 + + + SECONDARYMASTER + Secondary Master + 0x3 + + + SLAVE + Slave Only + 0x4 + + + + + HDRDDREN + Reflects the IC_SPEED_HDR_DDR Configurable Parameter. + 3 + 3 + read-only + + + NOTSUPPORTED + HDR-DDR not supported + 0x0 + + + SUPPORTED + HDR-DDR supported + 0x1 + + + + + HDRTSEN + Reflects the IC_SPEED_HDR_TS Configurable Parameter. + 4 + 4 + read-only + + + NOTSUPPORTED + HDR-TS not supported + 0x0 + + + SUPPORTED + HDR-TS supported + 0x1 + + + + + CLOCKPERIOD + Reflects the IC_CLK_PERIOD Configurable Parameter + 5 + 10 + read-only + + + HDRTXCLOCKPERIOD + Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. + 11 + 16 + read-only + + + DMAEN + Reflects the IC_HAS_DMA Configurable Parameter. + 17 + 17 + read-only + + + SLVHJCAP + Reflects the IC_SLV_HJ Configurable Parameter. + 18 + 18 + read-only + + + SLVIBICAP + Reflects the IC_SLV_IBI Configurable Parameter. + 19 + 19 + read-only + + + + + COMMANDQUEUEPORT + Command Queue Port. + 0x00C + read-write + 0x00000000 + 0x20 + + + COMMAND + 32 bit command + 0 + 31 + write-only + + + + + RESPONSEQUEUEPORT + Response Queue Port + 0x010 + read-write + 0x00000000 + 0x20 + + + RESPONSE + 32 bit Response + 0 + 31 + read-only + + + + + RXDATAPORT + Receive Data Port Register + 0x014 + read-write + 0x00000000 + 0x20 + + + RXDATAPORT + Receive Data Port. + 0 + 31 + read-only + + + + + TXDATAPORT + Transmit Data Port Register + 0x014 + read-write + 0x00000000 + RXDATAPORT + 0x20 + + + TXDATAPORT + Transmit Data Port + 0 + 31 + write-only + + + + + IBIQUEUEDATA + In-Band Interrupt Queue Data Register + 0x018 + read-write + 0x00000000 + 0x20 + + + IBIDATA + In-Band Interrupt Data + 0 + 31 + read-only + + + + + IBIQUEUESTATUS + In-Band Interrupt Queue Status Register + 0x018 + read-write + 0x00000000 + IBIQUEUEDATA + 0x20 + + + DATALENGTH + In-Band Interrupt data length. + 0 + 7 + read-only + + + IBIID + IBI Identifier. + 8 + 15 + read-only + + + IBIACK + The acknowledge bit of the IBI Received Status (IBISTS) bitfield. + 31 + 31 + read-only + + + ACK + Responded with ACK + 0x0 + + + NACK + Responded with NACK + 0x1 + + + + + + + QUEUETHLDCTRL + Queue Threshold Control Register + 0x01C + read-write + 0x01000101 + 0x20 + + + CMDEMPTYBUFTHLD + Command Buffer Empty Threshold Value. + 0 + 7 + + + RESPBUFTHLD + Response Buffer Threshold Value. + 8 + 15 + + + IBISTATUSTHLD + In-Band Interrupt Status Threshold Value. + 24 + 31 + + + + + DATABUFFERTHLDCTRL + Data Buffer Threshold Control Register + 0x020 + read-write + 0x01010101 + 0x20 + + + TXEMPTYBUFTHLD + Transmit Buffer Threshold Value + 0 + 2 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD14 + Unspecified + 0x1 + + + THRESHOLD18 + Unspecified + 0x2 + + + THRESHOLD116 + Unspecified + 0x3 + + + THRESHOLD132 + Unspecified + 0x4 + + + THRESHOLD164 + Unspecified + 0x5 + + + + + RXBUFTHLD + Receive Buffer Threshold Value + 8 + 10 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + TXSTARTTHLD + Transfer Start Threshold Value + 16 + 18 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + RXSTARTTHLD + Receive Start Threshold Value + 24 + 26 + + + THRESHOLD1 + Unspecified + 0x0 + + + THRESHOLD4 + Unspecified + 0x1 + + + THRESHOLD8 + Unspecified + 0x2 + + + THRESHOLD16 + Unspecified + 0x3 + + + THRESHOLD32 + Unspecified + 0x4 + + + THRESHOLD64 + Unspecified + 0x5 + + + + + + + IBIQUEUECTRL + This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked). + 0x024 + read-write + 0x00000000 + 0x20 + + + NOTIFYHJREJECTED + Notify Rejected Hot-Join Control. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + NOTIFYMRREJECTED + Notify Rejected Master Request Control. + 1 + 1 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a MR Request is NACKed and auto-disabled based on the IBI_MR_REQ_REJECT Register. + 0x1 + + + + + NOTIFYSIRREJECTED + Notify Rejected Slave Interrupt Request Control. + 3 + 3 + + + DISABLED + Suppress passing the IBI Status to the IBI FIFO (hence not notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x0 + + + ENABLED + Writes IBI Status to the IBI FIFO (hence notifying the application) when a Slave Interrupt Request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT Register. + 0x1 + + + + + + + IBIMRREQREJECT + IBI Master Request Rejection Control Register. + 0x02C + read-write + 0x00000000 + 0x20 + + + MRREQREJECT + In-band Master Request Reject. + 0 + 31 + + + ACK + ACK Master Request. + 0x00000000 + + + NACK + NACK and send Directed DISEC CCC to disable the interrupting slave. + 0x00000001 + + + + + + + IBISIRREQREJECT + IBI SIR Request Rejection Control + 0x030 + read-write + 0x00000000 + 0x20 + + + SIRREQREJECT + In-band Slave Interrupt Request Reject + 0 + 31 + + + ACK + ACK the SIR Request. + 0x00000000 + + + NACK + NACK and send directed auto disable CCC. + 0x00000001 + + + + + + + RESETCTRL + This Register is used for general software reset and for individual buffer reset. + 0x034 + read-write + 0x00000000 + 0x20 + + + SOFTRST + Core Software Reset. + 0 + 0 + + + CMDQUEUERST + Command Queue Software Reset + 1 + 1 + + + RESPQUEUERST + Response Queue Software Reset + 2 + 2 + + + TXFIFORST + Transmit Buffer Software Reset + 3 + 3 + + + RXFIFORST + Receive Buffer Software Reset. + 4 + 4 + + + IBIQUEUERST + IBI Queue Software Reset. + 5 + 5 + + + BUSRESETTYPE + Bus Reset type + 29 + 30 + + + EXIT + Exit Pattern. + 0x0 + + + SCL_LOW_RESET + SCL_LOW_RESET Pattern. + 0x3 + + + + + BUSRESET + Bus Reset. + 31 + 31 + + + + + SLVEVENTSTATUS + This register indicates the status/values of some events/controls that are relavant to slave mode of operation. + 0x038 + read-write + 0x0000000B + 0x20 + + + SIREN + Slave Interrupt Request Enable. + 0 + 0 + read-only + + + MREN + Master Request Enable. + 1 + 1 + read-only + + + HJEN + Hot-Join Interrupt Enable + 3 + 3 + + + ACTIVITYSTATE + Activity State Status. + 4 + 5 + read-only + + + ENTAS0 + Unspecified + 0x0 + + + ENTAS1 + Unspecified + 0x1 + + + ENTAS2 + Unspecified + 0x2 + + + ENTAS3 + Unspecified + 0x3 + + + + + MRLUPDATED + MRL Updated Status. + 6 + 6 + + + MWLUPDATED + MWL Updated Status. + 7 + 7 + + + + + INTRSTATUS + Interrupt Status Register + 0x03C + read-write + 0x00000000 + 0x20 + + + TXTHLDSTS + Transmit Buffer Threshold Status + 0 + 0 + read-only + + + RXTHLDSTS + Receive Buffer Threshold Status. + 1 + 1 + read-only + + + IBITHLDSTS + IBI Buffer Threshold Status. + 2 + 2 + read-only + + + CMDQUEUEREADYSTS + Command Queue Ready. + 3 + 3 + read-only + + + RESPREADYSTS + Response Queue Ready Status. + 4 + 4 + read-only + + + TRANSFERABORTSTS + Transfer Abort Status. + 5 + 5 + + + CCCUPDATEDSTS + CCC Table Updated Status. + 6 + 6 + + + DYNADDRASSGNSTS + Dynamic Address Assigned Status. + 8 + 8 + + + TRANSFERERRSTS + Transfer Error Status. + 9 + 9 + + + DEFSLVSTS + Define Slave CCC Received Status. + 10 + 10 + + + READREQRECVSTS + Read Request Received. + 11 + 11 + + + IBIUPDATEDSTS + IBI status is updated. + 12 + 12 + + + BUSOWNERUPDATEDSTS + This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa. + 13 + 13 + + + BUSRESETDONESTS + Bus Reset Pattern Generation Done Status. + 15 + 15 + + + + + INTRSTATUSEN + Interrupt Status Enable Register. + 0x040 + read-write + 0x00000000 + 0x20 + + + TXTHLDSTSEN + Transmit Buffer Threshold Status Enable. + 0 + 0 + + + RXTHLDSTSEN + Receive Buffer Threshold Status Enable + 1 + 1 + + + IBITHLDSTSEN + IBI Buffer Threshold Status Enable. + 2 + 2 + + + CMDQUEUEREADYSTSEN + Command Queue Ready Status Enable + 3 + 3 + + + RESPREADYSTSEN + Response Queue Ready Status Enable + 4 + 4 + + + TRANSFERABORTSTSEN + Transfer Abort Status Enable. + 5 + 5 + + + CCCUPDATEDSTSEN + CCC Table Updated Status Enable. + 6 + 6 + + + DYNADDRASSGNSTSEN + Dynamic Address Assigned Status Enable + 8 + 8 + + + TRANSFERERRSTSEN + Transfer Error Status Enable + 9 + 9 + + + DEFSLVSTSEN + Define Slave CCC Received Status Enable + 10 + 10 + + + READREQRECVSTSEN + Read Request Received Status Enable + 11 + 11 + + + IBIUPDATEDSTSEN + IBI Updated Status Enable + 12 + 12 + + + BUSOWNERUPDATEDSTSEN + Bus owner Updated Status Enable + 13 + 13 + + + BUSRESETDONESTSEN + Bus Reset Pattern Generation Done Status Enable. + 15 + 15 + + + + + INTRSIGNALEN + Interrupt Signal Enable Register + 0x044 + read-write + 0x00000000 + 0x20 + + + TXTHLDSIGNALEN + Transmit Buffer Threshold Signal Enable + 0 + 0 + + + RXTHLDSIGNALEN + Receive Buffer Threshold Signal Enable + 1 + 1 + + + IBITHLDSIGNALEN + IBI Buffer Threshold Signal Enable + 2 + 2 + + + CMDQUEUEREADYSIGNALEN + Command Queue Ready Signal Enable + 3 + 3 + + + RESPREADYSIGNALEN + Response Queue Ready Signal Enable + 4 + 4 + + + TRANSFERABORTSIGNALEN + Transfer Abort Signal Enable + 5 + 5 + + + CCCUPDATEDSIGNALEN + CCC Table Updated Signal Enable + 6 + 6 + + + DYNADDRASSGNSIGNALEN + Dynamic Address Assigned Signal Enable + 8 + 8 + + + TRANSFERERRSIGNALEN + Transfer Error Signal Enable + 9 + 9 + + + DEFSLVSIGNALEN + Define Slave CCC Received Signal Enable + 10 + 10 + + + READREQRECVSIGNALEN + Read Request Received Signal Enable + 11 + 11 + + + IBIUPDATEDSIGNALEN + IBI Updated Signal Enable + 12 + 12 + + + BUSOWNERUPDATEDSIGNALEN + Bus owner Updated Signal Enable + 13 + 13 + + + BUSRESETDONESIGNALEN + Bus Reset Pattern Generation Done Signal Enable. + 15 + 15 + + + + + INTRFORCE + Interrupt Force Enable Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TXTHLDFORCEEN + Transmit Buffer Threshold Force Enable + 0 + 0 + write-only + + + RXTHLDFORCEEN + Receive Buffer Threshold Force Enable + 1 + 1 + write-only + + + IBITHLDFORCEEN + IBI Buffer Threshold Force Enable + 2 + 2 + write-only + + + CMDQUEUEREADYFORCEEN + Command Queue Ready Force Enable + 3 + 3 + write-only + + + RESPREADYFORCEEN + Response Queue Ready Force Enable + 4 + 4 + write-only + + + TRANSFERABORTFORCEEN + Transfer Abort Force Enable + 5 + 5 + write-only + + + CCCUPDATEDFORCEEN + CCC Table Updated Force Enable + 6 + 6 + write-only + + + DYNADDRASSGNFORCEEN + Dynamic Address Assigned Force Enable + 8 + 8 + write-only + + + TRANSFERERRFORCEEN + Transfer Error Force Enable + 9 + 9 + write-only + + + DEFSLVFORCEEN + Define Slave CCC Received Force Enable + 10 + 10 + write-only + + + READREQFORCEEN + Read Request Received Force Enable + 11 + 11 + write-only + + + IBIUPDATEDFORCEEN + IBI Updated Force Enable + 12 + 12 + write-only + + + BUSOWNERUPDATEDFORCEEN + Bus owner Updated Force Enable + 13 + 13 + write-only + + + BUSRESETDONEFORCEEN + Bus Reset Pattern Generation Done Force Enable. + 15 + 15 + write-only + + + + + QUEUESTATUSLEVEL + Queue Status Level Register. + 0x04C + read-write + 0x00000010 + 0x20 + + + CMDQUEUEEMPTYLOC + Command Queue Empty Locations. + 0 + 7 + read-only + + + RESPBUFBLR + Response Buffer Level Value. + 8 + 15 + read-only + + + IBIBUFBLR + IBI Buffer Level Value. + 16 + 23 + read-only + + + IBISTSCNT + IBI Buffer Status Count. + 24 + 28 + read-only + + + + + DATABUFFERSTATUSLEVEL + Data Buffer Status Level Register. + 0x050 + read-write + 0x00000040 + 0x20 + + + TXBUFEMPTYLOC + Transmit Buffer Empty Level Value. + 0 + 7 + read-only + + + RXBUFBLR + Receive Buffer Level Value. + 16 + 23 + read-only + + + + + PRESENTSTATEM + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Master). + 0x054 + read-write + 0x10000003 + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + IDLE + Controller is in Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + BCCCWTRANSFER + Broadcast CCC Write Transfer. + 0x01 + + + DCCCWTRANSFER + Directed CCC Write Transfer. + 0x02 + + + DCCCRTRANSFER + Directed CCC Read Transfer. + 0x03 + + + ENTDAATRANSFER + ENTDAA Address Assignment Transfer. + 0x04 + + + SETDASATRANSFER + SETDASA Address Assignment Transfer. + 0x05 + + + SDRWTRANSFER + Private I3C SDR Write Transfer. + 0x06 + + + SDRRTRANSFER + Private I3C SDR Read Transfer. + 0x07 + + + SDRWTRANSFERI2C + Private I2C SDR Write Transfer. + 0x08 + + + SDRRTRANSFERI2C + Private I2C SDR Read Transfer. + 0x09 + + + TSWTRANSFER + Private HDR Ternary Symbol(TS) Write Transfer. + 0x0A + + + TSRTRANSFER + Private HDR Ternary Symbol(TS) Read Transfer. + 0x0B + + + DDRWTRANSFER + Private HDR Double-Data Rate(DDR) Write Transfer. + 0x0C + + + DDRRTRANSFER + Private HDR Double-Data Rate(DDR) Read Transfer. + 0x0D + + + IBITRANSFER + Servicing In-Band Interrupt Transfer. + 0x0E + + + HALT + Halt state. Controller is in Halt State, waiting for the application to resume through DEVICE_CTRL Register. + 0x0F + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + IDLE + Controller is Idle state, waiting for commands from application or Slave initated In-band Interrupt. + 0x00 + + + START + START Generation State. + 0x01 + + + RESTART + RESTART Generation State. + 0x02 + + + STOP + STOP Genration State. + 0x03 + + + STARTH + START Hold Generation for the Slave Initiated START State. + 0x04 + + + BWADDRGEN + Broadcast Write Address Header(7h7E,W) Generation State. + 0x05 + + + BRADDRGEN + Broadcast Read Address Header(7h7E,R) Generation State. + 0x06 + + + DAA + Dynamic Address Assignment State. + 0x07 + + + ADDRGEN + Slave Address Generation State. + 0x08 + + + CCCBYTEGEN + CCC Byte Generation State. + 0x0B + + + HDRCMDGEN + HDR Command Generation State. + 0x0C + + + WTRANSFER + Write Data Transfer State. + 0x0D + + + RTRANSFER + Read Data Transfer State. + 0x0E + + + RIBI + In-Band Interrupt(SIR) Read Data State. + 0x0F + + + IBIAUTODISABLE + In-Band Interrupt Auto-Disable State + 0x10 + + + DDRCRCGEN + HDR-DDR CRC Data Generation/Receive State. + 0x11 + + + CLKEXTEND + Clock Extension State. + 0x12 + + + HALT + Halt State. + 0x13 + + + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + PRESENTSTATES + The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register (Slave). + 0x054 + read-write + 0x10000003 + PRESENTSTATEM + 0x20 + + + SCLLINESIGNALLEVEL + This bit is used to check the SCL line level to recover from errors and for debugging. + 0 + 0 + read-only + + + SDALINESIGNALLEVEL + This bit is used to check the SDA line level to recover from errors and for debugging. + 1 + 1 + read-only + + + CURRENTMASTER + This Bit is used to check whether the Master is Current Master or not. + 2 + 2 + read-only + + + NOT_BUS_OWNER + Master is not Current Master + 0x0 + + + BUS_OWNER + Master is Current Master + 0x1 + + + + + CMTFRSTS + Transfer Type Status + 8 + 13 + read-only + + + SLAVEIDLE + Controller is in Idle state. + 0x00 + + + SLAVEHOTJOIN + Hot-Join transfer state. + 0x01 + + + SLAVEIBITRANSFER + IBI transfer state. + 0x02 + + + SLAVEWTRANSFER + Master write transfer ongoing. + 0x03 + + + SLAVERPREFETCH + Read data prefetch state. + 0x04 + + + SLAVERTRANSFER + Master read transfer ongoing. + 0x05 + + + SLAVEHALT + Slave controller in Halt State waiting for resume from application. + 0x06 + + + + + CMTFRSTSTS + Current Master Transfer State Status. + 16 + 21 + read-only + + + CMDTID + This field reflects the Transaction-ID of the current executing command. + 24 + 27 + read-only + + + MASTERIDLE + This field reflects whether the Master Controller is in Idle state or not. + 28 + 28 + read-only + + + MST_NOT_IDLE + Unspecified + 0x0 + + + MST_IDLE + Unspecified + 0x1 + + + + + + + CCCDEVICESTATUS + Device Operating Status Register. + 0x058 + read-write + 0x00000000 + 0x20 + + + PENDINGINTR + Pending Interrupt + 0 + 3 + read-only + + + PROTOCOLERR + Protocol Error + 5 + 5 + read-only + + + ACTIVITYMODE + Activity Mode + 6 + 7 + read-only + + + UNDERFLOWERR + Underflow error + 8 + 8 + read-only + + + SLAVEBUSY + Slave Busy + 9 + 9 + read-only + + + OVERFLOWERR + Overflow Error + 10 + 10 + read-only + + + DATANOTREADY + Data not ready + 11 + 11 + read-only + + + BUFFERNOTAVAIL + Buffer not available + 12 + 12 + read-only + + + FRAMEERROR + Frame Error + 13 + 13 + read-only + + + + + DEVICEADDRTABLEPOINTER + Pointer for Device Address Table + 0x05C + read-write + 0x000A02C0 + 0x20 + + + PDEVADDRTABLESTARTADDR + Start Address of Device Address Table. + 0 + 15 + read-only + + + DEVADDRTABLEDEPTH + Depth of Device Address Table + 16 + 31 + read-only + + + + + DEVCHARTABLEPOINTER + Pointer for Device Characteristics Table + 0x060 + read-write + 0x00028200 + 0x20 + + + PDEVCHARTABLESTARTADDR + Start Address of Device Characteristics Table. + 0 + 11 + read-only + + + DEVCHARTABLEDEPTH + Depth of Device Characteristics Table + 12 + 18 + read-only + + + PRESENTDEVCHARTABLEINDX + Current index of Device Characteristics Table. + 19 + 22 + + + + + VENDORSPECIFICREGPOINTER + Pointer for Vendor Specific Registers. + 0x06C + read-write + 0x000000B0 + 0x20 + + + PVENDORREGSTARTADDR + Start Address of Vendor specific registers. + 0 + 15 + read-only + + + + + SLVMIPIIDVALUE + I3C MIPI Manufacturer ID Register. + 0x070 + read-write + 0x00000000 + 0x20 + + + SLVPROVIDSEL + Specifies the Provisional ID Type Selector (PID[32]). + 0 + 0 + + + SLVMIPIMFGID + Specifies the MIPI Manufacturer ID. + 1 + 15 + + + + + SLVPIDVALUE + I3C Normal Provisional ID Register. + 0x074 + read-write + 0x00000000 + 0x20 + + + SLVPIDDCR + Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). + 0 + 11 + + + SLVINSTID + This field is used to program the instance ID of the Slave. + 12 + 15 + + + SLVPARTID + Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) + 16 + 31 + + + + + SLVCHARCTRL + I3C Slave Characteristic Register. + 0x078 + read-write + 0x00070062 + 0x20 + + + MAXDATASPEEDLIMIT + Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). + 0 + 0 + + + IBIREQUESTCAPABLE + IBI Request Capable field in Bus Characteristic Register (BCR[1]). + 1 + 1 + read-only + + + IBIPAYLOAD + IBI Payload field in Bus Characteristic Register (BCR[2]). + 2 + 2 + read-only + + + OFFLINECAPABLE + Offline Capable field in Bus Characteristic Register (BCR[3]). + 3 + 3 + read-only + + + BRIDGEIDENTIFIER + Bridge Identifier field in Bus Characteristic Register (BCR[4]). + 4 + 4 + read-only + + + HDRCAPABLE + SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). + 5 + 5 + + + DEVICEROLE + Device Role field in Bus Characteristic Register (BCR[7:6]). + 6 + 7 + + + DCR + I3C Device Characteristic Value. + 8 + 15 + + + HDRCAP + I3C Device HDR Capability Register Value. + 16 + 23 + read-only + + + + + SLVMAXLEN + I3C Max Write/Read Length Register. + 0x07C + read-write + 0x00FF00FF + 0x20 + + + MWL + I3C Device Max Write Length + 0 + 15 + read-only + + + MRL + I3C Device Max Read Length. + 16 + 31 + read-only + + + + + MAXREADTURNAROUND + MXDS Maximum Read Turnaround Time. + 0x080 + read-write + 0x00000000 + 0x20 + + + MXDSMAXRDTURN + Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. + 0 + 23 + read-only + + + + + MAXDATASPEED + The values in this register are returned by the slave as GETACCMST CCC data. + 0x084 + read-write + 0x00000000 + 0x20 + + + MXDSMAXWRSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device + 0 + 2 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSMAXRDSPEED + Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device + 8 + 10 + + + 12M5HZ + 12.5MHz + 0x0 + + + 8MHZ + 8MHZ + 0x1 + + + 6MHZ + 6MHz + 0x2 + + + 4MHZ + 4MHz + 0x3 + + + 2MHZ + 2MHz + 0x4 + + + + + MXDSCLKDATATURN + Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device + 16 + 18 + + + 8NS + 8ns + 0x0 + + + 9NS + 9ns + 0x1 + + + 10NS + 10ns + 0x2 + + + 11NS + 11ns + 0x3 + + + 12NS + 12ns + 0x4 + + + + + + + SLVINTRREQ + This register is used in slave mode of operation. + 0x08C + read-write + 0x00000000 + 0x20 + + + SIR + Slave Interrupt Request + 0 + 0 + + + SIRCTRL + Slave Interrupt Request Control + 1 + 2 + + + SEND + Send the Assigned Dynamic Address + 0x0 + + + + + MR + Master Request + 3 + 3 + + + IBISTS + IBI Completion Status + 8 + 9 + read-only + + + ACCEPTED + IBI accepted by the Master (ACK response received) + 0x1 + + + NOATTEMPT + IBI Not Attempted + 0x3 + + + + + + + SLVTSXSYMBLTIMING + TSP/TSL Symbol Timing Register + 0x090 + read-write + 0x0000003F + 0x20 + + + SLVTSXSYMBLCNT + TSP/TSL Symbol Count Value. + 0 + 5 + + + + + DEVICECTRLEXTENDED + Device Control Extended register. + 0x0B0 + read-write + 0x00000000 + 0x20 + + + DEVOPERATIONMODE + This bit is used to select the Device Operation Mode before the controller is enabled. + 0 + 1 + + + MASTER + Unspecified + 0x0 + + + SLAVE + Unspecified + 0x1 + + + + + REQMSTACKCTRL + In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current master. + 3 + 3 + + + ACK + ACK GETACCMST CCC + 0x0 + + + NACK + NACK GETACCMST CCC + 0x1 + + + + + + + SCLI3CODTIMING + SCL I3C Open Drain Timing Register + 0x0B4 + read-write + 0x000A0010 + 0x20 + + + I3CODLCNT + I3C Open Drain Low Count. + 0 + 7 + + + I3CODHCNT + I3C Open Drain High Count. + 16 + 23 + + + + + SCLI3CPPTIMING + SCL I3C Push Pull Timing Register + 0x0B8 + read-write + 0x000A000A + 0x20 + + + I3CPPLCNT + I3C Push Pull Low Count. + 0 + 7 + + + I3CPPHCNT + I3C Push Pull High Count. + 16 + 23 + + + + + SCLI2CFMTIMING + SCL I2C Fast Mode Timing Register + 0x0BC + read-write + 0x00100010 + 0x20 + + + I2CFMLCNT + I2C Fast Mode Low Count + 0 + 15 + + + I2CFMHCNT + I2C Fast Mode High Count + 16 + 31 + + + + + SCLI2CFMPTIMING + SCL I2C Fast Mode Plus Timing Register + 0x0C0 + read-write + 0x00100010 + 0x20 + + + I2CFMPLCNT + I2C Fast Mode Plus Low Count + 0 + 15 + + + I2CFMPHCNT + I2C Fast Mode Plus High Count + 16 + 23 + + + + + SCLEXTLCNTTIMING + SCL Extended Low Count Timing Register. + 0x0C8 + read-write + 0x20202020 + 0x20 + + + I3CEXTLCNT1 + I3C Extended Low Count Register 1 + 0 + 7 + + + I3CEXTLCNT2 + I3C Extended Low Count Register 2 + 8 + 15 + + + I3CEXTLCNT3 + I3C Extended Low Count Register 3 + 16 + 23 + + + I3CEXTLCNT4 + I3C Extended Low Count Register 4 + 24 + 31 + + + + + SCLEXTTERMNLCNTTIMING + SCL Termination Bit Low Count Timing Register + 0x0CC + read-write + 0x00030000 + 0x20 + + + I3CEXTTERMNLCNT + I3C Read Termination Bit Low count. + 0 + 3 + + + I3CTSSKEWCNT + I3C HDR Ternary Skew Count. + 16 + 19 + + + + + SDAHOLDSWITCHDLYTIMING + SDA Hold and Mode Switch Delay Timing Register + 0x0D0 + read-write + 0x00010000 + 0x20 + + + SDATXHOLD + This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with + 16 + 18 + + + + + BUSFREEAVAILTIMING + Bus Free and Available Timing Register + 0x0D4 + read-write + 0x00200020 + 0x20 + + + BUSFREETIME + This register field is used only in Master mode of operation + 0 + 15 + + + BUSAVAILABLETIME + This register field is used only in Slave mode of operation + 16 + 31 + + + + + BUSIDLETIMING + Bus Idle Timing Register + 0x0D8 + read-write + 0x00000020 + 0x20 + + + BUSIDLETIME + Bus Idle Count Value. + 0 + 19 + + + + + SCLLOWMSTEXTTIMEOUT + The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low Bus Reset Pattern. + 0x0DC + read-write + 0x003567E0 + 0x20 + + + SCLLOWMSTTIMEOUTCOUNT + This count defines the number of core clock periods to count for generation of the SCL Low Bus Reset Pattern. + 0 + 25 + + + + + I3CVERID + This register reflects the current release number of DWC_mipi_i3c + 0x0E0 + read-write + 0x3130302A + 0x20 + + + I3CVERID + Current release number + 0 + 31 + read-only + + + + + I3CVERTYPE + This register reflects the current release type of DWC_mipi_i3c. + 0x0E4 + read-write + 0x6C633033 + 0x20 + + + I3CVERTYPE + Current release type + 0 + 31 + read-only + + + + + QUEUESIZECAPABILITY + This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. + 0x0E8 + read-write + 0x00022355 + 0x20 + + + TXBUFSIZE + Transmit Data Buffer Size + 0 + 3 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + RXBUFSIZE + Receive Data Buffer Size + 4 + 7 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + 32DWORD + 32 DWORDS + 0x4 + + + 64DWORD + 64 DWORDS + 0x5 + + + + + CMDBUFSIZE + Command Queue Size + 8 + 11 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + RESPBUFSIZE + Response Queue Size + 12 + 15 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + IBIBUFSIZE + IBI Queue Size + 16 + 19 + read-only + + + 2DWORD + 2 DWORDS + 0x0 + + + 4DWORD + 4 DWORDS + 0x1 + + + 8DWORD + 8 DWORDS + 0x2 + + + 16DWORD + 16 DWORDS + 0x3 + + + + + + + 10 + 0x010 + DEVCHARTABLE[%s] + Unspecified + DEVCHARTABLE + read-write + 0x200 + + LOC1 + Description cluster: Device Characteristic Table Location-1 of Device [n] + 0x0 + read-write + 0x00000000 + 0x20 + + + LSBPROVISIONALID + The LSB 32-bit value of Provisional-ID + 0 + 31 + read-only + + + + + LOC2 + Description cluster: Device Characteristic Table Location-2 of Device [n] + 0x4 + read-write + 0x00000000 + 0x20 + + + MSBPROVISIONALID + The MSB 16-bit value of Provisional-ID + 0 + 15 + read-only + + + + + LOC3 + Description cluster: Device Characteristic Table Location-3 of Device [n] + 0x8 + read-write + 0x00000000 + 0x20 + + + DCR + Device Characteristic Value + 0 + 7 + read-only + + + BCR + Bus Characteristic Value + 8 + 15 + read-only + + + + + LOC4 + Description cluster: Device Characteristic Table Location-4 of Device [n] + 0xC + read-write + 0x00000000 + 0x20 + + + DEVDYNAMICADDR + Device Dynamic Address assigned. + 0 + 7 + read-only + + + + + + 0x20 + 0x4 + SECDEVCHARTABLE[%s] + Description collection: Secondary Master Device Characteristic Table Location of Device [n] + 0x200 + read-write + 0x00000000 + 0x20 + + + DYNAMICADDR + The Dynamic Addr of Device [n] + 0 + 7 + read-only + + + DCRTYPE + The DCR TYPE of Device [n] + 8 + 15 + read-only + + + BCRTYPE + The BCR TYPE of Device [n] + 16 + 23 + read-only + + + STATICADDR + The Static Addr of Device [n] + 24 + 31 + read-only + + + + + 0xA + 0x4 + DEVADDRTABLELOC[%s] + Description collection: Device Address Table of Device [n] + 0x2C0 + read-write + 0x00000000 + 0x20 + + + DEVSTATICADDR + Device Static Address. + 0 + 6 + + + DEVDYNAMICADDR + Device Dynamic Address with parity. + 16 + 23 + + + DEVNACKRETRYCNT + This field is used to set the Device NACK Retry count for the particular device. + 29 + 30 + + + LEGACYI2CDEVICE + Legacy I2C device or not. + 31 + 31 + + + + + + DMA + Unspecified + I3CCORE_DMA + read-write + 0x900 + + CH0 + Unspecified + I3CCORE_DMA_CH0 + read-write + 0x000 + + SAR0 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR0 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL00 + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x02504821 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + DSTTRWIDTH + Destination Transfer Width. + 1 + 3 + + + DST_TR_WIDTH_0 + Unspecified + 0x0 + + + DST_TR_WIDTH_1 + Unspecified + 0x1 + + + DST_TR_WIDTH_2 + Unspecified + 0x2 + + + DST_TR_WIDTH_3 + Unspecified + 0x3 + + + DST_TR_WIDTH_4 + Unspecified + 0x4 + + + DST_TR_WIDTH_5 + Unspecified + 0x5 + + + DST_TR_WIDTH_6 + Unspecified + 0x6 + + + DST_TR_WIDTH_7 + Unspecified + 0x7 + + + + + RSVDSRCTRWIDTH + Reserved field - read-only + 4 + 6 + read-only + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + RSVDSRCGATHEREN + Reserved field - read-only + 17 + 17 + read-only + + + DSTSCATTEREN + Destination scatter enable. + 18 + 18 + + + DST_SCATTER_DISABLE + Unspecified + 0x0 + + + DST_SCATTER_ENABLE + Unspecified + 0x1 + + + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL01 + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG0L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E00 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG0H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + RSVD2CFG + Reserved field - read-only + 12 + 14 + read-only + + + RSVD3CFG + Reserved field - read-only + 15 + 31 + read-only + + + + + DSR0 + Destination Scatter register. + 0x050 + read-write + 0x00000000 + 0x20 + + + DSI + Destination Scatter Interval. + 0 + 19 + + + DSC + Destination Scatter Count. + 20 + 24 + + + + + + CH1 + Unspecified + I3CCORE_DMA_CH1 + read-write + 0x058 + + SAR1 + This register contains the source address of the DMA transfer. + 0x000 + read-write + 0x00000000 + 0x20 + + + SAR + Current Source Address of DMA transfer. + 0 + 31 + + + + + DAR1 + This register contains the destination address of the DMA transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + DAR + Current Destination address of DMA transfer. + 0 + 31 + + + + + CTL1L + This register contains fields that control the DMA transfer. + 0x018 + read-write + 0x00F04805 + 0x20 + + + INTEN + Interrupt Enable Bit. + 0 + 0 + + + INTERRUPT_DISABLE + Unspecified + 0x0 + + + INTERRUPT_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTTRWIDTH + Reserved field - read-only + 1 + 3 + read-only + + + SRCTRWIDTH + Source Transfer Width. + 4 + 6 + + + SRC_TR_WIDTH_0 + Unspecified + 0x0 + + + SRC_TR_WIDTH_1 + Unspecified + 0x1 + + + SRC_TR_WIDTH_2 + Unspecified + 0x2 + + + SRC_TR_WIDTH_3 + Unspecified + 0x3 + + + SRC_TR_WIDTH_4 + Unspecified + 0x4 + + + SRC_TR_WIDTH_5 + Unspecified + 0x5 + + + SRC_TR_WIDTH_6 + Unspecified + 0x6 + + + SRC_TR_WIDTH_7 + Unspecified + 0x7 + + + + + DINC + Destination Address Increment. + 7 + 8 + + + DINC_0 + Unspecified + 0x0 + + + DINC_1 + Unspecified + 0x1 + + + DINC_2 + Unspecified + 0x2 + + + DINC_3 + Unspecified + 0x3 + + + + + SINC + Source Address Increment. + 9 + 10 + + + SINC_0 + Unspecified + 0x0 + + + SINC_1 + Unspecified + 0x1 + + + SINC_2 + Unspecified + 0x2 + + + SINC_3 + Unspecified + 0x3 + + + + + DESTMSIZE + Destination Burst Transaction Length. + 11 + 13 + + + DEST_MSIZE_0 + Unspecified + 0x0 + + + DEST_MSIZE_1 + Unspecified + 0x1 + + + DEST_MSIZE_2 + Unspecified + 0x2 + + + DEST_MSIZE_3 + Unspecified + 0x3 + + + DEST_MSIZE_4 + Unspecified + 0x4 + + + DEST_MSIZE_5 + Unspecified + 0x5 + + + DEST_MSIZE_6 + Unspecified + 0x6 + + + DEST_MSIZE_7 + Unspecified + 0x7 + + + + + SRCMSIZE + Source Burst Transaction Length. + 14 + 16 + + + SRC_MSIZE_0 + Unspecified + 0x0 + + + SRC_MSIZE_1 + Unspecified + 0x1 + + + SRC_MSIZE_2 + Unspecified + 0x2 + + + SRC_MSIZE_3 + Unspecified + 0x3 + + + SRC_MSIZE_4 + Unspecified + 0x4 + + + SRC_MSIZE_5 + Unspecified + 0x5 + + + SRC_MSIZE_6 + Unspecified + 0x6 + + + SRC_MSIZE_7 + Unspecified + 0x7 + + + + + SRCGATHEREN + Source gather enable. + 17 + 17 + + + SRC_GATHER_DISABLE + Unspecified + 0x0 + + + SRC_GATHER_ENABLE + Unspecified + 0x1 + + + + + RSVDDSTSCATTEREN + Reserved field - read-only + 18 + 18 + read-only + + + RSVDCTL + Reserved field - read-only + 19 + 19 + read-only + + + TTFC + Transfer Type and Flow Control. + 20 + 22 + + + TT_FC_0 + Unspecified + 0x0 + + + TT_FC_1 + Unspecified + 0x1 + + + TT_FC_2 + Unspecified + 0x2 + + + TT_FC_3 + Unspecified + 0x3 + + + TT_FC_4 + Unspecified + 0x4 + + + TT_FC_5 + Unspecified + 0x5 + + + TT_FC_6 + Unspecified + 0x6 + + + TT_FC_7 + Unspecified + 0x7 + + + + + RSVDDMS + Reserved field - read-only + 23 + 24 + read-only + + + RSVDSMS + Reserved field - read-only + 25 + 26 + read-only + + + RSVDLLPDSTEN + Reserved field - read-only + 27 + 27 + read-only + + + RSVDLLPSRCEN + Reserved field - read-only + 28 + 28 + read-only + + + RSVD1CTL + Reserved field - read-only + 29 + 31 + read-only + + + + + CTL1H + This register contains fields that control the DMA transfer. + 0x01C + read-write + 0x00000002 + 0x20 + + + BLOCKTS + Block Transfer Size. + 0 + 4 + + + RSVD2CTL + Reserved field - read-only + 5 + 11 + read-only + + + DONE + Done bit. + 12 + 12 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CFG1L + This register contains fields that configure the DMA transfer. + 0x040 + read-write + 0x00000E20 + 0x20 + + + RSVDCFG + Reserved field - read-only + 0 + 4 + read-only + + + CHPRIOR + Channel Priority. + 5 + 7 + + + CH_PRIOR_0 + Unspecified + 0x0 + + + CH_PRIOR_1 + Unspecified + 0x1 + + + CH_PRIOR_2 + Unspecified + 0x2 + + + CH_PRIOR_3 + Unspecified + 0x3 + + + CH_PRIOR_4 + Unspecified + 0x4 + + + CH_PRIOR_5 + Unspecified + 0x5 + + + CH_PRIOR_6 + Unspecified + 0x6 + + + CH_PRIOR_7 + Unspecified + 0x7 + + + + + CHSUSP + Channel Suspend. + 8 + 8 + + + NOT_SUSPENDED + Unspecified + 0x0 + + + SUSPENDED + Unspecified + 0x1 + + + + + FIFOEMPTY + Channel FIFO status. + 9 + 9 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + HSSELDST + Destination Software or Hardware Handshaking Select. + 10 + 10 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + HSSELSRC + Source Software or Hardware Handshaking Select. + 11 + 11 + + + HARDWARE_HS + Unspecified + 0x0 + + + SOFTWARE_HS + Unspecified + 0x1 + + + + + RSVDLOCKCHL + Reserved field - read-only + 12 + 13 + read-only + + + RSVDLOCKBL + Reserved field - read-only + 14 + 15 + read-only + + + RSVDLOCKCH + Reserved field - read-only + 16 + 16 + read-only + + + RSVDLOCKB + Reserved field - read-only + 17 + 17 + read-only + + + DSTHSPOL + Destination Handshaking Interface Polarity. + 18 + 18 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + SRCHSPOL + Source Handshaking Interface Polarity. + 19 + 19 + + + ACTIVE_HIGH + Unspecified + 0x0 + + + ACTIVE_LOW + Unspecified + 0x1 + + + + + MAXABRST + Maximum AMBA Burst Length. + 20 + 29 + + + RSVDRELOADSRC + Reserved field - read-only + 30 + 30 + read-only + + + RSVDRELOADDST + Reserved field- read-only + 31 + 31 + read-only + + + + + CFG1H + This register contains fields that configure the DMA transfer. + 0x044 + read-write + 0x00000004 + 0x20 + + + FCMODE + Flow Control Mode. + 0 + 0 + + + FCMODE_0 + Unspecified + 0x0 + + + FCMODE_1 + Unspecified + 0x1 + + + + + FIFOMODE + FIFO Mode Select. + 1 + 1 + + + FIFO_MODE_0 + Unspecified + 0x0 + + + FIFO_MODE_1 + Unspecified + 0x1 + + + + + PROTCTL + Protection Control bits used to drive the AHB HPROT[3:1] bus. + 2 + 4 + + + RSVDDSUPDEN + Reserved field- read-only + 5 + 5 + read-only + + + RSVDSSUPDEN + Reserved field- read-only + 6 + 6 + read-only + + + SRCPER + Source Hardware Interface. + 7 + 7 + + + RSVD1CFG + Reserved field - read-only + 8 + 10 + read-only + + + DESTPER + Destination hardware interface. + 11 + 11 + + + + + SGR1 + Source Gather register + 0x048 + read-write + 0x00000000 + 0x20 + + + SGI + Source Gather Interval. + 0 + 19 + + + SGC + Source Gather Count. + 20 + 24 + + + + + + INT + Unspecified + I3CCORE_DMA_INT + read-write + 0x2C0 + + RAWTFR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x000 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntTfr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWBLOCK + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x008 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntBlock Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWSRCTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x010 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntSrcTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWDSTTRAN + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x018 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntDstTran Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RAWERR + Interrupt events are stored in this Raw Interrupt Status register before masking. + 0x020 + read-write + 0x00000000 + 0x20 + + + RAW + Raw Status for IntErr Interrupt + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSTFR + Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x028 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntTfr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSBLOCK + Channel Block complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x030 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntBlock Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSSRCTRAN + Channel Source Transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x038 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntSrcTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSDSTTRAN + Channel destination transaction complete interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x040 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntDstTran Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + STATUSERR + Channel Error interrupt event from all channels is stored in this Interrupt Status register after masking. + 0x048 + read-write + 0x00000000 + 0x20 + + + STATUS + Status for IntErr Interrupt + 0 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + MASKTFR + The contents of the Raw Status register RawTfr is masked with the contents of the Mask register MaskTfr. + 0x050 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntTfr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKTFR + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKBLOCK + The contents of the Raw Status register RawBlock is masked with the contents of the Mask register MaskBlock. + 0x058 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntBlock Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKBLOCK + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKSRCTRAN + The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask register MaskSrcTran. + 0x060 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntSrcTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKSRCTRAN + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKDSTTRAN + The contents of the Raw Status register RawDstTran is masked with the contents of the Mask register MaskDstTran. + 0x068 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntDstTran Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKDSTTRAN + Reserved field - read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MASKERR + The contents of the Raw Status register RawErr is masked with the contents of the Mask register MaskErr. + 0x070 + read-write + 0x00000000 + 0x20 + + + INTMASK + Mask for IntErr Interrupt + 0 + 1 + + + MASK + Unspecified + 0x0 + + + UNMASK + Unspecified + 0x1 + + + + + RSVDMASKERR + Reserved field- read-only + 2 + 7 + read-only + + + INTMASKWE + Interrupt Mask Write Enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CLEARTFR + Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x078 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntTfr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARBLOCK + Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x080 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntBlock Interrupt + 0 + 1 + write-only + + + + + CLEARSRCTRAN + Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x088 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntSrcTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARDSTTRAN + Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x090 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntDstTran Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + CLEARERR + Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the corresponding location in the this registers. + 0x098 + read-write + 0x00000000 + 0x20 + + + CLEAR + Clear for IntErr Interrupt + 0 + 1 + write-only + + + NOT_CLEAR + Unspecified + 0x0 + + + CLEAR + Unspecified + 0x1 + + + + + + + STATUSINT + The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TFR + OR of the contents of StatusTfr register + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + BLOCK + OR of the contents of StatusBlock register + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + SRCT + OR of the contents of StatusSrcTran + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DSTT + OR of the contents of StatusDstTran + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + ERR + OR of the contents of StatusErr + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + + SWHANDSHAKE + Unspecified + I3CCORE_DMA_SWHANDSHAKE + read-write + 0x368 + + REQSRCREG + A bit is assigned for each channel in this register. + 0x000 + read-write + 0x00000000 + 0x20 + + + SRCREQ + Source Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCREQWE + Source Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + REQDSTREG + A bit is assigned for each channel in this register. + 0x008 + read-write + 0x00000000 + 0x20 + + + DSTREQ + Destination Software Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDREQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTREQWE + Destination Software Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQSRCREG + A bit is assigned for each channel in this register. + 0x010 + read-write + 0x00000000 + 0x20 + + + SRCSGLREQ + Source Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQSRCREG + Reserved field - read-only + 2 + 7 + read-only + + + SRCSGLREQWE + Source Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SGLRQDSTREG + A bit is assigned for each channel in this register. + 0x018 + read-write + 0x00000000 + 0x20 + + + DSTSGLREQ + Destination Single Transaction Request + 0 + 1 + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RSVDSGLRQDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + DSTSGLREQWE + Destination Single Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTSRCREG + A bit is assigned for each channel in this register. + 0x020 + read-write + 0x00000000 + 0x20 + + + LSTSRC + Source Last Transaction Request register + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTSRCREG + Reserved field- read-only + 2 + 7 + read-only + + + LSTSRCWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + LSTDSTREG + A bit is assigned for each channel in this register. + 0x028 + read-write + 0x00000000 + 0x20 + + + LSTDST + Destination Last Transaction Request + 0 + 1 + + + NOT_LAST + Unspecified + 0x0 + + + LAST + Unspecified + 0x1 + + + + + RSVDLSTDSTREG + Reserved field - read-only + 2 + 7 + read-only + + + LSTDSTWE + Source Last Transaction Request write enable + 8 + 9 + write-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + + MISC + Unspecified + I3CCORE_DMA_MISC + read-write + 0x398 + + DMACFGREG + This register is used to enable the DW_ahb_dmac, which must be done before any channel activity can begin. + 0x000 + read-write + 0x00000000 + 0x20 + + + DMAEN + DW_ahb_dmac Enable bit. + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + CHENREG + This is the DW_ahb_dmac Channel Enable Register. + 0x008 + read-write + 0x00000000 + 0x20 + + + CHEN + Channel Enable. + 0 + 1 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + RSVDCHENREG + Reserved field - read-only + 2 + 7 + read-only + + + CHENWE + Channel enable register + 8 + 9 + write-only + + + + + DMAIDREG + This is the DW_ahb_dmac ID register, which is a read-only register that reads back the coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. + 0x010 + read-write + 0x00000000 + 0x20 + + + DMAID + Hardcoded DW_ahb_dmac peripheral ID. + 0 + 31 + read-only + + + + + DMATESTREG + This register is used to put the AHB slave interface into test mode, during which the readback value of the writable registers match the value written, assuming the DW_ahb_dmac configuration has not optimized the same registers. + 0x018 + read-write + 0x00000000 + 0x20 + + + TESTSLVIF + DMA Test register + 0 + 0 + + + NORMAL_MODE + Unspecified + 0x0 + + + TEST_MODE + Unspecified + 0x1 + + + + + + + DMALPTIMEOUTREG + This register holds the timeout value of Low Power Counter. + 0x020 + read-write + 0x00000008 + 0x20 + + + DMALPTIMEOUT + This field holds timeout value of low power counter register. + 0 + 3 + + + + + DMACOMPPARAMS6L + DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about the component parameter settings for Channel 7. + 0x034 + read-write + 0x00000000 + 0x20 + + + CH7DTW + The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. + 0 + 2 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + DTW_8 + Unspecified + 0x1 + + + DTW_16 + Unspecified + 0x2 + + + DTW_32 + Unspecified + 0x3 + + + DTW_64 + Unspecified + 0x4 + + + DTW_128 + Unspecified + 0x5 + + + DTW_256 + Unspecified + 0x6 + + + + + CH7STW + The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. + 3 + 5 + read-only + + + NO_HARDCODE + Unspecified + 0x0 + + + STW_8 + Unspecified + 0x1 + + + STW_16 + Unspecified + 0x2 + + + STW_32 + Unspecified + 0x3 + + + STW_64 + Unspecified + 0x4 + + + STW_128 + Unspecified + 0x5 + + + STW_256 + Unspecified + 0x6 + + + + + CH7STATDST + The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7STATSRC + The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7DSTSCAEN + The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7SRCGATEN + The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7LOCKEN + The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7MULTIBLKEN + The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7CTLWBEN + The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH7HCLLP + The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH7FC + The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH7MAXMULTSIZE + The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH7DMS + The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7LMS + The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7SMS + The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH7FIFODEPTH + The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5L + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x038 + read-write + 0x00000000 + 0x20 + + + CH6DTW + The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STW + The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH6STATDST + The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6STATSRC + The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6DSTSCAEN + The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6SRCGATEN + The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6LOCKEN + The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6MULTIBLKEN + The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6CTLWBEN + The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH6HCLLP + The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH6FC + The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH6MAXMULTSIZE + The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH6DMS + The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6LMS + The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6SMS + The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH6FIFODEPTH + The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + IFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS5H + DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about the component parameter settings for Channel 5 and Channel 6. + 0x03C + read-write + 0x00000000 + 0x20 + + + CH5DTW + The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STW + The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH5STATDST + The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5STATSRC + The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5DSTSCAEN + The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5SRCGATEN + The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5LOCKEN + The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5MULTIBLKEN + The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5CTLWBEN + The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH5HCLLP + The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH5FC + The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH5MAXMULTSIZE + The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH5DMS + The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5LMS + The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5SMS + The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH5FIFODEPTH + The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4L + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x040 + read-write + 0x00000000 + 0x20 + + + CH4DTW + The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STW + The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH4STATDST + The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4STATSRC + The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4DSTSCAEN + The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4SRCGATEN + The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4LOCKEN + The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4MULTIBLKEN + The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4CTLWBEN + The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH4HCLLP + The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH4FC + The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH4MAXMULTSIZE + The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH4DMS + The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4LMS + The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4SMS + The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH4FIFODEPTH + The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS4H + DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about the component parameter settings for Channel 3 and Channel 4. + 0x044 + read-write + 0x00000000 + 0x20 + + + CH3DTW + The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STW + The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH3STATDST + The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3STATSRC + The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3DSTSCAEN + The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3SRCGATEN + The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3LOCKEN + The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3MULTIBLKEN + The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3CTLWBEN + The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH3HCLLP + The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH3FC + The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH3MAXMULTSIZE + The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH3DMS + The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3LMS + The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3SMS + The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH3FIFODEPTH + The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3L + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x048 + read-write + 0x00000000 + 0x20 + + + CH2DTW + The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STW + The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH2STATDST + The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2STATSRC + The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2DSTSCAEN + The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2SRCGATEN + The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2LOCKEN + The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2MULTIBLKEN + The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2CTLWBEN + The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH2HCLLP + The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH2FC + The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH2MAXMULTSIZE + The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH2DMS + The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH2LMS + The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2SMS + The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMALE + Unspecified + 0x4 + + + + + CH2FIFODEPTH + The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS3H + DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about the component parameter settings for Channel 1 and Channel 2. + 0x04C + read-write + 0x1109A203 + 0x20 + + + CH1DTW + The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STW + The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH1STATDST + The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1STATSRC + The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1DSTSCAEN + The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1SRCGATEN + The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1LOCKEN + The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1MULTIBLKEN + The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1CTLWBEN + The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH1HCLLP + The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH1FC + The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH1MAXMULTSIZE + The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH1DMS + The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1LMS + The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1SMS + The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH1FIFODEPTH + The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2L + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x050 + read-write + 0x13016118 + 0x20 + + + CH0DTW + The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. + 0 + 2 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STW + The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. + 3 + 5 + read-only + + + TRANS_WIDTH_PROGRAMMABLE + Unspecified + 0x0 + + + TRANS_WIDTH_8 + Unspecified + 0x1 + + + TRANS_WIDTH_16 + Unspecified + 0x2 + + + TRANS_WIDTH_32 + Unspecified + 0x3 + + + TRANS_WIDTH_64 + Unspecified + 0x4 + + + TRANS_WIDTH_128 + Unspecified + 0x5 + + + TRANS_WIDTH_256 + Unspecified + 0x6 + + + + + CH0STATDST + The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. + 6 + 6 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0STATSRC + The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. + 7 + 7 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0DSTSCAEN + The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. + 8 + 8 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0SRCGATEN + The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. + 9 + 9 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0LOCKEN + The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. + 10 + 10 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0MULTIBLKEN + The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. + 11 + 11 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0CTLWBEN + The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. + 12 + 12 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + CH0HCLLP + The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. + 13 + 13 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + HARDCODED + Unspecified + 0x1 + + + + + CH0FC + The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. + 14 + 15 + read-only + + + FC_DMA + Unspecified + 0x0 + + + FC_SRC + Unspecified + 0x1 + + + FC_DST + Unspecified + 0x2 + + + FC_ANY + Unspecified + 0x3 + + + + + CH0MAXMULTSIZE + The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. + 16 + 18 + read-only + + + MAX_MULT_SIZE_4 + Unspecified + 0x0 + + + MAX_MULT_SIZE_8 + Unspecified + 0x1 + + + MAX_MULT_SIZE_16 + Unspecified + 0x2 + + + MAX_MULT_SIZE_32 + Unspecified + 0x3 + + + MAX_MULT_SIZE_64 + Unspecified + 0x4 + + + MAX_MULT_SIZE_128 + Unspecified + 0x5 + + + MAX_MULT_SIZE_256 + Unspecified + 0x6 + + + + + CH0DMS + The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. + 19 + 21 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0LMS + The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. + 22 + 24 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0SMS + The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. + 25 + 27 + read-only + + + MASTER_1 + Unspecified + 0x0 + + + MASTER_2 + Unspecified + 0x1 + + + MASTER_3 + Unspecified + 0x2 + + + MASTER_4 + Unspecified + 0x3 + + + PROGRAMMABLE + Unspecified + 0x4 + + + + + CH0FIFODEPTH + The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. + 28 + 30 + read-only + + + FIFO_DEPTH_8 + Unspecified + 0x0 + + + FIFO_DEPTH_16 + Unspecified + 0x1 + + + FIFO_DEPTH_32 + Unspecified + 0x2 + + + FIFO_DEPTH_64 + Unspecified + 0x3 + + + FIFO_DEPTH_128 + Unspecified + 0x4 + + + FIFO_DEPTH_256 + Unspecified + 0x5 + + + + + + + DMACOMPPARAMS2H + DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about the component parameter settings. + 0x054 + read-write + 0x00000000 + 0x20 + + + CHOMULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant parameter. + 0 + 3 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH1MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant parameter. + 4 + 7 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH2MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant parameter. + 8 + 11 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH3MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant parameter. + 12 + 15 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH4MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant parameter. + 16 + 19 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH5MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant parameter. + 20 + 23 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH6MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant parameter. + 24 + 27 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + CH7MULTIBLKTYPE + The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant parameter. + 28 + 31 + read-only + + + PROGRAMMABLE + Unspecified + 0x0 + + + CONT_RELOAD + Unspecified + 0x1 + + + RELOAD_CONT + Unspecified + 0x2 + + + RELOAD_RELOAD + Unspecified + 0x3 + + + CONT_LLP + Unspecified + 0x4 + + + RELOAD_LLP + Unspecified + 0x5 + + + CNT_LLP + Unspecified + 0x6 + + + LLP_RELOAD + Unspecified + 0x7 + + + LLP_LLP + Unspecified + 0x8 + + + + + + + DMACOMPPARAMS1L + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x058 + read-write + 0x33333333 + 0x20 + + + CHOMAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant parameter. + 0 + 3 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH1MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant parameter. + 4 + 7 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH2MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant parameter. + 8 + 11 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH3MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant parameter. + 12 + 15 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH4MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant parameter. + 16 + 19 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH5MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant parameter. + 20 + 23 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH6MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant parameter. + 24 + 27 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + CH7MAXBLKSIZE + The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant parameter. + 28 + 31 + read-only + + + MAX_BLOCK_SIZE_3 + Unspecified + 0x0 + + + MAX_BLOCK_SIZE_7 + Unspecified + 0x1 + + + MAX_BLOCK_SIZE_15 + Unspecified + 0x2 + + + MAX_BLOCK_SIZE_31 + Unspecified + 0x3 + + + MAX_BLOCK_SIZE_63 + Unspecified + 0x4 + + + MAX_BLOCK_SIZE_127 + Unspecified + 0x5 + + + MAX_BLOCK_SIZE_255 + Unspecified + 0x6 + + + MAX_BLOCK_SIZE_511 + Unspecified + 0x7 + + + MAX_BLOCK_SIZE_1023 + Unspecified + 0x8 + + + MAX_BLOCK_SIZE_2047 + Unspecified + 0x9 + + + MAX_BLOCK_SIZE_4095 + Unspecified + 0xA + + + + + + + DMACOMPPARAMS1H + DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about the component parameter settings. + 0x05C + read-write + 0x3120090C + 0x20 + + + BIGENDIAN + The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. + 0 + 0 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + INTRIO + The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. + 1 + 2 + read-only + + + ALL_INT + Unspecified + 0x0 + + + TYPE_INT + Unspecified + 0x1 + + + COMBINED_INT + Unspecified + 0x2 + + + + + MAXABRST + The value of this register is derived from the DMAH_MABRST coreConsultant parameter. + 3 + 3 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + RSVDDMACOMPPARAMS1 + Reserved field- read-only + 4 + 7 + read-only + + + NUMCHANNELS + The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. + 8 + 10 + read-only + + + NUM_CHANNEL_1 + Unspecified + 0x0 + + + NUM_CHANNEL_2 + Unspecified + 0x1 + + + NUM_CHANNEL_3 + Unspecified + 0x2 + + + NUM_CHANNEL_4 + Unspecified + 0x3 + + + NUM_CHANNEL_5 + Unspecified + 0x4 + + + NUM_CHANNEL_6 + Unspecified + 0x5 + + + NUM_CHANNEL_7 + Unspecified + 0x6 + + + NUM_CHANNEL_8 + Unspecified + 0x7 + + + + + NUMMASTERINT + The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. + 11 + 12 + read-only + + + NUM_MST_INTERFACE_1 + Unspecified + 0x0 + + + NUM_MST_INTERFACE_2 + Unspecified + 0x1 + + + NUM_MST_INTERFACE_3 + Unspecified + 0x2 + + + NUM_MST_INTERFACE_4 + Unspecified + 0x3 + + + + + SHDATAWIDTH + The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. + 13 + 14 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M4HDATAWIDTH + The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. + 15 + 16 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M3HDATAWIDTH + The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. + 17 + 18 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M2HDATAWIDTH + The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. + 19 + 20 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + M1HDATAWIDTH + The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. + 21 + 22 + read-only + + + DATA_BUS_WIDTH_32 + Unspecified + 0x0 + + + DATA_BUS_WIDTH_64 + Unspecified + 0x1 + + + DATA_BUS_WIDTH_128 + Unspecified + 0x2 + + + DATA_BUS_WIDTH_256 + Unspecified + 0x3 + + + + + NUMHSINT + The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. + 23 + 27 + read-only + + + HS_INTERFACE_0 + Unspecified + 0x00 + + + HS_INTERFACE_1 + Unspecified + 0x01 + + + HS_INTERFACE_2 + Unspecified + 0x02 + + + HS_INTERFACE_3 + Unspecified + 0x03 + + + HS_INTERFACE_4 + Unspecified + 0x04 + + + HS_INTERFACE_5 + Unspecified + 0x05 + + + HS_INTERFACE_6 + Unspecified + 0x06 + + + HS_INTERFACE_7 + Unspecified + 0x07 + + + HS_INTERFACE_8 + Unspecified + 0x08 + + + HS_INTERFACE_9 + Unspecified + 0x09 + + + HS_INTERFACE_a + Unspecified + 0x0A + + + HS_INTERFACE_b + Unspecified + 0x0B + + + HS_INTERFACE_c + Unspecified + 0x0C + + + HS_INTERFACE_d + Unspecified + 0x0D + + + HS_INTERFACE_e + Unspecified + 0x0E + + + HS_INTERFACE_f + Unspecified + 0x0F + + + HS_INTERFACE_10 + Unspecified + 0x10 + + + + + ADDENCODEDPARAMS + The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. + 28 + 28 + read-only + + + FALSE + Unspecified + 0x0 + + + TRUE + Unspecified + 0x1 + + + + + STATICENDIANSELECT + The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant parameter. + 29 + 29 + read-only + + + + + DMACOMPSID0 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the component type. + 0x060 + read-write + 0x44571110 + 0x20 + + + DMACOMPTYPE + DMA Component Type Number = `h44571110. + 0 + 31 + read-only + + + + + DMACOMPSID1 + This is the DW_ahb_dmac Component Version register, which is a read-only register that specifies the version of the packaged component. + 0x064 + read-write + 0x3232322A + 0x20 + + + DMACOMPVERSION + DMA Component Version. + 0 + 31 + read-only + + + + + + + + + GLOBAL_I3CCORE121_NS + I3CCORE 1 + 0x2FBE1000 + + + + + GLOBAL_DMU120_NS + DMU 0 + 0x2FBEF800 + DMU + + + + 0 + 0x1000 + registers + + DMU + 0x20 + + + DMUCR + DMU Core Release + 0x3C0 + read-only + 0x00000000 + 0x20 + + + REL + Core Release + 1 + 1 + + + STEP + Step of Core Release + 2 + 2 + + + SUBSTEP + Sub-step of Core Release + 3 + 3 + + + YEAR + Time Stamp Year + 4 + 4 + + + MON + Time Stamp Month + 6 + 6 + + + DAY + Time Stamp Day + 8 + 8 + + + + + DMUI + DMU Internals + 0x3C4 + read-write + 0x00070000 + 0x20 + + + TXR + TX Service Request line of DMU + 0 + 0 + + + NotRequested + No TX DMA service requested + 0x0 + + + Requested + TX DMA Service requested + 0x1 + + + + + RX0R + RX0 Service Request line of DMU + 1 + 1 + + + NotRequested + No RX0 DMA service requested + 0x0 + + + Requested + RX0 DMA Service requested + 0x1 + + + + + RX1R + RX1 Service Request line of DMU + 2 + 2 + + + NotRequested + No RX1 DMA service requested + 0x0 + + + Requested + RX1 DMA Service requested + 0x1 + + + + + TXER + TX Event Service Request line of DMU + 3 + 3 + + + NotRequested + No TX Event DMA service requested + 0x0 + + + Requested + TX Event DMA Service requested + 0x1 + + + + + TFQPIP + TX FIFO/Queue Put Index Previous + 8 + 12 + + + ENA + DMU is enabled + 15 + 15 + + + Disabled + DMU is disabled + 0x0 + + + Enabled + DMU is enabled and can process DMA data + 0x1 + + + + + DEHS + Detect Element Handler State + 16 + 18 + + + DTX + Detect DMU Element Service + 20 + 20 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX0 + Detect DMU Element Service + 21 + 21 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DRX1 + Detect DMU Element Service + 22 + 22 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + DTXE + Detect DMU Element Service + 23 + 23 + + + Disabled + Queueing of DMU Element does not activate interrupt flag + 0x0 + + + Enabled + Queueing of DMU Element will activate interrupt flag when DMUI.EHS = DMUI.DEHS + 0x1 + + + + + EHS + Element Handler State + 24 + 26 + + + wait4cce + wait for bit MCAN:CCCR.CCE getting zero + 0x0 + + + wait4sa + wait for Start Address + 0x1 + + + wait4ta + wait for Trigger Address + 0x2 + + + transfer + wait for transfer of Element word + 0x3 + + + ack2mcan + acknowledge to MCAN + 0x4 + + + recovery + exception recovery + 0x5 + + + + + TX + Actual DMU Element Service + 28 + 28 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX0 + Actual DMU Element Service + 29 + 29 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + RX1 + Actual DMU Element Service + 30 + 30 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + TXE + Actual DMU Element Service + 31 + 31 + + + NotServed + DMU Virtual Buffer is currently not served + 0x0 + + + Served + DMU Virtual Buffer is currently served + 0x1 + + + + + + + DMUQC + DMU Queueing Counter + 0x3C8 + read-write + 0x00000000 + 0x20 + + + TXEEC + TX Element Enqueueing Counter + 0 + 7 + + + RX0EDC + RX0 Element Dequeueing Counter + 8 + 15 + + + RX1EDC + RX1 Element Dequeueing Counter + 16 + 23 + + + TXEEDC + TX Event Element Dequeueing Counter + 24 + 31 + + + + + DMUIR + DMU Interrupt Register + 0x3CC + read-write + 0x00000000 + 0x20 + + + TXENSA + TX Element Not Start Address + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal write access + 0x0 + + + Generated + Write to TX Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEIE + TX Element Illegal Enqueueing + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal enqueueing + 0x0 + + + Generated + Start of enqueueing without request detected, exception recovery started. + 0x1 + + + + + TXEIAS + TX Element Illegal Access Sequence + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEIDLC + TX Element Illegal DLC + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal DLC detected + 0x0 + + + Generated + DLC exceeds Tx Buffer element size of MCAN, exception recovery started. + 0x1 + + + + + TXEWATA + TX Element Write After Trigger Address + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write after Trigger Address + 0x0 + + + Generated + Write after Trigger address detected + 0x1 + + + + + TXEIR + TX Element Illegal Read + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read access + 0x0 + + + Generated + Illegal read access to DMU TX Element section detected, exception recovery started. + 0x1 + + + + + TXEE + A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx message enqueued + 0x0 + + + Generated + Tx message successfully enqueued + 0x1 + + + + + RX0ENSA + RX0 Element Not Start Address + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX0 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX0EID + RX0 Element Illegal Dequeueing + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX0EIAS + RX0 Element Illegal Access Sequence + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX0EIW + RX0 Element Illegal Write + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX0 Element detected, exception recovery started. + 0x1 + + + + + RX0ED + RX0 Element Dequeued + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX0EIO + RX0 Element Illegal Overwrite by timestamp + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + BEU + Bus Error Uncorrected + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + RX1ENSA + RX1 Element Not Start Address + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from RX1 Element begins without using start address, exception recovery started. + 0x1 + + + + + RX1EID + RX1 Element Illegal Dequeueing + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started, + 0x1 + + + + + RX1EIAS + RX0 Element Illegal Access Sequence + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + RX1EIW + RX1 Element Illegal Write + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU RX1 Element detected, exception recovery started. + 0x1 + + + + + RX1ED + RX0 Element Dequeued + 20 + 20 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx message dequeued + 0x0 + + + Generated + Rx message successfully dequeued + 0x1 + + + + + RX1EIO + RX1 Element Illegal Overwrite by timestamp + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal overwrite detected + 0x0 + + + Generated + DMU has internally overwritten the last element word of a SYNC message + 0x1 + + + + + TXEENSA + TX Event Element Not Start Address + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal read access + 0x0 + + + Generated + Read from TX Event Element begins without using start address, exception recovery started. + 0x1 + + + + + TXEEID + TX Event Element Illegal Dequeueing + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal dequeueing + 0x0 + + + Generated + Start of dequeueing without request detected, exception recovery started. + 0x1 + + + + + TXEEIAS + TX Event Element Illegal Access Sequence + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No illegal addressing sequence detected + 0x0 + + + Generated + Accesses are not strictly linear to ascending and consecutive addresses, exception recovery started. + 0x1 + + + + + TXEEIW + TX Event Element Illegal Write + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No write access detected + 0x0 + + + Generated + Illegal write access to DMU TX Event Element detected, exception recovery started. + 0x1 + + + + + TXEED + TX Event Element Dequeued + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No TX Event Element dequeued + 0x0 + + + Generated + TX Event Element successfully dequeued + 0x1 + + + + + DT + Debug Trigger + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Debug point not reached + 0x0 + + + Generated + Debug point reached + 0x1 + + + + + IAC + Illegal Access while in Configuration mode + 30 + 30 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Illegal Access while CCE mode + 0x0 + + + Generated + Illegal Access while CCE mode + 0x1 + + + + + + + DMUIE + DMU Interrupt Enable + 0x3D0 + read-write + 0x00000000 + 0x20 + + + TXENSAE + TX Element Not Start Address Enable + 0 + 0 + + + Disabled + Flag does not activate the interrupt line DMU + 0x0 + + + Enabled + the interrupt line DMU will be activated + 0x1 + + + + + + + DMUC + DMU Configuration + 0x3D4 + read-write + 0x00000000 + 0x20 + + + TTS + Transfer Timestamp + 0 + 0 + + + Disabled + No timestamp will be transferred via DMU Virtual Buffer + 0x0 + + + Enabled + Timestamp of message will be transferred from TSU via DMU Virtual Buffer + 0x1 + + + + + + + + + GLOBAL_MCAN120_NS + MCAN 0 + 0x2FBEF800 + GLOBAL_DMU120_NS + MCAN + + + + 0 + 0x1000 + registers + + MCAN + 0x20 + + + ENDN + Endian Register + 0x004 + read-only + 0x00000000 + 0x20 + + + ETV + Endianness Test Value + 0 + 31 + + + + + DBTP + Data Bit Timing and Prescaler Register + 0x00C + read-write + 0x00000000 + 0x20 + + + DSJW + Data (Re)Synchronization Jump Width + 0 + 3 + + + DTSEG2 + Data time segment after sample point + 4 + 7 + + + DTSEG1 + Data time segment before sample point + 8 + 12 + + + DBRP + Data Bit Rate Prescaler + 16 + 20 + + + TDC + Transmitter Delay Compensation + 23 + 23 + + + Disabled + Unspecified + 0x0 + + + Enabled + Unspecified + 0x1 + + + + + + + TEST + Test Register + 0x010 + read-write + 0x00000000 + 0x20 + + + LBCK + Loop Back Mode + 4 + 4 + + + Disabled + Loop Back Mode is disabled + 0x0 + + + Enabled + Loop Back Mode is enabled + 0x1 + + + + + TX + Control of Transmit Pin + 5 + 6 + + + CanCore + controlled by the CAN Core, updated at the end of the CAN bit time + 0x0 + + + Monitored + Sample Point can be monitored at pin m_can_tx + 0x1 + + + Dominant + Dominant (0) level at pin m_can_tx + 0x2 + + + Recessive + Recessive (1) at pin m_can_tx + 0x3 + + + + + RX + Receive Pin + 7 + 7 + + + Dominant + The CAN bus is dominant (m_can_rx = 0) + 0x0 + + + Recessive + The CAN bus is recessive (m_can_rx = '1') + 0x1 + + + + + TXBNP + Tx Buffer Number Prepared + 8 + 12 + + + PVAL + Prepared Valid + 13 + 13 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + TXBNS + Tx Buffer Number Started + 16 + 20 + + + SVAL + Started Valid + 21 + 21 + + + NotValid + Value of TXBNP not valid + 0x0 + + + Valid + Value of TXBNP valid + 0x1 + + + + + + + RWD + RAM Watchdog + 0x014 + read-write + 0x00000000 + 0x20 + + + WDC + Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is + disabled. + 0 + 7 + + + WDV + Actual Message RAM Watchdog Counter Value. + 8 + 15 + + + + + CCCR + CC Control Register + 0x018 + read-write + 0x00000000 + 0x20 + + + INIT + Initialization + 0 + 0 + + + Normal + Normal Operation + 0x0 + + + Initialization + Initialization is started + 0x1 + + + + + CCE + Configuration Change Enable + 1 + 1 + + + Disabled + The CPU has no write access to the protected configuration registers + 0x0 + + + Enabled + The CPU has write access to the protected configuration registers (while CCCR.INIT = '1') + 0x1 + + + + + ASM + Restricted Operation Mode + 2 + 2 + + + Disabled + Normal CAN operation + 0x0 + + + Enabled + Restricted Operation Mode active + 0x1 + + + + + CSA + Clock Stop Acknowledge + 3 + 3 + + + Disabled + No clock stop acknowledged + 0x0 + + + Enabled + MCAN may be set in power down by stopping m_can_hclk and m_can_cclk + 0x1 + + + + + CSR + Clock Stop Request + 4 + 4 + + + Disabled + No clock stop is requested + 0x0 + + + Enabled + Clock stop requested. + 0x1 + + + + + MON + Bus Monitoring Mode + 5 + 5 + + + Disabled + Bus Monitoring Mode is disabled + 0x0 + + + Enabled + Bus Monitoring Mode is enabled + 0x1 + + + + + DAR + Disable Automatic Retransmission + 6 + 6 + + + Enabled + Automatic retransmission of messages not transmitted successfully enabled + 0x0 + + + Disabled + Automatic retransmission disabled + 0x1 + + + + + TEST + Test Mode Enable + 7 + 7 + + + Disabled + Normal operation, register TEST holds reset values + 0x0 + + + Enabled + Test Mode, write access to register TEST enabled + 0x1 + + + + + FDOE + FD Operation Enable + 8 + 8 + + + Disabled + FD operation disabled + 0x0 + + + Enabled + FD operation enabled + 0x1 + + + + + BRSE + Bit Rate Switch Enable + 9 + 9 + + + Disabled + Bit rate switching for transmissions disabled + 0x0 + + + Enabled + Bit rate switching for transmissions enabled + 0x1 + + + + + WMM + Wide Message Marker + 11 + 11 + + + Disabled + 8-bit Message Marker used + 0x0 + + + Enabled + 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 0x1 + + + + + PXHD + Protocol Exception Handling Disable + 12 + 12 + + + Enabled + Protocol exception handling enabled + 0x0 + + + Disabled + Protocol exception handling disabled + 0x1 + + + + + EFBI + Edge Filtering during Bus Integration + 13 + 13 + + + Disabled + Edge filtering disabled + 0x0 + + + Enabled + Two consecutive dominant tq required to detect an edge for hard synchronization + 0x1 + + + + + TXP + Transmit Pause + 14 + 14 + + + Disabled + Transmit pause disabled + 0x0 + + + Enabled + Transmit pause enabled + 0x1 + + + + + NISO + Non ISO Operation + 15 + 15 + + + Disabled + CAN FD frame format according to ISO 11898-1:2015 + 0x0 + + + Enabled + CAN FD frame format according to Bosch CAN FD Specification V1.0 + 0x1 + + + + + + + NBTP + Nominal Bit Timing and Prescaler Register + 0x01C + read-write + 0x00000000 + 0x20 + + + NTSEG2 + Nominal Time segment after sample point + 0 + 6 + + + NTSEG1 + Nominal Time segment before sample point + 8 + 15 + + + NBRP + Nominal Bit Rate Prescaler + 16 + 24 + + + NSJW + Nominal (Re)Synchronization Jump Width + 25 + 31 + + + + + TSCC + Timestamp Counter Configuration + 0x020 + read-write + 0x00000000 + 0x20 + + + TSS + Timestamp Select + 0 + 1 + + + Zero + Timestamp counter value always 0x0000 + 0x0 + + + Increment + Timestamp counter value incremented according to TCP + 0x1 + + + External + External timestamp counter value used + 0x2 + + + Zero0 + Same as Zero + 0x3 + + + + + TCP + Timestamp Counter Prescaler + 16 + 19 + + + + + TSCV + Timestamp Counter Value + 0x024 + read-write + 0x00000000 + 0x20 + + + TSC + Timestamp Counter + 0 + 15 + + + + + TOCC + Timeout Counter Configuration + 0x028 + read-write + 0x00000000 + 0x20 + + + ETOC + Enable Timeout Counter + 0 + 0 + + + Disabled + Timeout Counter disabled + 0x0 + + + Enabled + Timeout Counter enabled + 0x1 + + + + + TOS + Timeout Select + 1 + 2 + + + Continuous + Continuous operation + 0x0 + + + TxEvent + Timeout controlled by Tx Event FIFO + 0x1 + + + RxFifo0 + Timeout controlled by Rx FIFO 0 + 0x2 + + + RxFifo1 + Timeout controlled by Rx FIFO 1 + 0x3 + + + + + TOP + Timeout Period + 16 + 31 + + + + + TOCV + Timeout Counter Value + 0x02C + read-write + 0x00000000 + 0x20 + + + TOC + Timeout Counter + 0 + 15 + + + + + ECR + Error Counter Register + 0x040 + read-write + 0x00000000 + 0x20 + + + TEC + Transmit Error Counter + 0 + 7 + + + REC + Receive Error Counter + 8 + 14 + + + RP + Receive Error Passive + 15 + 15 + + + Below + The Receive Error Counter is below the error passive level of 128 + 0x0 + + + Reached + The Receive Error Counter has reached the error passive level of 128 + 0x1 + + + + + CEL + CAN Error Logging + 16 + 23 + + + + + PSR + Protocol Status Register + 0x044 + read-write + 0x00000000 + 0x20 + + + LEC + Last Error Code + 0 + 2 + + + NoError + No error occurred since LEC has been reset by successful reception or transmission. + 0x0 + + + StuffError + More than 5 equal bits in a sequence have occurred in a part of a received message + where this is not allowed. + 0x1 + + + FormError + A fixed format part of a received frame has the wrong format. + 0x2 + + + AckError + The message transmitted by the MCAN was not acknowledged by another node. + 0x3 + + + Bit1Error + During the transmission of a message (with the exception of the arbitration field), + the device wanted to send a recessive level (bit of logical value 1), but the monitored bus + value was dominant. + 0x4 + + + Bit0Error + During the transmission of a message (or acknowledge bit, or active error flag, or + overload flag), the device wanted to send a dominant level (data or identifier bit logical value + '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set + each time a sequence of 11 recessive bits has been monitored. This enables the CPU to + monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + dominant or continuously disturbed). + 0x5 + + + CRCError + The CRC check sum of a received message was incorrect. The CRC of an incoming + message does not match with the CRC calculated from the received data. + 0x6 + + + NoChange + Any read access to the Protocol Status Register re-initializes the LEC to '7'. + When the LEC shows the value '7', no CAN bus event was detected since the last CPU read + access to the Protocol Status Register. + 0x7 + + + + + ACT + Activity + 3 + 4 + + + Synchronizing + Node is synchronizing on CAN communication + 0x0 + + + Idle + Node is neither receiver nor tr ansmitter + 0x1 + + + Receiver + Node is operating as receiver + 0x2 + + + Transmitter + Node is operating as transmitter + 0x3 + + + + + EP + Error Passive + 5 + 5 + + + Active + The MCAN is in the Error_Active state. It normally takes part in bus communication and + sends an active error flag when an error has been detected + 0x0 + + + Passive + The MCAN is in the Error_Passive state + 0x1 + + + + + EW + Warning Status + 6 + 6 + + + Below + Both error counters are below the Error_Warning limit of 96 + 0x0 + + + Reached + At least one of error counter has reached the Error_Warning limit of 96 + 0x1 + + + + + BO + Bus_Off Status + 7 + 7 + + + On + The MCAN is not Bus_Off + 0x0 + + + Off + The MCAN is in Bus_Off state + 0x1 + + + + + DLEC + Data Phase Last Error Code + 8 + 10 + + + RESI + ESI flag of last received CAN FD Message + 11 + 11 + + + NotReceived + Last received CAN FD message did not ha ve its ESI flag set + 0x0 + + + Received + Last received CAN FD message had its ESI flag set + 0x1 + + + + + RBRS + BRS flag of last received CAN FD Message + 12 + 12 + + + NotReceived + Last received CAN FD message did not ha ve its BRS flag set + 0x0 + + + Received + Last received CAN FD message had its BRS flag set + 0x1 + + + + + RFDF + Received a CAN FD Message + 13 + 13 + + + NotReceived + Since this bit was reset by the CPU, no CAN FD message has been received + 0x0 + + + Received + Message in CAN FD format with FDF flag set has been received + 0x1 + + + + + PXE + Protocol Exception Event + 14 + 14 + + + NotTriggered + No protocol exception event occurred since last read access + 0x0 + + + Triggered + Protocol exception event occurred + 0x1 + + + + + TDCV + Transmitter Delay Compensation Value + 16 + 22 + + + + + TDCR + Transmitter Delay Compensation Register + 0x048 + read-write + 0x00000000 + 0x20 + + + TDCF + Transmitter Delay Compensation Filter Window Length + 0 + 6 + + + TDCO + Transmitter Delay Compensation SSP Offset + 8 + 14 + + + + + IR + Interrupt Register + 0x050 + read-write + 0x00000000 + 0x20 + + + RF0N + Rx FIFO 0 New Message + 0 + 0 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 0 + 0x0 + + + Generated + New message written to Rx FIFO 0 + 0x1 + + + + + RF0W + Rx FIFO 0 Watermark Reached + 1 + 1 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 fill level below watermark + 0x0 + + + Generated + Rx FIFO 0 fill level reached watermark + 0x1 + + + + + RF0F + Rx FIFO 0 Full + 2 + 2 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 0 not full + 0x0 + + + Generated + Rx FIFO 0 full + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 3 + 3 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 0 message lost + 0x0 + + + Generated + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 0x1 + + + + + RF1N + Rx FIFO 1 New Message + 4 + 4 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No new message written to Rx FIFO 1 + 0x0 + + + Generated + New message written to Rx FIFO 1 + 0x1 + + + + + RF1W + Rx FIFO 1 Watermark Reached + 5 + 5 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 fill level below watermark + 0x0 + + + Generated + Rx FIFO 1 fill level reached watermark + 0x1 + + + + + RF1F + Rx FIFO 1 Full + 6 + 6 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Rx FIFO 1 not full + 0x0 + + + Generated + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 7 + 7 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx FIFO 1 message lost + 0x0 + + + Generated + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + HPM + High Priority Message + 8 + 8 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No high priority message received + 0x0 + + + Generated + High priority message received + 0x1 + + + + + TC + Transmission Completed + 9 + 9 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission completed + 0x0 + + + Generated + Transmission completed + 0x1 + + + + + TCF + Transmission Cancellation Finished + 10 + 10 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No transmission cancellation finished + 0x0 + + + Generated + Transmission cancellation finished + 0x1 + + + + + TFE + Tx FIFO Empty + 11 + 11 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx FIFO non-empty + 0x0 + + + Generated + Tx FIFO empty + 0x1 + + + + + TEFN + Tx Event FIFO New Entry + 12 + 12 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO unchanged + 0x0 + + + Generated + Tx Handler wrote Tx Event FIFO element + 0x1 + + + + + TEFW + Tx Event FIFO Watermark Reached + 13 + 13 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO fill level below watermark + 0x0 + + + Generated + Tx Event FIFO fill level reached watermark + 0x1 + + + + + TEFF + Tx Event FIFO Full + 14 + 14 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Tx Event FIFO not full + 0x0 + + + Generated + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 15 + 15 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Tx Event FIFO element lost + 0x0 + + + Generated + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero + 0x1 + + + + + TSW + Timestamp Wraparound + 16 + 16 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timestamp counter wrap-around + 0x0 + + + Generated + Timestamp counter wrapped around + 0x1 + + + + + MRAF + Message RAM Access Failure + 17 + 17 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM access failure occurred + 0x0 + + + Generated + Message RAM access failure occurred + 0x1 + + + + + TOO + Timeout Occurred + 18 + 18 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No timeout + 0x0 + + + Generated + Timeout reached + 0x1 + + + + + DRX + Message stored to Dedicated Rx Buffer + 19 + 19 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Rx Buffer updated + 0x0 + + + Generated + At least one received message stored into an Rx Buff er + 0x1 + + + + + BEU + Bus Error Uncorrected + 21 + 21 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No read slave error detected when reading from Message RAM + 0x0 + + + Generated + Read slave error detected + 0x1 + + + + + ELO + Error Logging Overflow + 22 + 22 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + CAN Error Logging Counter did not overflow + 0x0 + + + Generated + Overflow of CAN Error Logging Counter occurred + 0x1 + + + + + EP + Error Passive + 23 + 23 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Passive status unchanged + 0x0 + + + Generated + Error_Passive status changed + 0x1 + + + + + EW + Warning Status + 24 + 24 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Error_Warning status unchanged + 0x0 + + + Generated + Error_Warning status changed + 0x1 + + + + + BO + Bus_Off Status + 25 + 25 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + Bus_Off status unchanged + 0x0 + + + Generated + Bus_Off status changed + 0x1 + + + + + WDI + Watchdog Interrupt + 26 + 26 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No Message RAM Watchdog event occurred + 0x0 + + + Generated + Message RAM Watchdog event due to missing READY + 0x1 + + + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) + 27 + 27 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in arbitration phase + 0x0 + + + Generated + Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 0x1 + + + + + PED + Protocol Error in Data Phase (Data Bit Time is used) + 28 + 28 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No protocol error in data phase + 0x0 + + + Generated + Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 0x1 + + + + + ARA + Access to Reserved Address + 29 + 29 + + + Clear + Write '1' to clear interrupt flag + 0x1 + + + NotGenerated + No access to reserved address occurred + 0x0 + + + Generated + Access to reserved address occurred + 0x1 + + + + + + + IE + Interrupt Enable + 0x054 + read-write + 0x00000000 + 0x20 + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 0 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 2 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 3 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 4 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 5 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 6 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 7 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + HPME + High Priority Message Interrupt Enable + 8 + 8 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCE + Transmission Completed Interrupt Enable + 9 + 9 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 10 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 11 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 12 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 13 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 14 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 15 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 16 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 17 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 18 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 19 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BEUE + Bus Error Uncorrected Interrupt Enable + 21 + 21 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 22 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EPE + Error Passive Interrupt Enable + 23 + 23 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + EWE + Warning Status Interrupt Enable + 24 + 24 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + BOE + Bus_Off Status Interrupt Enable + 25 + 25 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + WDIE + Watchdog Interrupt Enable + 26 + 26 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 27 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + PEDE + Protocol Error in Data Phase Enable + 28 + 28 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + ARAE + Access to Reserved Address Enable + 29 + 29 + + + Disable + Interrupt disabled. + 0x0 + + + Enable + Interrupt enabled. + 0x1 + + + + + + + ILS + Interrupt Line Select + 0x058 + read-write + 0x00000000 + 0x20 + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 0 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 2 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 3 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 4 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 5 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 6 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 7 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + HPML + High Priority Message Interrupt Line + 8 + 8 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCL + Transmission Completed Interrupt Line + 9 + 9 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 10 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 11 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 12 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 13 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 14 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 15 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 16 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 17 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + TOOL + Timeout Occurred Interrupt Line + 18 + 18 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 19 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BEUL + Bus Error Uncorrected Interrupt Line + 21 + 21 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 22 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EPL + Error Passive Interrupt Line + 23 + 23 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + EWL + Warning Status Interrupt Line + 24 + 24 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + BOL + Bus_Off Status Interrupt Line + 25 + 25 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + WDIL + Watchdog Interrupt Line + 26 + 26 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 27 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + PEDL + Protocol Error in Data Phase Line + 28 + 28 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + ARAL + Access to Reserved Address Line + 29 + 29 + + + Assigned0 + Interrupt assigned to interrupt line CORE0. + 0x0 + + + Assigned1 + Interrupt assigned to interrupt line CORE1. + 0x1 + + + + + + + ILE + Interrupt Line Enable + 0x05C + read-write + 0x00000000 + 0x20 + + + EINT0 + Enable Interrupt Line 0 + 0 + 0 + + + Disable + Interrupt line CORE0 disabled. + 0x0 + + + Enable + Interrupt line CORE0 enabled. + 0x1 + + + + + EINT1 + Enable Interrupt Line 1 + 1 + 1 + + + Disable + Interrupt line CORE1 disabled. + 0x0 + + + Enable + Interrupt line CORE1 enabled. + 0x1 + + + + + + + GFC + Global Filter Configuration + 0x080 + read-write + 0x00000000 + 0x20 + + + RRFE + Reject Remote Frames Extended + 0 + 0 + + + Filter + Filter remote frames with 29-bit extended IDs. + 0x0 + + + Reject + Reject all remote frames with 29-bit extended IDs. + 0x1 + + + + + RRFS + Reject Remote Frames Standard + 1 + 1 + + + Filter + Filter remote frames with 11-bit standard IDs. + 0x0 + + + Reject + Reject all remote frames with 11-bit standard IDs. + 0x1 + + + + + ANFE + Accept Non-matching Frames Extended + 2 + 3 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + ANFS + 4 + 5 + + + Accept0 + Accept in Rx FIFO 0. + 0x0 + + + Accept1 + Accept in Rx FIFO 1. + 0x1 + + + Reject0 + Reject in both Rx FIFOs. + 0x2 + + + Reject1 + Reject in both Rx FIFOs. + 0x3 + + + + + + + SIDFC + Standard ID Filter Configuration + 0x084 + read-write + 0x00000000 + 0x20 + + + FLSSA + Filter List Standard Start Address + 2 + 15 + + + LSS + List Size Standard + 16 + 23 + + + + + XIDFC + Extended ID Filter Configuration + 0x088 + read-write + 0x00000000 + 0x20 + + + FLESA + Filter List Extended Start Address + 2 + 15 + + + LSE + List Size Extended + 16 + 22 + + + + + XIDAM + Extended ID AND Mask + 0x090 + read-write + 0x00000000 + 0x20 + + + EIDM + Extended ID Mask + 0 + 28 + + + + + HPMS + High Priority Message Status + 0x094 + read-only + 0x00000000 + 0x20 + + + BIDX + Buffer Index + 0 + 5 + + + MSI + Message Storage Indicator + 6 + 7 + + + NotSelected + No FIFO selected. + 0x0 + + + Lost + FIFO message lost. + 0x1 + + + Stored0 + Message stored in FIFO 0. + 0x2 + + + Stored1 + Message stored in FIFO 1. + 0x3 + + + + + FIDX + Filter Index + 8 + 14 + + + FLST + Filter List + 15 + 15 + + + Standard + Standard Filter List. + 0x0 + + + Extended + Extended Filter List. + 0x1 + + + + + + + NDAT1 + New Data 1 + 0x098 + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + NDAT2 + New Data 2 + 0x09C + read-write + 0x00000000 + 0x20 + + + ND + New Data + 0 + 31 + + + NotUpdated + Rx Buffer not updated. + 0x00000000 + + + Updated + Rx Buffer updated from new message. + 0x00000001 + + + + + + + RXF0C + Rx FIFO 0 Configuration + 0x0A0 + read-write + 0x00000000 + 0x20 + + + F0SA + Rx FIFO 0 Start Address + 2 + 15 + + + F0S + Rx FIFO 0 Size + 16 + 22 + + + F0WM + Rx FIFO 0 Watermark + 24 + 30 + + + F0OM + FIFO 0 Operation Mode + 31 + 31 + + + Blocking + FIFO 0 blocking mode. + 0x0 + + + Overwrite + FIFO 0 overwrite mode. + 0x1 + + + + + + + RXF0S + Rx FIFO 0 Status + 0x0A4 + read-only + 0x00000000 + 0x20 + + + F0FL + Rx FIFO 0 Fill Leve + 0 + 6 + + + F0GI + Rx FIFO 0 Get Index + 8 + 13 + + + F0PI + Rx FIFO 0 Put Index + 16 + 21 + + + F0F + Rx FIFO 0 Full + 24 + 24 + + + NotFull + Rx FIFO 0 not full. + 0x0 + + + Full + Rx FIFO 0 full. + 0x1 + + + + + RF0L + Rx FIFO 0 Message Lost + 25 + 25 + + + NotLost + No Rx FIFO 0 message lost. + 0x0 + + + Lost + Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + 0x1 + + + + + + + RXF0A + Rx FIFO 0 Acknowledge + 0x0A8 + read-write + 0x00000000 + 0x20 + + + F0AI + Rx FIFO 0 Acknowledge Index + 0 + 5 + + + + + RXBC + Rx Buffer Configuration + 0x0AC + read-write + 0x00000000 + 0x20 + + + RBSA + Rx Buffer Start Address + 2 + 15 + + + + + RXF1C + Rx FIFO 1 Configuration + 0x0B0 + read-write + 0x00000000 + 0x20 + + + F1SA + Rx FIFO 1 Start Address + 2 + 15 + + + F1S + Rx FIFO 1 Size + 16 + 22 + + + F1WM + Rx FIFO 1 Watermark + 24 + 30 + + + F1OM + FIFO 1 Operation Mode + 31 + 31 + + + BlockingMode + FIFO 1 blocking mode + 0x0 + + + OwerwriteMode + FIFO 1 overwrite mode + 0x1 + + + + + + + RXF1S + Rx FIFO 1 Status + 0x0B4 + read-only + 0x00000000 + 0x20 + + + F1FL + Rx FIFO 1 Fill Level + 0 + 6 + + + F1GI + Rx FIFO 1 Get Index + 8 + 13 + + + F1PI + Rx FIFO 1 Put Index + 16 + 21 + + + F1F + Rx FIFO 1 Full + 24 + 24 + + + NotFull + Rx FIFO 1 not full + 0x0 + + + Full + Rx FIFO 1 full + 0x1 + + + + + RF1L + Rx FIFO 1 Message Lost + 25 + 25 + + + NoMessageLost + No Rx FIFO 1 message lost + 0x0 + + + MessageLost + Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 0x1 + + + + + DMS + Debug Message Status + 30 + 31 + + + Idle + Idle state, wait for reception of debug messages, DMA request is cleared + 0x0 + + + ReceivedMesA + Debug message A received + 0x1 + + + ReceivedMesAB + Debug messages A, B received + 0x2 + + + ReceivedMesABC + Debug messages A, B, C received, DMA request is set + 0x3 + + + + + + + RXF1A + Rx FIFO 1 Acknowledge + 0x0B8 + read-write + 0x00000000 + 0x20 + + + F1AI + Rx FIFO 1 Acknowledge Index + 0 + 5 + + + + + RXESC + Rx Buffer / FIFO Element Size Configuration + 0x0BC + read-write + 0x00000000 + 0x20 + + + F0DS + Rx FIFO 0 Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + F1DS + Rx FIFO 1 Data Field Size + 4 + 6 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + RBDS + Rx Buffer Data Field Size + 8 + 10 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBC + Tx Buffer Configuration + 0x0C0 + read-write + 0x00000000 + 0x20 + + + TBSA + Tx Buffers Start Address + 2 + 15 + + + NDTB + Number of Dedicated Transmit Buffers + 16 + 21 + + + TFQS + Transmit FIFO/Queue Size + 24 + 29 + + + TFQM + Tx FIFO/Queue Mode + 30 + 30 + + + TxFIFO + Tx FIFO operation + 0x0 + + + TxQueue + Tx Queue operation + 0x1 + + + + + + + TXFQS + Tx FIFO/Queue Status + 0x0C4 + read-only + 0x00000000 + 0x20 + + + TFFL + Tx FIFO Free Level + 0 + 5 + + + TFGI + Tx FIFO Get Index + 8 + 12 + + + TFQPI + Tx FIFO/Queue Put Index + 16 + 20 + + + TFQF + Tx FIFO/Queue Full + 21 + 21 + + + NotFull + Tx FIFO/Queue not full + 0x0 + + + Full + Tx FIFO/Queue full + 0x1 + + + + + + + TXESC + Tx Buffer Element Size Configuration + 0x0C8 + read-write + 0x00000000 + 0x20 + + + TBDS + Tx Buffer Data Field Size + 0 + 2 + + + DataField8B + 8 byte data field + 0x0 + + + DataField12B + 12 byte data field + 0x1 + + + DataField16B + 16 byte data field + 0x2 + + + DataField20B + 20 byte data field + 0x3 + + + DataField24B + 24 byte data field + 0x4 + + + DataField32B + 32 byte data field + 0x5 + + + DataField48B + 48 byte data field + 0x6 + + + DataField64B + 64 byte data field + 0x7 + + + + + + + TXBRP + Tx Buffer Request Pending + 0x0CC + read-only + 0x00000000 + 0x20 + + + TRP + Transmission Request Pending + 0 + 31 + + + NoRequest + No transmission request pending + 0x00000000 + + + Request + Transmission request pending + 0x00000001 + + + + + + + TXBAR + Tx Buffer Add Request + 0x0D0 + read-write + 0x00000000 + 0x20 + + + AR + Add Request + 0 + 31 + + + NoRequest + No transmission request added + 0x00000000 + + + Request + Transmission requested added + 0x00000001 + + + + + + + TXBCR + Tx Buffer Cancellation Request + 0x0D4 + read-write + 0x00000000 + 0x20 + + + CR + Cancellation Request + 0 + 31 + + + NoCancellation + No cancellation pending + 0x00000000 + + + Cancellation + Cancellation pending + 0x00000001 + + + + + + + TXBTO + Tx Buffer Transmission Occurred + 0x0D8 + read-only + 0x00000000 + 0x20 + + + TO + Transmission Occurred + 0 + 31 + + + NoTransmittion + No transmission occurred + 0x00000000 + + + Transmittion + Transmission occurred + 0x00000001 + + + + + + + TXBCF + Tx Buffer Cancellation Finished + 0x0DC + read-only + 0x00000000 + 0x20 + + + CF + Cancellation Finished + 0 + 31 + + + NoCancellation + No transmit buffer cancellation + 0x00000000 + + + CancellationFinished + Transmit buffer cancellation finished + 0x00000001 + + + + + + + TXBTIE + Tx Buffer Transmission Interrupt Enable + 0x0E0 + read-write + 0x00000000 + 0x20 + + + TIE + Transmission Interrupt Enable + 0 + 31 + + + Disable + Transmission interrupt disabled + 0x00000000 + + + Enable + Transmission interrupt enable + 0x00000001 + + + + + + + TXBCIE + Tx Buffer Cancellation Finished Interrupt Enable + 0x0E4 + read-write + 0x00000000 + 0x20 + + + CFIE + Cancellation Finished Interrupt Enable + 0 + 31 + + + Disable + Cancellation finished interrupt disabled + 0x00000000 + + + Enable + Cancellation finished interrupt enabled + 0x00000001 + + + + + + + TXEFC + Tx Event FIFO Configuration + 0x0F0 + read-write + 0x00000000 + 0x20 + + + EFSA + Event FIFO Start Address + 2 + 15 + + + EFS + Event FIFO Size + 16 + 21 + + + EFWM + Event FIFO Watermark + 24 + 29 + + + + + TXEFS + Tx Event FIFO Status + 0x0F4 + read-only + 0x00000000 + 0x20 + + + EFFL + Event FIFO Fill Level + 0 + 5 + + + EFGI + Event FIFO Get Index + 8 + 12 + + + EFPI + Event FIFO Put Index + 16 + 20 + + + EFF + Event FIFO Full + 24 + 24 + + + NotFull + Tx Event FIFO not full + 0x0 + + + Full + Tx Event FIFO full + 0x1 + + + + + TEFL + Tx Event FIFO Element Lost + 25 + 25 + + + NotLost + No Tx Event FIFO element lost + 0x0 + + + Lost + Tx Event FIFO element lost, also set after wr ite attempt to Tx Event FIFO of siz e zero. + 0x1 + + + + + + + TXEFA + Tx Event FIFO Acknowledge + 0x0F8 + read-write + 0x00000000 + 0x20 + + + EFAI + Event FIFO Acknowledge Index + 0 + 4 + + + + + + + GLOBAL_DMU121_NS + DMU 1 + 0x2FBF7800 + + + + + GLOBAL_MCAN121_NS + MCAN 1 + 0x2FBF7800 + GLOBAL_DMU121_NS + + + + + GLOBAL_STMDATA_NS + System Trace Macrocell data buffer 0 + 0xA0000000 + STMDATA + + + + + 0 + 0x10000000 + registers + + STMDATA + 0x20 + + + 16 + 0x1000000 + DOMAIN[%s] + Unspecified + STMDATA_DOMAIN + read-write + 0x000 + + 0x1000000 + 0x1 + DATA[%s] + Description collection: STM extended stimulus port data buffer area for domain n. NonSecure writes to this region generates trace packets with id n+96. Secure writes to this region generates trace packets with id n+32. + 0x000 + read-write + 0x00 + uint8_t + 0x8 + + + + + + + GLOBAL_STMDATA_S + System Trace Macrocell data buffer 1 + 0xA0000000 + GLOBAL_STMDATA_NS + + + + + + GLOBAL_TDDCONF_NS + TDDCONF 0 + 0xBF001000 + TDDCONF + + + + 0 + 0x1000 + registers + + TDDCONF + 0x20 + + + SYSPWRUPREQ + System power-up request + 0x400 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + DBGPWRUPREQ + Debug power-up request + 0x404 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Activate power-up request + 0 + 0 + + + NotActive + Power-up request not active + 0x0 + + + Active + Power-up request active + 0x1 + + + + + + + TRACEPORTSPEED + Trace port trace clock speed + 0x408 + read-write + 0x00000000 + 0x20 + + + SPEED + Trace clock speed + 0 + 1 + + + Speed100MHz + Speed 100MHz + 0x0 + + + Speed50MHz + Speed 50MHz + 0x1 + + + Speed25MHz + Speed 25MHz + 0x2 + + + Speed12500KHz + Speed 12.5MHz + 0x3 + + + + + + + DEBUGPOWERREQSTATUS + Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests + 0x40C + read-only + 0x00000000 + 0x20 + + + SYSPWRUPREQUESTED + System powerup request status + 0 + 0 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + DBGPWRUPREQUESTED + Debug domain powerup request status + 1 + 1 + + + NoPowerReq + Power not requested + 0x0 + + + PowerReq + Power requested + 0x1 + + + + + + + + + GLOBAL_TDDCONF_S + TDDCONF 1 + 0xBF001000 + GLOBAL_TDDCONF_NS + + + + + GLOBAL_STM_NS + System Trace Macrocell + 0xBF042000 + STM + + + + 0 + 0x1000 + registers + + STM + 0x20 + + + DMACTLR + Controls the DMA transfer request mechanism. + 0xC10 + read-write + 0x00000000 + 0x20 + + + SENS + Determines the sensitivity of the DMA request to the current buffer level in the STM + 2 + 3 + + + LT25 + Buffer is &lt;25 percent full. + 0x0 + + + LT50 + Buffer is &lt;50 percent full. + 0x1 + + + LT75 + Buffer is &lt;75 percent full. + 0x2 + + + LT100 + Buffer is &lt;100 percent full. + 0x3 + + + + + + + HEMASTR + Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. + 0xDF4 + read-only + 0x00000000 + 0x20 + + + MASTER + The STPv2 master number that hardware event traces should be associated with. + 0 + 16 + + + + + HEFEAT1R + Indicates the features of the STM. + 0xDF8 + read-only + 0x00000000 + 0x20 + + + HETER + STMHETER support + 0 + 0 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEERR + Hardware event error detection support + 2 + 2 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + HEMASTR + STMHEMASTR support + 3 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NUMHE + The number of hardware events supported by the STM + 15 + 23 + + + + + HEIDR + Indicates the features of hardware event tracing in the STM. + 0xDFC + read-only + 0x00000000 + 0x20 + + + CLASS + The CLASS field identifies the programmers model + 0 + 3 + + + HardwareEventControl + Hardware Event Control programmers model + 0x1 + + + + + CLASSREV + The CLASSREV field identifies the revision of the programmers model + 4 + 7 + + + VENDSPEC + The VENDSPEC field identifies any vendor specific modifications or mappings + 8 + 11 + + + + + TCSR + Controls the STM settings. + 0xE80 + read-write + 0x00000000 + 0x20 + + + EN + Global STM enable + 0 + 0 + + + Disabled + The STM is disabled. + 0x0 + + + Enabled + The STM is enabled. + 0x1 + + + + + TSEN + Enable or disable timestamp bundling. + 1 + 1 + + + Disabled + Time stamps are disabled. Requests for timestamp generation are ignored, and stimulus port writes selecting timestamping are treated as if it were not selected. + 0x0 + + + Enabled + Time stamps are enabled. If stimulus writes select timestamping, a timestamp is output according to STPv2. + 0x1 + + + + + SYNCEN + STMSYNCR is implemented so this value is Read As One. + 2 + 2 + + + Disabled + The STM Sync feature is disabled. + 0x0 + + + Enabled + The STM Sync feature is enabled. + 0x1 + + + + + COMPEN + Compression Enable for Stimulus Ports. + 5 + 5 + + + Disabled + Compression disabled, data transfers are transmitted at the size of the transaction. + 0x0 + + + Enabled + Compression enabled, data transfers are compressed to save bandwidth. + 0x1 + + + + + TRACEID + ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. + 16 + 22 + + + BUSY + STM is busy, for example the STM trace FIFO is not empty. + 23 + 23 + + + Ready + STM is not busy. + 0x0 + + + Busy + STM is busy. + 0x1 + + + + + + + AUXCR + Used for implementation defined STM controls. + 0xE94 + read-write + 0x00000000 + 0x20 + + + FIFOAF + FIFO Auto-flush. + 0 + 0 + + + Disabled + Auto-flush is disabled. + 0x0 + + + Enabled + Auto-flush is enabled. The STM automatically drains all data it has even if the ATB interface is not fully utilized. + 0x1 + + + + + ASYNCPE + Is ASYNC priority higher than trace? + 1 + 1 + + + Lower + ASYNC priority is always lower than trace. + 0x0 + + + Escalate + ASYNC priority escalates on second synchronization request. + 0x1 + + + + + PRIORINVDIS + Controls arbitration between AXI and HW during flush. + 2 + 2 + + + Enabled + Priority inversion, when AXI flush is finished, HW gets priority until HW flush is done. + 0x0 + + + Disabled + Priority inversion disabled, AXI always has priority over HW. + 0x1 + + + + + CLKON + Provides override control for architectural clock gate enable. + 3 + 3 + + + Disabled + No override, clock gate is controlled by the state of STM. + 0x0 + + + Enabled + Override, clock is enabled. + 0x1 + + + + + AFREADYHIGH + Provides override control for the AFREADY output + 4 + 4 + + + Disabled + No override, AFREADY is controlled by the state of STM. + 0x0 + + + Enabled + Override, AFREADY is driven HIGH. + 0x1 + + + + + + + SPFEAT1R + Indicates the features of the STM. + 0xEA0 + read-write + 0x00000000 + 0x20 + + + PROT + Indicates the implemented STM protocol. + 0 + 3 + + + STPV2 + STM implements the STPV2 protocol. + 0x1 + + + + + TS + Timestamp support. + 4 + 5 + + + Absolute + Absolute timestamps implemented. + 0x1 + + + + + TSFREQ + Timestamp frequency indication configuration. + 6 + 6 + + + NotImplemented + STMTSFREQR is read-only. + 0x0 + + + Implemented + STMTSFREQR is read-write. + 0x1 + + + + + FORCETS + Timestamp force configuration. + 7 + 7 + + + NotImplemented + STMTSSTIMR bit 0 is read-only. + 0x0 + + + Implemented + STMTSSTIMR bit 0 is read-write. + 0x1 + + + + + TRACEBUS + Trace bus support. + 10 + 13 + + + TRIGCTL + Trigger control support. + 14 + 15 + + + TSPRESCALE + Timestamp prescale support + 16 + 17 + + + NotImplemented + Timestamp prescale is not implemented. + 0x0 + + + Implemented + Timestamp prescale is implemented. + 0x1 + + + + + HWTEN + STMTCSR.HWTEN support + 18 + 19 + + + NotImplemented + STMTCSR.HWTEN is not implemented + 0x1 + + + + + SYNCEN + STMTCSR.SYNCEN support + 20 + 21 + + + ReadAsOne + STMTCSR.SYNCEN implemented but always reads as b1 + 0x2 + + + + + SWOEN + STMTCSR.SWOEN support + 22 + 23 + + + NotImplemented + STMTCSR.SWOEN not implemented + 0x1 + + + + + + + SPFEAT2R + Indicates the features of the STM. + 0xEA4 + read-write + 0x00000000 + 0x20 + + + SPTER + STMSPTER support. + 0 + 1 + + + Implemented + STMSPTER is implemented. + 0x2 + + + + + SPER + STMSPER presence. + 2 + 2 + + + Implemented + STMSPER is implemented. + 0x0 + + + NotImplemented + STMSPER is not implemented. + 0x1 + + + + + SPCOMP + Data compression on stimulus ports support. + 4 + 5 + + + Programmable + Data compression support is programmable. STMTCSR.COMPEN is implemented. + 0x3 + + + + + SPOVERRIDE + Timestamp force configuration. + 6 + 6 + + + NotImplemented + STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. + 0x0 + + + Implemented + STMSPOVERRIDER and STMSPMOVERRIDER is implemented. + 0x1 + + + + + PRIVMASK + STMPRIVMASKR support. + 7 + 8 + + + NotImplemented + STMPRIVMASKR is not implemented. + 0x1 + + + + + SPTRTYPE + Stimulus port transaction type support. + 9 + 10 + + + InvariantAndGuaranteed + Both invariant timing and guaranteed transactions are supported. + 0x2 + + + + + DSIZE + Fundamental data size. + 12 + 15 + + + Bits32 + 32-bit data. + 0x0 + + + + + SPTYPE + Stimulus port type support + 18 + 19 + + + OnlyExtended + Only extended stimulus ports are implemented. + 0x1 + + + + + + + SPFEAT3R + Indicates the features of the STM. + 0xEA8 + read-write + 0x00000000 + 0x20 + + + NUMMAST + The number of stimulus ports masters implemented, minus 1. + 0 + 6 + + + Masters128 + Example: 128 masters implemented. + 0x3F + + + + + + + ITTRIGGER + Integration Test for Cross-Trigger Outputs Register. + 0xEE8 + write-only + 0x00000000 + 0x20 + + + TRIGOUTSPTE_W + Sets the value of the TRIGOUTSPTE output in integration mode. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTSW_W + Sets the value of the TRIGOUTSW output in integration mode. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + TRIGOUTHETE_W + Sets the value of the TRIGOUTHETE output in integration mode. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ASYNCOUT_W + Sets the value of the ASYNCOUT output in integration mode. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBDATA0 + Controls the value of the ATDATAM output in integration mode. + 0xEEC + write-only + 0x00000000 + 0x20 + + + ATDATAM0_W + Sets the value of the ATDATAM[0]. + 0 + 0 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM7_W + Sets the value of the ATDATAM[7] output. + 1 + 1 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM15_W + Sets the value of the ATDATAM[15]. + 2 + 2 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM23_W + Sets the value of the ATDATAM[23]. + 3 + 3 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + ATDATAM31_W + Sets the value of the ATDATAM[31]. + 4 + 4 + + + Low + Drive logic 0 on output. + 0x0 + + + High + Drive logic 1 on output. + 0x1 + + + + + + + ITATBCTR2 + Controls the value of the ATDATAM output in integration mode. + 0xEF0 + write-only + 0x00000000 + 0x20 + + + ATREADYM_R + Reads the value of the ATREADYM input. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFVALIDM_R + Reads the value of the AFVALIDM input. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBID + Controls the value of the ATIDM output in integration mode. + 0xEF4 + write-only + 0x00000000 + 0x20 + + + ATIDM_W_0 + Sets the value of pin 0 of the ATIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_1 + Sets the value of pin 1 of the ATIDM output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_2 + Sets the value of pin 2 of the ATIDM output. + 2 + 2 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_3 + Sets the value of pin 3 of the ATIDM output. + 3 + 3 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_4 + Sets the value of pin 4 of the ATIDM output. + 4 + 4 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_5 + Sets the value of pin 5 of the ATIDM output. + 5 + 5 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATIDM_W_6 + Sets the value of pin 6 of the ATIDM output. + 6 + 6 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITATBCTR0 + Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. + 0xEF8 + write-only + 0x00000000 + 0x20 + + + ATVALIDM_W + Sets the value of the ATVALIDM output. + 0 + 0 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + AFREADYM_W + Sets the value of the AFREADYM_W output. + 1 + 1 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_0 + Sets the value of pin 0 of the ATBYTESM output. + 8 + 8 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + ATBYTESM_W_1 + Sets the value of pin 1 of the ATBYTESM output. + 9 + 9 + + + Low + Pin is at logic 0. + 0x0 + + + High + Pin is at logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the STM. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + NUMSP + This value indicates the number of stimulus ports implemented. + 0 + 16 + + + Max + Maximum 65,536 stimulus ports can be implemented. + 0x10000 + + + + + + + DEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + StimulusTrace + Peripheral is a stimulus trace source. + 0x6 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_TPIU_NS + Trace Port Interface Unit + 0xBF043000 + TPIU + + + + 0 + 0x1000 + registers + + TPIU + 0x20 + + + SUPPORTEDPORTSIZES + Each bit location is a single port size that is supported on the device. + 0x000 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates whether the TPIU supports port size of 1-bit. + 0 + 0 + + + NotSupported + Port size 1 is not supported. + 0x0 + + + Supported + Port size 1 is supported. + 0x1 + + + + + PORT_SIZE_2 + Indicates whether the TPIU supports port size of 2-bit. + 1 + 1 + + + NotSupported + Port size 2 is not supported. + 0x0 + + + Supported + Port size 2 is supported. + 0x1 + + + + + PORT_SIZE_3 + Indicates whether the TPIU supports port size of 3-bit. + 2 + 2 + + + NotSupported + Port size 3 is not supported. + 0x0 + + + Supported + Port size 3 is supported. + 0x1 + + + + + PORT_SIZE_4 + Indicates whether the TPIU supports port size of 4-bit. + 3 + 3 + + + NotSupported + Port size 4 is not supported. + 0x0 + + + Supported + Port size 4 is supported. + 0x1 + + + + + PORT_SIZE_5 + Indicates whether the TPIU supports port size of 5-bit. + 4 + 4 + + + NotSupported + Port size 5 is not supported. + 0x0 + + + Supported + Port size 5 is supported. + 0x1 + + + + + PORT_SIZE_6 + Indicates whether the TPIU supports port size of 6-bit. + 5 + 5 + + + NotSupported + Port size 6 is not supported. + 0x0 + + + Supported + Port size 6 is supported. + 0x1 + + + + + PORT_SIZE_7 + Indicates whether the TPIU supports port size of 7-bit. + 6 + 6 + + + NotSupported + Port size 7 is not supported. + 0x0 + + + Supported + Port size 7 is supported. + 0x1 + + + + + PORT_SIZE_8 + Indicates whether the TPIU supports port size of 8-bit. + 7 + 7 + + + NotSupported + Port size 8 is not supported. + 0x0 + + + Supported + Port size 8 is supported. + 0x1 + + + + + PORT_SIZE_9 + Indicates whether the TPIU supports port size of 9-bit. + 8 + 8 + + + NotSupported + Port size 9 is not supported. + 0x0 + + + Supported + Port size 9 is supported. + 0x1 + + + + + PORT_SIZE_10 + Indicates whether the TPIU supports port size of 10-bit. + 9 + 9 + + + NotSupported + Port size 10 is not supported. + 0x0 + + + Supported + Port size 10 is supported. + 0x1 + + + + + PORT_SIZE_11 + Indicates whether the TPIU supports port size of 11-bit. + 10 + 10 + + + NotSupported + Port size 11 is not supported. + 0x0 + + + Supported + Port size 11 is supported. + 0x1 + + + + + PORT_SIZE_12 + Indicates whether the TPIU supports port size of 12-bit. + 11 + 11 + + + NotSupported + Port size 12 is not supported. + 0x0 + + + Supported + Port size 12 is supported. + 0x1 + + + + + PORT_SIZE_13 + Indicates whether the TPIU supports port size of 13-bit. + 12 + 12 + + + NotSupported + Port size 13 is not supported. + 0x0 + + + Supported + Port size 13 is supported. + 0x1 + + + + + PORT_SIZE_14 + Indicates whether the TPIU supports port size of 14-bit. + 13 + 13 + + + NotSupported + Port size 14 is not supported. + 0x0 + + + Supported + Port size 14 is supported. + 0x1 + + + + + PORT_SIZE_15 + Indicates whether the TPIU supports port size of 15-bit. + 14 + 14 + + + NotSupported + Port size 15 is not supported. + 0x0 + + + Supported + Port size 15 is supported. + 0x1 + + + + + PORT_SIZE_16 + Indicates whether the TPIU supports port size of 16-bit. + 15 + 15 + + + NotSupported + Port size 16 is not supported. + 0x0 + + + Supported + Port size 16 is supported. + 0x1 + + + + + PORT_SIZE_17 + Indicates whether the TPIU supports port size of 17-bit. + 16 + 16 + + + NotSupported + Port size 17 is not supported. + 0x0 + + + Supported + Port size 17 is supported. + 0x1 + + + + + PORT_SIZE_18 + Indicates whether the TPIU supports port size of 18-bit. + 17 + 17 + + + NotSupported + Port size 18 is not supported. + 0x0 + + + Supported + Port size 18 is supported. + 0x1 + + + + + PORT_SIZE_19 + Indicates whether the TPIU supports port size of 19-bit. + 18 + 18 + + + NotSupported + Port size 19 is not supported. + 0x0 + + + Supported + Port size 19 is supported. + 0x1 + + + + + PORT_SIZE_20 + Indicates whether the TPIU supports port size of 20-bit. + 19 + 19 + + + NotSupported + Port size 20 is not supported. + 0x0 + + + Supported + Port size 20 is supported. + 0x1 + + + + + PORT_SIZE_21 + Indicates whether the TPIU supports port size of 21-bit. + 20 + 20 + + + NotSupported + Port size 21 is not supported. + 0x0 + + + Supported + Port size 21 is supported. + 0x1 + + + + + PORT_SIZE_22 + Indicates whether the TPIU supports port size of 22-bit. + 21 + 21 + + + NotSupported + Port size 22 is not supported. + 0x0 + + + Supported + Port size 22 is supported. + 0x1 + + + + + PORT_SIZE_23 + Indicates whether the TPIU supports port size of 23-bit. + 22 + 22 + + + NotSupported + Port size 23 is not supported. + 0x0 + + + Supported + Port size 23 is supported. + 0x1 + + + + + PORT_SIZE_24 + Indicates whether the TPIU supports port size of 24-bit. + 23 + 23 + + + NotSupported + Port size 24 is not supported. + 0x0 + + + Supported + Port size 24 is supported. + 0x1 + + + + + PORT_SIZE_25 + Indicates whether the TPIU supports port size of 25-bit. + 24 + 24 + + + NotSupported + Port size 25 is not supported. + 0x0 + + + Supported + Port size 25 is supported. + 0x1 + + + + + PORT_SIZE_26 + Indicates whether the TPIU supports port size of 26-bit. + 25 + 25 + + + NotSupported + Port size 26 is not supported. + 0x0 + + + Supported + Port size 26 is supported. + 0x1 + + + + + PORT_SIZE_27 + Indicates whether the TPIU supports port size of 27-bit. + 26 + 26 + + + NotSupported + Port size 27 is not supported. + 0x0 + + + Supported + Port size 27 is supported. + 0x1 + + + + + PORT_SIZE_28 + Indicates whether the TPIU supports port size of 28-bit. + 27 + 27 + + + NotSupported + Port size 28 is not supported. + 0x0 + + + Supported + Port size 28 is supported. + 0x1 + + + + + PORT_SIZE_29 + Indicates whether the TPIU supports port size of 29-bit. + 28 + 28 + + + NotSupported + Port size 29 is not supported. + 0x0 + + + Supported + Port size 29 is supported. + 0x1 + + + + + PORT_SIZE_30 + Indicates whether the TPIU supports port size of 30-bit. + 29 + 29 + + + NotSupported + Port size 30 is not supported. + 0x0 + + + Supported + Port size 30 is supported. + 0x1 + + + + + PORT_SIZE_31 + Indicates whether the TPIU supports port size of 31-bit. + 30 + 30 + + + NotSupported + Port size 31 is not supported. + 0x0 + + + Supported + Port size 31 is supported. + 0x1 + + + + + PORT_SIZE_32 + Indicates whether the TPIU supports port size of 32-bit. + 31 + 31 + + + NotSupported + Port size 32 is not supported. + 0x0 + + + Supported + Port size 32 is supported. + 0x1 + + + + + + + CURRENTPORTSIZE + Each bit location is a single port size. One bit can be set, and indicates the current port size. + 0x004 + read-write + 0x00000000 + 0x20 + + + PORT_SIZE_1 + Indicates which port size is currently selected. + 0 + 0 + + + NotSelected + Port size 1 is not selected. + 0x0 + + + Selected + Port size 1 is selected. + 0x1 + + + + + PORT_SIZE_2 + Indicates which port size is currently selected. + 1 + 1 + + + NotSelected + Port size 2 is not selected. + 0x0 + + + Selected + Port size 2 is selected. + 0x1 + + + + + PORT_SIZE_3 + Indicates which port size is currently selected. + 2 + 2 + + + NotSelected + Port size 3 is not selected. + 0x0 + + + Selected + Port size 3 is selected. + 0x1 + + + + + PORT_SIZE_4 + Indicates which port size is currently selected. + 3 + 3 + + + NotSelected + Port size 4 is not selected. + 0x0 + + + Selected + Port size 4 is selected. + 0x1 + + + + + PORT_SIZE_5 + Indicates which port size is currently selected. + 4 + 4 + + + NotSelected + Port size 5 is not selected. + 0x0 + + + Selected + Port size 5 is selected. + 0x1 + + + + + PORT_SIZE_6 + Indicates which port size is currently selected. + 5 + 5 + + + NotSelected + Port size 6 is not selected. + 0x0 + + + Selected + Port size 6 is selected. + 0x1 + + + + + PORT_SIZE_7 + Indicates which port size is currently selected. + 6 + 6 + + + NotSelected + Port size 7 is not selected. + 0x0 + + + Selected + Port size 7 is selected. + 0x1 + + + + + PORT_SIZE_8 + Indicates which port size is currently selected. + 7 + 7 + + + NotSelected + Port size 8 is not selected. + 0x0 + + + Selected + Port size 8 is selected. + 0x1 + + + + + PORT_SIZE_9 + Indicates which port size is currently selected. + 8 + 8 + + + NotSelected + Port size 9 is not selected. + 0x0 + + + Selected + Port size 9 is selected. + 0x1 + + + + + PORT_SIZE_10 + Indicates which port size is currently selected. + 9 + 9 + + + NotSelected + Port size 10 is not selected. + 0x0 + + + Selected + Port size 10 is selected. + 0x1 + + + + + PORT_SIZE_11 + Indicates which port size is currently selected. + 10 + 10 + + + NotSelected + Port size 11 is not selected. + 0x0 + + + Selected + Port size 11 is selected. + 0x1 + + + + + PORT_SIZE_12 + Indicates which port size is currently selected. + 11 + 11 + + + NotSelected + Port size 12 is not selected. + 0x0 + + + Selected + Port size 12 is selected. + 0x1 + + + + + PORT_SIZE_13 + Indicates which port size is currently selected. + 12 + 12 + + + NotSelected + Port size 13 is not selected. + 0x0 + + + Selected + Port size 13 is selected. + 0x1 + + + + + PORT_SIZE_14 + Indicates which port size is currently selected. + 13 + 13 + + + NotSelected + Port size 14 is not selected. + 0x0 + + + Selected + Port size 14 is selected. + 0x1 + + + + + PORT_SIZE_15 + Indicates which port size is currently selected. + 14 + 14 + + + NotSelected + Port size 15 is not selected. + 0x0 + + + Selected + Port size 15 is selected. + 0x1 + + + + + PORT_SIZE_16 + Indicates which port size is currently selected. + 15 + 15 + + + NotSelected + Port size 16 is not selected. + 0x0 + + + Selected + Port size 16 is selected. + 0x1 + + + + + PORT_SIZE_17 + Indicates which port size is currently selected. + 16 + 16 + + + NotSelected + Port size 17 is not selected. + 0x0 + + + Selected + Port size 17 is selected. + 0x1 + + + + + PORT_SIZE_18 + Indicates which port size is currently selected. + 17 + 17 + + + NotSelected + Port size 18 is not selected. + 0x0 + + + Selected + Port size 18 is selected. + 0x1 + + + + + PORT_SIZE_19 + Indicates which port size is currently selected. + 18 + 18 + + + NotSelected + Port size 19 is not selected. + 0x0 + + + Selected + Port size 19 is selected. + 0x1 + + + + + PORT_SIZE_20 + Indicates which port size is currently selected. + 19 + 19 + + + NotSelected + Port size 20 is not selected. + 0x0 + + + Selected + Port size 20 is selected. + 0x1 + + + + + PORT_SIZE_21 + Indicates which port size is currently selected. + 20 + 20 + + + NotSelected + Port size 21 is not selected. + 0x0 + + + Selected + Port size 21 is selected. + 0x1 + + + + + PORT_SIZE_22 + Indicates which port size is currently selected. + 21 + 21 + + + NotSelected + Port size 22 is not selected. + 0x0 + + + Selected + Port size 22 is selected. + 0x1 + + + + + PORT_SIZE_23 + Indicates which port size is currently selected. + 22 + 22 + + + NotSelected + Port size 23 is not selected. + 0x0 + + + Selected + Port size 23 is selected. + 0x1 + + + + + PORT_SIZE_24 + Indicates which port size is currently selected. + 23 + 23 + + + NotSelected + Port size 24 is not selected. + 0x0 + + + Selected + Port size 24 is selected. + 0x1 + + + + + PORT_SIZE_25 + Indicates which port size is currently selected. + 24 + 24 + + + NotSelected + Port size 25 is not selected. + 0x0 + + + Selected + Port size 25 is selected. + 0x1 + + + + + PORT_SIZE_26 + Indicates which port size is currently selected. + 25 + 25 + + + NotSelected + Port size 26 is not selected. + 0x0 + + + Selected + Port size 26 is selected. + 0x1 + + + + + PORT_SIZE_27 + Indicates which port size is currently selected. + 26 + 26 + + + NotSelected + Port size 27 is not selected. + 0x0 + + + Selected + Port size 27 is selected. + 0x1 + + + + + PORT_SIZE_28 + Indicates which port size is currently selected. + 27 + 27 + + + NotSelected + Port size 28 is not selected. + 0x0 + + + Selected + Port size 28 is selected. + 0x1 + + + + + PORT_SIZE_29 + Indicates which port size is currently selected. + 28 + 28 + + + NotSelected + Port size 29 is not selected. + 0x0 + + + Selected + Port size 29 is selected. + 0x1 + + + + + PORT_SIZE_30 + Indicates which port size is currently selected. + 29 + 29 + + + NotSelected + Port size 30 is not selected. + 0x0 + + + Selected + Port size 30 is selected. + 0x1 + + + + + PORT_SIZE_31 + Indicates which port size is currently selected. + 30 + 30 + + + NotSelected + Port size 31 is not selected. + 0x0 + + + Selected + Port size 31 is selected. + 0x1 + + + + + PORT_SIZE_32 + Indicates which port size is currently selected. + 31 + 31 + + + NotSelected + Port size 32 is not selected. + 0x0 + + + Selected + Port size 32 is selected. + 0x1 + + + + + + + SUPPORTEDTRIGGERMODES + The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. + 0x100 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Indicates whether multiplying the trigger counter by 2^(0+1) is supported. + 0 + 0 + + + NotSelected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(0+1) is supported. + 0x1 + + + + + MULT_1 + Indicates whether multiplying the trigger counter by 2^(1+1) is supported. + 1 + 1 + + + NotSelected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(1+1) is supported. + 0x1 + + + + + MULT_2 + Indicates whether multiplying the trigger counter by 2^(2+1) is supported. + 2 + 2 + + + NotSelected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(2+1) is supported. + 0x1 + + + + + MULT_3 + Indicates whether multiplying the trigger counter by 2^(3+1) is supported. + 3 + 3 + + + NotSelected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(3+1) is supported. + 0x1 + + + + + MULT_4 + Indicates whether multiplying the trigger counter by 2^(4+1) is supported. + 4 + 4 + + + NotSelected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x0 + + + Selected + Multiplying the trigger counter by 2^(4+1) is supported. + 0x1 + + + + + TCOUNT8 + Indicates whether an 8-bit wide counter register is implemented. + 8 + 8 + + + NotImplemented + An 8-bit wide counter register is implemented. + 0x0 + + + Implemented + An 8-bit wide counter register is implemented. + 0x1 + + + + + TRIGGERED + A trigger has occurred and the counter has reached 0. + 16 + 16 + + + NotOccured + Trigger has not occurred. + 0x0 + + + Occured + Trigger has occurred. + 0x1 + + + + + TRGRUN + A trigger has occurred but the counter is not at 0. + 17 + 17 + + + NotOccured + Either a trigger has not occurred or the counter is at 0. + 0x0 + + + Occured + A trigger has occurred but the counter is not at 0. + 0x1 + + + + + + + TRIGGERCOUNTERVALUE + The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. + 0x104 + read-write + 0x00000000 + 0x20 + + + TrigCount + 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. + 0 + 7 + + + + + TRIGGERMULTIPLIER + The Trigger_multiplier register contains the selectors for the trigger counter multiplier. + 0x108 + read-write + 0x00000000 + 0x20 + + + MULT_0 + Multiply the Trigger Counter by 2^n. + 0 + 0 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_1 + Multiply the Trigger Counter by 2^n. + 1 + 1 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_2 + Multiply the Trigger Counter by 2^n. + 2 + 2 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_3 + Multiply the Trigger Counter by 2^n. + 3 + 3 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + MULT_4 + Multiply the Trigger Counter by 2^n. + 4 + 4 + + + Disabled + Multiplier disabled. + 0x0 + + + Enabled + Multiplier enabled. + 0x1 + + + + + + + SUPPPORTEDTESTPATTERNMODES + The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. + 0x200 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + NotSupported + Test pattern is not supported. + 0x0 + + + Supported + Test pattern is supported. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + NotSupported + Mode is not supported. + 0x0 + + + Supported + Mode is supported. + 0x1 + + + + + + + CURRENTTESTPATTERNMODES + Current_test_pattern_mode indicates the current test pattern or mode selected. + 0x204 + read-write + 0x00000000 + 0x20 + + + PATW1 + Indicates whether the walking 1s pattern is supported as output over the trace port. + 0 + 0 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATW0 + Indicates whether the walking 0s pattern is supported as output over the trace port. + 1 + 1 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATA5 + Indicates whether the AA/55 pattern is supported as output over the trace port. + 2 + 2 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PATF0 + Indicates whether the FF/00 pattern is supported as output over the trace port. + 3 + 3 + + + Disabled + Test pattern is disabled. + 0x0 + + + Enabled + Test pattern is enabled. + 0x1 + + + + + PTIMEEN + Indicates whether timed mode is supported. + 16 + 16 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + PCONTEN + Indicates whether continuous mode is supported. + 17 + 17 + + + Disabled + Mode is disabled. + 0x0 + + + Enabled + Mode is enabled. + 0x1 + + + + + + + TPRCR + The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. + 0x208 + read-write + 0x00000000 + 0x20 + + + PATTCOUNT + 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. + 0 + 7 + + + + + FFSR + The FFSR register indicates the current status of the formatter and flush features available in the TPIU. + 0x300 + read-write + 0x00000000 + 0x20 + + + FLINPROG + Flush in progress. + 0 + 0 + + + NotInProgress + A flush is not in progress. + 0x0 + + + InProgress + A flush is in progress. + 0x1 + + + + + FTSTOPPED + The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. + 1 + 1 + + + Running + Formatter has not stopped. + 0x0 + + + Stopped + Formatter has stopped. + 0x1 + + + + + TCPRESENT + Indicates whether the TRACECTL pin is available for use. + 2 + 2 + + + NotPresent + TRACECTL pin is not present. + 0x0 + + + Present + TRACECTL pin is present. + 0x1 + + + + + + + FFCR + The FFCR register controls the generation of stop, trigger, and flush events. + 0x304 + read-write + 0x00000000 + 0x20 + + + ENFTC + Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. + 0 + 0 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + ENFCONT + Is embedded in trigger packets and indicates that no cycle is using sync packets. + 1 + 1 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONFLIN + Enables the use of the flushin connection. + 4 + 4 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONTRIG + Initiates a manual flush of data in the system when a trigger event occurs. + 5 + 5 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANR + Generates a flush. This bit is set to 0 when this flush is serviced. + 6 + 6 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + FONMANW + Generates a flush. This bit is set to 1 when this flush is serviced. + 7 + 7 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGIN + Indicates a trigger when trigin is asserted. + 8 + 8 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGEVT + Indicates a trigger on a trigger event. + 9 + 9 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + TRIGFL + Indicates a trigger when flush completion on afreadys is returned. + 10 + 10 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPFL + Forces the FIFO to drain off any part-completed packets. + 12 + 12 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + STOPTRIG + Stops the formatter after a trigger event is observed. Reset to disabled or 0. + 13 + 13 + + + Disabled + The formatting feature is disabled. + 0x0 + + + Enabled + The formatting feature is enabled. + 0x1 + + + + + + + FSCR + The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. + 0x308 + read-write + 0x00000000 + 0x20 + + + CYCCOUNT + 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. + 0 + 11 + + + + + EXTCTLINPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. + 0x400 + read-write + 0x00000000 + 0x20 + + + EXTCTLIN_0 + EXTCTL inputs. + 0 + 0 + + + Low + Input EXTCTL0 is low. + 0x0 + + + High + Input EXTCTL0 is high. + 0x1 + + + + + EXTCTLIN_1 + EXTCTL inputs. + 1 + 1 + + + Low + Input EXTCTL1 is low. + 0x0 + + + High + Input EXTCTL1 is high. + 0x1 + + + + + EXTCTLIN_2 + EXTCTL inputs. + 2 + 2 + + + Low + Input EXTCTL2 is low. + 0x0 + + + High + Input EXTCTL2 is high. + 0x1 + + + + + EXTCTLIN_3 + EXTCTL inputs. + 3 + 3 + + + Low + Input EXTCTL3 is low. + 0x0 + + + High + Input EXTCTL3 is high. + 0x1 + + + + + EXTCTLIN_4 + EXTCTL inputs. + 4 + 4 + + + Low + Input EXTCTL4 is low. + 0x0 + + + High + Input EXTCTL4 is high. + 0x1 + + + + + EXTCTLIN_5 + EXTCTL inputs. + 5 + 5 + + + Low + Input EXTCTL5 is low. + 0x0 + + + High + Input EXTCTL5 is high. + 0x1 + + + + + EXTCTLIN_6 + EXTCTL inputs. + 6 + 6 + + + Low + Input EXTCTL6 is low. + 0x0 + + + High + Input EXTCTL6 is high. + 0x1 + + + + + EXTCTLIN_7 + EXTCTL inputs. + 7 + 7 + + + Low + Input EXTCTL7 is low. + 0x0 + + + High + Input EXTCTL7 is high. + 0x1 + + + + + + + EXTCTLOUTPORT + Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. + 0x404 + read-write + 0x00000000 + 0x20 + + + EXTCTLOUT_0 + EXTCTL outputs. + 0 + 0 + + + Low + Output EXTCTL0 is low. + 0x0 + + + High + Output EXTCTL0 is high. + 0x1 + + + + + EXTCTLOUT_1 + EXTCTL outputs. + 1 + 1 + + + Low + Output EXTCTL1 is low. + 0x0 + + + High + Output EXTCTL1 is high. + 0x1 + + + + + EXTCTLOUT_2 + EXTCTL outputs. + 2 + 2 + + + Low + Output EXTCTL2 is low. + 0x0 + + + High + Output EXTCTL2 is high. + 0x1 + + + + + EXTCTLOUT_3 + EXTCTL outputs. + 3 + 3 + + + Low + Output EXTCTL3 is low. + 0x0 + + + High + Output EXTCTL3 is high. + 0x1 + + + + + EXTCTLOUT_4 + EXTCTL outputs. + 4 + 4 + + + Low + Output EXTCTL4 is low. + 0x0 + + + High + Output EXTCTL4 is high. + 0x1 + + + + + EXTCTLOUT_5 + EXTCTL outputs. + 5 + 5 + + + Low + Output EXTCTL5 is low. + 0x0 + + + High + Output EXTCTL5 is high. + 0x1 + + + + + EXTCTLOUT_6 + EXTCTL outputs. + 6 + 6 + + + Low + Output EXTCTL6 is low. + 0x0 + + + High + Output EXTCTL6 is high. + 0x1 + + + + + EXTCTLOUT_7 + EXTCTL outputs. + 7 + 7 + + + Low + Output EXTCTL7 is low. + 0x0 + + + High + Output EXTCTL7 is high. + 0x1 + + + + + + + ITTRFLINACK + The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + TRIGINACK + Sets the value of triginack. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHINACK + Sets the value of flushinack. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITTRFLIN + The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. + 0xEE8 + read-write + 0x00000000 + 0x20 + + + TRIGIN + Reads the value of trigin. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + FLUSHIN + Reads the value of flushin. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBDATA0 + The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + Enables control of the atreadys and afvalids outputs of the TPIU. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + Sets the value of afvalid. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + Sets the value of atready. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATID + Reads the value of atids. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. + To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + Reads the value of atvalids. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + Reads the value of afreadys. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + Reads the value of atbytess. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + Used to enable topology detection. + This register enables the component to switch from a functional mode, the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. + 0xF00 + read-write + 0x00000000 + 0x20 + + + INTEGRATIONMODE + Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. + 0 + 0 + + + Disabled + Integration mode is disabled. + 0x0 + + + Enabled + Integration mode is Enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + MUXNUM + Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. + Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. + 0 + 4 + + + CLKRELAT + Indicates the relationship between atclk and traceclkin. + 5 + 5 + + + Synchronous + atclk and traceclkin are synchronous. + 0x0 + + + ASynchronous + atclk and traceclkin are asynchronous. + 0x1 + + + + + FIFOSIZE + FIFO size in powers of 2. + 6 + 8 + + + Entries4 + FIFO size of 4 entries, that is, 16 bytes. + 0x2 + + + + + TCLKDATA + Indicates whether trace clock plus data is supported. + 9 + 9 + + + Supported + Trace clock and data is supported. + 0x0 + + + NotSupported + Trace clock and data is not supported. + 0x1 + + + + + SWOMAN + Indicates whether Serial Wire Output, Manchester encoded format, is supported. + 10 + 10 + + + NotSupported + Serial Wire Output, Manchester encoded format, is not supported. + 0x0 + + + Supported + Serial Wire Output, Manchester encoded format, is supported. + 0x1 + + + + + SWOUARTNRZ + Indicates whether Serial Wire Output, UART or NRZ, is supported. + 11 + 11 + + + NotSupported + Serial Wire Output, UART or NRZ, is not supported. + 0x0 + + + Supported + Serial Wire Output, UART or NRZ, is supported. + 0x1 + + + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace sink. + 0x1 + + + + + SUB + The sub-type of the component + 4 + 7 + + + TracePort + Indicates that this component is a trace port component. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_CTI210_NS + Cross-Trigger Interface control 0 + 0xBF046000 + CTI + + + + 0 + 0x1000 + registers + + CTI + 0x20 + + + CTICONTROL + CTI Control register + 0x000 + read-write + 0x00000000 + 0x20 + + + GLBEN + Enables or disables the CTI. + 0 + 0 + + + Disabled + All cross-triggering mapping logic functionality is disabled. + 0x0 + + + Enabled + Cross-triggering mapping logic functionality is enabled. + 0x1 + + + + + + + CTIINTACK + CTI Interrupt Acknowledge register + 0x010 + write-only + 0x00000000 + 0x20 + + + INTACK_0 + Acknowledges the ctitrigout 0 output. + 0 + 0 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_1 + Acknowledges the ctitrigout 1 output. + 1 + 1 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_2 + Acknowledges the ctitrigout 2 output. + 2 + 2 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_3 + Acknowledges the ctitrigout 3 output. + 3 + 3 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_4 + Acknowledges the ctitrigout 4 output. + 4 + 4 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_5 + Acknowledges the ctitrigout 5 output. + 5 + 5 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_6 + Acknowledges the ctitrigout 6 output. + 6 + 6 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + INTACK_7 + Acknowledges the ctitrigout 7 output. + 7 + 7 + + write + + Acknowledge + Clears the ctitrigout. + 0x1 + + + + + + + CTIAPPSET + CTI Application Trigger Set register + 0x014 + read-write + 0x00000000 + 0x20 + + + APPSET_0 + Application trigger event for channel 0. + 0 + 0 + + read + + Inactive + Application trigger 0 is inactive. + 0x0 + + + Active + Application trigger 0 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 0. + 0x1 + + + + + APPSET_1 + Application trigger event for channel 1. + 1 + 1 + + read + + Inactive + Application trigger 1 is inactive. + 0x0 + + + Active + Application trigger 1 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 1. + 0x1 + + + + + APPSET_2 + Application trigger event for channel 2. + 2 + 2 + + read + + Inactive + Application trigger 2 is inactive. + 0x0 + + + Active + Application trigger 2 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 2. + 0x1 + + + + + APPSET_3 + Application trigger event for channel 3. + 3 + 3 + + read + + Inactive + Application trigger 3 is inactive. + 0x0 + + + Active + Application trigger 3 is active. + 0x1 + + + + write + + Activate + Generate channel event for channel 3. + 0x1 + + + + + + + CTIAPPCLEAR + CTI Application Trigger Clear register + 0x018 + write-only + 0x00000000 + 0x20 + + + APPCLEAR_0 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 0 + 0 + + write + + Clear + Clears the event for channel 0. + 0x1 + + + + + APPCLEAR_1 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 1 + 1 + + write + + Clear + Clears the event for channel 1. + 0x1 + + + + + APPCLEAR_2 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 2 + 2 + + write + + Clear + Clears the event for channel 2. + 0x1 + + + + + APPCLEAR_3 + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + 3 + 3 + + write + + Clear + Clears the event for channel 3. + 0x1 + + + + + + + CTIAPPPULSE + CTI Application Pulse register + 0x01C + write-only + 0x00000000 + 0x20 + + + APPULSE_0 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 0 + 0 + + write + + Generate + Generates an event pulse on channel 0. + 0x1 + + + + + APPULSE_1 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 1 + 1 + + write + + Generate + Generates an event pulse on channel 1. + 0x1 + + + + + APPULSE_2 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 2 + 2 + + write + + Generate + Generates an event pulse on channel 2. + 0x1 + + + + + APPULSE_3 + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + 3 + 3 + + write + + Generate + Generates an event pulse on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIINEN[%s] + Description collection: CTI Trigger to Channel Enable register + 0x020 + read-write + 0x00000000 + 0x20 + + + TRIGINEN_0 + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. + 0 + 0 + + + Disabled + Input trigger n events are ignored by channel 0. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. + 0x1 + + + + + TRIGINEN_1 + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. + 1 + 1 + + + Disabled + Input trigger n events are ignored by channel 1. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. + 0x1 + + + + + TRIGINEN_2 + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. + 2 + 2 + + + Disabled + Input trigger n events are ignored by channel 2. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. + 0x1 + + + + + TRIGINEN_3 + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. + 3 + 3 + + + Disabled + Input trigger n events are ignored by channel 3. + 0x0 + + + Enabled + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. + 0x1 + + + + + + + 0x8 + 0x4 + CTIOUTEN[%s] + Description collection: CTI Channel to Trigger Enable register + 0x0A0 + read-write + 0x00000000 + 0x20 + + + TRIGOUTEN_0 + Enables a cross trigger event to ctitrigout when channel 0 is activated. + 0 + 0 + + + Disabled + Channel 0 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_1 + Enables a cross trigger event to ctitrigout when channel 1 is activated. + 1 + 1 + + + Disabled + Channel 1 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_2 + Enables a cross trigger event to ctitrigout when channel 2 is activated. + 2 + 2 + + + Disabled + Channel 2 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + TRIGOUTEN_3 + Enables a cross trigger event to ctitrigout when channel 3 is activated. + 3 + 3 + + + Disabled + Channel 3 is ignored by output trigger n. + 0x0 + + + Enabled + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). + 0x1 + + + + + + + CTITRIGINSTATUS + CTI Trigger In Status register + 0x130 + read-only + 0x00000000 + 0x20 + + + TRIGINSTATUS_0 + Shows the status of ctitrigin0 input. + 0 + 0 + + + Active + Ctitrigin 0 is active. + 0x1 + + + Inactive + Ctitrigin 0 is inactive. + 0x0 + + + + + TRIGINSTATUS_1 + Shows the status of ctitrigin1 input. + 1 + 1 + + + Active + Ctitrigin 1 is active. + 0x1 + + + Inactive + Ctitrigin 1 is inactive. + 0x0 + + + + + TRIGINSTATUS_2 + Shows the status of ctitrigin2 input. + 2 + 2 + + + Active + Ctitrigin 2 is active. + 0x1 + + + Inactive + Ctitrigin 2 is inactive. + 0x0 + + + + + TRIGINSTATUS_3 + Shows the status of ctitrigin3 input. + 3 + 3 + + + Active + Ctitrigin 3 is active. + 0x1 + + + Inactive + Ctitrigin 3 is inactive. + 0x0 + + + + + TRIGINSTATUS_4 + Shows the status of ctitrigin4 input. + 4 + 4 + + + Active + Ctitrigin 4 is active. + 0x1 + + + Inactive + Ctitrigin 4 is inactive. + 0x0 + + + + + TRIGINSTATUS_5 + Shows the status of ctitrigin5 input. + 5 + 5 + + + Active + Ctitrigin 5 is active. + 0x1 + + + Inactive + Ctitrigin 5 is inactive. + 0x0 + + + + + TRIGINSTATUS_6 + Shows the status of ctitrigin6 input. + 6 + 6 + + + Active + Ctitrigin 6 is active. + 0x1 + + + Inactive + Ctitrigin 6 is inactive. + 0x0 + + + + + TRIGINSTATUS_7 + Shows the status of ctitrigin7 input. + 7 + 7 + + + Active + Ctitrigin 7 is active. + 0x1 + + + Inactive + Ctitrigin 7 is inactive. + 0x0 + + + + + + + CTITRIGOUTSTATUS + CTI Trigger Out Status register + 0x134 + read-only + 0x00000000 + 0x20 + + + TRIGOUTSTATUS_0 + Shows the status of ctitrigout0 output. + 0 + 0 + + + Active + Ctitrigout 0 is active. + 0x1 + + + Inactive + Ctitrigout 0 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_1 + Shows the status of ctitrigout1 output. + 1 + 1 + + + Active + Ctitrigout 1 is active. + 0x1 + + + Inactive + Ctitrigout 1 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_2 + Shows the status of ctitrigout2 output. + 2 + 2 + + + Active + Ctitrigout 2 is active. + 0x1 + + + Inactive + Ctitrigout 2 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_3 + Shows the status of ctitrigout3 output. + 3 + 3 + + + Active + Ctitrigout 3 is active. + 0x1 + + + Inactive + Ctitrigout 3 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_4 + Shows the status of ctitrigout4 output. + 4 + 4 + + + Active + Ctitrigout 4 is active. + 0x1 + + + Inactive + Ctitrigout 4 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_5 + Shows the status of ctitrigout5 output. + 5 + 5 + + + Active + Ctitrigout 5 is active. + 0x1 + + + Inactive + Ctitrigout 5 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_6 + Shows the status of ctitrigout6 output. + 6 + 6 + + + Active + Ctitrigout 6 is active. + 0x1 + + + Inactive + Ctitrigout 6 is inactive. + 0x0 + + + + + TRIGOUTSTATUS_7 + Shows the status of ctitrigout7 output. + 7 + 7 + + + Active + Ctitrigout 7 is active. + 0x1 + + + Inactive + Ctitrigout 7 is inactive. + 0x0 + + + + + + + CTICHINSTATUS + CTI Channel In Status register + 0x138 + read-only + 0x00000000 + 0x20 + + + CTICHINSTATUS_0 + Shows the status of the ctitrigin 0 input. + 0 + 0 + + + Active + Ctichin 0 is active. + 0x1 + + + Inactive + Ctichin 0 is inactive. + 0x0 + + + + + CTICHINSTATUS_1 + Shows the status of the ctitrigin 1 input. + 1 + 1 + + + Active + Ctichin 1 is active. + 0x1 + + + Inactive + Ctichin 1 is inactive. + 0x0 + + + + + CTICHINSTATUS_2 + Shows the status of the ctitrigin 2 input. + 2 + 2 + + + Active + Ctichin 2 is active. + 0x1 + + + Inactive + Ctichin 2 is inactive. + 0x0 + + + + + CTICHINSTATUS_3 + Shows the status of the ctitrigin 3 input. + 3 + 3 + + + Active + Ctichin 3 is active. + 0x1 + + + Inactive + Ctichin 3 is inactive. + 0x0 + + + + + + + CTIGATE + Enable CTI Channel Gate register + 0x140 + read-write + 0x0000000F + 0x20 + + + CTIGATEEN_0 + Enable ctichout0. + 0 + 0 + + + Enabled + Enable ctichout channel 0 propagation. + 0x1 + + + Disabled + Disable ctichout channel 0 propagation. + 0x0 + + + + + CTIGATEEN_1 + Enable ctichout1. + 1 + 1 + + + Enabled + Enable ctichout channel 1 propagation. + 0x1 + + + Disabled + Disable ctichout channel 1 propagation. + 0x0 + + + + + CTIGATEEN_2 + Enable ctichout2. + 2 + 2 + + + Enabled + Enable ctichout channel 2 propagation. + 0x1 + + + Disabled + Disable ctichout channel 2 propagation. + 0x0 + + + + + CTIGATEEN_3 + Enable ctichout3. + 3 + 3 + + + Enabled + Enable ctichout channel 3 propagation. + 0x1 + + + Disabled + Disable ctichout channel 3 propagation. + 0x0 + + + + + + + DEVARCH + Device Architecture register + 0xFBC + read-only + 0x47701A14 + 0x20 + + + Architecture + Contains the CTI device architecture. + 0 + 0 + + + + + DEVID + Device Configuration register + 0xFC8 + read-only + 0x00040800 + 0x20 + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. + The default value of 0b00000 indicates that no multiplexing is present. + 0 + 4 + + + NUMTRIG + Number of ECT triggers available. + 8 + 15 + + + NUMCH + Number of ECT channels available. + 16 + 19 + + + + + DEVTYPE + Device Type Identifier register + 0xFCC + read-only + 0x00000014 + 0x20 + + + MAJOR + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this + debug and trace component. + 0 + 3 + + + Controller + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 0x4 + + + + + SUB + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within + the major classification as specified in the MAJOR field. + 4 + 7 + + + Crosstrigger + Indicates that this component is a sub-triggering component. + 0x1 + + + + + + + PIDR4 + Peripheral ID4 Register + 0xFD0 + read-only + 0x00000004 + 0x20 + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 3 + + + Code + JEDEC continuation code. + 0x4 + + + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory. + 4 + 7 + + + + + PIDR5 + Peripheral ID5 register + 0xFD4 + read-only + 0x00000000 + 0x20 + + + PIDR6 + Peripheral ID6 register + 0xFD8 + read-only + 0x00000000 + 0x20 + + + PIDR7 + Peripheral ID7 register + 0xFDC + read-only + 0x00000000 + 0x20 + + + PIDR0 + Peripheral ID0 Register + 0xFE0 + read-only + 0x00000021 + 0x20 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 7 + + + PartnumberL + Indicates bits[7:0] of the part number of the component. + 0x21 + + + + + + + PIDR1 + Peripheral ID1 Register + 0xFE4 + read-only + 0x000000BD + 0x20 + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + 0 + 3 + + + PartnumberH + Indicates bits[11:8] of the part number of the component. + 0xD + + + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 4 + 7 + + + Arm + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 0xB + + + + + + + PIDR2 + Peripheral ID2 Register + 0xFE8 + read-only + 0x0000000B + 0x20 + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + 0 + 2 + + + Arm + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 0x3 + + + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + 3 + 3 + + + REVISION + Peripheral revision + 4 + 7 + + + Rev0p0 + This device is at r0p0 + 0x0 + + + + + + + PIDR3 + Peripheral ID3 Register + 0xFEC + read-only + 0x00000000 + 0x20 + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, + this field is 0b0000. Customers change this value when they make authorized modifications to this component. + 0 + 3 + + + Unmodified + Indicates that the customer has not modified this component. + 0x0 + + + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a + metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + 4 + 7 + + + NoErrata + Indicates that there are no errata fixes to this component. + 0x0 + + + + + + + CIDR0 + Component ID0 Register + 0xFF0 + read-only + 0x0000000D + 0x20 + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code. + 0 + 7 + + + Value + Bits[7:0] of the identification code. + 0x0D + + + + + + + CIDR1 + Component ID1 Register + 0xFF4 + read-only + 0x00000090 + 0x20 + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + 0 + 3 + + + Value + Bits[11:8] of the identification code. + 0x0 + + + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code + 4 + 7 + + + Coresight + Indicates that the component is a CoreSight component. + 0x9 + + + + + + + CIDR2 + Component ID2 Register + 0xFF8 + read-only + 0x00000005 + 0x20 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + 0 + 7 + + + Value + Bits[23:16] of the identification code. + 0x05 + + + + + + + CIDR3 + Component ID3 Register + 0xFFC + read-only + 0x000000B1 + 0x20 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + 0 + 7 + + + Value + Bits[31:24] of the identification code. + 0xB1 + + + + + + + + + GLOBAL_CTI211_NS + Cross-Trigger Interface control 1 + 0xBF047000 + + + + + GLOBAL_ATBREPLICATOR210_NS + ATB Replicator module 0 + 0xBF048000 + ATBREPLICATOR + + + + 0 + 0x1000 + registers + + ATBREPLICATOR + 0x20 + + + IDFILTER0 + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ID0_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID0_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 0. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + IDFILTER1 + The IDFILTER1 register enables the programming of ID filtering for master port 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + ID1_00_0F + Enable or disable ID filtering for IDs 0x00_0x0F. + 0 + 0 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_10_1F + Enable or disable ID filtering for IDs 0x10_0x1F. + 1 + 1 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_20_2F + Enable or disable ID filtering for IDs 0x20_0x2F. + 2 + 2 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_30_3F + Enable or disable ID filtering for IDs 0x30_0x3F. + 3 + 3 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_40_4F + Enable or disable ID filtering for IDs 0x40_0x4F. + 4 + 4 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_50_5F + Enable or disable ID filtering for IDs 0x50_0x5F. + 5 + 5 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_60_6F + Enable or disable ID filtering for IDs 0x60_0x6F. + 6 + 6 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + ID1_70_7F + Enable or disable ID filtering for IDs 0x70_0x7F. + 7 + 7 + + + NotFiltered + Transactions with these IDs are passed on to ATB master port 1. + 0x0 + + + Selected + Transactions with these IDs are discarded by the replicator. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATREADYM0 + Reads the value of the atreadym0 input. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYM1 + Reads the value of the atreadym1 input. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDS + Reads the value of the atvalids input. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR0 + The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + Sets the value of the atvalidm0 output. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATVALIDM1 + Sets the value of the atvalidm1 output. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATREADYS + Sets the value of the atreadys output. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTNUM + Indicates the number of master ports implemented. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + Indicates that this component replicates trace from a single source to multiple targets. + 0x2 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBREPLICATOR211_NS + ATB Replicator module 1 + 0xBF049000 + + + + + GLOBAL_ATBREPLICATOR212_NS + ATB Replicator module 2 + 0xBF04A000 + + + + + GLOBAL_ATBREPLICATOR213_NS + ATB Replicator module 3 + 0xBF04B000 + + + + + GLOBAL_ATBFUNNEL210_NS + ATB funnel module 0 + 0xBF04C000 + ATBFUNNEL + + + + 0 + 0x1000 + registers + + ATBFUNNEL + 0x20 + + + CTRLREG + The IDFILTER0 register enables the programming of ID filtering for master port 0. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENS_0 + Enable slave port 0. + 0 + 0 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_1 + Enable slave port 1. + 1 + 1 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_2 + Enable slave port 2. + 2 + 2 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_3 + Enable slave port 3. + 3 + 3 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_4 + Enable slave port 4. + 4 + 4 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_5 + Enable slave port 5. + 5 + 5 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_6 + Enable slave port 6. + 6 + 6 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + ENS_7 + Enable slave port 7. + 7 + 7 + + + Disabled + Slave port disabled. This excludes the port from the priority selection scheme. + 0x0 + + + Enabled + Slave port enabled. + 0x1 + + + + + HT + Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. + When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. + The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. + The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. + 8 + 11 + + + + + PRIORITYCTRLREG + The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. + 0x004 + read-write + 0x00000000 + 0x20 + + + PRIPORT0 + Priority value of port number 0. + 0 + 2 + + + PRIPORT1 + Priority value of port number 1. + 3 + 5 + + + PRIPORT2 + Priority value of port number 2. + 6 + 8 + + + PRIPORT3 + Priority value of port number 3. + 9 + 11 + + + PRIPORT4 + Priority value of port number 4. + 12 + 14 + + + PRIPORT5 + Priority value of port number 5. + 15 + 17 + + + PRIPORT6 + Priority value of port number 6. + 18 + 20 + + + PRIPORT7 + Priority value of port number 7. + 21 + 23 + + + + + ITATBDATA0 + The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. + 0xEEC + read-write + 0x00000000 + 0x20 + + + ATDATA_0 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_1 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_2 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_3 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 3 + 3 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_4 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 4 + 4 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_5 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 5 + 5 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_6 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 6 + 6 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_7 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 7 + 7 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_8 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 8 + 8 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_9 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 9 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_10 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 10 + 10 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_11 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 11 + 11 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_12 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 12 + 12 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_13 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 13 + 13 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_14 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 14 + 14 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_15 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 15 + 15 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATDATA_16 + A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. + 16 + 16 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR2 + The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. + 0xEF0 + read-write + 0x00000000 + 0x20 + + + ATREADY + A read access returns the value of atreadym. + A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFVALID + A read access returns the value of afvalidm. + A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. + 1 + 1 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITATBCTR1 + The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALIDM0 + A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. +A write outputs the value to the atidm port. + 0 + 6 + + + Low + Pin is logic 0. + 0x00 + + + High + Pin is logic 1. + 0x01 + + + + + + + ITATBCTR0 + The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. + 0xEF8 + read-write + 0x00000000 + 0x20 + + + ATVALID + A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. +A write outputs the value to atvalidm. + 0 + 0 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + AFREADY + A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to afreadym. + 2 + 2 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + ATBYTES + A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. +A write outputs the value to atbytesm. + 8 + 9 + + + Low + Pin is logic 0. + 0x0 + + + High + Pin is logic 1. + 0x1 + + + + + + + ITCTRL + The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration Mode Enable. + 0 + 0 + + + Disabled + Integration mode disabled. + 0x0 + + + Enabled + Integration mode enabled. + 0x1 + + + + + + + CLAIMSET + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Set claim bit 0 and check if bit is implemented or not. + 0 + 0 + + read + + NotImplemented + Claim bit 0 is not implemented. + 0x0 + + + Implemented + Claim bit 0 is implemented. + 0x1 + + + + write + + Set + Set claim bit 0. + 0x1 + + + + + BIT_1 + Set claim bit 1 and check if bit is implemented or not. + 1 + 1 + + read + + NotImplemented + Claim bit 1 is not implemented. + 0x0 + + + Implemented + Claim bit 1 is implemented. + 0x1 + + + + write + + Set + Set claim bit 1. + 0x1 + + + + + BIT_2 + Set claim bit 2 and check if bit is implemented or not. + 2 + 2 + + read + + NotImplemented + Claim bit 2 is not implemented. + 0x0 + + + Implemented + Claim bit 2 is implemented. + 0x1 + + + + write + + Set + Set claim bit 2. + 0x1 + + + + + BIT_3 + Set claim bit 3 and check if bit is implemented or not. + 3 + 3 + + read + + NotImplemented + Claim bit 3 is not implemented. + 0x0 + + + Implemented + Claim bit 3 is implemented. + 0x1 + + + + write + + Set + Set claim bit 3. + 0x1 + + + + + + + CLAIMCLR + Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. + The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + BIT_0 + Read or clear claim bit 0. + 0 + 0 + + read + + Cleared + Claim bit 0 is not set. + 0x0 + + + Set + Claim bit 0 is set. + 0x1 + + + + write + + Clear + Clear claim bit 0. + 0x1 + + + + + BIT_1 + Read or clear claim bit 1. + 1 + 1 + + read + + Cleared + Claim bit 1 is not set. + 0x0 + + + Set + Claim bit 1 is set. + 0x1 + + + + write + + Clear + Clear claim bit 1. + 0x1 + + + + + BIT_2 + Read or clear claim bit 2. + 2 + 2 + + read + + Cleared + Claim bit 2 is not set. + 0x0 + + + Set + Claim bit 2 is set. + 0x1 + + + + write + + Clear + Clear claim bit 2. + 0x1 + + + + + BIT_3 + Read or clear claim bit 3. + 3 + 3 + + read + + Cleared + Claim bit 3 is not set. + 0x0 + + + Set + Claim bit 3 is set. + 0x1 + + + + write + + Clear + Clear claim bit 3. + 0x1 + + + + + + + LAR + This is used to enable write access to device registers. + 0xFB0 + read-write + 0x00000000 + 0x20 + + + ACCESS + A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + 0 + 31 + + + UnLock + Unlock register interface. + 0xC5ACCE55 + + + + + + + LSR + This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. + The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. + 0xFB4 + read-write + 0x00000000 + 0x20 + + + PRESENT + Indicates that a lock control mechanism exists for this device. + 0 + 0 + + + NotImplemented + No lock control mechanism exists, writes to the Lock Access Register are ignored. + 0x0 + + + Implemented + Lock control mechanism is present. + 0x1 + + + + + LOCKED + Returns the current status of the Lock. + 1 + 1 + + + UnLocked + Write access is allowed to this device. + 0x0 + + + Locked + Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. + 0x1 + + + + + TYPE + Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. + 2 + 2 + + + Bits32 + This component implements a 32-bit Lock Access Register. + 0x0 + + + Bits8 + This component implements an 8-bit Lock Access Register. + 0x1 + + + + + + + AUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + DEVID + Indicates the capabilities of the component. + 0xFC8 + read-only + 0x00000000 + 0x20 + + + PORTCOUNT + Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. + 0 + 3 + + + + + DEVTYPE + The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + InputOutputDevice + Indicates that this component has ATB inputs and outputs. + 0x2 + + + + + SUB + The sub-type of the component + 4 + 7 + + + Replicator + This component arbitrates ATB inputs mapping to ATB outputs. + 0x1 + + + + + + + PIDR4 + Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + PIDR_0 + Coresight peripheral identification registers. + 0xFE0 + read-write + 0x00000000 + 0x20 + + + PIDR_1 + Coresight peripheral identification registers. + 0xFE4 + read-write + 0x00000000 + 0x20 + + + PIDR_2 + Coresight peripheral identification registers. + 0xFE8 + read-write + 0x00000000 + 0x20 + + + PIDR_3 + Coresight peripheral identification registers. + 0xFEC + read-write + 0x00000000 + 0x20 + + + CIDR_0 + Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + CIDR_1 + Coresight component identification registers. + 0xFF4 + read-write + 0x00000000 + 0x20 + + + CIDR_2 + Coresight component identification registers. + 0xFF8 + read-write + 0x00000000 + 0x20 + + + CIDR_3 + Coresight component identification registers. + 0xFFC + read-write + 0x00000000 + 0x20 + + + + + GLOBAL_ATBFUNNEL211_NS + ATB funnel module 1 + 0xBF04D000 + + + + + GLOBAL_ATBFUNNEL212_NS + ATB funnel module 2 + 0xBF04E000 + + + + + GLOBAL_ATBFUNNEL213_NS + ATB funnel module 3 + 0xBF04F000 + + + + + ETM_NS + Embedded Trace Macrocell + 0xE0041000 + ETM + + + + 0 + 0x1000 + registers + + ETM + 0x20 + + + TRCPRGCTLR + Enables the trace unit. + 0x004 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCPROCSELR + Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero. + 0x008 + read-write + 0x00000000 + 0x20 + + + PROCSEL + PE select bits that select the PE to trace. + 0 + 4 + + + + + TRCSTATR + Idle status bit + 0x00C + read-write + 0x00000000 + 0x20 + + + IDLE + Trace unit enable bit + 0 + 0 + + + NotIdle + The trace unit is not idle. + 0x0 + + + Idle + The trace unit is idle. + 0x1 + + + + + PMSTABLE + Programmers' model stable bit + 1 + 1 + + + NotStable + The programmers' model is not stable. + 0x0 + + + Stable + The programmers' model is stable. + 0x1 + + + + + + + TRCCONFIGR + Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x010 + read-write + 0x00000000 + 0x20 + + + LOADASP0INST + Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. + 1 + 1 + + + No + Do not trace load instructions as P0 instructions. + 0x0 + + + Yes + Trace load instructions as P0 instructions. + 0x1 + + + + + STOREASP0INST + Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. + 2 + 2 + + + No + Do not trace store instructions as P0 instructions. + 0x0 + + + Yes + Trace store instructions as P0 instructions. + 0x1 + + + + + BB + Branch broadcast mode bit. + 3 + 3 + + + Disabled + Branch broadcast mode is disabled. + 0x0 + + + Enabled + Branch broadcast mode is enabled. + 0x1 + + + + + CCI + Cycle counting instruction trace bit. + 4 + 4 + + + Disabled + Cycle counting in the instruction trace is disabled. + 0x0 + + + Enabled + Cycle counting in the instruction trace is enabled. + 0x1 + + + + + CID + Context ID tracing bit. + 6 + 6 + + + Disabled + Context ID tracing is disabled. + 0x0 + + + Enabled + Context ID tracing is enabled. + 0x1 + + + + + VMID + Virtual context identifier tracing bit. + 7 + 7 + + + Disabled + Virtual context identifier tracing is disabled. + 0x0 + + + Enabled + Virtual context identifier tracing is enabled. + 0x1 + + + + + COND + Conditional instruction tracing bit. + 8 + 10 + + + Disabled + Conditional instruction tracing is disabled. + 0x0 + + + LoadOnly + Conditional load instructions are traced. + 0x1 + + + StoreOnly + Conditional store instructions are traced. + 0x2 + + + LoadAndStore + Conditional load and store instructions are traced. + 0x3 + + + All + All conditional instructions are traced. + 0x7 + + + + + TS + Global timestamp tracing bit. + 11 + 11 + + + Disabled + Global timestamp tracing is disabled. + 0x0 + + + Enabled + Global timestamp tracing is enabled. + 0x1 + + + + + RS + Return stack enable bit. + 12 + 12 + + + Disabled + Return stack is disabled. + 0x0 + + + Enabled + Return stack is enabled. + 0x1 + + + + + QE + Q element enable field. + 13 + 14 + + + Disabled + Q elements are disabled. + 0x0 + + + OnlyWithoutInstCounts + Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. + 0x1 + + + Enabled + Q elements with and without instruction counts are enabled. + 0x3 + + + + + VMIDOPT + Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. + 15 + 15 + + + VTTBR_EL2 + VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context +identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always +zero. If the trace unit supports a Virtual context identifier larger than 8 bits and +if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits +[15:8] of the trace unit Virtual context identifier are always zero. + 0x0 + + + CONTEXTIDR_EL2 + CONTEXTIDR_EL2 is used. + 0x1 + + + + + DA + Data address tracing bit. + 16 + 16 + + + Disabled + Data address tracing is disabled. + 0x0 + + + Enabled + Data address tracing is enabled. + 0x1 + + + + + DV + Data value tracing bit. + 17 + 17 + + + Disabled + Data value tracing is disabled. + 0x0 + + + Enabled + Data value tracing is enabled. + 0x1 + + + + + + + TRCEVENTCTL0R + Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. + 0x20 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate trace elements. + 0 + 7 + + + + + TRCEVENTCTL1R + Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x24 + read-write + 0x00000000 + 0x20 + + + INSTEN_0 + Instruction event enable field. + 0 + 0 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 0, in the instruction trace stream. + 0x1 + + + + + INSTEN_1 + Instruction event enable field. + 1 + 1 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 1, in the instruction trace stream. + 0x1 + + + + + INSTEN_2 + Instruction event enable field. + 2 + 2 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 2, in the instruction trace stream. + 0x1 + + + + + INSTEN_3 + Instruction event enable field. + 3 + 3 + + + Disabled + The trace unit does not generate an Event element. + 0x0 + + + Enabled + The trace unit generates an Event element for event 3, in the instruction trace stream. + 0x1 + + + + + DATAEN + Data event enable bit. + 4 + 4 + + + Disabled + The trace unit does not generate an Event element if event 0 occurs. + 0x0 + + + Enabled + The trace unit generates an Event element in the data trace stream if event 0 occurs. + 0x1 + + + + + ATB + AMBA Trace Bus (ATB) trigger enable bit. + 11 + 11 + + + Disabled + ATB trigger is disabled. + 0x0 + + + Enabled + ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event. + 0x1 + + + + + LPOVERRIDE + Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. + 12 + 12 + + + Disabled + Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state. + 0x0 + + + Enabled + Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation. + 0x1 + + + + + + + TRCSTALLCTLR + Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. + 0x2C + read-write + 0x00000000 + 0x20 + + + LEVEL + Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct. + 0 + 3 + + + Min + Zero invasion. This setting has a greater risk of a FIFO overflow + 0x0 + + + Max + Maximum invasion occurs but there is less risk of a FIFO overflow. + 0xF + + + + + ISTALL + Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL. + 8 + 8 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + DSTALL + Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL. + 9 + 9 + + + Disabled + The trace unit must not stall the PE. + 0x0 + + + Enabled + The trace unit can stall the PE. + 0x1 + + + + + INSTPRIORITY + Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL. + 10 + 10 + + + Disabled + The trace unit must not prioritize instruction trace. + 0x0 + + + Enabled + The trace unit can prioritize instruction trace. A trace unit might prioritize +instruction trace by preventing output of data trace, or other means which ensure +that the instruction trace has a higher priority than the data trace. + 0x1 + + + + + DATADISCARDLOAD + Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL. + 11 + 11 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data loads. + 0x1 + + + + + DATADISCARDSTORE + Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL. + 12 + 12 + + + Disabled + The trace unit must not discard any data trace elements. + 0x0 + + + Enabled + The trace unit can discard P1 and P2 elements associated with data stores. + 0x1 + + + + + NOOVERFLOW + Trace overflow prevention bit. + 13 + 13 + + + Disabled + Trace overflow prevention is disabled. + 0x0 + + + Enabled + Trace overflow prevention is enabled. This might cause a significant performance impact. + 0x1 + + + + + + + TRCTSCTLR + Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. + 0x30 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should generate time stamps. + 0 + 7 + + + + + TRCSYNCPR + Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed. + 0x34 + read-write + 0x00000000 + 0x20 + + + PERIOD + Controls how many bytes of trace, the sum of instruction and data, that a trace unit can +generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD + 0 + 4 + + + Disabled + Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request. + 0x00 + + + + + + + TRCCCCTLR + Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1. + 0x38 + read-write + 0x00000000 + 0x20 + + + THRESHOLD + Sets the threshold value for instruction trace cycle counting. + 0 + 11 + + + + + TRCBBCTLR + Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. + 0x3C + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[0] controls the selection of address range comparator pair 0. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_1 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[1] controls the selection of address range comparator pair 1. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_2 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[2] controls the selection of address range comparator pair 2. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_3 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[3] controls the selection of address range comparator pair 3. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_4 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[4] controls the selection of address range comparator pair 4. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_5 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[5] controls the selection of address range comparator pair 5. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_6 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[6] controls the selection of address range comparator pair 6. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + RANGE_7 + Address range field. Selects which address range comparator pairs are in use with branch broadcasting. + Each field represents an address range comparator pair, so field[7] controls the selection of address range comparator pair 7. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected. + 0x0 + + + Enabled + The address range that address range comparator pair n defines, is selected. + 0x1 + + + + + + + TRCTRACEIDR + Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. + 0x40 + read-write + 0x00000000 + 0x20 + + + TRACEID + Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. + 0 + 6 + + + + + TRCQCTLR + Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. + 0x44 + read-write + 0x00000000 + 0x20 + + + RANGE_0 + Specifies the address range comparators to be used for controlling Q elements. + 0 + 0 + + + Disabled + Address range comparator 0 is disabled. + 0x0 + + + Enabled + Address range comparator 0 is selected for use. + 0x1 + + + + + RANGE_1 + Specifies the address range comparators to be used for controlling Q elements. + 1 + 1 + + + Disabled + Address range comparator 1 is disabled. + 0x0 + + + Enabled + Address range comparator 1 is selected for use. + 0x1 + + + + + RANGE_2 + Specifies the address range comparators to be used for controlling Q elements. + 2 + 2 + + + Disabled + Address range comparator 2 is disabled. + 0x0 + + + Enabled + Address range comparator 2 is selected for use. + 0x1 + + + + + RANGE_3 + Specifies the address range comparators to be used for controlling Q elements. + 3 + 3 + + + Disabled + Address range comparator 3 is disabled. + 0x0 + + + Enabled + Address range comparator 3 is selected for use. + 0x1 + + + + + RANGE_4 + Specifies the address range comparators to be used for controlling Q elements. + 4 + 4 + + + Disabled + Address range comparator 4 is disabled. + 0x0 + + + Enabled + Address range comparator 4 is selected for use. + 0x1 + + + + + RANGE_5 + Specifies the address range comparators to be used for controlling Q elements. + 5 + 5 + + + Disabled + Address range comparator 5 is disabled. + 0x0 + + + Enabled + Address range comparator 5 is selected for use. + 0x1 + + + + + RANGE_6 + Specifies the address range comparators to be used for controlling Q elements. + 6 + 6 + + + Disabled + Address range comparator 6 is disabled. + 0x0 + + + Enabled + Address range comparator 6 is selected for use. + 0x1 + + + + + RANGE_7 + Specifies the address range comparators to be used for controlling Q elements. + 7 + 7 + + + Disabled + Address range comparator 7 is disabled. + 0x0 + + + Enabled + Address range comparator 7 is selected for use. + 0x1 + + + + + MODE + Selects whether the address range comparators selected by the RANGE field indicate +address ranges where the trace unit is permitted to generate Q elements or address ranges +where the trace unit is not permitted to generate Q elements: + 8 + 8 + + + Exclude + Exclude mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit cannot generate Q elements. If no +ranges are selected, Q elements are permitted across the entire memory map. + 0x0 + + + Include + Include mode. The address range comparators selected by the RANGE field +indicate address ranges where the trace unit can generate Q elements. If all the +implemented bits in RANGE are set to 0 then Q elements are disabled. + 0x1 + + + + + + + TRCVICTLR + Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic. + 0x080 + read-write + 0x00000000 + 0x20 + + + EVENT_SEL + Select which resource number should be filtered. + 0 + 4 + + + Disabled + This event is not filtered. + 0x00 + + + Enabled + This event is filtered. + 0x01 + + + + + SSSTATUS + When TRCIDR4.NUMACPAIRS &gt; 0 or TRCIDR4.NUMPC &gt; 0, this bit returns the status of the start/stop logic. + 9 + 9 + + + Stopped + The start/stop logic is in the stopped state. + 0x0 + + + Started + The start/stop logic is in the started state. + 0x1 + + + + + TRCRESET + Controls whether a trace unit must trace a Reset exception. + 10 + 10 + + + Disabled + The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. + 0x0 + + + Enabled + The trace unit always traces a Reset exception. + 0x1 + + + + + TRCERR + When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. + 11 + 11 + + + Disabled + The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. + 0x0 + + + Enabled + The trace unit always traces a System error exception, regardless of the value of ViewInst. + 0x1 + + + + + EXLEVEL0_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 16 + 16 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 17 + 17 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 18 + 18 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_S + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 19 + 19 + + + Disabled + The trace unit does not generate instruction trace, in Secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Secure state, for Exception level 3. + 0x0 + + + + + EXLEVEL0_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. + 20 + 20 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 0. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 0. + 0x0 + + + + + EXLEVEL1_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. + 21 + 21 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 1. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 1. + 0x0 + + + + + EXLEVEL2_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. + 22 + 22 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 2. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 2. + 0x0 + + + + + EXLEVEL3_NS + In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. + 23 + 23 + + + Disabled + The trace unit does not generate instruction trace, in Non-secure state, for Exception level 3. + 0x1 + + + Enabled + The trace unit generates instruction trace, in Non-secure state, for Exception level 3. + 0x0 + + + + + + + TRCVIIECTLR + ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x084 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 0 + 0 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 1 + 1 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 2 + 2 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 3 + 3 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 4 + 4 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 5 + 5 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 6 + 6 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + 7 + 7 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst include control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator pair 0 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 0 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator pair 1 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 1 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator pair 2 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 2 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator pair 3 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 3 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator pair 4 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 4 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator pair 5 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 5 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator pair 6 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 6 defines, is selected for ViewInst exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator pair 7 defines, is not selected for ViewInst exclude control. + 0x0 + + + Enabled + The address range that address range comparator pair 7 defines, is selected for ViewInst exclude control. + 0x1 + + + + + + + TRCVISSCTLR + Use this to set, or read, the single address comparators that control the ViewInst start/stop +logic. The start/stop logic is active for an instruction which causes a start and remains active +up to and including an instruction which causes a stop, and then the start/stop logic becomes +inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x088 + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected as a start resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 16 + 16 + + + Disabled + The single address comparator 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 17 + 17 + + + Disabled + The single address comparator 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 18 + 18 + + + Disabled + The single address comparator 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 19 + 19 + + + Disabled + The single address comparator 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 20 + 20 + + + Disabled + The single address comparator 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 21 + 21 + + + Disabled + The single address comparator 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 22 + 22 + + + Disabled + The single address comparator 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace + 23 + 23 + + + Disabled + The single address comparator 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single address comparator 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVIPCSSCTLR + Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. + 0x08C + read-write + 0x00000000 + 0x20 + + + START_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 0 + 0 + + + Disabled + The single PE comparator input 0, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a start resource. + 0x1 + + + + + START_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 1 + 1 + + + Disabled + The single PE comparator input 1, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a start resource. + 0x1 + + + + + START_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 2 + 2 + + + Disabled + The single PE comparator input 2, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a start resource. + 0x1 + + + + + START_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 3 + 3 + + + Disabled + The single PE comparator input 3, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a start resource. + 0x1 + + + + + START_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 4 + 4 + + + Disabled + The single PE comparator input 4, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a start resource. + 0x1 + + + + + START_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 5 + 5 + + + Disabled + The single PE comparator input 5, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a start resource. + 0x1 + + + + + START_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 6 + 6 + + + Disabled + The single PE comparator input 6, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a start resource. + 0x1 + + + + + START_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace + 7 + 7 + + + Disabled + The single PE comparator input 7, is not selected as a start resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a start resource. + 0x1 + + + + + STOP_0 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 16 + 16 + + + Disabled + The single PE comparator input 0, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 0, is selected as a stop resource. + 0x1 + + + + + STOP_1 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 17 + 17 + + + Disabled + The single PE comparator input 1, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 1, is selected as a stop resource. + 0x1 + + + + + STOP_2 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 18 + 18 + + + Disabled + The single PE comparator input 2, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 2, is selected as a stop resource. + 0x1 + + + + + STOP_3 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 19 + 19 + + + Disabled + The single PE comparator input 3, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 3, is selected as a stop resource. + 0x1 + + + + + STOP_4 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 20 + 20 + + + Disabled + The single PE comparator input 4, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 4, is selected as a stop resource. + 0x1 + + + + + STOP_5 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 21 + 21 + + + Disabled + The single PE comparator input 5, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 5, is selected as a stop resource. + 0x1 + + + + + STOP_6 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 22 + 22 + + + Disabled + The single PE comparator input 6, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 6, is selected as a stop resource. + 0x1 + + + + + STOP_7 + Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. + 23 + 23 + + + Disabled + The single PE comparator input 7, is not selected as a stop resource. + 0x0 + + + Enabled + The single PE comparator input 7, is selected as a stop resource. + 0x1 + + + + + + + TRCVDCTLR + Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. + 0x0A0 + read-write + 0x00000000 + 0x20 + + + EVENT_0 + Event unit enable bit. + 0 + 0 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_1 + Event unit enable bit. + 1 + 1 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_2 + Event unit enable bit. + 2 + 2 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_3 + Event unit enable bit. + 3 + 3 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_4 + Event unit enable bit. + 4 + 4 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_5 + Event unit enable bit. + 5 + 5 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_6 + Event unit enable bit. + 6 + 6 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + EVENT_7 + Event unit enable bit. + 7 + 7 + + + Disabled + The trace event is not selected for trace filtering. + 0x0 + + + Enabled + The trace event is selected for trace filtering. + 0x1 + + + + + SPREL + Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). + 8 + 9 + + + Enabled + The trace unit does not affect the tracing of SP-relative transfers. + 0x0 + + + DataOnly + The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element. + 0x2 + + + Disabled + The trace unit does not trace the address or value portions of SP-relative transfers. + 0x3 + + + + + PCREL + Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). + 10 + 10 + + + Enabled + The trace unit does not affect the tracing of PC-relative transfers. + 0x0 + + + Disabled + The trace unit does not trace the address or value portions of PC-relative transfers. + 0x1 + + + + + TBI + Controls which information a trace unit populates in bits[63:56] of the data address. + 11 + 11 + + + SignExtend + The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value. + 0x0 + + + Copy + The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. + 0x1 + + + + + TRCEXDATA + Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs. + 12 + 12 + + + Disabled + Exception and exception return data transfers are not traced. + 0x0 + + + Enabled + Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced. + 0x1 + + + + + + + TRCVDSACCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A4 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Selects which single address comparators are in use with ViewData include control. + 0 + 0 + + + Disabled + The single address comparator 0, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 0, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Selects which single address comparators are in use with ViewData include control. + 1 + 1 + + + Disabled + The single address comparator 1, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 1, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Selects which single address comparators are in use with ViewData include control. + 2 + 2 + + + Disabled + The single address comparator 2, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 2, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Selects which single address comparators are in use with ViewData include control. + 3 + 3 + + + Disabled + The single address comparator 3, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 3, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Selects which single address comparators are in use with ViewData include control. + 4 + 4 + + + Disabled + The single address comparator 4, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 4, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Selects which single address comparators are in use with ViewData include control. + 5 + 5 + + + Disabled + The single address comparator 5, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 5, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Selects which single address comparators are in use with ViewData include control. + 6 + 6 + + + Disabled + The single address comparator 6, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 6, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Selects which single address comparators are in use with ViewData include control. + 7 + 7 + + + Disabled + The single address comparator 7, is not selected for ViewData include control. + 0x0 + + + Enabled + The single address comparator 7, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Selects which single address comparators are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The single address comparator 0, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 0, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Selects which single address comparators are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The single address comparator 1, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 1, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Selects which single address comparators are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The single address comparator 2, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 2, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Selects which single address comparators are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The single address comparator 3, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 3, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Selects which single address comparators are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The single address comparator 4, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 4, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Selects which single address comparators are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The single address comparator 5, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 5, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Selects which single address comparators are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The single address comparator 6, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 6, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Selects which single address comparators are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The single address comparator 7, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The single address comparator 7, s selected for ViewData exclude control. + 0x1 + + + + + + + TRCVDARCCTLR + ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. + 0x0A8 + read-write + 0x00000000 + 0x20 + + + INCLUDE_0 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 0 + 0 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_1 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 1 + 1 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_2 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 2 + 2 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_3 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 3 + 3 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_4 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 4 + 4 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_5 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 5 + 5 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_6 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 6 + 6 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, is selected for ViewData include control. + 0x1 + + + + + INCLUDE_7 + Include range field. Selects which address range comparator pairs are in use with ViewData include control. + 7 + 7 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData include control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, is selected for ViewData include control. + 0x1 + + + + + EXCLUDE_0 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 16 + 16 + + + Disabled + The address range that address range comparator 0 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 0 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_1 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 17 + 17 + + + Disabled + The address range that address range comparator 1 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 1 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_2 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 18 + 18 + + + Disabled + The address range that address range comparator 2 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 2 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_3 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 19 + 19 + + + Disabled + The address range that address range comparator 3 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 3 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_4 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 20 + 20 + + + Disabled + The address range that address range comparator 4 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 4 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_5 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 21 + 21 + + + Disabled + The address range that address range comparator 5 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 5 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_6 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 22 + 22 + + + Disabled + The address range that address range comparator 6 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 6 defines, s selected for ViewData exclude control. + 0x1 + + + + + EXCLUDE_7 + Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. + 23 + 23 + + + Disabled + The address range that address range comparator 7 defines, is not selected for ViewData exclude control. + 0x0 + + + Enabled + The address range that address range comparator 7 defines, s selected for ViewData exclude control. + 0x1 + + + + + + + 0x3 + 0x4 + TRCSEQEVR[%s] + Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x100 + read-write + 0x00000000 + 0x20 + + + F_0 + Forward field. + 0 + 0 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_1 + Forward field. + 1 + 1 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_2 + Forward field. + 2 + 2 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_3 + Forward field. + 3 + 3 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_4 + Forward field. + 4 + 4 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_5 + Forward field. + 5 + 5 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_6 + Forward field. + 6 + 6 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + F_7 + Forward field. + 7 + 7 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n to state n+1. + 0x1 + + + + + B_0 + Backward field. + 8 + 8 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_1 + Backward field. + 9 + 9 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_2 + Backward field. + 10 + 10 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_3 + Backward field. + 11 + 11 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_4 + Backward field. + 12 + 12 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_5 + Backward field. + 13 + 13 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_6 + Backward field. + 14 + 14 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + B_7 + Backward field. + 15 + 15 + + + Disabled + The trace event does not affect the sequencer. + 0x0 + + + Enabled + When the event occurs then the sequencer state moves from state n+1 to state n. + 0x1 + + + + + + + TRCSEQRSTEVR + Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENT + Select which event should reset the sequencer. + 0 + 7 + + + + + TRCSEQSTR + Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x11C + read-write + 0x00000000 + 0x20 + + + STATE + Sets or returns the state of the sequencer. + 0 + 1 + + + State0 + The sequencer is in state 0. + 0x0 + + + State1 + The sequencer is in state 1. + 0x1 + + + State2 + The sequencer is in state 2. + 0x2 + + + State3 + The sequencer is in state 3. + 0x3 + + + + + + + TRCEXTINSELR + Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. + 0x120 + read-write + 0x00000000 + 0x20 + + + SEL_0 + Each field in this collection selects an external input as a resource for the trace unit. + 0 + 7 + + + SEL_1 + Each field in this collection selects an external input as a resource for the trace unit. + 8 + 15 + + + SEL_2 + Each field in this collection selects an external input as a resource for the trace unit. + 16 + 23 + + + SEL_3 + Each field in this collection selects an external input as a resource for the trace unit. + 24 + 31 + + + + + 0x4 + 0x4 + TRCCNTRLDVR[%s] + Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x140 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n. + 0 + 15 + + + + + 0x4 + 0x4 + TRCCNTCTLR[%s] + Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. + 0x150 + read-write + 0x00000000 + 0x20 + + + CNTEVENT + Selects an event, that when it occurs causes counter n to decrement. + 0 + 7 + + + RLDEVENT + Selects an event, that when it occurs causes a reload event for counter n. + 8 + 15 + + + RLDSELF + Controls whether a reload event occurs for counter n, when counter n reaches zero. + 16 + 16 + + + Disabled + The counter is in Normal mode. + 0x0 + + + Enabled + The counter is in Self-reload mode. + 0x1 + + + + + CNTCHAIN + For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. + 17 + 17 + + + Disabled + Counter n does not decrement when a reload event for counter n-1 occurs. + 0x0 + + + Enabled + Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. + 0x1 + + + + + + + 0x4 + 0x4 + TRCCNTVR[%s] + Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle. + 0x160 + read-write + 0x00000000 + 0x20 + + + VALUE + Contains the count value of counter n. + 0 + 15 + + + + + 0x1E + 0x4 + TRCRSCTLR[%s] + Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE +behavior of the resource selector occurs, so the resource selector might fire +unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. + 0x200 + read-write + 0x00000000 + 0x20 + + + EN + Trace unit enable bit + 0 + 0 + + + Disabled + The trace unit is disabled. All trace resources are inactive and no trace is generated. + 0x0 + + + Enabled + The trace unit is enabled. + 0x1 + + + + + + + TRCSSCCR0 + Controls the single-shot comparator. + 0x280 + read-write + 0x00000000 + 0x20 + + + RST + Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected + 24 + 24 + + + Disabled + Multiple matches can not be detected. + 0x0 + + + Enabled + Multiple matches can occur. + 0x1 + + + + + + + TRCSSCSR0 + Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. + 0x2A0 + read-write + 0x00000000 + 0x20 + + + INST + Instruction address comparator support + 0 + 0 + + + False + Single-shot instruction address comparisons not supported. + 0x0 + + + True + Single-shot instruction address comparisons supported. + 0x1 + + + + + DA + Data address comparator support + 1 + 1 + + + False + Data address comparisons not supported. + 0x0 + + + True + Data address comparisons supported. + 0x1 + + + + + DV + Data value comparator support + 2 + 2 + + + False + Data value comparisons not supported. + 0x0 + + + True + Data value comparisons supported. + 0x1 + + + + + PC + Process counter value comparator support + 3 + 3 + + + False + Process counter value comparisons not supported. + 0x0 + + + True + Process counter value comparisons supported. + 0x1 + + + + + STATUS + Single-shot status. This indicates whether any of the selected comparators have matched. + 31 + 31 + + + NoMatch + Match has not occurred. + 0x0 + + + Match + Match has occurred at least once. + 0x1 + + + + + + + TRCSSPCICR0 + Selects the processor comparator inputs for Single-shot control. + 0x2C0 + read-write + 0x00000000 + 0x20 + + + PC_0 + Selects processor comparator 0 inputs for Single-shot control + 0 + 0 + + + Disabled + Processor comparator 0 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 0 is selected for Single-shot control. + 0x1 + + + + + PC_1 + Selects processor comparator 1 inputs for Single-shot control + 1 + 1 + + + Disabled + Processor comparator 1 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 1 is selected for Single-shot control. + 0x1 + + + + + PC_2 + Selects processor comparator 2 inputs for Single-shot control + 2 + 2 + + + Disabled + Processor comparator 2 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 2 is selected for Single-shot control. + 0x1 + + + + + PC_3 + Selects processor comparator 3 inputs for Single-shot control + 3 + 3 + + + Disabled + Processor comparator 3 is not selected for Single-shot control. + 0x0 + + + Enabled + Processor comparator 3 is selected for Single-shot control. + 0x1 + + + + + + + TRCPDCR + Controls the single-shot comparator. + 0x310 + read-write + 0x00000000 + 0x20 + + + PU + Power up request, to request that power to ETM and access to the trace registers is maintained. + 24 + 24 + + + Disabled + Power not requested. + 0x0 + + + Enabled + Power requested. + 0x1 + + + + + + + TRCPDSR + Indicates the power down status of the ETM. + 0x314 + read-write + 0x00000000 + 0x20 + + + POWER + Indicates ETM is powered up + 0 + 0 + + + NotPoweredUp + ETM is not powered up. All registers are not accessible. + 0x0 + + + PoweredUp + ETM is powered up. All registers are accessible. + 0x1 + + + + + STICKYPD + Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR + 1 + 1 + + + NotPoweredDown + Trace register power has not been removed since the TRCPDSR was last read. + 0x0 + + + PoweredDown + Trace register power has been removed since the TRCPDSR was last read. + 0x1 + + + + + + + TRCITATBIDR + Sets the state of output pins. + 0xEE4 + read-write + 0x00000000 + 0x20 + + + ID_0 + Drives the ATIDMI[0] output pin. + 0 + 0 + + + ID_1 + Drives the ATIDMI[1] output pin. + 1 + 1 + + + ID_2 + Drives the ATIDMI[2] output pin. + 2 + 2 + + + ID_3 + Drives the ATIDMI[3] output pin. + 3 + 3 + + + ID_4 + Drives the ATIDMI[4] output pin. + 4 + 4 + + + ID_5 + Drives the ATIDMI[5] output pin. + 5 + 5 + + + ID_6 + Drives the ATIDMI[6] output pin. + 6 + 6 + + + + + TRCITIATBINR + Reads the state of the input pins. + 0xEF4 + read-write + 0x00000000 + 0x20 + + + ATVALID + Returns the value of the ATVALIDMI input pin. + 0 + 0 + + + AFREADY + Returns the value of the AFREADYMI input pin. + 1 + 1 + + + + + TRCITIATBOUTR + Sets the state of the output pins. + 0xEFC + read-write + 0x00000000 + 0x20 + + + ATVALID + Drives the ATVALIDMI output pin. + 0 + 0 + + + AFREADY + Drives the AFREADYMI output pin. + 1 + 1 + + + + + TRCITCTRL + Enables topology detection or integration testing, by putting ETM-M33 into integration mode. + 0xF00 + read-write + 0x00000000 + 0x20 + + + IME + Integration mode enable + 0 + 0 + + + Disabled + ETM is not in integration mode. + 0x0 + + + Enabled + ETM is in integration mode. + 0x1 + + + + + + + TRCCLAIMSET + Sets bits in the claim tag and determines the number of claim tag bits implemented. + 0xFA0 + read-write + 0x00000000 + 0x20 + + + SET_0 + Claim tag set register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Claim + Set claim tag 0. + 0x1 + + + + + SET_1 + Claim tag set register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Claim + Set claim tag 1. + 0x1 + + + + + SET_2 + Claim tag set register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Claim + Set claim tag 2. + 0x1 + + + + + SET_3 + Claim tag set register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Claim + Set claim tag 3. + 0x1 + + + + + + + TRCCLAIMCLR + Clears bits in the claim tag and determines the current value of the claim tag. + 0xFA4 + read-write + 0x00000000 + 0x20 + + + CLR_0 + Claim tag clear register + 0 + 0 + + read + + NotSet + Claim tag 0 is not set. + 0x0 + + + Set + Claim tag 0 is set. + 0x1 + + + + write + + Clear + Clear claim tag 0. + 0x1 + + + + + CLR_1 + Claim tag clear register + 1 + 1 + + read + + NotSet + Claim tag 1 is not set. + 0x0 + + + Set + Claim tag 1 is set. + 0x1 + + + + write + + Clear + Clear claim tag 1. + 0x1 + + + + + CLR_2 + Claim tag clear register + 2 + 2 + + read + + NotSet + Claim tag 2 is not set. + 0x0 + + + Set + Claim tag 2 is set. + 0x1 + + + + write + + Clear + Clear claim tag 2. + 0x1 + + + + + CLR_3 + Claim tag clear register + 3 + 3 + + read + + NotSet + Claim tag 3 is not set. + 0x0 + + + Set + Claim tag 3 is set. + 0x1 + + + + write + + Clear + Clear claim tag 3. + 0x1 + + + + + + + TRCAUTHSTATUS + Indicates the current level of tracing permitted by the system + 0xFB8 + read-write + 0x00000000 + 0x20 + + + NSID + Non-secure Invasive Debug + 0 + 1 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + NSNID + Non-secure Non-Invasive Debug + 2 + 3 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SID + Secure Invasive Debug + 4 + 5 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + SNID + Secure Non-Invasive Debug + 6 + 7 + + + NotImplemented + The feature is not implemented. + 0x0 + + + Implemented + The feature is implemented. + 0x1 + + + + + + + TRCDEVARCH + The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component + 0xFBC + read-only + 0x00000000 + 0x20 + + + ARCHID + Architecture ID + 0 + 15 + + + ETMv42 + Component is an ETMv4 component + 0x4A13 + + + + + REVISION + Architecture revision + 16 + 19 + + + v2 + Component is part of architecture 4.2 + 0x2 + + + + + PRESENT + This register is implemented + 20 + 20 + + + Absent + The register is not implemented. + 0x0 + + + Present + The register is implemented. + 0x1 + + + + + ARCHITECT + Defines the architect of the component + 21 + 31 + + + Arm + This peripheral was architected by Arm. + 0x23B + + + + + + + TRCDEVTYPE + Controls the single-shot comparator. + 0xFCC + read-only + 0x00000000 + 0x20 + + + MAJOR + The main type of the component + 0 + 3 + + + TraceSource + Peripheral is a trace source. + 0x3 + + + + + SUB + The sub-type of the component + 4 + 7 + + + ProcessorTrace + Peripheral is a processor trace source. + 0x1 + + + + + + + 0x8 + 0x4 + TRCPIDR[%s] + Description collection: Coresight peripheral identification registers. + 0xFD0 + read-write + 0x00000000 + 0x20 + + + 0x4 + 0x4 + TRCCIDR[%s] + Description collection: Coresight component identification registers. + 0xFF0 + read-write + 0x00000000 + 0x20 + + + + + CTI_S + Cross-Trigger Interface control 2 + 0xE0042000 + + + + + CPUC_S + CM33 SubSystem + 0xE0080000 + CM33SS + + + + 0 + 0x1000 + registers + + CM33SS + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIOC + An invalid operation exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUDZC + A floating-point divide-by-zero exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUOFC + A floating-point overflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUUFC + A floating-point underflow exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIXC + A floating-point inexact exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_FPUIDC + A floating-point input denormal exception has occurred in the FPU. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LOCK + Register to lock the certain parts of the CPU from being modified. + 0x500 + read-write + 0x00000000 + 0x20 + + + LOCKVTORAIRCRS + Locks both the Vector table Offset Register (VTOR) and + Application Interrupt and Reset Control Register (AIRCR) for secure mode. + 0 + 0 + + + NotLocked + Both VTOR and AIRCR can be changed. + 0x0 + + + Locked + Prevents changes to both VTOR and AIRCR. + 0x1 + + + + + LOCKVTORNS + Locks the Vector table Offset Register (VTOR) for non-secure mode. + 1 + 1 + + + NotLocked + VTOR can be changed. + 0x0 + + + Locked + Prevents changes to VTOR. + 0x1 + + + + + LOCKMPUS + Locks the Memory Protection Unit (MPU) for secure mode. + 2 + 2 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKMPUNS + Locks the Memory Protection Unit (MPU) for non secure mode. + 3 + 3 + + + NotLocked + MPU registers can be changed. + 0x0 + + + Locked + Prevents changes to MPU registers. + 0x1 + + + + + LOCKSAU + Locks the Security Attribution Unit (SAU) + 4 + 4 + + + NotLocked + SAU registers can be changed. + 0x0 + + + Locked + Prevents changes to SAU registers. + 0x1 + + + + + + + CPUID + The identifier for the CPU in this subsystem. + 0x504 + read-only + 0x00000000 + 0x20 + + + CPUID + The CPU identifier. + 0 + 31 + + + + + + + ICACHE_S + Cache 0 + 0xE0082000 + CACHE + + + + 0 + 0x1000 + registers + + CACHE + 0x20 + + + TASKS_SAVE + Save the cache state to a retained memory space. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SAVE + Save the cache state to a retained memory space. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESTORE + Restore the cache state from a retained memory space. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESTORE + Restore the cache state from a retained memory space. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_INVALIDATECACHE + Invalidate the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEANCACHE + Clean the cache. + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEANCACHE + Clean the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSHCACHE + Flush the cache. + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHCACHE + Flush the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_INVALIDATELINE + Invalidate the line. + 0x014 + write-only + 0x00000000 + 0x20 + + + + TASKS_INVALIDATELINE + Invalidate the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEANLINE + Clean the line. + 0x018 + write-only + 0x00000000 + 0x20 + + + + TASKS_CLEANLINE + Clean the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSHLINE + Flush the line. + 0x01C + write-only + 0x00000000 + 0x20 + + + + TASKS_FLUSHLINE + Flush the line. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_ERASE + Erase the cache. + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_ERASE + Erase the cache. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_DONE + Save or Restore task is done. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + Save or Restore task is done. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + DONE + Enable or disable interrupt for event DONE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DONE + Write '1' to enable interrupt for event DONE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DONE + Write '1' to disable interrupt for event DONE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + DONE + Read pending status of interrupt for event DONE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + Status of the cache activities. + 0x400 + read-only + 0x00000000 + 0x20 + + + BUSY + Busy status. + 0 + 0 + + + Ready + Activity is done and ready for the next activity. + 0x0 + + + Busy + Activity is in progress. + 0x1 + + + + + + + ENABLE + Enable cache. + 0x404 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable cache + 0 + 0 + + + Disabled + Disable cache + 0x0 + + + Enabled + Enable cache + 0x1 + + + + + + + LINEADDR + Memory address covered by the line to be maintained. + 0x410 + read-write + 0x00000000 + 0x20 + + + ADDR + Address. + 0 + 31 + + + + + PROFILING + Unspecified + CACHE_PROFILING + read-write + 0x414 + + ENABLE + Enable the profiling counters. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable the profiling counters + 0 + 0 + + + Disable + Disable profiling + 0x0 + + + Enable + Enable profiling + 0x1 + + + + + + + CLEAR + Clear the profiling counters. + 0x004 + write-only + 0x00000000 + 0x20 + + + CLEAR + Clearing the profiling counters + 0 + 0 + + + Clear + Clear the profiling counters + 0x1 + + + + + + + HIT + The cache hit counter for cache region. + 0x008 + read-only + 0x00000000 + 0x20 + + + HITS + Number of cache hits + 0 + 31 + + + + + MISS + The cache miss counter for cache region. + 0x00C + read-only + 0x00000000 + 0x20 + + + MISSES + Number of cache misses + 0 + 31 + + + + + LMISS + The cache line miss counter for cache region. + 0x010 + read-only + 0x00000000 + 0x20 + + + LMISSES + Number of cache line misses + 0 + 31 + + + + + READS + Number of reads for cache region. + 0x014 + read-only + 0x00000000 + 0x20 + + + READS + Number of reads for cache region. + 0 + 31 + + + + + WRITES + Number of writes for cache region. + 0x018 + read-only + 0x00000000 + 0x20 + + + WRITES + Number of writes for cache region. + 0 + 31 + + + + + + DEBUGLOCK + Lock debug mode. + 0x430 + read-writeonce + 0x00000000 + 0x20 + + + DEBUGLOCK + Lock debug mode + 0 + 0 + + + Unlocked + Debug mode unlocked + 0x0 + + + Locked + Debug mode locked. Ignores any other value written. + 0x1 + + + + + + + WRITELOCK + Lock cache updates. + 0x434 + read-write + 0x00000000 + 0x20 + + + WRITELOCK + Lock cache updates + 0 + 0 + + + Unlocked + Cache updates unlocked + 0x0 + + + Locked + Cache updates locked + 0x1 + + + + + + + + + DCACHE_S + Cache 1 + 0xE0083000 + + + + + SPU000_S + System protection unit 0 + 0x53000000 + SPU + + + + 0 + 0x1000 + registers + + + SPU000 + 0 + + SPU + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_PERIPHACCERR + A security violation has been detected on one or several peripherals + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Enable or disable interrupt for event PERIPHACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to enable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + PERIPHACCERR + Write '1' to disable interrupt for event PERIPHACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + PERIPHACCERR + Read pending status of interrupt for event PERIPHACCERR + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + PERIPHACCERR + Unspecified + SPU_PERIPHACCERR + read-write + 0x404 + + ADDRESS + Address of the transaction that caused first error. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Address + 0 + 15 + + + + + INFO + Information about the transaction that caused first error. + 0x004 + read-only + 0x00000000 + 0x20 + + + OWNERID + OWNERID + 0 + 3 + + + + + + 32 + 0x004 + PERIPH[%s] + Unspecified + SPU_PERIPH + read-write + 0x500 + + PERM + Description cluster: Get and set the applicable access permissions for the peripheral slave index n + 0x000 + read-write + 0x8000000A + 0x20 + + + SECUREMAPPING + Read capabilities for TrustZone Cortex-M secure attribute + 0 + 1 + read-only + + + NonSecure + This peripheral is always accessible as a non-secure peripheral + 0x0 + + + Secure + This peripheral is always accessible as a secure peripheral + 0x1 + + + UserSelectable + Non-secure or secure attribute for this peripheral is defined by the PERIPH[n].PERM register + 0x2 + + + Split + This peripheral implements the split security mechanism. + 0x3 + + + + + DMA + Read the peripheral DMA capabilities + 2 + 3 + read-only + + + NoDMA + Peripheral has no DMA capability + 0x0 + + + NoSeparateAttribute + Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral + 0x1 + + + SeparateAttribute + Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral + 0x2 + + + + + SECATTR + Peripheral security mapping + 4 + 4 + + + Secure + Peripheral is mapped in secure peripheral address space + 0x1 + + + NonSecure + If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. + 0x0 + + + + + DMASEC + Security attribution for the DMA transfer + 5 + 5 + + + Secure + DMA transfers initiated by this peripheral have the secure attribute set + 0x1 + + + NonSecure + DMA transfers initiated by this peripheral have the non-secure attribute set + 0x0 + + + + + LOCK + Register lock + 8 + 8 + oneToSet + + + Unlocked + This register can be updated + 0x0 + + + Locked + The content of this register can not be changed until the next reset + 0x1 + + + + + OWNERID + Peripheral owner ID + 16 + 19 + + + OWNERPROG + Indicates if OWNERID is programmable or not + 30 + 30 + read-only + + + NotProgrammable + OWNERID is not programmable + 0x0 + + + Programmable + OWNERID is programmable + 0x1 + + + + + PRESENT + Indicates if a peripheral is present with peripheral slave index n + 31 + 31 + read-only + + + NotPresent + Peripheral is not present + 0x0 + + + IsPresent + Peripheral is present + 0x1 + + + + + + + + FEATURE + Unspecified + SPU_FEATURE + read-write + 0x600 + + STRUCT0 + Unspecified + SPU_FEATURE_STRUCT0 + read-write + 0x000 + + IPCT + Unspecified + SPU_FEATURE_STRUCT0_IPCT + read-write + 0x000 + + 0x18 + 0x4 + CH[%s] + Description collection: Configuration of features for channel n of IPCT + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt n of IPCT + 0x060 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + DPPIC + Unspecified + SPU_FEATURE_STRUCT0_DPPIC + read-write + 0x080 + + 0x18 + 0x4 + CH[%s] + Description collection: Configuration of features for channel n of DPPIC + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + CHG[%s] + Description collection: Configuration of features for channel group n of DPPIC + 0x060 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + 2 + 0x040 + GPIOTE[%s] + Unspecified + SPU_FEATURE_STRUCT0_GPIOTE + read-write + 0x100 + + 0x8 + 0x4 + CH[%s] + Description collection: Configuration of features for channel o of GPIOTE[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x8 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt o of GPIOTE[n] + 0x020 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + 14 + 0x080 + GPIO[%s] + Unspecified + GPIO + read-write + 0x200 + + 0x20 + 0x4 + PIN[%s] + Description collection: Configuration of features for GPIO[n] PIN[o] + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + STRUCT0 + Unspecified + STRUCT0 + GPIO[%s] + read-write + 0x200 + + GRTC + Unspecified + STRUCT0_GRTC + read-write + 0x000 + + 0x10 + 0x4 + CC[%s] + Description collection: Configuration of features for CC n of GRTC + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + PWMCONFIG + Configuration of feature for PWMCONFIG of GRTC + 0x074 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + CLK + Configuration of features for CLKOUT/CLKCFG of GRTC + 0x078 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + SYSCOUNTER + Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC + 0x07C + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0xD + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt n of GRTC + 0x080 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + 2 + 0x00C + MRAMC[%s] + Unspecified + MRAMC + GPIO[%s] + read-write + 0x200 + + WAITSTATES + Description cluster: Configuration of features for WAITSTATES of MRAMC [n] + 0x400 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + AUTODPOWERDOWN + Description cluster: Configuration of features for POWER.AUTODPOWERDOWN of MRAMC [n] + 0x404 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + READY + Description cluster: Configuration of features for READY and READYNEXT of MRAMC [n] + 0x408 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + BELLS + Unspecified + SPU_FEATURE_BELLS + STRUCT0 + read-write + 0x000 + + 8 + 0x0C0 + PROCESSOR[%s] + Unspecified + SPU_FEATURE_BELLS_PROCESSOR + read-write + 0x000 + + 0x10 + 0x4 + TASKS[%s] + Description collection: Configuration of features for tasks pair [(o * 2) + 1:o * 2] of Processor ID n + 0x000 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x10 + 0x4 + EVENTS[%s] + Description collection: Configuration of features for events pair [(o * 2) + 1:o * 2] of Processor ID n + 0x040 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + 0x10 + 0x4 + INTERRUPT[%s] + Description collection: Configuration of features for interrupt register pair [(o * 2) + 1:o * 2] of Processor ID n + 0x080 + read-write + 0x00000000 + 0x20 + + + SECATTR + SECATTR feature + 4 + 4 + + + NonSecure + Feature is available for non-secure usage + 0x0 + + + Secure + Feature is reserved for secure usage + 0x1 + + + + + LOCK + LOCK feature + 8 + 8 + oneToSet + + + Unlocked + Feature permissions can be updated + 0x0 + + + Locked + Feature permissions can not be changed until the next reset + 0x1 + + + + + OWNERID + Feature owner ID + 16 + 19 + + + + + + + + + + MPC_S + Memory Privilege Controller + 0x53001000 + MPC + + + + 0 + 0x1000 + registers + + + MPC + 1 + + MPC + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_MEMACCERR + Memory Access Error event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Enable or disable interrupt for event MEMACCERR + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to enable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + MEMACCERR + Write '1' to disable interrupt for event MEMACCERR + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MEMACCERR + Memory Access Error status registers + MPC_MEMACCERR + read-write + 0x400 + + ADDRESS + Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is active. + 0x000 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Target address for erroneous access + 0 + 31 + + + + + INFO + Access information for the transaction that triggered a memory access error. Register content won't be changed as long as MEMACCERR event is active. + 0x004 + read-only + 0x00000000 + 0x20 + + + OWNERID + Owner identifier of the erroneous access + 0 + 3 + + + MASTERPORT + Master port where erroneous access is detected + 4 + 8 + + + READ + Read bit of bus access + 12 + 12 + + + Set + Read access bit was set + 0x1 + + + NotSet + Read access bit was not set + 0x0 + + + + + WRITE + Write bit of bus access + 13 + 13 + + + Set + Write access bit was set + 0x1 + + + NotSet + Write access bit was not set + 0x0 + + + + + EXECUTE + Execute bit of bus access + 14 + 14 + + + Set + Execute access bit was set + 0x1 + + + NotSet + Execute access bit was not set + 0x0 + + + + + SECURE + Secure bit of bus access + 15 + 15 + + + Set + Secure access bit was set + 0x1 + + + NotSet + Secure access bit was not set + 0x0 + + + + + ERRORSOURCE + Source of memory access error + 16 + 16 + + + MPC + Error was triggered by MPC module + 0x1 + + + Slave + Error was triggered by an AXI slave + 0x0 + + + + + + + + GLOBALSLAVE + Global slave master port connection information + MPC_GLOBALSLAVE + read-write + 0x410 + + MASTERPORT + Global slave connection information for master port + 0x000 + read-write + 0x00000000 + 0x20 + + + CONNECTION_0 + Global slave connection information for master port + 0 + 0 + + + Disabled + Master port 0 connection to global slave is disabled + 0x0 + + + Enabled + Master port 0 connection to global slave is enabled + 0x1 + + + + + CONNECTION_1 + Global slave connection information for master port + 1 + 1 + + + Disabled + Master port 1 connection to global slave is disabled + 0x0 + + + Enabled + Master port 1 connection to global slave is enabled + 0x1 + + + + + CONNECTION_2 + Global slave connection information for master port + 2 + 2 + + + Disabled + Master port 2 connection to global slave is disabled + 0x0 + + + Enabled + Master port 2 connection to global slave is enabled + 0x1 + + + + + CONNECTION_3 + Global slave connection information for master port + 3 + 3 + + + Disabled + Master port 3 connection to global slave is disabled + 0x0 + + + Enabled + Master port 3 connection to global slave is enabled + 0x1 + + + + + CONNECTION_4 + Global slave connection information for master port + 4 + 4 + + + Disabled + Master port 4 connection to global slave is disabled + 0x0 + + + Enabled + Master port 4 connection to global slave is enabled + 0x1 + + + + + CONNECTION_5 + Global slave connection information for master port + 5 + 5 + + + Disabled + Master port 5 connection to global slave is disabled + 0x0 + + + Enabled + Master port 5 connection to global slave is enabled + 0x1 + + + + + CONNECTION_6 + Global slave connection information for master port + 6 + 6 + + + Disabled + Master port 6 connection to global slave is disabled + 0x0 + + + Enabled + Master port 6 connection to global slave is enabled + 0x1 + + + + + CONNECTION_7 + Global slave connection information for master port + 7 + 7 + + + Disabled + Master port 7 connection to global slave is disabled + 0x0 + + + Enabled + Master port 7 connection to global slave is enabled + 0x1 + + + + + CONNECTION_8 + Global slave connection information for master port + 8 + 8 + + + Disabled + Master port 8 connection to global slave is disabled + 0x0 + + + Enabled + Master port 8 connection to global slave is enabled + 0x1 + + + + + CONNECTION_9 + Global slave connection information for master port + 9 + 9 + + + Disabled + Master port 9 connection to global slave is disabled + 0x0 + + + Enabled + Master port 9 connection to global slave is enabled + 0x1 + + + + + CONNECTION_10 + Global slave connection information for master port + 10 + 10 + + + Disabled + Master port 10 connection to global slave is disabled + 0x0 + + + Enabled + Master port 10 connection to global slave is enabled + 0x1 + + + + + CONNECTION_11 + Global slave connection information for master port + 11 + 11 + + + Disabled + Master port 11 connection to global slave is disabled + 0x0 + + + Enabled + Master port 11 connection to global slave is enabled + 0x1 + + + + + CONNECTION_12 + Global slave connection information for master port + 12 + 12 + + + Disabled + Master port 12 connection to global slave is disabled + 0x0 + + + Enabled + Master port 12 connection to global slave is enabled + 0x1 + + + + + CONNECTION_13 + Global slave connection information for master port + 13 + 13 + + + Disabled + Master port 13 connection to global slave is disabled + 0x0 + + + Enabled + Master port 13 connection to global slave is enabled + 0x1 + + + + + CONNECTION_14 + Global slave connection information for master port + 14 + 14 + + + Disabled + Master port 14 connection to global slave is disabled + 0x0 + + + Enabled + Master port 14 connection to global slave is enabled + 0x1 + + + + + CONNECTION_15 + Global slave connection information for master port + 15 + 15 + + + Disabled + Master port 15 connection to global slave is disabled + 0x0 + + + Enabled + Master port 15 connection to global slave is enabled + 0x1 + + + + + CONNECTION_16 + Global slave connection information for master port + 16 + 16 + + + Disabled + Master port 16 connection to global slave is disabled + 0x0 + + + Enabled + Master port 16 connection to global slave is enabled + 0x1 + + + + + CONNECTION_17 + Global slave connection information for master port + 17 + 17 + + + Disabled + Master port 17 connection to global slave is disabled + 0x0 + + + Enabled + Master port 17 connection to global slave is enabled + 0x1 + + + + + CONNECTION_18 + Global slave connection information for master port + 18 + 18 + + + Disabled + Master port 18 connection to global slave is disabled + 0x0 + + + Enabled + Master port 18 connection to global slave is enabled + 0x1 + + + + + CONNECTION_19 + Global slave connection information for master port + 19 + 19 + + + Disabled + Master port 19 connection to global slave is disabled + 0x0 + + + Enabled + Master port 19 connection to global slave is enabled + 0x1 + + + + + CONNECTION_20 + Global slave connection information for master port + 20 + 20 + + + Disabled + Master port 20 connection to global slave is disabled + 0x0 + + + Enabled + Master port 20 connection to global slave is enabled + 0x1 + + + + + CONNECTION_21 + Global slave connection information for master port + 21 + 21 + + + Disabled + Master port 21 connection to global slave is disabled + 0x0 + + + Enabled + Master port 21 connection to global slave is enabled + 0x1 + + + + + CONNECTION_22 + Global slave connection information for master port + 22 + 22 + + + Disabled + Master port 22 connection to global slave is disabled + 0x0 + + + Enabled + Master port 22 connection to global slave is enabled + 0x1 + + + + + CONNECTION_23 + Global slave connection information for master port + 23 + 23 + + + Disabled + Master port 23 connection to global slave is disabled + 0x0 + + + Enabled + Master port 23 connection to global slave is enabled + 0x1 + + + + + CONNECTION_24 + Global slave connection information for master port + 24 + 24 + + + Disabled + Master port 24 connection to global slave is disabled + 0x0 + + + Enabled + Master port 24 connection to global slave is enabled + 0x1 + + + + + CONNECTION_25 + Global slave connection information for master port + 25 + 25 + + + Disabled + Master port 25 connection to global slave is disabled + 0x0 + + + Enabled + Master port 25 connection to global slave is enabled + 0x1 + + + + + CONNECTION_26 + Global slave connection information for master port + 26 + 26 + + + Disabled + Master port 26 connection to global slave is disabled + 0x0 + + + Enabled + Master port 26 connection to global slave is enabled + 0x1 + + + + + CONNECTION_27 + Global slave connection information for master port + 27 + 27 + + + Disabled + Master port 27 connection to global slave is disabled + 0x0 + + + Enabled + Master port 27 connection to global slave is enabled + 0x1 + + + + + CONNECTION_28 + Global slave connection information for master port + 28 + 28 + + + Disabled + Master port 28 connection to global slave is disabled + 0x0 + + + Enabled + Master port 28 connection to global slave is enabled + 0x1 + + + + + CONNECTION_29 + Global slave connection information for master port + 29 + 29 + + + Disabled + Master port 29 connection to global slave is disabled + 0x0 + + + Enabled + Master port 29 connection to global slave is enabled + 0x1 + + + + + CONNECTION_30 + Global slave connection information for master port + 30 + 30 + + + Disabled + Master port 30 connection to global slave is disabled + 0x0 + + + Enabled + Master port 30 connection to global slave is enabled + 0x1 + + + + + CONNECTION_31 + Global slave connection information for master port + 31 + 31 + + + Disabled + Master port 31 connection to global slave is disabled + 0x0 + + + Enabled + Master port 31 connection to global slave is enabled + 0x1 + + + + + + + LOCK + Lock global slave registers + 0x004 + read-write + 0x00000000 + 0x20 + + + LOCK + Enable lock + 0 + 0 + + + Disabled + Lock disabled. + 0x0 + + + Enabled + Lock enabled. + 0x1 + + + + + + + + EXTENDCLKREQ + Extend clock request configuration + 0x418 + read-write + 0x00000003 + 0x20 + + + INIT + Initial value of the down counter used for extending the clock request. + 0 + 15 + + + ENABLE + Enable the extend clock request feature + 31 + 31 + + + Disable + Disable + 0x0 + + + Enable + Enable + 0x1 + + + + + + + RTCHOKE + Real time choke configuration for AXI master port + MPC_RTCHOKE + read-write + 0x420 + + WRITEACCESS + Enable AXI Write Address Channel Real Time Choke for master port + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable Real Time Choke for Write Address Channel + 0 + 0 + + + Disable + Real Time Choke is disabled for master port 0 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 0 Write Address Channel + 0x1 + + + + + ENABLE_1 + Enable Real Time Choke for Write Address Channel + 1 + 1 + + + Disable + Real Time Choke is disabled for master port 1 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 1 Write Address Channel + 0x1 + + + + + ENABLE_2 + Enable Real Time Choke for Write Address Channel + 2 + 2 + + + Disable + Real Time Choke is disabled for master port 2 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 2 Write Address Channel + 0x1 + + + + + ENABLE_3 + Enable Real Time Choke for Write Address Channel + 3 + 3 + + + Disable + Real Time Choke is disabled for master port 3 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 3 Write Address Channel + 0x1 + + + + + ENABLE_4 + Enable Real Time Choke for Write Address Channel + 4 + 4 + + + Disable + Real Time Choke is disabled for master port 4 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 4 Write Address Channel + 0x1 + + + + + ENABLE_5 + Enable Real Time Choke for Write Address Channel + 5 + 5 + + + Disable + Real Time Choke is disabled for master port 5 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 5 Write Address Channel + 0x1 + + + + + ENABLE_6 + Enable Real Time Choke for Write Address Channel + 6 + 6 + + + Disable + Real Time Choke is disabled for master port 6 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 6 Write Address Channel + 0x1 + + + + + ENABLE_7 + Enable Real Time Choke for Write Address Channel + 7 + 7 + + + Disable + Real Time Choke is disabled for master port 7 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 7 Write Address Channel + 0x1 + + + + + ENABLE_8 + Enable Real Time Choke for Write Address Channel + 8 + 8 + + + Disable + Real Time Choke is disabled for master port 8 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 8 Write Address Channel + 0x1 + + + + + ENABLE_9 + Enable Real Time Choke for Write Address Channel + 9 + 9 + + + Disable + Real Time Choke is disabled for master port 9 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 9 Write Address Channel + 0x1 + + + + + ENABLE_10 + Enable Real Time Choke for Write Address Channel + 10 + 10 + + + Disable + Real Time Choke is disabled for master port 10 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 10 Write Address Channel + 0x1 + + + + + ENABLE_11 + Enable Real Time Choke for Write Address Channel + 11 + 11 + + + Disable + Real Time Choke is disabled for master port 11 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 11 Write Address Channel + 0x1 + + + + + ENABLE_12 + Enable Real Time Choke for Write Address Channel + 12 + 12 + + + Disable + Real Time Choke is disabled for master port 12 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 12 Write Address Channel + 0x1 + + + + + ENABLE_13 + Enable Real Time Choke for Write Address Channel + 13 + 13 + + + Disable + Real Time Choke is disabled for master port 13 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 13 Write Address Channel + 0x1 + + + + + ENABLE_14 + Enable Real Time Choke for Write Address Channel + 14 + 14 + + + Disable + Real Time Choke is disabled for master port 14 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 14 Write Address Channel + 0x1 + + + + + ENABLE_15 + Enable Real Time Choke for Write Address Channel + 15 + 15 + + + Disable + Real Time Choke is disabled for master port 15 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 15 Write Address Channel + 0x1 + + + + + ENABLE_16 + Enable Real Time Choke for Write Address Channel + 16 + 16 + + + Disable + Real Time Choke is disabled for master port 16 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 16 Write Address Channel + 0x1 + + + + + ENABLE_17 + Enable Real Time Choke for Write Address Channel + 17 + 17 + + + Disable + Real Time Choke is disabled for master port 17 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 17 Write Address Channel + 0x1 + + + + + ENABLE_18 + Enable Real Time Choke for Write Address Channel + 18 + 18 + + + Disable + Real Time Choke is disabled for master port 18 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 18 Write Address Channel + 0x1 + + + + + ENABLE_19 + Enable Real Time Choke for Write Address Channel + 19 + 19 + + + Disable + Real Time Choke is disabled for master port 19 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 19 Write Address Channel + 0x1 + + + + + ENABLE_20 + Enable Real Time Choke for Write Address Channel + 20 + 20 + + + Disable + Real Time Choke is disabled for master port 20 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 20 Write Address Channel + 0x1 + + + + + ENABLE_21 + Enable Real Time Choke for Write Address Channel + 21 + 21 + + + Disable + Real Time Choke is disabled for master port 21 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 21 Write Address Channel + 0x1 + + + + + ENABLE_22 + Enable Real Time Choke for Write Address Channel + 22 + 22 + + + Disable + Real Time Choke is disabled for master port 22 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 22 Write Address Channel + 0x1 + + + + + ENABLE_23 + Enable Real Time Choke for Write Address Channel + 23 + 23 + + + Disable + Real Time Choke is disabled for master port 23 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 23 Write Address Channel + 0x1 + + + + + ENABLE_24 + Enable Real Time Choke for Write Address Channel + 24 + 24 + + + Disable + Real Time Choke is disabled for master port 24 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 24 Write Address Channel + 0x1 + + + + + ENABLE_25 + Enable Real Time Choke for Write Address Channel + 25 + 25 + + + Disable + Real Time Choke is disabled for master port 25 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 25 Write Address Channel + 0x1 + + + + + ENABLE_26 + Enable Real Time Choke for Write Address Channel + 26 + 26 + + + Disable + Real Time Choke is disabled for master port 26 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 26 Write Address Channel + 0x1 + + + + + ENABLE_27 + Enable Real Time Choke for Write Address Channel + 27 + 27 + + + Disable + Real Time Choke is disabled for master port 27 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 27 Write Address Channel + 0x1 + + + + + ENABLE_28 + Enable Real Time Choke for Write Address Channel + 28 + 28 + + + Disable + Real Time Choke is disabled for master port 28 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 28 Write Address Channel + 0x1 + + + + + ENABLE_29 + Enable Real Time Choke for Write Address Channel + 29 + 29 + + + Disable + Real Time Choke is disabled for master port 29 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 29 Write Address Channel + 0x1 + + + + + ENABLE_30 + Enable Real Time Choke for Write Address Channel + 30 + 30 + + + Disable + Real Time Choke is disabled for master port 30 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 30 Write Address Channel + 0x1 + + + + + ENABLE_31 + Enable Real Time Choke for Write Address Channel + 31 + 31 + + + Disable + Real Time Choke is disabled for master port 31 Write Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 31 Write Address Channel + 0x1 + + + + + + + READACCESS + Enable AXI Read Address Channel Real Time Choke for master port + 0x004 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable Real Time Choke for Read Address Channel + 0 + 0 + + + Disable + Real Time Choke is disabled for master port 0 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 0 Read Address Channel + 0x1 + + + + + ENABLE_1 + Enable Real Time Choke for Read Address Channel + 1 + 1 + + + Disable + Real Time Choke is disabled for master port 1 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 1 Read Address Channel + 0x1 + + + + + ENABLE_2 + Enable Real Time Choke for Read Address Channel + 2 + 2 + + + Disable + Real Time Choke is disabled for master port 2 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 2 Read Address Channel + 0x1 + + + + + ENABLE_3 + Enable Real Time Choke for Read Address Channel + 3 + 3 + + + Disable + Real Time Choke is disabled for master port 3 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 3 Read Address Channel + 0x1 + + + + + ENABLE_4 + Enable Real Time Choke for Read Address Channel + 4 + 4 + + + Disable + Real Time Choke is disabled for master port 4 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 4 Read Address Channel + 0x1 + + + + + ENABLE_5 + Enable Real Time Choke for Read Address Channel + 5 + 5 + + + Disable + Real Time Choke is disabled for master port 5 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 5 Read Address Channel + 0x1 + + + + + ENABLE_6 + Enable Real Time Choke for Read Address Channel + 6 + 6 + + + Disable + Real Time Choke is disabled for master port 6 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 6 Read Address Channel + 0x1 + + + + + ENABLE_7 + Enable Real Time Choke for Read Address Channel + 7 + 7 + + + Disable + Real Time Choke is disabled for master port 7 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 7 Read Address Channel + 0x1 + + + + + ENABLE_8 + Enable Real Time Choke for Read Address Channel + 8 + 8 + + + Disable + Real Time Choke is disabled for master port 8 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 8 Read Address Channel + 0x1 + + + + + ENABLE_9 + Enable Real Time Choke for Read Address Channel + 9 + 9 + + + Disable + Real Time Choke is disabled for master port 9 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 9 Read Address Channel + 0x1 + + + + + ENABLE_10 + Enable Real Time Choke for Read Address Channel + 10 + 10 + + + Disable + Real Time Choke is disabled for master port 10 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 10 Read Address Channel + 0x1 + + + + + ENABLE_11 + Enable Real Time Choke for Read Address Channel + 11 + 11 + + + Disable + Real Time Choke is disabled for master port 11 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 11 Read Address Channel + 0x1 + + + + + ENABLE_12 + Enable Real Time Choke for Read Address Channel + 12 + 12 + + + Disable + Real Time Choke is disabled for master port 12 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 12 Read Address Channel + 0x1 + + + + + ENABLE_13 + Enable Real Time Choke for Read Address Channel + 13 + 13 + + + Disable + Real Time Choke is disabled for master port 13 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 13 Read Address Channel + 0x1 + + + + + ENABLE_14 + Enable Real Time Choke for Read Address Channel + 14 + 14 + + + Disable + Real Time Choke is disabled for master port 14 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 14 Read Address Channel + 0x1 + + + + + ENABLE_15 + Enable Real Time Choke for Read Address Channel + 15 + 15 + + + Disable + Real Time Choke is disabled for master port 15 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 15 Read Address Channel + 0x1 + + + + + ENABLE_16 + Enable Real Time Choke for Read Address Channel + 16 + 16 + + + Disable + Real Time Choke is disabled for master port 16 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 16 Read Address Channel + 0x1 + + + + + ENABLE_17 + Enable Real Time Choke for Read Address Channel + 17 + 17 + + + Disable + Real Time Choke is disabled for master port 17 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 17 Read Address Channel + 0x1 + + + + + ENABLE_18 + Enable Real Time Choke for Read Address Channel + 18 + 18 + + + Disable + Real Time Choke is disabled for master port 18 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 18 Read Address Channel + 0x1 + + + + + ENABLE_19 + Enable Real Time Choke for Read Address Channel + 19 + 19 + + + Disable + Real Time Choke is disabled for master port 19 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 19 Read Address Channel + 0x1 + + + + + ENABLE_20 + Enable Real Time Choke for Read Address Channel + 20 + 20 + + + Disable + Real Time Choke is disabled for master port 20 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 20 Read Address Channel + 0x1 + + + + + ENABLE_21 + Enable Real Time Choke for Read Address Channel + 21 + 21 + + + Disable + Real Time Choke is disabled for master port 21 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 21 Read Address Channel + 0x1 + + + + + ENABLE_22 + Enable Real Time Choke for Read Address Channel + 22 + 22 + + + Disable + Real Time Choke is disabled for master port 22 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 22 Read Address Channel + 0x1 + + + + + ENABLE_23 + Enable Real Time Choke for Read Address Channel + 23 + 23 + + + Disable + Real Time Choke is disabled for master port 23 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 23 Read Address Channel + 0x1 + + + + + ENABLE_24 + Enable Real Time Choke for Read Address Channel + 24 + 24 + + + Disable + Real Time Choke is disabled for master port 24 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 24 Read Address Channel + 0x1 + + + + + ENABLE_25 + Enable Real Time Choke for Read Address Channel + 25 + 25 + + + Disable + Real Time Choke is disabled for master port 25 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 25 Read Address Channel + 0x1 + + + + + ENABLE_26 + Enable Real Time Choke for Read Address Channel + 26 + 26 + + + Disable + Real Time Choke is disabled for master port 26 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 26 Read Address Channel + 0x1 + + + + + ENABLE_27 + Enable Real Time Choke for Read Address Channel + 27 + 27 + + + Disable + Real Time Choke is disabled for master port 27 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 27 Read Address Channel + 0x1 + + + + + ENABLE_28 + Enable Real Time Choke for Read Address Channel + 28 + 28 + + + Disable + Real Time Choke is disabled for master port 28 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 28 Read Address Channel + 0x1 + + + + + ENABLE_29 + Enable Real Time Choke for Read Address Channel + 29 + 29 + + + Disable + Real Time Choke is disabled for master port 29 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 29 Read Address Channel + 0x1 + + + + + ENABLE_30 + Enable Real Time Choke for Read Address Channel + 30 + 30 + + + Disable + Real Time Choke is disabled for master port 30 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 30 Read Address Channel + 0x1 + + + + + ENABLE_31 + Enable Real Time Choke for Read Address Channel + 31 + 31 + + + Disable + Real Time Choke is disabled for master port 31 Read Address Channel + 0x0 + + + Enable + Real Time Choke is enabled for master port 31 Read Address Channel + 0x1 + + + + + + + 0x20 + 0x4 + DELAY[%s] + Description collection: Real Time Choke delay value for slave number n + 0x60 + read-write + 0x00000000 + 0x20 + + + DELAY + Real Time Choke delay in bus clock cycles. + 0 + 7 + + + + + + 32 + 0x010 + REGION[%s] + Memory region to slave decoding table + MPC_REGION + read-write + 0x600 + + CONFIG + Description cluster: Slave region n Configuration register + 0x000 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Locks the region n setting + 8 + 8 + read-writeonce + + + Unlocked + Region n settings can be updated + 0x0 + + + Locked + Region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Region n enable + 9 + 9 + + + Disabled + Region n is not used + 0x0 + + + Enabled + Region n is used + 0x1 + + + + + READ + Read access + 12 + 12 + + + NotAllowed + Read access to region n is not allowed + 0x0 + + + Allowed + Read access to region n is allowed + 0x1 + + + + + WRITE + Write access + 13 + 13 + + + NotAllowed + Write access to region n is not allowed + 0x0 + + + Allowed + Write access to region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 14 + 14 + + + NotAllowed + Software execution from region n is not allowed + 0x0 + + + Allowed + Software execution from region n is allowed + 0x1 + + + + + SECATTR + Memory security mapping + 15 + 15 + + + Secure + Memory is mapped in secure memory address space + 0x1 + + + NonSecure + Memory is mapped in non-secure memory address space + 0x0 + + + + + OWNERID + Region owner identifier. + 16 + 19 + + + + + STARTADDR + Description cluster: Region n start address + 0x004 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for memory region n + 0 + 31 + + + + + ADDRMASK + Description cluster: Select which bits of the incoming address are compared against the STARTADDR + 0x008 + read-write + 0x00000000 + 0x20 + + + ADDRMASK + Address mask for memory region n + 0 + 31 + + + + + MASTERPORT + Description cluster: Region n local master enable + 0x00C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable region n for master port 0 + 0 + 0 + + + Disable + Region n is disabled for master port 0 + 0x0 + + + Enable + Region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable region n for master port 1 + 1 + 1 + + + Disable + Region n is disabled for master port 1 + 0x0 + + + Enable + Region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable region n for master port 2 + 2 + 2 + + + Disable + Region n is disabled for master port 2 + 0x0 + + + Enable + Region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable region n for master port 3 + 3 + 3 + + + Disable + Region n is disabled for master port 3 + 0x0 + + + Enable + Region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable region n for master port 4 + 4 + 4 + + + Disable + Region n is disabled for master port 4 + 0x0 + + + Enable + Region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable region n for master port 5 + 5 + 5 + + + Disable + Region n is disabled for master port 5 + 0x0 + + + Enable + Region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable region n for master port 6 + 6 + 6 + + + Disable + Region n is disabled for master port 6 + 0x0 + + + Enable + Region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable region n for master port 7 + 7 + 7 + + + Disable + Region n is disabled for master port 7 + 0x0 + + + Enable + Region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable region n for master port 8 + 8 + 8 + + + Disable + Region n is disabled for master port 8 + 0x0 + + + Enable + Region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable region n for master port 9 + 9 + 9 + + + Disable + Region n is disabled for master port 9 + 0x0 + + + Enable + Region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable region n for master port 10 + 10 + 10 + + + Disable + Region n is disabled for master port 10 + 0x0 + + + Enable + Region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable region n for master port 11 + 11 + 11 + + + Disable + Region n is disabled for master port 11 + 0x0 + + + Enable + Region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable region n for master port 12 + 12 + 12 + + + Disable + Region n is disabled for master port 12 + 0x0 + + + Enable + Region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable region n for master port 13 + 13 + 13 + + + Disable + Region n is disabled for master port 13 + 0x0 + + + Enable + Region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable region n for master port 14 + 14 + 14 + + + Disable + Region n is disabled for master port 14 + 0x0 + + + Enable + Region n is enabled for master port 14 + 0x1 + + + + + ENABLE15 + Enable region n for master port 15 + 15 + 15 + + + Disable + Region n is disabled for master port 15 + 0x0 + + + Enable + Region n is enabled for master port 15 + 0x1 + + + + + ENABLE16 + Enable region n for master port 16 + 16 + 16 + + + Disable + Region n is disabled for master port 16 + 0x0 + + + Enable + Region n is enabled for master port 16 + 0x1 + + + + + ENABLE17 + Enable region n for master port 17 + 17 + 17 + + + Disable + Region n is disabled for master port 17 + 0x0 + + + Enable + Region n is enabled for master port 17 + 0x1 + + + + + ENABLE18 + Enable region n for master port 18 + 18 + 18 + + + Disable + Region n is disabled for master port 18 + 0x0 + + + Enable + Region n is enabled for master port 18 + 0x1 + + + + + ENABLE19 + Enable region n for master port 19 + 19 + 19 + + + Disable + Region n is disabled for master port 19 + 0x0 + + + Enable + Region n is enabled for master port 19 + 0x1 + + + + + ENABLE20 + Enable region n for master port 20 + 20 + 20 + + + Disable + Region n is disabled for master port 20 + 0x0 + + + Enable + Region n is enabled for master port 20 + 0x1 + + + + + ENABLE21 + Enable region n for master port 21 + 21 + 21 + + + Disable + Region n is disabled for master port 21 + 0x0 + + + Enable + Region n is enabled for master port 21 + 0x1 + + + + + ENABLE22 + Enable region n for master port 22 + 22 + 22 + + + Disable + Region n is disabled for master port 22 + 0x0 + + + Enable + Region n is enabled for master port 22 + 0x1 + + + + + ENABLE23 + Enable region n for master port 23 + 23 + 23 + + + Disable + Region n is disabled for master port 23 + 0x0 + + + Enable + Region n is enabled for master port 23 + 0x1 + + + + + ENABLE24 + Enable region n for master port 24 + 24 + 24 + + + Disable + Region n is disabled for master port 24 + 0x0 + + + Enable + Region n is enabled for master port 24 + 0x1 + + + + + ENABLE25 + Enable region n for master port 25 + 25 + 25 + + + Disable + Region n is disabled for master port 25 + 0x0 + + + Enable + Region n is enabled for master port 25 + 0x1 + + + + + ENABLE26 + Enable region n for master port 26 + 26 + 26 + + + Disable + Region n is disabled for master port 26 + 0x0 + + + Enable + Region n is enabled for master port 26 + 0x1 + + + + + ENABLE27 + Enable region n for master port 27 + 27 + 27 + + + Disable + Region n is disabled for master port 27 + 0x0 + + + Enable + Region n is enabled for master port 27 + 0x1 + + + + + ENABLE28 + Enable region n for master port 28 + 28 + 28 + + + Disable + Region n is disabled for master port 28 + 0x0 + + + Enable + Region n is enabled for master port 28 + 0x1 + + + + + ENABLE29 + Enable region n for master port 29 + 29 + 29 + + + Disable + Region n is disabled for master port 29 + 0x0 + + + Enable + Region n is enabled for master port 29 + 0x1 + + + + + ENABLE30 + Enable region n for master port 30 + 30 + 30 + + + Disable + Region n is disabled for master port 30 + 0x0 + + + Enable + Region n is enabled for master port 30 + 0x1 + + + + + ENABLE31 + Enable region n for master port 31 + 31 + 31 + + + Disable + Region n is disabled for master port 31 + 0x0 + + + Enable + Region n is enabled for master port 31 + 0x1 + + + + + + + + 40 + 0x020 + OVERRIDE[%s] + Special privilege tables + MPC_OVERRIDE + read-write + 0x800 + + CONFIG + Description cluster: Override region n Configuration register + 0x0 + read-write + 0x00000000 + 0x20 + + + SLAVENUMBER + Target slave number for override region n accesses. Slave number 0 is reserved for default slave + 0 + 4 + + + LOCK + Lock Override region n + 8 + 8 + read-writeonce + + + Unlocked + Override region n settings can be updated + 0x0 + + + Locked + Override region n settings can't be updated until next reset + 0x1 + + + + + ENABLE + Enable Override region n + 9 + 9 + + + Disabled + Override region n is not used + 0x0 + + + Enabled + Override region n is used + 0x1 + + + + + SECDOMENABLE + Secure domain access enable for Override region n + 10 + 10 + + + Disabled + Overriding of secure domain permissions is disabled for override region n + 0x0 + + + Enabled + Overriding of secure domain permissions is enabled for override region n + 0x1 + + + + + SECUREMASK + Secure mask enable for Override region n + 12 + 12 + read-only + + + Disabled + Mask is disabled for override region n + 0x0 + + + Enabled + Mask is enabled for override region n + 0x1 + + + + + + + STARTADDR + Description cluster: Override region n Start Address + 0x4 + read-write + 0x00000000 + 0x20 + + + STARTADDR + Start address for override region n + 0 + 31 + + + + + ENDADDR + Description cluster: Override region n End Address + 0x8 + read-write + 0x00000000 + 0x20 + + + ENDADDR + End address for override region n + 0 + 31 + + + + + OFFSET + Description cluster: Address offset value divided by 2 for override region n address re-map + 0x0C + read-write + 0x00000000 + int32_t + 0x20 + + + OFFSET + Offset value + 0 + 31 + + + + + PERM + Description cluster: Permission settings for override region n + 0x10 + read-write + 0x00000000 + 0x20 + + + READ + Read access + 0 + 0 + + + NotAllowed + Read access to override region n is not allowed + 0x0 + + + Allowed + Read access to override region n is allowed + 0x1 + + + + + WRITE + Write access + 1 + 1 + + + NotAllowed + Write access to override region n is not allowed + 0x0 + + + Allowed + Write access to override region n is allowed + 0x1 + + + + + EXECUTE + Software execute + 2 + 2 + + + NotAllowed + Software execution from override region n is not allowed + 0x0 + + + Allowed + Software execution from override region n is allowed + 0x1 + + + + + SECATTR + Security mapping + 3 + 3 + + + Secure + Override region n is mapped in secure memory address space + 0x1 + + + NonSecure + Override region n is mapped in non-secure memory address space + 0x0 + + + + + + + PERMMASK + Description cluster: Masks permission setting fields from register OVERRIDE.PERM + 0x14 + read-write + 0x00000000 + 0x20 + + + READ + Read mask + 0 + 0 + + + Masked + Permission setting READ in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting READ in OVERRIDE register will be applied + 0x1 + + + + + WRITE + Write mask + 1 + 1 + + + Masked + Permission setting WRITE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting WRITE in OVERRIDE register will be applied + 0x1 + + + + + EXECUTE + Execute mask + 2 + 2 + + + Masked + Permission setting EXECUTE in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting EXECUTE in OVERRIDE register will be applied + 0x1 + + + + + SECATTR + Security mapping mask + 3 + 3 + + + Masked + Permission setting SECATTR in OVERRIDE register will not be applied + 0x0 + + + UnMasked + Permission setting SECATTR in OVERRIDE register will be applied + 0x1 + + + + + + + OWNER + Description cluster: Owner for override region + 0x18 + read-write + 0x00000000 + 0x20 + + + OWNERID + owner identifier for override region n + 0 + 3 + + + + + MASTERPORT + Description cluster: Override region n local master enable + 0x1C + read-write + 0x00000000 + 0x20 + + + ENABLE0 + Enable override + 0 + 0 + + + Disable + Override region n is disabled for master port 0 + 0x0 + + + Enable + Override region n is enabled for master port 0 + 0x1 + + + + + ENABLE1 + Enable override + 1 + 1 + + + Disable + Override region n is disabled for master port 1 + 0x0 + + + Enable + Override region n is enabled for master port 1 + 0x1 + + + + + ENABLE2 + Enable override + 2 + 2 + + + Disable + Override region n is disabled for master port 2 + 0x0 + + + Enable + Override region n is enabled for master port 2 + 0x1 + + + + + ENABLE3 + Enable override + 3 + 3 + + + Disable + Override region n is disabled for master port 3 + 0x0 + + + Enable + Override region n is enabled for master port 3 + 0x1 + + + + + ENABLE4 + Enable override + 4 + 4 + + + Disable + Override region n is disabled for master port 4 + 0x0 + + + Enable + Override region n is enabled for master port 4 + 0x1 + + + + + ENABLE5 + Enable override + 5 + 5 + + + Disable + Override region n is disabled for master port 5 + 0x0 + + + Enable + Override region n is enabled for master port 5 + 0x1 + + + + + ENABLE6 + Enable override + 6 + 6 + + + Disable + Override region n is disabled for master port 6 + 0x0 + + + Enable + Override region n is enabled for master port 6 + 0x1 + + + + + ENABLE7 + Enable override + 7 + 7 + + + Disable + Override region n is disabled for master port 7 + 0x0 + + + Enable + Override region n is enabled for master port 7 + 0x1 + + + + + ENABLE8 + Enable override + 8 + 8 + + + Disable + Override region n is disabled for master port 8 + 0x0 + + + Enable + Override region n is enabled for master port 8 + 0x1 + + + + + ENABLE9 + Enable override + 9 + 9 + + + Disable + Override region n is disabled for master port 9 + 0x0 + + + Enable + Override region n is enabled for master port 9 + 0x1 + + + + + ENABLE10 + Enable override + 10 + 10 + + + Disable + Override region n is disabled for master port 10 + 0x0 + + + Enable + Override region n is enabled for master port 10 + 0x1 + + + + + ENABLE11 + Enable override + 11 + 11 + + + Disable + Override region n is disabled for master port 11 + 0x0 + + + Enable + Override region n is enabled for master port 11 + 0x1 + + + + + ENABLE12 + Enable override + 12 + 12 + + + Disable + Override region n is disabled for master port 12 + 0x0 + + + Enable + Override region n is enabled for master port 12 + 0x1 + + + + + ENABLE13 + Enable override + 13 + 13 + + + Disable + Override region n is disabled for master port 13 + 0x0 + + + Enable + Override region n is enabled for master port 13 + 0x1 + + + + + ENABLE14 + Enable override + 14 + 14 + + + Disable + Override region n is disabled for master port 14 + 0x0 + + + Enable + Override region n is enabled for master port 14 + 0x1 + + + + + ENABLE15 + Enable override + 15 + 15 + + + Disable + Override region n is disabled for master port 15 + 0x0 + + + Enable + Override region n is enabled for master port 15 + 0x1 + + + + + ENABLE16 + Enable override + 16 + 16 + + + Disable + Override region n is disabled for master port 16 + 0x0 + + + Enable + Override region n is enabled for master port 16 + 0x1 + + + + + ENABLE17 + Enable override + 17 + 17 + + + Disable + Override region n is disabled for master port 17 + 0x0 + + + Enable + Override region n is enabled for master port 17 + 0x1 + + + + + ENABLE18 + Enable override + 18 + 18 + + + Disable + Override region n is disabled for master port 18 + 0x0 + + + Enable + Override region n is enabled for master port 18 + 0x1 + + + + + ENABLE19 + Enable override + 19 + 19 + + + Disable + Override region n is disabled for master port 19 + 0x0 + + + Enable + Override region n is enabled for master port 19 + 0x1 + + + + + ENABLE20 + Enable override + 20 + 20 + + + Disable + Override region n is disabled for master port 20 + 0x0 + + + Enable + Override region n is enabled for master port 20 + 0x1 + + + + + ENABLE21 + Enable override + 21 + 21 + + + Disable + Override region n is disabled for master port 21 + 0x0 + + + Enable + Override region n is enabled for master port 21 + 0x1 + + + + + ENABLE22 + Enable override + 22 + 22 + + + Disable + Override region n is disabled for master port 22 + 0x0 + + + Enable + Override region n is enabled for master port 22 + 0x1 + + + + + ENABLE23 + Enable override + 23 + 23 + + + Disable + Override region n is disabled for master port 23 + 0x0 + + + Enable + Override region n is enabled for master port 23 + 0x1 + + + + + ENABLE24 + Enable override + 24 + 24 + + + Disable + Override region n is disabled for master port 24 + 0x0 + + + Enable + Override region n is enabled for master port 24 + 0x1 + + + + + ENABLE25 + Enable override + 25 + 25 + + + Disable + Override region n is disabled for master port 25 + 0x0 + + + Enable + Override region n is enabled for master port 25 + 0x1 + + + + + ENABLE26 + Enable override + 26 + 26 + + + Disable + Override region n is disabled for master port 26 + 0x0 + + + Enable + Override region n is enabled for master port 26 + 0x1 + + + + + ENABLE27 + Enable override + 27 + 27 + + + Disable + Override region n is disabled for master port 27 + 0x0 + + + Enable + Override region n is enabled for master port 27 + 0x1 + + + + + ENABLE28 + Enable override + 28 + 28 + + + Disable + Override region n is disabled for master port 28 + 0x0 + + + Enable + Override region n is enabled for master port 28 + 0x1 + + + + + ENABLE29 + Enable override + 29 + 29 + + + Disable + Override region n is disabled for master port 29 + 0x0 + + + Enable + Override region n is enabled for master port 29 + 0x1 + + + + + ENABLE30 + Enable override + 30 + 30 + + + Disable + Override region n is disabled for master port 30 + 0x0 + + + Enable + Override region n is enabled for master port 30 + 0x1 + + + + + ENABLE31 + Enable override + 31 + 31 + + + Disable + Override region n is disabled for master port 31 + 0x0 + + + Enable + Override region n is enabled for master port 31 + 0x1 + + + + + + + + + + MVDMA_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x43003000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA + 3 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + MVDMA_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x53003000 + + + + MVDMA + 3 + + + + RAMC000_NS + RAM Controller 0 + 0x43004000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + SECBASE + Base address for secure access area. + 0x600 + read-write + 0x00000000 + 0x20 + + + ADDR + Base address + 0 + 31 + + + + + SECENABLE + Enable secure access restrictions. + 0x604 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable secure access restrictions + 0 + 0 + + + Disable + Secure access restrictions disabled + 0x0 + + + Enable + Secure access restrictions enabled + 0x1 + + + + + + + + + RAMC000_S + RAM Controller 1 + 0x53004000 + + + + + HSFLL_S + HSFLL + 0x5300D000 + HSFLL + + + + 0 + 0x1000 + registers + + HSFLL + 0x20 + + + TASKS_START + Start the HSFLL + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the HSFLL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the HSFLL + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the HSFLL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FREQMEAS + Start frequency measurement in software-controlled mode + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_FREQMEAS + Start frequency measurement in software-controlled mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FREQCHANGE + Trigger frequency change + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_FREQCHANGE + Trigger frequency change + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_STARTED + HSFLL started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + HSFLL started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + HSFLL stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + HSFLL stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FREQMDONE + Frequency measurement done + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_FREQMDONE + Frequency measurement done + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FREQCHANGED + Frequency change done + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_FREQCHANGED + Frequency change done + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + CLOCKSTATUS + Clock status + 0x400 + read-only + 0x00000000 + 0x20 + + + MODE + The HSFLL operating mode. + 0 + 1 + + + OpenLoop + Open loop mode. + 0x0 + + + ClosedLoop + Closed loop mode. + 0x1 + + + Bypass + Bypass mode. + 0x2 + + + + + OVERRIDE + HSFLL Override mode. + 4 + 4 + + + Disabled + Override mode disabled. + 0x0 + + + Enabled + Override mode enabled. + 0x1 + + + + + ACCURACY + Clock accuracy. + 9 + 9 + + + OutsideLimit + Clock accuracy is outside 2 percent. + 0x0 + + + WithinLimit + Clock accuracy is within 2 percent. + 0x1 + + + + + LOCKED + The HSFLL lock status. + 10 + 10 + + + NotLocked + Not locked to reference clock + 0x0 + + + Locked + Locked to reference clock. + 0x1 + + + + + + + FREQM + Unspecified + HSFLL_FREQM + read-write + 0x420 + + DONE + Frequency measurement done status + 0x000 + read-only + 0x00000000 + 0x20 + + + DONE + Measurement done. + 0 + 0 + + + InProgress + Frequency measurement is in progress. + 0x0 + + + Completed + Frequency measurement is completed. + 0x1 + + + + + + + ERROR + Frequency measurement error status + 0x004 + read-only + 0x00000000 + 0x20 + + + ERROR + Trim error status. + 0 + 0 + + + OutsideLimit + Frequency exceeded the accuracy 2 percent in closed loop mode. + 0x1 + + + WithinLimit + Frequency stayed within accuracy 2 percent in closed loop mode. + 0x0 + + + + + TRIMUNDERFLOW + Underflow error status. + 1 + 1 + + + OutsideLimit + Underflow + 0x1 + + + WithinLimit + No underflow + 0x0 + + + + + TRIMOVERFLOW + Overflow error status. + 2 + 2 + + + OutsideLimit + Overflow + 0x1 + + + WithinLimit + No overflow + 0x0 + + + + + + + MEAS + Frequency measurement + 0x008 + read-only + 0x00000000 + 0x20 + + + VALUE + Last frequency measurement value. + 0 + 7 + + + + + + TRIM + Unspecified + HSFLL_TRIM + read-write + 0x440 + + VSUP + Internal regulator voltage supply level trimming + 0x000 + read-write + 0x00000010 + 0x20 + + + VALUE + Trim value + 0 + 4 + + + + + COARSE + Coarse frequency trimming + 0x004 + read-write + 0x00000004 + 0x20 + + + VALUE + Coarse frequency trimming value. + 0 + 9 + + + + + FINE + Fine frequency trimming + 0x008 + read-write + 0x0000001E + 0x20 + + + VALUE + Fine frequency trimming value + 0 + 10 + + + + + + CLOCKCTRL + Unspecified + HSFLL_CLOCKCTRL + read-write + 0x460 + + MODE + Clock control + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + The HSFLL operating mode. + 0 + 1 + + + Auto + The PCGC controls the mode automatically. + 0x0 + + + OpenLoop + Open loop mode. + 0x1 + + + ClosedLoop + Closed loop mode. + 0x2 + + + Bypass + Bypass mode. + 0x3 + + + + + OVERRIDE + HSFLL override mode. + 4 + 4 + + + Disabled + Override mode disabled. + 0x0 + + + Enabled + Override mode enabled. + 0x1 + + + + + + + DITHERING + Clock dithering configuration + 0x004 + read-write + 0x00000033 + 0x20 + + + CYCLECOUNT + Cycle count configuration for clock dithering + 0 + 2 + + + MAXOFFSET + Maximum offset configuration for clock dithering + 4 + 6 + + + EN + Enable the clock dithering + 31 + 31 + + + Disabled + Clock dithering is disabled + 0x0 + + + Enabled + Clock dithering is enabled + 0x1 + + + + + + + MULT + Multiplication factor + 0x008 + read-write + 0x00000006 + 0x20 + + + VAL + Multiplication factor value. Valid range: 4 to 25. Output frequency is a multiplication of 16 MHz reference and the multiplication factor. + 0 + 4 + + + + + SLEEP + Sleep configuration + 0x00C + read-write + 0x00000001 + 0x20 + + + MODE + HSFLL sleep mode. + 0 + 0 + + + Normal + Normal mode operation + 0x0 + + + Sleep + Power down the HSFLL core + 0x1 + + + + + RETAIN + Retain. + 1 + 1 + + + Disabled + No retention while powered down + 0x0 + + + Enabled + Retain all inputs while powered down + 0x1 + + + + + + + RETAINFINETRIM + Fine trim retain control + 0x010 + read-write + 0x00000000 + 0x20 + + + RETAIN + Retain control + 0 + 0 + + + NoRetain + No retain. + 0x0 + + + Retain + Retain control when HSFLL goes to open-loop mode. + 0x1 + + + + + + + OVERRIDELOCKED + Override the LOCKED signal + 0x014 + read-write + 0x00000000 + 0x20 + + + OVERRIDE + Override + 0 + 0 + + + NoOperation + No Operation. + 0x0 + + + Override + Override + 0x1 + + + + + + + DITHERINIT + Clock dithering, configurable seed + 0x018 + read-write + 0x00000000 + 0x20 + + + SEED + Initial value for the PRBS + 0 + 31 + + + + + + MIRROR + Enable LOCK for mirrored registers + 0x480 + read-write + 0x00000001 + 0x20 + + + LOCK + Lock for mirrored registers + 0 + 0 + + + Disabled + Lock disabled + 0x0 + + + Enabled + Lock enabled + 0x1 + + + + + + + + + LRCCONF000_S + LRCCONF 0 + 0x5300E000 + LRCCONF + + + + 0 + 0x1000 + registers + + LRCCONF + 0x20 + + + 0x8 + 0x4 + TASKS_REQCLKSRC[%s] + Description collection: Request the clock source for clock [n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_REQCLKSRC + Request the clock source for clock [n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_STOPREQCLKSRC[%s] + Description collection: Stop requesting the clock source for clock [n] + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQCLKSRC + Stop requesting the clock source for clock [n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CONSTLAT + Peripheral tasks. + LRCCONF_TASKS_CONSTLAT + write-only + 0x040 + + ENABLE + Enable constant latency mode + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLE + Enable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DISABLE + Disable constant latency mode + 0x004 + write-only + 0x00000000 + 0x20 + + + DISABLE + Disable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TASKS_SYSTEMOFF + Peripheral tasks. + LRCCONF_TASKS_SYSTEMOFF + write-only + 0x048 + + NOTREADY + Not ready to go to System OFF + 0x000 + write-only + 0x00000000 + 0x20 + + + NOTREADY + Not ready to go to System OFF + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + READY + Ready to go to System OFF + 0x004 + write-only + 0x00000000 + 0x20 + + + READY + Ready to go to System OFF + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TASKS_REQHFXO + Request HFXO + 0x050 + write-only + 0x00000000 + 0x20 + + + TASKS_REQHFXO + Request HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQHFXO + Stop requesting HFXO + 0x054 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQHFXO + Stop requesting HFXO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_CLKSRCSTARTED[%s] + Description collection: Clock source is started for clock [n] + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CLKSRCSTARTED + Clock source is started for clock [n] + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_HFXOSTARTED + HFXO is started + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_HFXOSTARTED + HFXO is started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + CLKSTAT[%s] + Unspecified + LRCCONF_CLKSTAT + read-write + 0x400 + + RUN + Description cluster: Status indicating that TASKS_REQCLKSRC task has been triggered for clock [n]. + 0x000 + read-write + 0x00000000 + 0x20 + + + STATUS + Clock start task triggered or not + 0 + 0 + read-only + + + NotTriggered + Task not triggered + 0x0 + + + Triggered + Task triggered + 0x1 + + + + + + + SRC + Description cluster: Status indicating clock source for clock [n] + 0x004 + read-write + 0x00000000 + 0x20 + + + SRC + Clock source status + 0 + 0 + read-only + + + OpenLoop + Open loop. + 0x0 + + + ClosedLoop + Closed loop. + 0x1 + + + + + + + + 8 + 0x008 + CLKCTRL[%s] + Unspecified + LRCCONF_CLKCTRL + read-write + 0x440 + + ALWAYSRUN + Description cluster: Force the clock [n] and tree running always + 0x000 + read-write + 0x00000000 + 0x20 + + + FORCE + Force the clock always running + 0 + 0 + + + Automatic + Automatic clock control enabled + 0x0 + + + AlwaysRun + Clock always running + 0x1 + + + + + + + SRC + Description cluster: Select the clock source for clock [n] + 0x004 + read-write + 0x00000000 + 0x20 + + + SRC + Clock source + 0 + 0 + + + OpenLoop + Open loop. + 0x0 + + + ClosedLoop + Closed loop. + 0x1 + + + + + + + + CONSTLATSTAT + Status of constant latency + 0x480 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Disable + Constant latency disabled. + 0x0 + + + Enable + Constant latency enabled. + 0x1 + + + + + + + POWERON + Force power domain ON + 0x490 + read-write + 0x00000000 + 0x20 + + + MAIN + Force the main power domain ON + 0 + 0 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_0 + Force the active power domain[0] ON + 4 + 4 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_1 + Force the active power domain[1] ON + 5 + 5 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_2 + Force the active power domain[2] ON + 6 + 6 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_3 + Force the active power domain[3] ON + 7 + 7 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_4 + Force the active power domain[4] ON + 8 + 8 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_5 + Force the active power domain[5] ON + 9 + 9 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_6 + Force the active power domain[6] ON + 10 + 10 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + ACTIVE_7 + Force the active power domain[7] ON + 11 + 11 + + + Automatic + Automatic power control enabled + 0x0 + + + AlwaysOn + Keep the power domain ON even though there is no request + 0x1 + + + + + + + RETAIN + Retain power domain + 0x494 + read-write + 0x00000FF1 + 0x20 + + + MAIN + Retain the main power domain + 0 + 0 + read-only + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_0 + Retain the active power domain[0] + 4 + 4 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_1 + Retain the active power domain[1] + 5 + 5 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_2 + Retain the active power domain[2] + 6 + 6 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_3 + Retain the active power domain[3] + 7 + 7 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_4 + Retain the active power domain[4] + 8 + 8 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_5 + Retain the active power domain[5] + 9 + 9 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_6 + Retain the active power domain[6] + 10 + 10 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + ACTIVE_7 + Retain the active power domain[7] + 11 + 11 + + + Disable + Retain disabled + 0x0 + + + Enable + Retain enabled + 0x1 + + + + + + + 0x10 + 0x4 + AX2XWAITSTATES[%s] + Description collection: AX2X bridge waitstates for the domain [n], where n is the Domain ID. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates + 0 + 2 + + + + + + + SPU010_S + System protection unit 1 + 0x53010000 + + + + SPU010 + 16 + + + + MEMCONF_NS + Memory configuration 0 + 0x43012000 + MEMCONF + + + + 0 + 0x1000 + registers + + MEMCONF + 0x20 + + + 2 + 0x010 + POWER[%s] + Unspecified + MEMCONF_POWER + read-write + 0x500 + + CONTROL + Description cluster: Control memory block power. + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + MEM0 + Keep the memory block MEM[0] on or off when in System ON mode. + 0 + 0 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM1 + Keep the memory block MEM[1] on or off when in System ON mode. + 1 + 1 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM2 + Keep the memory block MEM[2] on or off when in System ON mode. + 2 + 2 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM3 + Keep the memory block MEM[3] on or off when in System ON mode. + 3 + 3 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM4 + Keep the memory block MEM[4] on or off when in System ON mode. + 4 + 4 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM5 + Keep the memory block MEM[5] on or off when in System ON mode. + 5 + 5 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM6 + Keep the memory block MEM[6] on or off when in System ON mode. + 6 + 6 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM7 + Keep the memory block MEM[7] on or off when in System ON mode. + 7 + 7 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM8 + Keep the memory block MEM[8] on or off when in System ON mode. + 8 + 8 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM9 + Keep the memory block MEM[9] on or off when in System ON mode. + 9 + 9 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM10 + Keep the memory block MEM[10] on or off when in System ON mode. + 10 + 10 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM11 + Keep the memory block MEM[11] on or off when in System ON mode. + 11 + 11 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM12 + Keep the memory block MEM[12] on or off when in System ON mode. + 12 + 12 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM13 + Keep the memory block MEM[13] on or off when in System ON mode. + 13 + 13 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM14 + Keep the memory block MEM[14] on or off when in System ON mode. + 14 + 14 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM15 + Keep the memory block MEM[15] on or off when in System ON mode. + 15 + 15 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM16 + Keep the memory block MEM[16] on or off when in System ON mode. + 16 + 16 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM17 + Keep the memory block MEM[17] on or off when in System ON mode. + 17 + 17 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM18 + Keep the memory block MEM[18] on or off when in System ON mode. + 18 + 18 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM19 + Keep the memory block MEM[19] on or off when in System ON mode. + 19 + 19 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM20 + Keep the memory block MEM[20] on or off when in System ON mode. + 20 + 20 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM21 + Keep the memory block MEM[21] on or off when in System ON mode. + 21 + 21 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM22 + Keep the memory block MEM[22] on or off when in System ON mode. + 22 + 22 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM23 + Keep the memory block MEM[23] on or off when in System ON mode. + 23 + 23 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM24 + Keep the memory block MEM[24] on or off when in System ON mode. + 24 + 24 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM25 + Keep the memory block MEM[25] on or off when in System ON mode. + 25 + 25 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM26 + Keep the memory block MEM[26] on or off when in System ON mode. + 26 + 26 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM27 + Keep the memory block MEM[27] on or off when in System ON mode. + 27 + 27 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM28 + Keep the memory block MEM[28] on or off when in System ON mode. + 28 + 28 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM29 + Keep the memory block MEM[29] on or off when in System ON mode. + 29 + 29 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM30 + Keep the memory block MEM[30] on or off when in System ON mode. + 30 + 30 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + MEM31 + Keep the memory block MEM[31] on or off when in System ON mode. + 31 + 31 + + + Off + Power down + 0x0 + + + On + Power up + 0x1 + + + + + + + RET + Description cluster: RAM retention for RAM [n]. + 0x008 + read-write + 0x00000000 + 0x20 + + + MEM0 + Keep the RAM block MEM[0] retained when the parent power domain of the RAM is off. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the RAM block MEM[1] retained when the parent power domain of the RAM is off. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the RAM block MEM[2] retained when the parent power domain of the RAM is off. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the RAM block MEM[3] retained when the parent power domain of the RAM is off. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the RAM block MEM[4] retained when the parent power domain of the RAM is off. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the RAM block MEM[5] retained when the parent power domain of the RAM is off. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the RAM block MEM[6] retained when the parent power domain of the RAM is off. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the RAM block MEM[7] retained when the parent power domain of the RAM is off. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the RAM block MEM[8] retained when the parent power domain of the RAM is off. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the RAM block MEM[9] retained when the parent power domain of the RAM is off. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the RAM block MEM[10] retained when the parent power domain of the RAM is off. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the RAM block MEM[11] retained when the parent power domain of the RAM is off. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the RAM block MEM[12] retained when the parent power domain of the RAM is off. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the RAM block MEM[13] retained when the parent power domain of the RAM is off. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the RAM block MEM[14] retained when the parent power domain of the RAM is off. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the RAM block MEM[15] retained when the parent power domain of the RAM is off. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the RAM block MEM[16] retained when the parent power domain of the RAM is off. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the RAM block MEM[17] retained when the parent power domain of the RAM is off. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the RAM block MEM[18] retained when the parent power domain of the RAM is off. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the RAM block MEM[19] retained when the parent power domain of the RAM is off. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the RAM block MEM[20] retained when the parent power domain of the RAM is off. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the RAM block MEM[21] retained when the parent power domain of the RAM is off. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the RAM block MEM[22] retained when the parent power domain of the RAM is off. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the RAM block MEM[23] retained when the parent power domain of the RAM is off. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the RAM block MEM[24] retained when the parent power domain of the RAM is off. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the RAM block MEM[25] retained when the parent power domain of the RAM is off. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the RAM block MEM[26] retained when the parent power domain of the RAM is off. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the RAM block MEM[27] retained when the parent power domain of the RAM is off. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the RAM block MEM[28] retained when the parent power domain of the RAM is off. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the RAM block MEM[29] retained when the parent power domain of the RAM is off. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the RAM block MEM[30] retained when the parent power domain of the RAM is off. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the RAM block MEM[31] retained when the parent power domain of the RAM is off. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + RET2 + Description cluster: RAM retention for the second bank in the RAM block + 0x00C + read-write + 0x00000000 + 0x20 + + + MEM0 + Keep the second bank in RAM block MEM[0] retained when parent power domain of the RAM is off. + 0 + 0 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM1 + Keep the second bank in RAM block MEM[1] retained when parent power domain of the RAM is off. + 1 + 1 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM2 + Keep the second bank in RAM block MEM[2] retained when parent power domain of the RAM is off. + 2 + 2 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM3 + Keep the second bank in RAM block MEM[3] retained when parent power domain of the RAM is off. + 3 + 3 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM4 + Keep the second bank in RAM block MEM[4] retained when parent power domain of the RAM is off. + 4 + 4 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM5 + Keep the second bank in RAM block MEM[5] retained when parent power domain of the RAM is off. + 5 + 5 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM6 + Keep the second bank in RAM block MEM[6] retained when parent power domain of the RAM is off. + 6 + 6 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM7 + Keep the second bank in RAM block MEM[7] retained when parent power domain of the RAM is off. + 7 + 7 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM8 + Keep the second bank in RAM block MEM[8] retained when parent power domain of the RAM is off. + 8 + 8 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM9 + Keep the second bank in RAM block MEM[9] retained when parent power domain of the RAM is off. + 9 + 9 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM10 + Keep the second bank in RAM block MEM[10] retained when parent power domain of the RAM is off. + 10 + 10 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM11 + Keep the second bank in RAM block MEM[11] retained when parent power domain of the RAM is off. + 11 + 11 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM12 + Keep the second bank in RAM block MEM[12] retained when parent power domain of the RAM is off. + 12 + 12 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM13 + Keep the second bank in RAM block MEM[13] retained when parent power domain of the RAM is off. + 13 + 13 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM14 + Keep the second bank in RAM block MEM[14] retained when parent power domain of the RAM is off. + 14 + 14 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM15 + Keep the second bank in RAM block MEM[15] retained when parent power domain of the RAM is off. + 15 + 15 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM16 + Keep the second bank in RAM block MEM[16] retained when parent power domain of the RAM is off. + 16 + 16 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM17 + Keep the second bank in RAM block MEM[17] retained when parent power domain of the RAM is off. + 17 + 17 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM18 + Keep the second bank in RAM block MEM[18] retained when parent power domain of the RAM is off. + 18 + 18 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM19 + Keep the second bank in RAM block MEM[19] retained when parent power domain of the RAM is off. + 19 + 19 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM20 + Keep the second bank in RAM block MEM[20] retained when parent power domain of the RAM is off. + 20 + 20 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM21 + Keep the second bank in RAM block MEM[21] retained when parent power domain of the RAM is off. + 21 + 21 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM22 + Keep the second bank in RAM block MEM[22] retained when parent power domain of the RAM is off. + 22 + 22 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM23 + Keep the second bank in RAM block MEM[23] retained when parent power domain of the RAM is off. + 23 + 23 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM24 + Keep the second bank in RAM block MEM[24] retained when parent power domain of the RAM is off. + 24 + 24 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM25 + Keep the second bank in RAM block MEM[25] retained when parent power domain of the RAM is off. + 25 + 25 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM26 + Keep the second bank in RAM block MEM[26] retained when parent power domain of the RAM is off. + 26 + 26 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM27 + Keep the second bank in RAM block MEM[27] retained when parent power domain of the RAM is off. + 27 + 27 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM28 + Keep the second bank in RAM block MEM[28] retained when parent power domain of the RAM is off. + 28 + 28 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM29 + Keep the second bank in RAM block MEM[29] retained when parent power domain of the RAM is off. + 29 + 29 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM30 + Keep the second bank in RAM block MEM[30] retained when parent power domain of the RAM is off. + 30 + 30 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + MEM31 + Keep the second bank in RAM block MEM[31] retained when parent power domain of the RAM is off. + 31 + 31 + + + Off + Retention off + 0x0 + + + On + Retention on + 0x1 + + + + + + + + 192 + 0x004 + REPAIR[%s] + Unspecified + MEMCONF_REPAIR + read-write + 0x600 + + BITLINE + Description cluster: Repair configuration for RAM blocks. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDR + Repair address of the bitline + 0 + 6 + + + EN + Enable bitline repair + 31 + 31 + + + Disabled + Repair disabled. + 0x0 + + + Enabled + Repair enabled. + 0x1 + + + + + + + + 64 + 0x004 + BLOCKTYPE[%s] + Unspecified + MEMCONF_BLOCKTYPE + read-write + 0x900 + + TRIM + Description cluster: Trim configuration for the memory block types. + 0x000 + read-write + 0x00000000 + 0x20 + + + MEMTRIM_0 + Read/write margin trim. + 0 + 0 + + + MEMTRIM_1 + Read/write margin trim. + 1 + 1 + + + MEMTRIM_2 + Read/write margin trim. + 2 + 2 + + + MEMTRIM_3 + Read/write margin trim. + 3 + 3 + + + MEMTRIM_4 + Read/write margin trim. + 4 + 4 + + + MEMTRIM_5 + Read/write margin trim. + 5 + 5 + + + MEMTRIM_6 + Read/write margin trim. + 6 + 6 + + + MEMTRIM_7 + Read/write margin trim. + 7 + 7 + + + MEMTRIM_8 + Read/write margin trim. + 8 + 8 + + + MEMTRIM_9 + Read/write margin trim. + 9 + 9 + + + MEMTRIM_10 + Read/write margin trim. + 10 + 10 + + + MEMTRIM_11 + Read/write margin trim. + 11 + 11 + + + MEMTRIM_12 + Read/write margin trim. + 12 + 12 + + + MEMTRIM_13 + Read/write margin trim. + 13 + 13 + + + MEMTRIM_14 + Read/write margin trim. + 14 + 14 + + + MEMTRIM_15 + Read/write margin trim. + 15 + 15 + + + MEMRETTRIM_0 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 16 + 16 + + + MEMRETTRIM_1 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 17 + 17 + + + MEMRETTRIM_2 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 18 + 18 + + + MEMRETTRIM_3 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 19 + 19 + + + MEMRETTRIM_4 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 20 + 20 + + + MEMRETTRIM_5 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 21 + 21 + + + MEMRETTRIM_6 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 22 + 22 + + + MEMRETTRIM_7 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 23 + 23 + + + MEMRETTRIM_8 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 24 + 24 + + + MEMRETTRIM_9 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 25 + 25 + + + MEMRETTRIM_10 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 26 + 26 + + + MEMRETTRIM_11 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 27 + 27 + + + MEMRETTRIM_12 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 28 + 28 + + + MEMRETTRIM_13 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 29 + 29 + + + MEMRETTRIM_14 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 30 + 30 + + + MEMRETTRIM_15 + Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. + 31 + 31 + + + + + + + + MEMCONF_S + Memory configuration 1 + 0x53012000 + + + + + WDT010_NS + Watchdog Timer 0 + 0x43013000 + WDT + + + + 0 + 0x1000 + registers + + + WDT010 + 19 + + WDT + 0x20 + + + TASKS_START + Start WDT + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop WDT + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop WDT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + Watchdog stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Watchdog stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TIMEOUT + Publish configuration for event TIMEOUT + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + NMIENSET + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + NMIENCLR + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + 0x00000000 + 0x20 + + + RUNSTATUSWDT + Indicates whether or not WDT is running + 0 + 0 + + + NotRunning + Watchdog is not running + 0x0 + + + Running + Watchdog is running + 0x1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + 0x20 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 0x1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0x0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 0x1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + 0x20 + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + 0x20 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0x0 + + + Enabled + Enable RR[0] register + 0x1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0x0 + + + Enabled + Enable RR[1] register + 0x1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0x0 + + + Enabled + Enable RR[2] register + 0x1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0x0 + + + Enabled + Enable RR[3] register + 0x1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0x0 + + + Enabled + Enable RR[4] register + 0x1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0x0 + + + Enabled + Enable RR[5] register + 0x1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0x0 + + + Enabled + Enable RR[6] register + 0x1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0x0 + + + Enabled + Enable RR[7] register + 0x1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + 0x20 + + + SLEEP + Configure WDT to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause WDT while the CPU is sleeping + 0x0 + + + Run + Keep WDT running while the CPU is sleeping + 0x1 + + + + + HALT + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause WDT while the CPU is halted by the debugger + 0x0 + + + Run + Keep WDT running while the CPU is halted by the debugger + 0x1 + + + + + STOPEN + Allow stopping WDT + 6 + 6 + + + Disable + Do not allow stopping WDT + 0x0 + + + Enable + Allow stopping WDT + 0x1 + + + + + + + TSEN + Task stop enable + 0x520 + write-only + 0x00000000 + 0x20 + + + TSEN + Allow stopping WDT + 0 + 31 + + + Enable + Value to allow stopping WDT + 0x6E524635 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + 0x00000000 + 0x20 + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + WDT010_S + Watchdog Timer 1 + 0x53013000 + + + + WDT010 + 19 + + + + WDT011_NS + Watchdog Timer 2 + 0x43014000 + + + + WDT011 + 20 + + + + WDT011_S + Watchdog Timer 3 + 0x53014000 + + + + WDT011 + 20 + + + + LRCCONF010_S + LRCCONF 1 + 0x5301E000 + + + + + RESETINFO_S + RESETINFO + 0x5301E000 + LRCCONF010_S + RESETINFO + + + + 0 + 0x1000 + registers + + RESETINFO + 0x20 + + + RESETREAS + Unspecified + RESETINFO_RESETREAS + read-write + 0x4A0 + + GLOBAL + Global reset reason. + 0x000 + read-write + 0x00000000 + 0x20 + + + RESETPORONLY + Reset from power on reset (reset reason POR or BOR). + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + RESETPIN + Reset from pin reset detected. + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOG + Reset from the SysCtrl watchdog timer detected. + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CTRLAP + Reset from CTRL-AP detected. + 3 + 3 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECSREQ + Reset due to secure domain system reset request. + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECWDT0 + Reset due to the first instance of watchdog timer in secure domain detected. + 5 + 5 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECWDT1 + Reset due to the second instance of watchdog timer in secure domain detected. + 6 + 6 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECLOCKUP + Reset due to secure domain lockup. + 7 + 7 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SECTAMPER + Reset due to secure domain tamper detected + 8 + 8 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + RESETPOR + Reset from power on reset (reset reason other than POR or BOR). + 9 + 9 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + OFF + Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO. + 16 + 16 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LPCOMP + Reset due to wakeup from System OFF mode when wakeup is triggered by LPCOMP (Low Power Comparator). + 17 + 17 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DIF + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode. + 18 + 18 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + GRTC + Reset due to wakeup from System OFF mode when wakeup is triggered by GRTC interrupt. + 19 + 19 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + NFC + Reset due to wakeup from System OFF mode when wakeup is triggered by NFC field detection in sense mode. + 20 + 20 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + VUSB + Reset after wakeup from System OFF mode due to VBUS rising into valid range. + 21 + 21 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + + + LOCAL + Local reset reason. + 0x004 + read-write + 0x00000000 + 0x20 + + + DOG + Reset from the local watchdog timer detected + 0 + 0 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + DOGNS + Reset from the local non-secure watchdog timer detected + 1 + 1 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + SREQ + Reset from the local soft reset request detected. + 2 + 2 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + LOCKUP + Reset from local CPU lockup detected + 3 + 3 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + CROSSDOMAIN + Reset due to cross domain reset source. + 4 + 4 + + + NotDetected + Not detected + 0x0 + + + Detected + Detected + 0x1 + + + + + UNRETAINEDWAKE + Reset due to wake from unretained state. + 5 + 5 + + + + + + ERROR + Unspecified + RESETINFO_ERROR + read-write + 0x4A8 + + STATUS + Reset error status. + 0x000 + read-write + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status + 0 + 3 + + + + + ADDRESS + Reset error address. + 0x004 + read-write + 0x00000000 + 0x20 + + + ERRORADDRESS + Error address + 0 + 31 + + + + + + RESTOREVALID + Valid restore image is present in RAM. + 0x4C0 + read-write + 0x00000000 + 0x20 + + + RESTOREVALID + Valid restore image is present in RAM. + 0 + 0 + + + NotPreset + Not present + 0x0 + + + Present + Present + 0x1 + + + + + + + + + SPU020_S + System protection unit 2 + 0x53020000 + + + + SPU020 + 32 + + + + DPPIC020_NS + Distributed programmable peripheral interconnect controller 0 + 0x43022000 + DPPIC + + + + + 0 + 0x1000 + registers + + DPPIC + 0x20 + + + 4 + 0x008 + TASKS_CHG[%s] + Channel group tasks + DPPIC_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + 0x00000000 + 0x20 + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + 0x00000000 + 0x20 + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + 4 + 0x008 + SUBSCRIBE_CHG[%s] + Subscribe configuration for tasks + DPPIC_SUBSCRIBE_CHG + read-write + 0x080 + + EN + Description cluster: Subscribe configuration for task CHG[n].EN + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].EN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + DIS + Description cluster: Subscribe configuration for task CHG[n].DIS + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CHG[n].DIS will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0x0 + + + Enabled + Enable channel + 0x1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + 0x00000000 + oneToSet + 0x20 + + + CH0 + Channel 0 enable set register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH1 + Channel 1 enable set register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH2 + Channel 2 enable set register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH3 + Channel 3 enable set register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH4 + Channel 4 enable set register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH5 + Channel 5 enable set register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH6 + Channel 6 enable set register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH7 + Channel 7 enable set register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH8 + Channel 8 enable set register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH9 + Channel 9 enable set register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH10 + Channel 10 enable set register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH11 + Channel 11 enable set register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH12 + Channel 12 enable set register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH13 + Channel 13 enable set register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH14 + Channel 14 enable set register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH15 + Channel 15 enable set register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH16 + Channel 16 enable set register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH17 + Channel 17 enable set register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH18 + Channel 18 enable set register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH19 + Channel 19 enable set register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH20 + Channel 20 enable set register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH21 + Channel 21 enable set register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH22 + Channel 22 enable set register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + CH23 + Channel 23 enable set register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Set + Write: Enable channel + 0x1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + 0x00000000 + oneToClear + 0x20 + + + CH0 + Channel 0 enable clear register. Writing 0 has no effect. + 0 + 0 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH1 + Channel 1 enable clear register. Writing 0 has no effect. + 1 + 1 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH2 + Channel 2 enable clear register. Writing 0 has no effect. + 2 + 2 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH3 + Channel 3 enable clear register. Writing 0 has no effect. + 3 + 3 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH4 + Channel 4 enable clear register. Writing 0 has no effect. + 4 + 4 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH5 + Channel 5 enable clear register. Writing 0 has no effect. + 5 + 5 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH6 + Channel 6 enable clear register. Writing 0 has no effect. + 6 + 6 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH7 + Channel 7 enable clear register. Writing 0 has no effect. + 7 + 7 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH8 + Channel 8 enable clear register. Writing 0 has no effect. + 8 + 8 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH9 + Channel 9 enable clear register. Writing 0 has no effect. + 9 + 9 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH10 + Channel 10 enable clear register. Writing 0 has no effect. + 10 + 10 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH11 + Channel 11 enable clear register. Writing 0 has no effect. + 11 + 11 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH12 + Channel 12 enable clear register. Writing 0 has no effect. + 12 + 12 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH13 + Channel 13 enable clear register. Writing 0 has no effect. + 13 + 13 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH14 + Channel 14 enable clear register. Writing 0 has no effect. + 14 + 14 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH15 + Channel 15 enable clear register. Writing 0 has no effect. + 15 + 15 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH16 + Channel 16 enable clear register. Writing 0 has no effect. + 16 + 16 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH17 + Channel 17 enable clear register. Writing 0 has no effect. + 17 + 17 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH18 + Channel 18 enable clear register. Writing 0 has no effect. + 18 + 18 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH19 + Channel 19 enable clear register. Writing 0 has no effect. + 19 + 19 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH20 + Channel 20 enable clear register. Writing 0 has no effect. + 20 + 20 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH21 + Channel 21 enable clear register. Writing 0 has no effect. + 21 + 21 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH22 + Channel 22 enable clear register. Writing 0 has no effect. + 22 + 22 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + CH23 + Channel 23 enable clear register. Writing 0 has no effect. + 23 + 23 + + read + + Disabled + Read: Channel disabled + 0x0 + + + Enabled + Read: Channel enabled + 0x1 + + + + write + + Clear + Write: Disable channel + 0x1 + + + + + + + 0x4 + 0x4 + CHG[%s] + Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled + 0x800 + read-write + 0x00000000 + 0x20 + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0x0 + + + Included + Include + 0x1 + + + + + + + + + DPPIC020_S + Distributed programmable peripheral interconnect controller 1 + 0x53022000 + + + + + + PPIB020_S + PPIB APB registers 0 + 0x53023000 + PPIB + + + + 0 + 0x1000 + registers + + PPIB + 0x20 + + + 0x20 + 0x4 + TASKS_SEND[%s] + Description collection: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + OVERFLOW + Unspecified + PPIB_OVERFLOW + read-write + 0x400 + + SEND + The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + The status for tasks overflow at SUBSCRIBE_SEND[0]. + 0 + 0 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_1 + The status for tasks overflow at SUBSCRIBE_SEND[1]. + 1 + 1 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_2 + The status for tasks overflow at SUBSCRIBE_SEND[2]. + 2 + 2 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_3 + The status for tasks overflow at SUBSCRIBE_SEND[3]. + 3 + 3 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_4 + The status for tasks overflow at SUBSCRIBE_SEND[4]. + 4 + 4 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_5 + The status for tasks overflow at SUBSCRIBE_SEND[5]. + 5 + 5 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_6 + The status for tasks overflow at SUBSCRIBE_SEND[6]. + 6 + 6 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_7 + The status for tasks overflow at SUBSCRIBE_SEND[7]. + 7 + 7 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_8 + The status for tasks overflow at SUBSCRIBE_SEND[8]. + 8 + 8 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_9 + The status for tasks overflow at SUBSCRIBE_SEND[9]. + 9 + 9 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_10 + The status for tasks overflow at SUBSCRIBE_SEND[10]. + 10 + 10 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_11 + The status for tasks overflow at SUBSCRIBE_SEND[11]. + 11 + 11 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_12 + The status for tasks overflow at SUBSCRIBE_SEND[12]. + 12 + 12 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_13 + The status for tasks overflow at SUBSCRIBE_SEND[13]. + 13 + 13 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_14 + The status for tasks overflow at SUBSCRIBE_SEND[14]. + 14 + 14 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_15 + The status for tasks overflow at SUBSCRIBE_SEND[15]. + 15 + 15 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_16 + The status for tasks overflow at SUBSCRIBE_SEND[16]. + 16 + 16 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_17 + The status for tasks overflow at SUBSCRIBE_SEND[17]. + 17 + 17 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_18 + The status for tasks overflow at SUBSCRIBE_SEND[18]. + 18 + 18 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_19 + The status for tasks overflow at SUBSCRIBE_SEND[19]. + 19 + 19 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_20 + The status for tasks overflow at SUBSCRIBE_SEND[20]. + 20 + 20 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_21 + The status for tasks overflow at SUBSCRIBE_SEND[21]. + 21 + 21 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_22 + The status for tasks overflow at SUBSCRIBE_SEND[22]. + 22 + 22 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_23 + The status for tasks overflow at SUBSCRIBE_SEND[23]. + 23 + 23 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_24 + The status for tasks overflow at SUBSCRIBE_SEND[24]. + 24 + 24 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_25 + The status for tasks overflow at SUBSCRIBE_SEND[25]. + 25 + 25 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_26 + The status for tasks overflow at SUBSCRIBE_SEND[26]. + 26 + 26 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_27 + The status for tasks overflow at SUBSCRIBE_SEND[27]. + 27 + 27 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_28 + The status for tasks overflow at SUBSCRIBE_SEND[28]. + 28 + 28 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_29 + The status for tasks overflow at SUBSCRIBE_SEND[29]. + 29 + 29 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_30 + The status for tasks overflow at SUBSCRIBE_SEND[30]. + 30 + 30 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + SEND_31 + The status for tasks overflow at SUBSCRIBE_SEND[31]. + 31 + 31 + + + Overflow + Task overflow is happened. + 0x1 + + + NoOverflow + Task overflow is not happened. + 0x0 + + + + + + + + + + EGU020_NS + Event generator unit 0 + 0x43025000 + EGU + + + + 0 + 0x1000 + registers + + + EGU020 + 37 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGGER[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TRIGGERED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + EGU020_S + Event generator unit 1 + 0x53025000 + + + + EGU020 + 37 + + + + TIMER020_NS + Timer/Counter 0 + 0x43028000 + TIMER + + + + 0 + 0x1000 + registers + + + TIMER020 + 40 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_COUNT + Subscribe configuration for task COUNT + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task COUNT will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SHUTDOWN + Deprecated register - Subscribe configuration for task SHUTDOWN + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SHUTDOWN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_STOP + Shortcut between event COMPARE[6] and task STOP + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_STOP + Shortcut between event COMPARE[7] and task STOP + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + 0x00000000 + 0x20 + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0x0 + + + Counter + Deprecated enumerator - Select Counter mode + 0x1 + + + LowPowerCounter + Select Low Power Counter mode + 0x2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + 0x00000000 + 0x20 + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0x0 + + + 08Bit + 8 bit timer bit width + 0x1 + + + 24Bit + 24 bit timer bit width + 0x2 + + + 32Bit + 32 bit timer bit width + 0x3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + 0x20 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + CC + Capture/Compare value + 0 + 31 + + + + + 0x8 + 0x4 + ONESHOTEN[%s] + Description collection: Enable one-shot operation for Capture/Compare channel n + 0x580 + read-write + 0x00000000 + 0x20 + + + ONESHOTEN + Enable one-shot operation + 0 + 0 + + + Disable + Disable one-shot operation + 0x0 + + + Enable + Enable one-shot operation + 0x1 + + + + + + + + + TIMER020_S + Timer/Counter 1 + 0x53028000 + + + + TIMER020 + 40 + + + + TIMER021_NS + Timer/Counter 2 + 0x43029000 + + + + TIMER021 + 41 + + + + TIMER021_S + Timer/Counter 3 + 0x53029000 + + + + TIMER021 + 41 + + + + TIMER022_NS + Timer/Counter 4 + 0x4302A000 + + + + TIMER022 + 42 + + + + TIMER022_S + Timer/Counter 5 + 0x5302A000 + + + + TIMER022 + 42 + + + + RTC_NS + Real-time counter 0 + 0x4302B000 + RTC + + + + 0 + 0x1000 + registers + + + RTC + 43 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable event routing for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable event routing for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable event routing for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable event routing for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 23 + + + + + + + RTC_S + Real-time counter 1 + 0x5302B000 + + + + RTC + 43 + + + + RADIO_NS + 2.4 GHz radio 0 + 0x4302C000 + RADIO + + + + 0 + 0x2000 + registers + + + RADIO_0 + 44 + + + RADIO_1 + 45 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x028 + write-only + 0x00000000 + 0x20 + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x02C + write-only + 0x00000000 + 0x20 + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_TXEN + Subscribe configuration for task TXEN + 0x100 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RXEN + Subscribe configuration for task RXEN + 0x104 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RXEN will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x108 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x10C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DISABLE + Subscribe configuration for task DISABLE + 0x110 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RSSISTART + Subscribe configuration for task RSSISTART + 0x114 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RSSISTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_BCSTART + Subscribe configuration for task BCSTART + 0x118 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task BCSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_BCSTOP + Subscribe configuration for task BCSTOP + 0x11C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task BCSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_EDSTART + Subscribe configuration for task EDSTART + 0x120 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task EDSTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_EDSTOP + Subscribe configuration for task EDSTOP + 0x124 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task EDSTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CCASTART + Subscribe configuration for task CCASTART + 0x128 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CCASTART will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CCASTOP + Subscribe configuration for task CCASTOP + 0x12C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CCASTOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x200 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x204 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x208 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x20C + read-write + 0x00000000 + 0x20 + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x210 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x214 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + Packet sent or received + 0x218 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PHYEND + The last bit is sent on air or last bit is received + 0x21C + read-write + 0x00000000 + 0x20 + + + EVENTS_PHYEND + The last bit is sent on air or last bit is received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x220 + read-write + 0x00000000 + 0x20 + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x224 + read-write + 0x00000000 + 0x20 + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x228 + read-write + 0x00000000 + 0x20 + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x22C + read-write + 0x00000000 + 0x20 + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x230 + read-write + 0x00000000 + 0x20 + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x238 + read-write + 0x00000000 + 0x20 + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register) + 0x23C + read-write + 0x00000000 + 0x20 + + + EVENTS_EDEND + Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE register) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x240 + read-write + 0x00000000 + 0x20 + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x244 + read-write + 0x00000000 + 0x20 + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x248 + read-write + 0x00000000 + 0x20 + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x24C + read-write + 0x00000000 + 0x20 + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit + 0x250 + read-write + 0x00000000 + 0x20 + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x254 + read-write + 0x00000000 + 0x20 + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYNC + Initial sync detected + 0x258 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYNC + Initial sync detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CTEPRESENT + CTEInfo byte is received + 0x25C + read-write + 0x00000000 + 0x20 + + + EVENTS_CTEPRESENT + CTEInfo byte is received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x300 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXREADY + Publish configuration for event TXREADY + 0x304 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXREADY + Publish configuration for event RXREADY + 0x308 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXREADY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ADDRESS + Publish configuration for event ADDRESS + 0x30C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ADDRESS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x310 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PAYLOAD + Publish configuration for event PAYLOAD + 0x314 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PAYLOAD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x318 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PHYEND + Publish configuration for event PHYEND + 0x31C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PHYEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DISABLED + Publish configuration for event DISABLED + 0x320 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DISABLED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DEVMATCH + Publish configuration for event DEVMATCH + 0x324 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DEVMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DEVMISS + Publish configuration for event DEVMISS + 0x328 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DEVMISS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CRCOK + Publish configuration for event CRCOK + 0x32C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CRCOK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CRCERROR + Publish configuration for event CRCERROR + 0x330 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CRCERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_BCMATCH + Publish configuration for event BCMATCH + 0x338 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BCMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_EDEND + Publish configuration for event EDEND + 0x33C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event EDEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_EDSTOPPED + Publish configuration for event EDSTOPPED + 0x340 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event EDSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCAIDLE + Publish configuration for event CCAIDLE + 0x344 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCAIDLE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCABUSY + Publish configuration for event CCABUSY + 0x348 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCABUSY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CCASTOPPED + Publish configuration for event CCASTOPPED + 0x34C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CCASTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RATEBOOST + Publish configuration for event RATEBOOST + 0x350 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RATEBOOST will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_MHRMATCH + Publish configuration for event MHRMATCH + 0x354 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MHRMATCH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SYNC + Publish configuration for event SYNC + 0x358 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SYNC will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CTEPRESENT + Publish configuration for event CTEPRESENT + 0x35C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTEPRESENT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x400 + read-write + 0x00000000 + 0x20 + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 11 + 11 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 15 + 15 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 16 + 16 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 19 + 19 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 20 + 20 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET00 + Enable interrupt + 0x488 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR00 + Disable interrupt + 0x490 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x4A8 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYNC + Write '1' to enable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CTEPRESENT + Write '1' to enable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x4B0 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYNC + Write '1' to disable interrupt for event SYNC + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CTEPRESENT + Write '1' to disable interrupt for event CTEPRESENT + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Data rate and modulation + 0x500 + read-write + 0x00000000 + 0x20 + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbps Nordic proprietary radio mode + 0x0 + + + Nrf_2Mbit + 2 Mbps Nordic proprietary radio mode + 0x1 + + + Ble_1Mbit + 1 Mbps BLE + 0x3 + + + Ble_2Mbit + 2 Mbps BLE + 0x4 + + + Ble_LR125Kbit + Long range 125 kbps TX, 125 kbps and 500 kbps RX + 0x5 + + + Ble_LR500Kbit + Long range 500 kbps TX, 125 kbps and 500 kbps RX + 0x6 + + + Nrf_4Mbit0_5 + 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.5) + 0x9 + + + Nrf_4Mbit0_25 + 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.25) + 0xA + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbps + 0xF + + + + + + + STATE + Current radio state + 0x520 + read-only + 0x00000000 + 0x20 + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0x0 + + + RxRu + RADIO is in the RXRU state + 0x1 + + + RxIdle + RADIO is in the RXIDLE state + 0x2 + + + Rx + RADIO is in the RX state + 0x3 + + + RxDisable + RADIO is in the RXDISABLED state + 0x4 + + + TxRu + RADIO is in the TXRU state + 0x9 + + + TxIdle + RADIO is in the TXIDLE state + 0xA + + + Tx + RADIO is in the TX state + 0xB + + + TxDisable + RADIO is in the TXDISABLED state + 0xC + + + + + + + EDCTRL + IEEE 802.15.4 energy detect control + 0x530 + read-write + 0x20000000 + 0x20 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + EDPERIOD + IEEE 802.15.4 energy detect/cca period, 4us resolution + 24 + 29 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x534 + read-only + 0x00000000 + 0x20 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x538 + read-write + 0x052D0000 + 0x20 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0x0 + + + CarrierMode + Carrier seen + 0x1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 0x2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 0x3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 0x4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + DATAWHITEIV + Data whitening initial value + 0x540 + read-write + 0x00000040 + 0x20 + + + DATAWHITEIV + 0 + 5 + + + + + TIMING + Timing + 0x704 + read-write + 0x00000000 + 0x20 + + + RU + 0: Default ramp-up time, compatible with 180nm radio. 1: Fast ramp-up. + 0 + 0 + + + + + FREQUENCY + Frequency + 0x708 + read-write + 0x00000002 + 0x20 + + + FREQUENCY + Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). + 0 + 6 + + + MAP + Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1: Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). + 8 + 8 + + + + + TXPOWER + Output power + 0x710 + read-write + 0x00000000 + 0x20 + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos10dBm + +10 dBm + 0x0A + + + Pos9dBm + +9 dBm + 0x09 + + + Pos8dBm + +8 dBm + 0x08 + + + Pos7dBm + +7 dBm + 0x07 + + + Pos6dBm + +6 dBm + 0x06 + + + Pos5dBm + +5 dBm + 0x05 + + + Pos4dBm + +4 dBm + 0x04 + + + Pos3dBm + +3 dBm + 0x03 + + + Pos2dBm + +2 dBm + 0x02 + + + Pos1dBm + +1 dBm + 0x01 + + + 0dBm + 0 dBm + 0x00 + + + Neg1dBm + -1 dBm + 0xFF + + + Neg2dBm + -2 dBm + 0xFE + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + -30 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + Neg70dBm + -70 dBm + 0xBA + + + + + + + TIFS + Interframe spacing in us + 0x714 + read-write + 0x00000000 + 0x20 + + + TIFS + Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet. + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x718 + read-only + 0x0000007F + 0x20 + + + RSSISAMPLE + RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm. + 0 + 6 + + + + + DFEMODE + Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) + 0xD00 + read-write + 0x00000000 + 0x20 + + + DFEOPMODE + Direction finding operation mode + 0 + 1 + + + Disabled + Direction finding mode disabled + 0x0 + + + AoD + Direction finding mode set to AoD + 0x2 + + + AoA + Direction finding mode set to AoA + 0x3 + + + + + + + DFESTATUS + DFE status information + 0xD04 + read-only + 0x00000000 + 0x20 + + + SWITCHINGSTATE + Internal state of switching state machine + 0 + 2 + + + Idle + Switching state Idle + 0x0 + + + Offset + Switching state Offset + 0x1 + + + Guard + Switching state Guard + 0x2 + + + Ref + Switching state Ref + 0x3 + + + Switching + Switching state Switching + 0x4 + + + Ending + Switching state Ending + 0x5 + + + + + SAMPLINGSTATE + Internal state of sampling state machine + 4 + 4 + + + Idle + Sampling state Idle + 0x0 + + + Sampling + Sampling state Sampling + 0x1 + + + + + + + DFECTRL1 + Various configuration for Direction finding + 0xD10 + read-write + 0x00023282 + 0x20 + + + NUMBEROF8US + Length of the AoA/AoD procedure in number of 8 us units + 0 + 5 + + + DFEINEXTENSION + Add CTE extension and do antenna switching/sampling in this extension + 7 + 7 + + + CRC + AoA/AoD procedure triggered at end of CRC + 0x1 + + + Payload + Antenna switching/sampling is done in the packet payload + 0x0 + + + + + TSWITCHSPACING + Interval between every time the antenna is changed in the SWITCHING state + 8 + 10 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + + + TSAMPLESPACINGREF + Interval between samples in the REFERENCE period + 12 + 14 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + SAMPLETYPE + Whether to sample I/Q or magnitude/phase + 15 + 15 + + + IQ + Complex samples in I and Q + 0x0 + + + MagPhase + Complex samples as magnitude and phase + 0x1 + + + + + TSAMPLESPACING + Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 + 16 + 18 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + REPEATPATTERN + Repeat every antenna pattern N times. + 20 + 23 + + + NoRepeat + Do not repeat (1 time in total) + 0x0 + + + + + AGCBACKOFFGAIN + Gain will be lowered by the specified number of gain steps at the start of CTE + 24 + 27 + + + + + DFECTRL2 + Start offset for Direction finding + 0xD14 + read-write + 0x00000000 + 0x20 + + + TSWITCHOFFSET + Signed value offset after the end of the CRC before starting switching in number of 16M cycles + 0 + 12 + + + TSAMPLEOFFSET + Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + 16 + 27 + + + + + SWITCHPATTERN + GPIO patterns to be used for each antenna + 0xD28 + read-write + 0x00000000 + 0x20 + + + SWITCHPATTERN + Fill array of GPIO patterns for antenna control + 0 + 7 + + + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control + 0xD2C + write-only + 0x00000000 + 0x20 + + + CLEARPATTERN + Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor IRQ + 0 + 0 + + + + + PSEL + Unspecified + RADIO_PSEL + read-write + 0xD30 + + 0x8 + 0x4 + DFEGPIO[%s] + Description collection: Pin select for DFE pin n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DFEPACKET + DFE packet EasyDMA channel + RADIO_DFEPACKET + read-write + 0xD50 + + PTR + Data pointer + 0x000 + read-write + 0x01000000 + 0x20 + + + OFFSET + Data pointer + 0 + 15 + + + BASE + 29 + 29 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + 0x00004000 + 0x20 + + + MAXCNT + Maximum number of bytes to transfer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 15 + + + + + + CRCSTATUS + CRC status + 0xE0C + read-only + 0x00000000 + 0x20 + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0x0 + + + CRCOk + Packet received with CRC ok + 0x1 + + + + + + + RXMATCH + Received address + 0xE10 + read-only + 0x00000000 + 0x20 + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0xE14 + read-only + 0x00000000 + 0x20 + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0xE18 + read-only + 0x00000000 + 0x20 + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0xE1C + read-only + 0x00000000 + 0x20 + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0x0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 0x1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125 kbps + 0x0 + + + LR500kbit + Frame is received at 500 kbps + 0x1 + + + + + + + PCNF0 + Packet configuration register 0 + 0xE20 + read-write + 0x00000000 + 0x20 + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 21 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0x0 + + + Include + Always include S1 field in RAM independent of S1LEN + 0x1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0x0 + + + 16bit + 16-bit preamble + 0x1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 0x2 + + + LongRange + Preamble - used for BLE long range + 0x3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0x0 + + + Include + LENGTH includes CRC + 0x1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0xE28 + read-write + 0x00000000 + 0x20 + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0x0 + + + Big + Most significant bit on air first + 0x1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BASE0 + Base address 0 + 0xE2C + read-write + 0x00000000 + 0x20 + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0xE30 + read-write + 0x00000000 + 0x20 + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0xE34 + read-write + 0x00000000 + 0x20 + + + AP0 + Address prefix 0 + 0 + 7 + + + AP1 + Address prefix 1 + 8 + 15 + + + AP2 + Address prefix 2 + 16 + 23 + + + AP3 + Address prefix 3 + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0xE38 + read-write + 0x00000000 + 0x20 + + + AP4 + Address prefix 4 + 0 + 7 + + + AP5 + Address prefix 5 + 8 + 15 + + + AP6 + Address prefix 6 + 16 + 23 + + + AP7 + Address prefix 7 + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0xE3C + read-write + 0x00000000 + 0x20 + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0xE40 + read-write + 0x00000000 + 0x20 + + + ADDR0 + Enable or disable reception on logical address 0 + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR1 + Enable or disable reception on logical address 1 + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR2 + Enable or disable reception on logical address 2 + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR3 + Enable or disable reception on logical address 3 + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR4 + Enable or disable reception on logical address 4 + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR5 + Enable or disable reception on logical address 5 + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR6 + Enable or disable reception on logical address 6 + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ADDR7 + Enable or disable reception on logical address 7 + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CRCCNF + CRC configuration + 0xE44 + read-write + 0x00000000 + 0x20 + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0x0 + + + One + CRC length is one byte and CRC calculation is enabled + 0x1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 0x2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 0x3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0x0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 0x1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 0x2 + + + + + + + CRCPOLY + CRC polynomial + 0xE48 + read-write + 0x00000000 + 0x20 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0xE4C + read-write + 0x00000000 + 0x20 + + + CRCINIT + CRC initial value + 0 + 23 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0xE50 + read-write + 0x00000000 + 0x20 + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0xE70 + read-write + 0x00000000 + 0x20 + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0xE90 + read-write + 0x00000000 + 0x20 + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + BCC + Bit counter compare + 0xE94 + read-write + 0x00000000 + 0x20 + + + BCC + Bit counter compare + 0 + 31 + + + + + CTESTATUS + CTEInfo parsed from received packet + 0xEA4 + read-only + 0x00000000 + 0x20 + + + CTETIME + CTETime parsed from packet + 0 + 4 + + + RFU + RFU parsed from packet + 5 + 5 + + + CTETYPE + CTEType parsed from packet + 6 + 7 + + + + + MHRMATCHCONF + Search pattern configuration + 0xEB4 + read-write + 0x00000000 + 0x20 + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMASK + Pattern mask + 0xEB8 + read-write + 0x00000000 + 0x20 + + + MHRMATCHMASK + Pattern mask + 0 + 31 + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0xEBC + read-write + 0x000000A7 + 0x20 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + CTEINLINECONF + Configuration for CTE inline mode + 0xEC0 + read-write + 0x00002800 + 0x20 + + + CTEINLINECTRLEN + Enable parsing of CTEInfo from received packet in BLE modes + 0 + 0 + + + Enabled + Parsing of CTEInfo is enabled + 0x1 + + + Disabled + Parsing of CTEInfo is disabled + 0x0 + + + + + CTEINFOINS1 + CTEInfo is S1 byte or not + 3 + 3 + + + InS1 + CTEInfo is in S1 byte (data PDU) + 0x1 + + + NotInS1 + CTEInfo is NOT in S1 byte (advertising PDU) + 0x0 + + + + + CTEERRORHANDLING + Sampling/switching if CRC is not OK + 4 + 4 + + + Yes + Sampling and antenna switching also when CRC is not OK + 0x1 + + + No + No sampling and antenna switching when CRC is not OK + 0x0 + + + + + CTETIMEVALIDRANGE + Max range of CTETime + 6 + 7 + + + 20 + 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 0x0 + + + 31 + 31 in 8us unit + 0x1 + + + 63 + 63 in 8us unit + 0x2 + + + + + CTEINLINERXMODE1US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 10 + 12 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + CTEINLINERXMODE2US + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + 13 + 15 + + + 4us + 4us + 0x1 + + + 2us + 2us + 0x2 + + + 1us + 1us + 0x3 + + + 500ns + 0.5us + 0x4 + + + 250ns + 0.25us + 0x5 + + + 125ns + 0.125us + 0x6 + + + + + S0CONF + S0 bit pattern to match + 16 + 23 + + + S0MASK + S0 bit mask to set which bit to match + 24 + 31 + + + + + PACKETPTR + Unspecified + 0xED0 + read-write + 0x00000000 + 0x20 + + + OFFSET + 0 + 15 + + + BASE + 29 + 29 + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + 0x20 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to + its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0x0 + + + Enabled + Peripheral is powered on + 0x1 + + + + + + + + + RADIO_S + 2.4 GHz radio 1 + 0x5302C000 + + + + RADIO_0 + 44 + + + RADIO_1 + 45 + + + + LRCCONF020_S + LRCCONF 2 + 0x5302E000 + + + + + SPU030_S + System protection unit 3 + 0x53030000 + + + + SPU030 + 48 + + + + PPIB030_S + PPIB APB registers 1 + 0x53031000 + + + + + VPR_NS + VPR peripheral registers 0 + 0x43034000 + VPR + + + + 0 + 0x1000 + registers + + + VPR + 52 + + VPR + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + SUBSCRIBE_TRIGGER[%s] + Description collection: Subscribe configuration for task TASKS_TRIGGER[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + EN + Subscription enable bit + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: VPR event [n] register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + VPR event [n] register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x20 + 0x4 + PUBLISH_TRIGGERED[%s] + Description collection: Publish configuration for event EVENTS_TRIGGERED[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + EN + Publication enable bit + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + DEBUGIF + Unspecified + VPR_DEBUGIF + read-write + 0x400 + + DATA0 + Abstract Data 0. Read/write data for argument 0 + 0x10 + read-write + 0x00000000 + 0x20 + + + DATA0 + Abstract Data 0 + 0 + 31 + + + + + DATA1 + Abstract Data 1. Read/write data for argument 1 + 0x14 + read-write + 0x00000000 + 0x20 + + + DATA1 + Abstract Data 1 + 0 + 31 + + + + + DMCONTROL + Debug Module Control + 0x40 + read-write + 0x00000000 + 0x20 + + + DMACTIVE + Reset signal for the debug module. + 0 + 0 + + + Disabled + Reset the debug module itself + 0x0 + + + Enabled + Normal operation + 0x1 + + + + + NDMRESET + Reset signal output from the debug module to the system. + 1 + 1 + + + Inactive + Reset inactive + 0x0 + + + Active + Reset active + 0x1 + + + + + CLRRESETHALTREQ + Clear the halt on reset request. + 2 + 2 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the halt on reset request + 0x1 + + + + + SETRESETHALTREQ + Set the halt on reset request. + 3 + 3 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Sets the halt on reset request + 0x1 + + + + + HARTSELHI + The high 10 bits of hartsel. + 6 + 15 + write-only + + + HARTSELLO + The low 10 bits of hartsel. + 16 + 25 + write-only + + + HASEL + Definition of currently selected harts. + 26 + 26 + write-only + + + Single + Single hart selected. + 0x0 + + + Multiple + Multiple harts selected + 0x1 + + + + + ACKHAVERESET + Clear the havereset. + 28 + 28 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Clear + Clears the havereset for selected harts. + 0x1 + + + + + HARTRESET + Reset harts. + 29 + 29 + + + Deasserted + Reset de-asserted. + 0x0 + + + Asserted + Reset asserted. + 0x1 + + + + + RESUMEREQ + Resume currently selected harts. + 30 + 30 + write-only + + + NoOperation + No operation when written 0. + 0x0 + + + Resumed + Currently selected harts resumed. + 0x1 + + + + + HALTREQ + Halt currently selected harts. + 31 + 31 + write-only + + + Clear + Clears halt request bit for all currently selected harts. + 0x0 + + + Halt + Currently selected harts halted. + 0x1 + + + + + + + DMSTATUS + Debug Module Status + 0x44 + read-only + 0x00400082 + 0x20 + + + VERSION + Version of the debug module. + 0 + 3 + + + NotPresent + Debug module not present. + 0x0 + + + V011 + There is a Debug Module and it conforms to version 0.11 of this specifcation. + 0x1 + + + V013 + There is a Debug Module and it conforms to version 0.13 of this specifcation. + 0x2 + + + NonConform + There is a Debug Module but it does not conform to any available version of the spec. + 0xF + + + + + CONFSTRPTRVALID + Configuration string. + 4 + 4 + + + NotRelevant + The confstrptr0..confstrptr3 holds information which is not relevant to the configuration string. + 0x0 + + + Address + The confstrptr0..confstrptr3 holds the address of the configuration string. + 0x1 + + + + + HASRESETHALTREQ + Halt-on-reset support status. + 5 + 5 + + + No + Halt-on-reset is supported. + 0x0 + + + Yes + Halt-on-reset is not supported. + 0x1 + + + + + AUTHBUSY + Authentication busy status. + 6 + 6 + + + No + The authentication module is ready. + 0x0 + + + Yes + The authentication module is busy. + 0x1 + + + + + AUTHENTICATED + Authentication status. + 7 + 7 + + + No + Authentication required before using the debug module. + 0x0 + + + Yes + Authentication passed. + 0x1 + + + + + ANYHALTED + Any currently selected harts halted status. + 8 + 8 + + + No + None of the currently selected harts halted. + 0x0 + + + Yes + Any of the currently selected harts halted. + 0x1 + + + + + ALLHALTED + All currently selected harts halted status. + 9 + 9 + + + No + Not all of the currently selected harts halted. + 0x0 + + + Yes + All of the currently selected harts halted. + 0x1 + + + + + ANYRUNNING + Any currently selected harts running status. + 10 + 10 + + + No + None of the currently selected harts running. + 0x0 + + + Yes + Any of the currently selected harts running. + 0x1 + + + + + ALLRUNNING + All currently selected harts running status. + 11 + 11 + + + No + Not all of the currently selected harts running. + 0x0 + + + Yes + All of the currently selected harts running. + 0x1 + + + + + ANYUNAVAIL + Any currently selected harts unavailable status. + 12 + 12 + + + No + None of the currently selected harts unavailable. + 0x0 + + + Yes + Any of the currently selected harts unavailable. + 0x1 + + + + + ALLUNAVAIL + All currently selected harts unavailable status. + 13 + 13 + + + No + Not all of the currently selected harts unavailable. + 0x0 + + + Yes + All of the currently selected harts unavailable. + 0x1 + + + + + ANYNONEXISTENT + Any currently selected harts nonexistent status. + 14 + 14 + + + No + None of the currently selected harts nonexistent. + 0x0 + + + Yes + Any of the currently selected harts nonexistent. + 0x1 + + + + + ALLNONEXISTENT + All currently selected harts nonexistent status. + 15 + 15 + + + No + Not all of the currently selected harts nonexistent. + 0x0 + + + Yes + All of the currently selected harts nonexistent. + 0x1 + + + + + ANYRESUMEACK + Any currently selected harts acknowledged last resume request. + 16 + 16 + + + No + None of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + Any of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ALLRESUMEACK + All currently selected harts acknowledged last resume + 17 + 17 + + + No + Not all of the currently selected harts acknowledged last resume request. + 0x0 + + + Yes + All of the currently selected harts acknowledged last resume request. + 0x1 + + + + + ANYHAVERESET + Any currently selected harts have been reset and reset is not acknowledged. + 18 + 18 + + + No + None of the currently selected harts have been reset and reset is not acknowledget. + 0x0 + + + Yes + Any of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + ALLHAVERESET + All currently selected harts have been reset and reset is not acknowledge + 19 + 19 + + + No + Not all of the currently selected harts have been reset and reset is not acknowledge. + 0x0 + + + Yes + All of the currently selected harts have been reset and reset is not acknowledge. + 0x1 + + + + + IMPEBREAK + Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. + 22 + 22 + + + No + No implicit ebreak instruction. + 0x0 + + + Yes + Implicit ebreak instruction. + 0x1 + + + + + + + HARTINFO + Hart Information + 0x48 + read-write + 0x00000000 + 0x20 + + + DATAADDR + Data Address + 0 + 11 + read-only + + + DATASIZE + Data Size + 12 + 15 + read-only + + + DATAACCESS + Data Access + 16 + 16 + read-only + + + No + The data registers are shadowed in the hart + by CSRs. Each CSR is DXLEN bits in size, and + corresponds to a single argument. + 0x0 + + + Yes + The data registers are shadowed in the hart's + memory map. Each register takes up 4 bytes in + the memory map. + 0x1 + + + + + NSCRATCH + Number of dscratch registers + 20 + 23 + read-only + + + + + HALTSUM1 + Halt Summary 1 + 0x4C + read-write + 0x00000000 + 0x20 + + + HALTSUM1 + Halt Summary 1 + 0 + 31 + read-only + + + + + HAWINDOWSEL + Hart Array Window Select + 0x50 + read-write + 0x00000000 + 0x20 + + + HAWINDOWSEL + The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. + 0 + 14 + read-only + + + + + HAWINDOW + Hart Array Window + 0x54 + read-write + 0x00000000 + 0x20 + + + MASKDATA + Mask data. + 0 + 31 + + + + + ABSTRACTCS + Abstract Control and Status + 0x58 + read-write + 0x01000002 + 0x20 + + + DATACOUNT + Number of data registers that are implemented as part of the abstract command interface. Valid sizes are 1..12. + 0 + 3 + read-only + + + CMDERR + Command error when the abstract command fails. + 8 + 10 + + + NoError + No error. + 0x0 + + + Busy + An abstract command was executing while command, + abstractcs, or abstractauto was written, or when one of the data or progbuf registers was read + or written. This status is only written if cmderr contains 0 + 0x1 + + + NotSupported + The requested command is notsupported, + regardless of whether the hart is running or not. + 0x2 + + + Exception + An exception occurred while executing the + command (e.g. while executing theProgram Buffer). + 0x3 + + + HaltResume + The abstract command couldn't execute + because the hart wasn't in the required state (running/halted). or unavailable. + 0x4 + + + Bus + The abstract command failed due to abus + error (e.g. alignment, access size, or timeout). + 0x5 + + + Other + The command failed for another reason. + 0x7 + + + + + BUSY + Abstract command execution status. + 12 + 12 + read-only + + + NotBusy + Not busy. + 0x0 + + + Busy + An abstract command is currently being executed. + This bit is set as soon as command is written, and is not cleared until that command has completed. + 0x1 + + + + + PROGBUFSIZE + Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. + 24 + 28 + read-only + + + + + ABSTRACTCMD + Abstract command + 0x5C + write-only + 0x00000000 + 0x20 + + + CONTROL + This Field is interpreted in a command specific manner, described for each abstract command. + 0 + 23 + + + CMDTYPE + The type determines the overall functionality of this abstract command. + 24 + 31 + + + REGACCESS + Register Access Command + 0x00 + + + QUICKACCESS + Quick Access Command + 0x01 + + + MEMACCESS + Memory Access Command + 0x02 + + + + + + + ABSTRACTAUTO + Abstract Command Autoexec + 0x60 + read-write + 0x00000000 + 0x20 + + + AUTOEXECDATA + When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. + 0 + 11 + read-only + + + AUTOEXECPROGBUF + When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. + 16 + 31 + read-only + + + + + 0x4 + 0x4 + CONFSTRPTR[%s] + Description collection: Configuration String Pointer [n] + 0x64 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + NEXTDM + Next Debug Module + 0x74 + read-write + 0x00000000 + 0x20 + + + ADDR + Address + 0 + 31 + read-only + + + + + 0x10 + 0x4 + PROGBUF[%s] + Description collection: Program Buffer [n] + 0x80 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + AUTHDATA + Authentication Data + 0xC0 + read-write + 0x00000000 + 0x20 + + + DATA + Data + 0 + 31 + read-only + + + + + HALTSUM2 + Halt Summary 2 + 0xD0 + read-write + 0x00000000 + 0x20 + + + HALTSUM2 + Halt Summary 2 + 0 + 31 + read-only + + + + + HALTSUM3 + Halt Summary 3 + 0xD4 + read-write + 0x00000000 + 0x20 + + + HALTSUM3 + Halt Summary 3 + 0 + 31 + read-only + + + + + SBADDRESS3 + System Bus Addres 127:96 + 0xDC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 127:96 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBCS + System Bus Access Control and Status + 0xE0 + read-write + 0x20000000 + 0x20 + + + SBACCESS8 + 0 + 0 + read-only + + + sbaccess8 + 8-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS16 + 1 + 1 + read-only + + + sbaccess16 + 16-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS32 + 2 + 2 + read-only + + + sbaccess32 + 32-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS64 + 3 + 3 + read-only + + + sbaccess64 + 64-bit system bus accesses are supported. + 0x1 + + + + + SBACCESS128 + 4 + 4 + read-only + + + sbaccess128 + 128-bit system bus accesses are supported. + 0x1 + + + + + SBASIZE + Width of system bus addresses in bits. (0 indicates there is no bus access support.) + 5 + 11 + read-only + + + SBERROR + 12 + 14 + read-only + + + Normal + There was no bus error. + 0x0 + + + Timeout + There was a timeout. + 0x1 + + + Address + A bad address was accessed. + 0x2 + + + Alignment + There was an alignment error. + 0x3 + + + Size + An access of unsupported size was requested. + 0x4 + + + Other + Other. + 0x7 + + + + + SBREADONDATA + 15 + 15 + read-only + + + sbreadondata + Every read from sbdata0 automatically + triggers a system bus read at the (possibly autoincremented) address. + 0x1 + + + + + SBAUTOINCREMENT + 16 + 16 + read-only + + + sbautoincrement + sbaddress is incremented by the access + size (in bytes) selected in sbaccess after every system bus access. + 0x1 + + + + + SBACCESS + 17 + 19 + read-only + + + size8 + 8-bit. + 0x0 + + + size16 + 16-bit. + 0x1 + + + size32 + 32-bit. + 0x2 + + + size64 + 64-bit. + 0x3 + + + size128 + 128-bit. + 0x4 + + + + + SBREADONADDR + 20 + 20 + read-only + + + sbreadonaddr + Every write to sbaddress0 automatically + triggers a system bus read at the new address. + 0x1 + + + + + SBBUSY + 21 + 21 + read-only + + + notbusy + System bus master is not busy. + 0x0 + + + busy + System bus master is busy. + 0x1 + + + + + SBBUSYERROR + 22 + 22 + read-only + + + noerror + No error. + 0x0 + + + error + Debugger access attempted while one in progress. + 0x1 + + + + + SBVERSION + 29 + 31 + read-only + + + version0 + The System Bus interface conforms to mainline + drafts of thia RISC-V External Debug Support spec older than 1 January, 2018. + 0x0 + + + version1 + The System Bus interface conforms to RISC-V External Debug Support version 0.14.0-DRAFT. + Other values are reserved for future versions. + 0x1 + + + + + + + SBADDRESS0 + System Bus Addres 31:0 + 0xE4 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 31:0 of the physical address in + sbaddress. + 0 + 31 + read-only + + + + + SBADDRESS1 + System Bus Addres 63:32 + 0xE8 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 63:32 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBADDRESS2 + System Bus Addres 95:64 + 0xEC + read-write + 0x00000000 + 0x20 + + + ADDRESS + Accesses bits 95:64 of the physical address in + sbaddress (if the system address bus is that + wide). + 0 + 31 + read-only + + + + + SBDATA0 + System Bus Data 31:0 + 0xF0 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 31:0 of sbdata + 0 + 31 + read-only + + + + + SBDATA1 + System Bus Data 63:32 + 0xF4 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 63:32 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA2 + System Bus Data 95:64 + 0xF8 + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 95:64 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + SBDATA3 + System Bus Data 127:96 + 0xFC + read-write + 0x00000000 + 0x20 + + + DATA + Accesses bits 127:96 of sbdata (if the system bus + is that wide). + 0 + 31 + read-only + + + + + HALTSUM0 + Halt summary 0 + 0x100 + read-write + 0x00000000 + 0x20 + + + HALTSUM0 + Halt summary 0 + 0 + 31 + read-only + + + + + + CPURUN + State of the CPU after a core reset + 0x800 + read-write + 0x00000000 + 0x20 + + + EN + Controls CPU running state after a core reset. + 0 + 0 + + + Stopped + CPU stopped. If this is the CPU state after a core reset, setting this bit will change the CPU state to CPU running. + 0x0 + + + Running + CPU running. If this is the CPU state after a core reset, clearing this bit will change the CPU state to CPU stopped after a core reset. + 0x1 + + + + + + + INITPC + Initial value of the PC at CPU start. + 0x808 + read-write + 0x00000000 + 0x20 + + + INITPC + Initial value of the PC at CPU start. + 0 + 31 + + + + + + + VPR_S + VPR peripheral registers 1 + 0x53034000 + + + + VPR + 52 + + + + RAMC001_NS + RAM Controller 2 + 0x43038000 + + + + + RAMC001_S + RAM Controller 3 + 0x53038000 + + + + + AAR030_NS + Accelerated Address Resolver 0 + 0x4303A000 + AAR + + + + 0 + 0x1000 + registers + + + AAR030_CCM030 + 58 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESOLVED + Publish configuration for event RESOLVED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESOLVED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NOTRESOLVED + Publish configuration for event NOTRESOLVED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NOTRESOLVED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable AAR + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x3 + + + + + + + MAXRESOLVED + Maximum number of IRKs to resolve + 0x508 + read-write + 0x00000001 + 0x20 + + + MAXRESOLVED + The maximum number of IRKs to resolve + 0 + 11 + + + + + IN + IN EasyDMA channel + AAR_IN + read-write + 0x530 + + PTR + Input pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Points to a job list containing AAR data structure + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + AAR_OUT + read-write + 0x538 + + PTR + Output pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x004 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes written to memory after triggering the START task. + 0 + 7 + + + + + + + + CCM030_NS + AES CCM Mode Encryption 0 + 0x4303A000 + AAR030_NS + CCM + + + + 0 + 0x1000 + registers + + + AAR030_CCM030 + 58 + + CCM + 0x20 + + + TASKS_START + Start encryption/decryption. This operation will stop by itself when completed. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RATEOVERRIDE + Subscribe configuration for task RATEOVERRIDE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RATEOVERRIDE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Encrypt/decrypt complete or ended because of an error + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Encrypt/decrypt complete or ended because of an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + CCM error event + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MACSTATUS + MAC check result + 0x400 + read-only + 0x00000000 + 0x20 + + + MACSTATUS + The result of the MAC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MAC check failed + 0x0 + + + CheckPassed + MAC check passed + 0x1 + + + + + + + ERRORSTATUS + Error status + 0x404 + read-only + 0x00000000 + 0x20 + + + ERRORSTATUS + Error status when the ERROR event is generated + 0 + 2 + + + NoError + No errors have occurred + 0x0 + + + PrematureInptrEnd + End of INPTR job list before CCM data structure was read. + 0x1 + + + PrematureOutptrEnd + End of OUTPTR job list before CCM data structure was read. + 0x2 + + + EncryptionTooSlow + Encryption of the unencrypted CCM data structure did not complete in time. + 0x3 + + + + + + + ENABLE + Enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + 0x20 + + + MODE + The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. + 0 + 1 + + + Encryption + AES CCM packet encryption mode + 0x0 + + + Decryption + AES CCM packet decryption mode + 0x1 + + + FastDecryption + AES fast decrypt mode. This mode will run CCM decryption as fast as possible, i.e. not locked to a radio data rate. This can be used when a packet has been completely received. + 0x2 + + + + + PROTOCOL + Protocol and packet format selection + 8 + 9 + + + Ble + Bluetooth Low Energy packet format + 0x0 + + + Ieee802154 + 802.15.4 packet format + 0x1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 18 + + + 125Kbit + 125 Kbps + 0x0 + + + 250Kbit + 250 Kbps + 0x1 + + + 500Kbit + 500 Kbps + 0x2 + + + 1Mbit + 1 Mbps + 0x3 + + + 2Mbit + 2 Mbps + 0x4 + + + 4Mbit + 4 Mbps + 0x5 + + + + + MACLEN + CCM MAC length (bytes) + 24 + 26 + + + M0 + M = 0 This is a special case for CCM* where encryption is required but not authentication + 0x0 + + + M4 + M = 4 + 0x1 + + + M6 + M = 6 + 0x2 + + + M8 + M = 8 + 0x3 + + + M10 + M = 10 + 0x4 + + + M12 + M = 12 + 0x5 + + + M14 + M = 14 + 0x6 + + + M16 + M = 16 + 0x7 + + + + + + + KEY + Unspecified + CCM_KEY + read-write + 0x510 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 128-bit AES key + 0x000 + write-only + 0x00000000 + 0x20 + + + VALUE + AES 128-bit key value, bits (32*(i+1))-1 : (32*i) + 0 + 31 + + + + + + NONCE + Unspecified + CCM_NONCE + read-write + 0x520 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 13-byte NONCE vector Only the lower 13 bytes are used + 0x000 + read-write + 0x00000000 + 0x20 + + + VALUE + NONCE value, bits (32*(n+1))-1 : (32*n) + 0 + 31 + + + + + + IN + IN EasyDMA channel + CCM_IN + read-write + 0x530 + + PTR + Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job list containing encrypted CCM data structure in Decryption mode + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Input pointer + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + CCM_OUT + read-write + 0x538 + + PTR + Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job list containing decrypted CCM data structure in Decryption mode + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + + RATEOVERRIDE + Data rate override setting. + 0x544 + read-write + 0x00000002 + 0x20 + + + RATEOVERRIDE + Data rate override setting. + 0 + 2 + + + 125Kbit + 125 Kbps + 0x0 + + + 500Kbit + 500 Kbps + 0x2 + + + + + + + ADATAMASK + CCM adata mask. + 0x548 + read-write + 0x000000E3 + 0x20 + + + ADATAMASK + CCM adata mask. + 0 + 7 + + + + + + + AAR030_S + Accelerated Address Resolver 1 + 0x5303A000 + + + + AAR030_CCM030 + 58 + + + + CCM030_S + AES CCM Mode Encryption 1 + 0x5303A000 + AAR030_S + + + + AAR030_CCM030 + 58 + + + + ECB030_NS + AES ECB Mode Encryption 0 + 0x4303B000 + ECB + + + + 0 + 0x1000 + registers + + + ECB030 + 59 + + ECB + 0x20 + + + TASKS_START + Start ECB block encrypt + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Abort a possible executing ECB operation + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + ECB block encrypt complete + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + ECB block encrypt aborted because of a STOP task or due to an error + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + ECB block encrypt aborted because of a STOP task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + KEY + Unspecified + ECB_KEY + read-write + 0x510 + + 0x4 + 0x4 + VALUE[%s] + Description collection: 128-bit AES key + 0x000 + write-only + 0x00000000 + 0x20 + + + VALUE + AES 128-bit key value, bits (32*(n+1))-1 : (32*n) + 0 + 31 + + + + + + IN + IN EasyDMA channel + ECB_IN + read-write + 0x530 + + PTR + Input pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Points to a job list containing unencrypted ECB data structure + 0 + 31 + + + + + AMOUNT + Number of bytes read from the input data, not including the job list structure + 0x004 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes read from the input data + 0 + 31 + + + + + + OUT + OUT EasyDMA channel + ECB_OUT + read-write + 0x538 + + PTR + Output pointer Points to a job list containing encrypted ECB data structure + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Output pointer + 0 + 31 + + + + + AMOUNT + Number of bytes available in the output data, not including the job list structure + 0x004 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes available in the output data + 0 + 31 + + + + + + + + ECB030_S + AES ECB Mode Encryption 1 + 0x5303B000 + + + + ECB030 + 59 + + + + AAR031_NS + Accelerated Address Resolver 2 + 0x4303C000 + + + + AAR031_CCM031 + 60 + + + + CCM031_NS + AES CCM Mode Encryption 2 + 0x4303C000 + AAR031_NS + + + + AAR031_CCM031 + 60 + + + + AAR031_S + Accelerated Address Resolver 3 + 0x5303C000 + + + + AAR031_CCM031 + 60 + + + + CCM031_S + AES CCM Mode Encryption 3 + 0x5303C000 + AAR031_S + + + + AAR031_CCM031 + 60 + + + + ECB031_NS + AES ECB Mode Encryption 2 + 0x4303D000 + + + + ECB031 + 61 + + + + ECB031_S + AES ECB Mode Encryption 3 + 0x5303D000 + + + + ECB031 + 61 + + + + IPCT_NS + IPCT APB registers 0 + 0x43024000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT_0 + 64 + + + IPCT_1 + 65 + + IPCT + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE4_FLUSH4 + Shortcut between event RECEIVE[4] and task FLUSH[4] + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE5_FLUSH5 + Shortcut between event RECEIVE[5] and task FLUSH[5] + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE6_FLUSH6 + Shortcut between event RECEIVE[6] and task FLUSH[6] + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE7_FLUSH7 + Shortcut between event RECEIVE[7] and task FLUSH[7] + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_4 + Overflow status for SEND[4] task + 4 + 4 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_5 + Overflow status for SEND[5] task + 5 + 5 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_6 + Overflow status for SEND[6] task + 6 + 6 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_7 + Overflow status for SEND[7] task + 7 + 7 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + IPCT_S + IPCT APB registers 1 + 0x53024000 + + + + + IPCT_0 + 64 + + + IPCT_1 + 65 + + + + SWI0_NS + Software interrupt 0 + 0x42058000 + SWI + + + + 0 + 0x1000 + registers + + + SWI0 + 88 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + SWI1_NS + Software interrupt 1 + 0x42059000 + + + + SWI1 + 89 + + + + SWI2_NS + Software interrupt 2 + 0x4205A000 + + + + SWI2 + 90 + + + + SWI3_NS + Software interrupt 3 + 0x4205B000 + + + + SWI3 + 91 + + + + SWI4_NS + Software interrupt 4 + 0x4205C000 + + + + SWI4 + 92 + + + + SWI5_NS + Software interrupt 5 + 0x4205D000 + + + + SWI5 + 93 + + + + SWI6_NS + Software interrupt 6 + 0x4205E000 + + + + SWI6 + 94 + + + + SWI7_NS + Software interrupt 7 + 0x4205F000 + + + + SWI7 + 95 + + + + BELLBOARD_NS + BELLBOARD APB registers 0 + 0x4F09B000 + BELLBOARD + + + + + 0 + 0x1000 + registers + + + BELLBOARD_0 + 96 + + + BELLBOARD_1 + 97 + + + BELLBOARD_2 + 98 + + + BELLBOARD_3 + 99 + + BELLBOARD + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x20 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event TRIGGERED[n] + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TRIGGERED + Event TRIGGERED[n] + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + 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status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 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Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable 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+ + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + 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write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED16 + Enable or disable interrupt for event TRIGGERED[16] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED17 + Enable or disable interrupt for event TRIGGERED[17] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED18 + Enable or disable interrupt for event TRIGGERED[18] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED19 + Enable or disable interrupt for event TRIGGERED[19] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED20 + Enable or disable interrupt for event TRIGGERED[20] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED21 + Enable or disable interrupt for event TRIGGERED[21] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED22 + Enable or disable interrupt for event TRIGGERED[22] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED23 + Enable or disable interrupt for event TRIGGERED[23] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED24 + Enable or disable interrupt for event TRIGGERED[24] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED25 + Enable or disable interrupt for event TRIGGERED[25] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED26 + Enable or disable interrupt for event TRIGGERED[26] + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED27 + Enable or disable interrupt for event TRIGGERED[27] + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED28 + Enable or disable interrupt for event TRIGGERED[28] + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED29 + Enable or disable interrupt for event TRIGGERED[29] + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED30 + Enable or disable interrupt for event TRIGGERED[30] + 30 + 30 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TRIGGERED31 + Enable or disable interrupt for event TRIGGERED[31] + 31 + 31 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED16 + Write '1' to enable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED17 + Write '1' to enable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED18 + Write '1' to enable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED19 + Write '1' to enable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED20 + Write '1' to enable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED21 + Write '1' to enable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED22 + Write '1' to enable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED23 + Write '1' to enable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED24 + Write '1' to enable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED25 + Write '1' to enable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED26 + Write '1' to enable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED27 + Write '1' to enable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED28 + Write '1' to enable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED29 + Write '1' to enable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED30 + Write '1' to enable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TRIGGERED31 + Write '1' to enable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED16 + Write '1' to disable interrupt for event TRIGGERED[16] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED17 + Write '1' to disable interrupt for event TRIGGERED[17] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED18 + Write '1' to disable interrupt for event TRIGGERED[18] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED19 + Write '1' to disable interrupt for event TRIGGERED[19] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED20 + Write '1' to disable interrupt for event TRIGGERED[20] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED21 + Write '1' to disable interrupt for event TRIGGERED[21] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED22 + Write '1' to disable interrupt for event TRIGGERED[22] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED23 + Write '1' to disable interrupt for event TRIGGERED[23] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED24 + Write '1' to disable interrupt for event TRIGGERED[24] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED25 + Write '1' to disable interrupt for event TRIGGERED[25] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED26 + Write '1' to disable interrupt for event TRIGGERED[26] + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED27 + Write '1' to disable interrupt for event TRIGGERED[27] + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED28 + Write '1' to disable interrupt for event TRIGGERED[28] + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED29 + Write '1' to disable interrupt for event TRIGGERED[29] + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED30 + Write '1' to disable interrupt for event TRIGGERED[30] + 30 + 30 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TRIGGERED31 + Write '1' to disable interrupt for event TRIGGERED[31] + 31 + 31 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + TRIGGERED0 + Read pending status of interrupt for event TRIGGERED[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED1 + Read pending status of interrupt for event TRIGGERED[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED2 + Read pending status of interrupt for event TRIGGERED[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED3 + Read pending status of interrupt for event TRIGGERED[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED4 + Read pending status of interrupt for event TRIGGERED[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED5 + Read pending status of interrupt for event TRIGGERED[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED6 + Read pending status of interrupt for event TRIGGERED[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED7 + Read pending status of interrupt for event TRIGGERED[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED8 + Read pending status of interrupt for event TRIGGERED[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED9 + Read pending status of interrupt for event TRIGGERED[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED10 + Read pending status of interrupt for event TRIGGERED[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED11 + Read pending status of interrupt for event TRIGGERED[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED12 + Read pending status of interrupt for event TRIGGERED[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED13 + Read pending status of interrupt for event TRIGGERED[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED14 + Read pending status of interrupt for event TRIGGERED[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED15 + Read pending status of interrupt for event TRIGGERED[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED16 + Read pending status of interrupt for event TRIGGERED[16] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED17 + Read pending status of interrupt for event TRIGGERED[17] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED18 + Read pending status of interrupt for event TRIGGERED[18] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED19 + Read pending status of interrupt for event TRIGGERED[19] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED20 + Read pending status of interrupt for event TRIGGERED[20] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED21 + Read pending status of interrupt for event TRIGGERED[21] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED22 + Read pending status of interrupt for event TRIGGERED[22] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED23 + Read pending status of interrupt for event TRIGGERED[23] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED24 + Read pending status of interrupt for event TRIGGERED[24] + 24 + 24 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED25 + Read pending status of interrupt for event TRIGGERED[25] + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED26 + Read pending status of interrupt for event TRIGGERED[26] + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED27 + Read pending status of interrupt for event TRIGGERED[27] + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED28 + Read pending status of interrupt for event TRIGGERED[28] + 28 + 28 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED29 + Read pending status of interrupt for event TRIGGERED[29] + 29 + 29 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED30 + Read pending status of interrupt for event TRIGGERED[30] + 30 + 30 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + TRIGGERED31 + Read pending status of interrupt for event TRIGGERED[31] + 31 + 31 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + BELLBOARD_S + BELLBOARD APB registers 1 + 0x5F09B000 + + + + + BELLBOARD_0 + 96 + + + BELLBOARD_1 + 97 + + + BELLBOARD_2 + 98 + + + BELLBOARD_3 + 99 + + + + GLOBAL_GPIOTE130_NS + GPIO Tasks and Events 0 + 0x4F934000 + GPIOTE + + + + + 0 + 0x1000 + registers + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + 0x00000000 + 0x20 + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + 0x00000000 + 0x20 + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_OUT[%s] + Description collection: Subscribe configuration for task OUT[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task OUT[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SET[%s] + Description collection: Subscribe configuration for task SET[n] + 0x0B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SET[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CLR[%s] + Description collection: Subscribe configuration for task CLR[n] + 0x0E0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLR[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event from pin specified in CONFIG[n].PSEL + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_IN + Event from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 4 + 0x008 + EVENTS_PORT[%s] + Peripheral events. + GLOBAL_GPIOTE_EVENTS_PORT + read-write + 0x140 + + NONSECURE + Description cluster: Non-secure port event from owner n + 0x000 + read-write + 0x00000000 + 0x20 + + + + NONSECURE + Non-secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SECURE + Description cluster: Secure port event from owner n + 0x004 + read-write + 0x00000000 + 0x20 + + + + SECURE + Secure port event from owner n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_IN[%s] + Description collection: Publish configuration for event IN[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event IN[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 4 + 0x008 + PUBLISH_PORT[%s] + Publish configuration for events + GLOBAL_GPIOTE_PUBLISH_PORT + read-write + 0x1C0 + + NONSECURE + Description cluster: Publish configuration for event PORT[n].NONSECURE + 0x000 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].NONSECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SECURE + Description cluster: Publish configuration for event PORT[n].SECURE + 0x004 + read-write + 0x00000000 + 0x20 + + + + CHIDX + DPPI channel that event PORT[n].SECURE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0NONSECURE + Write '1' to enable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT0SECURE + Write '1' to enable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1NONSECURE + Write '1' to enable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT1SECURE + Write '1' to enable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2NONSECURE + Write '1' to enable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT2SECURE + Write '1' to enable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3NONSECURE + Write '1' to enable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PORT3SECURE + Write '1' to enable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0NONSECURE + Write '1' to disable interrupt for event PORT0NONSECURE + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT0SECURE + Write '1' to disable interrupt for event PORT0SECURE + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1NONSECURE + Write '1' to disable interrupt for event PORT1NONSECURE + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT1SECURE + Write '1' to disable interrupt for event PORT1SECURE + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2NONSECURE + Write '1' to disable interrupt for event PORT2NONSECURE + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT2SECURE + Write '1' to disable interrupt for event PORT2SECURE + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3NONSECURE + Write '1' to disable interrupt for event PORT3NONSECURE + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PORT3SECURE + Write '1' to disable interrupt for event PORT3SECURE + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + 0x20 + + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting + 0x0 + + + LowLatency + Low latency setting + 0x1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event + 0x510 + read-write + 0x00000000 + 0x20 + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0x0 + + + Event + Event mode + 0x1 + + + Task + Task mode + 0x3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event + 4 + 8 + + + PORT + Port number + 9 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0x0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 0x1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 0x2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 0x3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0x0 + + + High + Task mode: Initial value of pin before task triggering is high + 0x1 + + + + + + + + + GLOBAL_GPIOTE130_S + GPIO Tasks and Events 1 + 0x5F934000 + + + + + GPIOTE130_0 + 104 + + + GPIOTE130_1 + 105 + + + + GLOBAL_GPIOTE131_NS + GPIO Tasks and Events 2 + 0x4F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GPIOTE131_S + GPIO Tasks and Events 3 + 0x5F935000 + + + + + GPIOTE131_0 + 106 + + + GPIOTE131_1 + 107 + + + + GLOBAL_GRTC_NS + Global Real-time counter 0 + 0x4F99C000 + GRTC + + + + + 0 + 0x1000 + registers + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + GRTC + 0x20 + + + 0x10 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture the counter value to CC[n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture the counter value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTART + Start the PWM + 0x06C + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTART + Start the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PWMSTOP + Stop the PWM + 0x070 + write-only + 0x00000000 + 0x20 + + + TASKS_PWMSTOP + Stop the PWM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x10 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x10 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0x164 + read-write + 0x00000000 + 0x20 + + + EVENTS_RTCOMPARESYNC + Synchronize always-on LFCLK clock domain + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0x168 + read-write + 0x00000000 + 0x20 + + + EVENTS_SYSCOUNTERVALID + The SYSCOUNTER is in active state and value is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0x16C + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Event on end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x10 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + INTEN0 + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET0 + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR0 + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND0 + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN1 + Enable or disable interrupt + 0x310 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET1 + Enable interrupt + 0x314 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR1 + Disable interrupt + 0x318 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND1 + Pending interrupts + 0x31C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN2 + Enable or disable interrupt + 0x320 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET2 + Enable interrupt + 0x324 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR2 + Disable interrupt + 0x328 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND2 + Pending interrupts + 0x32C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN3 + Enable or disable interrupt + 0x330 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET3 + Enable interrupt + 0x334 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR3 + Disable interrupt + 0x338 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND3 + Pending interrupts + 0x33C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN4 + Enable or disable interrupt + 0x340 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET4 + Enable interrupt + 0x344 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR4 + Disable interrupt + 0x348 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND4 + Pending interrupts + 0x34C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN5 + Enable or disable interrupt + 0x350 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET5 + Enable interrupt + 0x354 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR5 + Disable interrupt + 0x358 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND5 + Pending interrupts + 0x35C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN6 + Enable or disable interrupt + 0x360 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET6 + Enable interrupt + 0x364 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR6 + Disable interrupt + 0x368 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND6 + Pending interrupts + 0x36C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN7 + Enable or disable interrupt + 0x370 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET7 + Enable interrupt + 0x374 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR7 + Disable interrupt + 0x378 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND7 + Pending interrupts + 0x37C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN8 + Enable or disable interrupt + 0x380 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET8 + Enable interrupt + 0x384 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR8 + Disable interrupt + 0x388 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND8 + Pending interrupts + 0x38C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN9 + Enable or disable interrupt + 0x390 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET9 + Enable interrupt + 0x394 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR9 + Disable interrupt + 0x398 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND9 + Pending interrupts + 0x39C + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN10 + Enable or disable interrupt + 0x3A0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET10 + Enable interrupt + 0x3A4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR10 + Disable interrupt + 0x3A8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND10 + Pending interrupts + 0x3AC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN11 + Enable or disable interrupt + 0x3B0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET11 + Enable interrupt + 0x3B4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR11 + Disable interrupt + 0x3B8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND11 + Pending interrupts + 0x3BC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN12 + Enable or disable interrupt + 0x3C0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET12 + Enable interrupt + 0x3C4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR12 + Disable interrupt + 0x3C8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND12 + Pending interrupts + 0x3CC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN13 + Enable or disable interrupt + 0x3D0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET13 + Enable interrupt + 0x3D4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR13 + Disable interrupt + 0x3D8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND13 + Pending interrupts + 0x3DC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN14 + Enable or disable interrupt + 0x3E0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET14 + Enable interrupt + 0x3E4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR14 + Disable interrupt + 0x3E8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND14 + Pending interrupts + 0x3EC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + INTEN15 + Enable or disable interrupt + 0x3F0 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Enable or disable interrupt for event COMPARE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable interrupt for event COMPARE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable interrupt for event COMPARE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable interrupt for event COMPARE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable interrupt for event COMPARE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable interrupt for event COMPARE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable interrupt for event COMPARE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable interrupt for event COMPARE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE8 + Enable or disable interrupt for event COMPARE[8] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE9 + Enable or disable interrupt for event COMPARE[9] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE10 + Enable or disable interrupt for event COMPARE[10] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE11 + Enable or disable interrupt for event COMPARE[11] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE12 + Enable or disable interrupt for event COMPARE[12] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE13 + Enable or disable interrupt for event COMPARE[13] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE14 + Enable or disable interrupt for event COMPARE[14] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE15 + Enable or disable interrupt for event COMPARE[15] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RTCOMPARESYNC + Enable or disable interrupt for event RTCOMPARESYNC + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SYSCOUNTERVALID + Enable or disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET15 + Enable interrupt + 0x3F4 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE8 + Write '1' to enable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE9 + Write '1' to enable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE10 + Write '1' to enable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE11 + Write '1' to enable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE12 + Write '1' to enable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE13 + Write '1' to enable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE14 + Write '1' to enable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE15 + Write '1' to enable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to enable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to enable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR15 + Disable interrupt + 0x3F8 + read-write + 0x00000000 + 0x20 + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE8 + Write '1' to disable interrupt for event COMPARE[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE9 + Write '1' to disable interrupt for event COMPARE[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE10 + Write '1' to disable interrupt for event COMPARE[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE11 + Write '1' to disable interrupt for event COMPARE[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE12 + Write '1' to disable interrupt for event COMPARE[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE13 + Write '1' to disable interrupt for event COMPARE[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE14 + Write '1' to disable interrupt for event COMPARE[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE15 + Write '1' to disable interrupt for event COMPARE[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RTCOMPARESYNC + Write '1' to disable interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SYSCOUNTERVALID + Write '1' to disable interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND15 + Pending interrupts + 0x3FC + read-only + 0x00000000 + 0x20 + + + COMPARE0 + Read pending status of interrupt for event COMPARE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE1 + Read pending status of interrupt for event COMPARE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE2 + Read pending status of interrupt for event COMPARE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE3 + Read pending status of interrupt for event COMPARE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE4 + Read pending status of interrupt for event COMPARE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE5 + Read pending status of interrupt for event COMPARE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE6 + Read pending status of interrupt for event COMPARE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE7 + Read pending status of interrupt for event COMPARE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE8 + Read pending status of interrupt for event COMPARE[8] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE9 + Read pending status of interrupt for event COMPARE[9] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE10 + Read pending status of interrupt for event COMPARE[10] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE11 + Read pending status of interrupt for event COMPARE[11] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE12 + Read pending status of interrupt for event COMPARE[12] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE13 + Read pending status of interrupt for event COMPARE[13] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE14 + Read pending status of interrupt for event COMPARE[14] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPARE15 + Read pending status of interrupt for event COMPARE[15] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RTCOMPARESYNC + Read pending status of interrupt for event RTCOMPARESYNC + 25 + 25 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SYSCOUNTERVALID + Read pending status of interrupt for event SYSCOUNTERVALID + 26 + 26 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 27 + 27 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x400 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Enable or disable event routing for event PWMPERIODEND + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x404 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to enable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x408 + read-write + 0x00000000 + 0x20 + + + PWMPERIODEND + Write '1' to disable event routing for event PWMPERIODEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + MODE + Counter mode selection + 0x510 + read-write + 0x00000000 + 0x20 + + + AUTOEN + Automatic enable to keep the SYSCOUNTER active. + 0 + 0 + + + Default + Default configuration to keep the SYSCOUNTER active. + 0x0 + + + CpuActive + In addition to the above mode, any local CPU that is not sleeping keep the SYSCOUNTER active. + 0x1 + + + + + SYSCOUNTEREN + Enable the SYSCOUNTER + 1 + 1 + + + Disabled + SYSCOUNTER disabled + 0x0 + + + Enabled + SYSCOUNTER enabled + 0x1 + + + + + + + 16 + 0x010 + CC[%s] + Unspecified + GRTC_CC + read-write + 0x520 + + CCL + Description cluster: The lower 32-bits of Capture/Compare register CC[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CCL + Capture/Compare low value in 1 us + 0 + 31 + + + + + CCH + Description cluster: The higher 32-bits of Capture/Compare register CC[n] + 0x004 + read-write + 0x00000000 + 0x20 + + + CCH + Capture/Compare high value in 1 us + 0 + 19 + + + + + CCADD + Description cluster: Count to add to CC[n] when this register is written. + 0x008 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[n] + 0 + 30 + + + REFERENCE + Configure the Capture/Compare register + 31 + 31 + + + SYSCOUNTER + Adds SYSCOUNTER value. + 0x0 + + + CC + Adds CC value. + 0x1 + + + + + + + CCEN + Description cluster: Configure Capture/Compare register CC[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + ACTIVE + Configure the Capture/Compare register + 0 + 0 + + + Disable + Capture/Compare register CC[n] Disabled. + 0x0 + + + Enable + Capture/Compare register CC[n] enabled. + 0x1 + + + + + + + + KEEPRUNNING + Request to keep the SYSCOUNTER in the active state and prevent going to sleep + 0x6A0 + read-write + 0x00000000 + 0x20 + + + REQUEST_0 + Request from index [0] + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_1 + Request from index [1] + 1 + 1 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_2 + Request from index [2] + 2 + 2 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_3 + Request from index [3] + 3 + 3 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_4 + Request from index [4] + 4 + 4 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_5 + Request from index [5] + 5 + 5 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_6 + Request from index [6] + 6 + 6 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_7 + Request from index [7] + 7 + 7 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_8 + Request from index [8] + 8 + 8 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_9 + Request from index [9] + 9 + 9 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_10 + Request from index [10] + 10 + 10 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_11 + Request from index [11] + 11 + 11 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_12 + Request from index [12] + 12 + 12 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_13 + Request from index [13] + 13 + 13 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_14 + Request from index [14] + 14 + 14 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + REQUEST_15 + Request from index [15] + 15 + 15 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + TIMEOUT + Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER + 0x6A4 + read-write + 0x00000000 + 0x20 + + + VALUE + Number of 32Ki cycles + 0 + 15 + + + + + INTERVAL + Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. + 0x6A8 + read-write + 0x00000000 + 0x20 + + + VALUE + Count to add to CC[0] + 0 + 15 + + + + + PWMCONFIG + PWM configuration. + 0x710 + read-write + 0x00000000 + 0x20 + + + COMPAREVALUE + The PWM compare value + 0 + 7 + + + + + CLKOUT + Configuration of clock output + 0x714 + read-write + 0x00000000 + 0x20 + + + CLKOUT32K + Enable 32Ki clock output on pin + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + CLKOUTFAST + Enable fast clock output on pin + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + CLKCFG + Clock Configuration + 0x718 + read-write + 0x00010001 + 0x20 + + + CLKFASTDIV + Fast clock divisor value of clock output + 0 + 7 + + + CLKSEL + GRTC LFCLK clock source selection + 16 + 17 + + + LFXO + GRTC LFCLK clock source is LFXO + 0x0 + + + SystemLFCLK + GRTC LFCLK clock source is system LFCLK + 0x1 + + + + + + + 16 + 0x010 + SYSCOUNTER[%s] + Unspecified + GRTC_SYSCOUNTER + read-write + 0x720 + + SYSCOUNTERL + Description cluster: The lower 32-bits of the SYSCOUNTER for index [n] + 0x000 + read-only + 0x00000000 + 0x20 + + + VALUE + The lower 32-bits of the SYSCOUNTER value. + 0 + 31 + + + + + SYSCOUNTERH + Description cluster: The higher 20-bits of the SYSCOUNTER for index [n] + 0x004 + read-only + 0x40000000 + 0x20 + + + VALUE + The higher 20-bits of the SYSCOUNTER value. + 0 + 19 + + + BUSY + SYSCOUNTER busy status + 30 + 30 + + + Ready + SYSCOUNTER is ready for read + 0x0 + + + Busy + SYSCOUNTER is busy, so not ready for read (value returned in the VALUE field of this register is not valid) + 0x1 + + + + + OVERFLOW + The SYSCOUNTERL overflow indication after reading it. + 31 + 31 + + + NoOverflow + SYSCOUNTERL is not overflown + 0x0 + + + Overflow + SYSCOUNTERL overflown + 0x1 + + + + + + + ACTIVE + Description cluster: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] + 0x008 + read-write + 0x00000000 + 0x20 + + + ACTIVE + Keep SYSCOUNTER in active state + 0 + 0 + + + NotActive + Allow SYSCOUNTER to go to sleep + 0x0 + + + Active + Keep SYSCOUNTER active + 0x1 + + + + + + + + + + GLOBAL_GRTC_S + Global Real-time counter 1 + 0x5F99C000 + + + + + GRTC_0 + 108 + + + GRTC_1 + 109 + + + GRTC_2 + 110 + + + + GLOBAL_TBM_NS + Trace buffer monitor 0 + 0xBF003000 + TBM + + + + 0 + 0x1000 + registers + + + TBM + 127 + + TBM + 0x20 + + + TASKS_START + Start counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop counter, clear counter value + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop counter, clear counter value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Save current counter value to COUNTSNAPSHOT + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_HALFFULL + Counter value equals half-full + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_HALFFULL + Counter value equals half-full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FULL + Counter value equals full + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_FULL + Counter value equals full + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_FLUSH + Counter value saved to COUNTSNAPSHOT due to flush + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Enable or disable interrupt for event HALFFULL + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FULL + Enable or disable interrupt for event FULL + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FLUSH + Enable or disable interrupt for event FLUSH + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to enable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FULL + Write '1' to enable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FLUSH + Write '1' to enable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + HALFFULL + Write '1' to disable interrupt for event HALFFULL + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FULL + Write '1' to disable interrupt for event FULL + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FLUSH + Write '1' to disable interrupt for event FLUSH + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + HALFFULL + Read pending status of interrupt for event HALFFULL + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FULL + Read pending status of interrupt for event FULL + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + FLUSH + Read pending status of interrupt for event FLUSH + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + BUFFERSIZE + System RAM trace buffer total size in bytes + 0x400 + read-write + 0x00000400 + 0x20 + + + BUFFERSIZE + Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to make + half-buffer size always 64 bit word aligned. Typical minimum BUFFERSIZE value 0x010 i.e. 16 bytes, typical + maximum value 0x1000 i.e. 4096 bytes. + 0 + 12 + + + Zero + 0 bytes + 0x0000 + + + Min + 16 bytes + 0x0010 + + + Max + 4096 bytes + 0x1000 + + + + + + + COUNT + Counter current value + 0x404 + read-write + 0x00000000 + 0x20 + + + COUNT + Counter current value. Only writable when counter is in stopped state. Writing when not in stopped + state will generate a bus fault. + 0 + 12 + + + + + COUNTSNAPSHOT + Copy of the current COUNT value + 0x408 + read-only + 0x00000000 + 0x20 + + + COUNTSNAPSHOT + TASKS_FLUSH will copy the current COUNT value to this register. + 0 + 12 + + + + + + + GLOBAL_TBM_S + Trace buffer monitor 1 + 0xBF003000 + GLOBAL_TBM_NS + + + + TBM + 127 + + + + GLOBAL_USBHS_NS + USBHS 0 + 0x4F086000 + USBHS + + + + 0 + 0x1000 + registers + + + USBHS + 134 + + USBHS + 0x20 + + + TASKS_START + Start the USB peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the USB peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at USBHS core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable USB peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + CORE + Enable USB Controller + 0 + 0 + + + Disabled + USB Controller disabled. + 0x0 + + + Enabled + USB Controller enabled. + 0x1 + + + + + PHY + Enable USB PHY + 1 + 1 + + + Disabled + USB PHY disabled. + 0x0 + + + Enabled + USB PHY enabled. + 0x1 + + + + + + + + + GLOBAL_USBHS_S + USBHS 1 + 0x5F086000 + + + + USBHS + 134 + + + + GLOBAL_EXMIF_NS + External Memory Interface 0 + 0x4F095000 + EXMIF + + + + 0 + 0x1000 + registers + + + EXMIF + 149 + + EXMIF + 0x20 + + + TASKS_START + Start operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + LOCKEDACCESS + Enable or disable locked APB access to serial memory controller. + 0x14 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable locked APB access to SSI. + 0 + 0 + + + Disabled + Disable locked APB access. + 0x0 + + + Enabled + Enable locked APB access. + 0x1 + + + + + + + RESET + Reset the external memory. + 0x1C + read-write + 0x00000000 + 0x20 + + + RESET + 0 + 0 + + + Clear + Reset is cleared. + 0x0 + + + Set + Reset is set. + 0x1 + + + + + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at EXMIF core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the START task is completed and the EXMIF has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + EXTCONF1 + Configuration for external memory device 1. + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 1. + 0x0 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 1. + 0x4 + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x10 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + EXTCONF2 + Configuration for external memory device 2. + EXTCONF2 + EXTCONF1 + read-write + 0x400 + + OFFSET + Address offset for external memory device 2. + 0x8 + read-write + 0x00000000 + 0x20 + + + OFFSET + External memory Offset. + 0 + 31 + + + + + SIZE + Upper address range for external memory device 2. + 0xC + read-write + 0x0FFFFFFF + 0x20 + + + SIZE + Upper limit address. + 0 + 31 + + + + + ENABLE + Enable or disable external memory access. + 0x20 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable external memory access from AXI interface. + 0 + 0 + + + Disabled + Disable external memory. + 0x0 + + + Enabled + Enable external memory. + 0x1 + + + + + + + + CORE + Unspecified + GLOBAL_EXMIF_CORE + read-write + 0x500 + + SSICADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICADDRESS + read-write + 0x000 + + CTRLR0 + This register controls the serial data transfer. + 0x000 + read-write + 0x00004007 + 0x20 + + + DFS + Data Frame Size. + 0 + 4 + + + DFS_01_BIT + Unspecified + 0x00 + + + DFS_02_BIT + Unspecified + 0x01 + + + DFS_03_BIT + Unspecified + 0x02 + + + DFS_04_BIT + Unspecified + 0x03 + + + DFS_05_BIT + Unspecified + 0x04 + + + DFS_06_BIT + Unspecified + 0x05 + + + DFS_07_BIT + Unspecified + 0x06 + + + DFS_08_BIT + Unspecified + 0x07 + + + DFS_09_BIT + Unspecified + 0x08 + + + DFS_10_BIT + Unspecified + 0x09 + + + DFS_11_BIT + Unspecified + 0x0A + + + DFS_12_BIT + Unspecified + 0x0B + + + DFS_13_BIT + Unspecified + 0x0C + + + DFS_14_BIT + Unspecified + 0x0D + + + DFS_15_BIT + Unspecified + 0x0E + + + DFS_16_BIT + Unspecified + 0x0F + + + DFS_17_BIT + Unspecified + 0x10 + + + DFS_18_BIT + Unspecified + 0x11 + + + DFS_19_BIT + Unspecified + 0x12 + + + DFS_20_BIT + Unspecified + 0x13 + + + DFS_21_BIT + Unspecified + 0x14 + + + DFS_22_BIT + Unspecified + 0x15 + + + DFS_23_BIT + Unspecified + 0x16 + + + DFS_24_BIT + Unspecified + 0x17 + + + DFS_25_BIT + Unspecified + 0x18 + + + DFS_26_BIT + Unspecified + 0x19 + + + DFS_27_BIT + Unspecified + 0x1A + + + DFS_28_BIT + Unspecified + 0x1B + + + DFS_29_BIT + Unspecified + 0x1C + + + DFS_30_BIT + Unspecified + 0x1D + + + DFS_31_BIT + Unspecified + 0x1E + + + DFS_32_BIT + Unspecified + 0x1F + + + + + FRF + Frame Format. + 6 + 7 + + + SPI + Unspecified + 0x0 + + + SSP + Unspecified + 0x1 + + + MICROWIRE + Unspecified + 0x2 + + + + + SCPH + Serial Clock Phase. + 8 + 8 + + + MIDDLE_BIT + Unspecified + 0x0 + + + START_BIT + Unspecified + 0x1 + + + + + SCPOL + Serial Clock Polarity. + 9 + 9 + + + INACTIVE_HIGH + Unspecified + 0x0 + + + INACTIVE_LOW + Unspecified + 0x1 + + + + + TMOD + Transfer Mode. + 10 + 11 + + + TX_AND_RX + Unspecified + 0x0 + + + TX_ONLY + Unspecified + 0x1 + + + RX_ONLY + Unspecified + 0x2 + + + EEPROM_READ + Unspecified + 0x3 + + + + + SLVOE + Slave Output Enable. + 12 + 12 + + + ENABLED + Unspecified + 0x0 + + + DISABLED + Unspecified + 0x1 + + + + + SRL + Shift Register Loop. + 13 + 13 + + + NORMAL_MODE + Unspecified + 0x0 + + + TESTING_MODE + Unspecified + 0x1 + + + + + SSTE + Slave Select Toggle Enable. + 14 + 14 + + + TOGGLE_DISABLE + Unspecified + 0x0 + + + TOGGLE_EN + Unspecified + 0x1 + + + + + CFS + Control Frame Size. + 16 + 19 + + + SIZE_01_BIT + Unspecified + 0x0 + + + SIZE_02_BIT + Unspecified + 0x1 + + + SIZE_03_BIT + Unspecified + 0x2 + + + SIZE_04_BIT + Unspecified + 0x3 + + + SIZE_05_BIT + Unspecified + 0x4 + + + SIZE_06_BIT + Unspecified + 0x5 + + + SIZE_07_BIT + Unspecified + 0x6 + + + SIZE_08_BIT + Unspecified + 0x7 + + + SIZE_09_BIT + Unspecified + 0x8 + + + SIZE_10_BIT + Unspecified + 0x9 + + + SIZE_11_BIT + Unspecified + 0xA + + + SIZE_12_BIT + Unspecified + 0xB + + + SIZE_13_BIT + Unspecified + 0xC + + + SIZE_14_BIT + Unspecified + 0xD + + + SIZE_15_BIT + Unspecified + 0xE + + + SIZE_16_BIT + Unspecified + 0xF + + + + + SPIFRF + SPI Frame Format + 22 + 23 + + + SPI_STANDARD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + SPIHYPERBUSEN + SPI Hyperbus Frame format enable. + 24 + 24 + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SPIDWSEN + Enable Dynamic wait states in SPI mode of operation. + 25 + 25 + read-only + + + DISABLE + Unspecified + 0x0 + + + ENABLE + Unspecified + 0x1 + + + + + SSIISMST + This field selects if DWC_ssi is working in Master or Slave mode + 31 + 31 + read-only + + + SLAVE + Unspecified + 0x0 + + + MASTER + Unspecified + 0x1 + + + + + + + CTRLR1 + This register exists only when the DWC_ssi is configured as a master device. + 0x004 + read-write + 0x00000000 + 0x20 + + + NDF + Number of Data Frames. + 0 + 15 + + + + + SSIENR + This register enables and disables the DWC_ssi. + 0x008 + read-write + 0x00000000 + 0x20 + + + SSICEN + SSI Enable. + 0 + 0 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + MWCR + This register controls the direction of the data word for the half-duplex Microwire serial protocol. + 0x00C + read-write + 0x00000000 + 0x20 + + + MWMOD + Microwire Transfer Mode. + 0 + 0 + + + NON_SEQUENTIAL + Unspecified + 0x0 + + + SEQUENTIAL + Unspecified + 0x1 + + + + + MDD + Microwire Control. + 1 + 1 + + + RECEIVE + Unspecified + 0x0 + + + TRANSMIT + Unspecified + 0x1 + + + + + MHS + Microwire Handshaking. + 2 + 2 + + + DISABLE + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SER + This register is valid only when the DWC_ssi is configured as a master device. + 0x010 + read-write + 0x00000000 + 0x20 + + + SER + Slave Select Enable Flag. + 0 + 1 + + + NOTSELECTED + Unspecified + 0x0 + + + SELECTED + Unspecified + 0x1 + + + + + + + BAUDR + This register is valid only when the DWC_ssi is configured as a master device. + 0x014 + read-write + 0x00000000 + 0x20 + + + SCKDV + SSI Clock Divider. + 1 + 15 + + + + + TXFTLR + This register controls the threshold value for the transmit FIFO memory.. + 0x018 + read-write + 0x00000000 + 0x20 + + + TFT + Transmit FIFO Threshold. + 0 + 4 + + + TXFTHR + Transfer start FIFO level. + 16 + 20 + + + + + RXFTLR + This register controls the threshold value for the receive FIFO memory.. + 0x01C + read-write + 0x00000000 + 0x20 + + + RFT + Receive FIFO Threshold. + 0 + 4 + + + + + TXFLR + This register contains the number of valid data entries in the transmit FIFO memory. + 0x020 + read-write + 0x00000000 + 0x20 + + + TXTFL + Transmit FIFO Level. + 0 + 5 + read-only + + + + + RXFLR + This register contains the number of valid data entries in the receive FIFO memory. + 0x024 + read-write + 0x00000000 + 0x20 + + + RXTFL + Receive FIFO Level. + 0 + 5 + read-only + + + + + SR + This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. + 0x028 + read-write + 0x00000006 + 0x20 + + + BUSY + SSI Busy Flag. + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TFNF + Transmit FIFO Not Full. + 1 + 1 + read-only + + + FULL + Unspecified + 0x0 + + + NOT_FULL + Unspecified + 0x1 + + + + + TFE + Transmit FIFO Empty. + 2 + 2 + read-only + + + NOT_EMPTY + Unspecified + 0x0 + + + EMPTY + Unspecified + 0x1 + + + + + RFNE + Receive FIFO Not Empty. + 3 + 3 + read-only + + + EMPTY + Unspecified + 0x0 + + + NOT_EMPTY + Unspecified + 0x1 + + + + + RFF + Receive FIFO Full. + 4 + 4 + read-only + + + NOT_FULL + Unspecified + 0x0 + + + FULL + Unspecified + 0x1 + + + + + TXE + Transmission Error. + 5 + 5 + read-only + + + NO_ERROR + Unspecified + 0x0 + + + TX_ERROR + Unspecified + 0x1 + + + + + DCOL + Data Collision Error. + 6 + 6 + read-only + + + NO_ERROR_CONDITION + Unspecified + 0x0 + + + TX_COLLISION_ERROR + Unspecified + 0x1 + + + + + + + IMR + This read/write register masks or enables all interrupts generated by the DWC_ssi. + 0x02C + read-write + 0x000000FF + 0x20 + + + TXEIM + Transmit FIFO Empty Interrupt Mask + 0 + 0 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXOIM + Transmit FIFO Overflow Interrupt Mask + 1 + 1 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXUIM + Receive FIFO Underflow Interrupt Mask + 2 + 2 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXOIM + Receive FIFO Overflow Interrupt Mask + 3 + 3 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + RXFIM + Receive FIFO Full Interrupt Mask + 4 + 4 + + + MASKED + ssi_rxf_intr interrupt is masked + 0x0 + + + UNMASKED + ssi_rxf_intr interrupt is not masked + 0x1 + + + + + MSTIM + Multi-Master Contention Interrupt Mask. + 5 + 5 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + XRXOIM + XIP Receive FIFO Overflow Interrupt Mask + 6 + 6 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + TXUIM + Transmit FIFO Underflow Interrupt Mask + 7 + 7 + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + DONEM + SSI Done Interrupt Mask + 11 + 11 + read-only + + + MASKED + Unspecified + 0x0 + + + UNMASKED + Unspecified + 0x1 + + + + + + + ISR + This register reports the status of the DWC_ssi interrupts after they have been masked. + 0x030 + read-write + 0x00000000 + 0x20 + + + TXEIS + Transmit FIFO Empty Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIS + Transmit FIFO Overflow Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIS + Receive FIFO Underflow Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIS + Receive FIFO Overflow Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIS + Receive FIFO Full Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIS + Multi-Master Contention Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIS + XIP Receive FIFO Overflow Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIS + Transmit FIFO Underflow Interrupt Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONES + SSI Done Interrupt Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + RISR + Raw Interrupt Status Register + 0x034 + read-write + 0x00000000 + 0x20 + + + TXEIR + Transmit FIFO Empty Raw Interrupt Status + 0 + 0 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXOIR + Transmit FIFO Overflow Raw Interrupt Status + 1 + 1 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXUIR + Receive FIFO Underflow Raw Interrupt Status + 2 + 2 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXOIR + Receive FIFO Overflow Raw Interrupt Status + 3 + 3 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + RXFIR + Receive FIFO Full Raw Interrupt Status + 4 + 4 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + MSTIR + Multi-Master Contention Raw Interrupt Status. + 5 + 5 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + XRXOIR + XIP Receive FIFO Overflow Raw Interrupt Status + 6 + 6 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + TXUIR + Transmit FIFO Underflow Interrupt Raw Status + 7 + 7 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + DONER + SSI Done Interrupt Raw Status + 11 + 11 + read-only + + + INACTIVE + Unspecified + 0x0 + + + ACTIVE + Unspecified + 0x1 + + + + + + + TXEICR + Transmit FIFO Error Interrupt Clear Register + 0x038 + read-write + 0x00000000 + 0x20 + + + TXEICR + Clear Transmit FIFO Overflow/Underflow Interrupt. + 0 + 0 + read-only + + + + + RXOICR + Receive FIFO Overflow Interrupt Clear Register + 0x03C + read-write + 0x00000000 + 0x20 + + + RXOICR + Clear Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + RXUICR + Receive FIFO Underflow Interrupt Clear Register + 0x040 + read-write + 0x00000000 + 0x20 + + + RXUICR + Clear Receive FIFO Underflow Interrupt. + 0 + 0 + read-only + + + + + MSTICR + Multi-Master Interrupt Clear Register + 0x044 + read-write + 0x00000000 + 0x20 + + + MSTICR + Clear Multi-Master Contention Interrupt. + 0 + 0 + read-only + + + + + ICR + Interrupt Clear Register + 0x048 + read-write + 0x00000000 + 0x20 + + + ICR + Clear Interrupts. + 0 + 0 + read-only + + + + + IDR + This register contains the peripherals identification code, which is written into the register at configuration time using coreConsultant. + 0x058 + read-write + 0x00010003 + 0x20 + + + IDCODE + Identification code. + 0 + 31 + read-only + + + + + SSICVERSIONID + This read-only register stores the specific DWC_ssi component version. + 0x05C + read-write + 0x3130332A + 0x20 + + + SSICCOMPVERSION + Contains the hex representation of the Synopsys component version. + 0 + 31 + read-only + + + + + 0x24 + 0x4 + DR[%s] + Description collection: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. + 0x060 + read-write + 0x00000000 + 0x20 + + + DR + Data Register. + 0 + 31 + + + + + RXSAMPLEDELAY + This register is only valid when the DWC_ssi is configured with rxd sample delay logic (SSIC_HAS_RX_SAMPLE_DELAY==1). + 0x0F0 + read-write + 0x00000000 + 0x20 + + + RSD + Receive Data (rxd) Sample Delay. + 0 + 7 + + + SE + Receive Data (rxd) Sampling Edge. + 16 + 16 + + + + + SPICTRLR0 + This register is used to control the serial data transfer in enhanced SPI mode of operation. + 0x0F4 + read-write + 0x00000A00 + 0x20 + + + TRANSTYPE + Address and instruction transfer format. + 0 + 1 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 2 + 5 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + XIPMDBITEN + Mode bits enable in XIP mode. + 7 + 7 + read-only + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 11 + 15 + + + SPIDDREN + SPI DDR Enable bit. + 16 + 16 + + + INSTDDREN + Instruction DDR Enable bit. + 17 + 17 + + + SPIRXDSEN + Read data strobe enable bit. + 18 + 18 + + + XIPDFSHC + Fix DFS for XIP transfers. + 19 + 19 + read-only + + + XIPINSTEN + XIP instruction enable bit. + 20 + 20 + read-only + + + SSICXIPCONTXFEREN + Enable continuous transfer in XIP mode. + 21 + 21 + read-only + + + SPIDMEN + SPI data mask enable bit. + 24 + 24 + + + SPIRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + read-only + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + read-only + + + CLKSTRETCHEN + Enables clock stretching capability in SPI transfers. + 30 + 30 + + + + + DDRDRIVEEDGE + This Register is valid only when SSIC_HAS_DDR is equal to 1. + 0x0F8 + read-write + 0x00000000 + 0x20 + + + TDE + TXD Drive edge register which decided the driving edge of transmit data. + 0 + 7 + + + + + XIPMODEBITS + This register carries the mode bits which are sent in the XIP mode of operation after address phase. + 0x0FC + read-write + 0x00000000 + 0x20 + + + XIPMDBITS + XIP mode bits to be sent after address phase of XIP transfer. + 0 + 15 + + + + + + SSICXIPADDRESS + Unspecified + GLOBAL_EXMIF_CORE_SSICXIPADDRESS + read-write + 0x100 + + XIPINCRINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x000 + read-write + 0x00000000 + 0x20 + + + INCRINST + XIP INCR transfer opcode. + 0 + 15 + + + + + XIPWRAPINST + This Register is valid only when SSIC_XIP_EN is equal to 1. + 0x004 + read-write + 0x00000000 + 0x20 + + + WRAPINST + XIP WRAP transfer opcode. + 0 + 15 + + + + + XIPCTRL + This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. + 0x008 + read-write + 0x08000401 + 0x20 + + + FRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + TRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + ADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + ADDR_L36 + Unspecified + 0x9 + + + ADDR_L40 + Unspecified + 0xA + + + ADDR_L44 + Unspecified + 0xB + + + ADDR_L48 + Unspecified + 0xC + + + ADDR_L52 + Unspecified + 0xD + + + ADDR_L56 + Unspecified + 0xE + + + ADDR_L60 + Unspecified + 0xF + + + + + INSTL + Dual/Quad/Octal mode instruction length in bits. + 9 + 10 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + MDBITSEN + Mode bits enable in XIP mode. + 12 + 12 + + + WAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 13 + 17 + + + DFSHC + Fix DFS for XIP transfers. + 18 + 18 + + + DDREN + SPI DDR Enable bit. + 19 + 19 + + + INSTDDREN + Instruction DDR Enable bit. + 20 + 20 + + + RXDSEN + Read data strobe enable bit. + 21 + 21 + + + INSTEN + XIP instruction enable bit. + 22 + 22 + + + CONTXFEREN + Enable continuous transfer in XIP mode. + 23 + 23 + read-only + + + XIPHYPERBUSEN + SPI Hyperbus Frame format enable for XIP transfers. + 24 + 24 + + + RXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 25 + 25 + + + XIPMBL + XIP Mode bits length. + 26 + 27 + + + MBL_2 + Unspecified + 0x0 + + + MBL_4 + Unspecified + 0x1 + + + MBL_8 + Unspecified + 0x2 + + + MBL_16 + Unspecified + 0x3 + + + + + XIPPREFETCHEN + Enables XIP pre-fetch functionality in DWC_ssi. + 29 + 29 + + + + + XRXOICR + XIP Receive FIFO Overflow Interrupt Clear Register + 0x010 + read-write + 0x00000000 + 0x20 + + + XRXOICR + Clear XIP Receive FIFO Overflow Interrupt. + 0 + 0 + read-only + + + + + XIPWRITEINCRINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x040 + read-write + 0x00000000 + 0x20 + + + INCRWRITEINST + XIP Write INCR transfer opcode. + 0 + 15 + + + RSVDINCRINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITEWRAPINST + This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. + 0x044 + read-write + 0x00000000 + 0x20 + + + WRAPWRITEINST + XIP Write WRAP transfer opcode. + 0 + 15 + + + RSVDWRAPINST16TO31 + Reserved bits - Read Only + 16 + 31 + read-only + + + + + XIPWRITECTRL + This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. + 0x048 + read-write + 0x00000002 + 0x20 + + + WRFRF + SPI Frame Format + 0 + 1 + + + RSVD + Unspecified + 0x0 + + + SPI_DUAL + Unspecified + 0x1 + + + SPI_QUAD + Unspecified + 0x2 + + + SPI_OCTAL + Unspecified + 0x3 + + + + + WRTRANSTYPE + Address and instruction transfer format. + 2 + 3 + + + TT0 + Unspecified + 0x0 + + + TT1 + Unspecified + 0x1 + + + TT2 + Unspecified + 0x2 + + + TT3 + Unspecified + 0x3 + + + + + WRADDRL + This bit defines Length of Address to be transmitted. + 4 + 7 + + + ADDR_L0 + Unspecified + 0x0 + + + ADDR_L4 + Unspecified + 0x1 + + + ADDR_L8 + Unspecified + 0x2 + + + ADDR_L12 + Unspecified + 0x3 + + + ADDR_L16 + Unspecified + 0x4 + + + ADDR_L20 + Unspecified + 0x5 + + + ADDR_L24 + Unspecified + 0x6 + + + ADDR_L28 + Unspecified + 0x7 + + + ADDR_L32 + Unspecified + 0x8 + + + + + WRINSTL + Dual/Quad/Octal mode instruction length in bits. + 8 + 9 + + + INST_L0 + Unspecified + 0x0 + + + INST_L4 + Unspecified + 0x1 + + + INST_L8 + Unspecified + 0x2 + + + INST_L16 + Unspecified + 0x3 + + + + + WRSPIDDREN + SPI DDR Enable bit. + 10 + 10 + + + WRINSTDDREN + Instruction DDR Enable bit. + 11 + 11 + + + XIPWRHYPERBUSEN + SPI Hyperbus Frame format enable for XIP Write transfers. + 12 + 12 + + + XIPWRRXDSSIGEN + Enable rxds signaling during address and command phase of Hyperbus transfer. + 13 + 13 + + + RSVDXIPWRITECTRL14TO15 + Reserved bits - Read Only + 14 + 15 + read-only + + + XIPWRWAITCYCLES + Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. + 16 + 20 + + + RSVDXIPWRITECTRL21TO31 + Reserved bits - Read Only + 21 + 31 + read-only + + + + + + + + + GLOBAL_EXMIF_S + External Memory Interface 1 + 0x5F095000 + + + + EXMIF + 149 + + + + GLOBAL_SECDOMBELLBOARD_NS + BELLBOARD public registers 0 + 0x4F099000 + BELLBOARDPUBLIC + + + + + 0 + 0x1000 + registers + + BELLBOARDPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Task TRIGGER[n] + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + Task TRIGGER[n] + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_SECDOMBELLBOARD_S + BELLBOARD public registers 1 + 0x5F099000 + + + + + + GLOBAL_VPR120_NS + VPR peripheral registers 0 + 0x4F8C8000 + VPRPUBLIC + + + + 0 + 0x1000 + registers + + VPRPUBLIC + 0x20 + + + 0x20 + 0x4 + TASKS_TRIGGER[%s] + Description collection: VPR task [n] register + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGGER + VPR task [n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + GLOBAL_VPR120_S + VPR peripheral registers 1 + 0x5F8C8000 + + + + + GLOBAL_IPCT120_NS + IPCT APB registers 0 + 0x4F8D1000 + IPCT + + + + + 0 + 0x1000 + registers + + + IPCT120_0 + 209 + + IPCT + 0x20 + + + 0x8 + 0x4 + TASKS_SEND[%s] + Description collection: Trigger event on IPCT source channel n if there are no active signals present on that channel + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_SEND + Trigger event on IPCT source channel n if there are no active signals present on that channel + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_FLUSH[%s] + Description collection: Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSH + Flush IPCT sink channel n. Any pending IPCT signal on that channel will + re-trigger the RECEIVE[n] event. The flush can happen automatically by + configuring the SHORTS register accordingly. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_SEND[%s] + Description collection: Subscribe configuration for task SEND[n] + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SEND[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_FLUSH[%s] + Description collection: Subscribe configuration for task FLUSH[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_RECEIVE[%s] + Description collection: Event received on IPCT sink channel n + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_RECEIVE + Event received on IPCT sink channel n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_READY[%s] + Description collection: Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + Event received when hardware handshake of SEND task for IPCT + source channel n is complete and a new signal can be triggered + on that channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_RECEIVE[%s] + Description collection: Publish configuration for event RECEIVE[n] + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RECEIVE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_READY[%s] + Description collection: Publish configuration for event READY[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + RECEIVE0_FLUSH0 + Shortcut between event RECEIVE[0] and task FLUSH[0] + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE1_FLUSH1 + Shortcut between event RECEIVE[1] and task FLUSH[1] + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE2_FLUSH2 + Shortcut between event RECEIVE[2] and task FLUSH[2] + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE3_FLUSH3 + Shortcut between event RECEIVE[3] and task FLUSH[3] + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE4_FLUSH4 + Shortcut between event RECEIVE[4] and task FLUSH[4] + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE5_FLUSH5 + Shortcut between event RECEIVE[5] and task FLUSH[5] + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE6_FLUSH6 + Shortcut between event RECEIVE[6] and task FLUSH[6] + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RECEIVE7_FLUSH7 + Shortcut between event RECEIVE[7] and task FLUSH[7] + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Enable or disable interrupt for event RECEIVE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE1 + Enable or disable interrupt for event RECEIVE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE2 + Enable or disable interrupt for event RECEIVE[2] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE3 + Enable or disable interrupt for event RECEIVE[3] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE4 + Enable or disable interrupt for event RECEIVE[4] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE5 + Enable or disable interrupt for event RECEIVE[5] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE6 + Enable or disable interrupt for event RECEIVE[6] + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RECEIVE7 + Enable or disable interrupt for event RECEIVE[7] + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY0 + Enable or disable interrupt for event READY[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY1 + Enable or disable interrupt for event READY[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY2 + Enable or disable interrupt for event READY[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY3 + Enable or disable interrupt for event READY[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY4 + Enable or disable interrupt for event READY[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY5 + Enable or disable interrupt for event READY[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY6 + Enable or disable interrupt for event READY[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READY7 + Enable or disable interrupt for event READY[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to enable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE1 + Write '1' to enable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE2 + Write '1' to enable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE3 + Write '1' to enable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE4 + Write '1' to enable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE5 + Write '1' to enable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE6 + Write '1' to enable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RECEIVE7 + Write '1' to enable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY0 + Write '1' to enable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY1 + Write '1' to enable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY2 + Write '1' to enable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY3 + Write '1' to enable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY4 + Write '1' to enable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY5 + Write '1' to enable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY6 + Write '1' to enable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READY7 + Write '1' to enable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RECEIVE0 + Write '1' to disable interrupt for event RECEIVE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE1 + Write '1' to disable interrupt for event RECEIVE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE2 + Write '1' to disable interrupt for event RECEIVE[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE3 + Write '1' to disable interrupt for event RECEIVE[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE4 + Write '1' to disable interrupt for event RECEIVE[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE5 + Write '1' to disable interrupt for event RECEIVE[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE6 + Write '1' to disable interrupt for event RECEIVE[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RECEIVE7 + Write '1' to disable interrupt for event RECEIVE[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY0 + Write '1' to disable interrupt for event READY[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY1 + Write '1' to disable interrupt for event READY[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY2 + Write '1' to disable interrupt for event READY[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY3 + Write '1' to disable interrupt for event READY[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY4 + Write '1' to disable interrupt for event READY[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY5 + Write '1' to disable interrupt for event READY[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY6 + Write '1' to disable interrupt for event READY[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READY7 + Write '1' to disable interrupt for event READY[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + RECEIVE0 + Read pending status of interrupt for event RECEIVE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE1 + Read pending status of interrupt for event RECEIVE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE2 + Read pending status of interrupt for event RECEIVE[2] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE3 + Read pending status of interrupt for event RECEIVE[3] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE4 + Read pending status of interrupt for event RECEIVE[4] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE5 + Read pending status of interrupt for event RECEIVE[5] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE6 + Read pending status of interrupt for event RECEIVE[6] + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RECEIVE7 + Read pending status of interrupt for event RECEIVE[7] + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY0 + Read pending status of interrupt for event READY[0] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY1 + Read pending status of interrupt for event READY[1] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY2 + Read pending status of interrupt for event READY[2] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY3 + Read pending status of interrupt for event READY[3] + 19 + 19 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY4 + Read pending status of interrupt for event READY[4] + 20 + 20 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY5 + Read pending status of interrupt for event READY[5] + 21 + 21 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY6 + Read pending status of interrupt for event READY[6] + 22 + 22 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READY7 + Read pending status of interrupt for event READY[7] + 23 + 23 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + OVERFLOW + Unspecified + GLOBAL_IPCT_OVERFLOW + read-write + 0x400 + + SEND + Overflow status for SEND tasks Write 0 to clear + 0x000 + read-write + 0x00000000 + 0x20 + + + SEND_0 + Overflow status for SEND[0] task + 0 + 0 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_1 + Overflow status for SEND[1] task + 1 + 1 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_2 + Overflow status for SEND[2] task + 2 + 2 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_3 + Overflow status for SEND[3] task + 3 + 3 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_4 + Overflow status for SEND[4] task + 4 + 4 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_5 + Overflow status for SEND[5] task + 5 + 5 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_6 + Overflow status for SEND[6] task + 6 + 6 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + SEND_7 + Overflow status for SEND[7] task + 7 + 7 + + + Overflow + Task overflow has happened + 0x1 + + + NoOverflow + Task overflow has not happened + 0x0 + + + + + + + + + + GLOBAL_IPCT120_S + IPCT APB registers 1 + 0x5F8D1000 + + + + + IPCT120_0 + 209 + + + + GLOBAL_MUTEX120_NS + MUTEX 0 + 0x4F8D2000 + MUTEX + + + + 0 + 0x1000 + registers + + MUTEX + 0x20 + + + 0x20 + 0x4 + MUTEX[%s] + Description collection: Mutex register + 0x400 + read-write + 0x00000000 + 0x20 + + + MUTEX + Mutex register n + 0 + 0 + + + Unlocked + Mutex n is in unlocked state + 0x0 + + + Locked + Mutex n is in locked state + 0x1 + + + + + + + + + GLOBAL_I3C120_NS + I3C 0 + 0x4F8D3000 + I3C + + + + 0 + 0x1000 + registers + + + I3C120 + 211 + + I3C + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt triggered at I3C core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at I3C DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE + Enable or disable interrupt for event CORE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to enable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE + Write '1' to disable interrupt for event CORE + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE + Read pending status of interrupt for event CORE + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + Enable I3C peripheral. + 0x400 + read-write + 0x00000000 + 0x20 + + + EN + Enable + 0 + 0 + + + Disabled + I3C peripheral disabled. + 0x0 + + + Enabled + I3C peripheral enabled. + 0x1 + + + + + + + CDR + Unspecified + I3C_CDR + read-write + 0x404 + + STARTOFFSET + Start offset of recovered clock + 0x000 + read-write + 0x00000004 + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXCYCLERATIO + Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock + 0x004 + read-write + 0x0000001C + 0x20 + + + VAL + Value + 0 + 15 + + + + + MAXSKEW + Maximum skew between SCL and SCL in CDR clock cycles + 0x008 + read-write + 0x00000005 + 0x20 + + + VAL + Value + 0 + 7 + + + + + + SLAVEIF0 + I3C slave interface 0 + 0x410 + read-write + 0x00000000 + 0x20 + + + MODEI2C + I2C or I3C mode select signal + 0 + 0 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + ACTMODE + Slave activity mode for GETSTATUS CCC + 1 + 2 + + + PENDINGINT + Pending interrupt information for GETSTATUS CCC + 3 + 6 + + + STATICADDREN + Slave static address valid + 7 + 7 + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + STATICADDR + Slave static address + 8 + 14 + + + SLAVEMAXRDSPEED + Slave maximum read data rate + 15 + 17 + + + SLAVEMAXWRSPEED + Slave maximum write write rate + 18 + 20 + + + SLAVECLKDATATURNTIME + Slave maximum clock data turnaround time + 21 + 23 + + + SLAVEDCR + Device Characteristic Register value + 24 + 31 + + + + + SLAVEIF1 + I3C slave interface 1 + 0x414 + read-write + 0x00000000 + 0x20 + + + WAKEUP + Slave wakeup signal + 0 + 0 + read-only + + + DISABLED + Unspecified + 0x0 + + + ENABLED + Unspecified + 0x1 + + + + + + + SLAVEPID0 + Slave Device Provisioned ID 0 + 0x418 + read-write + 0x00000000 + 0x20 + + + ADDMEANING + Additional Meaning + 0 + 11 + + + INSTANCEID + Instance ID + 12 + 15 + + + PARTID + Part ID + 16 + 31 + + + + + SLAVEPID1 + Slave Device Provisioned ID 1 + 0x41C + read-write + 0x00000000 + 0x20 + + + PROVID + Provisional ID Type Selector + 0 + 0 + + + MIPIMID + MIPI Manufacturer ID + 1 + 15 + + + + + KEEPSDA + Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x420 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SDA high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + KEEPSCL + Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. + 0x424 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the SCL high-keeper + 0 + 0 + + + Disabled + High-keeper disabled. + 0x0 + + + Enabled + High-keeper enabled. + 0x1 + + + + + + + + + GLOBAL_I3C120_S + I3C 1 + 0x5F8D3000 + + + + I3C120 + 211 + + + + GLOBAL_VPR121_NS + VPR peripheral registers 2 + 0x4F8D4000 + + + + VPR121 + 212 + + + + GLOBAL_VPR121_S + VPR peripheral registers 3 + 0x5F8D4000 + + + + VPR121 + 212 + + + + GLOBAL_CAN120_NS + Controller Area Network 0 + 0x4F8D8000 + CAN + + + + 0 + 0x1000 + registers + + + CAN120 + 216 + + CAN + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the CAN peripheral. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOPREQ + Request to stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the CAN peripheral + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the CAN peripheral + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_CORE[%s] + Description collection: Event indicating that interrupt n triggered at CAN core + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CORE + Event indicating that interrupt n triggered at CAN core + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DMU + Event indicating that interrupt triggered at CAN DMU + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DMA + Event indicating that interrupt triggered at CAN DMA + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_READYFORSTOP + Event indicating that the CAN is ready to be stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READYFORSTOP_STOP + Shortcut between event READYFORSTOP and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CORE0 + Enable or disable interrupt for event CORE[0] + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CORE1 + Enable or disable interrupt for event CORE[1] + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMU + Enable or disable interrupt for event DMU + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMA + Enable or disable interrupt for event DMA + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READYFORSTOP + Enable or disable interrupt for event READYFORSTOP + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to enable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CORE1 + Write '1' to enable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMU + Write '1' to enable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMA + Write '1' to enable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READYFORSTOP + Write '1' to enable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CORE0 + Write '1' to disable interrupt for event CORE[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CORE1 + Write '1' to disable interrupt for event CORE[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMU + Write '1' to disable interrupt for event DMU + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMA + Write '1' to disable interrupt for event DMA + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READYFORSTOP + Write '1' to disable interrupt for event READYFORSTOP + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + CORE0 + Read pending status of interrupt for event CORE[0] + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CORE1 + Read pending status of interrupt for event CORE[1] + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMU + Read pending status of interrupt for event DMU + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMA + Read pending status of interrupt for event DMA + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + READYFORSTOP + Read pending status of interrupt for event READYFORSTOP + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + + + GLOBAL_CAN120_S + Controller Area Network 1 + 0x5F8D8000 + + + + CAN120 + 216 + + + + GLOBAL_MVDMA120_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 0 + 0x4F8D9000 + MVDMA + + + + 0 + 0x1000 + registers + + + MVDMA120 + 217 + + MVDMA + 0x20 + + + TASKS_PAUSE + Pause operation. + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_PAUSE + Pause operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESET + Reset operation. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_RESET + Reset operation. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_START[%s] + Description collection: Start operation of job list n. Base address for successive TASKS_STARTs. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start operation of job list n. Base address for successive TASKS_STARTs. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_START[%s] + Description collection: Subscribe configuration for task START[n] + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Event indicating that Sink data descriptor list has been completed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + Event indicating that the source list processing has started. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_PAUSED + Event indicating that the data transfer has been paused. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESET + Event indicating that the peripheral has been reset. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SOURCE + Peripheral events. + GLOBAL_MVDMA_EVENTS_SOURCE + read-write + 0x110 + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Source channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + EVENTS_SINK + Peripheral events. + GLOBAL_MVDMA_EVENTS_SINK + read-write + 0x118 + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0x000 + read-write + 0x00000000 + 0x20 + + + BUSERROR + Event indicating that a bus error has been received on the Sink channel. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0x004 + read-write + 0x00000000 + 0x20 + + + SELECTJOBDONE + Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + 0x8 + 0x4 + EVENTS_COMPLETED[%s] + Description collection: Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPLETED + Event indicating that the operation started by the task START[n] has been completed. Base address for successive EVENTS_COMPLETED. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SOURCE + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SOURCE + read-write + 0x190 + + SELECTJOBDONE + Publish configuration for event SOURCE.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SOURCE.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + PUBLISH_SINK + Publish configuration for events + GLOBAL_MVDMA_PUBLISH_SINK + read-write + 0x198 + + SELECTJOBDONE + Publish configuration for event SINK.SELECTJOBDONE + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SINK.SELECTJOBDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + 0x8 + 0x4 + PUBLISH_COMPLETED[%s] + Description collection: Publish configuration for event COMPLETED[n] + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPLETED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + END + Enable or disable interrupt for event END + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PAUSED + Enable or disable interrupt for event PAUSED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESET + Enable or disable interrupt for event RESET + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCEBUSERROR + Enable or disable interrupt for event SOURCEBUSERROR + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Enable or disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKBUSERROR + Enable or disable interrupt for event SINKBUSERROR + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Enable or disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED0 + Enable or disable interrupt for event COMPLETED[0] + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED1 + Enable or disable interrupt for event COMPLETED[1] + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED2 + Enable or disable interrupt for event COMPLETED[2] + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED3 + Enable or disable interrupt for event COMPLETED[3] + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED4 + Enable or disable interrupt for event COMPLETED[4] + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED5 + Enable or disable interrupt for event COMPLETED[5] + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED6 + Enable or disable interrupt for event COMPLETED[6] + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPLETED7 + Enable or disable interrupt for event COMPLETED[7] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PAUSED + Write '1' to enable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESET + Write '1' to enable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to enable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to enable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKBUSERROR + Write '1' to enable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to enable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED0 + Write '1' to enable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED1 + Write '1' to enable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED2 + Write '1' to enable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED3 + Write '1' to enable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED4 + Write '1' to enable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED5 + Write '1' to enable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED6 + Write '1' to enable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPLETED7 + Write '1' to enable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PAUSED + Write '1' to disable interrupt for event PAUSED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESET + Write '1' to disable interrupt for event RESET + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCEBUSERROR + Write '1' to disable interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SOURCESELECTJOBDONE + Write '1' to disable interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKBUSERROR + Write '1' to disable interrupt for event SINKBUSERROR + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SINKSELECTJOBDONE + Write '1' to disable interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED0 + Write '1' to disable interrupt for event COMPLETED[0] + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED1 + Write '1' to disable interrupt for event COMPLETED[1] + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED2 + Write '1' to disable interrupt for event COMPLETED[2] + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED3 + Write '1' to disable interrupt for event COMPLETED[3] + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED4 + Write '1' to disable interrupt for event COMPLETED[4] + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED5 + Write '1' to disable interrupt for event COMPLETED[5] + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED6 + Write '1' to disable interrupt for event COMPLETED[6] + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPLETED7 + Write '1' to disable interrupt for event COMPLETED[7] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + END + Read pending status of interrupt for event END + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STARTED + Read pending status of interrupt for event STARTED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PAUSED + Read pending status of interrupt for event PAUSED + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RESET + Read pending status of interrupt for event RESET + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCEBUSERROR + Read pending status of interrupt for event SOURCEBUSERROR + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SOURCESELECTJOBDONE + Read pending status of interrupt for event SOURCESELECTJOBDONE + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKBUSERROR + Read pending status of interrupt for event SINKBUSERROR + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SINKSELECTJOBDONE + Read pending status of interrupt for event SINKSELECTJOBDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED0 + Read pending status of interrupt for event COMPLETED[0] + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED1 + Read pending status of interrupt for event COMPLETED[1] + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED2 + Read pending status of interrupt for event COMPLETED[2] + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED3 + Read pending status of interrupt for event COMPLETED[3] + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED4 + Read pending status of interrupt for event COMPLETED[4] + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED5 + Read pending status of interrupt for event COMPLETED[5] + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED6 + Read pending status of interrupt for event COMPLETED[6] + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPLETED7 + Read pending status of interrupt for event COMPLETED[7] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + STATUS + MVDMA status registers. + GLOBAL_MVDMA_STATUS + read-write + 0x400 + + CRCRESULT + CRC checksum calculation result + 0x000 + read-only + 0x00000000 + 0x20 + + + CRC + Result + 0 + 31 + + + + + FIFO + Status of intermediate fifo: empty, not empty and full information available. + 0x004 + read-only + 0x00000000 + 0x20 + + + FIFOSTATUS + Result + 0 + 1 + + + Empty + Fifo is empty. + 0x0 + + + NotEmpty + Fifo contains data. + 0x1 + + + Full + Fifo is full. + 0x2 + + + + + + + ACTIVE + Status of DMA transfer. + 0x008 + read-only + 0x00000000 + 0x20 + + + ACTIVE + DMA activity + 0 + 0 + + + Idle + DMA is in IDLE state. + 0x0 + + + Active + Data being transferred. + 0x1 + + + + + + + + CONFIG + MVDMA configuration registers. + GLOBAL_MVDMA_CONFIG + read-write + 0x500 + + MODE + Configure MVDMA mode of operation. + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + 0 + 0 + + + SingleMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a single job list. + 0x0 + + + MultiMode + Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a list of job list pointers in memory. + 0x1 + + + + + + + + SOURCE + Source channel configuration and status. + GLOBAL_MVDMA_SOURCE + read-write + 0x600 + + LISTPTR + Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Source job descriptor list address. + 0 + 31 + + + + + BUSERROR + Source bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 1 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist, or error related to memory/register when reading data. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist, or error related to address when reading memory/register. + 0x2 + + + + + + + ADDRESS + Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Source address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Source job count + 0 + 31 + + + + + + SINK + Sink channel configuration and status. + GLOBAL_MVDMA_SINK + read-write + 0x620 + + LISTPTR + Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. + 0x000 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Sink descriptor list address. + 0 + 31 + + + + + BUSERROR + Sink bus error status. + 0x004 + read-only + 0x00000000 + 0x20 + + + BUSERROR + Bus error type + 0 + 2 + + + NoError + There are no errors. + 0x0 + + + ReadError + Error related to memory when reading joblist. + 0x1 + + + ReadDecodeError + Error related to the joblist address when reading joblist. + 0x2 + + + WriteError + Error related to memory/register when writing data. + 0x3 + + + WriteDecodeError + Error related to the memory/register address when writing data. + 0x4 + + + + + + + ADDRESS + Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain the address that cause the error. + 0x008 + read-only + 0x00000000 + 0x20 + + + ADDRESS + Sink address + 0 + 31 + + + + + JOBCOUNT + Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is started. + 0x00C + read-only + 0x00000000 + 0x20 + + + COUNT + Sink job count + 0 + 31 + + + + + + + + GLOBAL_MVDMA120_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 1 + 0x5F8D9000 + + + + MVDMA120 + 217 + + + + GLOBAL_RAMC122_NS + RAM Controller 0 + 0x4F8DA000 + RAMC + + + + 0 + 0x1000 + registers + + RAMC + 0x20 + + + WAITSTATES + Waitstates for read operations. + 0x500 + read-write + 0x00000000 + 0x20 + + + WAITSTATES + Number of waitstates for a read from the RAM. + 0 + 0 + + + + + + + GLOBAL_RAMC122_S + RAM Controller 1 + 0x5F8DA000 + + + + + GLOBAL_CAN121_NS + Controller Area Network 2 + 0x4F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_CAN121_S + Controller Area Network 3 + 0x5F8DB000 + + + + CAN121 + 219 + + + + GLOBAL_MVDMA121_NS + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 2 + 0x4F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_MVDMA121_S + MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes. 3 + 0x5F8DC000 + + + + MVDMA121 + 220 + + + + GLOBAL_RAMC123_NS + RAM Controller 2 + 0x4F8DD000 + + + + + GLOBAL_RAMC123_S + RAM Controller 3 + 0x5F8DD000 + + + + + GLOBAL_I3C121_NS + I3C 2 + 0x4F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_I3C121_S + I3C 3 + 0x5F8DE000 + + + + I3C121 + 222 + + + + GLOBAL_DPPIC120_NS + Distributed programmable peripheral interconnect controller 2 + 0x4F8E1000 + + + + + + GLOBAL_DPPIC120_S + Distributed programmable peripheral interconnect controller 3 + 0x5F8E1000 + + + + + + GLOBAL_TIMER120_NS + Timer/Counter 6 + 0x4F8E2000 + + + + TIMER120 + 226 + + + + GLOBAL_TIMER120_S + Timer/Counter 7 + 0x5F8E2000 + + + + TIMER120 + 226 + + + + GLOBAL_TIMER121_NS + Timer/Counter 8 + 0x4F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_TIMER121_S + Timer/Counter 9 + 0x5F8E3000 + + + + TIMER121 + 227 + + + + GLOBAL_PWM120_NS + Pulse width modulation unit 0 + 0x4F8E4000 + PWM + + + + 0 + 0x1000 + registers + + + PWM120 + 228 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + PWM_TASKS_DMA + write-only + 0x010 + + 2 + 0x008 + SEQ[%s] + Peripheral tasks. + PWM_TASKS_DMA_SEQ + write-only + 0x000 + + START + Description cluster: Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Description cluster: Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_NEXTSTEP + Subscribe configuration for task NEXTSTEP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task NEXTSTEP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA + read-write + 0x090 + + 2 + 0x008 + SEQ[%s] + Subscribe configuration for tasks + PWM_SUBSCRIBE_DMA_SEQ + read-write + 0x000 + + START + Description cluster: Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Description cluster: Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0x120 + read-write + 0x00000000 + 0x20 + + + EVENTS_RAMUNDERFLOW + Emitted when retrieving from RAM does not complete in time for the PWM module + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + PWM_EVENTS_DMA + read-write + 0x124 + + 2 + 0x00C + SEQ[%s] + Peripheral events. + PWM_EVENTS_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Description cluster: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + Description cluster: An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + 0x4 + 0x4 + EVENTS_COMPAREMATCH[%s] + Description collection: This event is generated when the compare matches for the compare channel [n]. + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPAREMATCH + This event is generated when the compare matches for the compare channel [n]. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQSTARTED[%s] + Description collection: Publish configuration for event SEQSTARTED[n] + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQSTARTED[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x2 + 0x4 + PUBLISH_SEQEND[%s] + Description collection: Publish configuration for event SEQEND[n] + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SEQEND[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_PWMPERIODEND + Publish configuration for event PWMPERIODEND + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event PWMPERIODEND will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LOOPSDONE + Publish configuration for event LOOPSDONE + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LOOPSDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RAMUNDERFLOW + Publish configuration for event RAMUNDERFLOW + 0x1A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RAMUNDERFLOW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + PWM_PUBLISH_DMA + read-write + 0x1A4 + + 2 + 0x00C + SEQ[%s] + Publish configuration for events + PWM_PUBLISH_DMA_SEQ + read-write + 0x000 + + END + Description cluster: Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Description cluster: Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Description cluster: Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + 0x4 + 0x4 + PUBLISH_COMPAREMATCH[%s] + Description collection: Publish configuration for event COMPAREMATCH[n] + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPAREMATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + SEQEND0_STOP + Shortcut between event SEQEND[n] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[n] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ0_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_DMA_SEQ1_START + Shortcut between event LOOPSDONE and task DMA.SEQ[n].START + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + RAMUNDERFLOW_STOP + Shortcut between event RAMUNDERFLOW and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ0_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_SEQ1_BUSERROR_STOP + Shortcut between event DMA.SEQ[n].BUSERROR and task STOP + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RAMUNDERFLOW + Enable or disable interrupt for event RAMUNDERFLOW + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0END + Enable or disable interrupt for event DMASEQ0END + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0READY + Enable or disable interrupt for event DMASEQ0READY + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Enable or disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1END + Enable or disable interrupt for event DMASEQ1END + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1READY + Enable or disable interrupt for event DMASEQ1READY + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Enable or disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH0 + Enable or disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH1 + Enable or disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH2 + Enable or disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPAREMATCH3 + Enable or disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to enable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0END + Write '1' to enable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0READY + Write '1' to enable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to enable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1END + Write '1' to enable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1READY + Write '1' to enable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to enable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to enable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to enable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to enable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to enable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RAMUNDERFLOW + Write '1' to disable interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0END + Write '1' to disable interrupt for event DMASEQ0END + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0READY + Write '1' to disable interrupt for event DMASEQ0READY + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ0BUSERROR + Write '1' to disable interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1END + Write '1' to disable interrupt for event DMASEQ1END + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1READY + Write '1' to disable interrupt for event DMASEQ1READY + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMASEQ1BUSERROR + Write '1' to disable interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH0 + Write '1' to disable interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH1 + Write '1' to disable interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH2 + Write '1' to disable interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPAREMATCH3 + Write '1' to disable interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED0 + Read pending status of interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQSTARTED1 + Read pending status of interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND0 + Read pending status of interrupt for event SEQEND[0] + 4 + 4 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + SEQEND1 + Read pending status of interrupt for event SEQEND[1] + 5 + 5 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + PWMPERIODEND + Read pending status of interrupt for event PWMPERIODEND + 6 + 6 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + LOOPSDONE + Read pending status of interrupt for event LOOPSDONE + 7 + 7 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + RAMUNDERFLOW + Read pending status of interrupt for event RAMUNDERFLOW + 8 + 8 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0END + Read pending status of interrupt for event DMASEQ0END + 9 + 9 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0READY + Read pending status of interrupt for event DMASEQ0READY + 10 + 10 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ0BUSERROR + Read pending status of interrupt for event DMASEQ0BUSERROR + 11 + 11 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1END + Read pending status of interrupt for event DMASEQ1END + 12 + 12 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1READY + Read pending status of interrupt for event DMASEQ1READY + 13 + 13 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DMASEQ1BUSERROR + Read pending status of interrupt for event DMASEQ1BUSERROR + 14 + 14 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH0 + Read pending status of interrupt for event COMPAREMATCH[0] + 15 + 15 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH1 + Read pending status of interrupt for event COMPAREMATCH[1] + 16 + 16 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH2 + Read pending status of interrupt for event COMPAREMATCH[2] + 17 + 17 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + COMPAREMATCH3 + Read pending status of interrupt for event COMPAREMATCH[3] + 18 + 18 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + 0x20 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0x0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 0x1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + 0x20 + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0x0 + + + DIV_2 + Divide by 2 (8 MHz) + 0x1 + + + DIV_4 + Divide by 4 (4 MHz) + 0x2 + + + DIV_8 + Divide by 8 (2 MHz) + 0x3 + + + DIV_16 + Divide by 16 (1 MHz) + 0x4 + + + DIV_32 + Divide by 32 (500 kHz) + 0x5 + + + DIV_64 + Divide by 64 (250 kHz) + 0x6 + + + DIV_128 + Divide by 128 (125 kHz) + 0x7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + 0x20 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0x0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 0x1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 0x2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 0x3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0x0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 0x1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + 0x20 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0x0000 + + + + + + + IDLEOUT + Configure the output value on the PWM channel during idle + 0x518 + read-write + 0x00000000 + 0x20 + + + VAL_0 + Idle output value for PWM channel [0] + 0 + 0 + + + VAL_1 + Idle output value for PWM channel [1] + 1 + 1 + + + VAL_2 + Idle output value for PWM channel [2] + 2 + 2 + + + VAL_3 + Idle output value for PWM channel [3] + 3 + 3 + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + 0x20 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0x000000 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + 0x20 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + PWM_DMA + read-write + 0x700 + + 2 + 0x024 + SEQ[%s] + Unspecified + PWM_DMA_SEQ + read-write + 0x000 + + PTR + Description cluster: RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction, updated after the END event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Description cluster: Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + TERMINATEONBUSERROR + Description cluster: Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Description cluster: Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_PWM120_S + Pulse width modulation unit 1 + 0x5F8E4000 + + + + PWM120 + 228 + + + + GLOBAL_SPIS120_NS + SPI Slave 0 + 0x4F8E5000 + SPIS + + + + 0 + 0x1000 + registers + + + SPIS120 + 229 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x014 + write-only + 0x00000000 + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x018 + write-only + 0x00000000 + 0x20 + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIS_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIS_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_ACQUIRE + Subscribe configuration for task ACQUIRE + 0x094 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ACQUIRE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RELEASE + Subscribe configuration for task RELEASE + 0x098 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RELEASE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIS_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x118 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACQUIRED + Publish configuration for event ACQUIRED + 0x198 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACQUIRED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + 0x20 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0x0 + + + CPU + Semaphore is assigned to CPU + 0x1 + + + SPIS + Semaphore is assigned to SPI slave + 0x2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 0x3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + 0x00000000 + 0x20 + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + write + + Clear + Write: clear error on writing '1' + 0x1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0x0 + + + Enabled + Enable SPI slave + 0x2 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + 0x00000000 + 0x20 + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CSN + Pin select for CSN signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIS_DMA + read-write + 0x700 + + RX + Unspecified + SPIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIS120_S + SPI Slave 1 + 0x5F8E5000 + + + + SPIS120 + 229 + + + + GLOBAL_SPIM120_NS + Serial Peripheral Interface Master with EasyDMA 0 + 0x4F8E6000 + SPIM + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + SPIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + SPIM_TASKS_DMA_RX + write-only + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + SPIM_SUBSCRIBE_DMA_RX + read-write + 0x008 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STARTED + SPI transaction has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + SPI transaction has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + SPIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + SPIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + SPIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + SPIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + SPIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + SPIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0x0 + + + Enabled + Enable SPIM + 0x7 + + + + + + + PRESCALER + The prescaler is used to set the SPI frequency. + 0x52C + read-write + 0x00000040 + 0x20 + + + DIVISOR + Core clock to SCK divisor + 0 + 6 + + + + + CONFIG + Configuration register + 0x554 + read-write + 0x00000000 + 0x20 + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0x0 + + + LsbFirst + Least significant bit shifted out first + 0x1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0x0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 0x1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0x0 + + + ActiveLow + Active low + 0x1 + + + + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x5AC + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + 0x20 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions. + 0x004 + read-write + 0x00000002 + 0x20 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum duration CSN must stay high between transactions. The value is specified in number of SPIM core clock cycles. + 0 + 7 + + + + + + DCXCNT + DCX configuration + 0x5B4 + read-write + 0x00000000 + 0x20 + + + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. + 0 + 3 + + + + + CSNPOL + Polarity of CSN output + 0x5B8 + read-write + 0x00000000 + 0x20 + + + CSNPOL_0 + Polarity of CSN output + 0 + 0 + + + LOW + Active low (idle state high) + 0x0 + + + HIGH + Active high (idle state low) + 0x1 + + + + + + + CSNCONTROL + Selects which CSN is used, only one CSN can be active at one time. This register can be safely written during an ongoing SPI transaction. + 0x5BC + read-write + 0x00000000 + 0x20 + + + CSN + CSN Number. + 0 + 0 + + + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x600 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DCX + Pin select for DCX signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + 0x1 + 0x4 + CSN[%s] + Description collection: Pin select for CSN + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + SPIM_DMA + read-write + 0x700 + + RX + Unspecified + SPIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + SPIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + SPIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE120_NS + UART with EasyDMA 0 + 0x4F8E6000 + GLOBAL_SPIM120_NS + UARTE + + + + 0 + 0x1000 + registers + + + SPIM120_UARTE120 + 230 + + UARTE + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x01C + write-only + 0x00000000 + 0x20 + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + UARTE_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + UARTE_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + UARTE_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_FLUSHRX + Subscribe configuration for task FLUSHRX + 0x09C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task FLUSHRX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + UARTE_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + Error detected + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x124 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x130 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + UARTE_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + UARTE_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + UARTE_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0x174 + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMETIMEOUT + Timed out due to bus being idle while receiving data. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_CTS + Publish configuration for event CTS + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_NCTS + Publish configuration for event NCTS + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event NCTS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXDRDY + Publish configuration for event TXDRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXDRDY + Publish configuration for event RXDRDY + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXDRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RXTO + Publish configuration for event RXTO + 0x1A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXTO will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXSTOPPED + Publish configuration for event TXSTOPPED + 0x1B0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXSTOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + UARTE_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + UARTE_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + UARTE_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + PUBLISH_FRAMETIMEOUT + Publish configuration for event FRAMETIMEOUT + 0x1F4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMETIMEOUT will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + DMA_RX_END_DMA_RX_START + Shortcut between event DMA.RX.END and task DMA.RX.START + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_END_DMA_RX_STOP + Shortcut between event DMA.RX.END and task DMA.RX.STOP + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_TX_END_DMA_TX_STOP + Shortcut between event DMA.TX.END and task DMA.TX.STOP + 18 + 18 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + FRAMETIMEOUT_DMA_RX_STOP + Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP + 29 + 29 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMETIMEOUT + Enable or disable interrupt for event FRAMETIMEOUT + 29 + 29 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to enable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMETIMEOUT + Write '1' to disable interrupt for event FRAMETIMEOUT + 29 + 29 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0x0 + + + Present + Read: error present + 0x1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0x0 + + + Enabled + Enable UARTE + 0x8 + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1 megabaud + 0x10000000 + + + + + + + CONFIG + Configuration of parity, hardware flow control, framesize, and packet timeout. + 0x56C + read-write + 0x00001000 + 0x20 + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0x0 + + + Two + Two stop bits + 0x1 + + + + + PARITYTYPE + Even or odd parity type + 8 + 8 + + + Even + Even parity + 0x0 + + + Odd + Odd parity + 0x1 + + + + + FRAMESIZE + Set the data frame size + 9 + 12 + + + 9bit + 9 bit data frame size. 9th bit is treated as address bit. + 0x9 + + + 8bit + 8 bit data frame size. + 0x8 + + + 7bit + 7 bit data frame size. + 0x7 + + + 6bit + 6 bit data frame size. + 0x6 + + + 5bit + 5 bit data frame size. + 0x5 + + + 4bit + 4 bit data frame size. + 0x4 + + + + + ENDIAN + Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. + 13 + 13 + + + MSB + Data is trimmed from MSB end. + 0x0 + + + LSB + Data is trimmed from LSB end. + 0x1 + + + + + FRAMETIMEOUT + Enable packet timeout. + 14 + 14 + + + DISABLED + Packet timeout is disabled. + 0x0 + + + ENABLED + Packet timeout is enabled. + 0x1 + + + + + + + ADDRESS + Set the address of the UARTE for RX when used in 9 bit data frame mode. + 0x574 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Set address + 0 + 7 + + + + + FRAMETIMEOUT + Set the number of UARTE bits to count before triggering packet timeout. + 0x578 + read-write + 0x00000010 + 0x20 + + + COUNTERTOP + Number of UARTE bits before timeout. + 0 + 9 + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x604 + + TXD + Pin select for TXD signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + CTS + Pin select for CTS signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RXD + Pin select for RXD signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + RTS + Pin select for RTS signal + 0x0C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + UARTE_DMA + read-write + 0x700 + + RX + Unspecified + UARTE_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + UARTE_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + UARTE_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_SPIM120_S + Serial Peripheral Interface Master with EasyDMA 1 + 0x5F8E6000 + + + + SPIM120_UARTE120 + 230 + + + + GLOBAL_UARTE120_S + UART with EasyDMA 1 + 0x5F8E6000 + GLOBAL_SPIM120_S + + + + SPIM120_UARTE120 + 230 + + + + GLOBAL_SPIM121_NS + Serial Peripheral Interface Master with EasyDMA 2 + 0x4F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_SPIM121_S + Serial Peripheral Interface Master with EasyDMA 3 + 0x5F8E7000 + + + + SPIM121 + 231 + + + + GLOBAL_VPR130_NS + VPR peripheral registers 4 + 0x4F908000 + + + + VPR130 + 264 + + + + GLOBAL_VPR130_S + VPR peripheral registers 5 + 0x5F908000 + + + + VPR130 + 264 + + + + GLOBAL_IPCT130_NS + IPCT APB registers 2 + 0x4F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_IPCT130_S + IPCT APB registers 3 + 0x5F921000 + + + + + IPCT130_0 + 289 + + + + GLOBAL_DPPIC130_NS + Distributed programmable peripheral interconnect controller 4 + 0x4F922000 + + + + + + GLOBAL_DPPIC130_S + Distributed programmable peripheral interconnect controller 5 + 0x5F922000 + + + + + + GLOBAL_MUTEX130_NS + MUTEX 1 + 0x4F927000 + + + + + GLOBAL_RTC130_NS + Real-time counter 0 + 0x4F928000 + RTC + + + + 0 + 0x1000 + registers + + + RTC130 + 296 + + RTC + 0x20 + + + TASKS_START + Start RTC counter + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop RTC counter + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CLEAR + Clear RTC counter + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_CLEAR + Clear RTC counter + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_TRIGOVRFLW + Set counter to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x8 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture RTC counter to CC[n] register + 0x040 + write-only + 0x00000000 + 0x20 + + + TASKS_CAPTURE + Capture RTC counter to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CLEAR + Subscribe configuration for task CLEAR + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CLEAR will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_TRIGOVRFLW + Subscribe configuration for task TRIGOVRFLW + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task TRIGOVRFLW will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x8 + 0x4 + SUBSCRIBE_CAPTURE[%s] + Description collection: Subscribe configuration for task CAPTURE[n] + 0x0C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CAPTURE[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_TICK + Event on counter increment + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_TICK + Event on counter increment + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_OVRFLW + Event on counter overflow + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_OVRFLW + Event on counter overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x8 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_TICK + Publish configuration for event TICK + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TICK will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_OVRFLW + Publish configuration for event OVRFLW + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event OVRFLW will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x8 + 0x4 + PUBLISH_COMPARE[%s] + Description collection: Publish configuration for event COMPARE[n] + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event COMPARE[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE6_CLEAR + Shortcut between event COMPARE[6] and task CLEAR + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + COMPARE7_CLEAR + Shortcut between event COMPARE[7] and task CLEAR + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable interrupt for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable interrupt for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + 0x00000000 + 0x20 + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE4 + Enable or disable event routing for event COMPARE[4] + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE5 + Enable or disable event routing for event COMPARE[5] + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE6 + Enable or disable event routing for event COMPARE[6] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + COMPARE7 + Enable or disable event routing for event COMPARE[7] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE4 + Write '1' to enable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE5 + Write '1' to enable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE6 + Write '1' to enable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + COMPARE7 + Write '1' to enable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + 0x00000000 + 0x20 + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE4 + Write '1' to disable event routing for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE5 + Write '1' to disable event routing for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE6 + Write '1' to disable event routing for event COMPARE[6] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + COMPARE7 + Write '1' to disable event routing for event COMPARE[7] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + COUNTER + Current counter value + 0x504 + read-only + 0x00000000 + 0x20 + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. + 0x508 + read-write + 0x00000000 + 0x20 + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x8 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + 0x00000000 + 0x20 + + + COMPARE + Compare value + 0 + 31 + + + + + + + GLOBAL_RTC130_S + Real-time counter 1 + 0x5F928000 + + + + RTC130 + 296 + + + + GLOBAL_RTC131_NS + Real-time counter 2 + 0x4F929000 + + + + RTC131 + 297 + + + + GLOBAL_RTC131_S + Real-time counter 3 + 0x5F929000 + + + + RTC131 + 297 + + + + GLOBAL_WDT131_NS + Watchdog Timer 4 + 0x4F92B000 + + + + WDT131 + 299 + + + + GLOBAL_WDT131_S + Watchdog Timer 5 + 0x5F92B000 + + + + WDT131 + 299 + + + + GLOBAL_WDT132_NS + Watchdog Timer 6 + 0x4F92C000 + + + + WDT132 + 300 + + + + GLOBAL_WDT132_S + Watchdog Timer 7 + 0x5F92C000 + + + + WDT132 + 300 + + + + GLOBAL_EGU130_NS + Event generator unit 2 + 0x4F92D000 + + + + EGU130 + 301 + + + + GLOBAL_EGU130_S + Event generator unit 3 + 0x5F92D000 + + + + EGU130 + 301 + + + + GLOBAL_P0_NS + GPIO Port 0 + 0x4F938000 + GPIO + + + + + 0 + 0x200 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x000 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0x0 + + + High + Pin driver is high + 0x1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x004 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 0x1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x008 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0x0 + + + High + Read: pin driver is high + 0x1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 0x1 + + + + + + + IN + Read GPIO port + 0x00C + read-only + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0x0 + + + High + Pin input is high + 0x1 + + + + + + + DIR + Direction of GPIO pins + 0x010 + read-write + 0x00000000 + 0x20 + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0x0 + + + Output + Pin set as output + 0x1 + + + + + + + DIRSET + DIR set register + 0x014 + read-write + 0x00000000 + oneToSet + 0x20 + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 0x1 + + + + + + + DIRCLR + DIR clear register + 0x018 + read-write + 0x00000000 + oneToClear + 0x20 + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0x0 + + + Output + Read: pin set as output + 0x1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 0x1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x020 + read-write + 0x00000000 + 0x20 + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0x0 + + + Latched + Criteria has been met + 0x1 + + + + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0x024 + read-write + 0x00000000 + 0x20 + + + + DETECTMODE + Select between default DETECT signal behavior and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0x0 + + + LDETECT + Use the latched LDETECT behavior + 0x1 + + + + + + + RETAIN + Enable retention for those GPIO registers marked as retained + 0x028 + read-write + 0x0000000C + 0x20 + + + APPLICAION + Enable retention for GPIO registers for Application domain + 2 + 2 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + RADIOCORE + Enable retention for GPIO registers for Radio core + 3 + 3 + + + Disabled + Retention disabled + 0x0 + + + Enabled + Retention enabled + 0x1 + + + + + + + PORTCNF + Unspecified + GPIO_PORTCNF + read-write + 0x030 + + DRIVECTRL + Drive control for impedance matching of the pins in this port + 0x00 + read-write + 0x00000000 + 0x20 + + + + IMPEDANCE50 + Enable 50 ohms impedance to the pins in this port + 0 + 0 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE100 + Enable 100 ohms impedance to the pins in this port + 1 + 1 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE200 + Enable 200 ohms impedance to the pins in this port + 2 + 2 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE400 + Enable 400 ohms impedance to the pins in this port + 3 + 3 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE800 + Enable 800 ohms impedance to the pins in this port + 4 + 4 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + IMPEDANCE1600 + Enable 1600 ohms impedance to the pins in this port + 5 + 5 + + + Disable + Disabled + 0x0 + + + Enable + Enable + 0x1 + + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Pin n configuration of GPIO pin + 0x080 + read-write + 0x00000002 + 0x20 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0x0 + + + Output + Configure pin as an output pin + 0x1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0x0 + + + Disconnect + Disconnect input buffer + 0x1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0x0 + + + Pulldown + Pull down on pin + 0x1 + + + Pullup + Pull up on pin + 0x3 + + + + + DRIVE0 + Drive configuration for '0' + 8 + 9 + + + S0 + Standard '0' + 0x0 + + + H0 + High drive '0' + 0x1 + + + D0 + Disconnect '0'(normally used for wired-or connections) + 0x2 + + + E0 + Extra high drive '0' + 0x3 + + + + + DRIVE1 + Drive configuration for '1' + 10 + 11 + + + S1 + Standard '1' + 0x0 + + + H1 + High drive '1' + 0x1 + + + D1 + Disconnect '1'(normally used for wired-or connections) + 0x2 + + + E1 + Extra high drive '1' + 0x3 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0x0 + + + High + Sense for high level + 0x2 + + + Low + Sense for low level + 0x3 + + + + + CLOCKPIN + Enable clock on the pin. + 31 + 31 + + + Disabled + Clock disabled + 0x0 + + + Enabled + Clock enabled + 0x1 + + + + + + + + + GLOBAL_P1_NS + GPIO Port 1 + 0x4F938200 + + + + + + GLOBAL_P2_NS + GPIO Port 2 + 0x4F938400 + + + + + + GLOBAL_P6_NS + GPIO Port 3 + 0x4F938C00 + + + + + + GLOBAL_P0_S + GPIO Port 4 + 0x5F938000 + + + + + + GLOBAL_P1_S + GPIO Port 5 + 0x5F938200 + + + + + + GLOBAL_P2_S + GPIO Port 6 + 0x5F938400 + + + + + + GLOBAL_P6_S + GPIO Port 7 + 0x5F938C00 + + + + + + GLOBAL_P8_NS + GPIO Port 8 + 0x4F939000 + + + + + + GLOBAL_P9_NS + GPIO Port 9 + 0x4F939200 + + + + + + GLOBAL_P10_NS + GPIO Port 10 + 0x4F939400 + + + + + + GLOBAL_P11_NS + GPIO Port 11 + 0x4F939600 + + + + + + GLOBAL_P12_NS + GPIO Port 12 + 0x4F939800 + + + + + + GLOBAL_P13_NS + GPIO Port 13 + 0x4F939A00 + + + + + + GLOBAL_P8_S + GPIO Port 14 + 0x5F939000 + + + + + + GLOBAL_P9_S + GPIO Port 15 + 0x5F939200 + + + + + + GLOBAL_P10_S + GPIO Port 16 + 0x5F939400 + + + + + + GLOBAL_P11_S + GPIO Port 17 + 0x5F939600 + + + + + + GLOBAL_P12_S + GPIO Port 18 + 0x5F939800 + + + + + + GLOBAL_P13_S + GPIO Port 19 + 0x5F939A00 + + + + + + GLOBAL_DPPIC131_NS + Distributed programmable peripheral interconnect controller 6 + 0x4F981000 + + + + + + GLOBAL_DPPIC131_S + Distributed programmable peripheral interconnect controller 7 + 0x5F981000 + + + + + + GLOBAL_SAADC_NS + Analog to Digital Converter 0 + 0x4F982000 + SAADC + + + + 0 + 0x1000 + registers + + + SAADC + 386 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_CALIBRATEOFFSET + Subscribe configuration for task CALIBRATEOFFSET + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task CALIBRATEOFFSET will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + GLOBAL_SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + 0x00000000 + 0x20 + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + 0x00000000 + 0x20 + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DONE + Publish configuration for event DONE + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_RESULTDONE + Publish configuration for event RESULTDONE + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RESULTDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CALIBRATEDONE + Publish configuration for event CALIBRATEDONE + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CALIBRATEDONE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 8 + 0x008 + PUBLISH_CH[%s] + Publish configuration for events + GLOBAL_SAADC_PUBLISH_CH + read-write + 0x198 + + LIMITH + Description cluster: Publish configuration for event CH[n].LIMITH + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITH will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + LIMITL + Description cluster: Publish configuration for event CH[n].LIMITL + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CH[n].LIMITL will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + STATUS + Status + 0x400 + read-only + 0x00000000 + 0x20 + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0x0 + + + Busy + ADC is busy. Single conversion in progress. + 0x1 + + + + + + + TRIM + Unspecified + GLOBAL_SAADC_TRIM + read-write + 0x440 + + 0x6 + 0x4 + LINCALCOEFF[%s] + Description collection: Linearity calibration coefficient + 0x000 + read-write + 0x00000000 + 0x20 + + + VAL + value + 0 + 15 + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0x0 + + + Enabled + Enable ADC + 0x1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + GLOBAL_SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x0 + read-write + 0x00000000 + 0x20 + + + PIN + Analog positive input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x4 + read-write + 0x00000000 + 0x20 + + + PIN + Analog negative input pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + CONNECT + Connection + 30 + 31 + + + NC + Not connected + 0x0 + + + AnalogInput + Select analog input + 0x1 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + 0x20 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0x0 + + + Pulldown + Pull-down to GND + 0x1 + + + Pullup + Pull-up to VDD_AO_1V8 + 0x2 + + + VDDAO1V8div2 + Set input at VDD_AO_1V8/2 + 0x3 + + + + + GAIN + Gain control + 8 + 9 + + + Gain2_3 + 2/3 + 0x0 + + + Gain1 + 1 + 0x1 + + + Gain2 + 2 + 0x2 + + + Gain4 + 4 + 0x3 + + + + + BURST + Enable burst mode + 11 + 11 + + + Disabled + Burst mode is disabled (normal operation) + 0x0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 0x1 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (1.024 V) + 0x0 + + + External + External reference given at PADC_EXT_REF_1V2 + 0x1 + + + + + MODE + Enable differential mode + 15 + 15 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0x0 + + + Diff + Differential + 0x1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is ((TACQ+1) x 125 ns) + 16 + 24 + + + TCONV + Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) + 28 + 30 + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + 0x20 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + 0x20 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0x0 + + + 10bit + 10 bit + 0x1 + + + 12bit + 12 bit + 0x2 + + + 14bit + 14 bit + 0x3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + 0x00000000 + 0x20 + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0x0 + + + Over2x + Oversample 2x + 0x1 + + + Over4x + Oversample 4x + 0x2 + + + Over8x + Oversample 8x + 0x3 + + + Over16x + Oversample 16x + 0x4 + + + Over32x + Oversample 32x + 0x5 + + + Over64x + Oversample 64x + 0x6 + + + Over128x + Oversample 128x + 0x7 + + + Over256x + Oversample 256x + 0x8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + 0x00000000 + 0x20 + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0x0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 0x1 + + + + + + + RESULT + RESULT EasyDMA channel + GLOBAL_SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer bytes to transfer + 0x004 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of buffer bytes to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer bytes transferred since last START + 0x008 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + GLOBAL_SAADC_S + Analog to Digital Converter 1 + 0x5F982000 + + + + SAADC + 386 + + + + GLOBAL_COMP_NS + Comparator 0 + 0x4F983000 + COMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x2 + + + + + + + PSEL + Pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (AVDD_AO_1V8 &gt;= 1.7 V) + 0x0 + + + AVDDAO1V8 + VREF = AVDD_AO_1V8 + 0x4 + + + ARef + VREF = AREF + 0x5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00002020 + 0x20 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + 0x00000000 + 0x20 + + + SP + Speed and power modes + 0 + 0 + + + Low + Low-power mode + 0x0 + + + High + High-speed mode + 0x1 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0x0 + + + Diff + Differential mode + 0x1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0x0 + + + Hyst40mV + Comparator hysteresis enabled + 0x1 + + + + + + + ISOURCE + Current source select on analog input + 0x53C + read-write + 0x00000000 + 0x20 + + + ISOURCE + Current source select on analog input + 0 + 1 + + + Off + Current source disabled + 0x0 + + + Ien2uA5 + Current source enabled (+/- 2.5 uA) + 0x1 + + + Ien5uA + Current source enabled (+/- 5 uA) + 0x2 + + + Ien10uA + Current source enabled (+/- 10 uA) + 0x3 + + + + + + + + + GLOBAL_LPCOMP_NS + Low-power comparator 0 + 0x4F983000 + GLOBAL_COMP_NS + LPCOMP + + + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 387 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SAMPLE + Subscribe configuration for task SAMPLE + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SAMPLE will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_READY + Publish configuration for event READY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DOWN + Publish configuration for event DOWN + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DOWN will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_UP + Publish configuration for event UP + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event UP will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_CROSS + Publish configuration for event CROSS + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event CROSS will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + READY + Read pending status of interrupt for event READY + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + DOWN + Read pending status of interrupt for event DOWN + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + UP + Read pending status of interrupt for event UP + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + CROSS + Read pending status of interrupt for event CROSS + 3 + 3 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + RESULT + Compare result + 0x400 + read-only + 0x00000000 + 0x20 + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-) + 0x0 + + + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-) + 0x1 + + + + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable LPCOMP + 0 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PSEL + Input pin select + 0x504 + read-write + 0x00000000 + 0x20 + + + PIN + Analog pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + 0x20 + + + REFSEL + Reference select + 0 + 3 + + + Ref1_8Vdd + VDD * 1/8 selected as reference + 0x0 + + + Ref2_8Vdd + VDD * 2/8 selected as reference + 0x1 + + + Ref3_8Vdd + VDD * 3/8 selected as reference + 0x2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 0x3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 0x4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 0x5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 0x6 + + + ARef + External analog reference selected + 0x7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 0x8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 0x9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 0xA + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 0xB + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 0xC + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 0xD + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 0xE + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 0xF + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + 0x00000000 + 0x20 + + + PIN + External analog reference pin select + 0 + 4 + + + PORT + GPIO Port selection + 8 + 11 + + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + 0x00000000 + 0x20 + + + ANADETECT + Analog detect configuration + 0 + 1 + + + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing + 0x0 + + + Up + Generate ANADETECT on upward crossing only + 0x1 + + + Down + Generate ANADETECT on downward crossing only + 0x2 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + 0x00000000 + 0x20 + + + HYST + Comparator hysteresis enable + 0 + 0 + + + Disabled + Comparator hysteresis disabled + 0x0 + + + Enabled + Comparator hysteresis enabled + 0x1 + + + + + + + + + GLOBAL_COMP_S + Comparator 1 + 0x5F983000 + + + + COMP_LPCOMP + 387 + + + + GLOBAL_LPCOMP_S + Low-power comparator 1 + 0x5F983000 + GLOBAL_COMP_S + + + + COMP_LPCOMP + 387 + + + + GLOBAL_TEMP_NS + Temperature Sensor 0 + 0x4F984000 + TEMP + + + + 0 + 0x1000 + registers + + + TEMP + 388 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_DATARDY + Publish configuration for event DATARDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DATARDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + 0x00000000 + int32_t + 0x20 + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000276 + 0x20 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000324 + 0x20 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AB + 0x20 + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x00000453 + 0x20 + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x0000049B + 0x20 + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x00000550 + 0x20 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + A6 + Slope of 7th piece wise linear function + 0x538 + read-write + 0x0000067E + 0x20 + + + A6 + Slope of 7th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00000FA6 + 0x20 + + + B0 + y-intercept of 1st piece wise linear function + 0 + 11 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00000F35 + 0x20 + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 11 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00000FAA + 0x20 + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 11 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x0000007E + 0x20 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 11 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x000000EA + 0x20 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 11 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x000001ED + 0x20 + + + B5 + y-intercept of 6th piece wise linear function + 0 + 11 + + + + + B6 + y-intercept of 7th piece wise linear function + 0x558 + read-write + 0x00000378 + 0x20 + + + B6 + y-intercept of 7th piece wise linear function + 0 + 11 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000ED + 0x20 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000013 + 0x20 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000029 + 0x20 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + 0x20 + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000044 + 0x20 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + T5 + End point of 6th piece wise linear function + 0x574 + read-write + 0x00000053 + 0x20 + + + T5 + End point of 6th piece wise linear function + 0 + 7 + + + + + + + GLOBAL_TEMP_S + Temperature Sensor 1 + 0x5F984000 + + + + TEMP + 388 + + + + GLOBAL_DPPIC132_NS + Distributed programmable peripheral interconnect controller 8 + 0x4F991000 + + + + + + GLOBAL_DPPIC132_S + Distributed programmable peripheral interconnect controller 9 + 0x5F991000 + + + + + + GLOBAL_I2S130_NS + Inter-IC Sound 0 + 0x4F992000 + I2S + + + + 0 + 0x1000 + registers + + + I2S130 + 402 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0x11C + read-write + 0x00000000 + 0x20 + + + EVENTS_FRAMESTART + Frame start event, generated on the active edge of LRCK + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_RXPTRUPD + Publish configuration for event RXPTRUPD + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event RXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_TXPTRUPD + Publish configuration for event TXPTRUPD + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event TXPTRUPD will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_FRAMESTART + Publish configuration for event FRAMESTART + 0x19C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event FRAMESTART will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + FRAMESTART + Enable or disable interrupt for event FRAMESTART + 7 + 7 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 7 + 7 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable I2S module + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable I2S module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + CONFIG + Unspecified + GLOBAL_I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode + 0x000 + read-write + 0x00000000 + 0x20 + + + MODE + I2S mode + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0x0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 0x1 + + + + + + + RXEN + Reception (RX) enable + 0x004 + read-write + 0x00000000 + 0x20 + + + RXEN + Reception (RX) enable + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0x0 + + + Enabled + Reception enabled. + 0x1 + + + + + + + TXEN + Transmission (TX) enable + 0x008 + read-write + 0x00000001 + 0x20 + + + TXEN + Transmission (TX) enable + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0x0 + + + Enabled + Transmission enabled. + 0x1 + + + + + + + MCKEN + Master clock generator enable + 0x00C + read-write + 0x00000001 + 0x20 + + + MCKEN + Master clock generator enable + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0x0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 0x1 + + + + + + + MCKFREQ + I2S clock generator control + 0x010 + read-write + 0x20000000 + 0x20 + + + MCKFREQ + I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. + 0 + 31 + + + 32MDIV2 + 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. + 0x80000000 + + + 32MDIV3 + 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. + 0x50000000 + + + 32MDIV4 + 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. + 0x40000000 + + + 32MDIV5 + 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. + 0x30000000 + + + 32MDIV6 + 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. + 0x28000000 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio + 0x014 + read-write + 0x00000006 + 0x20 + + + RATIO + MCK / LRCK ratio + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0x0 + + + 48X + LRCK = MCK / 48 + 0x1 + + + 64X + LRCK = MCK / 64 + 0x2 + + + 96X + LRCK = MCK / 96 + 0x3 + + + 128X + LRCK = MCK / 128 + 0x4 + + + 192X + LRCK = MCK / 192 + 0x5 + + + 256X + LRCK = MCK / 256 + 0x6 + + + 384X + LRCK = MCK / 384 + 0x7 + + + 512X + LRCK = MCK / 512 + 0x8 + + + + + + + SWIDTH + Sample width + 0x018 + read-write + 0x00000001 + 0x20 + + + SWIDTH + Sample and half-frame width + 0 + 2 + + + 8Bit + 8 bit sample. + 0x0 + + + 16Bit + 16 bit sample. + 0x1 + + + 24Bit + 24 bit sample. + 0x2 + + + 32Bit + 32 bit sample. + 0x3 + + + 8BitIn16 + 8 bit sample in a 16-bit half-frame. + 0x4 + + + 8BitIn32 + 8 bit sample in a 32-bit half-frame. + 0x5 + + + 16BitIn32 + 16 bit sample in a 32-bit half-frame. + 0x6 + + + 24BitIn32 + 24 bit sample in a 32-bit half-frame. + 0x7 + + + + + + + ALIGN + Alignment of sample within a frame + 0x01C + read-write + 0x00000000 + 0x20 + + + ALIGN + Alignment of sample within a frame + 0 + 0 + + + Left + Left-aligned. + 0x0 + + + Right + Right-aligned. + 0x1 + + + + + + + FORMAT + Frame format + 0x020 + read-write + 0x00000000 + 0x20 + + + FORMAT + Frame format + 0 + 0 + + + I2S + Original I2S format. + 0x0 + + + Aligned + Alternate (left- or right-aligned) format. + 0x1 + + + + + + + CHANNELS + Enable channels + 0x024 + read-write + 0x00000000 + 0x20 + + + CHANNELS + Enable channels + 0 + 1 + + + Stereo + Stereo. + 0x0 + + + Left + Left only. + 0x1 + + + Right + Right only. + 0x2 + + + + + + + CLKCONFIG + Clock source selection for the I2S module + 0x028 + read-write + 0x00000000 + 0x20 + + + CLKSRC + Clock source selection + 0 + 0 + + + PCLK32M + 32MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + BYPASS + Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. + 8 + 8 + + + Disable + Disable bypass + 0x0 + + + Enable + Enable bypass + 0x1 + + + + + + + + RXD + Unspecified + GLOBAL_I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + GLOBAL_I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address + 0x000 + read-write + 0x00000000 + 0x20 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + GLOBAL_I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers + 0x000 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words + 0 + 13 + + + + + + PSEL + Unspecified + GLOBAL_I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SCK + Pin select for SCK signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + LRCK + Pin select for LRCK signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDIN + Pin select for SDIN signal + 0x00C + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDOUT + Pin select for SDOUT signal + 0x010 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + + + GLOBAL_I2S130_S + Inter-IC Sound 1 + 0x5F992000 + + + + I2S130 + 402 + + + + GLOBAL_PDM_NS + Pulse Density Modulation (Digital Microphone) Interface 0 + 0x4F993000 + PDM + + + + 0 + 0x1000 + registers + + + PDM + 403 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_STARTED + Publish configuration for event STARTED + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STARTED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_END + Publish configuration for event END + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + INTPEND + Pending interrupts + 0x30C + read-only + 0x00000000 + 0x20 + + + STARTED + Read pending status of interrupt for event STARTED + 0 + 0 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + STOPPED + Read pending status of interrupt for event STOPPED + 1 + 1 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + END + Read pending status of interrupt for event END + 2 + 2 + + read + + NotPending + Read: Not pending + 0x0 + + + Pending + Read: Pending + 0x1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + 0x20 + + + FREQ + PDM_CLK frequency configuration. Enumerations are deprecated, use + PDMCLKCTRL equation to find the register value. The 12 least significant bits of the + register are ignored and shall be set to zero. + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + 0x20 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] + 0x0 + + + Mono + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] + 0x1 + + + + + EDGE + Defines on which PDM_CLK edge left (or mono) is sampled. + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0x0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 0x1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + 0x20 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + 0x20 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20 dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0 dB gain adjustment + 0x28 + + + MaxGain + +20 dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + 0x20 + + + RATIO + Selects the decimation ratio between PDM_CLK and output sample rate + 0 + 2 + + + Ratio64 + Ratio of 64 + 0x0 + + + Ratio80 + Ratio of 80 + 0x1 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + MCLKCONFIG + Master clock generator configuration + 0x54C + read-write + 0x00000000 + 0x20 + + + SRC + Master clock source selection + 0 + 0 + + + PCLK32M + 32 MHz peripheral clock + 0x0 + + + ACLK + Audio PLL clock + 0x1 + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + 0x00000000 + 0x20 + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + 0x00000000 + 0x20 + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + DMA + Unspecified + PDM_DMA + read-write + 0x700 + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x004 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + GLOBAL_PDM_S + Pulse Density Modulation (Digital Microphone) Interface 1 + 0x5F993000 + + + + PDM + 403 + + + + GLOBAL_QDEC130_NS + Quadrature Decoder 0 + 0x4F994000 + QDEC + + + + 0 + 0x1000 + registers + + + QDEC130 + 404 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + 0x00000000 + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + 0x00000000 + 0x20 + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + SUBSCRIBE_START + Subscribe configuration for task START + 0x080 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_READCLRACC + Subscribe configuration for task READCLRACC + 0x088 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task READCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRACC + Subscribe configuration for task RDCLRACC + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRACC will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RDCLRDBL + Subscribe configuration for task RDCLRDBL + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RDCLRDBL will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + 0x00000000 + 0x20 + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + 0x00000000 + 0x20 + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + 0x00000000 + 0x20 + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + PUBLISH_SAMPLERDY + Publish configuration for event SAMPLERDY + 0x180 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SAMPLERDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_REPORTRDY + Publish configuration for event REPORTRDY + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event REPORTRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ACCOF + Publish configuration for event ACCOF + 0x188 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ACCOF will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DBLRDY + Publish configuration for event DBLRDY + 0x18C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event DBLRDY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x190 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + 0x00000000 + 0x20 + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0x0 + + + ActiveHigh + Led active on output pin high + 0x1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + 0x00000000 + 0x20 + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0x0 + + + 256us + 256 us + 0x1 + + + 512us + 512 us + 0x2 + + + 1024us + 1024 us + 0x3 + + + 2048us + 2048 us + 0x4 + + + 4096us + 4096 us + 0x5 + + + 8192us + 8192 us + 0x6 + + + 16384us + 16384 us + 0x7 + + + 32ms + 32768 us + 0x8 + + + 65ms + 65536 us + 0x9 + + + 131ms + 131072 us + 0xA + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + 0x00000000 + int32_t + 0x20 + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + 0x00000000 + 0x20 + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 + + + 10Smpl + 10 samples/report + 0x0 + + + 40Smpl + 40 samples/report + 0x1 + + + 80Smpl + 80 samples/report + 0x2 + + + 120Smpl + 120 samples/report + 0x3 + + + 160Smpl + 160 samples/report + 0x4 + + + 200Smpl + 200 samples/report + 0x5 + + + 240Smpl + 240 samples/report + 0x6 + + + 280Smpl + 280 samples/report + 0x7 + + + 1Smpl + 1 sample/report + 0x8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + 0x00000000 + int32_t + 0x20 + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + 0x00000000 + int32_t + 0x20 + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + 0x00000000 + 0x20 + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0x0 + + + Enabled + Debounce input filters enabled + 0x1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + 0x20 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + 0x00000000 + 0x20 + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + 0x00000000 + 0x20 + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + GLOBAL_QDEC130_S + Quadrature Decoder 1 + 0x5F994000 + + + + QDEC130 + 404 + + + + GLOBAL_QDEC131_NS + Quadrature Decoder 2 + 0x4F995000 + + + + QDEC131 + 405 + + + + GLOBAL_QDEC131_S + Quadrature Decoder 3 + 0x5F995000 + + + + QDEC131 + 405 + + + + GLOBAL_I2S131_NS + Inter-IC Sound 2 + 0x4F997000 + + + + I2S131 + 407 + + + + GLOBAL_I2S131_S + Inter-IC Sound 3 + 0x5F997000 + + + + I2S131 + 407 + + + + GLOBAL_DPPIC133_NS + Distributed programmable peripheral interconnect controller 10 + 0x4F9A1000 + + + + + + GLOBAL_DPPIC133_S + Distributed programmable peripheral interconnect controller 11 + 0x5F9A1000 + + + + + + GLOBAL_TIMER130_NS + Timer/Counter 10 + 0x4F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER130_S + Timer/Counter 11 + 0x5F9A2000 + + + + TIMER130 + 418 + + + + GLOBAL_TIMER131_NS + Timer/Counter 12 + 0x4F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_TIMER131_S + Timer/Counter 13 + 0x5F9A3000 + + + + TIMER131 + 419 + + + + GLOBAL_PWM130_NS + Pulse width modulation unit 2 + 0x4F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_PWM130_S + Pulse width modulation unit 3 + 0x5F9A4000 + + + + PWM130 + 420 + + + + GLOBAL_SPIM130_NS + Serial Peripheral Interface Master with EasyDMA 4 + 0x4F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130_NS + SPI Slave 2 + 0x4F9A5000 + GLOBAL_SPIM130_NS + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130_NS + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x4F9A5000 + GLOBAL_SPIM130_NS + TWIM + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIM + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIM_TASKS_DMA + write-only + 0x028 + + RX + Peripheral tasks. + TWIM_TASKS_DMA_RX + write-only + 0x000 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x008 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x018 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + TX + Peripheral tasks. + TWIM_TASKS_DMA_TX + write-only + 0x028 + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0x000 + write-only + 0x00000000 + 0x20 + + + START + Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0x004 + write-only + 0x00000000 + 0x20 + + + STOP + Stops operation using easyDMA. This does not trigger an END event. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA + read-write + 0x0A8 + + RX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_RX + read-write + 0x000 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x018 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + TX + Subscribe configuration for tasks + TWIM_SUBSCRIBE_DMA_TX + read-write + 0x028 + + START + Subscribe configuration for task START + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task START will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + STOP + Subscribe configuration for task STOP + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0x128 + read-write + 0x00000000 + 0x20 + + + EVENTS_SUSPENDED + SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x134 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x138 + read-write + 0x00000000 + 0x20 + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIM_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIM_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIM_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_SUSPENDED + Publish configuration for event SUSPENDED + 0x1A8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event SUSPENDED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTRX + Publish configuration for event LASTRX + 0x1B4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTRX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_LASTTX + Publish configuration for event LASTTX + 0x1B8 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event LASTTX will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIM_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIM_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIM_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + LASTTX_DMA_RX_START + Shortcut between event LASTTX and task DMA.RX.START + 7 + 7 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_DMA_TX_START + Shortcut between event LASTRX and task DMA.TX.START + 10 + 10 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 10 + 10 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 13 + 13 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 14 + 14 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 10 + 10 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 13 + 13 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 14 + 14 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0x0 + + + Enabled + Enable TWIM + 0x6 + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + 0x20 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + K1000 + 1000 kbps + 0x0FF00000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIM_DMA + read-write + 0x700 + + RX + Unspecified + TWIM_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIM_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIM_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-only + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_TWIS130_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x4F9A5000 + GLOBAL_SPIM130_NS + TWIS + + + + 0 + 0x1000 + registers + + + SERIAL0 + 421 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x004 + write-only + 0x00000000 + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x00C + write-only + 0x00000000 + 0x20 + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x010 + write-only + 0x00000000 + 0x20 + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x020 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x024 + write-only + 0x00000000 + 0x20 + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + TASKS_DMA + Peripheral tasks. + TWIS_TASKS_DMA + write-only + 0x030 + + RX + Peripheral tasks. + TWIS_TASKS_DMA_RX + write-only + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0x000 + write-only + 0x00000000 + 0x20 + + + ENABLEMATCH + Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0x010 + write-only + 0x00000000 + 0x20 + + + DISABLEMATCH + Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. + 0 + 0 + + + Trigger + Trigger task + 0x1 + + + + + + + + + SUBSCRIBE_STOP + Subscribe configuration for task STOP + 0x084 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task STOP will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_SUSPEND + Subscribe configuration for task SUSPEND + 0x08C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task SUSPEND will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_RESUME + Subscribe configuration for task RESUME + 0x090 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task RESUME will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARERX + Subscribe configuration for task PREPARERX + 0x0A0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARERX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_PREPARETX + Subscribe configuration for task PREPARETX + 0x0A4 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task PREPARETX will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + SUBSCRIBE_DMA + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA + read-write + 0x0B0 + + RX + Subscribe configuration for tasks + TWIS_SUBSCRIBE_DMA_RX + read-write + 0x000 + + 0x4 + 0x4 + ENABLEMATCH[%s] + Description collection: Subscribe configuration for task ENABLEMATCH[n] + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task ENABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + 0x4 + 0x4 + DISABLEMATCH[%s] + Description collection: Subscribe configuration for task DISABLEMATCH[n] + 0x010 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that task DISABLEMATCH[n] will subscribe to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable subscription + 0x0 + + + Enabled + Enable subscription + 0x1 + + + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + 0x00000000 + 0x20 + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_ERROR + TWI error + 0x114 + read-write + 0x00000000 + 0x20 + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_WRITE + Write command received + 0x13C + read-write + 0x00000000 + 0x20 + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_READ + Read command received + 0x140 + read-write + 0x00000000 + 0x20 + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + EVENTS_DMA + Peripheral events. + TWIS_EVENTS_DMA + read-write + 0x14C + + RX + Peripheral events. + TWIS_EVENTS_DMA_RX + read-write + 0x000 + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Pattern match is detected on the DMA data bus. + 0x00C + read-write + 0x00000000 + 0x20 + + + MATCH + Pattern match is detected on the DMA data bus. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + TX + Peripheral events. + TWIS_EVENTS_DMA_TX + read-write + 0x01C + + END + Generated after all MAXCNT bytes have been transferred + 0x000 + read-write + 0x00000000 + 0x20 + + + END + Generated after all MAXCNT bytes have been transferred + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0x004 + read-write + 0x00000000 + 0x20 + + + READY + Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be written to prepare for the next sequence. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + BUSERROR + An error occured during the bus transfer. + 0x008 + read-write + 0x00000000 + 0x20 + + + BUSERROR + An error occured during the bus transfer. + 0 + 0 + + + NotGenerated + Event not generated + 0x0 + + + Generated + Event generated + 0x1 + + + + + + + + + PUBLISH_STOPPED + Publish configuration for event STOPPED + 0x184 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event STOPPED will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_ERROR + Publish configuration for event ERROR + 0x194 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event ERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_WRITE + Publish configuration for event WRITE + 0x1BC + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event WRITE will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_READ + Publish configuration for event READ + 0x1C0 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READ will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + PUBLISH_DMA + Publish configuration for events + TWIS_PUBLISH_DMA + read-write + 0x1CC + + RX + Publish configuration for events + TWIS_PUBLISH_DMA_RX + read-write + 0x000 + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + 0x4 + 0x4 + MATCH[%s] + Description collection: Publish configuration for event MATCH[n] + 0x00C + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event MATCH[n] will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + TX + Publish configuration for events + TWIS_PUBLISH_DMA_TX + read-write + 0x01C + + END + Publish configuration for event END + 0x000 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event END will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + READY + Publish configuration for event READY + 0x004 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event READY will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + BUSERROR + Publish configuration for event BUSERROR + 0x008 + read-write + 0x00000000 + 0x20 + + + CHIDX + DPPI channel that event BUSERROR will publish to + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0x0 + + + Enabled + Enable publishing + 0x1 + + + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + 0x00000000 + 0x20 + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows daisy-chaining match events. + 21 + 21 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows daisy-chaining match events. + 22 + 22 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows daisy-chaining match events. + 23 + 23 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows daisy-chaining match events. + 24 + 24 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 25 + 25 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 26 + 26 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 27 + 27 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] + 28 + 28 + + + Disabled + Disable shortcut + 0x0 + + + Enabled + Enable shortcut + 0x1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + 0x00000000 + 0x20 + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 5 + 5 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 15 + 15 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + READ + Enable or disable interrupt for event READ + 16 + 16 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXEND + Enable or disable interrupt for event DMARXEND + 19 + 19 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXREADY + Enable or disable interrupt for event DMARXREADY + 20 + 20 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXBUSERROR + Enable or disable interrupt for event DMARXBUSERROR + 21 + 21 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH0 + Enable or disable interrupt for event DMARXMATCH[0] + 22 + 22 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH1 + Enable or disable interrupt for event DMARXMATCH[1] + 23 + 23 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH2 + Enable or disable interrupt for event DMARXMATCH[2] + 24 + 24 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMARXMATCH3 + Enable or disable interrupt for event DMARXMATCH[3] + 25 + 25 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXEND + Enable or disable interrupt for event DMATXEND + 26 + 26 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXREADY + Enable or disable interrupt for event DMATXREADY + 27 + 27 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + DMATXBUSERROR + Enable or disable interrupt for event DMATXBUSERROR + 28 + 28 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + READ + Write '1' to enable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXEND + Write '1' to enable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXREADY + Write '1' to enable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXBUSERROR + Write '1' to enable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH0 + Write '1' to enable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH1 + Write '1' to enable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH2 + Write '1' to enable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMARXMATCH3 + Write '1' to enable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXEND + Write '1' to enable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXREADY + Write '1' to enable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + DMATXBUSERROR + Write '1' to enable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Set + Enable + 0x1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + 0x00000000 + 0x20 + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 5 + 5 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 15 + 15 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + READ + Write '1' to disable interrupt for event READ + 16 + 16 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXEND + Write '1' to disable interrupt for event DMARXEND + 19 + 19 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXREADY + Write '1' to disable interrupt for event DMARXREADY + 20 + 20 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXBUSERROR + Write '1' to disable interrupt for event DMARXBUSERROR + 21 + 21 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH0 + Write '1' to disable interrupt for event DMARXMATCH[0] + 22 + 22 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH1 + Write '1' to disable interrupt for event DMARXMATCH[1] + 23 + 23 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH2 + Write '1' to disable interrupt for event DMARXMATCH[2] + 24 + 24 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMARXMATCH3 + Write '1' to disable interrupt for event DMARXMATCH[3] + 25 + 25 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXEND + Write '1' to disable interrupt for event DMATXEND + 26 + 26 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXREADY + Write '1' to disable interrupt for event DMATXREADY + 27 + 27 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + DMATXBUSERROR + Write '1' to disable interrupt for event DMATXBUSERROR + 28 + 28 + + read + + Disabled + Read: Disabled + 0x0 + + + Enabled + Read: Enabled + 0x1 + + + + write + + Clear + Disable + 0x1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + 0x00000000 + oneToClear + 0x20 + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0x0 + + + Received + Error occurred + 0x1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0x0 + + + Detected + Error occurred + 0x1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + 0x00000000 + 0x20 + + + MATCH + Indication of which address in ADDRESS that matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + 0x00000000 + 0x20 + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0x0 + + + Enabled + Enable TWIS + 0x9 + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + 0x00000000 + 0x20 + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + 0x20 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0x0 + + + Enabled + Enabled + 0x1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + 0x00000000 + 0x20 + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x600 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + 0x20 + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 8 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 0x1 + + + Connected + Connect + 0x0 + + + + + + + + DMA + Unspecified + TWIS_DMA + read-write + 0x700 + + RX + Unspecified + TWIS_DMA_RX + read-write + 0x000 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + MATCH + Registers to control the behavior of the pattern matcher engine + TWIS_DMA_RX_MATCH + read-write + 0x024 + + CONFIG + Configure individual match events + 0x000 + read-write + 0x00000000 + 0x20 + + + ENABLE_0 + Enable match filter 0 + 0 + 0 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_1 + Enable match filter 1 + 1 + 1 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_2 + Enable match filter 2 + 2 + 2 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ENABLE_3 + Enable match filter 3 + 3 + 3 + + + Disabled + Match filter disabled + 0x0 + + + Enabled + Match filter enabled + 0x1 + + + + + ONESHOT_0 + Configure match filter 0 as one-shot or sticky + 16 + 16 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_1 + Configure match filter 1 as one-shot or sticky + 17 + 17 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_2 + Configure match filter 2 as one-shot or sticky + 18 + 18 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + ONESHOT_3 + Configure match filter 3 as one-shot or sticky + 19 + 19 + + + Continuous + Match filter stays enabled until disabled by task + 0x0 + + + Oneshot + Match filter stays enabled until next data word is received + 0x1 + + + + + + + 0x4 + 0x4 + CANDIDATE[%s] + Description collection: The data to look for - any match will trigger the MATCH[n] event, if enabled. + 0x004 + read-write + 0x00000000 + 0x20 + + + DATA + Data to look for + 0 + 31 + + + + + + + TX + Unspecified + TWIS_DMA_TX + read-write + 0x038 + + PTR + RAM buffer start address + 0x004 + read-write + 0x00000000 + 0x20 + + + PTR + RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in channel buffer + 0x008 + read-write + 0x00000000 + 0x20 + + + MAXCNT + Maximum number of bytes in channel buffer + 0 + 14 + + + + + AMOUNT + Number of bytes transferred in the last transaction, updated after the END event. Also updated after each MATCH event. + 0x00C + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 14 + + + + + CURRENTAMOUNT + Number of bytes transferred in the current transaction + 0x010 + read-only + 0x00000000 + 0x20 + + + AMOUNT + Number of bytes transferred in the current transaction. Continuously updated. + 0 + 14 + + + + + LIST + EasyDMA list type + 0x014 + read-write + 0x00000000 + 0x20 + + + TYPE + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0x0 + + + ArrayList + Use array list + 0x1 + + + + + + + TERMINATEONBUSERROR + Terminate the transaction if a BUSERROR event is detected. + 0x01C + read-write + 0x00000000 + 0x20 + + + ENABLE + 0 + 0 + + + Disabled + Disable + 0x0 + + + Enabled + Enable + 0x1 + + + + + + + BUSERRORADDRESS + Address of transaction that generated the last BUSERROR event. + 0x020 + read-write + 0x00000000 + 0x20 + + + ADDRESS + 0 + 31 + + + + + + + + + GLOBAL_UARTE130_NS + UART with EasyDMA 2 + 0x4F9A5000 + GLOBAL_SPIM130_NS + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM130_S + Serial Peripheral Interface Master with EasyDMA 5 + 0x5F9A5000 + + + + SERIAL0 + 421 + + + + GLOBAL_SPIS130_S + SPI Slave 3 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_TWIM130_S + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_TWIS130_S + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_UARTE130_S + UART with EasyDMA 3 + 0x5F9A5000 + GLOBAL_SPIM130_S + + + + SERIAL0 + 421 + + + + GLOBAL_SPIM131_NS + Serial Peripheral Interface Master with EasyDMA 6 + 0x4F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131_NS + SPI Slave 4 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131_NS + I2C compatible Two-Wire Master Interface with EasyDMA 2 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 2 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131_NS + UART with EasyDMA 4 + 0x4F9A6000 + GLOBAL_SPIM131_NS + + + + SERIAL1 + 422 + + + + GLOBAL_SPIM131_S + Serial Peripheral Interface Master with EasyDMA 7 + 0x5F9A6000 + + + + SERIAL1 + 422 + + + + GLOBAL_SPIS131_S + SPI Slave 5 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_TWIM131_S + I2C compatible Two-Wire Master Interface with EasyDMA 3 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_TWIS131_S + I2C compatible Two-Wire Slave Interface with EasyDMA 3 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_UARTE131_S + UART with EasyDMA 5 + 0x5F9A6000 + GLOBAL_SPIM131_S + + + + SERIAL1 + 422 + + + + GLOBAL_DPPIC134_NS + Distributed programmable peripheral interconnect controller 12 + 0x4F9B1000 + + + + + + GLOBAL_DPPIC134_S + Distributed programmable peripheral interconnect controller 13 + 0x5F9B1000 + + + + + + GLOBAL_TIMER132_NS + Timer/Counter 14 + 0x4F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER132_S + Timer/Counter 15 + 0x5F9B2000 + + + + TIMER132 + 434 + + + + GLOBAL_TIMER133_NS + Timer/Counter 16 + 0x4F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_TIMER133_S + Timer/Counter 17 + 0x5F9B3000 + + + + TIMER133 + 435 + + + + GLOBAL_PWM131_NS + Pulse width modulation unit 4 + 0x4F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_PWM131_S + Pulse width modulation unit 5 + 0x5F9B4000 + + + + PWM131 + 436 + + + + GLOBAL_SPIM132_NS + Serial Peripheral Interface Master with EasyDMA 8 + 0x4F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132_NS + SPI Slave 6 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132_NS + I2C compatible Two-Wire Master Interface with EasyDMA 4 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 4 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132_NS + UART with EasyDMA 6 + 0x4F9B5000 + GLOBAL_SPIM132_NS + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM132_S + Serial Peripheral Interface Master with EasyDMA 9 + 0x5F9B5000 + + + + SERIAL2 + 437 + + + + GLOBAL_SPIS132_S + SPI Slave 7 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_TWIM132_S + I2C compatible Two-Wire Master Interface with EasyDMA 5 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_TWIS132_S + I2C compatible Two-Wire Slave Interface with EasyDMA 5 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_UARTE132_S + UART with EasyDMA 7 + 0x5F9B5000 + GLOBAL_SPIM132_S + + + + SERIAL2 + 437 + + + + GLOBAL_SPIM133_NS + Serial Peripheral Interface Master with EasyDMA 10 + 0x4F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133_NS + SPI Slave 8 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133_NS + I2C compatible Two-Wire Master Interface with EasyDMA 6 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 6 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133_NS + UART with EasyDMA 8 + 0x4F9B6000 + GLOBAL_SPIM133_NS + + + + SERIAL3 + 438 + + + + GLOBAL_SPIM133_S + Serial Peripheral Interface Master with EasyDMA 11 + 0x5F9B6000 + + + + SERIAL3 + 438 + + + + GLOBAL_SPIS133_S + SPI Slave 9 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_TWIM133_S + I2C compatible Two-Wire Master Interface with EasyDMA 7 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_TWIS133_S + I2C compatible Two-Wire Slave Interface with EasyDMA 7 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_UARTE133_S + UART with EasyDMA 9 + 0x5F9B6000 + GLOBAL_SPIM133_S + + + + SERIAL3 + 438 + + + + GLOBAL_DPPIC135_NS + Distributed programmable peripheral interconnect controller 14 + 0x4F9C1000 + + + + + + GLOBAL_DPPIC135_S + Distributed programmable peripheral interconnect controller 15 + 0x5F9C1000 + + + + + + GLOBAL_TIMER134_NS + Timer/Counter 18 + 0x4F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER134_S + Timer/Counter 19 + 0x5F9C2000 + + + + TIMER134 + 450 + + + + GLOBAL_TIMER135_NS + Timer/Counter 20 + 0x4F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_TIMER135_S + Timer/Counter 21 + 0x5F9C3000 + + + + TIMER135 + 451 + + + + GLOBAL_PWM132_NS + Pulse width modulation unit 6 + 0x4F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_PWM132_S + Pulse width modulation unit 7 + 0x5F9C4000 + + + + PWM132 + 452 + + + + GLOBAL_SPIM134_NS + Serial Peripheral Interface Master with EasyDMA 12 + 0x4F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134_NS + SPI Slave 10 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134_NS + I2C compatible Two-Wire Master Interface with EasyDMA 8 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 8 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134_NS + UART with EasyDMA 10 + 0x4F9C5000 + GLOBAL_SPIM134_NS + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM134_S + Serial Peripheral Interface Master with EasyDMA 13 + 0x5F9C5000 + + + + SERIAL4 + 453 + + + + GLOBAL_SPIS134_S + SPI Slave 11 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_TWIM134_S + I2C compatible Two-Wire Master Interface with EasyDMA 9 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_TWIS134_S + I2C compatible Two-Wire Slave Interface with EasyDMA 9 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_UARTE134_S + UART with EasyDMA 11 + 0x5F9C5000 + GLOBAL_SPIM134_S + + + + SERIAL4 + 453 + + + + GLOBAL_SPIM135_NS + Serial Peripheral Interface Master with EasyDMA 14 + 0x4F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135_NS + SPI Slave 12 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135_NS + I2C compatible Two-Wire Master Interface with EasyDMA 10 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 10 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135_NS + UART with EasyDMA 12 + 0x4F9C6000 + GLOBAL_SPIM135_NS + + + + SERIAL5 + 454 + + + + GLOBAL_SPIM135_S + Serial Peripheral Interface Master with EasyDMA 15 + 0x5F9C6000 + + + + SERIAL5 + 454 + + + + GLOBAL_SPIS135_S + SPI Slave 13 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_TWIM135_S + I2C compatible Two-Wire Master Interface with EasyDMA 11 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_TWIS135_S + I2C compatible Two-Wire Slave Interface with EasyDMA 11 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_UARTE135_S + UART with EasyDMA 13 + 0x5F9C6000 + GLOBAL_SPIM135_S + + + + SERIAL5 + 454 + + + + GLOBAL_DPPIC136_NS + Distributed programmable peripheral interconnect controller 16 + 0x4F9D1000 + + + + + + GLOBAL_DPPIC136_S + Distributed programmable peripheral interconnect controller 17 + 0x5F9D1000 + + + + + + GLOBAL_TIMER136_NS + Timer/Counter 22 + 0x4F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER136_S + Timer/Counter 23 + 0x5F9D2000 + + + + TIMER136 + 466 + + + + GLOBAL_TIMER137_NS + Timer/Counter 24 + 0x4F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_TIMER137_S + Timer/Counter 25 + 0x5F9D3000 + + + + TIMER137 + 467 + + + + GLOBAL_PWM133_NS + Pulse width modulation unit 8 + 0x4F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_PWM133_S + Pulse width modulation unit 9 + 0x5F9D4000 + + + + PWM133 + 468 + + + + GLOBAL_SPIM136_NS + Serial Peripheral Interface Master with EasyDMA 16 + 0x4F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136_NS + SPI Slave 14 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136_NS + I2C compatible Two-Wire Master Interface with EasyDMA 12 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 12 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136_NS + UART with EasyDMA 14 + 0x4F9D5000 + GLOBAL_SPIM136_NS + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM136_S + Serial Peripheral Interface Master with EasyDMA 17 + 0x5F9D5000 + + + + SERIAL6 + 469 + + + + GLOBAL_SPIS136_S + SPI Slave 15 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_TWIM136_S + I2C compatible Two-Wire Master Interface with EasyDMA 13 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_TWIS136_S + I2C compatible Two-Wire Slave Interface with EasyDMA 13 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_UARTE136_S + UART with EasyDMA 15 + 0x5F9D5000 + GLOBAL_SPIM136_S + + + + SERIAL6 + 469 + + + + GLOBAL_SPIM137_NS + Serial Peripheral Interface Master with EasyDMA 18 + 0x4F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137_NS + SPI Slave 16 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137_NS + I2C compatible Two-Wire Master Interface with EasyDMA 14 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137_NS + I2C compatible Two-Wire Slave Interface with EasyDMA 14 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137_NS + UART with EasyDMA 16 + 0x4F9D6000 + GLOBAL_SPIM137_NS + + + + SERIAL7 + 470 + + + + GLOBAL_SPIM137_S + Serial Peripheral Interface Master with EasyDMA 19 + 0x5F9D6000 + + + + SERIAL7 + 470 + + + + GLOBAL_SPIS137_S + SPI Slave 17 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_TWIM137_S + I2C compatible Two-Wire Master Interface with EasyDMA 15 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_TWIS137_S + I2C compatible Two-Wire Slave Interface with EasyDMA 15 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + GLOBAL_UARTE137_S + UART with EasyDMA 17 + 0x5F9D6000 + GLOBAL_SPIM137_S + + + + SERIAL7 + 470 + + + + \ No newline at end of file diff --git a/mdk/nrf9230_enga_radiocore_peripherals.h b/mdk/nrf9230_enga_radiocore_peripherals.h new file mode 100644 index 000000000..78c98edc2 --- /dev/null +++ b/mdk/nrf9230_enga_radiocore_peripherals.h @@ -0,0 +1,1623 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_RADIOCORE_PERIPHERALS_H +#define NRF9230_ENGA_RADIOCORE_PERIPHERALS_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +/*CACHEDATA*/ +#define ICACHEDATA_PRESENT 1 +#define ICACHEDATA_COUNT 1 + +#define ICACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ +#define ICACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ +#define ICACHEDATA_NUMDATAUNIT 4 /*!< Number of data units : 4 */ +#define ICACHEDATA_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ + +/*CACHEINFO*/ +#define ICACHEINFO_PRESENT 1 +#define ICACHEINFO_COUNT 1 + +#define ICACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ +#define ICACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ +#define ICACHEINFO_NUMDATAUNIT 4 /*!< Number of data units : 4 */ +#define ICACHEINFO_DATAWIDTH 2 /*!< Data width of a data unit : 2 word(s) */ +#define ICACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ +#define ICACHEINFO_DU_EXTENSION 0 /*!< (unspecified) */ + +/*User information configuration registers*/ +#define UICR_PRESENT 1 +#define UICR_COUNT 1 + +/*CACHEDATA*/ +#define DCACHEDATA_PRESENT 1 +#define DCACHEDATA_COUNT 1 + +#define DCACHEDATA_NUMSETS 256 /*!< Number of sets : 256 */ +#define DCACHEDATA_NUMWAYS 2 /*!< Number of ways : 2 */ +#define DCACHEDATA_NUMDATAUNIT 8 /*!< Number of data units : 8 */ +#define DCACHEDATA_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ + +/*CACHEINFO*/ +#define DCACHEINFO_PRESENT 1 +#define DCACHEINFO_COUNT 1 + +#define DCACHEINFO_NUMSETS 256 /*!< Number of sets : 256 */ +#define DCACHEINFO_NUMWAYS 2 /*!< Number of ways : 2 */ +#define DCACHEINFO_NUMDATAUNIT 8 /*!< Number of data units : 8 */ +#define DCACHEINFO_DATAWIDTH 1 /*!< Data width of a data unit : 1 word(s) */ +#define DCACHEINFO_TAGWIDTH 19 /*!< TAG width : 19 */ +#define DCACHEINFO_DU_EXTENSION 1 /*!< (unspecified) */ + +/*Embedded Trace Macrocell*/ +#define ETM_PRESENT 1 +#define ETM_COUNT 1 + +/*Cross-Trigger Interface control*/ +#define CTI_PRESENT 1 +#define CTI_COUNT 3 + +/*CM33 SubSystem*/ +#define CM33SS_PRESENT 1 +#define CM33SS_COUNT 1 + +#define CPUC_FPUAVAILABLE 1 /*!< (unspecified) */ + +/*Cache*/ +#define CACHE_PRESENT 1 +#define CACHE_COUNT 2 + +#define ICACHE_VIRTUALCACHE 0 /*!< (unspecified) */ +#define ICACHE_FLUSH 0 /*!< (unspecified) */ +#define ICACHE_CLEAN 0 /*!< (unspecified) */ +#define ICACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ +#define ICACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ +#define ICACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ +#define ICACHE_SECUREINVALIDATE 0 /*!< (unspecified) */ + +#define DCACHE_VIRTUALCACHE 0 /*!< (unspecified) */ +#define DCACHE_FLUSH 1 /*!< (unspecified) */ +#define DCACHE_CLEAN 1 /*!< (unspecified) */ +#define DCACHE_NONCACHEABLEMISS 1 /*!< (unspecified) */ +#define DCACHE_BUSWIDTH_MIN 0 /*!< Data bus width : 0..63 */ +#define DCACHE_BUSWIDTH_MAX 63 /*!< Data bus width : 0..63 */ +#define DCACHE_BUSWIDTH_SIZE 64 /*!< Data bus width : 0..63 */ +#define DCACHE_SECUREINVALIDATE 0 /*!< (unspecified) */ + +/*System protection unit*/ +#define SPU_PRESENT 1 +#define SPU_COUNT 4 + +#define SPU000_BELLS 0 /*!< (unspecified) */ +#define SPU000_IPCT 0 /*!< (unspecified) */ +#define SPU000_DPPI 0 /*!< (unspecified) */ +#define SPU000_GPIOTE 0 /*!< (unspecified) */ +#define SPU000_GRTC 0 /*!< (unspecified) */ +#define SPU000_GPIO 0 /*!< (unspecified) */ +#define SPU000_CRACEN 0 /*!< (unspecified) */ +#define SPU000_MRAMC 0 /*!< (unspecified) */ +#define SPU000_COEXC 0 /*!< (unspecified) */ +#define SPU000_ANTSWC 0 /*!< (unspecified) */ +#define SPU000_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU010_BELLS 0 /*!< (unspecified) */ +#define SPU010_IPCT 0 /*!< (unspecified) */ +#define SPU010_DPPI 0 /*!< (unspecified) */ +#define SPU010_GPIOTE 0 /*!< (unspecified) */ +#define SPU010_GRTC 0 /*!< (unspecified) */ +#define SPU010_GPIO 0 /*!< (unspecified) */ +#define SPU010_CRACEN 0 /*!< (unspecified) */ +#define SPU010_MRAMC 0 /*!< (unspecified) */ +#define SPU010_COEXC 0 /*!< (unspecified) */ +#define SPU010_ANTSWC 0 /*!< (unspecified) */ +#define SPU010_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU020_BELLS 0 /*!< (unspecified) */ +#define SPU020_IPCT 1 /*!< (unspecified) */ +#define SPU020_DPPI 1 /*!< (unspecified) */ +#define SPU020_GPIOTE 0 /*!< (unspecified) */ +#define SPU020_GRTC 0 /*!< (unspecified) */ +#define SPU020_GPIO 0 /*!< (unspecified) */ +#define SPU020_CRACEN 0 /*!< (unspecified) */ +#define SPU020_MRAMC 0 /*!< (unspecified) */ +#define SPU020_COEXC 0 /*!< (unspecified) */ +#define SPU020_ANTSWC 0 /*!< (unspecified) */ +#define SPU020_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +#define SPU030_BELLS 0 /*!< (unspecified) */ +#define SPU030_IPCT 0 /*!< (unspecified) */ +#define SPU030_DPPI 1 /*!< (unspecified) */ +#define SPU030_GPIOTE 0 /*!< (unspecified) */ +#define SPU030_GRTC 0 /*!< (unspecified) */ +#define SPU030_GPIO 0 /*!< (unspecified) */ +#define SPU030_CRACEN 0 /*!< (unspecified) */ +#define SPU030_MRAMC 0 /*!< (unspecified) */ +#define SPU030_COEXC 0 /*!< (unspecified) */ +#define SPU030_ANTSWC 0 /*!< (unspecified) */ +#define SPU030_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the + peripheral slave index)*/ + +/*Memory Privilege Controller*/ +#define MPC_PRESENT 1 +#define MPC_COUNT 1 + +#define MPC_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ +#define MPC_RTCHOKE 1 /*!< (unspecified) */ +#define MPC_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ + +/*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ + +#define MVDMA_PRESENT 1 +#define MVDMA_COUNT 3 + +#define MVDMA_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA_DPPI_DISCONNECTED 0 /*!< (unspecified) */ +#define MVDMA_INSTANCE_IN_WRAPPER 0 /*!< (unspecified) */ + +#define MVDMA120_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA120_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA120_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +#define MVDMA121_COMPLETED_EVENT 1 /*!< (unspecified) */ +#define MVDMA121_DPPI_DISCONNECTED 1 /*!< (unspecified) */ +#define MVDMA121_INSTANCE_IN_WRAPPER 1 /*!< (unspecified) */ + +/*RAM Controller*/ +#define RAMC_PRESENT 1 +#define RAMC_COUNT 4 + +#define RAMC000_ECC 0 /*!< (unspecified) */ +#define RAMC000_SEC 1 /*!< (unspecified) */ + +#define RAMC001_ECC 0 /*!< (unspecified) */ +#define RAMC001_SEC 0 /*!< (unspecified) */ + +#define RAMC122_ECC 0 /*!< (unspecified) */ +#define RAMC122_SEC 0 /*!< (unspecified) */ + +#define RAMC123_ECC 0 /*!< (unspecified) */ +#define RAMC123_SEC 0 /*!< (unspecified) */ + +/*HSFLL*/ +#define HSFLL_PRESENT 1 +#define HSFLL_COUNT 1 + +#define HSFLL_DITHER_32B 1 /*!< (unspecified) */ +#define HSFLL_CLOCKCTRL_MULT_RESET 6 /*!< Reset value of register CLOCKCTRL.MULT: clockctrl_mult_reset */ + +/*LRCCONF*/ +#define LRCCONF_PRESENT 1 +#define LRCCONF_COUNT 3 + +#define LRCCONF000_POWERON 0 /*!< (unspecified) */ +#define LRCCONF000_RETAIN 0 /*!< (unspecified) */ +#define LRCCONF000_SYSTEMOFF 0 /*!< (unspecified) */ +#define LRCCONF000_LRCREQHFXO 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_MAX 0 /*!< (unspecified) */ +#define LRCCONF000_NCLK_SIZE 1 /*!< (unspecified) */ +#define LRCCONF000_CLKCTRL 1 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF000_NACTPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF000_PDACT 0 /*!< (unspecified) */ +#define LRCCONF000_NPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF000_NPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF000_OTHERON 0 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_MIN 0 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_MAX 15 /*!< (unspecified) */ +#define LRCCONF000_NDOMAINS_SIZE 16 /*!< (unspecified) */ +#define LRCCONF000_AX2XWAITSTATES 0 /*!< (unspecified) */ +#define LRCCONF000_POWERON_MAIN_RESET 0 /*!< (unspecified) */ +#define LRCCONF000_POWERON_ACT_RESET 0 /*!< (unspecified) */ +#define LRCCONF000_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ +#define LRCCONF000_RETAIN_ACT_RESET 1 /*!< (unspecified) */ + +#define LRCCONF010_POWERON 1 /*!< (unspecified) */ +#define LRCCONF010_RETAIN 1 /*!< (unspecified) */ +#define LRCCONF010_SYSTEMOFF 1 /*!< (unspecified) */ +#define LRCCONF010_LRCREQHFXO 1 /*!< (unspecified) */ +#define LRCCONF010_NCLK_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NCLK_MAX 0 /*!< (unspecified) */ +#define LRCCONF010_NCLK_SIZE 1 /*!< (unspecified) */ +#define LRCCONF010_CLKCTRL 1 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_MAX 1 /*!< (unspecified) */ +#define LRCCONF010_NACTPD_SIZE 2 /*!< (unspecified) */ +#define LRCCONF010_PDACT 1 /*!< (unspecified) */ +#define LRCCONF010_NPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF010_NPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF010_OTHERON 0 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_MIN 0 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_MAX 15 /*!< (unspecified) */ +#define LRCCONF010_NDOMAINS_SIZE 16 /*!< (unspecified) */ +#define LRCCONF010_AX2XWAITSTATES 0 /*!< (unspecified) */ +#define LRCCONF010_POWERON_MAIN_RESET 1 /*!< Reset value of register POWERON.MAIN: 1 */ +#define LRCCONF010_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ +#define LRCCONF010_RETAIN_MAIN_RESET 0 /*!< Reset value of register RETAIN.MAIN: 0 */ +#define LRCCONF010_RETAIN_ACT_RESET 0 /*!< Reset value of register RETAIN.ACT: 0 */ + +#define LRCCONF020_POWERON 0 /*!< (unspecified) */ +#define LRCCONF020_RETAIN 0 /*!< (unspecified) */ +#define LRCCONF020_SYSTEMOFF 0 /*!< (unspecified) */ +#define LRCCONF020_LRCREQHFXO 0 /*!< (unspecified) */ +#define LRCCONF020_NCLK_MIN 0 /*!< (unspecified) */ +#define LRCCONF020_NCLK_MAX 7 /*!< (unspecified) */ +#define LRCCONF020_NCLK_SIZE 8 /*!< (unspecified) */ +#define LRCCONF020_CLKCTRL 0 /*!< (unspecified) */ +#define LRCCONF020_NACTPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF020_NACTPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF020_NACTPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF020_PDACT 0 /*!< (unspecified) */ +#define LRCCONF020_NPD_MIN 0 /*!< (unspecified) */ +#define LRCCONF020_NPD_MAX 7 /*!< (unspecified) */ +#define LRCCONF020_NPD_SIZE 8 /*!< (unspecified) */ +#define LRCCONF020_OTHERON 0 /*!< (unspecified) */ +#define LRCCONF020_NDOMAINS_MIN 0 /*!< (unspecified) */ +#define LRCCONF020_NDOMAINS_MAX 15 /*!< (unspecified) */ +#define LRCCONF020_NDOMAINS_SIZE 16 /*!< (unspecified) */ +#define LRCCONF020_AX2XWAITSTATES 0 /*!< (unspecified) */ +#define LRCCONF020_POWERON_MAIN_RESET 0 /*!< (unspecified) */ +#define LRCCONF020_POWERON_ACT_RESET 0 /*!< (unspecified) */ +#define LRCCONF020_RETAIN_MAIN_RESET 1 /*!< (unspecified) */ +#define LRCCONF020_RETAIN_ACT_RESET 1 /*!< (unspecified) */ + +/*Memory configuration*/ +#define MEMCONF_PRESENT 1 +#define MEMCONF_COUNT 1 + +#define MEMCONF_RETTRIM 1 /*!< (unspecified) */ +#define MEMCONF_REPAIR 0 /*!< (unspecified) */ +#define MEMCONF_POWER 1 /*!< (unspecified) */ + +/*Watchdog Timer*/ +#define WDT_PRESENT 1 +#define WDT_COUNT 4 + +#define WDT010_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT010_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT011_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT011_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT131_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT131_HAS_INTEN 0 /*!< (unspecified) */ + +#define WDT132_ALLOW_STOP 0 /*!< (unspecified) */ +#define WDT132_HAS_INTEN 0 /*!< (unspecified) */ + +/*RESETINFO*/ +#define RESETINFO_PRESENT 1 +#define RESETINFO_COUNT 1 + +#define RESETINFO_HASRESETREAS 1 /*!< (unspecified) */ +#define RESETINFO_CROSSDOMAINRESET 1 /*!< (unspecified) */ + +/*Distributed programmable peripheral interconnect controller*/ +#define DPPIC_PRESENT 1 +#define DPPIC_COUNT 9 + +#define DPPIC020_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC020_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC020_CH_NUM_MAX 23 /*!< (unspecified) */ +#define DPPIC020_CH_NUM_SIZE 24 /*!< (unspecified) */ +#define DPPIC020_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC020_GROUP_NUM_MAX 3 /*!< (unspecified) */ +#define DPPIC020_GROUP_NUM_SIZE 4 /*!< (unspecified) */ + +#define DPPIC120_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC120_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC120_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC130_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC130_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC130_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC131_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC131_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC131_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC132_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC132_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC132_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC133_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC133_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC133_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC134_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC134_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC134_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC135_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC135_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC135_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +#define DPPIC136_HASCHANNELGROUPS 1 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_MAX 7 /*!< (unspecified) */ +#define DPPIC136_CH_NUM_SIZE 8 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MIN 0 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_MAX 1 /*!< (unspecified) */ +#define DPPIC136_GROUP_NUM_SIZE 2 /*!< (unspecified) */ + +/*PPIB APB registers*/ +#define PPIB_PRESENT 1 +#define PPIB_COUNT 2 + +#define PPIB020_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB020_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ +#define PPIB020_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ + +#define PPIB030_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ +#define PPIB030_NTASKSEVENTS_MAX 15 /*!< (unspecified) */ +#define PPIB030_NTASKSEVENTS_SIZE 16 /*!< (unspecified) */ + +/*Event generator unit*/ +#define EGU_PRESENT 1 +#define EGU_COUNT 2 + +#define EGU020_PEND 0 /*!< (unspecified) */ +#define EGU020_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU020_CH_NUM_MAX 15 /*!< (unspecified) */ +#define EGU020_CH_NUM_SIZE 16 /*!< (unspecified) */ + +#define EGU130_PEND 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MIN 0 /*!< (unspecified) */ +#define EGU130_CH_NUM_MAX 7 /*!< (unspecified) */ +#define EGU130_CH_NUM_SIZE 8 /*!< (unspecified) */ + +/*Timer/Counter*/ +#define TIMER_PRESENT 1 +#define TIMER_COUNT 13 + +#define TIMER020_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER020_CC_NUM_MAX 7 /*!< (unspecified) */ +#define TIMER020_CC_NUM_SIZE 8 /*!< (unspecified) */ +#define TIMER020_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER020_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER020_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER020_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ +#define TIMER020_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER021_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER021_CC_NUM_MAX 7 /*!< (unspecified) */ +#define TIMER021_CC_NUM_SIZE 8 /*!< (unspecified) */ +#define TIMER021_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER021_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER021_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER021_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ +#define TIMER021_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER022_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER022_CC_NUM_MAX 7 /*!< (unspecified) */ +#define TIMER022_CC_NUM_SIZE 8 /*!< (unspecified) */ +#define TIMER022_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER022_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER022_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER022_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ +#define TIMER022_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER120_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER120_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER120_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER120_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER120_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER120_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER121_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER121_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER121_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER121_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER121_PCLK_MHZ 320 /*!< Peripheral clock frequency (PCLK) is 320 MHz */ +#define TIMER121_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER130_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER130_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER130_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER130_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER130_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER131_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER131_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER131_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER131_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER131_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER132_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER132_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER132_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER132_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER132_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER132_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER133_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER133_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER133_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER133_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER133_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER133_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER134_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER134_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER134_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER134_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER134_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER134_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER135_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER135_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER135_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER135_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER135_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER135_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER136_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER136_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER136_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER136_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER136_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER136_PCLK_VARIABLE 0 /*!< (unspecified) */ + +#define TIMER137_CC_NUM_MIN 0 /*!< (unspecified) */ +#define TIMER137_CC_NUM_MAX 5 /*!< (unspecified) */ +#define TIMER137_CC_NUM_SIZE 6 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MIN 0 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_MAX 31 /*!< (unspecified) */ +#define TIMER137_MAX_SIZE_SIZE 32 /*!< (unspecified) */ +#define TIMER137_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ +#define TIMER137_PCLK_VARIABLE 0 /*!< (unspecified) */ + +/*Real-time counter*/ +#define RTC_PRESENT 1 +#define RTC_COUNT 3 + +#define RTC_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC_CC_NUM_MAX 7 /*!< (unspecified) */ +#define RTC_CC_NUM_SIZE 8 /*!< (unspecified) */ +#define RTC_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC_LFCLK_ENABLE 0 /*!< (unspecified) */ + +#define RTC130_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC130_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC130_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC130_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC130_LFCLK_ENABLE 0 /*!< (unspecified) */ + +#define RTC131_CC_NUM_MIN 0 /*!< (unspecified) */ +#define RTC131_CC_NUM_MAX 3 /*!< (unspecified) */ +#define RTC131_CC_NUM_SIZE 4 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MIN 0 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_MAX 23 /*!< (unspecified) */ +#define RTC131_BIT_WIDTH_SIZE 24 /*!< (unspecified) */ +#define RTC131_LFCLK_ENABLE 0 /*!< (unspecified) */ + +/*2.4 GHz radio*/ +#define RADIO_PRESENT 1 +#define RADIO_COUNT 1 + +#define RADIO_IRQ_COUNT 2 +#define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ +#define RADIO_PERPOWER 1 /*!< (unspecified) */ + +/*VPR peripheral registers*/ +#define VPR_PRESENT 1 +#define VPR_COUNT 3 + +#define VPR_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR_RAM_BASE_ADDR 0x23040000 /*!< (unspecified) */ +#define VPR_RAM_SZ 15 /*!< (unspecified) */ +#define VPR_RETAINED 1 /*!< (unspecified) */ +#define VPR_VPRSAVEDCTX 0 /*!< (unspecified) */ +#define VPR_VPRSAVEADDR 0x00000000 /*!< (unspecified) */ +#define VPR_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPR_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPR_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPR_VEVIF_TASKS_MASK 0x0000FF00 /*!< Mask of supported VEVIF tasks: 0x0000FF00 */ +#define VPR_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..10 */ +#define VPR_VEVIF_NDPPI_MAX 10 /*!< VEVIF DPPI channels: 8..10 */ +#define VPR_VEVIF_NDPPI_SIZE 11 /*!< VEVIF DPPI channels: 8..10 */ +#define VPR_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPR_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPR_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPR_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x53034400 */ + +#define VPR121_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR121_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR121_RAM_BASE_ADDR 0x2F890000 /*!< (unspecified) */ +#define VPR121_RAM_SZ 15 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGNAME NRF_MEMCONF120->POWER[0].RET /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX_REGBIT 23 /*!< (unspecified) */ +#define VPR121_RETAINED 0 /*!< (unspecified) */ +#define VPR121_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR121_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR121_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR121_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR121_VEVIF_TASKS_MASK 0xFFFF0000 /*!< Mask of supported VEVIF tasks: 0xFFFF0000 */ +#define VPR121_VEVIF_NDPPI_MIN 24 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_MAX 27 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NDPPI_SIZE 28 /*!< VEVIF DPPI channels: 24..27 */ +#define VPR121_VEVIF_NEVENTS_MIN 28 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 28..31 */ +#define VPR121_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 28..31 */ +#define VPR121_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F8D4400 */ + +#define VPR130_INIT_PC_RESET_VALUE 0x00000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x00000000 */ +#define VPR130_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ +#define VPR130_RAM_BASE_ADDR 0x2FC00000 /*!< (unspecified) */ +#define VPR130_RAM_SZ 15 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGNAME NRF_MEMCONF130->POWER[0].RET /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX_REGBIT 5 /*!< (unspecified) */ +#define VPR130_RETAINED 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEDCTX 1 /*!< (unspecified) */ +#define VPR130_VPRSAVEADDR 0x2F800000 /*!< (unspecified) */ +#define VPR130_VPRREMAPADDRVTOB 0x00000000 /*!< (unspecified) */ +#define VPR130_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_MAX 15 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_NTASKS_SIZE 16 /*!< VEVIF tasks: 0..15 */ +#define VPR130_VEVIF_TASKS_MASK 0x0000FFF0 /*!< Mask of supported VEVIF tasks: 0x0000FFF0 */ +#define VPR130_VEVIF_NDPPI_MIN 8 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_MAX 11 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NDPPI_SIZE 12 /*!< VEVIF DPPI channels: 8..11 */ +#define VPR130_VEVIF_NEVENTS_MIN 12 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_MAX 15 /*!< VEVIF events: 12..15 */ +#define VPR130_VEVIF_NEVENTS_SIZE 16 /*!< VEVIF events: 12..15 */ +#define VPR130_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5F908400 */ + +/*Accelerated Address Resolver*/ +#define AAR_PRESENT 1 +#define AAR_COUNT 2 + +/*AES CCM Mode Encryption*/ +#define CCM_PRESENT 1 +#define CCM_COUNT 2 + +#define CCM030_AMOUNTREG 0 /*!< (unspecified) */ +#define CCM030_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ +#define CCM030_DMAERROR 0 /*!< (unspecified) */ + +#define CCM031_AMOUNTREG 0 /*!< (unspecified) */ +#define CCM031_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ +#define CCM031_DMAERROR 0 /*!< (unspecified) */ + +/*AES ECB Mode Encryption*/ +#define ECB_PRESENT 1 +#define ECB_COUNT 2 + +#define ECB030_AMOUNTREG 1 /*!< (unspecified) */ + +#define ECB031_AMOUNTREG 1 /*!< (unspecified) */ + +/*IPCT APB registers*/ +#define IPCT_PRESENT 1 +#define IPCT_COUNT 3 + +#define IPCT_IRQ_COUNT 2 + +#define IPCT120_IRQ_COUNT 1 + +#define IPCT130_IRQ_COUNT 1 + +/*Software interrupt*/ +#define SWI_PRESENT 1 +#define SWI_COUNT 8 + +/*BELLBOARD APB registers*/ +#define BELLBOARD_PRESENT 1 +#define BELLBOARD_COUNT 1 + +#define BELLBOARD_IRQ_COUNT 4 + +/*Factory Information Configuration Registers*/ +#define FICR_PRESENT 1 +#define FICR_COUNT 1 + +/*USBHSCORE*/ +#define USBHSCORE_PRESENT 1 +#define USBHSCORE_COUNT 1 + +/*I3CCORE*/ +#define I3CCORE_PRESENT 1 +#define I3CCORE_COUNT 2 + +/*DMU*/ +#define DMU_PRESENT 1 +#define DMU_COUNT 2 + +/*MCAN*/ +#define MCAN_PRESENT 1 +#define MCAN_COUNT 2 + +/*System Trace Macrocell data buffer*/ +#define STMDATA_PRESENT 1 +#define STMDATA_COUNT 1 + +/*TDDCONF*/ +#define TDDCONF_PRESENT 1 +#define TDDCONF_COUNT 1 + +#define TDDCONF_FEATEN_TDDCONF_CLK_320MHZ 0 /*!< (unspecified) */ +#define TDDCONF_FEATEN_TDDCONF_CLK_400MHZ 1 /*!< (unspecified) */ + +/*System Trace Macrocell*/ +#define STM_PRESENT 1 +#define STM_COUNT 1 + +/*Trace Port Interface Unit*/ +#define TPIU_PRESENT 1 +#define TPIU_COUNT 1 + +/*ATB Replicator module*/ +#define ATBREPLICATOR_PRESENT 1 +#define ATBREPLICATOR_COUNT 4 + +/*ATB funnel module*/ +#define ATBFUNNEL_PRESENT 1 +#define ATBFUNNEL_COUNT 4 + +/*GPIO Tasks and Events*/ +#define GPIOTE_PRESENT 1 +#define GPIOTE_COUNT 2 + +#define GPIOTE130_IRQ_COUNT 2 +#define GPIOTE130_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE130_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +#define GPIOTE131_IRQ_COUNT 2 +#define GPIOTE131_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_MAX 3 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NPORTEVENTS_SIZE 4 /*!< Number of GPIOTE port events: 0..3 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ +#define GPIOTE131_HAS_PORT_EVENT 1 /*!< (unspecified) */ + +/*Global Real-time counter*/ +#define GRTC_PRESENT 1 +#define GRTC_COUNT 1 + +#define GRTC_IRQ_COUNT 3 +#define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : + 0..14*/ +#define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ +#define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ +#define GRTC_NDOMAIN_MIN 0 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_MAX 15 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_NDOMAIN_SIZE 16 /*!< Number of domains at the KEEPRUNNING register: 0..15 */ +#define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_MAX 2 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_GRTC_NINTERRUPTS_SIZE 3 /*!< Number of GRTC interrupts : 0..2 */ +#define GRTC_PWMREGS 1 /*!< (unspecified) */ +#define GRTC_CLKOUTREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELREG 1 /*!< (unspecified) */ +#define GRTC_CLKSELLFLPRC 0 /*!< (unspecified) */ +#define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ +#define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ + +/*Trace buffer monitor*/ +#define TBM_PRESENT 1 +#define TBM_COUNT 1 + +/*USBHS*/ +#define USBHS_PRESENT 1 +#define USBHS_COUNT 1 + +/*External Memory Interface*/ +#define EXMIF_PRESENT 1 +#define EXMIF_COUNT 1 + +/*BELLBOARD public registers*/ +#define BELLBOARDPUBLIC_PRESENT 1 +#define BELLBOARDPUBLIC_COUNT 1 + +/*VPR peripheral registers*/ +#define VPRPUBLIC_PRESENT 1 +#define VPRPUBLIC_COUNT 1 + +#define VPR120_VEVIF_NTASKS_MIN 0 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_MAX 31 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_NTASKS_SIZE 32 /*!< VEVIF tasks: 0..31 */ +#define VPR120_VEVIF_TASKS_MASK 0xFFFFF0FF /*!< Mask of supported VEVIF tasks: 0xFFFFF0FF */ + +/*MUTEX*/ +#define MUTEX_PRESENT 1 +#define MUTEX_COUNT 2 + +/*I3C*/ +#define I3C_PRESENT 1 +#define I3C_COUNT 2 + +/*Controller Area Network*/ +#define CAN_PRESENT 1 +#define CAN_COUNT 2 + +/*Pulse width modulation unit*/ +#define PWM_PRESENT 1 +#define PWM_COUNT 5 + +#define PWM120_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM120_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM120_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM120_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM130_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM130_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM130_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM130_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM131_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM131_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM131_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM131_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM132_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM132_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM132_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM132_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define PWM133_IDLE_OUT 1 /*!< (unspecified) */ +#define PWM133_COMPARE_MATCH 1 /*!< (unspecified) */ +#define PWM133_FEATURES_V2 0 /*!< (unspecified) */ +#define PWM133_NO_FEATURES_V2 1 /*!< (unspecified) */ +#define PWM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*SPI Slave*/ +#define SPIS_PRESENT 1 +#define SPIS_COUNT 9 + +#define SPIS120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define SPIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Serial Peripheral Interface Master with EasyDMA*/ +#define SPIM_PRESENT 1 +#define SPIM_COUNT 10 + +#define SPIM120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM120_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM120_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM120_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM120_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM120_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM120_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM120_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM120_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM121_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM121_MAX_DATARATE 32 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM121_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM121_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM121_CORE_FREQUENCY 320 /*!< Peripheral core frequency is 320 MHz. */ +#define SPIM121_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM121_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM121_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM121_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM121_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM130_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM130_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM130_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM130_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM130_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM130_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM130_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM130_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM131_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM131_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM131_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM131_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM131_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM131_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM131_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM131_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM132_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM132_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM132_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM132_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM132_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM132_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM132_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM132_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM133_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM133_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM133_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM133_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM133_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM133_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM133_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM133_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM134_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM134_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM134_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM134_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM134_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM134_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM134_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM134_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM135_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM135_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM135_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM135_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM135_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM135_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM135_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM135_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM136_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM136_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM136_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM136_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM136_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM136_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM136_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM136_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +#define SPIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ +#define SPIM137_MAX_DATARATE 8 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define SPIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ +#define SPIM137_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ +#define SPIM137_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ +#define SPIM137_PRESCALER_PRESENT 1 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ +#define SPIM137_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ +#define SPIM137_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ +#define SPIM137_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ +#define SPIM137_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ + +/*UART with EasyDMA*/ +#define UARTE_PRESENT 1 +#define UARTE_COUNT 9 + +#define UARTE120_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE120_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE120_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE120_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE120_CORE_FREQUENCY 320 /*!< Peripheral clock frequency is 320 MHz. */ +#define UARTE120_CORE_CLOCK_320 1 /*!< (unspecified) */ +#define UARTE120_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE120_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE130_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE130_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE130_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE130_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE130_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE131_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE131_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE131_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE131_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE131_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE132_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE132_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE132_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE132_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE132_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE133_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE133_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE133_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE133_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE133_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE134_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE134_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE134_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE134_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE134_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE135_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE135_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE135_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE135_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE135_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE136_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE136_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE136_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE136_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE136_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define UARTE137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define UARTE137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define UARTE137_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ +#define UARTE137_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ +#define UARTE137_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ +#define UARTE137_CORE_CLOCK_16 1 /*!< (unspecified) */ +#define UARTE137_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ +#define UARTE137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*GPIO Port*/ +#define GPIO_PRESENT 1 +#define GPIO_COUNT 10 + +#define P0_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P0_PIN_NUM_MAX 12 /*!< (unspecified) */ +#define P0_PIN_NUM_SIZE 13 /*!< (unspecified) */ +#define P0_FEATURE_PINS_PRESENT 0x00001FFFUL /*!< (unspecified) */ +#define P0_DRIVECTRL 0 /*!< (unspecified) */ +#define P0_RETAIN 1 /*!< (unspecified) */ +#define P0_PWRCTRL 0 /*!< (unspecified) */ +#define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P0_BIASCTRL 0 /*!< (unspecified) */ + +#define P1_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P1_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P1_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P1_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P1_DRIVECTRL 0 /*!< (unspecified) */ +#define P1_RETAIN 1 /*!< (unspecified) */ +#define P1_PWRCTRL 0 /*!< (unspecified) */ +#define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P1_BIASCTRL 0 /*!< (unspecified) */ + +#define P2_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ +#define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ +#define P2_FEATURE_PINS_PRESENT 0x00000FFFUL /*!< (unspecified) */ +#define P2_DRIVECTRL 0 /*!< (unspecified) */ +#define P2_RETAIN 1 /*!< (unspecified) */ +#define P2_PWRCTRL 0 /*!< (unspecified) */ +#define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P2_BIASCTRL 0 /*!< (unspecified) */ + +#define P6_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P6_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P6_PIN_NUM_MAX 13 /*!< (unspecified) */ +#define P6_PIN_NUM_SIZE 14 /*!< (unspecified) */ +#define P6_FEATURE_PINS_PRESENT 0x00003FFFUL /*!< (unspecified) */ +#define P6_DRIVECTRL 1 /*!< (unspecified) */ +#define P6_RETAIN 1 /*!< (unspecified) */ +#define P6_PWRCTRL 0 /*!< (unspecified) */ +#define P6_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P6_BIASCTRL 0 /*!< (unspecified) */ + +#define P8_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P8_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P8_PIN_NUM_MAX 4 /*!< (unspecified) */ +#define P8_PIN_NUM_SIZE 5 /*!< (unspecified) */ +#define P8_FEATURE_PINS_PRESENT 0x0000001FUL /*!< (unspecified) */ +#define P8_DRIVECTRL 1 /*!< (unspecified) */ +#define P8_RETAIN 1 /*!< (unspecified) */ +#define P8_PWRCTRL 0 /*!< (unspecified) */ +#define P8_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P8_BIASCTRL 0 /*!< (unspecified) */ + +#define P9_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P9_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P9_PIN_NUM_MAX 5 /*!< (unspecified) */ +#define P9_PIN_NUM_SIZE 6 /*!< (unspecified) */ +#define P9_FEATURE_PINS_PRESENT 0x0000003FUL /*!< (unspecified) */ +#define P9_DRIVECTRL 0 /*!< (unspecified) */ +#define P9_RETAIN 1 /*!< (unspecified) */ +#define P9_PWRCTRL 1 /*!< (unspecified) */ +#define P9_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P9_BIASCTRL 0 /*!< (unspecified) */ + +#define P10_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P10_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P10_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P10_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P10_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P10_DRIVECTRL 0 /*!< (unspecified) */ +#define P10_RETAIN 1 /*!< (unspecified) */ +#define P10_PWRCTRL 0 /*!< (unspecified) */ +#define P10_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P10_BIASCTRL 0 /*!< (unspecified) */ + +#define P11_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P11_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P11_PIN_NUM_MAX 7 /*!< (unspecified) */ +#define P11_PIN_NUM_SIZE 8 /*!< (unspecified) */ +#define P11_FEATURE_PINS_PRESENT 0x000000FFUL /*!< (unspecified) */ +#define P11_DRIVECTRL 0 /*!< (unspecified) */ +#define P11_RETAIN 1 /*!< (unspecified) */ +#define P11_PWRCTRL 0 /*!< (unspecified) */ +#define P11_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P11_BIASCTRL 0 /*!< (unspecified) */ + +#define P12_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P12_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P12_PIN_NUM_MAX 2 /*!< (unspecified) */ +#define P12_PIN_NUM_SIZE 3 /*!< (unspecified) */ +#define P12_FEATURE_PINS_PRESENT 0x00000007UL /*!< (unspecified) */ +#define P12_DRIVECTRL 0 /*!< (unspecified) */ +#define P12_RETAIN 1 /*!< (unspecified) */ +#define P12_PWRCTRL 0 /*!< (unspecified) */ +#define P12_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P12_BIASCTRL 0 /*!< (unspecified) */ + +#define P13_CTRLSEL_MAP1 1 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP2 0 /*!< (unspecified) */ +#define P13_CTRLSEL_MAP3 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MIN 0 /*!< (unspecified) */ +#define P13_PIN_NUM_MAX 3 /*!< (unspecified) */ +#define P13_PIN_NUM_SIZE 4 /*!< (unspecified) */ +#define P13_FEATURE_PINS_PRESENT 0x0000000FUL /*!< (unspecified) */ +#define P13_DRIVECTRL 0 /*!< (unspecified) */ +#define P13_RETAIN 1 /*!< (unspecified) */ +#define P13_PWRCTRL 0 /*!< (unspecified) */ +#define P13_PIN_OWNER_SEC 0 /*!< (unspecified) */ +#define P13_BIASCTRL 0 /*!< (unspecified) */ + +/*Analog to Digital Converter*/ +#define SAADC_PRESENT 1 +#define SAADC_COUNT 1 + +#define SAADC_PSEL_V2 1 /*!< (unspecified) */ +#define SAADC_TASKS_CALIBRATEGAIN 0 /*!< (unspecified) */ +#define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ + +/*Comparator*/ +#define COMP_PRESENT 1 +#define COMP_COUNT 1 + +/*Low-power comparator*/ +#define LPCOMP_PRESENT 1 +#define LPCOMP_COUNT 1 + +/*Temperature Sensor*/ +#define TEMP_PRESENT 1 +#define TEMP_COUNT 1 + +/*Inter-IC Sound*/ +#define I2S_PRESENT 1 +#define I2S_COUNT 2 + +/*Pulse Density Modulation (Digital Microphone) Interface*/ +#define PDM_PRESENT 1 +#define PDM_COUNT 1 + +#define PDM_SAMPLE16 1 /*!< (unspecified) */ +#define PDM_SAMPLE48 0 /*!< (unspecified) */ +#define PDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*Quadrature Decoder*/ +#define QDEC_PRESENT 1 +#define QDEC_COUNT 2 + +/*I2C compatible Two-Wire Master Interface with EasyDMA*/ +#define TWIM_PRESENT 1 +#define TWIM_COUNT 8 + +#define TWIM130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIM137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIM137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIM137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/*I2C compatible Two-Wire Slave Interface with EasyDMA*/ +#define TWIS_PRESENT 1 +#define TWIS_COUNT 8 + +#define TWIS130_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS130_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS130_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS131_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS131_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS131_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS132_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS132_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS132_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS133_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS133_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS133_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS134_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS134_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS134_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS135_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS135_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS135_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS136_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS136_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS136_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +#define TWIS137_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_MAX 14 /*!< (unspecified) */ +#define TWIS137_EASYDMA_MAXCNT_SIZE 15 /*!< (unspecified) */ +#define TWIS137_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ + +/* ============================================= SPU020 Split Security Features ============================================== */ +/** + * @brief Indexes in SPU020.FEATURES controlling access permissions of features with split security + */ +typedef enum { + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_0 = 0, /*!< Index of access permissions for channel 0 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_1 = 1, /*!< Index of access permissions for channel 1 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_2 = 2, /*!< Index of access permissions for channel 2 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_3 = 3, /*!< Index of access permissions for channel 3 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_4 = 4, /*!< Index of access permissions for channel 4 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_5 = 5, /*!< Index of access permissions for channel 5 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_6 = 6, /*!< Index of access permissions for channel 6 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_CH_7 = 7, /*!< Index of access permissions for channel 7 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_INTERRUPT_0 = 24, /*!< Index of access permissions for interrupt 0 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_IPCT_INTERRUPT_1 = 25, /*!< Index of access permissions for interrupt 1 of IPCT */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_0 = 32, /*!< Index of access permissions for channel 0 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_1 = 33, /*!< Index of access permissions for channel 1 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_2 = 34, /*!< Index of access permissions for channel 2 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_3 = 35, /*!< Index of access permissions for channel 3 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_4 = 36, /*!< Index of access permissions for channel 4 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_5 = 37, /*!< Index of access permissions for channel 5 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_6 = 38, /*!< Index of access permissions for channel 6 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_7 = 39, /*!< Index of access permissions for channel 7 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_8 = 40, /*!< Index of access permissions for channel 8 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_9 = 41, /*!< Index of access permissions for channel 9 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_10 = 42, /*!< Index of access permissions for channel 10 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_11 = 43, /*!< Index of access permissions for channel 11 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_12 = 44, /*!< Index of access permissions for channel 12 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_13 = 45, /*!< Index of access permissions for channel 13 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_14 = 46, /*!< Index of access permissions for channel 14 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_15 = 47, /*!< Index of access permissions for channel 15 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_16 = 48, /*!< Index of access permissions for channel 16 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_17 = 49, /*!< Index of access permissions for channel 17 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_18 = 50, /*!< Index of access permissions for channel 18 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_19 = 51, /*!< Index of access permissions for channel 19 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_20 = 52, /*!< Index of access permissions for channel 20 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_21 = 53, /*!< Index of access permissions for channel 21 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_22 = 54, /*!< Index of access permissions for channel 22 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CH_23 = 55, /*!< Index of access permissions for channel 23 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_0 = 56, /*!< Index of access permissions for channel group 0 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_1 = 57, /*!< Index of access permissions for channel group 1 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_2 = 58, /*!< Index of access permissions for channel group 2 of DPPIC020 */ + NRF_RADIOCORE_SPU020_FEATURES_DPPIC020_CHG_3 = 59, /*!< Index of access permissions for channel group 3 of DPPIC020 */ +} NRF_RADIOCORE_SPU020_FEATURES_ENUM_t; + +/* ============================================= SPU030 Split Security Features ============================================== */ +/** + * @brief Indexes in SPU030.FEATURES controlling access permissions of features with split security + */ +typedef enum { + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_0 = 32, /*!< Index of access permissions for channel 0 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_1 = 33, /*!< Index of access permissions for channel 1 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_2 = 34, /*!< Index of access permissions for channel 2 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_3 = 35, /*!< Index of access permissions for channel 3 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_4 = 36, /*!< Index of access permissions for channel 4 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_5 = 37, /*!< Index of access permissions for channel 5 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_6 = 38, /*!< Index of access permissions for channel 6 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_7 = 39, /*!< Index of access permissions for channel 7 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_8 = 40, /*!< Index of access permissions for channel 8 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_9 = 41, /*!< Index of access permissions for channel 9 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_10 = 42, /*!< Index of access permissions for channel 10 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_11 = 43, /*!< Index of access permissions for channel 11 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_12 = 44, /*!< Index of access permissions for channel 12 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_13 = 45, /*!< Index of access permissions for channel 13 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_14 = 46, /*!< Index of access permissions for channel 14 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CH_15 = 47, /*!< Index of access permissions for channel 15 of DPPIC030 */ + NRF_RADIOCORE_SPU030_FEATURES_DPPIC030_CHG_0 = 56, /*!< Index of access permissions for channel group 0 of DPPIC030 */ +} NRF_RADIOCORE_SPU030_FEATURES_ENUM_t; + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_RADIOCORE_PERIPHERALS_H */ + diff --git a/mdk/nrf9230_enga_radiocore_vectors.h b/mdk/nrf9230_enga_radiocore_vectors.h new file mode 100644 index 000000000..9822f8403 --- /dev/null +++ b/mdk/nrf9230_enga_radiocore_vectors.h @@ -0,0 +1,708 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_VECTORS_H_ +#define NRF_DEVICE_VECTORS_H_ + +/*--------------------------------------------------------------------------- + Exception / Interrupt Handler + *---------------------------------------------------------------------------*/ +/* Exceptions */ +void Reset_Handler (void); +__WEAK void NMI_Handler(void) +{ + while(1); +} + +__WEAK void HardFault_Handler(void) +{ + while(1); +} + +__WEAK void MemoryManagement_Handler(void) +{ + while(1); +} + +__WEAK void BusFault_Handler(void) +{ + while(1); +} + +__WEAK void UsageFault_Handler(void) +{ + while(1); +} + +__WEAK void SecureFault_Handler(void) +{ + while(1); +} + +__WEAK void SVC_Handler(void) +{ + while(1); +} + +__WEAK void DebugMon_Handler(void) +{ + while(1); +} + +__WEAK void PendSV_Handler(void) +{ + while(1); +} + +__WEAK void SysTick_Handler(void) +{ + while(1); +} + +/* Device specific interrupt handlers */ + __HANDLER("Default_Handler") void SPU000_IRQHandler (void); + __HANDLER("Default_Handler") void MPC_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA_IRQHandler (void); + __HANDLER("Default_Handler") void SPU010_IRQHandler (void); + __HANDLER("Default_Handler") void WDT010_IRQHandler (void); + __HANDLER("Default_Handler") void WDT011_IRQHandler (void); + __HANDLER("Default_Handler") void SPU020_IRQHandler (void); + __HANDLER("Default_Handler") void EGU020_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER020_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER021_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER022_IRQHandler (void); + __HANDLER("Default_Handler") void RTC_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_0_IRQHandler (void); + __HANDLER("Default_Handler") void RADIO_1_IRQHandler (void); + __HANDLER("Default_Handler") void SPU030_IRQHandler (void); + __HANDLER("Default_Handler") void VPR_IRQHandler (void); + __HANDLER("Default_Handler") void AAR030_CCM030_IRQHandler (void); + __HANDLER("Default_Handler") void ECB030_IRQHandler (void); + __HANDLER("Default_Handler") void AAR031_CCM031_IRQHandler (void); + __HANDLER("Default_Handler") void ECB031_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT_0_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT_1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI0_IRQHandler (void); + __HANDLER("Default_Handler") void SWI1_IRQHandler (void); + __HANDLER("Default_Handler") void SWI2_IRQHandler (void); + __HANDLER("Default_Handler") void SWI3_IRQHandler (void); + __HANDLER("Default_Handler") void SWI4_IRQHandler (void); + __HANDLER("Default_Handler") void SWI5_IRQHandler (void); + __HANDLER("Default_Handler") void SWI6_IRQHandler (void); + __HANDLER("Default_Handler") void SWI7_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_0_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_1_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_2_IRQHandler (void); + __HANDLER("Default_Handler") void BELLBOARD_3_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE130_1_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_0_IRQHandler (void); + __HANDLER("Default_Handler") void GPIOTE131_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_0_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_1_IRQHandler (void); + __HANDLER("Default_Handler") void GRTC_2_IRQHandler (void); + __HANDLER("Default_Handler") void TBM_IRQHandler (void); + __HANDLER("Default_Handler") void USBHS_IRQHandler (void); + __HANDLER("Default_Handler") void EXMIF_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT120_0_IRQHandler (void); + __HANDLER("Default_Handler") void I3C120_IRQHandler (void); + __HANDLER("Default_Handler") void VPR121_IRQHandler (void); + __HANDLER("Default_Handler") void CAN120_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA120_IRQHandler (void); + __HANDLER("Default_Handler") void CAN121_IRQHandler (void); + __HANDLER("Default_Handler") void MVDMA121_IRQHandler (void); + __HANDLER("Default_Handler") void I3C121_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER120_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER121_IRQHandler (void); + __HANDLER("Default_Handler") void PWM120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIS120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM120_UARTE120_IRQHandler (void); + __HANDLER("Default_Handler") void SPIM121_IRQHandler (void); + __HANDLER("Default_Handler") void VPR130_IRQHandler (void); + __HANDLER("Default_Handler") void IPCT130_0_IRQHandler (void); + __HANDLER("Default_Handler") void RTC130_IRQHandler (void); + __HANDLER("Default_Handler") void RTC131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT131_IRQHandler (void); + __HANDLER("Default_Handler") void WDT132_IRQHandler (void); + __HANDLER("Default_Handler") void EGU130_IRQHandler (void); + __HANDLER("Default_Handler") void SAADC_IRQHandler (void); + __HANDLER("Default_Handler") void COMP_LPCOMP_IRQHandler (void); + __HANDLER("Default_Handler") void TEMP_IRQHandler (void); + __HANDLER("Default_Handler") void I2S130_IRQHandler (void); + __HANDLER("Default_Handler") void PDM_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC130_IRQHandler (void); + __HANDLER("Default_Handler") void QDEC131_IRQHandler (void); + __HANDLER("Default_Handler") void I2S131_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER130_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER131_IRQHandler (void); + __HANDLER("Default_Handler") void PWM130_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL0_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL1_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER132_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER133_IRQHandler (void); + __HANDLER("Default_Handler") void PWM131_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL2_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL3_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER134_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER135_IRQHandler (void); + __HANDLER("Default_Handler") void PWM132_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL4_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL5_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER136_IRQHandler (void); + __HANDLER("Default_Handler") void TIMER137_IRQHandler (void); + __HANDLER("Default_Handler") void PWM133_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL6_IRQHandler (void); + __HANDLER("Default_Handler") void SERIAL7_IRQHandler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +__VECTOR_TABLE_ATTRIBUTE const VECTOR_TABLE_Type __VECTOR_TABLE[] = { + (VECTOR_TABLE_Type)(__STACK_BASE), +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemoryManagement_Handler, + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + 0, + 0, + 0, + SVC_Handler, + DebugMon_Handler, + 0, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + SPU000_IRQHandler, + MPC_IRQHandler, + 0, + MVDMA_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SPU010_IRQHandler, + 0, + 0, + WDT010_IRQHandler, + WDT011_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SPU020_IRQHandler, + 0, + 0, + 0, + 0, + EGU020_IRQHandler, + 0, + 0, + TIMER020_IRQHandler, + TIMER021_IRQHandler, + TIMER022_IRQHandler, + RTC_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + 0, + 0, + SPU030_IRQHandler, + 0, + 0, + 0, + VPR_IRQHandler, + 0, + 0, + 0, + 0, + 0, + AAR030_CCM030_IRQHandler, + ECB030_IRQHandler, + AAR031_CCM031_IRQHandler, + ECB031_IRQHandler, + 0, + 0, + IPCT_0_IRQHandler, + IPCT_1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SWI0_IRQHandler, + SWI1_IRQHandler, + SWI2_IRQHandler, + SWI3_IRQHandler, + SWI4_IRQHandler, + SWI5_IRQHandler, + SWI6_IRQHandler, + SWI7_IRQHandler, + BELLBOARD_0_IRQHandler, + BELLBOARD_1_IRQHandler, + BELLBOARD_2_IRQHandler, + BELLBOARD_3_IRQHandler, + 0, + 0, + 0, + 0, + GPIOTE130_0_IRQHandler, + GPIOTE130_1_IRQHandler, + GPIOTE131_0_IRQHandler, + GPIOTE131_1_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TBM_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + USBHS_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + EXMIF_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT120_0_IRQHandler, + 0, + I3C120_IRQHandler, + VPR121_IRQHandler, + 0, + 0, + 0, + CAN120_IRQHandler, + MVDMA120_IRQHandler, + 0, + CAN121_IRQHandler, + MVDMA121_IRQHandler, + 0, + I3C121_IRQHandler, + 0, + 0, + 0, + TIMER120_IRQHandler, + TIMER121_IRQHandler, + PWM120_IRQHandler, + SPIS120_IRQHandler, + SPIM120_UARTE120_IRQHandler, + SPIM121_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + VPR130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + IPCT130_0_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + RTC130_IRQHandler, + RTC131_IRQHandler, + 0, + WDT131_IRQHandler, + WDT132_IRQHandler, + EGU130_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + SAADC_IRQHandler, + COMP_LPCOMP_IRQHandler, + TEMP_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + I2S130_IRQHandler, + PDM_IRQHandler, + QDEC130_IRQHandler, + QDEC131_IRQHandler, + 0, + I2S131_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER130_IRQHandler, + TIMER131_IRQHandler, + PWM130_IRQHandler, + SERIAL0_IRQHandler, + SERIAL1_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER132_IRQHandler, + TIMER133_IRQHandler, + PWM131_IRQHandler, + SERIAL2_IRQHandler, + SERIAL3_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER134_IRQHandler, + TIMER135_IRQHandler, + PWM132_IRQHandler, + SERIAL4_IRQHandler, + SERIAL5_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TIMER136_IRQHandler, + TIMER137_IRQHandler, + PWM133_IRQHandler, + SERIAL6_IRQHandler, + SERIAL7_IRQHandler, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +__STATIC_FORCEINLINE void NRFPreInit() +{ +} + +#endif diff --git a/mdk/nrf9230_enga_types.h b/mdk/nrf9230_enga_types.h new file mode 100644 index 000000000..18ebc81f2 --- /dev/null +++ b/mdk/nrf9230_enga_types.h @@ -0,0 +1,105221 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_TYPES_H +#define NRF9230_ENGA_TYPES_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include "compiler_abstraction.h" + + +/* ============================================ Include required type specifiers ============================================= */ + +#ifndef __I + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif +#endif +#ifndef __O + #define __O volatile /*!< Defines 'write only' permissions */ +#endif +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +/* The following defines should be used for structure members */ +#ifndef __IM + #define __IM volatile const /*!< Defines 'read only' structure member permissions */ +#endif +#ifndef __OM + #define __OM volatile /*!< Defines 'write only' structure member permissions */ +#endif +#ifndef __IOM + #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ +#endif + +/* ======================================================= Domain IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_DOMAIN_APPLICATION = 2, /*!< Application Core */ + NRF_DOMAIN_RADIOCORE = 3, /*!< Radio Core */ + NRF_DOMAIN_GLOBALFAST = 12, /*!< Global Domain - Fast clock domain */ + NRF_DOMAIN_GLOBALSLOW = 13, /*!< Global Domain - Slow clock domain */ + NRF_DOMAIN_GLOBAL = 15, /*!< Global Domain */ +} NRF_DOMAINID_Type; + +/* ====================================================== Processor IDs ====================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_PROCESSOR_APPLICATION = 2, /*!< Application Core Processor */ + NRF_PROCESSOR_RADIOCORE = 3, /*!< Radio Core Processor */ + NRF_PROCESSOR_PPR = 13, /*!< Peripheral Processor */ + NRF_PROCESSOR_FLPR = 14, /*!< Fast Lightweight Processor */ +} NRF_PROCESSORID_Type; + +/* ======================================================== Owner IDs ======================================================== */ +/** + * @brief (unspecified) + */ +typedef enum { + NRF_OWNER_NONE = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_GLOBAL = 0, /*!< Used to denote that ownership is not enforced */ + NRF_OWNER_APPLICATION = 2, /*!< Application Core */ + NRF_OWNER_RADIOCORE = 3, /*!< Radio Core */ +} NRF_OWNERID_Type; + + +/* ========================================= Start of section using anonymous unions ========================================= */ + +#include "compiler_abstraction.h" + +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Unsupported compiler type +#endif + +/* =========================================================================================================================== */ +/* ================ Peripherals Section ================ */ +/* =========================================================================================================================== */ + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ====================================================== Struct AAR_IN ====================================================== */ +/** + * @brief IN [AAR_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer */ +} NRF_AAR_IN_Type; /*!< Size = 4 (0x004) */ + +/* AAR_IN_PTR: Input pointer */ + #define AAR_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Points to a job list containing AAR data structure */ + #define AAR_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define AAR_IN_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct AAR_OUT ====================================================== */ +/** + * @brief OUT [AAR_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Number of bytes transferred in the last transaction */ +} NRF_AAR_OUT_Type; /*!< Size = 8 (0x008) */ + +/* AAR_OUT_PTR: Output pointer */ + #define AAR_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define AAR_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define AAR_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* AAR_OUT_AMOUNT: Number of bytes transferred in the last transaction */ + #define AAR_OUT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..7 : Number of bytes written to memory after triggering the START task. */ + #define AAR_OUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Msk (0xFFUL << AAR_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Min (0x01UL) /*!< Min value of AMOUNT field. */ + #define AAR_OUT_AMOUNT_AMOUNT_Max (0xFFUL) /*!< Max size of AMOUNT field. */ + + +/* ======================================================= Struct AAR ======================================================== */ +/** + * @brief Accelerated Address Resolver + */ + typedef struct { /*!< AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified in + the IRK data structure*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop resolving addresses */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[29]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ + __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ + __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ + __IM uint32_t RESERVED3[94]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IM uint32_t RESERVED5; + __IOM uint32_t MAXRESOLVED; /*!< (@ 0x00000508) Maximum number of IRKs to resolve */ + __IM uint32_t RESERVED6[9]; + __IOM NRF_AAR_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IM uint32_t RESERVED7; + __IOM NRF_AAR_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + } NRF_AAR_Type; /*!< Size = 1344 (0x540) */ + +/* AAR_TASKS_START: Start resolving addresses based on IRKs specified in the IRK data structure */ + #define AAR_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ + #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define AAR_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* AAR_TASKS_STOP: Stop resolving addresses */ + #define AAR_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop resolving addresses */ + #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define AAR_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* AAR_SUBSCRIBE_START: Subscribe configuration for task START */ + #define AAR_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define AAR_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* AAR_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define AAR_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define AAR_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* AAR_EVENTS_END: Address resolution procedure complete */ + #define AAR_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Address resolution procedure complete */ + #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_EVENTS_RESOLVED: Address resolved */ + #define AAR_EVENTS_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESOLVED register. */ + +/* EVENTS_RESOLVED @Bit 0 : Address resolved */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of + EVENTS_RESOLVED field.*/ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESOLVED field. */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_EVENTS_NOTRESOLVED: Address not resolved */ + #define AAR_EVENTS_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NOTRESOLVED register. */ + +/* EVENTS_NOTRESOLVED @Bit 0 : Address not resolved */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask + of EVENTS_NOTRESOLVED field.*/ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_NOTRESOLVED field. */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0x0UL) /*!< Event not generated */ + #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (0x1UL) /*!< Event generated */ + + +/* AAR_PUBLISH_END: Publish configuration for event END */ + #define AAR_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_PUBLISH_RESOLVED: Publish configuration for event RESOLVED */ + #define AAR_PUBLISH_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESOLVED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RESOLVED will publish to */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_RESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_RESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_RESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_PUBLISH_NOTRESOLVED: Publish configuration for event NOTRESOLVED */ + #define AAR_PUBLISH_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NOTRESOLVED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event NOTRESOLVED will publish to */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* AAR_INTENSET: Enable interrupt */ + #define AAR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 0 : Write '1' to enable interrupt for event END */ + #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ + #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define AAR_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define AAR_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define AAR_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESOLVED @Bit 1 : Write '1' to enable interrupt for event RESOLVED */ + #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Min (0x0UL) /*!< Min enumerator value of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Max (0x1UL) /*!< Max enumerator value of RESOLVED field. */ + #define AAR_INTENSET_RESOLVED_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NOTRESOLVED @Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ + #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of NOTRESOLVED field. */ + #define AAR_INTENSET_NOTRESOLVED_Set (0x1UL) /*!< Enable */ + #define AAR_INTENSET_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENSET_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AAR_INTENCLR: Disable interrupt */ + #define AAR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 0 : Write '1' to disable interrupt for event END */ + #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ + #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define AAR_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define AAR_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define AAR_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESOLVED @Bit 1 : Write '1' to disable interrupt for event RESOLVED */ + #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Min (0x0UL) /*!< Min enumerator value of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Max (0x1UL) /*!< Max enumerator value of RESOLVED field. */ + #define AAR_INTENCLR_RESOLVED_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_RESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_RESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NOTRESOLVED @Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ + #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of NOTRESOLVED field. */ + #define AAR_INTENCLR_NOTRESOLVED_Clear (0x1UL) /*!< Disable */ + #define AAR_INTENCLR_NOTRESOLVED_Disabled (0x0UL) /*!< Read: Disabled */ + #define AAR_INTENCLR_NOTRESOLVED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* AAR_ENABLE: Enable AAR */ + #define AAR_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable AAR */ + #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Max (0x3UL) /*!< Max enumerator value of ENABLE field. */ + #define AAR_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define AAR_ENABLE_ENABLE_Enabled (0x3UL) /*!< Enable */ + + +/* AAR_MAXRESOLVED: Maximum number of IRKs to resolve */ + #define AAR_MAXRESOLVED_ResetValue (0x00000001UL) /*!< Reset value of MAXRESOLVED register. */ + +/* MAXRESOLVED @Bits 0..11 : The maximum number of IRKs to resolve */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Pos (0UL) /*!< Position of MAXRESOLVED field. */ + #define AAR_MAXRESOLVED_MAXRESOLVED_Msk (0xFFFUL << AAR_MAXRESOLVED_MAXRESOLVED_Pos) /*!< Bit mask of MAXRESOLVED field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ABB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct ABB ======================================================== */ +/** + * @brief ABB peripheral + */ + typedef struct { /*!< ABB Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) ABB status */ + __IM uint32_t RESERVED1[31]; + __IOM uint32_t MODE; /*!< (@ 0x00000480) ABB control */ + } NRF_ABB_Type; /*!< Size = 1156 (0x484) */ + +/* ABB_STATUS: ABB status */ + #define ABB_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* OPPOINT @Bits 0..1 : The current ABB operating point */ + #define ABB_STATUS_OPPOINT_Pos (0UL) /*!< Position of OPPOINT field. */ + #define ABB_STATUS_OPPOINT_Msk (0x3UL << ABB_STATUS_OPPOINT_Pos) /*!< Bit mask of OPPOINT field. */ + #define ABB_STATUS_OPPOINT_Min (0x0UL) /*!< Min enumerator value of OPPOINT field. */ + #define ABB_STATUS_OPPOINT_Max (0x3UL) /*!< Max enumerator value of OPPOINT field. */ + #define ABB_STATUS_OPPOINT_OpPoint0V4 (0x0UL) /*!< Operating point 0.4V */ + #define ABB_STATUS_OPPOINT_OpPoint0V5 (0x1UL) /*!< Operating point 0.5V */ + #define ABB_STATUS_OPPOINT_OpPoint0V6 (0x2UL) /*!< Operating point 0.6V */ + #define ABB_STATUS_OPPOINT_OpPoint0V8 (0x3UL) /*!< Operating point 0.8V */ + +/* EN @Bit 4 : The ABB enable status. */ + #define ABB_STATUS_EN_Pos (4UL) /*!< Position of EN field. */ + #define ABB_STATUS_EN_Msk (0x1UL << ABB_STATUS_EN_Pos) /*!< Bit mask of EN field. */ + #define ABB_STATUS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ABB_STATUS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ABB_STATUS_EN_Disabled (0x0UL) /*!< ABB disabled */ + #define ABB_STATUS_EN_Enabled (0x1UL) /*!< ABB enabled */ + +/* LOCKED @Bit 5 : The ABB lock status. */ + #define ABB_STATUS_LOCKED_Pos (5UL) /*!< Position of LOCKED field. */ + #define ABB_STATUS_LOCKED_Msk (0x1UL << ABB_STATUS_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define ABB_STATUS_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define ABB_STATUS_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define ABB_STATUS_LOCKED_NotLocked (0x0UL) /*!< Not locked */ + #define ABB_STATUS_LOCKED_Locked (0x1UL) /*!< Locked. */ + + +/* ABB_MODE: ABB control */ + #define ABB_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* OPPOINT @Bits 0..2 : The ABB operating point. */ + #define ABB_MODE_OPPOINT_Pos (0UL) /*!< Position of OPPOINT field. */ + #define ABB_MODE_OPPOINT_Msk (0x7UL << ABB_MODE_OPPOINT_Pos) /*!< Bit mask of OPPOINT field. */ + #define ABB_MODE_OPPOINT_Min (0x0UL) /*!< Min enumerator value of OPPOINT field. */ + #define ABB_MODE_OPPOINT_Max (0x4UL) /*!< Max enumerator value of OPPOINT field. */ + #define ABB_MODE_OPPOINT_Auto (0x0UL) /*!< The peripheral controls the operating point automatically based on + request from the master ABB controller.*/ + #define ABB_MODE_OPPOINT_OpPoint0V4 (0x1UL) /*!< Force the operating point to 0.4V */ + #define ABB_MODE_OPPOINT_OpPoint0V5 (0x2UL) /*!< Force the operating point to 0.5V */ + #define ABB_MODE_OPPOINT_OpPoint0V6 (0x3UL) /*!< Force the operating point to 0.6V */ + #define ABB_MODE_OPPOINT_OpPoint0V8 (0x4UL) /*!< Force the operating point to 0.8V */ + +/* ABBEN @Bits 4..5 : Enable ABB. */ + #define ABB_MODE_ABBEN_Pos (4UL) /*!< Position of ABBEN field. */ + #define ABB_MODE_ABBEN_Msk (0x3UL << ABB_MODE_ABBEN_Pos) /*!< Bit mask of ABBEN field. */ + #define ABB_MODE_ABBEN_Min (0x0UL) /*!< Min enumerator value of ABBEN field. */ + #define ABB_MODE_ABBEN_Max (0x2UL) /*!< Max enumerator value of ABBEN field. */ + #define ABB_MODE_ABBEN_Auto (0x0UL) /*!< The peripheral controls the ABB enable automatically based on + request.*/ + #define ABB_MODE_ABBEN_Enable (0x1UL) /*!< Force enable ABB */ + #define ABB_MODE_ABBEN_Disable (0x2UL) /*!< Force disable ABB */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ATBFUNNEL ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ==================================================== Struct ATBFUNNEL ===================================================== */ +/** + * @brief ATB funnel module + */ + typedef struct { /*!< ATBFUNNEL Structure */ + __IOM uint32_t CTRLREG; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming of ID + filtering for master port 0.*/ + __IOM uint32_t PRIORITYCTRLREG; /*!< (@ 0x00000004) The Priority_Ctrl_Reg register defines the order in + which inputs are selected. Each 3-bit field is a + priority for each particular slave interface.*/ + __IM uint32_t RESERVED[953]; + __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register performs different functions + depending on whether the access is a read or a write.*/ + __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) The ITATBCTR2 register performs different functions + depending on whether the access is a read or a write.*/ + __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register performs different functions + depending on whether the access is a read or a write.*/ + __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register performs different functions + depending on whether the access is a read or a write.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to switch + from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the + component can be directly controlled for the purposes + of integration testing and topology detection.*/ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMSET register sets + bits in the claim tag, and determines the number of + claim bits implemented.*/ + __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMCLR register sets + the bits in the claim tag to 0 and determines the + current value of the claim tag.*/ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device + registers.*/ + __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control + mechanism. This lock prevents accidental writes by code + under debug. Accesses to the extended stimulus port + registers are not affected by the lock mechanism. This + register must always be present although there might + not be any lock access control mechanism. The lock + mechanism, where present and locked, must block write + accesses to any control register, except the Lock + Access Register. For most components this covers all + registers except for the Lock Access Register.*/ + __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t RESERVED4[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with + information about the component when the Part Number + field is not recognized. The debugger can then report + this information.*/ + __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t PIDR0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ + __IOM uint32_t CIDR0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + __IOM uint32_t CIDR1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ + __IOM uint32_t CIDR2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ + __IOM uint32_t CIDR3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ + } NRF_ATBFUNNEL_Type; /*!< Size = 4096 (0x1000) */ + +/* ATBFUNNEL_CTRLREG: The IDFILTER0 register enables the programming of ID filtering for master port 0. */ + #define ATBFUNNEL_CTRLREG_ResetValue (0x00000000UL) /*!< Reset value of CTRLREG register. */ + +/* ENS0 @Bit 0 : Enable slave port 0. */ + #define ATBFUNNEL_CTRLREG_ENS0_Pos (0UL) /*!< Position of ENS0 field. */ + #define ATBFUNNEL_CTRLREG_ENS0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS0_Pos) /*!< Bit mask of ENS0 field. */ + #define ATBFUNNEL_CTRLREG_ENS0_Min (0x0UL) /*!< Min enumerator value of ENS0 field. */ + #define ATBFUNNEL_CTRLREG_ENS0_Max (0x1UL) /*!< Max enumerator value of ENS0 field. */ + #define ATBFUNNEL_CTRLREG_ENS0_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS0_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS1 @Bit 1 : Enable slave port 1. */ + #define ATBFUNNEL_CTRLREG_ENS1_Pos (1UL) /*!< Position of ENS1 field. */ + #define ATBFUNNEL_CTRLREG_ENS1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS1_Pos) /*!< Bit mask of ENS1 field. */ + #define ATBFUNNEL_CTRLREG_ENS1_Min (0x0UL) /*!< Min enumerator value of ENS1 field. */ + #define ATBFUNNEL_CTRLREG_ENS1_Max (0x1UL) /*!< Max enumerator value of ENS1 field. */ + #define ATBFUNNEL_CTRLREG_ENS1_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS1_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS2 @Bit 2 : Enable slave port 2. */ + #define ATBFUNNEL_CTRLREG_ENS2_Pos (2UL) /*!< Position of ENS2 field. */ + #define ATBFUNNEL_CTRLREG_ENS2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS2_Pos) /*!< Bit mask of ENS2 field. */ + #define ATBFUNNEL_CTRLREG_ENS2_Min (0x0UL) /*!< Min enumerator value of ENS2 field. */ + #define ATBFUNNEL_CTRLREG_ENS2_Max (0x1UL) /*!< Max enumerator value of ENS2 field. */ + #define ATBFUNNEL_CTRLREG_ENS2_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS2_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS3 @Bit 3 : Enable slave port 3. */ + #define ATBFUNNEL_CTRLREG_ENS3_Pos (3UL) /*!< Position of ENS3 field. */ + #define ATBFUNNEL_CTRLREG_ENS3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS3_Pos) /*!< Bit mask of ENS3 field. */ + #define ATBFUNNEL_CTRLREG_ENS3_Min (0x0UL) /*!< Min enumerator value of ENS3 field. */ + #define ATBFUNNEL_CTRLREG_ENS3_Max (0x1UL) /*!< Max enumerator value of ENS3 field. */ + #define ATBFUNNEL_CTRLREG_ENS3_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS3_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS4 @Bit 4 : Enable slave port 4. */ + #define ATBFUNNEL_CTRLREG_ENS4_Pos (4UL) /*!< Position of ENS4 field. */ + #define ATBFUNNEL_CTRLREG_ENS4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS4_Pos) /*!< Bit mask of ENS4 field. */ + #define ATBFUNNEL_CTRLREG_ENS4_Min (0x0UL) /*!< Min enumerator value of ENS4 field. */ + #define ATBFUNNEL_CTRLREG_ENS4_Max (0x1UL) /*!< Max enumerator value of ENS4 field. */ + #define ATBFUNNEL_CTRLREG_ENS4_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS4_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS5 @Bit 5 : Enable slave port 5. */ + #define ATBFUNNEL_CTRLREG_ENS5_Pos (5UL) /*!< Position of ENS5 field. */ + #define ATBFUNNEL_CTRLREG_ENS5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS5_Pos) /*!< Bit mask of ENS5 field. */ + #define ATBFUNNEL_CTRLREG_ENS5_Min (0x0UL) /*!< Min enumerator value of ENS5 field. */ + #define ATBFUNNEL_CTRLREG_ENS5_Max (0x1UL) /*!< Max enumerator value of ENS5 field. */ + #define ATBFUNNEL_CTRLREG_ENS5_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS5_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS6 @Bit 6 : Enable slave port 6. */ + #define ATBFUNNEL_CTRLREG_ENS6_Pos (6UL) /*!< Position of ENS6 field. */ + #define ATBFUNNEL_CTRLREG_ENS6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS6_Pos) /*!< Bit mask of ENS6 field. */ + #define ATBFUNNEL_CTRLREG_ENS6_Min (0x0UL) /*!< Min enumerator value of ENS6 field. */ + #define ATBFUNNEL_CTRLREG_ENS6_Max (0x1UL) /*!< Max enumerator value of ENS6 field. */ + #define ATBFUNNEL_CTRLREG_ENS6_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS6_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* ENS7 @Bit 7 : Enable slave port 7. */ + #define ATBFUNNEL_CTRLREG_ENS7_Pos (7UL) /*!< Position of ENS7 field. */ + #define ATBFUNNEL_CTRLREG_ENS7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS7_Pos) /*!< Bit mask of ENS7 field. */ + #define ATBFUNNEL_CTRLREG_ENS7_Min (0x0UL) /*!< Min enumerator value of ENS7 field. */ + #define ATBFUNNEL_CTRLREG_ENS7_Max (0x1UL) /*!< Max enumerator value of ENS7 field. */ + #define ATBFUNNEL_CTRLREG_ENS7_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority + selection scheme.*/ + #define ATBFUNNEL_CTRLREG_ENS7_Enabled (0x1UL) /*!< Slave port enabled. */ + +/* HT @Bits 8..11 : Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this + setting to minimize switching. When a source has nothing to transmit, then another source is selected + irrespective of the minimum number of transactions. The ATB funnel holds for the minimum hold time and one + additional transaction. The actual hold time is the register value plus 1. The maximum value that can be + entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. */ + + #define ATBFUNNEL_CTRLREG_HT_Pos (8UL) /*!< Position of HT field. */ + #define ATBFUNNEL_CTRLREG_HT_Msk (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos) /*!< Bit mask of HT field. */ + #define ATBFUNNEL_CTRLREG_HT_Min (0x0UL) /*!< Min value of HT field. */ + #define ATBFUNNEL_CTRLREG_HT_Max (0xEUL) /*!< Max size of HT field. */ + + +/* ATBFUNNEL_PRIORITYCTRLREG: The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is + a priority for each particular slave interface. */ + + #define ATBFUNNEL_PRIORITYCTRLREG_ResetValue (0x00000000UL) /*!< Reset value of PRIORITYCTRLREG register. */ + +/* PRIPORT0 @Bits 0..2 : Priority value of port number 0. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos (0UL) /*!< Position of PRIPORT0 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos) /*!< Bit mask of PRIPORT0 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Min (0x0UL) /*!< Min value of PRIPORT0 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Max (0x7UL) /*!< Max size of PRIPORT0 field. */ + +/* PRIPORT1 @Bits 3..5 : Priority value of port number 1. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos (3UL) /*!< Position of PRIPORT1 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos) /*!< Bit mask of PRIPORT1 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Min (0x0UL) /*!< Min value of PRIPORT1 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Max (0x7UL) /*!< Max size of PRIPORT1 field. */ + +/* PRIPORT2 @Bits 6..8 : Priority value of port number 2. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos (6UL) /*!< Position of PRIPORT2 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos) /*!< Bit mask of PRIPORT2 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Min (0x0UL) /*!< Min value of PRIPORT2 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Max (0x7UL) /*!< Max size of PRIPORT2 field. */ + +/* PRIPORT3 @Bits 9..11 : Priority value of port number 3. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos (9UL) /*!< Position of PRIPORT3 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos) /*!< Bit mask of PRIPORT3 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Min (0x0UL) /*!< Min value of PRIPORT3 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Max (0x7UL) /*!< Max size of PRIPORT3 field. */ + +/* PRIPORT4 @Bits 12..14 : Priority value of port number 4. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos (12UL) /*!< Position of PRIPORT4 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos) /*!< Bit mask of PRIPORT4 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Min (0x0UL) /*!< Min value of PRIPORT4 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Max (0x7UL) /*!< Max size of PRIPORT4 field. */ + +/* PRIPORT5 @Bits 15..17 : Priority value of port number 5. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos (15UL) /*!< Position of PRIPORT5 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos) /*!< Bit mask of PRIPORT5 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Min (0x0UL) /*!< Min value of PRIPORT5 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Max (0x7UL) /*!< Max size of PRIPORT5 field. */ + +/* PRIPORT6 @Bits 18..20 : Priority value of port number 6. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos (18UL) /*!< Position of PRIPORT6 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos) /*!< Bit mask of PRIPORT6 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Min (0x0UL) /*!< Min value of PRIPORT6 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Max (0x7UL) /*!< Max size of PRIPORT6 field. */ + +/* PRIPORT7 @Bits 21..23 : Priority value of port number 7. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos (21UL) /*!< Position of PRIPORT7 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos) /*!< Bit mask of PRIPORT7 + field.*/ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Min (0x0UL) /*!< Min value of PRIPORT7 field. */ + #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Max (0x7UL) /*!< Max size of PRIPORT7 field. */ + + +/* ATBFUNNEL_ITATBDATA0: The ITATBDATA0 register performs different functions depending on whether the access is a read or a + write. */ + + #define ATBFUNNEL_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register. */ + +/* ATDATA0 @Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA0_Pos (0UL) /*!< Position of ATDATA0 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA0_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA0_Pos) /*!< Bit mask of ATDATA0 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA0_Min (0x0UL) /*!< Min enumerator value of ATDATA0 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA0_Max (0x1UL) /*!< Max enumerator value of ATDATA0 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA0_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA0_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA1 @Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA1_Pos (1UL) /*!< Position of ATDATA1 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA1_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA1_Pos) /*!< Bit mask of ATDATA1 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA1_Min (0x0UL) /*!< Min enumerator value of ATDATA1 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA1_Max (0x1UL) /*!< Max enumerator value of ATDATA1 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA1_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA1_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA2 @Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA2_Pos (2UL) /*!< Position of ATDATA2 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA2_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA2_Pos) /*!< Bit mask of ATDATA2 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA2_Min (0x0UL) /*!< Min enumerator value of ATDATA2 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA2_Max (0x1UL) /*!< Max enumerator value of ATDATA2 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA2_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA2_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA3 @Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA3_Pos (3UL) /*!< Position of ATDATA3 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA3_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA3_Pos) /*!< Bit mask of ATDATA3 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA3_Min (0x0UL) /*!< Min enumerator value of ATDATA3 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA3_Max (0x1UL) /*!< Max enumerator value of ATDATA3 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA3_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA3_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA4 @Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA4_Pos (4UL) /*!< Position of ATDATA4 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA4_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA4_Pos) /*!< Bit mask of ATDATA4 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA4_Min (0x0UL) /*!< Min enumerator value of ATDATA4 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA4_Max (0x1UL) /*!< Max enumerator value of ATDATA4 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA4_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA4_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA5 @Bit 5 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA5_Pos (5UL) /*!< Position of ATDATA5 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA5_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA5_Pos) /*!< Bit mask of ATDATA5 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA5_Min (0x0UL) /*!< Min enumerator value of ATDATA5 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA5_Max (0x1UL) /*!< Max enumerator value of ATDATA5 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA5_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA5_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA6 @Bit 6 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA6_Pos (6UL) /*!< Position of ATDATA6 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA6_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA6_Pos) /*!< Bit mask of ATDATA6 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA6_Min (0x0UL) /*!< Min enumerator value of ATDATA6 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA6_Max (0x1UL) /*!< Max enumerator value of ATDATA6 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA6_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA6_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA7 @Bit 7 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA7_Pos (7UL) /*!< Position of ATDATA7 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA7_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA7_Pos) /*!< Bit mask of ATDATA7 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA7_Min (0x0UL) /*!< Min enumerator value of ATDATA7 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA7_Max (0x1UL) /*!< Max enumerator value of ATDATA7 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA7_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA7_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA8 @Bit 8 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA8_Pos (8UL) /*!< Position of ATDATA8 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA8_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA8_Pos) /*!< Bit mask of ATDATA8 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA8_Min (0x0UL) /*!< Min enumerator value of ATDATA8 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA8_Max (0x1UL) /*!< Max enumerator value of ATDATA8 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA8_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA8_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA9 @Bit 9 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA9_Pos (9UL) /*!< Position of ATDATA9 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA9_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA9_Pos) /*!< Bit mask of ATDATA9 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA9_Min (0x0UL) /*!< Min enumerator value of ATDATA9 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA9_Max (0x1UL) /*!< Max enumerator value of ATDATA9 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA9_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA9_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA10 @Bit 10 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA10_Pos (10UL) /*!< Position of ATDATA10 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA10_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA10_Pos) /*!< Bit mask of ATDATA10 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA10_Min (0x0UL) /*!< Min enumerator value of ATDATA10 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA10_Max (0x1UL) /*!< Max enumerator value of ATDATA10 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA10_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA10_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA11 @Bit 11 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA11_Pos (11UL) /*!< Position of ATDATA11 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA11_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA11_Pos) /*!< Bit mask of ATDATA11 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA11_Min (0x0UL) /*!< Min enumerator value of ATDATA11 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA11_Max (0x1UL) /*!< Max enumerator value of ATDATA11 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA11_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA11_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA12 @Bit 12 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA12_Pos (12UL) /*!< Position of ATDATA12 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA12_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA12_Pos) /*!< Bit mask of ATDATA12 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA12_Min (0x0UL) /*!< Min enumerator value of ATDATA12 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA12_Max (0x1UL) /*!< Max enumerator value of ATDATA12 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA12_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA12_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA13 @Bit 13 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA13_Pos (13UL) /*!< Position of ATDATA13 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA13_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA13_Pos) /*!< Bit mask of ATDATA13 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA13_Min (0x0UL) /*!< Min enumerator value of ATDATA13 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA13_Max (0x1UL) /*!< Max enumerator value of ATDATA13 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA13_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA13_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA14 @Bit 14 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA14_Pos (14UL) /*!< Position of ATDATA14 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA14_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA14_Pos) /*!< Bit mask of ATDATA14 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA14_Min (0x0UL) /*!< Min enumerator value of ATDATA14 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA14_Max (0x1UL) /*!< Max enumerator value of ATDATA14 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA14_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA14_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA15 @Bit 15 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA15_Pos (15UL) /*!< Position of ATDATA15 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA15_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA15_Pos) /*!< Bit mask of ATDATA15 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA15_Min (0x0UL) /*!< Min enumerator value of ATDATA15 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA15_Max (0x1UL) /*!< Max enumerator value of ATDATA15 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA15_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA15_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA16 @Bit 16 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define ATBFUNNEL_ITATBDATA0_ATDATA16_Pos (16UL) /*!< Position of ATDATA16 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA16_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA16_Pos) /*!< Bit mask of ATDATA16 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA16_Min (0x0UL) /*!< Min enumerator value of ATDATA16 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA16_Max (0x1UL) /*!< Max enumerator value of ATDATA16 field. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA16_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBDATA0_ATDATA16_High (0x1UL) /*!< Pin is logic 1. */ + + +/* ATBFUNNEL_ITATBCTR2: The ITATBCTR2 register performs different functions depending on whether the access is a read or a + write. */ + + #define ATBFUNNEL_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register. */ + +/* ATREADY @Bit 0 : A read access returns the value of atreadym. A write access outputs the data to afvalids[n], where the value + of the CTRLREG at 0x000 defines n. */ + + #define ATBFUNNEL_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */ + #define ATBFUNNEL_ITATBCTR2_ATREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */ + #define ATBFUNNEL_ITATBCTR2_ATREADY_Min (0x0UL) /*!< Min enumerator value of ATREADY field. */ + #define ATBFUNNEL_ITATBCTR2_ATREADY_Max (0x1UL) /*!< Max enumerator value of ATREADY field. */ + #define ATBFUNNEL_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */ + +/* AFVALID @Bit 1 : A read access returns the value of afvalidm. A write access outputs the data to atreadys[n], where the value + of the CTRLREG at 0x000 defines n. */ + + #define ATBFUNNEL_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */ + #define ATBFUNNEL_ITATBCTR2_AFVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */ + #define ATBFUNNEL_ITATBCTR2_AFVALID_Min (0x0UL) /*!< Min enumerator value of AFVALID field. */ + #define ATBFUNNEL_ITATBCTR2_AFVALID_Max (0x1UL) /*!< Max enumerator value of AFVALID field. */ + #define ATBFUNNEL_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */ + + +/* ATBFUNNEL_ITATBCTR1: The ITATBCTR1 register performs different functions depending on whether the access is a read or a + write. */ + + #define ATBFUNNEL_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register. */ + +/* ATVALIDM0 @Bits 0..6 : A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 + defines n. A write outputs the value to the atidm port. */ + + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */ + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Msk (0x7FUL << ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field. */ + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Min (0x0UL) /*!< Min enumerator value of ATVALIDM0 field. */ + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Max (0x1UL) /*!< Max enumerator value of ATVALIDM0 field. */ + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Low (0x00UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_High (0x01UL) /*!< Pin is logic 1. */ + + +/* ATBFUNNEL_ITATBCTR0: The ITATBCTR0 register performs different functions depending on whether the access is a read or a + write. */ + + #define ATBFUNNEL_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALID @Bit 0 : A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. A + write outputs the value to atvalidm. */ + + #define ATBFUNNEL_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ATBFUNNEL_ITATBCTR0_ATVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + #define ATBFUNNEL_ITATBCTR0_ATVALID_Min (0x0UL) /*!< Min enumerator value of ATVALID field. */ + #define ATBFUNNEL_ITATBCTR0_ATVALID_Max (0x1UL) /*!< Max enumerator value of ATVALID field. */ + #define ATBFUNNEL_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */ + +/* AFREADY @Bit 2 : A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. A + write outputs the value to afreadym. */ + + #define ATBFUNNEL_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */ + #define ATBFUNNEL_ITATBCTR0_AFREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + #define ATBFUNNEL_ITATBCTR0_AFREADY_Min (0x0UL) /*!< Min enumerator value of AFREADY field. */ + #define ATBFUNNEL_ITATBCTR0_AFREADY_Max (0x1UL) /*!< Max enumerator value of AFREADY field. */ + #define ATBFUNNEL_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATBYTES @Bits 8..9 : A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. + A write outputs the value to atbytesm. */ + + #define ATBFUNNEL_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ + #define ATBFUNNEL_ITATBCTR0_ATBYTES_Msk (0x3UL << ATBFUNNEL_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ + #define ATBFUNNEL_ITATBCTR0_ATBYTES_Min (0x0UL) /*!< Min enumerator value of ATBYTES field. */ + #define ATBFUNNEL_ITATBCTR0_ATBYTES_Max (0x1UL) /*!< Max enumerator value of ATBYTES field. */ + #define ATBFUNNEL_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBFUNNEL_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */ + + +/* ATBFUNNEL_ITCTRL: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the component can be directly controlled for the + purposes of integration testing and topology detection. */ + + #define ATBFUNNEL_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* IME @Bit 0 : Integration Mode Enable. */ + #define ATBFUNNEL_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ + #define ATBFUNNEL_ITCTRL_IME_Msk (0x1UL << ATBFUNNEL_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */ + #define ATBFUNNEL_ITCTRL_IME_Min (0x0UL) /*!< Min enumerator value of IME field. */ + #define ATBFUNNEL_ITCTRL_IME_Max (0x1UL) /*!< Max enumerator value of IME field. */ + #define ATBFUNNEL_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */ + #define ATBFUNNEL_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */ + + +/* ATBFUNNEL_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the + claim tag, and determines the number of claim bits implemented. */ + + #define ATBFUNNEL_CLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of CLAIMSET register. */ + +/* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define ATBFUNNEL_CLAIMSET_BIT0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT0_Set (0x1UL) /*!< Set claim bit 0. */ + +/* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define ATBFUNNEL_CLAIMSET_BIT1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT1_Set (0x1UL) /*!< Set claim bit 1. */ + +/* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define ATBFUNNEL_CLAIMSET_BIT2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT2_Set (0x1UL) /*!< Set claim bit 2. */ + +/* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define ATBFUNNEL_CLAIMSET_BIT3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ + #define ATBFUNNEL_CLAIMSET_BIT3_Set (0x1UL) /*!< Set claim bit 3. */ + + +/* ATBFUNNEL_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. + The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in + the claim tag to 0 and determines the current value of the claim tag. */ + + #define ATBFUNNEL_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* BIT0 @Bit 0 : Read or clear claim bit 0. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Set (0x1UL) /*!< Claim bit 0 is set. */ + #define ATBFUNNEL_CLAIMCLR_BIT0_Clear (0x1UL) /*!< Clear claim bit 0. */ + +/* BIT1 @Bit 1 : Read or clear claim bit 1. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Set (0x1UL) /*!< Claim bit 1 is set. */ + #define ATBFUNNEL_CLAIMCLR_BIT1_Clear (0x1UL) /*!< Clear claim bit 1. */ + +/* BIT2 @Bit 2 : Read or clear claim bit 2. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Set (0x1UL) /*!< Claim bit 2 is set. */ + #define ATBFUNNEL_CLAIMCLR_BIT2_Clear (0x1UL) /*!< Clear claim bit 2. */ + +/* BIT3 @Bit 3 : Read or clear claim bit 3. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Set (0x1UL) /*!< Claim bit 3 is set. */ + #define ATBFUNNEL_CLAIMCLR_BIT3_Clear (0x1UL) /*!< Clear claim bit 3. */ + + +/* ATBFUNNEL_LAR: This is used to enable write access to device registers. */ + #define ATBFUNNEL_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + */ + + #define ATBFUNNEL_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ + #define ATBFUNNEL_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBFUNNEL_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ + #define ATBFUNNEL_LAR_ACCESS_Min (0xC5ACCE55UL) /*!< Min enumerator value of ACCESS field. */ + #define ATBFUNNEL_LAR_ACCESS_Max (0xC5ACCE55UL) /*!< Max enumerator value of ACCESS field. */ + #define ATBFUNNEL_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ + + +/* ATBFUNNEL_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under + debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register + must always be present although there might not be any lock access control mechanism. The lock mechanism, + where present and locked, must block write accesses to any control register, except the Lock Access Register. + For most components this covers all registers except for the Lock Access Register. */ + + #define ATBFUNNEL_LSR_ResetValue (0x00000000UL) /*!< Reset value of LSR register. */ + +/* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */ + #define ATBFUNNEL_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ + #define ATBFUNNEL_LSR_PRESENT_Msk (0x1UL << ATBFUNNEL_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define ATBFUNNEL_LSR_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define ATBFUNNEL_LSR_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define ATBFUNNEL_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register + are ignored.*/ + #define ATBFUNNEL_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ + +/* LOCKED @Bit 1 : Returns the current status of the Lock. */ + #define ATBFUNNEL_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ + #define ATBFUNNEL_LSR_LOCKED_Msk (0x1UL << ATBFUNNEL_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define ATBFUNNEL_LSR_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define ATBFUNNEL_LSR_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define ATBFUNNEL_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ + #define ATBFUNNEL_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control + registers are ignored. Reads are permitted.*/ + +/* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ + #define ATBFUNNEL_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ + #define ATBFUNNEL_LSR_TYPE_Msk (0x1UL << ATBFUNNEL_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define ATBFUNNEL_LSR_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define ATBFUNNEL_LSR_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define ATBFUNNEL_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ + #define ATBFUNNEL_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ + + +/* ATBFUNNEL_AUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define ATBFUNNEL_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define ATBFUNNEL_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBFUNNEL_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBFUNNEL_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define ATBFUNNEL_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ATBFUNNEL_AUTHSTATUS_SID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define ATBFUNNEL_AUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define ATBFUNNEL_AUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define ATBFUNNEL_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBFUNNEL_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define ATBFUNNEL_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ATBFUNNEL_AUTHSTATUS_SNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define ATBFUNNEL_AUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define ATBFUNNEL_AUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define ATBFUNNEL_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBFUNNEL_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* ATBFUNNEL_DEVID: Indicates the capabilities of the component. */ + #define ATBFUNNEL_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register. */ + +/* PORTCOUNT @Bits 0..3 : Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. */ + #define ATBFUNNEL_DEVID_PORTCOUNT_Pos (0UL) /*!< Position of PORTCOUNT field. */ + #define ATBFUNNEL_DEVID_PORTCOUNT_Msk (0xFUL << ATBFUNNEL_DEVID_PORTCOUNT_Pos) /*!< Bit mask of PORTCOUNT field. */ + #define ATBFUNNEL_DEVID_PORTCOUNT_Min (0x2UL) /*!< Min value of PORTCOUNT field. */ + #define ATBFUNNEL_DEVID_PORTCOUNT_Max (0x8UL) /*!< Max size of PORTCOUNT field. */ + + +/* ATBFUNNEL_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number field + is not recognized. The debugger can then report this information. */ + + #define ATBFUNNEL_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define ATBFUNNEL_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define ATBFUNNEL_DEVTYPE_MAJOR_Msk (0xFUL << ATBFUNNEL_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define ATBFUNNEL_DEVTYPE_MAJOR_Min (0x2UL) /*!< Min enumerator value of MAJOR field. */ + #define ATBFUNNEL_DEVTYPE_MAJOR_Max (0x2UL) /*!< Max enumerator value of MAJOR field. */ + #define ATBFUNNEL_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define ATBFUNNEL_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define ATBFUNNEL_DEVTYPE_SUB_Msk (0xFUL << ATBFUNNEL_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define ATBFUNNEL_DEVTYPE_SUB_Min (0x1UL) /*!< Min enumerator value of SUB field. */ + #define ATBFUNNEL_DEVTYPE_SUB_Max (0x1UL) /*!< Max enumerator value of SUB field. */ + #define ATBFUNNEL_DEVTYPE_SUB_Replicator (0x1UL) /*!< This component arbitrates ATB inputs mapping to ATB outputs. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ATBREPLICATOR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct ATBREPLICATOR =================================================== */ +/** + * @brief ATB Replicator module + */ + typedef struct { /*!< ATBREPLICATOR Structure */ + __IOM uint32_t IDFILTER0; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming of ID + filtering for master port 0.*/ + __IOM uint32_t IDFILTER1; /*!< (@ 0x00000004) The IDFILTER1 register enables the programming of ID + filtering for master port 1.*/ + __IM uint32_t RESERVED[956]; + __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF8) The ITATBCTR1 register returns the value of the + atreadym0, atreadym1, and atvalids inputs in + integration mode.*/ + __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EFC) The ITATBCTR0 register controls the value of the + atvalidm0, atvalidm1, and atreadys outputs in + integration mode.*/ + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to switch + from a functional mode, which is the default behavior, + to integration mode where the inputs and outputs of the + component can be directly controlled for the purposes + of integration testing and topology detection.*/ + __IM uint32_t RESERVED1[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMSET register sets + bits in the claim tag, and determines the number of + claim bits implemented.*/ + __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMCLR register sets + the bits in the claim tag to 0 and determines the + current value of the claim tag.*/ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device + registers.*/ + __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control + mechanism. This lock prevents accidental writes by code + under debug. Accesses to the extended stimulus port + registers are not affected by the lock mechanism. This + register must always be present although there might + not be any lock access control mechanism. The lock + mechanism, where present and locked, must block write + accesses to any control register, except the Lock + Access Register. For most components this covers all + registers except for the Lock Access Register.*/ + __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t RESERVED3[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with + information about the component when the Part Number + field is not recognized. The debugger can then report + this information.*/ + __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t PIDR0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ + __IOM uint32_t CIDR0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + __IOM uint32_t CIDR1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ + __IOM uint32_t CIDR2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ + __IOM uint32_t CIDR3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ + } NRF_ATBREPLICATOR_Type; /*!< Size = 4096 (0x1000) */ + +/* ATBREPLICATOR_IDFILTER0: The IDFILTER0 register enables the programming of ID filtering for master port 0. */ + #define ATBREPLICATOR_IDFILTER0_ResetValue (0x00000000UL) /*!< Reset value of IDFILTER0 register. */ + +/* ID0_00_0F @Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos (0UL) /*!< Position of ID0_00_0F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos) /*!< Bit mask of ID0_00_0F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Min (0x0UL) /*!< Min enumerator value of ID0_00_0F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Max (0x1UL) /*!< Max enumerator value of ID0_00_0F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_10_1F @Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos (1UL) /*!< Position of ID0_10_1F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos) /*!< Bit mask of ID0_10_1F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Min (0x0UL) /*!< Min enumerator value of ID0_10_1F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Max (0x1UL) /*!< Max enumerator value of ID0_10_1F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_20_2F @Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos (2UL) /*!< Position of ID0_20_2F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos) /*!< Bit mask of ID0_20_2F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Min (0x0UL) /*!< Min enumerator value of ID0_20_2F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Max (0x1UL) /*!< Max enumerator value of ID0_20_2F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_30_3F @Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos (3UL) /*!< Position of ID0_30_3F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos) /*!< Bit mask of ID0_30_3F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Min (0x0UL) /*!< Min enumerator value of ID0_30_3F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Max (0x1UL) /*!< Max enumerator value of ID0_30_3F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_40_4F @Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos (4UL) /*!< Position of ID0_40_4F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos) /*!< Bit mask of ID0_40_4F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Min (0x0UL) /*!< Min enumerator value of ID0_40_4F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Max (0x1UL) /*!< Max enumerator value of ID0_40_4F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_50_5F @Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos (5UL) /*!< Position of ID0_50_5F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos) /*!< Bit mask of ID0_50_5F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Min (0x0UL) /*!< Min enumerator value of ID0_50_5F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Max (0x1UL) /*!< Max enumerator value of ID0_50_5F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_60_6F @Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos (6UL) /*!< Position of ID0_60_6F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos) /*!< Bit mask of ID0_60_6F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Min (0x0UL) /*!< Min enumerator value of ID0_60_6F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Max (0x1UL) /*!< Max enumerator value of ID0_60_6F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID0_70_7F @Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos (7UL) /*!< Position of ID0_70_7F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos) /*!< Bit mask of ID0_70_7F + field.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Min (0x0UL) /*!< Min enumerator value of ID0_70_7F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Max (0x1UL) /*!< Max enumerator value of ID0_70_7F field. */ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 0.*/ + #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + + +/* ATBREPLICATOR_IDFILTER1: The IDFILTER1 register enables the programming of ID filtering for master port 1. */ + #define ATBREPLICATOR_IDFILTER1_ResetValue (0x00000000UL) /*!< Reset value of IDFILTER1 register. */ + +/* ID1_00_0F @Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos (0UL) /*!< Position of ID1_00_0F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos) /*!< Bit mask of ID1_00_0F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Min (0x0UL) /*!< Min enumerator value of ID1_00_0F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Max (0x1UL) /*!< Max enumerator value of ID1_00_0F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_10_1F @Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos (1UL) /*!< Position of ID1_10_1F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos) /*!< Bit mask of ID1_10_1F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Min (0x0UL) /*!< Min enumerator value of ID1_10_1F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Max (0x1UL) /*!< Max enumerator value of ID1_10_1F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_20_2F @Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos (2UL) /*!< Position of ID1_20_2F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos) /*!< Bit mask of ID1_20_2F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Min (0x0UL) /*!< Min enumerator value of ID1_20_2F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Max (0x1UL) /*!< Max enumerator value of ID1_20_2F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_30_3F @Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos (3UL) /*!< Position of ID1_30_3F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos) /*!< Bit mask of ID1_30_3F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Min (0x0UL) /*!< Min enumerator value of ID1_30_3F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Max (0x1UL) /*!< Max enumerator value of ID1_30_3F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_40_4F @Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos (4UL) /*!< Position of ID1_40_4F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos) /*!< Bit mask of ID1_40_4F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Min (0x0UL) /*!< Min enumerator value of ID1_40_4F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Max (0x1UL) /*!< Max enumerator value of ID1_40_4F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_50_5F @Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos (5UL) /*!< Position of ID1_50_5F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos) /*!< Bit mask of ID1_50_5F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Min (0x0UL) /*!< Min enumerator value of ID1_50_5F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Max (0x1UL) /*!< Max enumerator value of ID1_50_5F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_60_6F @Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos (6UL) /*!< Position of ID1_60_6F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos) /*!< Bit mask of ID1_60_6F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Min (0x0UL) /*!< Min enumerator value of ID1_60_6F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Max (0x1UL) /*!< Max enumerator value of ID1_60_6F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + +/* ID1_70_7F @Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos (7UL) /*!< Position of ID1_70_7F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos) /*!< Bit mask of ID1_70_7F + field.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Min (0x0UL) /*!< Min enumerator value of ID1_70_7F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Max (0x1UL) /*!< Max enumerator value of ID1_70_7F field. */ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master + port 1.*/ + #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ + + +/* ATBREPLICATOR_ITATBCTR1: The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in + integration mode. */ + + #define ATBREPLICATOR_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register. */ + +/* ATREADYM0 @Bit 0 : Reads the value of the atreadym0 input. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos (0UL) /*!< Position of ATREADYM0 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos) /*!< Bit mask of ATREADYM0 + field.*/ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Min (0x0UL) /*!< Min enumerator value of ATREADYM0 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Max (0x1UL) /*!< Max enumerator value of ATREADYM0 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATREADYM1 @Bit 1 : Reads the value of the atreadym1 input. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos (1UL) /*!< Position of ATREADYM1 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos) /*!< Bit mask of ATREADYM1 + field.*/ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Min (0x0UL) /*!< Min enumerator value of ATREADYM1 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Max (0x1UL) /*!< Max enumerator value of ATREADYM1 field. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATVALIDS @Bit 3 : Reads the value of the atvalids input. */ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos (3UL) /*!< Position of ATVALIDS field. */ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field.*/ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Min (0x0UL) /*!< Min enumerator value of ATVALIDS field. */ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Max (0x1UL) /*!< Max enumerator value of ATVALIDS field. */ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_High (0x1UL) /*!< Pin is logic 1. */ + + +/* ATBREPLICATOR_ITATBCTR0: The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in + integration mode. */ + + #define ATBREPLICATOR_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALIDM0 @Bit 0 : Sets the value of the atvalidm0 output. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 + field.*/ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Min (0x0UL) /*!< Min enumerator value of ATVALIDM0 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Max (0x1UL) /*!< Max enumerator value of ATVALIDM0 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATVALIDM1 @Bit 2 : Sets the value of the atvalidm1 output. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos (2UL) /*!< Position of ATVALIDM1 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos) /*!< Bit mask of ATVALIDM1 + field.*/ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Min (0x0UL) /*!< Min enumerator value of ATVALIDM1 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Max (0x1UL) /*!< Max enumerator value of ATVALIDM1 field. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATREADYS @Bit 3 : Sets the value of the atreadys output. */ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos (3UL) /*!< Position of ATREADYS field. */ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos) /*!< Bit mask of ATREADYS field.*/ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Min (0x0UL) /*!< Min enumerator value of ATREADYS field. */ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Max (0x1UL) /*!< Max enumerator value of ATREADYS field. */ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Low (0x0UL) /*!< Pin is logic 0. */ + #define ATBREPLICATOR_ITATBCTR0_ATREADYS_High (0x1UL) /*!< Pin is logic 1. */ + + +/* ATBREPLICATOR_ITCTRL: The ITCTRL register enables the component to switch from a functional mode, which is the default + behavior, to integration mode where the inputs and outputs of the component can be directly controlled + for the purposes of integration testing and topology detection. */ + + #define ATBREPLICATOR_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* IME @Bit 0 : Integration Mode Enable. */ + #define ATBREPLICATOR_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ + #define ATBREPLICATOR_ITCTRL_IME_Msk (0x1UL << ATBREPLICATOR_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */ + #define ATBREPLICATOR_ITCTRL_IME_Min (0x0UL) /*!< Min enumerator value of IME field. */ + #define ATBREPLICATOR_ITCTRL_IME_Max (0x1UL) /*!< Max enumerator value of IME field. */ + #define ATBREPLICATOR_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */ + #define ATBREPLICATOR_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */ + + +/* ATBREPLICATOR_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit + functionality. The claim tags have no effect on the operation of the component. The CLAIMSET + register sets bits in the claim tag, and determines the number of claim bits implemented. */ + + #define ATBREPLICATOR_CLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of CLAIMSET register. */ + +/* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT0_Set (0x1UL) /*!< Set claim bit 0. */ + +/* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT1_Set (0x1UL) /*!< Set claim bit 1. */ + +/* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT2_Set (0x1UL) /*!< Set claim bit 2. */ + +/* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ + #define ATBREPLICATOR_CLAIMSET_BIT3_Set (0x1UL) /*!< Set claim bit 3. */ + + +/* ATBREPLICATOR_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit + functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR + register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */ + + #define ATBREPLICATOR_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* BIT0 @Bit 0 : Read or clear claim bit 0. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Set (0x1UL) /*!< Claim bit 0 is set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT0_Clear (0x1UL) /*!< Clear claim bit 0. */ + +/* BIT1 @Bit 1 : Read or clear claim bit 1. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Set (0x1UL) /*!< Claim bit 1 is set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT1_Clear (0x1UL) /*!< Clear claim bit 1. */ + +/* BIT2 @Bit 2 : Read or clear claim bit 2. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Set (0x1UL) /*!< Claim bit 2 is set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT2_Clear (0x1UL) /*!< Clear claim bit 2. */ + +/* BIT3 @Bit 3 : Read or clear claim bit 3. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Set (0x1UL) /*!< Claim bit 3 is set. */ + #define ATBREPLICATOR_CLAIMCLR_BIT3_Clear (0x1UL) /*!< Clear claim bit 3. */ + + +/* ATBREPLICATOR_LAR: This is used to enable write access to device registers. */ + #define ATBREPLICATOR_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + */ + + #define ATBREPLICATOR_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ + #define ATBREPLICATOR_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBREPLICATOR_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ + #define ATBREPLICATOR_LAR_ACCESS_Min (0xC5ACCE55UL) /*!< Min enumerator value of ACCESS field. */ + #define ATBREPLICATOR_LAR_ACCESS_Max (0xC5ACCE55UL) /*!< Max enumerator value of ACCESS field. */ + #define ATBREPLICATOR_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ + + +/* ATBREPLICATOR_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code + under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. + This register must always be present although there might not be any lock access control mechanism. The + lock mechanism, where present and locked, must block write accesses to any control register, except the + Lock Access Register. For most components this covers all registers except for the Lock Access Register. + */ + + #define ATBREPLICATOR_LSR_ResetValue (0x00000000UL) /*!< Reset value of LSR register. */ + +/* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */ + #define ATBREPLICATOR_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ + #define ATBREPLICATOR_LSR_PRESENT_Msk (0x1UL << ATBREPLICATOR_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define ATBREPLICATOR_LSR_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define ATBREPLICATOR_LSR_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define ATBREPLICATOR_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access + Register are ignored.*/ + #define ATBREPLICATOR_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ + +/* LOCKED @Bit 1 : Returns the current status of the Lock. */ + #define ATBREPLICATOR_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ + #define ATBREPLICATOR_LSR_LOCKED_Msk (0x1UL << ATBREPLICATOR_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define ATBREPLICATOR_LSR_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define ATBREPLICATOR_LSR_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define ATBREPLICATOR_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ + #define ATBREPLICATOR_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control + registers are ignored. Reads are permitted.*/ + +/* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ + #define ATBREPLICATOR_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ + #define ATBREPLICATOR_LSR_TYPE_Msk (0x1UL << ATBREPLICATOR_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define ATBREPLICATOR_LSR_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define ATBREPLICATOR_LSR_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define ATBREPLICATOR_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ + #define ATBREPLICATOR_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ + + +/* ATBREPLICATOR_AUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define ATBREPLICATOR_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBREPLICATOR_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBREPLICATOR_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define ATBREPLICATOR_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBREPLICATOR_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ATBREPLICATOR_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* ATBREPLICATOR_DEVID: Indicates the capabilities of the component. */ + #define ATBREPLICATOR_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register. */ + +/* PORTNUM @Bits 0..3 : Indicates the number of master ports implemented. */ + #define ATBREPLICATOR_DEVID_PORTNUM_Pos (0UL) /*!< Position of PORTNUM field. */ + #define ATBREPLICATOR_DEVID_PORTNUM_Msk (0xFUL << ATBREPLICATOR_DEVID_PORTNUM_Pos) /*!< Bit mask of PORTNUM field. */ + #define ATBREPLICATOR_DEVID_PORTNUM_Min (0x0UL) /*!< Min value of PORTNUM field. */ + #define ATBREPLICATOR_DEVID_PORTNUM_Max (0xFUL) /*!< Max size of PORTNUM field. */ + + +/* ATBREPLICATOR_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number + field is not recognized. The debugger can then report this information. */ + + #define ATBREPLICATOR_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define ATBREPLICATOR_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define ATBREPLICATOR_DEVTYPE_MAJOR_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define ATBREPLICATOR_DEVTYPE_MAJOR_Min (0x2UL) /*!< Min enumerator value of MAJOR field. */ + #define ATBREPLICATOR_DEVTYPE_MAJOR_Max (0x2UL) /*!< Max enumerator value of MAJOR field. */ + #define ATBREPLICATOR_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define ATBREPLICATOR_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define ATBREPLICATOR_DEVTYPE_SUB_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define ATBREPLICATOR_DEVTYPE_SUB_Min (0x2UL) /*!< Min enumerator value of SUB field. */ + #define ATBREPLICATOR_DEVTYPE_SUB_Max (0x2UL) /*!< Max enumerator value of SUB field. */ + #define ATBREPLICATOR_DEVTYPE_SUB_Replicator (0x2UL) /*!< Indicates that this component replicates trace from a single source + to multiple targets.*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ BELLBOARD ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ==================================================== Struct BELLBOARD ===================================================== */ +/** + * @brief BELLBOARD APB registers + */ + typedef struct { /*!< BELLBOARD Structure */ + __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) Task TRIGGER[n] */ + __IM uint32_t RESERVED[32]; + __IOM uint32_t EVENTS_TRIGGERED[32]; /*!< (@ 0x00000100) Event TRIGGERED[n] */ + __IM uint32_t RESERVED1[96]; + __IOM uint32_t INTEN0; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND0; /*!< (@ 0x0000030C) Pending interrupts */ + __IOM uint32_t INTEN1; /*!< (@ 0x00000310) Enable or disable interrupt */ + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t INTPEND1; /*!< (@ 0x0000031C) Pending interrupts */ + __IOM uint32_t INTEN2; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t INTENSET2; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t INTENCLR2; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t INTPEND2; /*!< (@ 0x0000032C) Pending interrupts */ + __IOM uint32_t INTEN3; /*!< (@ 0x00000330) Enable or disable interrupt */ + __IOM uint32_t INTENSET3; /*!< (@ 0x00000334) Enable interrupt */ + __IOM uint32_t INTENCLR3; /*!< (@ 0x00000338) Disable interrupt */ + __IM uint32_t INTPEND3; /*!< (@ 0x0000033C) Pending interrupts */ + } NRF_BELLBOARD_Type; /*!< Size = 832 (0x340) */ + +/* BELLBOARD_TASKS_TRIGGER: Task TRIGGER[n] */ + #define BELLBOARD_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ + #define BELLBOARD_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ + #define BELLBOARD_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ + #define BELLBOARD_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + +/* TASKS_TRIGGER @Bit 0 : Task TRIGGER[n] */ + #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of + TASKS_TRIGGER field.*/ + #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +/* BELLBOARD_EVENTS_TRIGGERED: Event TRIGGERED[n] */ + #define BELLBOARD_EVENTS_TRIGGERED_MaxCount (32UL) /*!< Max size of EVENTS_TRIGGERED[32] array. */ + #define BELLBOARD_EVENTS_TRIGGERED_MaxIndex (31UL) /*!< Max index of EVENTS_TRIGGERED[32] array. */ + #define BELLBOARD_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[32] array. */ + #define BELLBOARD_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register. */ + +/* EVENTS_TRIGGERED @Bit 0 : Event TRIGGERED[n] */ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit + mask of EVENTS_TRIGGERED field.*/ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field. */ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field. */ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ + #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ + + +/* BELLBOARD_INTEN0: Enable or disable interrupt */ + #define BELLBOARD_INTEN0_ResetValue (0x00000000UL) /*!< Reset value of INTEN0 register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTEN0_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTEN0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTEN0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN0_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTEN0_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTEN0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTEN0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN0_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTEN0_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTEN0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTEN0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN0_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTEN0_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTEN0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTEN0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN0_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTEN0_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTEN0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTEN0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN0_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTEN0_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTEN0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTEN0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN0_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTEN0_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTEN0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTEN0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN0_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTEN0_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTEN0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTEN0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN0_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTEN0_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTEN0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTEN0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN0_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTEN0_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTEN0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTEN0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN0_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTEN0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTEN0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTEN0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN0_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTEN0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTEN0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTEN0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN0_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTEN0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTEN0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTEN0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN0_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTEN0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTEN0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTEN0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN0_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTEN0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTEN0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTEN0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN0_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTEN0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTEN0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTEN0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN0_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTEN0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTEN0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTEN0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN0_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTEN0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTEN0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTEN0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN0_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTEN0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTEN0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTEN0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN0_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTEN0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTEN0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTEN0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN0_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTEN0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTEN0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTEN0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN0_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTEN0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTEN0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTEN0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN0_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTEN0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTEN0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTEN0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN0_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTEN0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTEN0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTEN0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN0_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTEN0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTEN0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTEN0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN0_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTEN0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTEN0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTEN0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN0_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTEN0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTEN0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTEN0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN0_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTEN0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTEN0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTEN0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN0_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTEN0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTEN0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTEN0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN0_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTEN0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTEN0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTEN0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN0_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTEN0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTEN0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTEN0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN0_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTEN0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTEN0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTEN0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN0_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN0_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ + + +/* BELLBOARD_INTENSET0: Enable interrupt */ + #define BELLBOARD_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENSET0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET0_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTENCLR0: Disable interrupt */ + #define BELLBOARD_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR0_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTPEND0: Pending interrupts */ + #define BELLBOARD_INTPEND0_ResetValue (0x00000000UL) /*!< Reset value of INTPEND0 register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTPEND0_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTPEND0_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTPEND0_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTPEND0_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTPEND0_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTPEND0_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTPEND0_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTPEND0_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTPEND0_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTPEND0_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTPEND0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTPEND0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTPEND0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTPEND0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTPEND0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTPEND0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTPEND0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTPEND0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTPEND0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTPEND0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTPEND0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTPEND0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTPEND0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTPEND0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTPEND0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTPEND0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTPEND0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTPEND0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTPEND0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTPEND0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTPEND0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTPEND0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND0_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND0_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ + + +/* BELLBOARD_INTEN1: Enable or disable interrupt */ + #define BELLBOARD_INTEN1_ResetValue (0x00000000UL) /*!< Reset value of INTEN1 register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTEN1_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTEN1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTEN1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN1_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTEN1_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTEN1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTEN1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN1_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTEN1_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTEN1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTEN1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN1_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTEN1_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTEN1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTEN1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN1_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTEN1_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTEN1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTEN1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN1_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTEN1_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTEN1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTEN1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN1_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTEN1_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTEN1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTEN1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN1_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTEN1_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTEN1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTEN1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN1_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTEN1_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTEN1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTEN1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN1_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTEN1_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTEN1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTEN1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN1_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTEN1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTEN1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTEN1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN1_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTEN1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTEN1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTEN1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN1_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTEN1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTEN1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTEN1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN1_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTEN1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTEN1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTEN1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN1_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTEN1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTEN1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTEN1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN1_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTEN1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTEN1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTEN1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN1_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTEN1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTEN1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTEN1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN1_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTEN1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTEN1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTEN1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN1_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTEN1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTEN1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTEN1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN1_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTEN1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTEN1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTEN1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN1_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTEN1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTEN1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTEN1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN1_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTEN1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTEN1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTEN1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN1_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTEN1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTEN1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTEN1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN1_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTEN1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTEN1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTEN1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN1_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTEN1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTEN1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTEN1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN1_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTEN1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTEN1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTEN1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN1_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTEN1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTEN1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTEN1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN1_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTEN1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTEN1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTEN1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN1_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTEN1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTEN1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTEN1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN1_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTEN1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTEN1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTEN1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN1_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTEN1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTEN1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTEN1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN1_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTEN1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTEN1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTEN1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN1_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN1_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ + + +/* BELLBOARD_INTENSET1: Enable interrupt */ + #define BELLBOARD_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENSET1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET1_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTENCLR1: Disable interrupt */ + #define BELLBOARD_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR1_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTPEND1: Pending interrupts */ + #define BELLBOARD_INTPEND1_ResetValue (0x00000000UL) /*!< Reset value of INTPEND1 register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTPEND1_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTPEND1_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTPEND1_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTPEND1_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTPEND1_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTPEND1_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTPEND1_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTPEND1_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTPEND1_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTPEND1_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTPEND1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTPEND1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTPEND1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTPEND1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTPEND1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTPEND1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTPEND1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTPEND1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTPEND1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTPEND1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTPEND1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTPEND1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTPEND1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTPEND1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTPEND1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTPEND1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTPEND1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTPEND1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTPEND1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTPEND1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTPEND1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTPEND1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND1_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND1_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ + + +/* BELLBOARD_INTEN2: Enable or disable interrupt */ + #define BELLBOARD_INTEN2_ResetValue (0x00000000UL) /*!< Reset value of INTEN2 register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTEN2_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTEN2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTEN2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN2_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTEN2_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTEN2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTEN2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN2_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTEN2_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTEN2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTEN2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN2_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTEN2_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTEN2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTEN2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN2_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTEN2_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTEN2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTEN2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN2_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTEN2_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTEN2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTEN2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN2_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTEN2_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTEN2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTEN2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN2_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTEN2_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTEN2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTEN2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN2_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTEN2_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTEN2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTEN2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN2_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTEN2_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTEN2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTEN2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN2_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTEN2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTEN2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTEN2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN2_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTEN2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTEN2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTEN2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN2_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTEN2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTEN2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTEN2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN2_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTEN2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTEN2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTEN2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN2_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTEN2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTEN2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTEN2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN2_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTEN2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTEN2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTEN2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN2_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTEN2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTEN2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTEN2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN2_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTEN2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTEN2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTEN2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN2_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTEN2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTEN2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTEN2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN2_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTEN2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTEN2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTEN2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN2_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTEN2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTEN2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTEN2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN2_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTEN2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTEN2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTEN2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN2_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTEN2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTEN2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTEN2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN2_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTEN2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTEN2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTEN2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN2_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTEN2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTEN2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTEN2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN2_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTEN2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTEN2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTEN2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN2_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTEN2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTEN2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTEN2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN2_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTEN2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTEN2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTEN2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN2_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTEN2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTEN2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTEN2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN2_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTEN2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTEN2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTEN2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN2_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTEN2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTEN2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTEN2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN2_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTEN2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTEN2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTEN2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN2_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN2_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ + + +/* BELLBOARD_INTENSET2: Enable interrupt */ + #define BELLBOARD_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENSET2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET2_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTENCLR2: Disable interrupt */ + #define BELLBOARD_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR2_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTPEND2: Pending interrupts */ + #define BELLBOARD_INTPEND2_ResetValue (0x00000000UL) /*!< Reset value of INTPEND2 register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTPEND2_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTPEND2_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTPEND2_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTPEND2_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTPEND2_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTPEND2_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTPEND2_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTPEND2_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTPEND2_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTPEND2_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTPEND2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTPEND2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTPEND2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTPEND2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTPEND2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTPEND2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTPEND2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTPEND2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTPEND2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTPEND2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTPEND2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTPEND2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTPEND2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTPEND2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTPEND2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTPEND2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTPEND2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTPEND2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTPEND2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTPEND2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTPEND2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTPEND2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND2_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND2_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ + + +/* BELLBOARD_INTEN3: Enable or disable interrupt */ + #define BELLBOARD_INTEN3_ResetValue (0x00000000UL) /*!< Reset value of INTEN3 register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTEN3_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTEN3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTEN3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTEN3_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTEN3_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTEN3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTEN3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTEN3_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTEN3_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTEN3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTEN3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTEN3_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTEN3_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTEN3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTEN3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTEN3_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTEN3_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTEN3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTEN3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTEN3_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTEN3_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTEN3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTEN3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTEN3_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTEN3_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTEN3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTEN3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTEN3_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTEN3_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTEN3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTEN3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTEN3_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTEN3_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTEN3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTEN3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTEN3_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTEN3_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTEN3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTEN3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTEN3_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTEN3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTEN3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTEN3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTEN3_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTEN3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTEN3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTEN3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTEN3_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTEN3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTEN3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTEN3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTEN3_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTEN3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTEN3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTEN3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTEN3_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTEN3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTEN3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTEN3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTEN3_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTEN3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTEN3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTEN3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTEN3_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTEN3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTEN3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTEN3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTEN3_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTEN3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTEN3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTEN3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTEN3_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTEN3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTEN3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTEN3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTEN3_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTEN3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTEN3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTEN3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTEN3_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTEN3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTEN3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTEN3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTEN3_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTEN3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTEN3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTEN3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTEN3_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTEN3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTEN3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTEN3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTEN3_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTEN3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTEN3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTEN3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTEN3_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTEN3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTEN3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTEN3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTEN3_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTEN3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTEN3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTEN3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTEN3_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTEN3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTEN3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTEN3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTEN3_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTEN3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTEN3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTEN3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTEN3_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTEN3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTEN3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTEN3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTEN3_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTEN3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTEN3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTEN3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTEN3_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTEN3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTEN3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTEN3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTEN3_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTEN3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTEN3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTEN3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTEN3_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ + #define BELLBOARD_INTEN3_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ + + +/* BELLBOARD_INTENSET3: Enable interrupt */ + #define BELLBOARD_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENSET3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Set (0x1UL) /*!< Enable */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENSET3_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTENCLR3: Disable interrupt */ + #define BELLBOARD_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 + field.*/ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Clear (0x1UL) /*!< Disable */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define BELLBOARD_INTENCLR3_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* BELLBOARD_INTPEND3: Pending interrupts */ + #define BELLBOARD_INTPEND3_ResetValue (0x00000000UL) /*!< Reset value of INTPEND3 register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define BELLBOARD_INTPEND3_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define BELLBOARD_INTPEND3_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define BELLBOARD_INTPEND3_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define BELLBOARD_INTPEND3_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define BELLBOARD_INTPEND3_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define BELLBOARD_INTPEND3_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define BELLBOARD_INTPEND3_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define BELLBOARD_INTPEND3_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define BELLBOARD_INTPEND3_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define BELLBOARD_INTPEND3_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define BELLBOARD_INTPEND3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define BELLBOARD_INTPEND3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define BELLBOARD_INTPEND3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define BELLBOARD_INTPEND3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define BELLBOARD_INTPEND3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define BELLBOARD_INTPEND3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define BELLBOARD_INTPEND3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define BELLBOARD_INTPEND3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define BELLBOARD_INTPEND3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define BELLBOARD_INTPEND3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define BELLBOARD_INTPEND3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define BELLBOARD_INTPEND3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define BELLBOARD_INTPEND3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ + #define BELLBOARD_INTPEND3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ + #define BELLBOARD_INTPEND3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ + #define BELLBOARD_INTPEND3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ + #define BELLBOARD_INTPEND3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ + #define BELLBOARD_INTPEND3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ + #define BELLBOARD_INTPEND3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ + #define BELLBOARD_INTPEND3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ + #define BELLBOARD_INTPEND3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ + #define BELLBOARD_INTPEND3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define BELLBOARD_INTPEND3_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ + #define BELLBOARD_INTPEND3_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ BELLBOARDPUBLIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================= Struct BELLBOARDPUBLIC ================================================== */ +/** + * @brief BELLBOARD public registers + */ + typedef struct { /*!< BELLBOARDPUBLIC Structure */ + __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) Task TRIGGER[n] */ + } NRF_BELLBOARDPUBLIC_Type; /*!< Size = 128 (0x080) */ + +/* BELLBOARDPUBLIC_TASKS_TRIGGER: Task TRIGGER[n] */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + +/* TASKS_TRIGGER @Bit 0 : Task TRIGGER[n] */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit + mask of TASKS_TRIGGER field.*/ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ BICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct BICR_IOPORT ==================================================== */ +/** + * @brief IOPORT [BICR_IOPORT] (unspecified) + */ +typedef struct { + __IOM uint32_t POWER0; /*!< (@ 0x00000000) Power configuration for P0 to P7 IO ports. Note: P0 is + not included in the fields of this register because it + is always internally supplied and therefore considered + 'Shorted'.*/ + __IOM uint32_t POWER1; /*!< (@ 0x00000004) Power configuration for P8 to P15 IO ports. */ + __IOM uint32_t DRIVECTRL0; /*!< (@ 0x00000008) Drive control configuration for P0 to P7 IO ports. */ + __IOM uint32_t DRIVECTRL1; /*!< (@ 0x0000000C) Drive control configuration for P8 to P15 IO ports. */ +} NRF_BICR_IOPORT_Type; /*!< Size = 16 (0x010) */ + +/* BICR_IOPORT_POWER0: Power configuration for P0 to P7 IO ports. Note: P0 is not included in the fields of this register + because it is always internally supplied and therefore considered 'Shorted'. */ + + #define BICR_IOPORT_POWER0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of POWER0 register. */ + +/* P1 @Bits 4..7 : P1 power configuration. */ + #define BICR_IOPORT_POWER0_P1_Pos (4UL) /*!< Position of P1 field. */ + #define BICR_IOPORT_POWER0_P1_Msk (0xFUL << BICR_IOPORT_POWER0_P1_Pos) /*!< Bit mask of P1 field. */ + #define BICR_IOPORT_POWER0_P1_Min (0x0UL) /*!< Min enumerator value of P1 field. */ + #define BICR_IOPORT_POWER0_P1_Max (0xFUL) /*!< Max enumerator value of P1 field. */ + #define BICR_IOPORT_POWER0_P1_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER0_P1_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER0_P1_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER0_P1_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P2 @Bits 8..11 : P2 power configuration. */ + #define BICR_IOPORT_POWER0_P2_Pos (8UL) /*!< Position of P2 field. */ + #define BICR_IOPORT_POWER0_P2_Msk (0xFUL << BICR_IOPORT_POWER0_P2_Pos) /*!< Bit mask of P2 field. */ + #define BICR_IOPORT_POWER0_P2_Min (0x0UL) /*!< Min enumerator value of P2 field. */ + #define BICR_IOPORT_POWER0_P2_Max (0xFUL) /*!< Max enumerator value of P2 field. */ + #define BICR_IOPORT_POWER0_P2_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER0_P2_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER0_P2_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER0_P2_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P6 @Bits 24..27 : P6 power configuration. */ + #define BICR_IOPORT_POWER0_P6_Pos (24UL) /*!< Position of P6 field. */ + #define BICR_IOPORT_POWER0_P6_Msk (0xFUL << BICR_IOPORT_POWER0_P6_Pos) /*!< Bit mask of P6 field. */ + #define BICR_IOPORT_POWER0_P6_Min (0x0UL) /*!< Min enumerator value of P6 field. */ + #define BICR_IOPORT_POWER0_P6_Max (0xFUL) /*!< Max enumerator value of P6 field. */ + #define BICR_IOPORT_POWER0_P6_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER0_P6_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER0_P6_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER0_P6_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + + +/* BICR_IOPORT_POWER1: Power configuration for P8 to P15 IO ports. */ + #define BICR_IOPORT_POWER1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of POWER1 register. */ + +/* P8 @Bits 0..3 : P8 power configuration. */ + #define BICR_IOPORT_POWER1_P8_Pos (0UL) /*!< Position of P8 field. */ + #define BICR_IOPORT_POWER1_P8_Msk (0xFUL << BICR_IOPORT_POWER1_P8_Pos) /*!< Bit mask of P8 field. */ + #define BICR_IOPORT_POWER1_P8_Min (0x0UL) /*!< Min enumerator value of P8 field. */ + #define BICR_IOPORT_POWER1_P8_Max (0xFUL) /*!< Max enumerator value of P8 field. */ + #define BICR_IOPORT_POWER1_P8_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P8_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P8_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P8_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P9 @Bits 4..7 : P9 power configuration. */ + #define BICR_IOPORT_POWER1_P9_Pos (4UL) /*!< Position of P9 field. */ + #define BICR_IOPORT_POWER1_P9_Msk (0xFUL << BICR_IOPORT_POWER1_P9_Pos) /*!< Bit mask of P9 field. */ + #define BICR_IOPORT_POWER1_P9_Min (0x0UL) /*!< Min enumerator value of P9 field. */ + #define BICR_IOPORT_POWER1_P9_Max (0xFUL) /*!< Max enumerator value of P9 field. */ + #define BICR_IOPORT_POWER1_P9_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P9_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P9_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P9_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + #define BICR_IOPORT_POWER1_P9_External3V (0x3UL) /*!< Port supply is provided externally at 3 V. */ + #define BICR_IOPORT_POWER1_P9_ExternalFull (0x4UL) /*!< Port supply is provided externally with a full range of values, from 3 + V to 1.8 V.*/ + +/* P10 @Bits 8..11 : P10 power configuration. */ + #define BICR_IOPORT_POWER1_P10_Pos (8UL) /*!< Position of P10 field. */ + #define BICR_IOPORT_POWER1_P10_Msk (0xFUL << BICR_IOPORT_POWER1_P10_Pos) /*!< Bit mask of P10 field. */ + #define BICR_IOPORT_POWER1_P10_Min (0x0UL) /*!< Min enumerator value of P10 field. */ + #define BICR_IOPORT_POWER1_P10_Max (0xFUL) /*!< Max enumerator value of P10 field. */ + #define BICR_IOPORT_POWER1_P10_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P10_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P10_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P10_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P11 @Bits 12..15 : P11 power configuration. */ + #define BICR_IOPORT_POWER1_P11_Pos (12UL) /*!< Position of P11 field. */ + #define BICR_IOPORT_POWER1_P11_Msk (0xFUL << BICR_IOPORT_POWER1_P11_Pos) /*!< Bit mask of P11 field. */ + #define BICR_IOPORT_POWER1_P11_Min (0x0UL) /*!< Min enumerator value of P11 field. */ + #define BICR_IOPORT_POWER1_P11_Max (0xFUL) /*!< Max enumerator value of P11 field. */ + #define BICR_IOPORT_POWER1_P11_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P11_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P11_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P11_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P12 @Bits 16..19 : P12 power configuration. */ + #define BICR_IOPORT_POWER1_P12_Pos (16UL) /*!< Position of P12 field. */ + #define BICR_IOPORT_POWER1_P12_Msk (0xFUL << BICR_IOPORT_POWER1_P12_Pos) /*!< Bit mask of P12 field. */ + #define BICR_IOPORT_POWER1_P12_Min (0x0UL) /*!< Min enumerator value of P12 field. */ + #define BICR_IOPORT_POWER1_P12_Max (0xFUL) /*!< Max enumerator value of P12 field. */ + #define BICR_IOPORT_POWER1_P12_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P12_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P12_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P12_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + +/* P13 @Bits 20..23 : P13 power configuration. */ + #define BICR_IOPORT_POWER1_P13_Pos (20UL) /*!< Position of P13 field. */ + #define BICR_IOPORT_POWER1_P13_Msk (0xFUL << BICR_IOPORT_POWER1_P13_Pos) /*!< Bit mask of P13 field. */ + #define BICR_IOPORT_POWER1_P13_Min (0x0UL) /*!< Min enumerator value of P13 field. */ + #define BICR_IOPORT_POWER1_P13_Max (0xFUL) /*!< Max enumerator value of P13 field. */ + #define BICR_IOPORT_POWER1_P13_Unconfigured (0xFUL) /*!< Port supply is unconfigured. */ + #define BICR_IOPORT_POWER1_P13_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used. */ + #define BICR_IOPORT_POWER1_P13_Shorted (0x1UL) /*!< Port supply is shorted to VDD_AO_1V8. */ + #define BICR_IOPORT_POWER1_P13_External1V8 (0x2UL) /*!< Port supply is provided externally at 1.8 V. */ + + +/* BICR_IOPORT_DRIVECTRL0: Drive control configuration for P0 to P7 IO ports. */ + #define BICR_IOPORT_DRIVECTRL0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DRIVECTRL0 register. */ + +/* P6 @Bits 24..27 : P6 drive control configuration. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Pos (24UL) /*!< Position of P6 field. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P6_Pos) /*!< Bit mask of P6 field. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Min (0x0UL) /*!< Min enumerator value of P6 field. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Max (0xFUL) /*!< Max enumerator value of P6 field. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be + adjusted.*/ + #define BICR_IOPORT_DRIVECTRL0_P6_Ohms33 (0x0UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 33 Ohms. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Ohms40 (0x1UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 40 Ohms. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Ohms50 (0x2UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 50 Ohms. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Ohms66 (0x3UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 66 Ohms. */ + #define BICR_IOPORT_DRIVECTRL0_P6_Ohms100 (0x4UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 100 Ohms. */ + + +/* BICR_IOPORT_DRIVECTRL1: Drive control configuration for P8 to P15 IO ports. */ + #define BICR_IOPORT_DRIVECTRL1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DRIVECTRL1 register. */ + +/* P8 @Bits 0..3 : P8 drive control configuration. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Pos (0UL) /*!< Position of P8 field. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Msk (0xFUL << BICR_IOPORT_DRIVECTRL1_P8_Pos) /*!< Bit mask of P8 field. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Min (0x0UL) /*!< Min enumerator value of P8 field. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Max (0xFUL) /*!< Max enumerator value of P8 field. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be + adjusted.*/ + #define BICR_IOPORT_DRIVECTRL1_P8_Ohms33 (0x0UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 33 Ohms. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Ohms40 (0x1UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 40 Ohms. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Ohms50 (0x2UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 50 Ohms. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Ohms66 (0x3UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 66 Ohms. */ + #define BICR_IOPORT_DRIVECTRL1_P8_Ohms100 (0x4UL) /*!< PORTCNF.DRIVECTRL will be adjusted for 100 Ohms. */ + + + +/* ==================================================== Struct BICR_LFOSC ==================================================== */ +/** + * @brief LFOSC [BICR_LFOSC] (unspecified) + */ +typedef struct { + __IOM uint32_t LFXOCONFIG; /*!< (@ 0x00000000) LFXO configuration. Note. This configuration might be + overridden by FICR configuration.*/ + __IOM uint32_t LFXOCAL; /*!< (@ 0x00000004) LFXO calibration needed. Must be written to 0xFFFFFFFF + after any modification of the LFXO board circuit, load + capacitance, or crystal swap.*/ + __IOM uint32_t LFRCAUTOCALCONFIG; /*!< (@ 0x00000008) LFRC autocalibration configuration. */ +} NRF_BICR_LFOSC_Type; /*!< Size = 12 (0x00C) */ + +/* BICR_LFOSC_LFXOCONFIG: LFXO configuration. Note. This configuration might be overridden by FICR configuration. */ + #define BICR_LFOSC_LFXOCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCONFIG register. */ + +/* ACCURACY @Bits 0..3 : LFXO crystal or external signal accuracy. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Pos (0UL) /*!< Position of ACCURACY field. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Msk (0xFUL << BICR_LFOSC_LFXOCONFIG_ACCURACY_Pos) /*!< Bit mask of ACCURACY field. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Min (0x0UL) /*!< Min enumerator value of ACCURACY field. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Max (0xFUL) /*!< Max enumerator value of ACCURACY field. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Unconfigured (0xFUL) /*!< The accuracy is unconfigured. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_500ppm (0x0UL) /*!< LFXO crystal or external signal has an accuracy of 500 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_250ppm (0x1UL) /*!< LFXO crystal or external signal has an accuracy of 250 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_150ppm (0x2UL) /*!< LFXO crystal or external signal has an accuracy of 150 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_100ppm (0x3UL) /*!< LFXO crystal or external signal has an accuracy of 100 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_75ppm (0x4UL) /*!< LFXO crystal or external signal has an accuracy of 75 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_50ppm (0x5UL) /*!< LFXO crystal or external signal has an accuracy of 50 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_30ppm (0x6UL) /*!< LFXO crystal or external signal has an accuracy of 30 ppm. */ + #define BICR_LFOSC_LFXOCONFIG_ACCURACY_20ppm (0x7UL) /*!< LFXO crystal or external signal has an accuracy of 20 ppm. */ + +/* MODE @Bits 4..6 : LFXO mode. LFXO will not start unless MODE is configured. Setting this field to anyting but Unconfigured + will be used as the indication that the selected source is available as input to the LFXO. */ + + #define BICR_LFOSC_LFXOCONFIG_MODE_Pos (4UL) /*!< Position of MODE field. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Msk (0x7UL << BICR_LFOSC_LFXOCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Max (0x7UL) /*!< Max enumerator value of MODE field. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Crystal (0x0UL) /*!< LFXO in external crystal oscillator mode. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSine (0x2UL) /*!< LFXO in external sine wave mode. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSquare (0x3UL) /*!< LFXO in external square wave mode. */ + #define BICR_LFOSC_LFXOCONFIG_MODE_Disabled (0x6UL) /*!< LFXO is not to be used. */ + +/* LOADCAP @Bits 8..15 : Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. */ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Pos (8UL) /*!< Position of LOADCAP field. */ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Msk (0xFFUL << BICR_LFOSC_LFXOCONFIG_LOADCAP_Pos) /*!< Bit mask of LOADCAP field. */ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Min (0x0UL) /*!< Min enumerator value of LOADCAP field. */ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Max (0xFFUL) /*!< Max enumerator value of LOADCAP field. */ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Unconfigured (0xFFUL) /*!< The built-in load capacitors is unconfigured. LFXO will not + start unless LOADCAP is configured.*/ + #define BICR_LFOSC_LFXOCONFIG_LOADCAP_External (0x00UL) /*!< Do not use the built-in load capacitors, only external capacitors + will be used.*/ + +/* TIME @Bits 16..27 : LFXO startup time in ms. */ + #define BICR_LFOSC_LFXOCONFIG_TIME_Pos (16UL) /*!< Position of TIME field. */ + #define BICR_LFOSC_LFXOCONFIG_TIME_Msk (0xFFFUL << BICR_LFOSC_LFXOCONFIG_TIME_Pos) /*!< Bit mask of TIME field. */ + #define BICR_LFOSC_LFXOCONFIG_TIME_Min (0xFFFUL) /*!< Min enumerator value of TIME field. */ + #define BICR_LFOSC_LFXOCONFIG_TIME_Max (0xFFFUL) /*!< Max enumerator value of TIME field. */ + #define BICR_LFOSC_LFXOCONFIG_TIME_Unconfigured (0xFFFUL) /*!< Startup time has not been configured. */ + + +/* BICR_LFOSC_LFXOCAL: LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit, + load capacitance, or crystal swap. */ + + #define BICR_LFOSC_LFXOCAL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCAL register. */ + +/* LFXOCAL @Bits 0..31 : LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board + circuit, load capacitance, or crystal swap. */ + + #define BICR_LFOSC_LFXOCAL_LFXOCAL_Pos (0UL) /*!< Position of LFXOCAL field. */ + #define BICR_LFOSC_LFXOCAL_LFXOCAL_Msk (0xFFFFFFFFUL << BICR_LFOSC_LFXOCAL_LFXOCAL_Pos) /*!< Bit mask of LFXOCAL field. */ + #define BICR_LFOSC_LFXOCAL_LFXOCAL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of LFXOCAL field. */ + #define BICR_LFOSC_LFXOCAL_LFXOCAL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of LFXOCAL field. */ + #define BICR_LFOSC_LFXOCAL_LFXOCAL_Calibrate (0xFFFFFFFFUL) /*!< Calibrate the LFXO at startup. */ + + +/* BICR_LFOSC_LFRCAUTOCALCONFIG: LFRC autocalibration configuration. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFRCAUTOCALCONFIG register. */ + +/* TEMPINTERVAL @Bits 0..6 : Temperature measurement interval in 0.25 s steps. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos (0UL) /*!< Position of TEMPINTERVAL field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Msk (0x7FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos) /*!< Bit mask + of TEMPINTERVAL field.*/ + +/* TEMPDELTA @Bits 8..13 : Temperature delta that should trigger a calibration in 0.25 degrees steps. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos (8UL) /*!< Position of TEMPDELTA field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Msk (0x3FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos) /*!< Bit mask of + TEMPDELTA field.*/ + +/* INTERVALMAXNO @Bits 16..20 : Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature + changes. */ + + #define BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos (16UL) /*!< Position of INTERVALMAXNO field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Msk (0x1FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos) /*!< Bit + mask of INTERVALMAXNO field.*/ + +/* ENABLE @Bit 31 : LFRC.AUTOCALCONFIG register enable. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Msk (0x1UL << BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Enabled (0x0UL) /*!< LFRC.AUTOCALCONFIG register has been configured and can be + used.*/ + #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Disabled (0x1UL) /*!< LFRC.AUTOCALCONFIG register has not been configured and + cannot be used.*/ + + + +/* =================================================== Struct BICR_HFXO64M =================================================== */ +/** + * @brief HFXO64M [BICR_HFXO64M] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) HFXO64M configuration. Note. This configuration might + be overridden by FICR configuration.*/ + __IOM uint32_t STARTUPTIME; /*!< (@ 0x00000004) HFXO64M startup time in us. Note. This configuration + might be overridden by FICR configuration.*/ +} NRF_BICR_HFXO64M_Type; /*!< Size = 8 (0x008) */ + +/* BICR_HFXO64M_CONFIG: HFXO64M configuration. Note. This configuration might be overridden by FICR configuration. */ + #define BICR_HFXO64M_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* MODE @Bits 0..2 : HFXO64M mode. */ + #define BICR_HFXO64M_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define BICR_HFXO64M_CONFIG_MODE_Msk (0x7UL << BICR_HFXO64M_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define BICR_HFXO64M_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define BICR_HFXO64M_CONFIG_MODE_Max (0x7UL) /*!< Max enumerator value of MODE field. */ + #define BICR_HFXO64M_CONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured. */ + #define BICR_HFXO64M_CONFIG_MODE_Normal (0x0UL) /*!< Normal operating mode. */ + #define BICR_HFXO64M_CONFIG_MODE_TCXO (0x1UL) /*!< TCXO/bypass mode */ + #define BICR_HFXO64M_CONFIG_MODE_Crystal2 (0x2UL) /*!< Reserved value */ + #define BICR_HFXO64M_CONFIG_MODE_Crystal3 (0x3UL) /*!< Reserved value */ + #define BICR_HFXO64M_CONFIG_MODE_Crystal4 (0x4UL) /*!< Reserved value */ + #define BICR_HFXO64M_CONFIG_MODE_Crystal5 (0x5UL) /*!< Reserved value */ + #define BICR_HFXO64M_CONFIG_MODE_Crystal6 (0x6UL) /*!< Reserved value */ + + +/* BICR_HFXO64M_STARTUPTIME: HFXO64M startup time in us. Note. This configuration might be overridden by FICR configuration. */ + #define BICR_HFXO64M_STARTUPTIME_ResetValue (0xFFFFFFFFUL) /*!< Reset value of STARTUPTIME register. */ + +/* TIME @Bits 0..31 : HFXO64M startup time in us. */ + #define BICR_HFXO64M_STARTUPTIME_TIME_Pos (0UL) /*!< Position of TIME field. */ + #define BICR_HFXO64M_STARTUPTIME_TIME_Msk (0xFFFFFFFFUL << BICR_HFXO64M_STARTUPTIME_TIME_Pos) /*!< Bit mask of TIME field. */ + #define BICR_HFXO64M_STARTUPTIME_TIME_Min (0xFFFFFFFFUL) /*!< Min enumerator value of TIME field. */ + #define BICR_HFXO64M_STARTUPTIME_TIME_Max (0xFFFFFFFFUL) /*!< Max enumerator value of TIME field. */ + #define BICR_HFXO64M_STARTUPTIME_TIME_Unconfigured (0xFFFFFFFFUL) /*!< Startup time has not been configured. */ + + + +/* ==================================================== Struct BICR_TAMPC ==================================================== */ +/** + * @brief TAMPC [BICR_TAMPC] (unspecified) + */ +typedef struct { + __IOM uint32_t TAMPERSWITCH; /*!< (@ 0x00000000) Configuration for external tamper switch detector. */ + __IOM uint32_t ACTIVESHIELD; /*!< (@ 0x00000004) Configuration for active shield channels. */ +} NRF_BICR_TAMPC_Type; /*!< Size = 8 (0x008) */ + +/* BICR_TAMPC_TAMPERSWITCH: Configuration for external tamper switch detector. */ + #define BICR_TAMPC_TAMPERSWITCH_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAMPERSWITCH register. */ + +/* TAMPERSWITCH @Bits 0..3 : Tamper switch enable. */ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Pos (0UL) /*!< Position of TAMPERSWITCH field. */ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Msk (0xFUL << BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Pos) /*!< Bit mask of + TAMPERSWITCH field.*/ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Min (0x0UL) /*!< Min enumerator value of TAMPERSWITCH field. */ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Max (0xFUL) /*!< Max enumerator value of TAMPERSWITCH field. */ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Disabled (0xFUL) /*!< Tamper switch is disabled. */ + #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Enabled (0x0UL) /*!< Tamper switch is enabled. */ + + +/* BICR_TAMPC_ACTIVESHIELD: Configuration for active shield channels. */ + #define BICR_TAMPC_ACTIVESHIELD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ACTIVESHIELD register. */ + +/* CHEN0 @Bits 0..3 : Active shield enable for channel 0. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Min (0x0UL) /*!< Min enumerator value of CHEN0 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Max (0xFUL) /*!< Max enumerator value of CHEN0 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Disabled (0xFUL) /*!< Active shield channel 0 is disabled. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Enabled (0x0UL) /*!< Active shield channel 0 is enabled. */ + +/* CHEN1 @Bits 4..7 : Active shield enable for channel 1. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Pos (4UL) /*!< Position of CHEN1 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Min (0x0UL) /*!< Min enumerator value of CHEN1 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Max (0xFUL) /*!< Max enumerator value of CHEN1 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Disabled (0xFUL) /*!< Active shield channel 1 is disabled. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Enabled (0x0UL) /*!< Active shield channel 1 is enabled. */ + +/* CHEN2 @Bits 8..11 : Active shield enable for channel 2. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Pos (8UL) /*!< Position of CHEN2 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Min (0x0UL) /*!< Min enumerator value of CHEN2 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Max (0xFUL) /*!< Max enumerator value of CHEN2 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Disabled (0xFUL) /*!< Active shield channel 2 is disabled. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Enabled (0x0UL) /*!< Active shield channel 2 is enabled. */ + +/* CHEN3 @Bits 12..15 : Active shield enable for channel 3. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Pos (12UL) /*!< Position of CHEN3 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Min (0x0UL) /*!< Min enumerator value of CHEN3 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Max (0xFUL) /*!< Max enumerator value of CHEN3 field. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Disabled (0xFUL) /*!< Active shield channel 3 is disabled. */ + #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Enabled (0x0UL) /*!< Active shield channel 3 is enabled. */ + + + +/* ==================================================== Struct BICR_PMIC ===================================================== */ +/** + * @brief PMIC [BICR_PMIC] (unspecified) + */ +typedef struct { + __IOM uint32_t LDOIO1V8; /*!< (@ 0x00000000) Configuration for PMIC LDO_IO1V8. */ + __IOM uint32_t LDOIO3V3; /*!< (@ 0x00000004) Configuration for PMIC LDO_IO3V3. */ +} NRF_BICR_PMIC_Type; /*!< Size = 8 (0x008) */ + +/* BICR_PMIC_LDOIO1V8: Configuration for PMIC LDO_IO1V8. */ + #define BICR_PMIC_LDOIO1V8_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LDOIO1V8 register. */ + +/* LEVEL @Bits 0..4 : PMIC LDO_IO1V8 output voltage in 100mV steps. All values above 0x0F are invalid. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_Msk (0x1FUL << BICR_PMIC_LDOIO1V8_LEVEL_Pos) /*!< Bit mask of LEVEL field. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_Min (0x0UL) /*!< Min enumerator value of LEVEL field. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_Max (0x1FUL) /*!< Max enumerator value of LEVEL field. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_1v8 (0x00UL) /*!< PMIC LDO_IO1V8 output voltage configured for 1v8 operation. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_2v6 (0x08UL) /*!< PMIC LDO_IO1V8 output voltage configured for 2v6 operation. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_3v3 (0x0FUL) /*!< PMIC LDO_IO1V8 output voltage configured for 3v3 operation. */ + #define BICR_PMIC_LDOIO1V8_LEVEL_Unconfigured (0x1FUL) /*!< PMIC LDO_IO1V8 output voltage is unconfigured. */ + +/* ONMODE @Bits 5..6 : PMIC LDO_IO1V8 operation mode during system ON. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Pos (5UL) /*!< Position of ONMODE field. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Msk (0x3UL << BICR_PMIC_LDOIO1V8_ONMODE_Pos) /*!< Bit mask of ONMODE field. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Min (0x0UL) /*!< Min enumerator value of ONMODE field. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Max (0x3UL) /*!< Max enumerator value of ONMODE field. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Normal (0x0UL) /*!< PMIC LDO_IO1V8 is configured for normal operation during system ON. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_ULP (0x1UL) /*!< PMIC LDO_IO1V8 is configured for ULP operation during system ON. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Off (0x2UL) /*!< PMIC LDO_IO1V8 is not used. */ + #define BICR_PMIC_LDOIO1V8_ONMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO1V8 mode during system ON is unconfigured. */ + +/* IDLEMODE @Bits 7..8 : PMIC LDO_IO1V8 operation mode during system ON IDLE. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Pos (7UL) /*!< Position of IDLEMODE field. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Msk (0x3UL << BICR_PMIC_LDOIO1V8_IDLEMODE_Pos) /*!< Bit mask of IDLEMODE field. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Min (0x0UL) /*!< Min enumerator value of IDLEMODE field. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Max (0x3UL) /*!< Max enumerator value of IDLEMODE field. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Normal (0x0UL) /*!< PMIC LDO_IO1V8 is configured for normal operation during system ON + IDLE.*/ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_ULP (0x1UL) /*!< PMIC LDO_IO1V8 is configured for ULP operation during system ON IDLE.*/ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Off (0x2UL) /*!< PMIC LDO_IO1V8 is forced off during system ON IDLE. */ + #define BICR_PMIC_LDOIO1V8_IDLEMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO1V8 mode during system ON IDLE is unconfigured. */ + +/* OFFMODE @Bits 9..10 : PMIC LDO_IO1V8 operation mode during system OFF. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Pos (9UL) /*!< Position of OFFMODE field. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Msk (0x3UL << BICR_PMIC_LDOIO1V8_OFFMODE_Pos) /*!< Bit mask of OFFMODE field. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Min (0x0UL) /*!< Min enumerator value of OFFMODE field. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Max (0x3UL) /*!< Max enumerator value of OFFMODE field. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Normal (0x0UL) /*!< PMIC LDO_IO1V8 is configured for normal operation during system OFF. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_ULP (0x1UL) /*!< PMIC LDO_IO1V8 is configured for ULP operation during system OFF. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Off (0x2UL) /*!< PMIC LDO_IO1V8 is forced off during system OFF. */ + #define BICR_PMIC_LDOIO1V8_OFFMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO1V8 mode for system OFF is unconfigured. */ + + +/* BICR_PMIC_LDOIO3V3: Configuration for PMIC LDO_IO3V3. */ + #define BICR_PMIC_LDOIO3V3_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LDOIO3V3 register. */ + +/* LEVEL @Bits 0..4 : PMIC LDO_IO3V3 output voltage in 100mV steps. All values above 0x0F are invalid. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_Msk (0x1FUL << BICR_PMIC_LDOIO3V3_LEVEL_Pos) /*!< Bit mask of LEVEL field. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_Min (0x0UL) /*!< Min enumerator value of LEVEL field. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_Max (0x1FUL) /*!< Max enumerator value of LEVEL field. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_1v8 (0x00UL) /*!< PMIC LDO_IO3V3 output voltage configured for 1v8 operation. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_2v6 (0x08UL) /*!< PMIC LDO_IO3V3 output voltage configured for 2v6 operation. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_3v3 (0x0FUL) /*!< PMIC LDO_IO3V3 output voltage configured for 3v3 operation. */ + #define BICR_PMIC_LDOIO3V3_LEVEL_Unconfigured (0x1FUL) /*!< PMIC LDO_IO3V3 output voltage is unconfigured. */ + +/* ONMODE @Bits 5..6 : PMIC LDO_IO3V3 operation mode during system ON. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Pos (5UL) /*!< Position of ONMODE field. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Msk (0x3UL << BICR_PMIC_LDOIO3V3_ONMODE_Pos) /*!< Bit mask of ONMODE field. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Min (0x0UL) /*!< Min enumerator value of ONMODE field. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Max (0x3UL) /*!< Max enumerator value of ONMODE field. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Normal (0x0UL) /*!< PMIC LDO_IO3V3 is configured for normal operation during system ON. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_ULP (0x1UL) /*!< PMIC LDO_IO3V3 is configured for ULP operation during system ON */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Off (0x2UL) /*!< PMIC LDO_IO3V3 is not used. */ + #define BICR_PMIC_LDOIO3V3_ONMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO3V3 mode during system ON is unconfigured. */ + +/* IDLEMODE @Bits 7..8 : PMIC LDO_IO3V3 operation mode during system ON IDLE. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Pos (7UL) /*!< Position of IDLEMODE field. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Msk (0x3UL << BICR_PMIC_LDOIO3V3_IDLEMODE_Pos) /*!< Bit mask of IDLEMODE field. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Min (0x0UL) /*!< Min enumerator value of IDLEMODE field. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Max (0x3UL) /*!< Max enumerator value of IDLEMODE field. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Normal (0x0UL) /*!< PMIC LDO_IO3V3 is configured for normal operation during system ON + IDLE.*/ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_ULP (0x1UL) /*!< PMIC LDO_IO3V3 is configured for ULP operation during system ON IDLE.*/ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Off (0x2UL) /*!< PMIC LDO_IO3V3 is forced off during system ON IDLE. */ + #define BICR_PMIC_LDOIO3V3_IDLEMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO3V3 mode during system ON IDLE is unconfigured. */ + +/* OFFMODE @Bits 9..10 : PMIC LDO_IO3V3 operation mode during system OFF. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Pos (9UL) /*!< Position of OFFMODE field. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Msk (0x3UL << BICR_PMIC_LDOIO3V3_OFFMODE_Pos) /*!< Bit mask of OFFMODE field. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Min (0x0UL) /*!< Min enumerator value of OFFMODE field. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Max (0x3UL) /*!< Max enumerator value of OFFMODE field. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Normal (0x0UL) /*!< PMIC LDO_IO3V3 is configured for normal operation during system OFF. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_ULP (0x1UL) /*!< PMIC LDO_IO3V3 is configured for ULP operation during system OFF */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Off (0x2UL) /*!< PMIC LDO_IO3V3 is forced off during system OFF. */ + #define BICR_PMIC_LDOIO3V3_OFFMODE_Unconfigured (0x3UL) /*!< PMIC LDO_IO3V3 mode for system OFF is unconfigured. */ + + +/* ======================================================= Struct BICR ======================================================= */ +/** + * @brief Board information configuration registers + */ + typedef struct { /*!< BICR Structure */ + __IM uint32_t RESERVED; + __IOM NRF_BICR_IOPORT_Type IOPORT; /*!< (@ 0x00000004) (unspecified) */ + __IM uint32_t RESERVED1; + __IOM NRF_BICR_LFOSC_Type LFOSC; /*!< (@ 0x00000018) (unspecified) */ + __IM uint32_t RESERVED2[2]; + __IOM NRF_BICR_HFXO64M_Type HFXO64M; /*!< (@ 0x0000002C) (unspecified) */ + __IOM NRF_BICR_TAMPC_Type TAMPC; /*!< (@ 0x00000034) (unspecified) */ + __IM uint32_t RESERVED3[35]; + __IOM NRF_BICR_PMIC_Type PMIC; /*!< (@ 0x000000C8) (unspecified) */ + } NRF_BICR_Type; /*!< Size = 208 (0x0D0) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CACHE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct CACHE_PROFILING ================================================== */ +/** + * @brief PROFILING [CACHE_PROFILING] (unspecified) + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) Enable the profiling counters. */ + __OM uint32_t CLEAR; /*!< (@ 0x00000004) Clear the profiling counters. */ + __IM uint32_t HIT; /*!< (@ 0x00000008) The cache hit counter for cache region. */ + __IM uint32_t MISS; /*!< (@ 0x0000000C) The cache miss counter for cache region. */ + __IM uint32_t LMISS; /*!< (@ 0x00000010) The cache line miss counter for cache region. */ + __IM uint32_t READS; /*!< (@ 0x00000014) Number of reads for cache region. */ + __IM uint32_t WRITES; /*!< (@ 0x00000018) Number of writes for cache region. */ +} NRF_CACHE_PROFILING_Type; /*!< Size = 28 (0x01C) */ + +/* CACHE_PROFILING_ENABLE: Enable the profiling counters. */ + #define CACHE_PROFILING_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable the profiling counters */ + #define CACHE_PROFILING_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILING_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CACHE_PROFILING_ENABLE_ENABLE_Disable (0x0UL) /*!< Disable profiling */ + #define CACHE_PROFILING_ENABLE_ENABLE_Enable (0x1UL) /*!< Enable profiling */ + + +/* CACHE_PROFILING_CLEAR: Clear the profiling counters. */ + #define CACHE_PROFILING_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of CLEAR register. */ + +/* CLEAR @Bit 0 : Clearing the profiling counters */ + #define CACHE_PROFILING_CLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILING_CLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Min (0x1UL) /*!< Min enumerator value of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define CACHE_PROFILING_CLEAR_CLEAR_Clear (0x1UL) /*!< Clear the profiling counters */ + + +/* CACHE_PROFILING_HIT: The cache hit counter for cache region. */ + #define CACHE_PROFILING_HIT_ResetValue (0x00000000UL) /*!< Reset value of HIT register. */ + +/* HITS @Bits 0..31 : Number of cache hits */ + #define CACHE_PROFILING_HIT_HITS_Pos (0UL) /*!< Position of HITS field. */ + #define CACHE_PROFILING_HIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_HIT_HITS_Pos) /*!< Bit mask of HITS field. */ + + +/* CACHE_PROFILING_MISS: The cache miss counter for cache region. */ + #define CACHE_PROFILING_MISS_ResetValue (0x00000000UL) /*!< Reset value of MISS register. */ + +/* MISSES @Bits 0..31 : Number of cache misses */ + #define CACHE_PROFILING_MISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ + #define CACHE_PROFILING_MISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_MISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* CACHE_PROFILING_LMISS: The cache line miss counter for cache region. */ + #define CACHE_PROFILING_LMISS_ResetValue (0x00000000UL) /*!< Reset value of LMISS register. */ + +/* LMISSES @Bits 0..31 : Number of cache line misses */ + #define CACHE_PROFILING_LMISS_LMISSES_Pos (0UL) /*!< Position of LMISSES field. */ + #define CACHE_PROFILING_LMISS_LMISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_LMISS_LMISSES_Pos) /*!< Bit mask of LMISSES field.*/ + + +/* CACHE_PROFILING_READS: Number of reads for cache region. */ + #define CACHE_PROFILING_READS_ResetValue (0x00000000UL) /*!< Reset value of READS register. */ + +/* READS @Bits 0..31 : Number of reads for cache region. */ + #define CACHE_PROFILING_READS_READS_Pos (0UL) /*!< Position of READS field. */ + #define CACHE_PROFILING_READS_READS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_READS_READS_Pos) /*!< Bit mask of READS field. */ + + +/* CACHE_PROFILING_WRITES: Number of writes for cache region. */ + #define CACHE_PROFILING_WRITES_ResetValue (0x00000000UL) /*!< Reset value of WRITES register. */ + +/* WRITES @Bits 0..31 : Number of writes for cache region. */ + #define CACHE_PROFILING_WRITES_WRITES_Pos (0UL) /*!< Position of WRITES field. */ + #define CACHE_PROFILING_WRITES_WRITES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_WRITES_WRITES_Pos) /*!< Bit mask of WRITES field. */ + + +/* ====================================================== Struct CACHE ======================================================= */ +/** + * @brief Cache + */ + typedef struct { /*!< CACHE Structure */ + __OM uint32_t TASKS_SAVE; /*!< (@ 0x00000000) Save the cache state to a retained memory space. */ + __OM uint32_t TASKS_RESTORE; /*!< (@ 0x00000004) Restore the cache state from a retained memory space. */ + __OM uint32_t TASKS_INVALIDATECACHE; /*!< (@ 0x00000008) Invalidate the cache. */ + __OM uint32_t TASKS_CLEANCACHE; /*!< (@ 0x0000000C) Clean the cache. */ + __OM uint32_t TASKS_FLUSHCACHE; /*!< (@ 0x00000010) Flush the cache. */ + __OM uint32_t TASKS_INVALIDATELINE; /*!< (@ 0x00000014) Invalidate the line. */ + __OM uint32_t TASKS_CLEANLINE; /*!< (@ 0x00000018) Clean the line. */ + __OM uint32_t TASKS_FLUSHLINE; /*!< (@ 0x0000001C) Flush the line. */ + __OM uint32_t TASKS_ERASE; /*!< (@ 0x00000020) Erase the cache. */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000100) Save or Restore task is done. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status of the cache activities. */ + __IOM uint32_t ENABLE; /*!< (@ 0x00000404) Enable cache. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t LINEADDR; /*!< (@ 0x00000410) Memory address covered by the line to be maintained. */ + __IOM NRF_CACHE_PROFILING_Type PROFILING; /*!< (@ 0x00000414) (unspecified) */ + __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000430) Lock debug mode. */ + __IOM uint32_t WRITELOCK; /*!< (@ 0x00000434) Lock cache updates. */ + } NRF_CACHE_Type; /*!< Size = 1080 (0x438) */ + +/* CACHE_TASKS_SAVE: Save the cache state to a retained memory space. */ + #define CACHE_TASKS_SAVE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAVE register. */ + +/* TASKS_SAVE @Bit 0 : Save the cache state to a retained memory space. */ + #define CACHE_TASKS_SAVE_TASKS_SAVE_Pos (0UL) /*!< Position of TASKS_SAVE field. */ + #define CACHE_TASKS_SAVE_TASKS_SAVE_Msk (0x1UL << CACHE_TASKS_SAVE_TASKS_SAVE_Pos) /*!< Bit mask of TASKS_SAVE field. */ + #define CACHE_TASKS_SAVE_TASKS_SAVE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAVE field. */ + #define CACHE_TASKS_SAVE_TASKS_SAVE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAVE field. */ + #define CACHE_TASKS_SAVE_TASKS_SAVE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_RESTORE: Restore the cache state from a retained memory space. */ + #define CACHE_TASKS_RESTORE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESTORE register. */ + +/* TASKS_RESTORE @Bit 0 : Restore the cache state from a retained memory space. */ + #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Pos (0UL) /*!< Position of TASKS_RESTORE field. */ + #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Msk (0x1UL << CACHE_TASKS_RESTORE_TASKS_RESTORE_Pos) /*!< Bit mask of TASKS_RESTORE + field.*/ + #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Min (0x1UL) /*!< Min enumerator value of TASKS_RESTORE field. */ + #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Max (0x1UL) /*!< Max enumerator value of TASKS_RESTORE field. */ + #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_INVALIDATECACHE: Invalidate the cache. */ + #define CACHE_TASKS_INVALIDATECACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATECACHE register. */ + +/* TASKS_INVALIDATECACHE @Bit 0 : Invalidate the cache. */ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos (0UL) /*!< Position of TASKS_INVALIDATECACHE field. */ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Msk (0x1UL << CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos) + /*!< Bit mask of TASKS_INVALIDATECACHE field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATECACHE + field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATECACHE + field.*/ + #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_CLEANCACHE: Clean the cache. */ + #define CACHE_TASKS_CLEANCACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEANCACHE register. */ + +/* TASKS_CLEANCACHE @Bit 0 : Clean the cache. */ + #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Pos (0UL) /*!< Position of TASKS_CLEANCACHE field. */ + #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Msk (0x1UL << CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Pos) /*!< Bit mask of + TASKS_CLEANCACHE field.*/ + #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEANCACHE field. */ + #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEANCACHE field. */ + #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_FLUSHCACHE: Flush the cache. */ + #define CACHE_TASKS_FLUSHCACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHCACHE register. */ + +/* TASKS_FLUSHCACHE @Bit 0 : Flush the cache. */ + #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Pos (0UL) /*!< Position of TASKS_FLUSHCACHE field. */ + #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Msk (0x1UL << CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Pos) /*!< Bit mask of + TASKS_FLUSHCACHE field.*/ + #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHCACHE field. */ + #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHCACHE field. */ + #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_INVALIDATELINE: Invalidate the line. */ + #define CACHE_TASKS_INVALIDATELINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATELINE register. */ + +/* TASKS_INVALIDATELINE @Bit 0 : Invalidate the line. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos (0UL) /*!< Position of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Msk (0x1UL << CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos) + /*!< Bit mask of TASKS_INVALIDATELINE field.*/ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATELINE field. */ + #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_CLEANLINE: Clean the line. */ + #define CACHE_TASKS_CLEANLINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEANLINE register. */ + +/* TASKS_CLEANLINE @Bit 0 : Clean the line. */ + #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Pos (0UL) /*!< Position of TASKS_CLEANLINE field. */ + #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Msk (0x1UL << CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Pos) /*!< Bit mask of + TASKS_CLEANLINE field.*/ + #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEANLINE field. */ + #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEANLINE field. */ + #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_FLUSHLINE: Flush the line. */ + #define CACHE_TASKS_FLUSHLINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHLINE register. */ + +/* TASKS_FLUSHLINE @Bit 0 : Flush the line. */ + #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Pos (0UL) /*!< Position of TASKS_FLUSHLINE field. */ + #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Msk (0x1UL << CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Pos) /*!< Bit mask of + TASKS_FLUSHLINE field.*/ + #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHLINE field. */ + #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHLINE field. */ + #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_TASKS_ERASE: Erase the cache. */ + #define CACHE_TASKS_ERASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ERASE register. */ + +/* TASKS_ERASE @Bit 0 : Erase the cache. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Pos (0UL) /*!< Position of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Msk (0x1UL << CACHE_TASKS_ERASE_TASKS_ERASE_Pos) /*!< Bit mask of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Min (0x1UL) /*!< Min enumerator value of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Max (0x1UL) /*!< Max enumerator value of TASKS_ERASE field. */ + #define CACHE_TASKS_ERASE_TASKS_ERASE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CACHE_EVENTS_DONE: Save or Restore task is done. */ + #define CACHE_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register. */ + +/* EVENTS_DONE @Bit 0 : Save or Restore task is done. */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CACHE_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_DONE field. */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_DONE field. */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define CACHE_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ + + +/* CACHE_INTEN: Enable or disable interrupt */ + #define CACHE_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* DONE @Bit 0 : Enable or disable interrupt for event DONE */ + #define CACHE_INTEN_DONE_Pos (0UL) /*!< Position of DONE field. */ + #define CACHE_INTEN_DONE_Msk (0x1UL << CACHE_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CACHE_INTEN_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CACHE_INTEN_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CACHE_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ + #define CACHE_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ + + +/* CACHE_INTENSET: Enable interrupt */ + #define CACHE_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* DONE @Bit 0 : Write '1' to enable interrupt for event DONE */ + #define CACHE_INTENSET_DONE_Pos (0UL) /*!< Position of DONE field. */ + #define CACHE_INTENSET_DONE_Msk (0x1UL << CACHE_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CACHE_INTENSET_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CACHE_INTENSET_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CACHE_INTENSET_DONE_Set (0x1UL) /*!< Enable */ + #define CACHE_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CACHE_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CACHE_INTENCLR: Disable interrupt */ + #define CACHE_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* DONE @Bit 0 : Write '1' to disable interrupt for event DONE */ + #define CACHE_INTENCLR_DONE_Pos (0UL) /*!< Position of DONE field. */ + #define CACHE_INTENCLR_DONE_Msk (0x1UL << CACHE_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CACHE_INTENCLR_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CACHE_INTENCLR_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CACHE_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ + #define CACHE_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CACHE_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CACHE_INTPEND: Pending interrupts */ + #define CACHE_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* DONE @Bit 0 : Read pending status of interrupt for event DONE */ + #define CACHE_INTPEND_DONE_Pos (0UL) /*!< Position of DONE field. */ + #define CACHE_INTPEND_DONE_Msk (0x1UL << CACHE_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */ + #define CACHE_INTPEND_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define CACHE_INTPEND_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define CACHE_INTPEND_DONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define CACHE_INTPEND_DONE_Pending (0x1UL) /*!< Read: Pending */ + + +/* CACHE_STATUS: Status of the cache activities. */ + #define CACHE_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* BUSY @Bit 0 : Busy status. */ + #define CACHE_STATUS_BUSY_Pos (0UL) /*!< Position of BUSY field. */ + #define CACHE_STATUS_BUSY_Msk (0x1UL << CACHE_STATUS_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define CACHE_STATUS_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define CACHE_STATUS_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define CACHE_STATUS_BUSY_Ready (0x0UL) /*!< Activity is done and ready for the next activity. */ + #define CACHE_STATUS_BUSY_Busy (0x1UL) /*!< Activity is in progress. */ + + +/* CACHE_ENABLE: Enable cache. */ + #define CACHE_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable cache */ + #define CACHE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define CACHE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable cache */ + #define CACHE_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable cache */ + + +/* CACHE_LINEADDR: Memory address covered by the line to be maintained. */ + #define CACHE_LINEADDR_ResetValue (0x00000000UL) /*!< Reset value of LINEADDR register. */ + +/* ADDR @Bits 0..31 : Address. */ + #define CACHE_LINEADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define CACHE_LINEADDR_ADDR_Msk (0xFFFFFFFFUL << CACHE_LINEADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* CACHE_DEBUGLOCK: Lock debug mode. */ + #define CACHE_DEBUGLOCK_ResetValue (0x00000000UL) /*!< Reset value of DEBUGLOCK register. */ + +/* DEBUGLOCK @Bit 0 : Lock debug mode */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL) /*!< Position of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Min (0x0UL) /*!< Min enumerator value of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Max (0x1UL) /*!< Max enumerator value of DEBUGLOCK field. */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0x0UL) /*!< Debug mode unlocked */ + #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (0x1UL) /*!< Debug mode locked. Ignores any other value written. */ + + +/* CACHE_WRITELOCK: Lock cache updates. */ + #define CACHE_WRITELOCK_ResetValue (0x00000000UL) /*!< Reset value of WRITELOCK register. */ + +/* WRITELOCK @Bit 0 : Lock cache updates */ + #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL) /*!< Position of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Min (0x0UL) /*!< Min enumerator value of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Max (0x1UL) /*!< Max enumerator value of WRITELOCK field. */ + #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0x0UL) /*!< Cache updates unlocked */ + #define CACHE_WRITELOCK_WRITELOCK_Locked (0x1UL) /*!< Cache updates locked */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CAN ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct CAN ======================================================== */ +/** + * @brief Controller Area Network + */ + typedef struct { /*!< CAN Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the CAN peripheral. */ + __OM uint32_t TASKS_STOPREQ; /*!< (@ 0x00000004) Request to stop the CAN peripheral */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the CAN peripheral */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_CORE[2]; /*!< (@ 0x00000100) Event indicating that interrupt n triggered at CAN + core*/ + __IOM uint32_t EVENTS_DMU; /*!< (@ 0x00000108) Event indicating that interrupt triggered at CAN DMU */ + __IOM uint32_t EVENTS_DMA; /*!< (@ 0x0000010C) Event indicating that interrupt triggered at CAN DMA */ + __IOM uint32_t EVENTS_READYFORSTOP; /*!< (@ 0x00000110) Event indicating that the CAN is ready to be stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + } NRF_CAN_Type; /*!< Size = 784 (0x310) */ + +/* CAN_TASKS_START: Start the CAN peripheral. */ + #define CAN_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the CAN peripheral. */ + #define CAN_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define CAN_TASKS_START_TASKS_START_Msk (0x1UL << CAN_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define CAN_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define CAN_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define CAN_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* CAN_TASKS_STOPREQ: Request to stop the CAN peripheral */ + #define CAN_TASKS_STOPREQ_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPREQ register. */ + +/* TASKS_STOPREQ @Bit 0 : Request to stop the CAN peripheral */ + #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Pos (0UL) /*!< Position of TASKS_STOPREQ field. */ + #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Msk (0x1UL << CAN_TASKS_STOPREQ_TASKS_STOPREQ_Pos) /*!< Bit mask of TASKS_STOPREQ + field.*/ + #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPREQ field. */ + #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPREQ field. */ + #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Trigger (0x1UL) /*!< Trigger task */ + + +/* CAN_TASKS_STOP: Stop the CAN peripheral */ + #define CAN_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the CAN peripheral */ + #define CAN_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define CAN_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CAN_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define CAN_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define CAN_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define CAN_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CAN_EVENTS_CORE: Event indicating that interrupt n triggered at CAN core */ + #define CAN_EVENTS_CORE_MaxCount (2UL) /*!< Max size of EVENTS_CORE[2] array. */ + #define CAN_EVENTS_CORE_MaxIndex (1UL) /*!< Max index of EVENTS_CORE[2] array. */ + #define CAN_EVENTS_CORE_MinIndex (0UL) /*!< Min index of EVENTS_CORE[2] array. */ + #define CAN_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE[2] register. */ + +/* EVENTS_CORE @Bit 0 : Event indicating that interrupt n triggered at CAN core */ + #define CAN_EVENTS_CORE_EVENTS_CORE_Pos (0UL) /*!< Position of EVENTS_CORE field. */ + #define CAN_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << CAN_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ + #define CAN_EVENTS_CORE_EVENTS_CORE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ + #define CAN_EVENTS_CORE_EVENTS_CORE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ + #define CAN_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated */ + #define CAN_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated */ + + +/* CAN_EVENTS_DMU: Event indicating that interrupt triggered at CAN DMU */ + #define CAN_EVENTS_DMU_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DMU register. */ + +/* EVENTS_DMU @Bit 0 : Event indicating that interrupt triggered at CAN DMU */ + #define CAN_EVENTS_DMU_EVENTS_DMU_Pos (0UL) /*!< Position of EVENTS_DMU field. */ + #define CAN_EVENTS_DMU_EVENTS_DMU_Msk (0x1UL << CAN_EVENTS_DMU_EVENTS_DMU_Pos) /*!< Bit mask of EVENTS_DMU field. */ + #define CAN_EVENTS_DMU_EVENTS_DMU_Min (0x0UL) /*!< Min enumerator value of EVENTS_DMU field. */ + #define CAN_EVENTS_DMU_EVENTS_DMU_Max (0x1UL) /*!< Max enumerator value of EVENTS_DMU field. */ + #define CAN_EVENTS_DMU_EVENTS_DMU_NotGenerated (0x0UL) /*!< Event not generated */ + #define CAN_EVENTS_DMU_EVENTS_DMU_Generated (0x1UL) /*!< Event generated */ + + +/* CAN_EVENTS_DMA: Event indicating that interrupt triggered at CAN DMA */ + #define CAN_EVENTS_DMA_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DMA register. */ + +/* EVENTS_DMA @Bit 0 : Event indicating that interrupt triggered at CAN DMA */ + #define CAN_EVENTS_DMA_EVENTS_DMA_Pos (0UL) /*!< Position of EVENTS_DMA field. */ + #define CAN_EVENTS_DMA_EVENTS_DMA_Msk (0x1UL << CAN_EVENTS_DMA_EVENTS_DMA_Pos) /*!< Bit mask of EVENTS_DMA field. */ + #define CAN_EVENTS_DMA_EVENTS_DMA_Min (0x0UL) /*!< Min enumerator value of EVENTS_DMA field. */ + #define CAN_EVENTS_DMA_EVENTS_DMA_Max (0x1UL) /*!< Max enumerator value of EVENTS_DMA field. */ + #define CAN_EVENTS_DMA_EVENTS_DMA_NotGenerated (0x0UL) /*!< Event not generated */ + #define CAN_EVENTS_DMA_EVENTS_DMA_Generated (0x1UL) /*!< Event generated */ + + +/* CAN_EVENTS_READYFORSTOP: Event indicating that the CAN is ready to be stopped */ + #define CAN_EVENTS_READYFORSTOP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READYFORSTOP register. */ + +/* EVENTS_READYFORSTOP @Bit 0 : Event indicating that the CAN is ready to be stopped */ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Pos (0UL) /*!< Position of EVENTS_READYFORSTOP field. */ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Msk (0x1UL << CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Pos) /*!< Bit + mask of EVENTS_READYFORSTOP field.*/ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of EVENTS_READYFORSTOP field. */ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of EVENTS_READYFORSTOP field. */ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_NotGenerated (0x0UL) /*!< Event not generated */ + #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Generated (0x1UL) /*!< Event generated */ + + +/* CAN_SHORTS: Shortcuts between local events and tasks */ + #define CAN_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READYFORSTOP_STOP @Bit 0 : Shortcut between event READYFORSTOP and task STOP */ + #define CAN_SHORTS_READYFORSTOP_STOP_Pos (0UL) /*!< Position of READYFORSTOP_STOP field. */ + #define CAN_SHORTS_READYFORSTOP_STOP_Msk (0x1UL << CAN_SHORTS_READYFORSTOP_STOP_Pos) /*!< Bit mask of READYFORSTOP_STOP + field.*/ + #define CAN_SHORTS_READYFORSTOP_STOP_Min (0x0UL) /*!< Min enumerator value of READYFORSTOP_STOP field. */ + #define CAN_SHORTS_READYFORSTOP_STOP_Max (0x1UL) /*!< Max enumerator value of READYFORSTOP_STOP field. */ + #define CAN_SHORTS_READYFORSTOP_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define CAN_SHORTS_READYFORSTOP_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* CAN_INTEN: Enable or disable interrupt */ + #define CAN_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CORE0 @Bit 0 : Enable or disable interrupt for event CORE[0] */ + #define CAN_INTEN_CORE0_Pos (0UL) /*!< Position of CORE0 field. */ + #define CAN_INTEN_CORE0_Msk (0x1UL << CAN_INTEN_CORE0_Pos) /*!< Bit mask of CORE0 field. */ + #define CAN_INTEN_CORE0_Min (0x0UL) /*!< Min enumerator value of CORE0 field. */ + #define CAN_INTEN_CORE0_Max (0x1UL) /*!< Max enumerator value of CORE0 field. */ + #define CAN_INTEN_CORE0_Disabled (0x0UL) /*!< Disable */ + #define CAN_INTEN_CORE0_Enabled (0x1UL) /*!< Enable */ + +/* CORE1 @Bit 1 : Enable or disable interrupt for event CORE[1] */ + #define CAN_INTEN_CORE1_Pos (1UL) /*!< Position of CORE1 field. */ + #define CAN_INTEN_CORE1_Msk (0x1UL << CAN_INTEN_CORE1_Pos) /*!< Bit mask of CORE1 field. */ + #define CAN_INTEN_CORE1_Min (0x0UL) /*!< Min enumerator value of CORE1 field. */ + #define CAN_INTEN_CORE1_Max (0x1UL) /*!< Max enumerator value of CORE1 field. */ + #define CAN_INTEN_CORE1_Disabled (0x0UL) /*!< Disable */ + #define CAN_INTEN_CORE1_Enabled (0x1UL) /*!< Enable */ + +/* DMU @Bit 2 : Enable or disable interrupt for event DMU */ + #define CAN_INTEN_DMU_Pos (2UL) /*!< Position of DMU field. */ + #define CAN_INTEN_DMU_Msk (0x1UL << CAN_INTEN_DMU_Pos) /*!< Bit mask of DMU field. */ + #define CAN_INTEN_DMU_Min (0x0UL) /*!< Min enumerator value of DMU field. */ + #define CAN_INTEN_DMU_Max (0x1UL) /*!< Max enumerator value of DMU field. */ + #define CAN_INTEN_DMU_Disabled (0x0UL) /*!< Disable */ + #define CAN_INTEN_DMU_Enabled (0x1UL) /*!< Enable */ + +/* DMA @Bit 3 : Enable or disable interrupt for event DMA */ + #define CAN_INTEN_DMA_Pos (3UL) /*!< Position of DMA field. */ + #define CAN_INTEN_DMA_Msk (0x1UL << CAN_INTEN_DMA_Pos) /*!< Bit mask of DMA field. */ + #define CAN_INTEN_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define CAN_INTEN_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define CAN_INTEN_DMA_Disabled (0x0UL) /*!< Disable */ + #define CAN_INTEN_DMA_Enabled (0x1UL) /*!< Enable */ + +/* READYFORSTOP @Bit 4 : Enable or disable interrupt for event READYFORSTOP */ + #define CAN_INTEN_READYFORSTOP_Pos (4UL) /*!< Position of READYFORSTOP field. */ + #define CAN_INTEN_READYFORSTOP_Msk (0x1UL << CAN_INTEN_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field. */ + #define CAN_INTEN_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of READYFORSTOP field. */ + #define CAN_INTEN_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of READYFORSTOP field. */ + #define CAN_INTEN_READYFORSTOP_Disabled (0x0UL) /*!< Disable */ + #define CAN_INTEN_READYFORSTOP_Enabled (0x1UL) /*!< Enable */ + + +/* CAN_INTENSET: Enable interrupt */ + #define CAN_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CORE0 @Bit 0 : Write '1' to enable interrupt for event CORE[0] */ + #define CAN_INTENSET_CORE0_Pos (0UL) /*!< Position of CORE0 field. */ + #define CAN_INTENSET_CORE0_Msk (0x1UL << CAN_INTENSET_CORE0_Pos) /*!< Bit mask of CORE0 field. */ + #define CAN_INTENSET_CORE0_Min (0x0UL) /*!< Min enumerator value of CORE0 field. */ + #define CAN_INTENSET_CORE0_Max (0x1UL) /*!< Max enumerator value of CORE0 field. */ + #define CAN_INTENSET_CORE0_Set (0x1UL) /*!< Enable */ + #define CAN_INTENSET_CORE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENSET_CORE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CORE1 @Bit 1 : Write '1' to enable interrupt for event CORE[1] */ + #define CAN_INTENSET_CORE1_Pos (1UL) /*!< Position of CORE1 field. */ + #define CAN_INTENSET_CORE1_Msk (0x1UL << CAN_INTENSET_CORE1_Pos) /*!< Bit mask of CORE1 field. */ + #define CAN_INTENSET_CORE1_Min (0x0UL) /*!< Min enumerator value of CORE1 field. */ + #define CAN_INTENSET_CORE1_Max (0x1UL) /*!< Max enumerator value of CORE1 field. */ + #define CAN_INTENSET_CORE1_Set (0x1UL) /*!< Enable */ + #define CAN_INTENSET_CORE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENSET_CORE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMU @Bit 2 : Write '1' to enable interrupt for event DMU */ + #define CAN_INTENSET_DMU_Pos (2UL) /*!< Position of DMU field. */ + #define CAN_INTENSET_DMU_Msk (0x1UL << CAN_INTENSET_DMU_Pos) /*!< Bit mask of DMU field. */ + #define CAN_INTENSET_DMU_Min (0x0UL) /*!< Min enumerator value of DMU field. */ + #define CAN_INTENSET_DMU_Max (0x1UL) /*!< Max enumerator value of DMU field. */ + #define CAN_INTENSET_DMU_Set (0x1UL) /*!< Enable */ + #define CAN_INTENSET_DMU_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENSET_DMU_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMA @Bit 3 : Write '1' to enable interrupt for event DMA */ + #define CAN_INTENSET_DMA_Pos (3UL) /*!< Position of DMA field. */ + #define CAN_INTENSET_DMA_Msk (0x1UL << CAN_INTENSET_DMA_Pos) /*!< Bit mask of DMA field. */ + #define CAN_INTENSET_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define CAN_INTENSET_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define CAN_INTENSET_DMA_Set (0x1UL) /*!< Enable */ + #define CAN_INTENSET_DMA_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENSET_DMA_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READYFORSTOP @Bit 4 : Write '1' to enable interrupt for event READYFORSTOP */ + #define CAN_INTENSET_READYFORSTOP_Pos (4UL) /*!< Position of READYFORSTOP field. */ + #define CAN_INTENSET_READYFORSTOP_Msk (0x1UL << CAN_INTENSET_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field. */ + #define CAN_INTENSET_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of READYFORSTOP field. */ + #define CAN_INTENSET_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of READYFORSTOP field. */ + #define CAN_INTENSET_READYFORSTOP_Set (0x1UL) /*!< Enable */ + #define CAN_INTENSET_READYFORSTOP_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENSET_READYFORSTOP_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CAN_INTENCLR: Disable interrupt */ + #define CAN_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CORE0 @Bit 0 : Write '1' to disable interrupt for event CORE[0] */ + #define CAN_INTENCLR_CORE0_Pos (0UL) /*!< Position of CORE0 field. */ + #define CAN_INTENCLR_CORE0_Msk (0x1UL << CAN_INTENCLR_CORE0_Pos) /*!< Bit mask of CORE0 field. */ + #define CAN_INTENCLR_CORE0_Min (0x0UL) /*!< Min enumerator value of CORE0 field. */ + #define CAN_INTENCLR_CORE0_Max (0x1UL) /*!< Max enumerator value of CORE0 field. */ + #define CAN_INTENCLR_CORE0_Clear (0x1UL) /*!< Disable */ + #define CAN_INTENCLR_CORE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENCLR_CORE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CORE1 @Bit 1 : Write '1' to disable interrupt for event CORE[1] */ + #define CAN_INTENCLR_CORE1_Pos (1UL) /*!< Position of CORE1 field. */ + #define CAN_INTENCLR_CORE1_Msk (0x1UL << CAN_INTENCLR_CORE1_Pos) /*!< Bit mask of CORE1 field. */ + #define CAN_INTENCLR_CORE1_Min (0x0UL) /*!< Min enumerator value of CORE1 field. */ + #define CAN_INTENCLR_CORE1_Max (0x1UL) /*!< Max enumerator value of CORE1 field. */ + #define CAN_INTENCLR_CORE1_Clear (0x1UL) /*!< Disable */ + #define CAN_INTENCLR_CORE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENCLR_CORE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMU @Bit 2 : Write '1' to disable interrupt for event DMU */ + #define CAN_INTENCLR_DMU_Pos (2UL) /*!< Position of DMU field. */ + #define CAN_INTENCLR_DMU_Msk (0x1UL << CAN_INTENCLR_DMU_Pos) /*!< Bit mask of DMU field. */ + #define CAN_INTENCLR_DMU_Min (0x0UL) /*!< Min enumerator value of DMU field. */ + #define CAN_INTENCLR_DMU_Max (0x1UL) /*!< Max enumerator value of DMU field. */ + #define CAN_INTENCLR_DMU_Clear (0x1UL) /*!< Disable */ + #define CAN_INTENCLR_DMU_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENCLR_DMU_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMA @Bit 3 : Write '1' to disable interrupt for event DMA */ + #define CAN_INTENCLR_DMA_Pos (3UL) /*!< Position of DMA field. */ + #define CAN_INTENCLR_DMA_Msk (0x1UL << CAN_INTENCLR_DMA_Pos) /*!< Bit mask of DMA field. */ + #define CAN_INTENCLR_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define CAN_INTENCLR_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define CAN_INTENCLR_DMA_Clear (0x1UL) /*!< Disable */ + #define CAN_INTENCLR_DMA_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENCLR_DMA_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READYFORSTOP @Bit 4 : Write '1' to disable interrupt for event READYFORSTOP */ + #define CAN_INTENCLR_READYFORSTOP_Pos (4UL) /*!< Position of READYFORSTOP field. */ + #define CAN_INTENCLR_READYFORSTOP_Msk (0x1UL << CAN_INTENCLR_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field. */ + #define CAN_INTENCLR_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of READYFORSTOP field. */ + #define CAN_INTENCLR_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of READYFORSTOP field. */ + #define CAN_INTENCLR_READYFORSTOP_Clear (0x1UL) /*!< Disable */ + #define CAN_INTENCLR_READYFORSTOP_Disabled (0x0UL) /*!< Read: Disabled */ + #define CAN_INTENCLR_READYFORSTOP_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CAN_INTPEND: Pending interrupts */ + #define CAN_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* CORE0 @Bit 0 : Read pending status of interrupt for event CORE[0] */ + #define CAN_INTPEND_CORE0_Pos (0UL) /*!< Position of CORE0 field. */ + #define CAN_INTPEND_CORE0_Msk (0x1UL << CAN_INTPEND_CORE0_Pos) /*!< Bit mask of CORE0 field. */ + #define CAN_INTPEND_CORE0_Min (0x0UL) /*!< Min enumerator value of CORE0 field. */ + #define CAN_INTPEND_CORE0_Max (0x1UL) /*!< Max enumerator value of CORE0 field. */ + #define CAN_INTPEND_CORE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define CAN_INTPEND_CORE0_Pending (0x1UL) /*!< Read: Pending */ + +/* CORE1 @Bit 1 : Read pending status of interrupt for event CORE[1] */ + #define CAN_INTPEND_CORE1_Pos (1UL) /*!< Position of CORE1 field. */ + #define CAN_INTPEND_CORE1_Msk (0x1UL << CAN_INTPEND_CORE1_Pos) /*!< Bit mask of CORE1 field. */ + #define CAN_INTPEND_CORE1_Min (0x0UL) /*!< Min enumerator value of CORE1 field. */ + #define CAN_INTPEND_CORE1_Max (0x1UL) /*!< Max enumerator value of CORE1 field. */ + #define CAN_INTPEND_CORE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define CAN_INTPEND_CORE1_Pending (0x1UL) /*!< Read: Pending */ + +/* DMU @Bit 2 : Read pending status of interrupt for event DMU */ + #define CAN_INTPEND_DMU_Pos (2UL) /*!< Position of DMU field. */ + #define CAN_INTPEND_DMU_Msk (0x1UL << CAN_INTPEND_DMU_Pos) /*!< Bit mask of DMU field. */ + #define CAN_INTPEND_DMU_Min (0x0UL) /*!< Min enumerator value of DMU field. */ + #define CAN_INTPEND_DMU_Max (0x1UL) /*!< Max enumerator value of DMU field. */ + #define CAN_INTPEND_DMU_NotPending (0x0UL) /*!< Read: Not pending */ + #define CAN_INTPEND_DMU_Pending (0x1UL) /*!< Read: Pending */ + +/* DMA @Bit 3 : Read pending status of interrupt for event DMA */ + #define CAN_INTPEND_DMA_Pos (3UL) /*!< Position of DMA field. */ + #define CAN_INTPEND_DMA_Msk (0x1UL << CAN_INTPEND_DMA_Pos) /*!< Bit mask of DMA field. */ + #define CAN_INTPEND_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define CAN_INTPEND_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define CAN_INTPEND_DMA_NotPending (0x0UL) /*!< Read: Not pending */ + #define CAN_INTPEND_DMA_Pending (0x1UL) /*!< Read: Pending */ + +/* READYFORSTOP @Bit 4 : Read pending status of interrupt for event READYFORSTOP */ + #define CAN_INTPEND_READYFORSTOP_Pos (4UL) /*!< Position of READYFORSTOP field. */ + #define CAN_INTPEND_READYFORSTOP_Msk (0x1UL << CAN_INTPEND_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field. */ + #define CAN_INTPEND_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of READYFORSTOP field. */ + #define CAN_INTPEND_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of READYFORSTOP field. */ + #define CAN_INTPEND_READYFORSTOP_NotPending (0x0UL) /*!< Read: Not pending */ + #define CAN_INTPEND_READYFORSTOP_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct CCM_KEY ====================================================== */ +/** + * @brief KEY [CCM_KEY] (unspecified) + */ +typedef struct { + __OM uint32_t VALUE[4]; /*!< (@ 0x00000000) 128-bit AES key */ +} NRF_CCM_KEY_Type; /*!< Size = 16 (0x010) */ + +/* CCM_KEY_VALUE: 128-bit AES key */ + #define CCM_KEY_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define CCM_KEY_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define CCM_KEY_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define CCM_KEY_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(i+1))-1 : (32*i) */ + #define CCM_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define CCM_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ==================================================== Struct CCM_NONCE ===================================================== */ +/** + * @brief NONCE [CCM_NONCE] (unspecified) + */ +typedef struct { + __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) 13-byte NONCE vector Only the lower 13 bytes are used */ +} NRF_CCM_NONCE_Type; /*!< Size = 16 (0x010) */ + +/* CCM_NONCE_VALUE: 13-byte NONCE vector Only the lower 13 bytes are used */ + #define CCM_NONCE_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define CCM_NONCE_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define CCM_NONCE_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define CCM_NONCE_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : NONCE value, bits (32*(n+1))-1 : (32*n) */ + #define CCM_NONCE_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define CCM_NONCE_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_NONCE_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ====================================================== Struct CCM_IN ====================================================== */ +/** + * @brief IN [CCM_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer Points to a job list containing + unencrypted CCM data structure in Encryption mode + Points to a job list containing encrypted CCM data + structure in Decryption mode*/ +} NRF_CCM_IN_Type; /*!< Size = 4 (0x004) */ + +/* CCM_IN_PTR: Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job + list containing encrypted CCM data structure in Decryption mode */ + + #define CCM_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Input pointer */ + #define CCM_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define CCM_IN_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct CCM_OUT ====================================================== */ +/** + * @brief OUT [CCM_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer Points to a job list containing + encrypted CCM data structure in Encryption mode Points + to a job list containing decrypted CCM data structure + in Decryption mode*/ +} NRF_CCM_OUT_Type; /*!< Size = 4 (0x004) */ + +/* CCM_OUT_PTR: Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job + list containing decrypted CCM data structure in Decryption mode */ + + #define CCM_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define CCM_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define CCM_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* ======================================================= Struct CCM ======================================================== */ +/** + * @brief AES CCM Mode Encryption + */ + typedef struct { /*!< CCM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start encryption/decryption. This operation will stop + by itself when completed.*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x00000008) Override DATARATE setting in MODE register with the + contents of the RATEOVERRIDE register for any ongoing + encryption/decryption*/ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x00000088) Subscribe configuration for task RATEOVERRIDE */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Encrypt/decrypt complete or ended because of an error */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Publish configuration for event ERROR */ + __IM uint32_t RESERVED3[94]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t MACSTATUS; /*!< (@ 0x00000400) MAC check result */ + __IM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) Error status */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IM uint32_t RESERVED6[2]; + __IOM NRF_CCM_KEY_Type KEY; /*!< (@ 0x00000510) (unspecified) */ + __IOM NRF_CCM_NONCE_Type NONCE; /*!< (@ 0x00000520) (unspecified) */ + __IOM NRF_CCM_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IM uint32_t RESERVED7; + __IOM NRF_CCM_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x00000544) Data rate override setting. */ + __IOM uint32_t ADATAMASK; /*!< (@ 0x00000548) CCM adata mask. */ + } NRF_CCM_Type; /*!< Size = 1356 (0x54C) */ + +/* CCM_TASKS_START: Start encryption/decryption. This operation will stop by itself when completed. */ + #define CCM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ + #define CCM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Msk (0x1UL << CCM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define CCM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_TASKS_STOP: Stop encryption/decryption */ + #define CCM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop encryption/decryption */ + #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define CCM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_TASKS_RATEOVERRIDE: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any + ongoing encryption/decryption */ + + #define CCM_TASKS_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RATEOVERRIDE register. */ + +/* TASKS_RATEOVERRIDE @Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any + ongoing encryption/decryption */ + + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask + of TASKS_RATEOVERRIDE field.*/ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Min (0x1UL) /*!< Min enumerator value of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Max (0x1UL) /*!< Max enumerator value of TASKS_RATEOVERRIDE field. */ + #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (0x1UL) /*!< Trigger task */ + + +/* CCM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define CCM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define CCM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Msk (0x1UL << CCM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define CCM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_SUBSCRIBE_RATEOVERRIDE: Subscribe configuration for task RATEOVERRIDE */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RATEOVERRIDE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RATEOVERRIDE will subscribe to */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* CCM_EVENTS_END: Encrypt/decrypt complete or ended because of an error */ + #define CCM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Encrypt/decrypt complete or ended because of an error */ + #define CCM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Msk (0x1UL << CCM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define CCM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define CCM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* CCM_EVENTS_ERROR: CCM error event */ + #define CCM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : CCM error event */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* CCM_PUBLISH_END: Publish configuration for event END */ + #define CCM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define CCM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Msk (0xFFUL << CCM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_PUBLISH_END_EN_Msk (0x1UL << CCM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CCM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CCM_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define CCM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define CCM_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define CCM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define CCM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* CCM_INTENSET: Enable interrupt */ + #define CCM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define CCM_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define CCM_INTENSET_END_Msk (0x1UL << CCM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define CCM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define CCM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define CCM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define CCM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 2 : Write '1' to enable interrupt for event ERROR */ + #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ + #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define CCM_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define CCM_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define CCM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define CCM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CCM_INTENCLR: Disable interrupt */ + #define CCM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define CCM_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define CCM_INTENCLR_END_Msk (0x1UL << CCM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define CCM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define CCM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define CCM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define CCM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 2 : Write '1' to disable interrupt for event ERROR */ + #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ + #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define CCM_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define CCM_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define CCM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define CCM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define CCM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CCM_MACSTATUS: MAC check result */ + #define CCM_MACSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MACSTATUS register. */ + +/* MACSTATUS @Bit 0 : The result of the MAC check performed during the previous decryption operation */ + #define CCM_MACSTATUS_MACSTATUS_Pos (0UL) /*!< Position of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Msk (0x1UL << CCM_MACSTATUS_MACSTATUS_Pos) /*!< Bit mask of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Min (0x0UL) /*!< Min enumerator value of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_Max (0x1UL) /*!< Max enumerator value of MACSTATUS field. */ + #define CCM_MACSTATUS_MACSTATUS_CheckFailed (0x0UL) /*!< MAC check failed */ + #define CCM_MACSTATUS_MACSTATUS_CheckPassed (0x1UL) /*!< MAC check passed */ + + +/* CCM_ERRORSTATUS: Error status */ + #define CCM_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register. */ + +/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << CCM_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Min (0x0UL) /*!< Min enumerator value of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_Max (0x3UL) /*!< Max enumerator value of ERRORSTATUS field. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred */ + #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before CCM data structure was read. */ + #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before CCM data structure was + read.*/ + #define CCM_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption of the unencrypted CCM data structure did not + complete in time.*/ + + +/* CCM_ENABLE: Enable */ + #define CCM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable CCM */ + #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define CCM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define CCM_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */ + + +/* CCM_MODE: Operation mode */ + #define CCM_MODE_ResetValue (0x00000001UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. */ + #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define CCM_MODE_MODE_Msk (0x3UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define CCM_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define CCM_MODE_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define CCM_MODE_MODE_Encryption (0x0UL) /*!< AES CCM packet encryption mode */ + #define CCM_MODE_MODE_Decryption (0x1UL) /*!< AES CCM packet decryption mode */ + #define CCM_MODE_MODE_FastDecryption (0x2UL) /*!< AES fast decrypt mode. This mode will run CCM decryption as fast as + possible, i.e. not locked to a radio data rate. This can be used when + a packet has been completely received.*/ + +/* PROTOCOL @Bits 8..9 : Protocol and packet format selection */ + #define CCM_MODE_PROTOCOL_Pos (8UL) /*!< Position of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Msk (0x3UL << CCM_MODE_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Min (0x0UL) /*!< Min enumerator value of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Max (0x1UL) /*!< Max enumerator value of PROTOCOL field. */ + #define CCM_MODE_PROTOCOL_Ble (0x0UL) /*!< Bluetooth Low Energy packet format */ + #define CCM_MODE_PROTOCOL_Ieee802154 (0x1UL) /*!< 802.15.4 packet format */ + +/* DATARATE @Bits 16..18 : Radio data rate that the CCM shall run synchronous with */ + #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ + #define CCM_MODE_DATARATE_Msk (0x7UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ + #define CCM_MODE_DATARATE_Min (0x0UL) /*!< Min enumerator value of DATARATE field. */ + #define CCM_MODE_DATARATE_Max (0x5UL) /*!< Max enumerator value of DATARATE field. */ + #define CCM_MODE_DATARATE_125Kbit (0x0UL) /*!< 125 Kbps */ + #define CCM_MODE_DATARATE_250Kbit (0x1UL) /*!< 250 Kbps */ + #define CCM_MODE_DATARATE_500Kbit (0x2UL) /*!< 500 Kbps */ + #define CCM_MODE_DATARATE_1Mbit (0x3UL) /*!< 1 Mbps */ + #define CCM_MODE_DATARATE_2Mbit (0x4UL) /*!< 2 Mbps */ + #define CCM_MODE_DATARATE_4Mbit (0x5UL) /*!< 4 Mbps */ + +/* MACLEN @Bits 24..26 : CCM MAC length (bytes) */ + #define CCM_MODE_MACLEN_Pos (24UL) /*!< Position of MACLEN field. */ + #define CCM_MODE_MACLEN_Msk (0x7UL << CCM_MODE_MACLEN_Pos) /*!< Bit mask of MACLEN field. */ + #define CCM_MODE_MACLEN_Min (0x0UL) /*!< Min enumerator value of MACLEN field. */ + #define CCM_MODE_MACLEN_Max (0x7UL) /*!< Max enumerator value of MACLEN field. */ + #define CCM_MODE_MACLEN_M0 (0x0UL) /*!< M = 0 This is a special case for CCM* where encryption is required but + not authentication*/ + #define CCM_MODE_MACLEN_M4 (0x1UL) /*!< M = 4 */ + #define CCM_MODE_MACLEN_M6 (0x2UL) /*!< M = 6 */ + #define CCM_MODE_MACLEN_M8 (0x3UL) /*!< M = 8 */ + #define CCM_MODE_MACLEN_M10 (0x4UL) /*!< M = 10 */ + #define CCM_MODE_MACLEN_M12 (0x5UL) /*!< M = 12 */ + #define CCM_MODE_MACLEN_M14 (0x6UL) /*!< M = 14 */ + #define CCM_MODE_MACLEN_M16 (0x7UL) /*!< M = 16 */ + + +/* CCM_RATEOVERRIDE: Data rate override setting. */ + #define CCM_RATEOVERRIDE_ResetValue (0x00000002UL) /*!< Reset value of RATEOVERRIDE register. */ + +/* RATEOVERRIDE @Bits 0..2 : Data rate override setting. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x7UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Min (0x0UL) /*!< Min enumerator value of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_Max (0x2UL) /*!< Max enumerator value of RATEOVERRIDE field. */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbit (0x0UL) /*!< 125 Kbps */ + #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbit (0x2UL) /*!< 500 Kbps */ + + +/* CCM_ADATAMASK: CCM adata mask. */ + #define CCM_ADATAMASK_ResetValue (0x000000E3UL) /*!< Reset value of ADATAMASK register. */ + +/* ADATAMASK @Bits 0..7 : CCM adata mask. */ + #define CCM_ADATAMASK_ADATAMASK_Pos (0UL) /*!< Position of ADATAMASK field. */ + #define CCM_ADATAMASK_ADATAMASK_Msk (0xFFUL << CCM_ADATAMASK_ADATAMASK_Pos) /*!< Bit mask of ADATAMASK field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CLIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct CLIC_CLIC ===================================================== */ +/** + * @brief CLIC [CLIC_CLIC] (unspecified) + */ +typedef struct { + __IM uint32_t CLICCFG; /*!< (@ 0x00000000) CLIC configuration. */ + __IM uint32_t CLICINFO; /*!< (@ 0x00000004) CLIC information. */ + __IM uint32_t RESERVED[1022]; + __IOM uint32_t CLICINT[480]; /*!< (@ 0x00001000) Interrupt control register for IRQ number [n]. */ +} NRF_CLIC_CLIC_Type; /*!< Size = 6016 (0x1780) */ + +/* CLIC_CLIC_CLICCFG: CLIC configuration. */ + #define CLIC_CLIC_CLICCFG_ResetValue (0x00000011UL) /*!< Reset value of CLICCFG register. */ + +/* NVBITS @Bit 0 : Selective interrupt hardware vectoring. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Pos (0UL) /*!< Position of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Msk (0x1UL << CLIC_CLIC_CLICCFG_NVBITS_Pos) /*!< Bit mask of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Min (0x1UL) /*!< Min enumerator value of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Max (0x1UL) /*!< Max enumerator value of NVBITS field. */ + #define CLIC_CLIC_CLICCFG_NVBITS_Implemented (0x1UL) /*!< Selective interrupt hardware vectoring is implemented */ + +/* NLBITS @Bits 1..4 : Interrupt level encoding. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Pos (1UL) /*!< Position of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Msk (0xFUL << CLIC_CLIC_CLICCFG_NLBITS_Pos) /*!< Bit mask of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Min (0x8UL) /*!< Min enumerator value of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Max (0x8UL) /*!< Max enumerator value of NLBITS field. */ + #define CLIC_CLIC_CLICCFG_NLBITS_Eight (0x8UL) /*!< 8 bits = interrupt levels encoded in eight bits */ + +/* NMBITS @Bits 5..6 : Interrupt privilege mode. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Pos (5UL) /*!< Position of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Msk (0x3UL << CLIC_CLIC_CLICCFG_NMBITS_Pos) /*!< Bit mask of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Min (0x0UL) /*!< Min enumerator value of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_Max (0x0UL) /*!< Max enumerator value of NMBITS field. */ + #define CLIC_CLIC_CLICCFG_NMBITS_ModeM (0x0UL) /*!< All interrupts are M-mode only */ + + +/* CLIC_CLIC_CLICINFO: CLIC information. */ + #define CLIC_CLIC_CLICINFO_ResetValue (0x00401FFFUL) /*!< Reset value of CLICINFO register. */ + +/* NUMINTERRUPTS @Bits 0..12 : Maximum number of interrupts supported. */ + #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos (0UL) /*!< Position of NUMINTERRUPTS field. */ + #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Msk (0x1FFFUL << CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos) /*!< Bit mask of NUMINTERRUPTS + field.*/ + +/* VERSION @Bits 13..20 : Version */ + #define CLIC_CLIC_CLICINFO_VERSION_Pos (13UL) /*!< Position of VERSION field. */ + #define CLIC_CLIC_CLICINFO_VERSION_Msk (0xFFUL << CLIC_CLIC_CLICINFO_VERSION_Pos) /*!< Bit mask of VERSION field. */ + +/* NUMTRIGGER @Bits 25..30 : Number of maximum interrupt triggers supported */ + #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos (25UL) /*!< Position of NUMTRIGGER field. */ + #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Msk (0x3FUL << CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos) /*!< Bit mask of NUMTRIGGER field. */ + + +/* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */ + #define CLIC_CLIC_CLICINT_MaxCount (480UL) /*!< Max size of CLICINT[480] array. */ + #define CLIC_CLIC_CLICINT_MaxIndex (479UL) /*!< Max index of CLICINT[480] array. */ + #define CLIC_CLIC_CLICINT_MinIndex (0UL) /*!< Min index of CLICINT[480] array. */ + #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[480] register. */ + +/* IP @Bit 0 : Interrupt Pending bit. */ + #define CLIC_CLIC_CLICINT_IP_Pos (0UL) /*!< Position of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Msk (0x1UL << CLIC_CLIC_CLICINT_IP_Pos) /*!< Bit mask of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Min (0x0UL) /*!< Min enumerator value of IP field. */ + #define CLIC_CLIC_CLICINT_IP_Max (0x1UL) /*!< Max enumerator value of IP field. */ + #define CLIC_CLIC_CLICINT_IP_NotPending (0x0UL) /*!< Interrupt not pending */ + #define CLIC_CLIC_CLICINT_IP_Pending (0x1UL) /*!< Interrupt pending */ + +/* READ1 @Bits 1..7 : Read as 0, write ignored. */ + #define CLIC_CLIC_CLICINT_READ1_Pos (1UL) /*!< Position of READ1 field. */ + #define CLIC_CLIC_CLICINT_READ1_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ1_Pos) /*!< Bit mask of READ1 field. */ + +/* IE @Bit 8 : Interrupt enable bit. */ + #define CLIC_CLIC_CLICINT_IE_Pos (8UL) /*!< Position of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Msk (0x1UL << CLIC_CLIC_CLICINT_IE_Pos) /*!< Bit mask of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Min (0x0UL) /*!< Min enumerator value of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Max (0x1UL) /*!< Max enumerator value of IE field. */ + #define CLIC_CLIC_CLICINT_IE_Disabled (0x0UL) /*!< Interrupt disabled */ + #define CLIC_CLIC_CLICINT_IE_Enabled (0x1UL) /*!< Interrupt enabled */ + +/* READ2 @Bits 9..15 : Read as 0, write ignored. */ + #define CLIC_CLIC_CLICINT_READ2_Pos (9UL) /*!< Position of READ2 field. */ + #define CLIC_CLIC_CLICINT_READ2_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ2_Pos) /*!< Bit mask of READ2 field. */ + +/* SHV @Bit 16 : Selective Hardware Vectoring. */ + #define CLIC_CLIC_CLICINT_SHV_Pos (16UL) /*!< Position of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Msk (0x1UL << CLIC_CLIC_CLICINT_SHV_Pos) /*!< Bit mask of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Min (0x1UL) /*!< Min enumerator value of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Max (0x1UL) /*!< Max enumerator value of SHV field. */ + #define CLIC_CLIC_CLICINT_SHV_Vectored (0x1UL) /*!< Hardware vectored */ + +/* TRIG @Bits 17..18 : Trigger type and polarity for each interrupt input. */ + #define CLIC_CLIC_CLICINT_TRIG_Pos (17UL) /*!< Position of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Msk (0x3UL << CLIC_CLIC_CLICINT_TRIG_Pos) /*!< Bit mask of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Min (0x1UL) /*!< Min enumerator value of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_Max (0x1UL) /*!< Max enumerator value of TRIG field. */ + #define CLIC_CLIC_CLICINT_TRIG_EdgeTriggered (0x1UL) /*!< Interrupts are edge-triggered */ + +/* MODE @Bits 22..23 : Privilege mode. */ + #define CLIC_CLIC_CLICINT_MODE_Pos (22UL) /*!< Position of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Msk (0x3UL << CLIC_CLIC_CLICINT_MODE_Pos) /*!< Bit mask of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Min (0x3UL) /*!< Min enumerator value of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define CLIC_CLIC_CLICINT_MODE_MachineMode (0x3UL) /*!< Machine mode */ + +/* PRIORITY @Bits 24..31 : Interrupt priority level */ + #define CLIC_CLIC_CLICINT_PRIORITY_Pos (24UL) /*!< Position of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Msk (0xFFUL << CLIC_CLIC_CLICINT_PRIORITY_Pos) /*!< Bit mask of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Min (0x3FUL) /*!< Min enumerator value of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_Max (0xFFUL) /*!< Max enumerator value of PRIORITY field. */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL0 (0x3FUL) /*!< Priority level 0 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL1 (0x7FUL) /*!< Priority level 1 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL2 (0xBFUL) /*!< Priority level 2 */ + #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL3 (0xFFUL) /*!< Priority level 3 */ + + +/* ======================================================= Struct CLIC ======================================================= */ +/** + * @brief VPR CLIC registers + */ + typedef struct { /*!< CLIC Structure */ + __IOM NRF_CLIC_CLIC_Type CLIC; /*!< (@ 0x00000000) (unspecified) */ + } NRF_CLIC_Type; /*!< Size = 6016 (0x1780) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CM33SS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct CM33SS ====================================================== */ +/** + * @brief CM33 SubSystem + */ + typedef struct { /*!< CM33SS Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_FPUIOC; /*!< (@ 0x00000100) An invalid operation exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUDZC; /*!< (@ 0x00000104) A floating-point divide-by-zero exception has occurred + in the FPU.*/ + __IOM uint32_t EVENTS_FPUOFC; /*!< (@ 0x00000108) A floating-point overflow exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUUFC; /*!< (@ 0x0000010C) A floating-point underflow exception has occurred in + the FPU.*/ + __IOM uint32_t EVENTS_FPUIXC; /*!< (@ 0x00000110) A floating-point inexact exception has occurred in the + FPU.*/ + __IOM uint32_t EVENTS_FPUIDC; /*!< (@ 0x00000114) A floating-point input denormal exception has occurred + in the FPU.*/ + __IM uint32_t RESERVED1[250]; + __IOM uint32_t LOCK; /*!< (@ 0x00000500) Register to lock the certain parts of the CPU from + being modified.*/ + __IM uint32_t CPUID; /*!< (@ 0x00000504) The identifier for the CPU in this subsystem. */ + } NRF_CM33SS_Type; /*!< Size = 1288 (0x508) */ + +/* CM33SS_EVENTS_FPUIOC: An invalid operation exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIOC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIOC register. */ + +/* EVENTS_FPUIOC @Bit 0 : An invalid operation exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos (0UL) /*!< Position of EVENTS_FPUIOC field. */ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Msk (0x1UL << CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos) /*!< Bit mask of + EVENTS_FPUIOC field.*/ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIOC field. */ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIOC field. */ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_EVENTS_FPUDZC: A floating-point divide-by-zero exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUDZC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUDZC register. */ + +/* EVENTS_FPUDZC @Bit 0 : A floating-point divide-by-zero exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos (0UL) /*!< Position of EVENTS_FPUDZC field. */ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Msk (0x1UL << CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos) /*!< Bit mask of + EVENTS_FPUDZC field.*/ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUDZC field. */ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUDZC field. */ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_EVENTS_FPUOFC: A floating-point overflow exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUOFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUOFC register. */ + +/* EVENTS_FPUOFC @Bit 0 : A floating-point overflow exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos (0UL) /*!< Position of EVENTS_FPUOFC field. */ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Msk (0x1UL << CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos) /*!< Bit mask of + EVENTS_FPUOFC field.*/ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUOFC field. */ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUOFC field. */ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_EVENTS_FPUUFC: A floating-point underflow exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUUFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUUFC register. */ + +/* EVENTS_FPUUFC @Bit 0 : A floating-point underflow exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos (0UL) /*!< Position of EVENTS_FPUUFC field. */ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Msk (0x1UL << CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos) /*!< Bit mask of + EVENTS_FPUUFC field.*/ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUUFC field. */ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUUFC field. */ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_EVENTS_FPUIXC: A floating-point inexact exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIXC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIXC register. */ + +/* EVENTS_FPUIXC @Bit 0 : A floating-point inexact exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos (0UL) /*!< Position of EVENTS_FPUIXC field. */ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Msk (0x1UL << CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos) /*!< Bit mask of + EVENTS_FPUIXC field.*/ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIXC field. */ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIXC field. */ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_EVENTS_FPUIDC: A floating-point input denormal exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIDC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIDC register. */ + +/* EVENTS_FPUIDC @Bit 0 : A floating-point input denormal exception has occurred in the FPU. */ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos (0UL) /*!< Position of EVENTS_FPUIDC field. */ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Msk (0x1UL << CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos) /*!< Bit mask of + EVENTS_FPUIDC field.*/ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIDC field. */ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIDC field. */ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_NotGenerated (0x0UL) /*!< Event not generated */ + #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Generated (0x1UL) /*!< Event generated */ + + +/* CM33SS_LOCK: Register to lock the certain parts of the CPU from being modified. */ + #define CM33SS_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register. */ + +/* LOCKVTORAIRCRS @Bit 0 : Locks both the Vector table Offset Register (VTOR) and Application Interrupt and Reset Control + Register (AIRCR) for secure mode. */ + + #define CM33SS_LOCK_LOCKVTORAIRCRS_Pos (0UL) /*!< Position of LOCKVTORAIRCRS field. */ + #define CM33SS_LOCK_LOCKVTORAIRCRS_Msk (0x1UL << CM33SS_LOCK_LOCKVTORAIRCRS_Pos) /*!< Bit mask of LOCKVTORAIRCRS field. */ + #define CM33SS_LOCK_LOCKVTORAIRCRS_Min (0x0UL) /*!< Min enumerator value of LOCKVTORAIRCRS field. */ + #define CM33SS_LOCK_LOCKVTORAIRCRS_Max (0x1UL) /*!< Max enumerator value of LOCKVTORAIRCRS field. */ + #define CM33SS_LOCK_LOCKVTORAIRCRS_NotLocked (0x0UL) /*!< Both VTOR and AIRCR can be changed. */ + #define CM33SS_LOCK_LOCKVTORAIRCRS_Locked (0x1UL) /*!< Prevents changes to both VTOR and AIRCR. */ + +/* LOCKVTORNS @Bit 1 : Locks the Vector table Offset Register (VTOR) for non-secure mode. */ + #define CM33SS_LOCK_LOCKVTORNS_Pos (1UL) /*!< Position of LOCKVTORNS field. */ + #define CM33SS_LOCK_LOCKVTORNS_Msk (0x1UL << CM33SS_LOCK_LOCKVTORNS_Pos) /*!< Bit mask of LOCKVTORNS field. */ + #define CM33SS_LOCK_LOCKVTORNS_Min (0x0UL) /*!< Min enumerator value of LOCKVTORNS field. */ + #define CM33SS_LOCK_LOCKVTORNS_Max (0x1UL) /*!< Max enumerator value of LOCKVTORNS field. */ + #define CM33SS_LOCK_LOCKVTORNS_NotLocked (0x0UL) /*!< VTOR can be changed. */ + #define CM33SS_LOCK_LOCKVTORNS_Locked (0x1UL) /*!< Prevents changes to VTOR. */ + +/* LOCKMPUS @Bit 2 : Locks the Memory Protection Unit (MPU) for secure mode. */ + #define CM33SS_LOCK_LOCKMPUS_Pos (2UL) /*!< Position of LOCKMPUS field. */ + #define CM33SS_LOCK_LOCKMPUS_Msk (0x1UL << CM33SS_LOCK_LOCKMPUS_Pos) /*!< Bit mask of LOCKMPUS field. */ + #define CM33SS_LOCK_LOCKMPUS_Min (0x0UL) /*!< Min enumerator value of LOCKMPUS field. */ + #define CM33SS_LOCK_LOCKMPUS_Max (0x1UL) /*!< Max enumerator value of LOCKMPUS field. */ + #define CM33SS_LOCK_LOCKMPUS_NotLocked (0x0UL) /*!< MPU registers can be changed. */ + #define CM33SS_LOCK_LOCKMPUS_Locked (0x1UL) /*!< Prevents changes to MPU registers. */ + +/* LOCKMPUNS @Bit 3 : Locks the Memory Protection Unit (MPU) for non secure mode. */ + #define CM33SS_LOCK_LOCKMPUNS_Pos (3UL) /*!< Position of LOCKMPUNS field. */ + #define CM33SS_LOCK_LOCKMPUNS_Msk (0x1UL << CM33SS_LOCK_LOCKMPUNS_Pos) /*!< Bit mask of LOCKMPUNS field. */ + #define CM33SS_LOCK_LOCKMPUNS_Min (0x0UL) /*!< Min enumerator value of LOCKMPUNS field. */ + #define CM33SS_LOCK_LOCKMPUNS_Max (0x1UL) /*!< Max enumerator value of LOCKMPUNS field. */ + #define CM33SS_LOCK_LOCKMPUNS_NotLocked (0x0UL) /*!< MPU registers can be changed. */ + #define CM33SS_LOCK_LOCKMPUNS_Locked (0x1UL) /*!< Prevents changes to MPU registers. */ + +/* LOCKSAU @Bit 4 : Locks the Security Attribution Unit (SAU) */ + #define CM33SS_LOCK_LOCKSAU_Pos (4UL) /*!< Position of LOCKSAU field. */ + #define CM33SS_LOCK_LOCKSAU_Msk (0x1UL << CM33SS_LOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field. */ + #define CM33SS_LOCK_LOCKSAU_Min (0x0UL) /*!< Min enumerator value of LOCKSAU field. */ + #define CM33SS_LOCK_LOCKSAU_Max (0x1UL) /*!< Max enumerator value of LOCKSAU field. */ + #define CM33SS_LOCK_LOCKSAU_NotLocked (0x0UL) /*!< SAU registers can be changed. */ + #define CM33SS_LOCK_LOCKSAU_Locked (0x1UL) /*!< Prevents changes to SAU registers. */ + + +/* CM33SS_CPUID: The identifier for the CPU in this subsystem. */ + #define CM33SS_CPUID_ResetValue (0x00000000UL) /*!< Reset value of CPUID register. */ + +/* CPUID @Bits 0..31 : The CPU identifier. */ + #define CM33SS_CPUID_CPUID_Pos (0UL) /*!< Position of CPUID field. */ + #define CM33SS_CPUID_CPUID_Msk (0xFFFFFFFFUL << CM33SS_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct COMP ======================================================= */ +/** + * @brief Comparator + */ + typedef struct { /*!< COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ + __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ + __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ + __IM uint32_t RESERVED3[28]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED5[60]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ + } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ + +/* COMP_TASKS_START: Start comparator */ + #define COMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start comparator */ + #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_TASKS_STOP: Stop comparator */ + #define COMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop comparator */ + #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_TASKS_SAMPLE: Sample comparator value */ + #define COMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Sample comparator value */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field.*/ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* COMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define COMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define COMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define COMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* COMP_EVENTS_READY: COMP is ready and output is valid */ + #define COMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : COMP is ready and output is valid */ + #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/ + #define COMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_DOWN: Downward crossing */ + #define COMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register. */ + +/* EVENTS_DOWN @Bit 0 : Downward crossing */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field. */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_UP: Upward crossing */ + #define COMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register. */ + +/* EVENTS_UP @Bit 0 : Upward crossing */ + #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Min (0x0UL) /*!< Min enumerator value of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_Max (0x1UL) /*!< Max enumerator value of EVENTS_UP field. */ + #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_EVENTS_CROSS: Downward or upward crossing */ + #define COMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register. */ + +/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field.*/ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field. */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */ + #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */ + + +/* COMP_PUBLISH_READY: Publish configuration for event READY */ + #define COMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define COMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_DOWN: Publish configuration for event DOWN */ + #define COMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */ + #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_UP: Publish configuration for event UP */ + #define COMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */ + #define COMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_UP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_UP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_UP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_PUBLISH_CROSS: Publish configuration for event CROSS */ + #define COMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */ + #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define COMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define COMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define COMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define COMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* COMP_SHORTS: Shortcuts between local events and tasks */ + #define COMP_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */ + #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Min (0x0UL) /*!< Min enumerator value of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Max (0x1UL) /*!< Max enumerator value of READY_SAMPLE field. */ + #define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */ + #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Min (0x0UL) /*!< Min enumerator value of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Max (0x1UL) /*!< Max enumerator value of READY_STOP field. */ + #define COMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */ + #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Min (0x0UL) /*!< Min enumerator value of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Max (0x1UL) /*!< Max enumerator value of DOWN_STOP field. */ + #define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */ + #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Min (0x0UL) /*!< Min enumerator value of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Max (0x1UL) /*!< Max enumerator value of UP_STOP field. */ + #define COMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */ + #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Min (0x0UL) /*!< Min enumerator value of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Max (0x1UL) /*!< Max enumerator value of CROSS_STOP field. */ + #define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* COMP_INTEN: Enable or disable interrupt */ + #define COMP_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* READY @Bit 0 : Enable or disable interrupt for event READY */ + #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */ + #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTEN_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTEN_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */ + +/* UP @Bit 2 : Enable or disable interrupt for event UP */ + #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTEN_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTEN_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */ + +/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */ + #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTEN_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTEN_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */ + #define COMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */ + + +/* COMP_INTENSET: Enable interrupt */ + #define COMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */ + #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTENSET_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTENSET_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to enable interrupt for event UP */ + #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTENSET_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTENSET_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTENSET_UP_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */ + #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTENSET_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTENSET_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */ + #define COMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* COMP_INTENCLR: Disable interrupt */ + #define COMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */ + #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTENCLR_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTENCLR_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to disable interrupt for event UP */ + #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTENCLR_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTENCLR_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */ + #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTENCLR_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTENCLR_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */ + #define COMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define COMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* COMP_INTPEND: Pending interrupts */ + #define COMP_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* READY @Bit 0 : Read pending status of interrupt for event READY */ + #define COMP_INTPEND_READY_Pos (0UL) /*!< Position of READY field. */ + #define COMP_INTPEND_READY_Msk (0x1UL << COMP_INTPEND_READY_Pos) /*!< Bit mask of READY field. */ + #define COMP_INTPEND_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define COMP_INTPEND_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define COMP_INTPEND_READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */ + #define COMP_INTPEND_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define COMP_INTPEND_DOWN_Msk (0x1UL << COMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define COMP_INTPEND_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define COMP_INTPEND_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define COMP_INTPEND_DOWN_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_DOWN_Pending (0x1UL) /*!< Read: Pending */ + +/* UP @Bit 2 : Read pending status of interrupt for event UP */ + #define COMP_INTPEND_UP_Pos (2UL) /*!< Position of UP field. */ + #define COMP_INTPEND_UP_Msk (0x1UL << COMP_INTPEND_UP_Pos) /*!< Bit mask of UP field. */ + #define COMP_INTPEND_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define COMP_INTPEND_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define COMP_INTPEND_UP_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_UP_Pending (0x1UL) /*!< Read: Pending */ + +/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */ + #define COMP_INTPEND_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define COMP_INTPEND_CROSS_Msk (0x1UL << COMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define COMP_INTPEND_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define COMP_INTPEND_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define COMP_INTPEND_CROSS_NotPending (0x0UL) /*!< Read: Not pending */ + #define COMP_INTPEND_CROSS_Pending (0x1UL) /*!< Read: Pending */ + + +/* COMP_RESULT: Compare result */ + #define COMP_RESULT_ResetValue (0x00000000UL) /*!< Reset value of RESULT register. */ + +/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */ + #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ + #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + #define COMP_RESULT_RESULT_Min (0x0UL) /*!< Min enumerator value of RESULT field. */ + #define COMP_RESULT_RESULT_Max (0x1UL) /*!< Max enumerator value of RESULT field. */ + #define COMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ + #define COMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + + +/* COMP_ENABLE: COMP enable */ + #define COMP_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable COMP */ + #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define COMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define COMP_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable */ + + +/* COMP_PSEL: Pin select */ + #define COMP_PSEL_ResetValue (0x00000000UL) /*!< Reset value of PSEL register. */ + +/* PIN @Bits 0..4 : Analog pin select */ + #define COMP_PSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define COMP_PSEL_PIN_Msk (0x1FUL << COMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define COMP_PSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define COMP_PSEL_PORT_Msk (0xFUL << COMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* COMP_REFSEL: Reference source select for single-ended mode */ + #define COMP_REFSEL_ResetValue (0x00000004UL) /*!< Reset value of REFSEL register. */ + +/* REFSEL @Bits 0..2 : Reference select */ + #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Max (0x5UL) /*!< Max enumerator value of REFSEL field. */ + #define COMP_REFSEL_REFSEL_Int1V2 (0x0UL) /*!< VREF = internal 1.2 V reference (AVDD_AO_1V8 >= 1.7 V) */ + #define COMP_REFSEL_REFSEL_AVDDAO1V8 (0x4UL) /*!< VREF = AVDD_AO_1V8 */ + #define COMP_REFSEL_REFSEL_ARef (0x5UL) /*!< VREF = AREF */ + + +/* COMP_EXTREFSEL: External reference select */ + #define COMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register. */ + +/* PIN @Bits 0..4 : External analog reference pin select */ + #define COMP_EXTREFSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define COMP_EXTREFSEL_PIN_Msk (0x1FUL << COMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define COMP_EXTREFSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define COMP_EXTREFSEL_PORT_Msk (0xFUL << COMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* COMP_TH: Threshold configuration for hysteresis unit */ + #define COMP_TH_ResetValue (0x00002020UL) /*!< Reset value of TH register. */ + +/* THDOWN @Bits 0..5 : VDOWN = (THDOWN+1)/64*VREF */ + #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ + #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + #define COMP_TH_THDOWN_Min (0x00UL) /*!< Min value of THDOWN field. */ + #define COMP_TH_THDOWN_Max (0x3FUL) /*!< Max size of THDOWN field. */ + +/* THUP @Bits 8..13 : VUP = (THUP+1)/64*VREF */ + #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ + #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + #define COMP_TH_THUP_Min (0x00UL) /*!< Min value of THUP field. */ + #define COMP_TH_THUP_Max (0x3FUL) /*!< Max size of THUP field. */ + + +/* COMP_MODE: Mode configuration */ + #define COMP_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* SP @Bit 0 : Speed and power modes */ + #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ + #define COMP_MODE_SP_Msk (0x1UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ + #define COMP_MODE_SP_Min (0x0UL) /*!< Min enumerator value of SP field. */ + #define COMP_MODE_SP_Max (0x1UL) /*!< Max enumerator value of SP field. */ + #define COMP_MODE_SP_Low (0x0UL) /*!< Low-power mode */ + #define COMP_MODE_SP_High (0x1UL) /*!< High-speed mode */ + +/* MAIN @Bit 8 : Main operation modes */ + #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ + #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ + #define COMP_MODE_MAIN_Min (0x0UL) /*!< Min enumerator value of MAIN field. */ + #define COMP_MODE_MAIN_Max (0x1UL) /*!< Max enumerator value of MAIN field. */ + #define COMP_MODE_MAIN_SE (0x0UL) /*!< Single-ended mode */ + #define COMP_MODE_MAIN_Diff (0x1UL) /*!< Differential mode */ + + +/* COMP_HYST: Comparator hysteresis enable */ + #define COMP_HYST_ResetValue (0x00000000UL) /*!< Reset value of HYST register. */ + +/* HYST @Bit 0 : Comparator hysteresis */ + #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ + #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ + #define COMP_HYST_HYST_Min (0x0UL) /*!< Min enumerator value of HYST field. */ + #define COMP_HYST_HYST_Max (0x1UL) /*!< Max enumerator value of HYST field. */ + #define COMP_HYST_HYST_NoHyst (0x0UL) /*!< Comparator hysteresis disabled */ + #define COMP_HYST_HYST_Hyst40mV (0x1UL) /*!< Comparator hysteresis enabled */ + + +/* COMP_ISOURCE: Current source select on analog input */ + #define COMP_ISOURCE_ResetValue (0x00000000UL) /*!< Reset value of ISOURCE register. */ + +/* ISOURCE @Bits 0..1 : Current source select on analog input */ + #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Min (0x0UL) /*!< Min enumerator value of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Max (0x3UL) /*!< Max enumerator value of ISOURCE field. */ + #define COMP_ISOURCE_ISOURCE_Off (0x0UL) /*!< Current source disabled */ + #define COMP_ISOURCE_ISOURCE_Ien2uA5 (0x1UL) /*!< Current source enabled (+/- 2.5 uA) */ + #define COMP_ISOURCE_ISOURCE_Ien5uA (0x2UL) /*!< Current source enabled (+/- 5 uA) */ + #define COMP_ISOURCE_ISOURCE_Ien10uA (0x3UL) /*!< Current source enabled (+/- 10 uA) */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CTI ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct CTI ======================================================== */ +/** + * @brief Cross-Trigger Interface control + */ + typedef struct { /*!< CTI Structure */ + __IOM uint32_t CTICONTROL; /*!< (@ 0x00000000) CTI Control register */ + __IM uint32_t RESERVED[3]; + __OM uint32_t CTIINTACK; /*!< (@ 0x00000010) CTI Interrupt Acknowledge register */ + __IOM uint32_t CTIAPPSET; /*!< (@ 0x00000014) CTI Application Trigger Set register */ + __OM uint32_t CTIAPPCLEAR; /*!< (@ 0x00000018) CTI Application Trigger Clear register */ + __OM uint32_t CTIAPPPULSE; /*!< (@ 0x0000001C) CTI Application Pulse register */ + __IOM uint32_t CTIINEN[8]; /*!< (@ 0x00000020) CTI Trigger to Channel Enable register */ + __IM uint32_t RESERVED1[24]; + __IOM uint32_t CTIOUTEN[8]; /*!< (@ 0x000000A0) CTI Channel to Trigger Enable register */ + __IM uint32_t RESERVED2[28]; + __IM uint32_t CTITRIGINSTATUS; /*!< (@ 0x00000130) CTI Trigger In Status register */ + __IM uint32_t CTITRIGOUTSTATUS; /*!< (@ 0x00000134) CTI Trigger Out Status register */ + __IM uint32_t CTICHINSTATUS; /*!< (@ 0x00000138) CTI Channel In Status register */ + __IM uint32_t RESERVED3; + __IOM uint32_t CTIGATE; /*!< (@ 0x00000140) Enable CTI Channel Gate register */ + __IM uint32_t RESERVED4[926]; + __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture register */ + __IM uint32_t RESERVED5[2]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration register */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier register */ + __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ + __IM uint32_t PIDR5; /*!< (@ 0x00000FD4) Peripheral ID5 register */ + __IM uint32_t PIDR6; /*!< (@ 0x00000FD8) Peripheral ID6 register */ + __IM uint32_t PIDR7; /*!< (@ 0x00000FDC) Peripheral ID7 register */ + __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ + __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ + __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ + __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ + __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ + __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ + __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ + __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ + } NRF_CTI_Type; /*!< Size = 4096 (0x1000) */ + +/* CTI_CTICONTROL: CTI Control register */ + #define CTI_CTICONTROL_ResetValue (0x00000000UL) /*!< Reset value of CTICONTROL register. */ + +/* GLBEN @Bit 0 : Enables or disables the CTI. */ + #define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */ + #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */ + #define CTI_CTICONTROL_GLBEN_Min (0x0UL) /*!< Min enumerator value of GLBEN field. */ + #define CTI_CTICONTROL_GLBEN_Max (0x1UL) /*!< Max enumerator value of GLBEN field. */ + #define CTI_CTICONTROL_GLBEN_Disabled (0x0UL) /*!< All cross-triggering mapping logic functionality is disabled. */ + #define CTI_CTICONTROL_GLBEN_Enabled (0x1UL) /*!< Cross-triggering mapping logic functionality is enabled. */ + + +/* CTI_CTIINTACK: CTI Interrupt Acknowledge register */ + #define CTI_CTIINTACK_ResetValue (0x00000000UL) /*!< Reset value of CTIINTACK register. */ + +/* INTACK0 @Bit 0 : Acknowledges the ctitrigout 0 output. */ + #define CTI_CTIINTACK_INTACK0_Pos (0UL) /*!< Position of INTACK0 field. */ + #define CTI_CTIINTACK_INTACK0_Msk (0x1UL << CTI_CTIINTACK_INTACK0_Pos) /*!< Bit mask of INTACK0 field. */ + #define CTI_CTIINTACK_INTACK0_Min (0x1UL) /*!< Min enumerator value of INTACK0 field. */ + #define CTI_CTIINTACK_INTACK0_Max (0x1UL) /*!< Max enumerator value of INTACK0 field. */ + #define CTI_CTIINTACK_INTACK0_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK1 @Bit 1 : Acknowledges the ctitrigout 1 output. */ + #define CTI_CTIINTACK_INTACK1_Pos (1UL) /*!< Position of INTACK1 field. */ + #define CTI_CTIINTACK_INTACK1_Msk (0x1UL << CTI_CTIINTACK_INTACK1_Pos) /*!< Bit mask of INTACK1 field. */ + #define CTI_CTIINTACK_INTACK1_Min (0x1UL) /*!< Min enumerator value of INTACK1 field. */ + #define CTI_CTIINTACK_INTACK1_Max (0x1UL) /*!< Max enumerator value of INTACK1 field. */ + #define CTI_CTIINTACK_INTACK1_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK2 @Bit 2 : Acknowledges the ctitrigout 2 output. */ + #define CTI_CTIINTACK_INTACK2_Pos (2UL) /*!< Position of INTACK2 field. */ + #define CTI_CTIINTACK_INTACK2_Msk (0x1UL << CTI_CTIINTACK_INTACK2_Pos) /*!< Bit mask of INTACK2 field. */ + #define CTI_CTIINTACK_INTACK2_Min (0x1UL) /*!< Min enumerator value of INTACK2 field. */ + #define CTI_CTIINTACK_INTACK2_Max (0x1UL) /*!< Max enumerator value of INTACK2 field. */ + #define CTI_CTIINTACK_INTACK2_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK3 @Bit 3 : Acknowledges the ctitrigout 3 output. */ + #define CTI_CTIINTACK_INTACK3_Pos (3UL) /*!< Position of INTACK3 field. */ + #define CTI_CTIINTACK_INTACK3_Msk (0x1UL << CTI_CTIINTACK_INTACK3_Pos) /*!< Bit mask of INTACK3 field. */ + #define CTI_CTIINTACK_INTACK3_Min (0x1UL) /*!< Min enumerator value of INTACK3 field. */ + #define CTI_CTIINTACK_INTACK3_Max (0x1UL) /*!< Max enumerator value of INTACK3 field. */ + #define CTI_CTIINTACK_INTACK3_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK4 @Bit 4 : Acknowledges the ctitrigout 4 output. */ + #define CTI_CTIINTACK_INTACK4_Pos (4UL) /*!< Position of INTACK4 field. */ + #define CTI_CTIINTACK_INTACK4_Msk (0x1UL << CTI_CTIINTACK_INTACK4_Pos) /*!< Bit mask of INTACK4 field. */ + #define CTI_CTIINTACK_INTACK4_Min (0x1UL) /*!< Min enumerator value of INTACK4 field. */ + #define CTI_CTIINTACK_INTACK4_Max (0x1UL) /*!< Max enumerator value of INTACK4 field. */ + #define CTI_CTIINTACK_INTACK4_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK5 @Bit 5 : Acknowledges the ctitrigout 5 output. */ + #define CTI_CTIINTACK_INTACK5_Pos (5UL) /*!< Position of INTACK5 field. */ + #define CTI_CTIINTACK_INTACK5_Msk (0x1UL << CTI_CTIINTACK_INTACK5_Pos) /*!< Bit mask of INTACK5 field. */ + #define CTI_CTIINTACK_INTACK5_Min (0x1UL) /*!< Min enumerator value of INTACK5 field. */ + #define CTI_CTIINTACK_INTACK5_Max (0x1UL) /*!< Max enumerator value of INTACK5 field. */ + #define CTI_CTIINTACK_INTACK5_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK6 @Bit 6 : Acknowledges the ctitrigout 6 output. */ + #define CTI_CTIINTACK_INTACK6_Pos (6UL) /*!< Position of INTACK6 field. */ + #define CTI_CTIINTACK_INTACK6_Msk (0x1UL << CTI_CTIINTACK_INTACK6_Pos) /*!< Bit mask of INTACK6 field. */ + #define CTI_CTIINTACK_INTACK6_Min (0x1UL) /*!< Min enumerator value of INTACK6 field. */ + #define CTI_CTIINTACK_INTACK6_Max (0x1UL) /*!< Max enumerator value of INTACK6 field. */ + #define CTI_CTIINTACK_INTACK6_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + +/* INTACK7 @Bit 7 : Acknowledges the ctitrigout 7 output. */ + #define CTI_CTIINTACK_INTACK7_Pos (7UL) /*!< Position of INTACK7 field. */ + #define CTI_CTIINTACK_INTACK7_Msk (0x1UL << CTI_CTIINTACK_INTACK7_Pos) /*!< Bit mask of INTACK7 field. */ + #define CTI_CTIINTACK_INTACK7_Min (0x1UL) /*!< Min enumerator value of INTACK7 field. */ + #define CTI_CTIINTACK_INTACK7_Max (0x1UL) /*!< Max enumerator value of INTACK7 field. */ + #define CTI_CTIINTACK_INTACK7_Acknowledge (0x1UL) /*!< Clears the ctitrigout. */ + + +/* CTI_CTIAPPSET: CTI Application Trigger Set register */ + #define CTI_CTIAPPSET_ResetValue (0x00000000UL) /*!< Reset value of CTIAPPSET register. */ + +/* APPSET0 @Bit 0 : Application trigger event for channel 0. */ + #define CTI_CTIAPPSET_APPSET0_Pos (0UL) /*!< Position of APPSET0 field. */ + #define CTI_CTIAPPSET_APPSET0_Msk (0x1UL << CTI_CTIAPPSET_APPSET0_Pos) /*!< Bit mask of APPSET0 field. */ + #define CTI_CTIAPPSET_APPSET0_Min (0x0UL) /*!< Min enumerator value of APPSET0 field. */ + #define CTI_CTIAPPSET_APPSET0_Max (0x1UL) /*!< Max enumerator value of APPSET0 field. */ + #define CTI_CTIAPPSET_APPSET0_Inactive (0x0UL) /*!< Application trigger 0 is inactive. */ + #define CTI_CTIAPPSET_APPSET0_Active (0x1UL) /*!< Application trigger 0 is active. */ + #define CTI_CTIAPPSET_APPSET0_Activate (0x1UL) /*!< Generate channel event for channel 0. */ + +/* APPSET1 @Bit 1 : Application trigger event for channel 1. */ + #define CTI_CTIAPPSET_APPSET1_Pos (1UL) /*!< Position of APPSET1 field. */ + #define CTI_CTIAPPSET_APPSET1_Msk (0x1UL << CTI_CTIAPPSET_APPSET1_Pos) /*!< Bit mask of APPSET1 field. */ + #define CTI_CTIAPPSET_APPSET1_Min (0x0UL) /*!< Min enumerator value of APPSET1 field. */ + #define CTI_CTIAPPSET_APPSET1_Max (0x1UL) /*!< Max enumerator value of APPSET1 field. */ + #define CTI_CTIAPPSET_APPSET1_Inactive (0x0UL) /*!< Application trigger 1 is inactive. */ + #define CTI_CTIAPPSET_APPSET1_Active (0x1UL) /*!< Application trigger 1 is active. */ + #define CTI_CTIAPPSET_APPSET1_Activate (0x1UL) /*!< Generate channel event for channel 1. */ + +/* APPSET2 @Bit 2 : Application trigger event for channel 2. */ + #define CTI_CTIAPPSET_APPSET2_Pos (2UL) /*!< Position of APPSET2 field. */ + #define CTI_CTIAPPSET_APPSET2_Msk (0x1UL << CTI_CTIAPPSET_APPSET2_Pos) /*!< Bit mask of APPSET2 field. */ + #define CTI_CTIAPPSET_APPSET2_Min (0x0UL) /*!< Min enumerator value of APPSET2 field. */ + #define CTI_CTIAPPSET_APPSET2_Max (0x1UL) /*!< Max enumerator value of APPSET2 field. */ + #define CTI_CTIAPPSET_APPSET2_Inactive (0x0UL) /*!< Application trigger 2 is inactive. */ + #define CTI_CTIAPPSET_APPSET2_Active (0x1UL) /*!< Application trigger 2 is active. */ + #define CTI_CTIAPPSET_APPSET2_Activate (0x1UL) /*!< Generate channel event for channel 2. */ + +/* APPSET3 @Bit 3 : Application trigger event for channel 3. */ + #define CTI_CTIAPPSET_APPSET3_Pos (3UL) /*!< Position of APPSET3 field. */ + #define CTI_CTIAPPSET_APPSET3_Msk (0x1UL << CTI_CTIAPPSET_APPSET3_Pos) /*!< Bit mask of APPSET3 field. */ + #define CTI_CTIAPPSET_APPSET3_Min (0x0UL) /*!< Min enumerator value of APPSET3 field. */ + #define CTI_CTIAPPSET_APPSET3_Max (0x1UL) /*!< Max enumerator value of APPSET3 field. */ + #define CTI_CTIAPPSET_APPSET3_Inactive (0x0UL) /*!< Application trigger 3 is inactive. */ + #define CTI_CTIAPPSET_APPSET3_Active (0x1UL) /*!< Application trigger 3 is active. */ + #define CTI_CTIAPPSET_APPSET3_Activate (0x1UL) /*!< Generate channel event for channel 3. */ + + +/* CTI_CTIAPPCLEAR: CTI Application Trigger Clear register */ + #define CTI_CTIAPPCLEAR_ResetValue (0x00000000UL) /*!< Reset value of CTIAPPCLEAR register. */ + +/* APPCLEAR0 @Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ + #define CTI_CTIAPPCLEAR_APPCLEAR0_Pos (0UL) /*!< Position of APPCLEAR0 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR0_Pos) /*!< Bit mask of APPCLEAR0 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR0_Min (0x1UL) /*!< Min enumerator value of APPCLEAR0 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR0_Max (0x1UL) /*!< Max enumerator value of APPCLEAR0 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR0_Clear (0x1UL) /*!< Clears the event for channel 0. */ + +/* APPCLEAR1 @Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ + #define CTI_CTIAPPCLEAR_APPCLEAR1_Pos (1UL) /*!< Position of APPCLEAR1 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR1_Pos) /*!< Bit mask of APPCLEAR1 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR1_Min (0x1UL) /*!< Min enumerator value of APPCLEAR1 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR1_Max (0x1UL) /*!< Max enumerator value of APPCLEAR1 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR1_Clear (0x1UL) /*!< Clears the event for channel 1. */ + +/* APPCLEAR2 @Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ + #define CTI_CTIAPPCLEAR_APPCLEAR2_Pos (2UL) /*!< Position of APPCLEAR2 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR2_Pos) /*!< Bit mask of APPCLEAR2 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR2_Min (0x1UL) /*!< Min enumerator value of APPCLEAR2 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR2_Max (0x1UL) /*!< Max enumerator value of APPCLEAR2 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR2_Clear (0x1UL) /*!< Clears the event for channel 2. */ + +/* APPCLEAR3 @Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ + #define CTI_CTIAPPCLEAR_APPCLEAR3_Pos (3UL) /*!< Position of APPCLEAR3 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR3_Pos) /*!< Bit mask of APPCLEAR3 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR3_Min (0x1UL) /*!< Min enumerator value of APPCLEAR3 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR3_Max (0x1UL) /*!< Max enumerator value of APPCLEAR3 field. */ + #define CTI_CTIAPPCLEAR_APPCLEAR3_Clear (0x1UL) /*!< Clears the event for channel 3. */ + + +/* CTI_CTIAPPPULSE: CTI Application Pulse register */ + #define CTI_CTIAPPPULSE_ResetValue (0x00000000UL) /*!< Reset value of CTIAPPPULSE register. */ + +/* APPULSE0 @Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the + register for each channel. */ + + #define CTI_CTIAPPPULSE_APPULSE0_Pos (0UL) /*!< Position of APPULSE0 field. */ + #define CTI_CTIAPPPULSE_APPULSE0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE0_Pos) /*!< Bit mask of APPULSE0 field. */ + #define CTI_CTIAPPPULSE_APPULSE0_Min (0x1UL) /*!< Min enumerator value of APPULSE0 field. */ + #define CTI_CTIAPPPULSE_APPULSE0_Max (0x1UL) /*!< Max enumerator value of APPULSE0 field. */ + #define CTI_CTIAPPPULSE_APPULSE0_Generate (0x1UL) /*!< Generates an event pulse on channel 0. */ + +/* APPULSE1 @Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the + register for each channel. */ + + #define CTI_CTIAPPPULSE_APPULSE1_Pos (1UL) /*!< Position of APPULSE1 field. */ + #define CTI_CTIAPPPULSE_APPULSE1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE1_Pos) /*!< Bit mask of APPULSE1 field. */ + #define CTI_CTIAPPPULSE_APPULSE1_Min (0x1UL) /*!< Min enumerator value of APPULSE1 field. */ + #define CTI_CTIAPPPULSE_APPULSE1_Max (0x1UL) /*!< Max enumerator value of APPULSE1 field. */ + #define CTI_CTIAPPPULSE_APPULSE1_Generate (0x1UL) /*!< Generates an event pulse on channel 1. */ + +/* APPULSE2 @Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the + register for each channel. */ + + #define CTI_CTIAPPPULSE_APPULSE2_Pos (2UL) /*!< Position of APPULSE2 field. */ + #define CTI_CTIAPPPULSE_APPULSE2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE2_Pos) /*!< Bit mask of APPULSE2 field. */ + #define CTI_CTIAPPPULSE_APPULSE2_Min (0x1UL) /*!< Min enumerator value of APPULSE2 field. */ + #define CTI_CTIAPPPULSE_APPULSE2_Max (0x1UL) /*!< Max enumerator value of APPULSE2 field. */ + #define CTI_CTIAPPPULSE_APPULSE2_Generate (0x1UL) /*!< Generates an event pulse on channel 2. */ + +/* APPULSE3 @Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the + register for each channel. */ + + #define CTI_CTIAPPPULSE_APPULSE3_Pos (3UL) /*!< Position of APPULSE3 field. */ + #define CTI_CTIAPPPULSE_APPULSE3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE3_Pos) /*!< Bit mask of APPULSE3 field. */ + #define CTI_CTIAPPPULSE_APPULSE3_Min (0x1UL) /*!< Min enumerator value of APPULSE3 field. */ + #define CTI_CTIAPPPULSE_APPULSE3_Max (0x1UL) /*!< Max enumerator value of APPULSE3 field. */ + #define CTI_CTIAPPPULSE_APPULSE3_Generate (0x1UL) /*!< Generates an event pulse on channel 3. */ + + +/* CTI_CTIINEN: CTI Trigger to Channel Enable register */ + #define CTI_CTIINEN_MaxCount (8UL) /*!< Max size of CTIINEN[8] array. */ + #define CTI_CTIINEN_MaxIndex (7UL) /*!< Max index of CTIINEN[8] array. */ + #define CTI_CTIINEN_MinIndex (0UL) /*!< Min index of CTIINEN[8] array. */ + #define CTI_CTIINEN_ResetValue (0x00000000UL) /*!< Reset value of CTIINEN[8] register. */ + +/* TRIGINEN0 @Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */ + #define CTI_CTIINEN_TRIGINEN0_Pos (0UL) /*!< Position of TRIGINEN0 field. */ + #define CTI_CTIINEN_TRIGINEN0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN0_Pos) /*!< Bit mask of TRIGINEN0 field. */ + #define CTI_CTIINEN_TRIGINEN0_Min (0x0UL) /*!< Min enumerator value of TRIGINEN0 field. */ + #define CTI_CTIINEN_TRIGINEN0_Max (0x1UL) /*!< Max enumerator value of TRIGINEN0 field. */ + #define CTI_CTIINEN_TRIGINEN0_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 0. */ + #define CTI_CTIINEN_TRIGINEN0_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate + an event on channel 0.*/ + +/* TRIGINEN1 @Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */ + #define CTI_CTIINEN_TRIGINEN1_Pos (1UL) /*!< Position of TRIGINEN1 field. */ + #define CTI_CTIINEN_TRIGINEN1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN1_Pos) /*!< Bit mask of TRIGINEN1 field. */ + #define CTI_CTIINEN_TRIGINEN1_Min (0x0UL) /*!< Min enumerator value of TRIGINEN1 field. */ + #define CTI_CTIINEN_TRIGINEN1_Max (0x1UL) /*!< Max enumerator value of TRIGINEN1 field. */ + #define CTI_CTIINEN_TRIGINEN1_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 1. */ + #define CTI_CTIINEN_TRIGINEN1_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate + an event on channel 1.*/ + +/* TRIGINEN2 @Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */ + #define CTI_CTIINEN_TRIGINEN2_Pos (2UL) /*!< Position of TRIGINEN2 field. */ + #define CTI_CTIINEN_TRIGINEN2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN2_Pos) /*!< Bit mask of TRIGINEN2 field. */ + #define CTI_CTIINEN_TRIGINEN2_Min (0x0UL) /*!< Min enumerator value of TRIGINEN2 field. */ + #define CTI_CTIINEN_TRIGINEN2_Max (0x1UL) /*!< Max enumerator value of TRIGINEN2 field. */ + #define CTI_CTIINEN_TRIGINEN2_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 2. */ + #define CTI_CTIINEN_TRIGINEN2_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate + an event on channel 2.*/ + +/* TRIGINEN3 @Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */ + #define CTI_CTIINEN_TRIGINEN3_Pos (3UL) /*!< Position of TRIGINEN3 field. */ + #define CTI_CTIINEN_TRIGINEN3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN3_Pos) /*!< Bit mask of TRIGINEN3 field. */ + #define CTI_CTIINEN_TRIGINEN3_Min (0x0UL) /*!< Min enumerator value of TRIGINEN3 field. */ + #define CTI_CTIINEN_TRIGINEN3_Max (0x1UL) /*!< Max enumerator value of TRIGINEN3 field. */ + #define CTI_CTIINEN_TRIGINEN3_Disabled (0x0UL) /*!< Input trigger n events are ignored by channel 3. */ + #define CTI_CTIINEN_TRIGINEN3_Enabled (0x1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate + an event on channel 3.*/ + + +/* CTI_CTIOUTEN: CTI Channel to Trigger Enable register */ + #define CTI_CTIOUTEN_MaxCount (8UL) /*!< Max size of CTIOUTEN[8] array. */ + #define CTI_CTIOUTEN_MaxIndex (7UL) /*!< Max index of CTIOUTEN[8] array. */ + #define CTI_CTIOUTEN_MinIndex (0UL) /*!< Min index of CTIOUTEN[8] array. */ + #define CTI_CTIOUTEN_ResetValue (0x00000000UL) /*!< Reset value of CTIOUTEN[8] register. */ + +/* TRIGOUTEN0 @Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Pos (0UL) /*!< Position of TRIGOUTEN0 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN0_Pos) /*!< Bit mask of TRIGOUTEN0 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Min (0x0UL) /*!< Min enumerator value of TRIGOUTEN0 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Max (0x1UL) /*!< Max enumerator value of TRIGOUTEN0 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Disabled (0x0UL) /*!< Channel 0 is ignored by output trigger n. */ + #define CTI_CTIOUTEN_TRIGOUTEN0_Enabled (0x1UL) /*!< When an event occurs on channel 0, generate an event on output event n + (ctitrigout[n]).*/ + +/* TRIGOUTEN1 @Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Pos (1UL) /*!< Position of TRIGOUTEN1 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN1_Pos) /*!< Bit mask of TRIGOUTEN1 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Min (0x0UL) /*!< Min enumerator value of TRIGOUTEN1 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Max (0x1UL) /*!< Max enumerator value of TRIGOUTEN1 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Disabled (0x0UL) /*!< Channel 1 is ignored by output trigger n. */ + #define CTI_CTIOUTEN_TRIGOUTEN1_Enabled (0x1UL) /*!< When an event occurs on channel 1, generate an event on output event n + (ctitrigout[n]).*/ + +/* TRIGOUTEN2 @Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Pos (2UL) /*!< Position of TRIGOUTEN2 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN2_Pos) /*!< Bit mask of TRIGOUTEN2 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Min (0x0UL) /*!< Min enumerator value of TRIGOUTEN2 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Max (0x1UL) /*!< Max enumerator value of TRIGOUTEN2 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Disabled (0x0UL) /*!< Channel 2 is ignored by output trigger n. */ + #define CTI_CTIOUTEN_TRIGOUTEN2_Enabled (0x1UL) /*!< When an event occurs on channel 2, generate an event on output event n + (ctitrigout[n]).*/ + +/* TRIGOUTEN3 @Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Pos (3UL) /*!< Position of TRIGOUTEN3 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN3_Pos) /*!< Bit mask of TRIGOUTEN3 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Min (0x0UL) /*!< Min enumerator value of TRIGOUTEN3 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Max (0x1UL) /*!< Max enumerator value of TRIGOUTEN3 field. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Disabled (0x0UL) /*!< Channel 3 is ignored by output trigger n. */ + #define CTI_CTIOUTEN_TRIGOUTEN3_Enabled (0x1UL) /*!< When an event occurs on channel 3, generate an event on output event n + (ctitrigout[n]).*/ + + +/* CTI_CTITRIGINSTATUS: CTI Trigger In Status register */ + #define CTI_CTITRIGINSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTITRIGINSTATUS register. */ + +/* TRIGINSTATUS0 @Bit 0 : Shows the status of ctitrigin0 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Pos (0UL) /*!< Position of TRIGINSTATUS0 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Pos) /*!< Bit mask of TRIGINSTATUS0 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS0 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS0 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Active (0x1UL) /*!< Ctitrigin 0 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Inactive (0x0UL) /*!< Ctitrigin 0 is inactive. */ + +/* TRIGINSTATUS1 @Bit 1 : Shows the status of ctitrigin1 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Pos (1UL) /*!< Position of TRIGINSTATUS1 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Pos) /*!< Bit mask of TRIGINSTATUS1 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS1 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS1 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Active (0x1UL) /*!< Ctitrigin 1 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Inactive (0x0UL) /*!< Ctitrigin 1 is inactive. */ + +/* TRIGINSTATUS2 @Bit 2 : Shows the status of ctitrigin2 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Pos (2UL) /*!< Position of TRIGINSTATUS2 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Pos) /*!< Bit mask of TRIGINSTATUS2 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS2 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS2 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Active (0x1UL) /*!< Ctitrigin 2 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Inactive (0x0UL) /*!< Ctitrigin 2 is inactive. */ + +/* TRIGINSTATUS3 @Bit 3 : Shows the status of ctitrigin3 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Pos (3UL) /*!< Position of TRIGINSTATUS3 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Pos) /*!< Bit mask of TRIGINSTATUS3 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS3 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS3 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Active (0x1UL) /*!< Ctitrigin 3 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Inactive (0x0UL) /*!< Ctitrigin 3 is inactive. */ + +/* TRIGINSTATUS4 @Bit 4 : Shows the status of ctitrigin4 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Pos (4UL) /*!< Position of TRIGINSTATUS4 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Pos) /*!< Bit mask of TRIGINSTATUS4 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS4 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS4 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Active (0x1UL) /*!< Ctitrigin 4 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Inactive (0x0UL) /*!< Ctitrigin 4 is inactive. */ + +/* TRIGINSTATUS5 @Bit 5 : Shows the status of ctitrigin5 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Pos (5UL) /*!< Position of TRIGINSTATUS5 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Pos) /*!< Bit mask of TRIGINSTATUS5 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS5 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS5 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Active (0x1UL) /*!< Ctitrigin 5 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Inactive (0x0UL) /*!< Ctitrigin 5 is inactive. */ + +/* TRIGINSTATUS6 @Bit 6 : Shows the status of ctitrigin6 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Pos (6UL) /*!< Position of TRIGINSTATUS6 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Pos) /*!< Bit mask of TRIGINSTATUS6 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS6 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS6 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Active (0x1UL) /*!< Ctitrigin 6 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Inactive (0x0UL) /*!< Ctitrigin 6 is inactive. */ + +/* TRIGINSTATUS7 @Bit 7 : Shows the status of ctitrigin7 input. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Pos (7UL) /*!< Position of TRIGINSTATUS7 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Pos) /*!< Bit mask of TRIGINSTATUS7 + field.*/ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS7 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS7 field. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Active (0x1UL) /*!< Ctitrigin 7 is active. */ + #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Inactive (0x0UL) /*!< Ctitrigin 7 is inactive. */ + + +/* CTI_CTITRIGOUTSTATUS: CTI Trigger Out Status register */ + #define CTI_CTITRIGOUTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTITRIGOUTSTATUS register. */ + +/* TRIGOUTSTATUS0 @Bit 0 : Shows the status of ctitrigout0 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Pos (0UL) /*!< Position of TRIGOUTSTATUS0 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Pos) /*!< Bit mask of + TRIGOUTSTATUS0 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS0 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS0 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Active (0x1UL) /*!< Ctitrigout 0 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Inactive (0x0UL) /*!< Ctitrigout 0 is inactive. */ + +/* TRIGOUTSTATUS1 @Bit 1 : Shows the status of ctitrigout1 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Pos (1UL) /*!< Position of TRIGOUTSTATUS1 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Pos) /*!< Bit mask of + TRIGOUTSTATUS1 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS1 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS1 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Active (0x1UL) /*!< Ctitrigout 1 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Inactive (0x0UL) /*!< Ctitrigout 1 is inactive. */ + +/* TRIGOUTSTATUS2 @Bit 2 : Shows the status of ctitrigout2 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Pos (2UL) /*!< Position of TRIGOUTSTATUS2 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Pos) /*!< Bit mask of + TRIGOUTSTATUS2 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS2 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS2 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Active (0x1UL) /*!< Ctitrigout 2 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Inactive (0x0UL) /*!< Ctitrigout 2 is inactive. */ + +/* TRIGOUTSTATUS3 @Bit 3 : Shows the status of ctitrigout3 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Pos (3UL) /*!< Position of TRIGOUTSTATUS3 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Pos) /*!< Bit mask of + TRIGOUTSTATUS3 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS3 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS3 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Active (0x1UL) /*!< Ctitrigout 3 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Inactive (0x0UL) /*!< Ctitrigout 3 is inactive. */ + +/* TRIGOUTSTATUS4 @Bit 4 : Shows the status of ctitrigout4 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Pos (4UL) /*!< Position of TRIGOUTSTATUS4 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Pos) /*!< Bit mask of + TRIGOUTSTATUS4 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS4 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS4 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Active (0x1UL) /*!< Ctitrigout 4 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Inactive (0x0UL) /*!< Ctitrigout 4 is inactive. */ + +/* TRIGOUTSTATUS5 @Bit 5 : Shows the status of ctitrigout5 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Pos (5UL) /*!< Position of TRIGOUTSTATUS5 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Pos) /*!< Bit mask of + TRIGOUTSTATUS5 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS5 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS5 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Active (0x1UL) /*!< Ctitrigout 5 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Inactive (0x0UL) /*!< Ctitrigout 5 is inactive. */ + +/* TRIGOUTSTATUS6 @Bit 6 : Shows the status of ctitrigout6 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Pos (6UL) /*!< Position of TRIGOUTSTATUS6 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Pos) /*!< Bit mask of + TRIGOUTSTATUS6 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS6 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS6 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Active (0x1UL) /*!< Ctitrigout 6 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Inactive (0x0UL) /*!< Ctitrigout 6 is inactive. */ + +/* TRIGOUTSTATUS7 @Bit 7 : Shows the status of ctitrigout7 output. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Pos (7UL) /*!< Position of TRIGOUTSTATUS7 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Pos) /*!< Bit mask of + TRIGOUTSTATUS7 field.*/ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS7 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS7 field. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Active (0x1UL) /*!< Ctitrigout 7 is active. */ + #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Inactive (0x0UL) /*!< Ctitrigout 7 is inactive. */ + + +/* CTI_CTICHINSTATUS: CTI Channel In Status register */ + #define CTI_CTICHINSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTICHINSTATUS register. */ + +/* CTICHINSTATUS0 @Bit 0 : Shows the status of the ctitrigin 0 input. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Pos (0UL) /*!< Position of CTICHINSTATUS0 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS0_Pos) /*!< Bit mask of CTICHINSTATUS0 + field.*/ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS0 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS0 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Active (0x1UL) /*!< Ctichin 0 is active. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Inactive (0x0UL) /*!< Ctichin 0 is inactive. */ + +/* CTICHINSTATUS1 @Bit 1 : Shows the status of the ctitrigin 1 input. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Pos (1UL) /*!< Position of CTICHINSTATUS1 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS1_Pos) /*!< Bit mask of CTICHINSTATUS1 + field.*/ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS1 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS1 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Active (0x1UL) /*!< Ctichin 1 is active. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Inactive (0x0UL) /*!< Ctichin 1 is inactive. */ + +/* CTICHINSTATUS2 @Bit 2 : Shows the status of the ctitrigin 2 input. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Pos (2UL) /*!< Position of CTICHINSTATUS2 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS2_Pos) /*!< Bit mask of CTICHINSTATUS2 + field.*/ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS2 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS2 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Active (0x1UL) /*!< Ctichin 2 is active. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Inactive (0x0UL) /*!< Ctichin 2 is inactive. */ + +/* CTICHINSTATUS3 @Bit 3 : Shows the status of the ctitrigin 3 input. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Pos (3UL) /*!< Position of CTICHINSTATUS3 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS3_Pos) /*!< Bit mask of CTICHINSTATUS3 + field.*/ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS3 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS3 field. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Active (0x1UL) /*!< Ctichin 3 is active. */ + #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Inactive (0x0UL) /*!< Ctichin 3 is inactive. */ + + +/* CTI_CTIGATE: Enable CTI Channel Gate register */ + #define CTI_CTIGATE_ResetValue (0x0000000FUL) /*!< Reset value of CTIGATE register. */ + +/* CTIGATEEN0 @Bit 0 : Enable ctichout0. */ + #define CTI_CTIGATE_CTIGATEEN0_Pos (0UL) /*!< Position of CTIGATEEN0 field. */ + #define CTI_CTIGATE_CTIGATEEN0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN0_Pos) /*!< Bit mask of CTIGATEEN0 field. */ + #define CTI_CTIGATE_CTIGATEEN0_Min (0x0UL) /*!< Min enumerator value of CTIGATEEN0 field. */ + #define CTI_CTIGATE_CTIGATEEN0_Max (0x1UL) /*!< Max enumerator value of CTIGATEEN0 field. */ + #define CTI_CTIGATE_CTIGATEEN0_Enabled (0x1UL) /*!< Enable ctichout channel 0 propagation. */ + #define CTI_CTIGATE_CTIGATEEN0_Disabled (0x0UL) /*!< Disable ctichout channel 0 propagation. */ + +/* CTIGATEEN1 @Bit 1 : Enable ctichout1. */ + #define CTI_CTIGATE_CTIGATEEN1_Pos (1UL) /*!< Position of CTIGATEEN1 field. */ + #define CTI_CTIGATE_CTIGATEEN1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN1_Pos) /*!< Bit mask of CTIGATEEN1 field. */ + #define CTI_CTIGATE_CTIGATEEN1_Min (0x0UL) /*!< Min enumerator value of CTIGATEEN1 field. */ + #define CTI_CTIGATE_CTIGATEEN1_Max (0x1UL) /*!< Max enumerator value of CTIGATEEN1 field. */ + #define CTI_CTIGATE_CTIGATEEN1_Enabled (0x1UL) /*!< Enable ctichout channel 1 propagation. */ + #define CTI_CTIGATE_CTIGATEEN1_Disabled (0x0UL) /*!< Disable ctichout channel 1 propagation. */ + +/* CTIGATEEN2 @Bit 2 : Enable ctichout2. */ + #define CTI_CTIGATE_CTIGATEEN2_Pos (2UL) /*!< Position of CTIGATEEN2 field. */ + #define CTI_CTIGATE_CTIGATEEN2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN2_Pos) /*!< Bit mask of CTIGATEEN2 field. */ + #define CTI_CTIGATE_CTIGATEEN2_Min (0x0UL) /*!< Min enumerator value of CTIGATEEN2 field. */ + #define CTI_CTIGATE_CTIGATEEN2_Max (0x1UL) /*!< Max enumerator value of CTIGATEEN2 field. */ + #define CTI_CTIGATE_CTIGATEEN2_Enabled (0x1UL) /*!< Enable ctichout channel 2 propagation. */ + #define CTI_CTIGATE_CTIGATEEN2_Disabled (0x0UL) /*!< Disable ctichout channel 2 propagation. */ + +/* CTIGATEEN3 @Bit 3 : Enable ctichout3. */ + #define CTI_CTIGATE_CTIGATEEN3_Pos (3UL) /*!< Position of CTIGATEEN3 field. */ + #define CTI_CTIGATE_CTIGATEEN3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN3_Pos) /*!< Bit mask of CTIGATEEN3 field. */ + #define CTI_CTIGATE_CTIGATEEN3_Min (0x0UL) /*!< Min enumerator value of CTIGATEEN3 field. */ + #define CTI_CTIGATE_CTIGATEEN3_Max (0x1UL) /*!< Max enumerator value of CTIGATEEN3 field. */ + #define CTI_CTIGATE_CTIGATEEN3_Enabled (0x1UL) /*!< Enable ctichout channel 3 propagation. */ + #define CTI_CTIGATE_CTIGATEEN3_Disabled (0x0UL) /*!< Disable ctichout channel 3 propagation. */ + + +/* CTI_DEVARCH: Device Architecture register */ + #define CTI_DEVARCH_ResetValue (0x47701A14UL) /*!< Reset value of DEVARCH register. */ + +/* Architecture @Bit 0 : Contains the CTI device architecture. */ + #define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */ + #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */ + + +/* CTI_DEVID: Device Configuration register */ + #define CTI_DEVID_ResetValue (0x00040800UL) /*!< Reset value of DEVID register. */ + +/* EXTMUXNUM @Bits 0..4 : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using + asicctl. The default value of 0b00000 indicates that no multiplexing is present. */ + + #define CTI_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */ + #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */ + +/* NUMTRIG @Bits 8..15 : Number of ECT triggers available. */ + #define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */ + #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */ + +/* NUMCH @Bits 16..19 : Number of ECT channels available. */ + #define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */ + #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */ + + +/* CTI_DEVTYPE: Device Type Identifier register */ + #define CTI_DEVTYPE_ResetValue (0x00000014UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR @Bits 0..3 : Major classification of the type of the debug component as specified in the Arm Architecture Specification + for this debug and trace component. */ + + #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define CTI_DEVTYPE_MAJOR_Min (0x4UL) /*!< Min enumerator value of MAJOR field. */ + #define CTI_DEVTYPE_MAJOR_Max (0x4UL) /*!< Max enumerator value of MAJOR field. */ + #define CTI_DEVTYPE_MAJOR_Controller (0x4UL) /*!< Indicates that this component allows a debugger to control other + components in an Arm CoreSight SoC-400 system.*/ + +/* SUB @Bits 4..7 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification + within the major classification as specified in the MAJOR field. */ + + #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define CTI_DEVTYPE_SUB_Min (0x1UL) /*!< Min enumerator value of SUB field. */ + #define CTI_DEVTYPE_SUB_Max (0x1UL) /*!< Max enumerator value of SUB field. */ + #define CTI_DEVTYPE_SUB_Crosstrigger (0x1UL) /*!< Indicates that this component is a sub-triggering component. */ + + +/* CTI_PIDR4: Peripheral ID4 Register */ + #define CTI_PIDR4_ResetValue (0x00000004UL) /*!< Reset value of PIDR4 register. */ + +/* DES_2 @Bits 0..3 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ + #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ + #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ + #define CTI_PIDR4_DES_2_Min (0x4UL) /*!< Min enumerator value of DES_2 field. */ + #define CTI_PIDR4_DES_2_Max (0x4UL) /*!< Max enumerator value of DES_2 field. */ + #define CTI_PIDR4_DES_2_Code (0x4UL) /*!< JEDEC continuation code. */ + +/* SIZE @Bits 4..7 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */ + #define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ + #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* CTI_PIDR0: Peripheral ID0 Register */ + #define CTI_PIDR0_ResetValue (0x00000021UL) /*!< Reset value of PIDR0 register. */ + +/* PART_0 @Bits 0..7 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part + number. */ + + #define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ + #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ + #define CTI_PIDR0_PART_0_Min (0x21UL) /*!< Min enumerator value of PART_0 field. */ + #define CTI_PIDR0_PART_0_Max (0x21UL) /*!< Max enumerator value of PART_0 field. */ + #define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */ + + +/* CTI_PIDR1: Peripheral ID1 Register */ + #define CTI_PIDR1_ResetValue (0x000000BDUL) /*!< Reset value of PIDR1 register. */ + +/* PART_1 @Bits 0..3 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part + number. */ + + #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ + #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ + #define CTI_PIDR1_PART_1_Min (0xDUL) /*!< Min enumerator value of PART_1 field. */ + #define CTI_PIDR1_PART_1_Max (0xDUL) /*!< Max enumerator value of PART_1 field. */ + #define CTI_PIDR1_PART_1_PartnumberH (0xDUL) /*!< Indicates bits[11:8] of the part number of the component. */ + +/* DES_0 @Bits 4..7 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ + #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ + #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ + #define CTI_PIDR1_DES_0_Min (0xBUL) /*!< Min enumerator value of DES_0 field. */ + #define CTI_PIDR1_DES_0_Max (0xBUL) /*!< Max enumerator value of DES_0 field. */ + #define CTI_PIDR1_DES_0_Arm (0xBUL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */ + + +/* CTI_PIDR2: Peripheral ID2 Register */ + #define CTI_PIDR2_ResetValue (0x0000000BUL) /*!< Reset value of PIDR2 register. */ + +/* DES_1 @Bits 0..2 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ + #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ + #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ + #define CTI_PIDR2_DES_1_Min (0x3UL) /*!< Min enumerator value of DES_1 field. */ + #define CTI_PIDR2_DES_1_Max (0x3UL) /*!< Max enumerator value of DES_1 field. */ + #define CTI_PIDR2_DES_1_Arm (0x3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */ + +/* JEDEC @Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */ + #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ + #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ + +/* REVISION @Bits 4..7 : Peripheral revision */ + #define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ + #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ + #define CTI_PIDR2_REVISION_Min (0x0UL) /*!< Min enumerator value of REVISION field. */ + #define CTI_PIDR2_REVISION_Max (0x0UL) /*!< Max enumerator value of REVISION field. */ + #define CTI_PIDR2_REVISION_Rev0p0 (0x0UL) /*!< This device is at r0p0 */ + + +/* CTI_PIDR3: Peripheral ID3 Register */ + #define CTI_PIDR3_ResetValue (0x00000000UL) /*!< Reset value of PIDR3 register. */ + +/* CMOD @Bits 0..3 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most + cases, this field is 0b0000. Customers change this value when they make authorized modifications to this + component. */ + + #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ + #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ + #define CTI_PIDR3_CMOD_Min (0x0UL) /*!< Min enumerator value of CMOD field. */ + #define CTI_PIDR3_CMOD_Max (0x0UL) /*!< Max enumerator value of CMOD field. */ + #define CTI_PIDR3_CMOD_Unmodified (0x0UL) /*!< Indicates that the customer has not modified this component. */ + +/* REVAND @Bits 4..7 : Indicates minor errata fixes specific to the revision of the component being used, for example metal + fixes after implementation. In most cases, this field is 0b0000. Arm recommends that the component + designers ensure that a metal fix can change this field if required, for example, by driving it from + registers that reset to 0b0000. */ + + #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ + #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ + #define CTI_PIDR3_REVAND_Min (0x0UL) /*!< Min enumerator value of REVAND field. */ + #define CTI_PIDR3_REVAND_Max (0x0UL) /*!< Max enumerator value of REVAND field. */ + #define CTI_PIDR3_REVAND_NoErrata (0x0UL) /*!< Indicates that there are no errata fixes to this component. */ + + +/* CTI_CIDR0: Component ID0 Register */ + #define CTI_CIDR0_ResetValue (0x0000000DUL) /*!< Reset value of CIDR0 register. */ + +/* PRMBL_0 @Bits 0..7 : Preamble[0]. Contains bits[7:0] of the component identification code. */ + #define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ + #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ + #define CTI_CIDR0_PRMBL_0_Min (0xDUL) /*!< Min enumerator value of PRMBL_0 field. */ + #define CTI_CIDR0_PRMBL_0_Max (0xDUL) /*!< Max enumerator value of PRMBL_0 field. */ + #define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */ + + +/* CTI_CIDR1: Component ID1 Register */ + #define CTI_CIDR1_ResetValue (0x00000090UL) /*!< Reset value of CIDR1 register. */ + +/* PRMBL_1 @Bits 0..3 : Preamble[1]. Contains bits[11:8] of the component identification code. */ + #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ + #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ + #define CTI_CIDR1_PRMBL_1_Min (0x0UL) /*!< Min enumerator value of PRMBL_1 field. */ + #define CTI_CIDR1_PRMBL_1_Max (0x0UL) /*!< Max enumerator value of PRMBL_1 field. */ + #define CTI_CIDR1_PRMBL_1_Value (0x0UL) /*!< Bits[11:8] of the identification code. */ + +/* CLASS @Bits 4..7 : Class of the component, for example, whether the component is a ROM table or a generic CoreSight + component. Contains bits[15:12] of the component identification code */ + + #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ + #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ + #define CTI_CIDR1_CLASS_Min (0x9UL) /*!< Min enumerator value of CLASS field. */ + #define CTI_CIDR1_CLASS_Max (0x9UL) /*!< Max enumerator value of CLASS field. */ + #define CTI_CIDR1_CLASS_Coresight (0x9UL) /*!< Indicates that the component is a CoreSight component. */ + + +/* CTI_CIDR2: Component ID2 Register */ + #define CTI_CIDR2_ResetValue (0x00000005UL) /*!< Reset value of CIDR2 register. */ + +/* PRMBL_2 @Bits 0..7 : Preamble[2]. Contains bits[23:16] of the component identification code. */ + #define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ + #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ + #define CTI_CIDR2_PRMBL_2_Min (0x5UL) /*!< Min enumerator value of PRMBL_2 field. */ + #define CTI_CIDR2_PRMBL_2_Max (0x5UL) /*!< Max enumerator value of PRMBL_2 field. */ + #define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */ + + +/* CTI_CIDR3: Component ID3 Register */ + #define CTI_CIDR3_ResetValue (0x000000B1UL) /*!< Reset value of CIDR3 register. */ + +/* PRMBL_3 @Bits 0..7 : Preamble[3]. Contains bits[31:24] of the component identification code. */ + #define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ + #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ + #define CTI_CIDR3_PRMBL_3_Min (0xB1UL) /*!< Min enumerator value of PRMBL_3 field. */ + #define CTI_CIDR3_PRMBL_3_Max (0xB1UL) /*!< Max enumerator value of PRMBL_3 field. */ + #define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ CTRLAPPERI ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct CTRLAPPERI_MAILBOX ================================================ */ +/** + * @brief MAILBOX [CTRLAPPERI_MAILBOX] (unspecified) + */ +typedef struct { + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger to + the CPU has been read*/ + __IM uint32_t RESERVED[30]; + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU to the + debugger has been read*/ + __IM uint32_t BOOTMODE; /*!< (@ 0x00000088) Secure domain boot mode. */ +} NRF_CTRLAPPERI_MAILBOX_Type; /*!< Size = 140 (0x08C) */ + +/* CTRLAPPERI_MAILBOX_RXDATA: Data sent from the debugger to the CPU */ + #define CTRLAPPERI_MAILBOX_RXDATA_ResetValue (0x00000000UL) /*!< Reset value of RXDATA register. */ + +/* RXDATA @Bits 0..31 : Data received from debugger */ + #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ + #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA + field.*/ + + +/* CTRLAPPERI_MAILBOX_RXSTATUS: Status to indicate if data sent from the debugger to the CPU has been read */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RXSTATUS register. */ + +/* RXSTATUS @Bit 0 : Status of data in register RXDATA */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS + field.*/ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Min (0x0UL) /*!< Min enumerator value of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Max (0x1UL) /*!< Max enumerator value of RXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA */ + #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA */ + + +/* CTRLAPPERI_MAILBOX_TXDATA: Data sent from the CPU to the debugger */ + #define CTRLAPPERI_MAILBOX_TXDATA_ResetValue (0x00000000UL) /*!< Reset value of TXDATA register. */ + +/* TXDATA @Bits 0..31 : Data sent to debugger */ + #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ + #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA + field.*/ + + +/* CTRLAPPERI_MAILBOX_TXSTATUS: Status to indicate if data sent from the CPU to the debugger has been read */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TXSTATUS register. */ + +/* TXSTATUS @Bit 0 : Status of data in register TXDATA */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS + field.*/ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Min (0x0UL) /*!< Min enumerator value of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Max (0x1UL) /*!< Max enumerator value of TXSTATUS field. */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA */ + #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA */ + + +/* CTRLAPPERI_MAILBOX_BOOTMODE: Secure domain boot mode. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_ResetValue (0x00000000UL) /*!< Reset value of BOOTMODE register. */ + +/* MODE @Bit 0 : Mode */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Msk (0x1UL << CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Normal (0x0UL) /*!< Normal mode of operation */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_ROMOperation (0x1UL) /*!< ROM operation mode */ + +/* SAFEMODE @Bit 4 : Secure domain safe boot mode */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Pos (4UL) /*!< Position of SAFEMODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Msk (0x1UL << CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Pos) /*!< Bit mask of SAFEMODE + field.*/ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Min (0x0UL) /*!< Min enumerator value of SAFEMODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Max (0x1UL) /*!< Max enumerator value of SAFEMODE field. */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_Normal (0x0UL) /*!< Normal mode of operation */ + #define CTRLAPPERI_MAILBOX_BOOTMODE_SAFEMODE_SafeOperation (0x1UL) /*!< Safe operation mode */ + + + +/* ================================================= Struct CTRLAPPERI_INFO ================================================== */ +/** + * @brief INFO [CTRLAPPERI_INFO] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM uint32_t READY; /*!< (@ 0x00000008) Ready status. */ +} NRF_CTRLAPPERI_INFO_Type; /*!< Size = 12 (0x00C) */ + +/* CTRLAPPERI_INFO_READY: Ready status. */ + #define CTRLAPPERI_INFO_READY_ResetValue (0x00000001UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Ready status. */ + #define CTRLAPPERI_INFO_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define CTRLAPPERI_INFO_READY_READY_Msk (0x1UL << CTRLAPPERI_INFO_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define CTRLAPPERI_INFO_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define CTRLAPPERI_INFO_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define CTRLAPPERI_INFO_READY_READY_Ready (0x0UL) /*!< Ready */ + #define CTRLAPPERI_INFO_READY_READY_NotReady (0x1UL) /*!< Not ready */ + + +/* ==================================================== Struct CTRLAPPERI ==================================================== */ +/** + * @brief Control access port + */ + typedef struct { /*!< CTRLAPPERI Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000100) The RXSTATUS is changed to DataPending */ + __IOM uint32_t EVENTS_TXDONE; /*!< (@ 0x00000104) The TXSTATUS is changed to NoDataPending */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM NRF_CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED3[29]; + __IOM NRF_CTRLAPPERI_INFO_Type INFO; /*!< (@ 0x00000500) (unspecified) */ + __IOM uint32_t BOOTSTATUS; /*!< (@ 0x0000050C) Boot status */ + } NRF_CTRLAPPERI_Type; /*!< Size = 1296 (0x510) */ + +/* CTRLAPPERI_EVENTS_RXREADY: The RXSTATUS is changed to DataPending */ + #define CTRLAPPERI_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register. */ + +/* EVENTS_RXREADY @Bit 0 : The RXSTATUS is changed to DataPending */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of + EVENTS_RXREADY field.*/ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field. */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* CTRLAPPERI_EVENTS_TXDONE: The TXSTATUS is changed to NoDataPending */ + #define CTRLAPPERI_EVENTS_TXDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDONE register. */ + +/* EVENTS_TXDONE @Bit 0 : The TXSTATUS is changed to NoDataPending */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos (0UL) /*!< Position of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Msk (0x1UL << CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos) /*!< Bit mask of + EVENTS_TXDONE field.*/ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDONE field. */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Generated (0x1UL) /*!< Event generated */ + + +/* CTRLAPPERI_INTEN: Enable or disable interrupt */ + #define CTRLAPPERI_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* RXREADY @Bit 0 : Enable or disable interrupt for event RXREADY */ + #define CTRLAPPERI_INTEN_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Msk (0x1UL << CTRLAPPERI_INTEN_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTEN_RXREADY_Disabled (0x0UL) /*!< Disable */ + #define CTRLAPPERI_INTEN_RXREADY_Enabled (0x1UL) /*!< Enable */ + +/* TXDONE @Bit 1 : Enable or disable interrupt for event TXDONE */ + #define CTRLAPPERI_INTEN_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Msk (0x1UL << CTRLAPPERI_INTEN_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTEN_TXDONE_Disabled (0x0UL) /*!< Disable */ + #define CTRLAPPERI_INTEN_TXDONE_Enabled (0x1UL) /*!< Enable */ + + +/* CTRLAPPERI_INTENSET: Enable interrupt */ + #define CTRLAPPERI_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* RXREADY @Bit 0 : Write '1' to enable interrupt for event RXREADY */ + #define CTRLAPPERI_INTENSET_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENSET_RXREADY_Set (0x1UL) /*!< Enable */ + #define CTRLAPPERI_INTENSET_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENSET_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDONE @Bit 1 : Write '1' to enable interrupt for event TXDONE */ + #define CTRLAPPERI_INTENSET_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENSET_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENSET_TXDONE_Set (0x1UL) /*!< Enable */ + #define CTRLAPPERI_INTENSET_TXDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENSET_TXDONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CTRLAPPERI_INTENCLR: Disable interrupt */ + #define CTRLAPPERI_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* RXREADY @Bit 0 : Write '1' to disable interrupt for event RXREADY */ + #define CTRLAPPERI_INTENCLR_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTENCLR_RXREADY_Clear (0x1UL) /*!< Disable */ + #define CTRLAPPERI_INTENCLR_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENCLR_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDONE @Bit 1 : Write '1' to disable interrupt for event TXDONE */ + #define CTRLAPPERI_INTENCLR_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENCLR_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTENCLR_TXDONE_Clear (0x1UL) /*!< Disable */ + #define CTRLAPPERI_INTENCLR_TXDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define CTRLAPPERI_INTENCLR_TXDONE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* CTRLAPPERI_INTPEND: Pending interrupts */ + #define CTRLAPPERI_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* RXREADY @Bit 0 : Read pending status of interrupt for event RXREADY */ + #define CTRLAPPERI_INTPEND_RXREADY_Pos (0UL) /*!< Position of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Msk (0x1UL << CTRLAPPERI_INTPEND_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define CTRLAPPERI_INTPEND_RXREADY_NotPending (0x0UL) /*!< Read: Not pending */ + #define CTRLAPPERI_INTPEND_RXREADY_Pending (0x1UL) /*!< Read: Pending */ + +/* TXDONE @Bit 1 : Read pending status of interrupt for event TXDONE */ + #define CTRLAPPERI_INTPEND_TXDONE_Pos (1UL) /*!< Position of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Msk (0x1UL << CTRLAPPERI_INTPEND_TXDONE_Pos) /*!< Bit mask of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Min (0x0UL) /*!< Min enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_Max (0x1UL) /*!< Max enumerator value of TXDONE field. */ + #define CTRLAPPERI_INTPEND_TXDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define CTRLAPPERI_INTPEND_TXDONE_Pending (0x1UL) /*!< Read: Pending */ + + +/* CTRLAPPERI_BOOTSTATUS: Boot status */ + #define CTRLAPPERI_BOOTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of BOOTSTATUS register. */ + +/* VAL @Bits 0..31 : Value */ + #define CTRLAPPERI_BOOTSTATUS_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define CTRLAPPERI_BOOTSTATUS_VAL_Msk (0xFFFFFFFFUL << CTRLAPPERI_BOOTSTATUS_VAL_Pos) /*!< Bit mask of VAL field. */ + #define CTRLAPPERI_BOOTSTATUS_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define CTRLAPPERI_BOOTSTATUS_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ DCACHEDATA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================== Struct DCACHEDATA_SET_WAY_DU =============================================== */ +/** + * @brief DU [DCACHEDATA_SET_WAY_DU] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[1]; /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of + SET[n], WAY[o].*/ +} NRF_DCACHEDATA_SET_WAY_DU_Type; /*!< Size = 4 (0x004) */ + #define DCACHEDATA_SET_WAY_DU_MaxCount (8UL) /*!< Size of DU[8] array. */ + #define DCACHEDATA_SET_WAY_DU_MaxIndex (7UL) /*!< Max index of DU[8] array. */ + #define DCACHEDATA_SET_WAY_DU_MinIndex (0UL) /*!< Min index of DU[8] array. */ + +/* DCACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */ + #define DCACHEDATA_SET_WAY_DU_DATA_MaxCount (1UL) /*!< Max size of DATA[1] array. */ + #define DCACHEDATA_SET_WAY_DU_DATA_MaxIndex (0UL) /*!< Max index of DATA[1] array. */ + #define DCACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL) /*!< Min index of DATA[1] array. */ + #define DCACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[1] register. */ + +/* Data @Bits 0..31 : Data */ + #define DCACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL) /*!< Position of Data field. */ + #define DCACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << DCACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data + field.*/ + + + +/* ================================================ Struct DCACHEDATA_SET_WAY ================================================ */ +/** + * @brief WAY [DCACHEDATA_SET_WAY] (unspecified) + */ +typedef struct { + __IOM NRF_DCACHEDATA_SET_WAY_DU_Type DU[8]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_DCACHEDATA_SET_WAY_Type; /*!< Size = 32 (0x020) */ + #define DCACHEDATA_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define DCACHEDATA_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define DCACHEDATA_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + + +/* ================================================== Struct DCACHEDATA_SET ================================================== */ +/** + * @brief SET [DCACHEDATA_SET] (unspecified) + */ +typedef struct { + __IOM NRF_DCACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_DCACHEDATA_SET_Type; /*!< Size = 64 (0x040) */ + #define DCACHEDATA_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ + #define DCACHEDATA_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ + #define DCACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + +/* ==================================================== Struct DCACHEDATA ==================================================== */ +/** + * @brief CACHEDATA + */ + typedef struct { /*!< DCACHEDATA Structure */ + __IOM NRF_DCACHEDATA_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_DCACHEDATA_Type; /*!< Size = 16384 (0x4000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ DCACHEINFO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct DCACHEINFO_SET_WAY ================================================ */ +/** + * @brief WAY [DCACHEINFO_SET_WAY] (unspecified) + */ +typedef struct { + __IOM uint32_t INFO; /*!< (@ 0x00000000) Cache information for SET[n], WAY[o]. */ + __IOM uint32_t INFOEXT; /*!< (@ 0x00000004) Extended cache information for SET[n], WAY[o]. */ +} NRF_DCACHEINFO_SET_WAY_Type; /*!< Size = 8 (0x008) */ + #define DCACHEINFO_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define DCACHEINFO_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define DCACHEINFO_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + +/* DCACHEINFO_SET_WAY_INFO: Cache information for SET[n], WAY[o]. */ + #define DCACHEINFO_SET_WAY_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* TAG @Bits 0..19 : Cache tag. */ + #define DCACHEINFO_SET_WAY_INFO_TAG_Pos (0UL) /*!< Position of TAG field. */ + #define DCACHEINFO_SET_WAY_INFO_TAG_Msk (0xFFFFFUL << DCACHEINFO_SET_WAY_INFO_TAG_Pos) /*!< Bit mask of TAG field. */ + +/* DUV0 @Bit 24 : Data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Pos (24UL) /*!< Position of DUV0 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_DUV0_Pos) /*!< Bit mask of DUV0 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Min (0x0UL) /*!< Min enumerator value of DUV0 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Max (0x1UL) /*!< Max enumerator value of DUV0 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFO_DUV0_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV1 @Bit 25 : Data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Pos (25UL) /*!< Position of DUV1 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_DUV1_Pos) /*!< Bit mask of DUV1 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Min (0x0UL) /*!< Min enumerator value of DUV1 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Max (0x1UL) /*!< Max enumerator value of DUV1 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFO_DUV1_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV2 @Bit 26 : Data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Pos (26UL) /*!< Position of DUV2 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_DUV2_Pos) /*!< Bit mask of DUV2 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Min (0x0UL) /*!< Min enumerator value of DUV2 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Max (0x1UL) /*!< Max enumerator value of DUV2 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFO_DUV2_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV3 @Bit 27 : Data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Pos (27UL) /*!< Position of DUV3 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_DUV3_Pos) /*!< Bit mask of DUV3 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Min (0x0UL) /*!< Min enumerator value of DUV3 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Max (0x1UL) /*!< Max enumerator value of DUV3 field. */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFO_DUV3_Valid (0x1UL) /*!< Valid data unit */ + +/* D0 @Bit 28 : Dirty status of combined data unit 0 and 1. */ + #define DCACHEINFO_SET_WAY_INFO_D0_Pos (28UL) /*!< Position of D0 field. */ + #define DCACHEINFO_SET_WAY_INFO_D0_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_D0_Pos) /*!< Bit mask of D0 field. */ + #define DCACHEINFO_SET_WAY_INFO_D0_Min (0x0UL) /*!< Min enumerator value of D0 field. */ + #define DCACHEINFO_SET_WAY_INFO_D0_Max (0x1UL) /*!< Max enumerator value of D0 field. */ + #define DCACHEINFO_SET_WAY_INFO_D0_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFO_D0_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D1 @Bit 29 : Dirty status of combined data unit 2 and 3. */ + #define DCACHEINFO_SET_WAY_INFO_D1_Pos (29UL) /*!< Position of D1 field. */ + #define DCACHEINFO_SET_WAY_INFO_D1_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_D1_Pos) /*!< Bit mask of D1 field. */ + #define DCACHEINFO_SET_WAY_INFO_D1_Min (0x0UL) /*!< Min enumerator value of D1 field. */ + #define DCACHEINFO_SET_WAY_INFO_D1_Max (0x1UL) /*!< Max enumerator value of D1 field. */ + #define DCACHEINFO_SET_WAY_INFO_D1_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFO_D1_Dirty (0x1UL) /*!< Dirty data unit */ + +/* V @Bit 30 : Line valid bit. */ + #define DCACHEINFO_SET_WAY_INFO_V_Pos (30UL) /*!< Position of V field. */ + #define DCACHEINFO_SET_WAY_INFO_V_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_V_Pos) /*!< Bit mask of V field. */ + #define DCACHEINFO_SET_WAY_INFO_V_Min (0x0UL) /*!< Min enumerator value of V field. */ + #define DCACHEINFO_SET_WAY_INFO_V_Max (0x1UL) /*!< Max enumerator value of V field. */ + #define DCACHEINFO_SET_WAY_INFO_V_Invalid (0x0UL) /*!< Invalid cache line */ + #define DCACHEINFO_SET_WAY_INFO_V_Valid (0x1UL) /*!< Valid cache line */ + +/* MRU @Bit 31 : Most recently used way. */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Pos (31UL) /*!< Position of MRU field. */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Msk (0x1UL << DCACHEINFO_SET_WAY_INFO_MRU_Pos) /*!< Bit mask of MRU field. */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Min (0x0UL) /*!< Min enumerator value of MRU field. */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Max (0x1UL) /*!< Max enumerator value of MRU field. */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Way0 (0x0UL) /*!< Way0 was most recently used */ + #define DCACHEINFO_SET_WAY_INFO_MRU_Way1 (0x1UL) /*!< Way1 was most recently used */ + + +/* DCACHEINFO_SET_WAY_INFOEXT: Extended cache information for SET[n], WAY[o]. */ + #define DCACHEINFO_SET_WAY_INFOEXT_ResetValue (0x00000000UL) /*!< Reset value of INFOEXT register. */ + +/* D0 @Bit 16 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Pos (16UL) /*!< Position of D0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D0_Pos) /*!< Bit mask of D0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Min (0x0UL) /*!< Min enumerator value of D0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Max (0x1UL) /*!< Max enumerator value of D0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D0_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D1 @Bit 17 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Pos (17UL) /*!< Position of D1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D1_Pos) /*!< Bit mask of D1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Min (0x0UL) /*!< Min enumerator value of D1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Max (0x1UL) /*!< Max enumerator value of D1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D1_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D2 @Bit 18 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Pos (18UL) /*!< Position of D2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D2_Pos) /*!< Bit mask of D2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Min (0x0UL) /*!< Min enumerator value of D2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Max (0x1UL) /*!< Max enumerator value of D2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D2_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D3 @Bit 19 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Pos (19UL) /*!< Position of D3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D3_Pos) /*!< Bit mask of D3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Min (0x0UL) /*!< Min enumerator value of D3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Max (0x1UL) /*!< Max enumerator value of D3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D3_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D4 @Bit 20 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Pos (20UL) /*!< Position of D4 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D4_Pos) /*!< Bit mask of D4 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Min (0x0UL) /*!< Min enumerator value of D4 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Max (0x1UL) /*!< Max enumerator value of D4 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D4_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D5 @Bit 21 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Pos (21UL) /*!< Position of D5 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D5_Pos) /*!< Bit mask of D5 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Min (0x0UL) /*!< Min enumerator value of D5 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Max (0x1UL) /*!< Max enumerator value of D5 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D5_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D6 @Bit 22 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Pos (22UL) /*!< Position of D6 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D6_Pos) /*!< Bit mask of D6 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Min (0x0UL) /*!< Min enumerator value of D6 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Max (0x1UL) /*!< Max enumerator value of D6 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D6_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D7 @Bit 23 : Dirty status. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Pos (23UL) /*!< Position of D7 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_D7_Pos) /*!< Bit mask of D7 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Min (0x0UL) /*!< Min enumerator value of D7 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Max (0x1UL) /*!< Max enumerator value of D7 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Clean (0x0UL) /*!< Clean data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_D7_Dirty (0x1UL) /*!< Dirty data unit */ + +/* DUVEXT0 @Bit 24 : Extended data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Pos (24UL) /*!< Position of DUVEXT0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Pos) /*!< Bit mask of DUVEXT0 + field.*/ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Min (0x0UL) /*!< Min enumerator value of DUVEXT0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Max (0x1UL) /*!< Max enumerator value of DUVEXT0 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT0_Valid (0x1UL) /*!< Valid data unit */ + +/* DUVEXT1 @Bit 25 : Extended data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Pos (25UL) /*!< Position of DUVEXT1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Pos) /*!< Bit mask of DUVEXT1 + field.*/ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Min (0x0UL) /*!< Min enumerator value of DUVEXT1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Max (0x1UL) /*!< Max enumerator value of DUVEXT1 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT1_Valid (0x1UL) /*!< Valid data unit */ + +/* DUVEXT2 @Bit 26 : Extended data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Pos (26UL) /*!< Position of DUVEXT2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Pos) /*!< Bit mask of DUVEXT2 + field.*/ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Min (0x0UL) /*!< Min enumerator value of DUVEXT2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Max (0x1UL) /*!< Max enumerator value of DUVEXT2 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT2_Valid (0x1UL) /*!< Valid data unit */ + +/* DUVEXT3 @Bit 27 : Extended data unit valid info. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Pos (27UL) /*!< Position of DUVEXT3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Msk (0x1UL << DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Pos) /*!< Bit mask of DUVEXT3 + field.*/ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Min (0x0UL) /*!< Min enumerator value of DUVEXT3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Max (0x1UL) /*!< Max enumerator value of DUVEXT3 field. */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Invalid (0x0UL) /*!< Invalid data unit */ + #define DCACHEINFO_SET_WAY_INFOEXT_DUVEXT3_Valid (0x1UL) /*!< Valid data unit */ + + + +/* ================================================== Struct DCACHEINFO_SET ================================================== */ +/** + * @brief SET [DCACHEINFO_SET] (unspecified) + */ +typedef struct { + __IOM NRF_DCACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_DCACHEINFO_SET_Type; /*!< Size = 16 (0x010) */ + #define DCACHEINFO_SET_MaxCount (256UL) /*!< Size of SET[256] array. */ + #define DCACHEINFO_SET_MaxIndex (255UL) /*!< Max index of SET[256] array. */ + #define DCACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[256] array. */ + +/* ==================================================== Struct DCACHEINFO ==================================================== */ +/** + * @brief CACHEINFO + */ + typedef struct { /*!< DCACHEINFO Structure */ + __IOM NRF_DCACHEINFO_SET_Type SET[256]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_DCACHEINFO_Type; /*!< Size = 4096 (0x1000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ DMU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct DMU ======================================================== */ +/** + * @brief DMU + */ + typedef struct { /*!< DMU Structure */ + __IM uint32_t RESERVED[240]; + __IM uint32_t DMUCR; /*!< (@ 0x000003C0) DMU Core Release */ + __IOM uint32_t DMUI; /*!< (@ 0x000003C4) DMU Internals */ + __IOM uint32_t DMUQC; /*!< (@ 0x000003C8) DMU Queueing Counter */ + __IOM uint32_t DMUIR; /*!< (@ 0x000003CC) DMU Interrupt Register */ + __IOM uint32_t DMUIE; /*!< (@ 0x000003D0) DMU Interrupt Enable */ + __IOM uint32_t DMUC; /*!< (@ 0x000003D4) DMU Configuration */ + } NRF_DMU_Type; /*!< Size = 984 (0x3D8) */ + +/* DMU_DMUCR: DMU Core Release */ + #define DMU_DMUCR_ResetValue (0x00000000UL) /*!< Reset value of DMUCR register. */ + +/* REL @Bit 1 : Core Release */ + #define DMU_DMUCR_REL_Pos (1UL) /*!< Position of REL field. */ + #define DMU_DMUCR_REL_Msk (0x1UL << DMU_DMUCR_REL_Pos) /*!< Bit mask of REL field. */ + +/* STEP @Bit 2 : Step of Core Release */ + #define DMU_DMUCR_STEP_Pos (2UL) /*!< Position of STEP field. */ + #define DMU_DMUCR_STEP_Msk (0x1UL << DMU_DMUCR_STEP_Pos) /*!< Bit mask of STEP field. */ + +/* SUBSTEP @Bit 3 : Sub-step of Core Release */ + #define DMU_DMUCR_SUBSTEP_Pos (3UL) /*!< Position of SUBSTEP field. */ + #define DMU_DMUCR_SUBSTEP_Msk (0x1UL << DMU_DMUCR_SUBSTEP_Pos) /*!< Bit mask of SUBSTEP field. */ + +/* YEAR @Bit 4 : Time Stamp Year */ + #define DMU_DMUCR_YEAR_Pos (4UL) /*!< Position of YEAR field. */ + #define DMU_DMUCR_YEAR_Msk (0x1UL << DMU_DMUCR_YEAR_Pos) /*!< Bit mask of YEAR field. */ + +/* MON @Bit 6 : Time Stamp Month */ + #define DMU_DMUCR_MON_Pos (6UL) /*!< Position of MON field. */ + #define DMU_DMUCR_MON_Msk (0x1UL << DMU_DMUCR_MON_Pos) /*!< Bit mask of MON field. */ + +/* DAY @Bit 8 : Time Stamp Day */ + #define DMU_DMUCR_DAY_Pos (8UL) /*!< Position of DAY field. */ + #define DMU_DMUCR_DAY_Msk (0x1UL << DMU_DMUCR_DAY_Pos) /*!< Bit mask of DAY field. */ + + +/* DMU_DMUI: DMU Internals */ + #define DMU_DMUI_ResetValue (0x00070000UL) /*!< Reset value of DMUI register. */ + +/* TXR @Bit 0 : TX Service Request line of DMU */ + #define DMU_DMUI_TXR_Pos (0UL) /*!< Position of TXR field. */ + #define DMU_DMUI_TXR_Msk (0x1UL << DMU_DMUI_TXR_Pos) /*!< Bit mask of TXR field. */ + #define DMU_DMUI_TXR_Min (0x0UL) /*!< Min enumerator value of TXR field. */ + #define DMU_DMUI_TXR_Max (0x1UL) /*!< Max enumerator value of TXR field. */ + #define DMU_DMUI_TXR_NotRequested (0x0UL) /*!< No TX DMA service requested */ + #define DMU_DMUI_TXR_Requested (0x1UL) /*!< TX DMA Service requested */ + +/* RX0R @Bit 1 : RX0 Service Request line of DMU */ + #define DMU_DMUI_RX0R_Pos (1UL) /*!< Position of RX0R field. */ + #define DMU_DMUI_RX0R_Msk (0x1UL << DMU_DMUI_RX0R_Pos) /*!< Bit mask of RX0R field. */ + #define DMU_DMUI_RX0R_Min (0x0UL) /*!< Min enumerator value of RX0R field. */ + #define DMU_DMUI_RX0R_Max (0x1UL) /*!< Max enumerator value of RX0R field. */ + #define DMU_DMUI_RX0R_NotRequested (0x0UL) /*!< No RX0 DMA service requested */ + #define DMU_DMUI_RX0R_Requested (0x1UL) /*!< RX0 DMA Service requested */ + +/* RX1R @Bit 2 : RX1 Service Request line of DMU */ + #define DMU_DMUI_RX1R_Pos (2UL) /*!< Position of RX1R field. */ + #define DMU_DMUI_RX1R_Msk (0x1UL << DMU_DMUI_RX1R_Pos) /*!< Bit mask of RX1R field. */ + #define DMU_DMUI_RX1R_Min (0x0UL) /*!< Min enumerator value of RX1R field. */ + #define DMU_DMUI_RX1R_Max (0x1UL) /*!< Max enumerator value of RX1R field. */ + #define DMU_DMUI_RX1R_NotRequested (0x0UL) /*!< No RX1 DMA service requested */ + #define DMU_DMUI_RX1R_Requested (0x1UL) /*!< RX1 DMA Service requested */ + +/* TXER @Bit 3 : TX Event Service Request line of DMU */ + #define DMU_DMUI_TXER_Pos (3UL) /*!< Position of TXER field. */ + #define DMU_DMUI_TXER_Msk (0x1UL << DMU_DMUI_TXER_Pos) /*!< Bit mask of TXER field. */ + #define DMU_DMUI_TXER_Min (0x0UL) /*!< Min enumerator value of TXER field. */ + #define DMU_DMUI_TXER_Max (0x1UL) /*!< Max enumerator value of TXER field. */ + #define DMU_DMUI_TXER_NotRequested (0x0UL) /*!< No TX Event DMA service requested */ + #define DMU_DMUI_TXER_Requested (0x1UL) /*!< TX Event DMA Service requested */ + +/* TFQPIP @Bits 8..12 : TX FIFO/Queue Put Index Previous */ + #define DMU_DMUI_TFQPIP_Pos (8UL) /*!< Position of TFQPIP field. */ + #define DMU_DMUI_TFQPIP_Msk (0x1FUL << DMU_DMUI_TFQPIP_Pos) /*!< Bit mask of TFQPIP field. */ + +/* ENA @Bit 15 : DMU is enabled */ + #define DMU_DMUI_ENA_Pos (15UL) /*!< Position of ENA field. */ + #define DMU_DMUI_ENA_Msk (0x1UL << DMU_DMUI_ENA_Pos) /*!< Bit mask of ENA field. */ + #define DMU_DMUI_ENA_Min (0x0UL) /*!< Min enumerator value of ENA field. */ + #define DMU_DMUI_ENA_Max (0x1UL) /*!< Max enumerator value of ENA field. */ + #define DMU_DMUI_ENA_Disabled (0x0UL) /*!< DMU is disabled */ + #define DMU_DMUI_ENA_Enabled (0x1UL) /*!< DMU is enabled and can process DMA data */ + +/* DEHS @Bits 16..18 : Detect Element Handler State */ + #define DMU_DMUI_DEHS_Pos (16UL) /*!< Position of DEHS field. */ + #define DMU_DMUI_DEHS_Msk (0x7UL << DMU_DMUI_DEHS_Pos) /*!< Bit mask of DEHS field. */ + +/* DTX @Bit 20 : Detect DMU Element Service */ + #define DMU_DMUI_DTX_Pos (20UL) /*!< Position of DTX field. */ + #define DMU_DMUI_DTX_Msk (0x1UL << DMU_DMUI_DTX_Pos) /*!< Bit mask of DTX field. */ + #define DMU_DMUI_DTX_Min (0x0UL) /*!< Min enumerator value of DTX field. */ + #define DMU_DMUI_DTX_Max (0x1UL) /*!< Max enumerator value of DTX field. */ + #define DMU_DMUI_DTX_Disabled (0x0UL) /*!< Queueing of DMU Element does not activate interrupt flag */ + #define DMU_DMUI_DTX_Enabled (0x1UL) /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS = + DMUI.DEHS*/ + +/* DRX0 @Bit 21 : Detect DMU Element Service */ + #define DMU_DMUI_DRX0_Pos (21UL) /*!< Position of DRX0 field. */ + #define DMU_DMUI_DRX0_Msk (0x1UL << DMU_DMUI_DRX0_Pos) /*!< Bit mask of DRX0 field. */ + #define DMU_DMUI_DRX0_Min (0x0UL) /*!< Min enumerator value of DRX0 field. */ + #define DMU_DMUI_DRX0_Max (0x1UL) /*!< Max enumerator value of DRX0 field. */ + #define DMU_DMUI_DRX0_Disabled (0x0UL) /*!< Queueing of DMU Element does not activate interrupt flag */ + #define DMU_DMUI_DRX0_Enabled (0x1UL) /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS = + DMUI.DEHS*/ + +/* DRX1 @Bit 22 : Detect DMU Element Service */ + #define DMU_DMUI_DRX1_Pos (22UL) /*!< Position of DRX1 field. */ + #define DMU_DMUI_DRX1_Msk (0x1UL << DMU_DMUI_DRX1_Pos) /*!< Bit mask of DRX1 field. */ + #define DMU_DMUI_DRX1_Min (0x0UL) /*!< Min enumerator value of DRX1 field. */ + #define DMU_DMUI_DRX1_Max (0x1UL) /*!< Max enumerator value of DRX1 field. */ + #define DMU_DMUI_DRX1_Disabled (0x0UL) /*!< Queueing of DMU Element does not activate interrupt flag */ + #define DMU_DMUI_DRX1_Enabled (0x1UL) /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS = + DMUI.DEHS*/ + +/* DTXE @Bit 23 : Detect DMU Element Service */ + #define DMU_DMUI_DTXE_Pos (23UL) /*!< Position of DTXE field. */ + #define DMU_DMUI_DTXE_Msk (0x1UL << DMU_DMUI_DTXE_Pos) /*!< Bit mask of DTXE field. */ + #define DMU_DMUI_DTXE_Min (0x0UL) /*!< Min enumerator value of DTXE field. */ + #define DMU_DMUI_DTXE_Max (0x1UL) /*!< Max enumerator value of DTXE field. */ + #define DMU_DMUI_DTXE_Disabled (0x0UL) /*!< Queueing of DMU Element does not activate interrupt flag */ + #define DMU_DMUI_DTXE_Enabled (0x1UL) /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS = + DMUI.DEHS*/ + +/* EHS @Bits 24..26 : Element Handler State */ + #define DMU_DMUI_EHS_Pos (24UL) /*!< Position of EHS field. */ + #define DMU_DMUI_EHS_Msk (0x7UL << DMU_DMUI_EHS_Pos) /*!< Bit mask of EHS field. */ + #define DMU_DMUI_EHS_Min (0x0UL) /*!< Min enumerator value of EHS field. */ + #define DMU_DMUI_EHS_Max (0x5UL) /*!< Max enumerator value of EHS field. */ + #define DMU_DMUI_EHS_wait4cce (0x0UL) /*!< wait for bit MCAN:CCCR.CCE getting zero */ + #define DMU_DMUI_EHS_wait4sa (0x1UL) /*!< wait for Start Address */ + #define DMU_DMUI_EHS_wait4ta (0x2UL) /*!< wait for Trigger Address */ + #define DMU_DMUI_EHS_transfer (0x3UL) /*!< wait for transfer of Element word */ + #define DMU_DMUI_EHS_ack2mcan (0x4UL) /*!< acknowledge to MCAN */ + #define DMU_DMUI_EHS_recovery (0x5UL) /*!< exception recovery */ + +/* TX @Bit 28 : Actual DMU Element Service */ + #define DMU_DMUI_TX_Pos (28UL) /*!< Position of TX field. */ + #define DMU_DMUI_TX_Msk (0x1UL << DMU_DMUI_TX_Pos) /*!< Bit mask of TX field. */ + #define DMU_DMUI_TX_Min (0x0UL) /*!< Min enumerator value of TX field. */ + #define DMU_DMUI_TX_Max (0x1UL) /*!< Max enumerator value of TX field. */ + #define DMU_DMUI_TX_NotServed (0x0UL) /*!< DMU Virtual Buffer is currently not served */ + #define DMU_DMUI_TX_Served (0x1UL) /*!< DMU Virtual Buffer is currently served */ + +/* RX0 @Bit 29 : Actual DMU Element Service */ + #define DMU_DMUI_RX0_Pos (29UL) /*!< Position of RX0 field. */ + #define DMU_DMUI_RX0_Msk (0x1UL << DMU_DMUI_RX0_Pos) /*!< Bit mask of RX0 field. */ + #define DMU_DMUI_RX0_Min (0x0UL) /*!< Min enumerator value of RX0 field. */ + #define DMU_DMUI_RX0_Max (0x1UL) /*!< Max enumerator value of RX0 field. */ + #define DMU_DMUI_RX0_NotServed (0x0UL) /*!< DMU Virtual Buffer is currently not served */ + #define DMU_DMUI_RX0_Served (0x1UL) /*!< DMU Virtual Buffer is currently served */ + +/* RX1 @Bit 30 : Actual DMU Element Service */ + #define DMU_DMUI_RX1_Pos (30UL) /*!< Position of RX1 field. */ + #define DMU_DMUI_RX1_Msk (0x1UL << DMU_DMUI_RX1_Pos) /*!< Bit mask of RX1 field. */ + #define DMU_DMUI_RX1_Min (0x0UL) /*!< Min enumerator value of RX1 field. */ + #define DMU_DMUI_RX1_Max (0x1UL) /*!< Max enumerator value of RX1 field. */ + #define DMU_DMUI_RX1_NotServed (0x0UL) /*!< DMU Virtual Buffer is currently not served */ + #define DMU_DMUI_RX1_Served (0x1UL) /*!< DMU Virtual Buffer is currently served */ + +/* TXE @Bit 31 : Actual DMU Element Service */ + #define DMU_DMUI_TXE_Pos (31UL) /*!< Position of TXE field. */ + #define DMU_DMUI_TXE_Msk (0x1UL << DMU_DMUI_TXE_Pos) /*!< Bit mask of TXE field. */ + #define DMU_DMUI_TXE_Min (0x0UL) /*!< Min enumerator value of TXE field. */ + #define DMU_DMUI_TXE_Max (0x1UL) /*!< Max enumerator value of TXE field. */ + #define DMU_DMUI_TXE_NotServed (0x0UL) /*!< DMU Virtual Buffer is currently not served */ + #define DMU_DMUI_TXE_Served (0x1UL) /*!< DMU Virtual Buffer is currently served */ + + +/* DMU_DMUQC: DMU Queueing Counter */ + #define DMU_DMUQC_ResetValue (0x00000000UL) /*!< Reset value of DMUQC register. */ + +/* TXEEC @Bits 0..7 : TX Element Enqueueing Counter */ + #define DMU_DMUQC_TXEEC_Pos (0UL) /*!< Position of TXEEC field. */ + #define DMU_DMUQC_TXEEC_Msk (0xFFUL << DMU_DMUQC_TXEEC_Pos) /*!< Bit mask of TXEEC field. */ + +/* RX0EDC @Bits 8..15 : RX0 Element Dequeueing Counter */ + #define DMU_DMUQC_RX0EDC_Pos (8UL) /*!< Position of RX0EDC field. */ + #define DMU_DMUQC_RX0EDC_Msk (0xFFUL << DMU_DMUQC_RX0EDC_Pos) /*!< Bit mask of RX0EDC field. */ + +/* RX1EDC @Bits 16..23 : RX1 Element Dequeueing Counter */ + #define DMU_DMUQC_RX1EDC_Pos (16UL) /*!< Position of RX1EDC field. */ + #define DMU_DMUQC_RX1EDC_Msk (0xFFUL << DMU_DMUQC_RX1EDC_Pos) /*!< Bit mask of RX1EDC field. */ + +/* TXEEDC @Bits 24..31 : TX Event Element Dequeueing Counter */ + #define DMU_DMUQC_TXEEDC_Pos (24UL) /*!< Position of TXEEDC field. */ + #define DMU_DMUQC_TXEEDC_Msk (0xFFUL << DMU_DMUQC_TXEEDC_Pos) /*!< Bit mask of TXEEDC field. */ + + +/* DMU_DMUIR: DMU Interrupt Register */ + #define DMU_DMUIR_ResetValue (0x00000000UL) /*!< Reset value of DMUIR register. */ + +/* TXENSA @Bit 0 : TX Element Not Start Address */ + #define DMU_DMUIR_TXENSA_Pos (0UL) /*!< Position of TXENSA field. */ + #define DMU_DMUIR_TXENSA_Msk (0x1UL << DMU_DMUIR_TXENSA_Pos) /*!< Bit mask of TXENSA field. */ + #define DMU_DMUIR_TXENSA_Min (0x0UL) /*!< Min enumerator value of TXENSA field. */ + #define DMU_DMUIR_TXENSA_Max (0x1UL) /*!< Max enumerator value of TXENSA field. */ + #define DMU_DMUIR_TXENSA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXENSA_NotGenerated (0x0UL) /*!< No illegal write access */ + #define DMU_DMUIR_TXENSA_Generated (0x1UL) /*!< Write to TX Element begins without using start address, exception + recovery started.*/ + +/* TXEIE @Bit 1 : TX Element Illegal Enqueueing */ + #define DMU_DMUIR_TXEIE_Pos (1UL) /*!< Position of TXEIE field. */ + #define DMU_DMUIR_TXEIE_Msk (0x1UL << DMU_DMUIR_TXEIE_Pos) /*!< Bit mask of TXEIE field. */ + #define DMU_DMUIR_TXEIE_Min (0x0UL) /*!< Min enumerator value of TXEIE field. */ + #define DMU_DMUIR_TXEIE_Max (0x1UL) /*!< Max enumerator value of TXEIE field. */ + #define DMU_DMUIR_TXEIE_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEIE_NotGenerated (0x0UL) /*!< No illegal enqueueing */ + #define DMU_DMUIR_TXEIE_Generated (0x1UL) /*!< Start of enqueueing without request detected, exception recovery + started.*/ + +/* TXEIAS @Bit 2 : TX Element Illegal Access Sequence */ + #define DMU_DMUIR_TXEIAS_Pos (2UL) /*!< Position of TXEIAS field. */ + #define DMU_DMUIR_TXEIAS_Msk (0x1UL << DMU_DMUIR_TXEIAS_Pos) /*!< Bit mask of TXEIAS field. */ + #define DMU_DMUIR_TXEIAS_Min (0x0UL) /*!< Min enumerator value of TXEIAS field. */ + #define DMU_DMUIR_TXEIAS_Max (0x1UL) /*!< Max enumerator value of TXEIAS field. */ + #define DMU_DMUIR_TXEIAS_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEIAS_NotGenerated (0x0UL) /*!< No illegal addressing sequence detected */ + #define DMU_DMUIR_TXEIAS_Generated (0x1UL) /*!< Accesses are not strictly linear to ascending and consecutive + addresses, exception recovery started.*/ + +/* TXEIDLC @Bit 3 : TX Element Illegal DLC */ + #define DMU_DMUIR_TXEIDLC_Pos (3UL) /*!< Position of TXEIDLC field. */ + #define DMU_DMUIR_TXEIDLC_Msk (0x1UL << DMU_DMUIR_TXEIDLC_Pos) /*!< Bit mask of TXEIDLC field. */ + #define DMU_DMUIR_TXEIDLC_Min (0x0UL) /*!< Min enumerator value of TXEIDLC field. */ + #define DMU_DMUIR_TXEIDLC_Max (0x1UL) /*!< Max enumerator value of TXEIDLC field. */ + #define DMU_DMUIR_TXEIDLC_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEIDLC_NotGenerated (0x0UL) /*!< No illegal DLC detected */ + #define DMU_DMUIR_TXEIDLC_Generated (0x1UL) /*!< DLC exceeds Tx Buffer element size of MCAN, exception recovery + started.*/ + +/* TXEWATA @Bit 4 : TX Element Write After Trigger Address */ + #define DMU_DMUIR_TXEWATA_Pos (4UL) /*!< Position of TXEWATA field. */ + #define DMU_DMUIR_TXEWATA_Msk (0x1UL << DMU_DMUIR_TXEWATA_Pos) /*!< Bit mask of TXEWATA field. */ + #define DMU_DMUIR_TXEWATA_Min (0x0UL) /*!< Min enumerator value of TXEWATA field. */ + #define DMU_DMUIR_TXEWATA_Max (0x1UL) /*!< Max enumerator value of TXEWATA field. */ + #define DMU_DMUIR_TXEWATA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEWATA_NotGenerated (0x0UL) /*!< No write after Trigger Address */ + #define DMU_DMUIR_TXEWATA_Generated (0x1UL) /*!< Write after Trigger address detected */ + +/* TXEIR @Bit 5 : TX Element Illegal Read */ + #define DMU_DMUIR_TXEIR_Pos (5UL) /*!< Position of TXEIR field. */ + #define DMU_DMUIR_TXEIR_Msk (0x1UL << DMU_DMUIR_TXEIR_Pos) /*!< Bit mask of TXEIR field. */ + #define DMU_DMUIR_TXEIR_Min (0x0UL) /*!< Min enumerator value of TXEIR field. */ + #define DMU_DMUIR_TXEIR_Max (0x1UL) /*!< Max enumerator value of TXEIR field. */ + #define DMU_DMUIR_TXEIR_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEIR_NotGenerated (0x0UL) /*!< No read access */ + #define DMU_DMUIR_TXEIR_Generated (0x1UL) /*!< Illegal read access to DMU TX Element section detected, exception + recovery started.*/ + +/* TXEE @Bit 6 : A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. */ + #define DMU_DMUIR_TXEE_Pos (6UL) /*!< Position of TXEE field. */ + #define DMU_DMUIR_TXEE_Msk (0x1UL << DMU_DMUIR_TXEE_Pos) /*!< Bit mask of TXEE field. */ + #define DMU_DMUIR_TXEE_Min (0x0UL) /*!< Min enumerator value of TXEE field. */ + #define DMU_DMUIR_TXEE_Max (0x1UL) /*!< Max enumerator value of TXEE field. */ + #define DMU_DMUIR_TXEE_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEE_NotGenerated (0x0UL) /*!< No Tx message enqueued */ + #define DMU_DMUIR_TXEE_Generated (0x1UL) /*!< Tx message successfully enqueued */ + +/* RX0ENSA @Bit 7 : RX0 Element Not Start Address */ + #define DMU_DMUIR_RX0ENSA_Pos (7UL) /*!< Position of RX0ENSA field. */ + #define DMU_DMUIR_RX0ENSA_Msk (0x1UL << DMU_DMUIR_RX0ENSA_Pos) /*!< Bit mask of RX0ENSA field. */ + #define DMU_DMUIR_RX0ENSA_Min (0x0UL) /*!< Min enumerator value of RX0ENSA field. */ + #define DMU_DMUIR_RX0ENSA_Max (0x1UL) /*!< Max enumerator value of RX0ENSA field. */ + #define DMU_DMUIR_RX0ENSA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0ENSA_NotGenerated (0x0UL) /*!< No illegal read access */ + #define DMU_DMUIR_RX0ENSA_Generated (0x1UL) /*!< Read from RX0 Element begins without using start address, exception + recovery started.*/ + +/* RX0EID @Bit 8 : RX0 Element Illegal Dequeueing */ + #define DMU_DMUIR_RX0EID_Pos (8UL) /*!< Position of RX0EID field. */ + #define DMU_DMUIR_RX0EID_Msk (0x1UL << DMU_DMUIR_RX0EID_Pos) /*!< Bit mask of RX0EID field. */ + #define DMU_DMUIR_RX0EID_Min (0x0UL) /*!< Min enumerator value of RX0EID field. */ + #define DMU_DMUIR_RX0EID_Max (0x1UL) /*!< Max enumerator value of RX0EID field. */ + #define DMU_DMUIR_RX0EID_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0EID_NotGenerated (0x0UL) /*!< No illegal dequeueing */ + #define DMU_DMUIR_RX0EID_Generated (0x1UL) /*!< Start of dequeueing without request detected, exception recovery + started,*/ + +/* RX0EIAS @Bit 9 : RX0 Element Illegal Access Sequence */ + #define DMU_DMUIR_RX0EIAS_Pos (9UL) /*!< Position of RX0EIAS field. */ + #define DMU_DMUIR_RX0EIAS_Msk (0x1UL << DMU_DMUIR_RX0EIAS_Pos) /*!< Bit mask of RX0EIAS field. */ + #define DMU_DMUIR_RX0EIAS_Min (0x0UL) /*!< Min enumerator value of RX0EIAS field. */ + #define DMU_DMUIR_RX0EIAS_Max (0x1UL) /*!< Max enumerator value of RX0EIAS field. */ + #define DMU_DMUIR_RX0EIAS_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0EIAS_NotGenerated (0x0UL) /*!< No illegal addressing sequence detected */ + #define DMU_DMUIR_RX0EIAS_Generated (0x1UL) /*!< Accesses are not strictly linear to ascending and consecutive + addresses, exception recovery started.*/ + +/* RX0EIW @Bit 10 : RX0 Element Illegal Write */ + #define DMU_DMUIR_RX0EIW_Pos (10UL) /*!< Position of RX0EIW field. */ + #define DMU_DMUIR_RX0EIW_Msk (0x1UL << DMU_DMUIR_RX0EIW_Pos) /*!< Bit mask of RX0EIW field. */ + #define DMU_DMUIR_RX0EIW_Min (0x0UL) /*!< Min enumerator value of RX0EIW field. */ + #define DMU_DMUIR_RX0EIW_Max (0x1UL) /*!< Max enumerator value of RX0EIW field. */ + #define DMU_DMUIR_RX0EIW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0EIW_NotGenerated (0x0UL) /*!< No write access detected */ + #define DMU_DMUIR_RX0EIW_Generated (0x1UL) /*!< Illegal write access to DMU RX0 Element detected, exception recovery + started.*/ + +/* RX0ED @Bit 11 : RX0 Element Dequeued */ + #define DMU_DMUIR_RX0ED_Pos (11UL) /*!< Position of RX0ED field. */ + #define DMU_DMUIR_RX0ED_Msk (0x1UL << DMU_DMUIR_RX0ED_Pos) /*!< Bit mask of RX0ED field. */ + #define DMU_DMUIR_RX0ED_Min (0x0UL) /*!< Min enumerator value of RX0ED field. */ + #define DMU_DMUIR_RX0ED_Max (0x1UL) /*!< Max enumerator value of RX0ED field. */ + #define DMU_DMUIR_RX0ED_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0ED_NotGenerated (0x0UL) /*!< No Rx message dequeued */ + #define DMU_DMUIR_RX0ED_Generated (0x1UL) /*!< Rx message successfully dequeued */ + +/* RX0EIO @Bit 12 : RX0 Element Illegal Overwrite by timestamp */ + #define DMU_DMUIR_RX0EIO_Pos (12UL) /*!< Position of RX0EIO field. */ + #define DMU_DMUIR_RX0EIO_Msk (0x1UL << DMU_DMUIR_RX0EIO_Pos) /*!< Bit mask of RX0EIO field. */ + #define DMU_DMUIR_RX0EIO_Min (0x0UL) /*!< Min enumerator value of RX0EIO field. */ + #define DMU_DMUIR_RX0EIO_Max (0x1UL) /*!< Max enumerator value of RX0EIO field. */ + #define DMU_DMUIR_RX0EIO_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX0EIO_NotGenerated (0x0UL) /*!< No illegal overwrite detected */ + #define DMU_DMUIR_RX0EIO_Generated (0x1UL) /*!< DMU has internally overwritten the last element word of a SYNC + message*/ + +/* BEU @Bit 15 : Bus Error Uncorrected */ + #define DMU_DMUIR_BEU_Pos (15UL) /*!< Position of BEU field. */ + #define DMU_DMUIR_BEU_Msk (0x1UL << DMU_DMUIR_BEU_Pos) /*!< Bit mask of BEU field. */ + #define DMU_DMUIR_BEU_Min (0x0UL) /*!< Min enumerator value of BEU field. */ + #define DMU_DMUIR_BEU_Max (0x1UL) /*!< Max enumerator value of BEU field. */ + #define DMU_DMUIR_BEU_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_BEU_NotGenerated (0x0UL) /*!< No read slave error detected when reading from Message RAM */ + #define DMU_DMUIR_BEU_Generated (0x1UL) /*!< Read slave error detected */ + +/* RX1ENSA @Bit 16 : RX1 Element Not Start Address */ + #define DMU_DMUIR_RX1ENSA_Pos (16UL) /*!< Position of RX1ENSA field. */ + #define DMU_DMUIR_RX1ENSA_Msk (0x1UL << DMU_DMUIR_RX1ENSA_Pos) /*!< Bit mask of RX1ENSA field. */ + #define DMU_DMUIR_RX1ENSA_Min (0x0UL) /*!< Min enumerator value of RX1ENSA field. */ + #define DMU_DMUIR_RX1ENSA_Max (0x1UL) /*!< Max enumerator value of RX1ENSA field. */ + #define DMU_DMUIR_RX1ENSA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1ENSA_NotGenerated (0x0UL) /*!< No illegal read access */ + #define DMU_DMUIR_RX1ENSA_Generated (0x1UL) /*!< Read from RX1 Element begins without using start address, exception + recovery started.*/ + +/* RX1EID @Bit 17 : RX1 Element Illegal Dequeueing */ + #define DMU_DMUIR_RX1EID_Pos (17UL) /*!< Position of RX1EID field. */ + #define DMU_DMUIR_RX1EID_Msk (0x1UL << DMU_DMUIR_RX1EID_Pos) /*!< Bit mask of RX1EID field. */ + #define DMU_DMUIR_RX1EID_Min (0x0UL) /*!< Min enumerator value of RX1EID field. */ + #define DMU_DMUIR_RX1EID_Max (0x1UL) /*!< Max enumerator value of RX1EID field. */ + #define DMU_DMUIR_RX1EID_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1EID_NotGenerated (0x0UL) /*!< No illegal dequeueing */ + #define DMU_DMUIR_RX1EID_Generated (0x1UL) /*!< Start of dequeueing without request detected, exception recovery + started,*/ + +/* RX1EIAS @Bit 18 : RX0 Element Illegal Access Sequence */ + #define DMU_DMUIR_RX1EIAS_Pos (18UL) /*!< Position of RX1EIAS field. */ + #define DMU_DMUIR_RX1EIAS_Msk (0x1UL << DMU_DMUIR_RX1EIAS_Pos) /*!< Bit mask of RX1EIAS field. */ + #define DMU_DMUIR_RX1EIAS_Min (0x0UL) /*!< Min enumerator value of RX1EIAS field. */ + #define DMU_DMUIR_RX1EIAS_Max (0x1UL) /*!< Max enumerator value of RX1EIAS field. */ + #define DMU_DMUIR_RX1EIAS_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1EIAS_NotGenerated (0x0UL) /*!< No illegal addressing sequence detected */ + #define DMU_DMUIR_RX1EIAS_Generated (0x1UL) /*!< Accesses are not strictly linear to ascending and consecutive + addresses, exception recovery started.*/ + +/* RX1EIW @Bit 19 : RX1 Element Illegal Write */ + #define DMU_DMUIR_RX1EIW_Pos (19UL) /*!< Position of RX1EIW field. */ + #define DMU_DMUIR_RX1EIW_Msk (0x1UL << DMU_DMUIR_RX1EIW_Pos) /*!< Bit mask of RX1EIW field. */ + #define DMU_DMUIR_RX1EIW_Min (0x0UL) /*!< Min enumerator value of RX1EIW field. */ + #define DMU_DMUIR_RX1EIW_Max (0x1UL) /*!< Max enumerator value of RX1EIW field. */ + #define DMU_DMUIR_RX1EIW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1EIW_NotGenerated (0x0UL) /*!< No write access detected */ + #define DMU_DMUIR_RX1EIW_Generated (0x1UL) /*!< Illegal write access to DMU RX1 Element detected, exception recovery + started.*/ + +/* RX1ED @Bit 20 : RX0 Element Dequeued */ + #define DMU_DMUIR_RX1ED_Pos (20UL) /*!< Position of RX1ED field. */ + #define DMU_DMUIR_RX1ED_Msk (0x1UL << DMU_DMUIR_RX1ED_Pos) /*!< Bit mask of RX1ED field. */ + #define DMU_DMUIR_RX1ED_Min (0x0UL) /*!< Min enumerator value of RX1ED field. */ + #define DMU_DMUIR_RX1ED_Max (0x1UL) /*!< Max enumerator value of RX1ED field. */ + #define DMU_DMUIR_RX1ED_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1ED_NotGenerated (0x0UL) /*!< No Rx message dequeued */ + #define DMU_DMUIR_RX1ED_Generated (0x1UL) /*!< Rx message successfully dequeued */ + +/* RX1EIO @Bit 21 : RX1 Element Illegal Overwrite by timestamp */ + #define DMU_DMUIR_RX1EIO_Pos (21UL) /*!< Position of RX1EIO field. */ + #define DMU_DMUIR_RX1EIO_Msk (0x1UL << DMU_DMUIR_RX1EIO_Pos) /*!< Bit mask of RX1EIO field. */ + #define DMU_DMUIR_RX1EIO_Min (0x0UL) /*!< Min enumerator value of RX1EIO field. */ + #define DMU_DMUIR_RX1EIO_Max (0x1UL) /*!< Max enumerator value of RX1EIO field. */ + #define DMU_DMUIR_RX1EIO_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_RX1EIO_NotGenerated (0x0UL) /*!< No illegal overwrite detected */ + #define DMU_DMUIR_RX1EIO_Generated (0x1UL) /*!< DMU has internally overwritten the last element word of a SYNC + message*/ + +/* TXEENSA @Bit 24 : TX Event Element Not Start Address */ + #define DMU_DMUIR_TXEENSA_Pos (24UL) /*!< Position of TXEENSA field. */ + #define DMU_DMUIR_TXEENSA_Msk (0x1UL << DMU_DMUIR_TXEENSA_Pos) /*!< Bit mask of TXEENSA field. */ + #define DMU_DMUIR_TXEENSA_Min (0x0UL) /*!< Min enumerator value of TXEENSA field. */ + #define DMU_DMUIR_TXEENSA_Max (0x1UL) /*!< Max enumerator value of TXEENSA field. */ + #define DMU_DMUIR_TXEENSA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEENSA_NotGenerated (0x0UL) /*!< No illegal read access */ + #define DMU_DMUIR_TXEENSA_Generated (0x1UL) /*!< Read from TX Event Element begins without using start address, + exception recovery started.*/ + +/* TXEEID @Bit 25 : TX Event Element Illegal Dequeueing */ + #define DMU_DMUIR_TXEEID_Pos (25UL) /*!< Position of TXEEID field. */ + #define DMU_DMUIR_TXEEID_Msk (0x1UL << DMU_DMUIR_TXEEID_Pos) /*!< Bit mask of TXEEID field. */ + #define DMU_DMUIR_TXEEID_Min (0x0UL) /*!< Min enumerator value of TXEEID field. */ + #define DMU_DMUIR_TXEEID_Max (0x1UL) /*!< Max enumerator value of TXEEID field. */ + #define DMU_DMUIR_TXEEID_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEEID_NotGenerated (0x0UL) /*!< No illegal dequeueing */ + #define DMU_DMUIR_TXEEID_Generated (0x1UL) /*!< Start of dequeueing without request detected, exception recovery + started.*/ + +/* TXEEIAS @Bit 26 : TX Event Element Illegal Access Sequence */ + #define DMU_DMUIR_TXEEIAS_Pos (26UL) /*!< Position of TXEEIAS field. */ + #define DMU_DMUIR_TXEEIAS_Msk (0x1UL << DMU_DMUIR_TXEEIAS_Pos) /*!< Bit mask of TXEEIAS field. */ + #define DMU_DMUIR_TXEEIAS_Min (0x0UL) /*!< Min enumerator value of TXEEIAS field. */ + #define DMU_DMUIR_TXEEIAS_Max (0x1UL) /*!< Max enumerator value of TXEEIAS field. */ + #define DMU_DMUIR_TXEEIAS_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEEIAS_NotGenerated (0x0UL) /*!< No illegal addressing sequence detected */ + #define DMU_DMUIR_TXEEIAS_Generated (0x1UL) /*!< Accesses are not strictly linear to ascending and consecutive + addresses, exception recovery started.*/ + +/* TXEEIW @Bit 27 : TX Event Element Illegal Write */ + #define DMU_DMUIR_TXEEIW_Pos (27UL) /*!< Position of TXEEIW field. */ + #define DMU_DMUIR_TXEEIW_Msk (0x1UL << DMU_DMUIR_TXEEIW_Pos) /*!< Bit mask of TXEEIW field. */ + #define DMU_DMUIR_TXEEIW_Min (0x0UL) /*!< Min enumerator value of TXEEIW field. */ + #define DMU_DMUIR_TXEEIW_Max (0x1UL) /*!< Max enumerator value of TXEEIW field. */ + #define DMU_DMUIR_TXEEIW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEEIW_NotGenerated (0x0UL) /*!< No write access detected */ + #define DMU_DMUIR_TXEEIW_Generated (0x1UL) /*!< Illegal write access to DMU TX Event Element detected, exception + recovery started.*/ + +/* TXEED @Bit 28 : TX Event Element Dequeued */ + #define DMU_DMUIR_TXEED_Pos (28UL) /*!< Position of TXEED field. */ + #define DMU_DMUIR_TXEED_Msk (0x1UL << DMU_DMUIR_TXEED_Pos) /*!< Bit mask of TXEED field. */ + #define DMU_DMUIR_TXEED_Min (0x0UL) /*!< Min enumerator value of TXEED field. */ + #define DMU_DMUIR_TXEED_Max (0x1UL) /*!< Max enumerator value of TXEED field. */ + #define DMU_DMUIR_TXEED_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_TXEED_NotGenerated (0x0UL) /*!< No TX Event Element dequeued */ + #define DMU_DMUIR_TXEED_Generated (0x1UL) /*!< TX Event Element successfully dequeued */ + +/* DT @Bit 29 : Debug Trigger */ + #define DMU_DMUIR_DT_Pos (29UL) /*!< Position of DT field. */ + #define DMU_DMUIR_DT_Msk (0x1UL << DMU_DMUIR_DT_Pos) /*!< Bit mask of DT field. */ + #define DMU_DMUIR_DT_Min (0x0UL) /*!< Min enumerator value of DT field. */ + #define DMU_DMUIR_DT_Max (0x1UL) /*!< Max enumerator value of DT field. */ + #define DMU_DMUIR_DT_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_DT_NotGenerated (0x0UL) /*!< Debug point not reached */ + #define DMU_DMUIR_DT_Generated (0x1UL) /*!< Debug point reached */ + +/* IAC @Bit 30 : Illegal Access while in Configuration mode */ + #define DMU_DMUIR_IAC_Pos (30UL) /*!< Position of IAC field. */ + #define DMU_DMUIR_IAC_Msk (0x1UL << DMU_DMUIR_IAC_Pos) /*!< Bit mask of IAC field. */ + #define DMU_DMUIR_IAC_Min (0x0UL) /*!< Min enumerator value of IAC field. */ + #define DMU_DMUIR_IAC_Max (0x1UL) /*!< Max enumerator value of IAC field. */ + #define DMU_DMUIR_IAC_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define DMU_DMUIR_IAC_NotGenerated (0x0UL) /*!< No Illegal Access while CCE mode */ + #define DMU_DMUIR_IAC_Generated (0x1UL) /*!< Illegal Access while CCE mode */ + + +/* DMU_DMUIE: DMU Interrupt Enable */ + #define DMU_DMUIE_ResetValue (0x00000000UL) /*!< Reset value of DMUIE register. */ + +/* TXENSAE @Bit 0 : TX Element Not Start Address Enable */ + #define DMU_DMUIE_TXENSAE_Pos (0UL) /*!< Position of TXENSAE field. */ + #define DMU_DMUIE_TXENSAE_Msk (0x1UL << DMU_DMUIE_TXENSAE_Pos) /*!< Bit mask of TXENSAE field. */ + #define DMU_DMUIE_TXENSAE_Min (0x0UL) /*!< Min enumerator value of TXENSAE field. */ + #define DMU_DMUIE_TXENSAE_Max (0x1UL) /*!< Max enumerator value of TXENSAE field. */ + #define DMU_DMUIE_TXENSAE_Disabled (0x0UL) /*!< Flag does not activate the interrupt line DMU */ + #define DMU_DMUIE_TXENSAE_Enabled (0x1UL) /*!< the interrupt line DMU will be activated */ + + +/* DMU_DMUC: DMU Configuration */ + #define DMU_DMUC_ResetValue (0x00000000UL) /*!< Reset value of DMUC register. */ + +/* TTS @Bit 0 : Transfer Timestamp */ + #define DMU_DMUC_TTS_Pos (0UL) /*!< Position of TTS field. */ + #define DMU_DMUC_TTS_Msk (0x1UL << DMU_DMUC_TTS_Pos) /*!< Bit mask of TTS field. */ + #define DMU_DMUC_TTS_Min (0x0UL) /*!< Min enumerator value of TTS field. */ + #define DMU_DMUC_TTS_Max (0x1UL) /*!< Max enumerator value of TTS field. */ + #define DMU_DMUC_TTS_Disabled (0x0UL) /*!< No timestamp will be transferred via DMU Virtual Buffer */ + #define DMU_DMUC_TTS_Enabled (0x1UL) /*!< Timestamp of message will be transferred from TSU via DMU Virtual + Buffer*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ DPPIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct DPPIC_TASKS_CHG ================================================== */ +/** + * @brief TASKS_CHG [DPPIC_TASKS_CHG] Channel group tasks + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group n */ +} NRF_DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x008) */ + #define DPPIC_TASKS_CHG_MaxCount (4UL) /*!< Size of TASKS_CHG[4] array. */ + #define DPPIC_TASKS_CHG_MaxIndex (3UL) /*!< Max index of TASKS_CHG[4] array. */ + #define DPPIC_TASKS_CHG_MinIndex (0UL) /*!< Min index of TASKS_CHG[4] array. */ + +/* DPPIC_TASKS_CHG_EN: Enable channel group n */ + #define DPPIC_TASKS_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register. */ + +/* EN @Bit 0 : Enable channel group n */ + #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Min (0x1UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */ + + +/* DPPIC_TASKS_CHG_DIS: Disable channel group n */ + #define DPPIC_TASKS_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register. */ + +/* DIS @Bit 0 : Disable channel group n */ + #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Min (0x1UL) /*!< Min enumerator value of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Max (0x1UL) /*!< Max enumerator value of DIS field. */ + #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */ + + + +/* =============================================== Struct DPPIC_SUBSCRIBE_CHG ================================================ */ +/** + * @brief SUBSCRIBE_CHG [DPPIC_SUBSCRIBE_CHG] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t EN; /*!< (@ 0x00000000) Subscribe configuration for task CHG[n].EN */ + __IOM uint32_t DIS; /*!< (@ 0x00000004) Subscribe configuration for task CHG[n].DIS */ +} NRF_DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x008) */ + #define DPPIC_SUBSCRIBE_CHG_MaxCount (4UL) /*!< Size of SUBSCRIBE_CHG[4] array. */ + #define DPPIC_SUBSCRIBE_CHG_MaxIndex (3UL) /*!< Max index of SUBSCRIBE_CHG[4] array. */ + #define DPPIC_SUBSCRIBE_CHG_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CHG[4] array. */ + +/* DPPIC_SUBSCRIBE_CHG_EN: Subscribe configuration for task CHG[n].EN */ + #define DPPIC_SUBSCRIBE_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].EN will subscribe to */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* DPPIC_SUBSCRIBE_CHG_DIS: Subscribe configuration for task CHG[n].DIS */ + #define DPPIC_SUBSCRIBE_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].DIS will subscribe to */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ====================================================== Struct DPPIC ======================================================= */ +/** + * @brief Distributed programmable peripheral interconnect controller + */ + typedef struct { /*!< DPPIC Structure */ + __OM NRF_DPPIC_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[24]; + __IOM NRF_DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[4]; /*!< (@ 0x00000080) Subscribe configuration for tasks */ + __IM uint32_t RESERVED1[280]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED2[189]; + __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group n Note: Writes to this register are + ignored if either SUBSCRIBE_CHG[n].EN or + SUBSCRIBE_CHG[n].DIS is enabled*/ + } NRF_DPPIC_Type; /*!< Size = 2064 (0x810) */ + +/* DPPIC_CHEN: Channel enable register */ + #define DPPIC_CHEN_ResetValue (0x00000000UL) /*!< Reset value of CHEN register. */ + +/* CH0 @Bit 0 : Enable or disable channel 0 */ + #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHEN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHEN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */ + +/* CH1 @Bit 1 : Enable or disable channel 1 */ + #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHEN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHEN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */ + +/* CH2 @Bit 2 : Enable or disable channel 2 */ + #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHEN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHEN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */ + +/* CH3 @Bit 3 : Enable or disable channel 3 */ + #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHEN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHEN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */ + +/* CH4 @Bit 4 : Enable or disable channel 4 */ + #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHEN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHEN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */ + +/* CH5 @Bit 5 : Enable or disable channel 5 */ + #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHEN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHEN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */ + +/* CH6 @Bit 6 : Enable or disable channel 6 */ + #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHEN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHEN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */ + +/* CH7 @Bit 7 : Enable or disable channel 7 */ + #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHEN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHEN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */ + +/* CH8 @Bit 8 : Enable or disable channel 8 */ + #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHEN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHEN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */ + +/* CH9 @Bit 9 : Enable or disable channel 9 */ + #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHEN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHEN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */ + +/* CH10 @Bit 10 : Enable or disable channel 10 */ + #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHEN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHEN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */ + +/* CH11 @Bit 11 : Enable or disable channel 11 */ + #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHEN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHEN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */ + +/* CH12 @Bit 12 : Enable or disable channel 12 */ + #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHEN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHEN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */ + +/* CH13 @Bit 13 : Enable or disable channel 13 */ + #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHEN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHEN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */ + +/* CH14 @Bit 14 : Enable or disable channel 14 */ + #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHEN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHEN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */ + +/* CH15 @Bit 15 : Enable or disable channel 15 */ + #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHEN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHEN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */ + +/* CH16 @Bit 16 : Enable or disable channel 16 */ + #define DPPIC_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHEN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHEN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHEN_CH16_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH16_Enabled (0x1UL) /*!< Enable channel */ + +/* CH17 @Bit 17 : Enable or disable channel 17 */ + #define DPPIC_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHEN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHEN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHEN_CH17_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH17_Enabled (0x1UL) /*!< Enable channel */ + +/* CH18 @Bit 18 : Enable or disable channel 18 */ + #define DPPIC_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHEN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHEN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHEN_CH18_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH18_Enabled (0x1UL) /*!< Enable channel */ + +/* CH19 @Bit 19 : Enable or disable channel 19 */ + #define DPPIC_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHEN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHEN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHEN_CH19_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH19_Enabled (0x1UL) /*!< Enable channel */ + +/* CH20 @Bit 20 : Enable or disable channel 20 */ + #define DPPIC_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHEN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHEN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHEN_CH20_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH20_Enabled (0x1UL) /*!< Enable channel */ + +/* CH21 @Bit 21 : Enable or disable channel 21 */ + #define DPPIC_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHEN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHEN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHEN_CH21_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH21_Enabled (0x1UL) /*!< Enable channel */ + +/* CH22 @Bit 22 : Enable or disable channel 22 */ + #define DPPIC_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHEN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHEN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHEN_CH22_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH22_Enabled (0x1UL) /*!< Enable channel */ + +/* CH23 @Bit 23 : Enable or disable channel 23 */ + #define DPPIC_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHEN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHEN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHEN_CH23_Disabled (0x0UL) /*!< Disable channel */ + #define DPPIC_CHEN_CH23_Enabled (0x1UL) /*!< Enable channel */ + + +/* DPPIC_CHENSET: Channel enable set register */ + #define DPPIC_CHENSET_ResetValue (0x00000000UL) /*!< Reset value of CHENSET register. */ + +/* CH0 @Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHENSET_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHENSET_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH1 @Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHENSET_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHENSET_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH2 @Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHENSET_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHENSET_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH3 @Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHENSET_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHENSET_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH4 @Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHENSET_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHENSET_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH5 @Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHENSET_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHENSET_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH6 @Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHENSET_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHENSET_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH7 @Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHENSET_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHENSET_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH8 @Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHENSET_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHENSET_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH9 @Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHENSET_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHENSET_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH10 @Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHENSET_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHENSET_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH11 @Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHENSET_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHENSET_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH12 @Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHENSET_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHENSET_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH13 @Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHENSET_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHENSET_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH14 @Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHENSET_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHENSET_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH15 @Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHENSET_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHENSET_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH16 @Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHENSET_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHENSET_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHENSET_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH16_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH17 @Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHENSET_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHENSET_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHENSET_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH17_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH18 @Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHENSET_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHENSET_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHENSET_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH18_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH19 @Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHENSET_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHENSET_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHENSET_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH19_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH20 @Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHENSET_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHENSET_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHENSET_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH20_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH21 @Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHENSET_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHENSET_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHENSET_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH21_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH22 @Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHENSET_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHENSET_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHENSET_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH22_Set (0x1UL) /*!< Write: Enable channel */ + +/* CH23 @Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */ + #define DPPIC_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHENSET_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHENSET_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHENSET_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENSET_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENSET_CH23_Set (0x1UL) /*!< Write: Enable channel */ + + +/* DPPIC_CHENCLR: Channel enable clear register */ + #define DPPIC_CHENCLR_ResetValue (0x00000000UL) /*!< Reset value of CHENCLR register. */ + +/* CH0 @Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH1 @Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH2 @Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH3 @Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH4 @Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH5 @Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH6 @Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH7 @Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH8 @Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH9 @Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH10 @Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH11 @Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH12 @Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH13 @Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH14 @Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH15 @Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH16 @Bit 16 : Channel 16 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHENCLR_CH16_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH16_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH16_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH17 @Bit 17 : Channel 17 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHENCLR_CH17_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH17_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH17_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH18 @Bit 18 : Channel 18 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHENCLR_CH18_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH18_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH18_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH19 @Bit 19 : Channel 19 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHENCLR_CH19_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH19_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH19_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH20 @Bit 20 : Channel 20 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHENCLR_CH20_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH20_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH20_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH21 @Bit 21 : Channel 21 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHENCLR_CH21_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH21_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH21_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH22 @Bit 22 : Channel 22 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHENCLR_CH22_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH22_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH22_Clear (0x1UL) /*!< Write: Disable channel */ + +/* CH23 @Bit 23 : Channel 23 enable clear register. Writing 0 has no effect. */ + #define DPPIC_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHENCLR_CH23_Disabled (0x0UL) /*!< Read: Channel disabled */ + #define DPPIC_CHENCLR_CH23_Enabled (0x1UL) /*!< Read: Channel enabled */ + #define DPPIC_CHENCLR_CH23_Clear (0x1UL) /*!< Write: Disable channel */ + + +/* DPPIC_CHG: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is + enabled */ + + #define DPPIC_CHG_MaxCount (4UL) /*!< Max size of CHG[4] array. */ + #define DPPIC_CHG_MaxIndex (3UL) /*!< Max index of CHG[4] array. */ + #define DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[4] array. */ + #define DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[4] register. */ + +/* CH0 @Bit 0 : Include or exclude channel 0 */ + #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define DPPIC_CHG_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define DPPIC_CHG_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */ + +/* CH1 @Bit 1 : Include or exclude channel 1 */ + #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define DPPIC_CHG_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define DPPIC_CHG_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */ + +/* CH2 @Bit 2 : Include or exclude channel 2 */ + #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define DPPIC_CHG_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define DPPIC_CHG_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */ + +/* CH3 @Bit 3 : Include or exclude channel 3 */ + #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define DPPIC_CHG_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define DPPIC_CHG_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */ + +/* CH4 @Bit 4 : Include or exclude channel 4 */ + #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define DPPIC_CHG_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define DPPIC_CHG_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */ + +/* CH5 @Bit 5 : Include or exclude channel 5 */ + #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define DPPIC_CHG_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define DPPIC_CHG_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */ + +/* CH6 @Bit 6 : Include or exclude channel 6 */ + #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define DPPIC_CHG_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define DPPIC_CHG_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */ + +/* CH7 @Bit 7 : Include or exclude channel 7 */ + #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define DPPIC_CHG_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define DPPIC_CHG_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */ + +/* CH8 @Bit 8 : Include or exclude channel 8 */ + #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define DPPIC_CHG_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define DPPIC_CHG_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */ + +/* CH9 @Bit 9 : Include or exclude channel 9 */ + #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define DPPIC_CHG_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define DPPIC_CHG_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */ + +/* CH10 @Bit 10 : Include or exclude channel 10 */ + #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define DPPIC_CHG_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define DPPIC_CHG_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */ + +/* CH11 @Bit 11 : Include or exclude channel 11 */ + #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define DPPIC_CHG_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define DPPIC_CHG_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */ + +/* CH12 @Bit 12 : Include or exclude channel 12 */ + #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define DPPIC_CHG_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define DPPIC_CHG_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */ + +/* CH13 @Bit 13 : Include or exclude channel 13 */ + #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define DPPIC_CHG_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define DPPIC_CHG_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */ + +/* CH14 @Bit 14 : Include or exclude channel 14 */ + #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define DPPIC_CHG_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define DPPIC_CHG_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */ + +/* CH15 @Bit 15 : Include or exclude channel 15 */ + #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define DPPIC_CHG_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define DPPIC_CHG_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */ + +/* CH16 @Bit 16 : Include or exclude channel 16 */ + #define DPPIC_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define DPPIC_CHG_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define DPPIC_CHG_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define DPPIC_CHG_CH16_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH16_Included (0x1UL) /*!< Include */ + +/* CH17 @Bit 17 : Include or exclude channel 17 */ + #define DPPIC_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define DPPIC_CHG_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define DPPIC_CHG_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define DPPIC_CHG_CH17_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH17_Included (0x1UL) /*!< Include */ + +/* CH18 @Bit 18 : Include or exclude channel 18 */ + #define DPPIC_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define DPPIC_CHG_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define DPPIC_CHG_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define DPPIC_CHG_CH18_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH18_Included (0x1UL) /*!< Include */ + +/* CH19 @Bit 19 : Include or exclude channel 19 */ + #define DPPIC_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define DPPIC_CHG_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define DPPIC_CHG_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define DPPIC_CHG_CH19_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH19_Included (0x1UL) /*!< Include */ + +/* CH20 @Bit 20 : Include or exclude channel 20 */ + #define DPPIC_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define DPPIC_CHG_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define DPPIC_CHG_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define DPPIC_CHG_CH20_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH20_Included (0x1UL) /*!< Include */ + +/* CH21 @Bit 21 : Include or exclude channel 21 */ + #define DPPIC_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define DPPIC_CHG_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define DPPIC_CHG_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define DPPIC_CHG_CH21_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH21_Included (0x1UL) /*!< Include */ + +/* CH22 @Bit 22 : Include or exclude channel 22 */ + #define DPPIC_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define DPPIC_CHG_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define DPPIC_CHG_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define DPPIC_CHG_CH22_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH22_Included (0x1UL) /*!< Include */ + +/* CH23 @Bit 23 : Include or exclude channel 23 */ + #define DPPIC_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define DPPIC_CHG_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define DPPIC_CHG_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define DPPIC_CHG_CH23_Excluded (0x0UL) /*!< Exclude */ + #define DPPIC_CHG_CH23_Included (0x1UL) /*!< Include */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct ECB_KEY ====================================================== */ +/** + * @brief KEY [ECB_KEY] (unspecified) + */ +typedef struct { + __OM uint32_t VALUE[4]; /*!< (@ 0x00000000) 128-bit AES key */ +} NRF_ECB_KEY_Type; /*!< Size = 16 (0x010) */ + +/* ECB_KEY_VALUE: 128-bit AES key */ + #define ECB_KEY_VALUE_MaxCount (4UL) /*!< Max size of VALUE[4] array. */ + #define ECB_KEY_VALUE_MaxIndex (3UL) /*!< Max index of VALUE[4] array. */ + #define ECB_KEY_VALUE_MinIndex (0UL) /*!< Min index of VALUE[4] array. */ + #define ECB_KEY_VALUE_ResetValue (0x00000000UL) /*!< Reset value of VALUE[4] register. */ + +/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(n+1))-1 : (32*n) */ + #define ECB_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ECB_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << ECB_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ====================================================== Struct ECB_IN ====================================================== */ +/** + * @brief IN [ECB_IN] IN EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Input pointer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Number of bytes read from the input data, not including + the job list structure*/ +} NRF_ECB_IN_Type; /*!< Size = 8 (0x008) */ + +/* ECB_IN_PTR: Input pointer */ + #define ECB_IN_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Points to a job list containing unencrypted ECB data structure */ + #define ECB_IN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define ECB_IN_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* ECB_IN_AMOUNT: Number of bytes read from the input data, not including the job list structure */ + #define ECB_IN_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..31 : Number of bytes read from the input data */ + #define ECB_IN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define ECB_IN_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << ECB_IN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + + +/* ===================================================== Struct ECB_OUT ====================================================== */ +/** + * @brief OUT [ECB_OUT] OUT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Output pointer Points to a job list containing + encrypted ECB data structure*/ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Number of bytes available in the output data, not + including the job list structure*/ +} NRF_ECB_OUT_Type; /*!< Size = 8 (0x008) */ + +/* ECB_OUT_PTR: Output pointer Points to a job list containing encrypted ECB data structure */ + #define ECB_OUT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Output pointer */ + #define ECB_OUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define ECB_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* ECB_OUT_AMOUNT: Number of bytes available in the output data, not including the job list structure */ + #define ECB_OUT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..31 : Number of bytes available in the output data */ + #define ECB_OUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define ECB_OUT_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << ECB_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* ======================================================= Struct ECB ======================================================== */ +/** + * @brief AES ECB Mode Encryption + */ + typedef struct { /*!< ECB Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOP task or due + to an error*/ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000184) Publish configuration for event ERROR */ + __IM uint32_t RESERVED3[95]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[129]; + __IOM NRF_ECB_KEY_Type KEY; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED5[4]; + __IOM NRF_ECB_IN_Type IN; /*!< (@ 0x00000530) IN EasyDMA channel */ + __IOM NRF_ECB_OUT_Type OUT; /*!< (@ 0x00000538) OUT EasyDMA channel */ + } NRF_ECB_Type; /*!< Size = 1344 (0x540) */ + +/* ECB_TASKS_START: Start ECB block encrypt */ + #define ECB_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start ECB block encrypt */ + #define ECB_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Msk (0x1UL << ECB_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define ECB_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* ECB_TASKS_STOP: Abort a possible executing ECB operation */ + #define ECB_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Abort a possible executing ECB operation */ + #define ECB_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Msk (0x1UL << ECB_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define ECB_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* ECB_SUBSCRIBE_START: Subscribe configuration for task START */ + #define ECB_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define ECB_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Msk (0x1UL << ECB_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define ECB_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ECB_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define ECB_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define ECB_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* ECB_EVENTS_END: ECB block encrypt complete */ + #define ECB_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : ECB block encrypt complete */ + #define ECB_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Msk (0x1UL << ECB_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define ECB_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define ECB_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* ECB_EVENTS_ERROR: ECB block encrypt aborted because of a STOP task or due to an error */ + #define ECB_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : ECB block encrypt aborted because of a STOP task or due to an error */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << ECB_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define ECB_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* ECB_PUBLISH_END: Publish configuration for event END */ + #define ECB_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define ECB_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Msk (0xFFUL << ECB_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_PUBLISH_END_EN_Msk (0x1UL << ECB_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define ECB_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ECB_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define ECB_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define ECB_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define ECB_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define ECB_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Msk (0x1UL << ECB_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ECB_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define ECB_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ECB_INTENSET: Enable interrupt */ + #define ECB_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 0 : Write '1' to enable interrupt for event END */ + #define ECB_INTENSET_END_Pos (0UL) /*!< Position of END field. */ + #define ECB_INTENSET_END_Msk (0x1UL << ECB_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define ECB_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define ECB_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define ECB_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define ECB_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 1 : Write '1' to enable interrupt for event ERROR */ + #define ECB_INTENSET_ERROR_Pos (1UL) /*!< Position of ERROR field. */ + #define ECB_INTENSET_ERROR_Msk (0x1UL << ECB_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define ECB_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define ECB_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define ECB_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define ECB_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* ECB_INTENCLR: Disable interrupt */ + #define ECB_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 0 : Write '1' to disable interrupt for event END */ + #define ECB_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ + #define ECB_INTENCLR_END_Msk (0x1UL << ECB_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define ECB_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define ECB_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define ECB_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define ECB_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 1 : Write '1' to disable interrupt for event ERROR */ + #define ECB_INTENCLR_ERROR_Pos (1UL) /*!< Position of ERROR field. */ + #define ECB_INTENCLR_ERROR_Msk (0x1UL << ECB_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define ECB_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define ECB_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define ECB_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define ECB_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define ECB_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ EGU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct EGU ======================================================== */ +/** + * @brief Event generator unit + */ + typedef struct { /*!< EGU Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Trigger n for triggering the corresponding TRIGGERED[n] + event*/ + __IM uint32_t RESERVED[16]; + __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Subscribe configuration for task TRIGGER[n] */ + __IM uint32_t RESERVED1[16]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Event number n generated by triggering the + corresponding TRIGGER[n] task*/ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Publish configuration for event TRIGGERED[n] */ + __IM uint32_t RESERVED3[80]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + } NRF_EGU_Type; /*!< Size = 784 (0x310) */ + +/* EGU_TASKS_TRIGGER: Trigger n for triggering the corresponding TRIGGERED[n] event */ + #define EGU_TASKS_TRIGGER_MaxCount (16UL) /*!< Max size of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_MaxIndex (15UL) /*!< Max index of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[16] array. */ + #define EGU_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[16] register. */ + +/* TASKS_TRIGGER @Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER + field.*/ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +/* EGU_SUBSCRIBE_TRIGGER: Subscribe configuration for task TRIGGER[n] */ + #define EGU_SUBSCRIBE_TRIGGER_MaxCount (16UL) /*!< Max size of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_MaxIndex (15UL) /*!< Max index of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[16] array. */ + #define EGU_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task TRIGGER[n] will subscribe to */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* EGU_EVENTS_TRIGGERED: Event number n generated by triggering the corresponding TRIGGER[n] task */ + #define EGU_EVENTS_TRIGGERED_MaxCount (16UL) /*!< Max size of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_MaxIndex (15UL) /*!< Max index of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[16] array. */ + #define EGU_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[16] register. */ + +/* EVENTS_TRIGGERED @Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of + EVENTS_TRIGGERED field.*/ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field. */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ + #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ + + +/* EGU_PUBLISH_TRIGGERED: Publish configuration for event TRIGGERED[n] */ + #define EGU_PUBLISH_TRIGGERED_MaxCount (16UL) /*!< Max size of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_MaxIndex (15UL) /*!< Max index of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[16] array. */ + #define EGU_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TRIGGERED[n] will publish to */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define EGU_PUBLISH_TRIGGERED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* EGU_INTEN: Enable or disable interrupt */ + #define EGU_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + + +/* EGU_INTENSET: Enable interrupt */ + #define EGU_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* EGU_INTENCLR: Disable interrupt */ + #define EGU_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* EGU_INTPEND: Pending interrupts */ + #define EGU_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define EGU_INTPEND_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define EGU_INTPEND_TRIGGERED0_Msk (0x1UL << EGU_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define EGU_INTPEND_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define EGU_INTPEND_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define EGU_INTPEND_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define EGU_INTPEND_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define EGU_INTPEND_TRIGGERED1_Msk (0x1UL << EGU_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define EGU_INTPEND_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define EGU_INTPEND_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define EGU_INTPEND_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define EGU_INTPEND_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define EGU_INTPEND_TRIGGERED2_Msk (0x1UL << EGU_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define EGU_INTPEND_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define EGU_INTPEND_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define EGU_INTPEND_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define EGU_INTPEND_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define EGU_INTPEND_TRIGGERED3_Msk (0x1UL << EGU_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define EGU_INTPEND_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define EGU_INTPEND_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define EGU_INTPEND_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define EGU_INTPEND_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define EGU_INTPEND_TRIGGERED4_Msk (0x1UL << EGU_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define EGU_INTPEND_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define EGU_INTPEND_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define EGU_INTPEND_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define EGU_INTPEND_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define EGU_INTPEND_TRIGGERED5_Msk (0x1UL << EGU_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define EGU_INTPEND_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define EGU_INTPEND_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define EGU_INTPEND_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define EGU_INTPEND_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define EGU_INTPEND_TRIGGERED6_Msk (0x1UL << EGU_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define EGU_INTPEND_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define EGU_INTPEND_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define EGU_INTPEND_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define EGU_INTPEND_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define EGU_INTPEND_TRIGGERED7_Msk (0x1UL << EGU_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define EGU_INTPEND_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define EGU_INTPEND_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define EGU_INTPEND_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define EGU_INTPEND_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define EGU_INTPEND_TRIGGERED8_Msk (0x1UL << EGU_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define EGU_INTPEND_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define EGU_INTPEND_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define EGU_INTPEND_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define EGU_INTPEND_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define EGU_INTPEND_TRIGGERED9_Msk (0x1UL << EGU_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define EGU_INTPEND_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define EGU_INTPEND_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define EGU_INTPEND_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define EGU_INTPEND_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define EGU_INTPEND_TRIGGERED10_Msk (0x1UL << EGU_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define EGU_INTPEND_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define EGU_INTPEND_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define EGU_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define EGU_INTPEND_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define EGU_INTPEND_TRIGGERED11_Msk (0x1UL << EGU_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define EGU_INTPEND_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define EGU_INTPEND_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define EGU_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define EGU_INTPEND_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define EGU_INTPEND_TRIGGERED12_Msk (0x1UL << EGU_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define EGU_INTPEND_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define EGU_INTPEND_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define EGU_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define EGU_INTPEND_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define EGU_INTPEND_TRIGGERED13_Msk (0x1UL << EGU_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define EGU_INTPEND_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define EGU_INTPEND_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define EGU_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define EGU_INTPEND_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define EGU_INTPEND_TRIGGERED14_Msk (0x1UL << EGU_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define EGU_INTPEND_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define EGU_INTPEND_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define EGU_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define EGU_INTPEND_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define EGU_INTPEND_TRIGGERED15_Msk (0x1UL << EGU_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define EGU_INTPEND_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define EGU_INTPEND_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define EGU_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define EGU_INTPEND_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ETB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct ETB ======================================================== */ +/** + * @brief Embedded Trace Buffer + */ + typedef struct { /*!< ETB Structure */ + __IM uint32_t RESERVED; + __IM uint32_t RDP; /*!< (@ 0x00000004) ETB RAM Depth Register */ + __IM uint32_t RESERVED1; + __IM uint32_t STS; /*!< (@ 0x0000000C) ETB Status Register */ + __IM uint32_t RRD; /*!< (@ 0x00000010) ETB RAM Read Data Register */ + __IOM uint32_t RRP; /*!< (@ 0x00000014) ETB RAM Read Pointer Register */ + __IOM uint32_t RWP; /*!< (@ 0x00000018) ETB RAM Write Pointer Register */ + __IOM uint32_t TRG; /*!< (@ 0x0000001C) ETB Trigger Counter Register */ + __IOM uint32_t CTL; /*!< (@ 0x00000020) ETB Control Register */ + __IOM uint32_t RWD; /*!< (@ 0x00000024) ETB RAM Write Data Register */ + __IM uint32_t RESERVED2[182]; + __IM uint32_t FFSR; /*!< (@ 0x00000300) ETB Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< (@ 0x00000304) ETB Formatter and Flush Control Register */ + __IM uint32_t RESERVED3[758]; + __OM uint32_t ITMISCOP0; /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 0 */ + __OM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) Integration Test Trigger In and Flush In Acknowledge + Register*/ + __IM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register */ + __IM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0 */ + __OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Integration Test ATB Control Register 2 */ + __IM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) Integration Test ATB Control Register 1 */ + __IM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) Integration Test ATB Control Register 0 */ + __IM uint32_t RESERVED4; + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Integration Mode Control Register */ + __IM uint32_t RESERVED5[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Claim Tag Set Register */ + __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Claim Tag Clear Register */ + __IM uint32_t RESERVED6[2]; + __OM uint32_t LAR; /*!< (@ 0x00000FB0) Lock Access Register */ + __IM uint32_t LSR; /*!< (@ 0x00000FB4) Lock Status Register */ + __IM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Authentication Status Register */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier Register */ + __IM uint32_t PERIPHID4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ + __IM uint32_t RESERVED8[3]; + __IM uint32_t PERIPHID0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ + __IM uint32_t PERIPHID1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ + __IM uint32_t PERIPHID2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ + __IM uint32_t PERIPHID3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ + __IM uint32_t COMPID0; /*!< (@ 0x00000FF0) Component ID0 Register */ + __IM uint32_t COMPID1; /*!< (@ 0x00000FF4) Component ID1 Register */ + __IM uint32_t COMPID2; /*!< (@ 0x00000FF8) Component ID2 Register */ + __IM uint32_t COMPID3; /*!< (@ 0x00000FFC) Component ID3 Register */ + } NRF_ETB_Type; /*!< Size = 4096 (0x1000) */ + +/* ETB_RDP: ETB RAM Depth Register */ + #define ETB_RDP_ResetValue (0x00000000UL) /*!< Reset value of RDP register. */ + +/* ETB_RAM_DEPTH @Bits 0..31 : Defines the depth, in words, of the trace RAM. */ + #define ETB_RDP_ETB_RAM_DEPTH_Pos (0UL) /*!< Position of ETB_RAM_DEPTH field. */ + #define ETB_RDP_ETB_RAM_DEPTH_Msk (0xFFFFFFFFUL << ETB_RDP_ETB_RAM_DEPTH_Pos) /*!< Bit mask of ETB_RAM_DEPTH field. */ + + +/* ETB_STS: ETB Status Register */ + #define ETB_STS_ResetValue (0x00000008UL) /*!< Reset value of STS register. */ + +/* FULL @Bit 0 : RAM Full. The flag indicates when the RAM write pointer has wrapped around. */ + #define ETB_STS_FULL_Pos (0UL) /*!< Position of FULL field. */ + #define ETB_STS_FULL_Msk (0x1UL << ETB_STS_FULL_Pos) /*!< Bit mask of FULL field. */ + +/* TRIGGERED @Bit 1 : The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been + embedded in the trace data by the formatter, but is determined by the programming of the Formatter and + Flush Control Register. */ + + #define ETB_STS_TRIGGERED_Pos (1UL) /*!< Position of TRIGGERED field. */ + #define ETB_STS_TRIGGERED_Msk (0x1UL << ETB_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */ + +/* ACQCOMP @Bit 2 : The acquisition complete flag indicates that capture has been completed when the formatter stops because of + any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also + results in FtStopped in the Formatter and Flush Status Register going HIGH. */ + + #define ETB_STS_ACQCOMP_Pos (2UL) /*!< Position of ACQCOMP field. */ + #define ETB_STS_ACQCOMP_Msk (0x1UL << ETB_STS_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */ + +/* FTEMPTY @Bit 3 : Formatter pipeline empty. All data stored to RAM. */ + #define ETB_STS_FTEMPTY_Pos (3UL) /*!< Position of FTEMPTY field. */ + #define ETB_STS_FTEMPTY_Msk (0x1UL << ETB_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field. */ + + +/* ETB_RRD: ETB RAM Read Data Register */ + #define ETB_RRD_ResetValue (0x00000000UL) /*!< Reset value of RRD register. */ + +/* RAM_READ_DATA @Bits 0..31 : Data read from the ETB Trace RAM. */ + #define ETB_RRD_RAM_READ_DATA_Pos (0UL) /*!< Position of RAM_READ_DATA field. */ + #define ETB_RRD_RAM_READ_DATA_Msk (0xFFFFFFFFUL << ETB_RRD_RAM_READ_DATA_Pos) /*!< Bit mask of RAM_READ_DATA field. */ + + +/* ETB_RRP: ETB RAM Read Pointer Register */ + #define ETB_RRP_ResetValue (0x00000000UL) /*!< Reset value of RRP register. */ + +/* RAM_READ_POINTER @Bits 0..9 : Sets the read pointer used to read entries from the Trace RAM over the APB interface. */ + #define ETB_RRP_RAM_READ_POINTER_Pos (0UL) /*!< Position of RAM_READ_POINTER field. */ + #define ETB_RRP_RAM_READ_POINTER_Msk (0x3FFUL << ETB_RRP_RAM_READ_POINTER_Pos) /*!< Bit mask of RAM_READ_POINTER field. */ + + +/* ETB_RWP: ETB RAM Write Pointer Register */ + #define ETB_RWP_ResetValue (0x00000000UL) /*!< Reset value of RWP register. */ + +/* RAM_WRITE_POINTER @Bits 0..9 : Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM. */ + #define ETB_RWP_RAM_WRITE_POINTER_Pos (0UL) /*!< Position of RAM_WRITE_POINTER field. */ + #define ETB_RWP_RAM_WRITE_POINTER_Msk (0x3FFUL << ETB_RWP_RAM_WRITE_POINTER_Pos) /*!< Bit mask of RAM_WRITE_POINTER field. */ + + +/* ETB_TRG: ETB Trigger Counter Register */ + #define ETB_TRG_ResetValue (0x00000000UL) /*!< Reset value of TRG register. */ + +/* TRIGGER_COUNTER @Bits 0..9 : The counter is used as follows:Trace after - The counter is set to a large value, slightly less + than the number of entries in the RAM. Trace before - The counter is set to a small value. Trace + about - The counter is set to half the depth of the Trace RAM. This register must not be written + to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the + register is not updated. A read access is permitted with trace capture enabled. */ + + #define ETB_TRG_TRIGGER_COUNTER_Pos (0UL) /*!< Position of TRIGGER_COUNTER field. */ + #define ETB_TRG_TRIGGER_COUNTER_Msk (0x3FFUL << ETB_TRG_TRIGGER_COUNTER_Pos) /*!< Bit mask of TRIGGER_COUNTER field. */ + + +/* ETB_CTL: ETB Control Register */ + #define ETB_CTL_ResetValue (0x00000000UL) /*!< Reset value of CTL register. */ + +/* TRACECAPTEN @Bit 0 : ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW. + When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is + stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes + HIGH. See ETB Formatter and Flush Status Register, FFSR, 0x300. */ + + #define ETB_CTL_TRACECAPTEN_Pos (0UL) /*!< Position of TRACECAPTEN field. */ + #define ETB_CTL_TRACECAPTEN_Msk (0x1UL << ETB_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field. */ + + +/* ETB_RWD: ETB RAM Write Data Register */ + #define ETB_RWD_ResetValue (0x00000000UL) /*!< Reset value of RWD register. */ + +/* RAM_WRITE_DATA @Bits 0..31 : Data written to the ETB Trace RAM. When trace capture is disabled, the contents of this register + are placed into the ETB Trace RAM when this register is written to. Writing to this register + increments the RAM Write Pointer Register. If trace capture is enabled, and this register is + accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never + increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a + synchronization output from the ETB. If a write access is attempted, the data is not written + into Trace RAM. */ + + #define ETB_RWD_RAM_WRITE_DATA_Pos (0UL) /*!< Position of RAM_WRITE_DATA field. */ + #define ETB_RWD_RAM_WRITE_DATA_Msk (0xFFFFFFFFUL << ETB_RWD_RAM_WRITE_DATA_Pos) /*!< Bit mask of RAM_WRITE_DATA field. */ + + +/* ETB_FFSR: ETB Formatter and Flush Status Register */ + #define ETB_FFSR_ResetValue (0x00000002UL) /*!< Reset value of FFSR register. */ + +/* FLINPROG @Bit 0 : Flush In Progress. This is an indication of the current state of afvalids. */ + #define ETB_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */ + #define ETB_FFSR_FLINPROG_Msk (0x1UL << ETB_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */ + +/* FTSTOPPED @Bit 1 : Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has + been output. Any more trace data on the ATB interface is ignored and atreadys goes HIGH. */ + + #define ETB_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */ + #define ETB_FFSR_FTSTOPPED_Msk (0x1UL << ETB_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */ + + +/* ETB_FFCR: ETB Formatter and Flush Control Register */ + #define ETB_FFCR_ResetValue (0x00000000UL) /*!< Reset value of FFCR register. */ + +/* ENFTC @Bit 0 : Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, + where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */ + + #define ETB_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */ + #define ETB_FFCR_ENFTC_Msk (0x1UL << ETB_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */ + +/* ENFCONT @Bit 1 : Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed + when FtStopped is HIGH. This bit is clear on reset. */ + + #define ETB_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */ + #define ETB_FFCR_ENFCONT_Msk (0x1UL << ETB_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */ + +/* FONFLIN @Bit 4 : Set this bit to enable use of the flushin connection. This is clear on reset. */ + #define ETB_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */ + #define ETB_FFCR_FONFLIN_Msk (0x1UL << ETB_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */ + +/* FONTRIG @Bit 5 : Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event + occurs. This bit is clear on reset. A Trigger Event is defined as when the Trigger counter reaches zero + (where fitted) or, in the case of the trigger counter being zero (or not fitted), when trigin is HIGH. */ + + #define ETB_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */ + #define ETB_FFCR_FONTRIG_Msk (0x1UL << ETB_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */ + +/* FONMAN @Bit 6 : Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit + is clear on reset. */ + + #define ETB_FFCR_FONMAN_Pos (6UL) /*!< Position of FONMAN field. */ + #define ETB_FFCR_FONMAN_Msk (0x1UL << ETB_FFCR_FONMAN_Pos) /*!< Bit mask of FONMAN field. */ + +/* TRIGIN @Bit 8 : Indicate a trigger on trigin being asserted. */ + #define ETB_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */ + #define ETB_FFCR_TRIGIN_Msk (0x1UL << ETB_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ + +/* TRIGEVT @Bit 9 : Indicate a trigger on a Trigger Event. */ + #define ETB_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */ + #define ETB_FFCR_TRIGEVT_Msk (0x1UL << ETB_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */ + +/* TRIGFL @Bit 10 : Indicates a trigger on Flush completion (afreadys being returned). */ + #define ETB_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */ + #define ETB_FFCR_TRIGFL_Msk (0x1UL << ETB_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */ + +/* STOPFL @Bit 12 : This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but + this is clear on reset (disabled). */ + + #define ETB_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */ + #define ETB_FFCR_STOPFL_Msk (0x1UL << ETB_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */ + +/* STOPTRIG @Bit 13 : Stop the formatter after a Trigger Event is observed. Reset to disabled (zero). */ + #define ETB_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */ + #define ETB_FFCR_STOPTRIG_Msk (0x1UL << ETB_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */ + + +/* ETB_ITMISCOP0: Integration Test Miscellaneous Output Register 0 */ + #define ETB_ITMISCOP0_ResetValue (0x00000000UL) /*!< Reset value of ITMISCOP0 register. */ + +/* ACQCOMP @Bit 0 : Set the value of acqcomp. */ + #define ETB_ITMISCOP0_ACQCOMP_Pos (0UL) /*!< Position of ACQCOMP field. */ + #define ETB_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETB_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */ + +/* FULL @Bit 1 : Set the value of full output port. */ + #define ETB_ITMISCOP0_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define ETB_ITMISCOP0_FULL_Msk (0x1UL << ETB_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field. */ + + +/* ETB_ITTRFLINACK: Integration Test Trigger In and Flush In Acknowledge Register */ + #define ETB_ITTRFLINACK_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLINACK register. */ + +/* TRIGINACK @Bit 0 : Set the value of triginack. */ + #define ETB_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */ + #define ETB_ITTRFLINACK_TRIGINACK_Msk (0x1UL << ETB_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */ + +/* FLUSHINACK @Bit 1 : Set the value of flushinack. */ + #define ETB_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */ + #define ETB_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << ETB_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */ + + +/* ETB_ITTRFLIN: Integration Test Trigger In and Flush In Register */ + #define ETB_ITTRFLIN_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLIN register. */ + +/* TRIGIN @Bit 0 : Read the value of trigin. */ + #define ETB_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */ + #define ETB_ITTRFLIN_TRIGIN_Msk (0x1UL << ETB_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ + +/* FLUSHIN @Bit 1 : Read the value of flushin. */ + #define ETB_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */ + #define ETB_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETB_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */ + + +/* ETB_ITATBDATA0: Integration Test ATB Data Register 0 */ + #define ETB_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register. */ + +/* ATDATA_0 @Bit 0 : Read the value of atdatas[0]. */ + #define ETB_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */ + #define ETB_ITATBDATA0_ATDATA_0_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */ + +/* ATDATA_7 @Bit 1 : Read the value of atdatas[7]. */ + #define ETB_ITATBDATA0_ATDATA_7_Pos (1UL) /*!< Position of ATDATA_7 field. */ + #define ETB_ITATBDATA0_ATDATA_7_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field. */ + +/* ATDATA_15 @Bit 2 : Read the value of atdatas[15]. */ + #define ETB_ITATBDATA0_ATDATA_15_Pos (2UL) /*!< Position of ATDATA_15 field. */ + #define ETB_ITATBDATA0_ATDATA_15_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field. */ + +/* ATDATA_23 @Bit 3 : Read the value of atdatas[23]. */ + #define ETB_ITATBDATA0_ATDATA_23_Pos (3UL) /*!< Position of ATDATA_23 field. */ + #define ETB_ITATBDATA0_ATDATA_23_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_23_Pos) /*!< Bit mask of ATDATA_23 field. */ + +/* ATDATA_31 @Bit 4 : Read the value of atdatas[31]. */ + #define ETB_ITATBDATA0_ATDATA_31_Pos (4UL) /*!< Position of ATDATA_31 field. */ + #define ETB_ITATBDATA0_ATDATA_31_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_31_Pos) /*!< Bit mask of ATDATA_31 field. */ + + +/* ETB_ITATBCTR2: Integration Test ATB Control Register 2 */ + #define ETB_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register. */ + +/* ATREADYS @Bit 0 : Set the value of atreadys. */ + #define ETB_ITATBCTR2_ATREADYS_Pos (0UL) /*!< Position of ATREADYS field. */ + #define ETB_ITATBCTR2_ATREADYS_Msk (0x1UL << ETB_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */ + +/* AFVALIDS @Bit 1 : Set the value of afvalids. */ + #define ETB_ITATBCTR2_AFVALIDS_Pos (1UL) /*!< Position of AFVALIDS field. */ + #define ETB_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETB_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field. */ + + +/* ETB_ITATBCTR1: Integration Test ATB Control Register 1 */ + #define ETB_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register. */ + +/* ATID @Bits 0..6 : Read the value of atids. */ + #define ETB_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */ + #define ETB_ITATBCTR1_ATID_Msk (0x7FUL << ETB_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */ + + +/* ETB_ITATBCTR0: Integration Test ATB Control Register 0 */ + #define ETB_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALID @Bit 0 : Read the value of atvalids. */ + #define ETB_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ETB_ITATBCTR0_ATVALID_Msk (0x1UL << ETB_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + +/* AFREADY @Bit 1 : Read the value of afreadys. */ + #define ETB_ITATBCTR0_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ + #define ETB_ITATBCTR0_AFREADY_Msk (0x1UL << ETB_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + +/* ATBYTES @Bits 8..9 : Read the value of atbytess. */ + #define ETB_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ + #define ETB_ITATBCTR0_ATBYTES_Msk (0x3UL << ETB_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ + + +/* ETB_ITCTRL: Integration Mode Control Register */ + #define ETB_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* INTEGRATION_MODE @Bit 0 : Allows the component to switch from functional mode to integration mode or back. */ + #define ETB_ITCTRL_INTEGRATION_MODE_Pos (0UL) /*!< Position of INTEGRATION_MODE field. */ + #define ETB_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETB_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field. */ + + +/* ETB_CLAIMSET: Claim Tag Set Register */ + #define ETB_CLAIMSET_ResetValue (0x0000000FUL) /*!< Reset value of CLAIMSET register. */ + +/* CLAIMSET @Bits 0..3 : This claim tag bit is implemented */ + #define ETB_CLAIMSET_CLAIMSET_Pos (0UL) /*!< Position of CLAIMSET field. */ + #define ETB_CLAIMSET_CLAIMSET_Msk (0xFUL << ETB_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field. */ + + +/* ETB_CLAIMCLR: Claim Tag Clear Register */ + #define ETB_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* CLAIMCLR @Bits 0..3 : The value present reflects the current setting of the Claim Tag. */ + #define ETB_CLAIMCLR_CLAIMCLR_Pos (0UL) /*!< Position of CLAIMCLR field. */ + #define ETB_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETB_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field. */ + + +/* ETB_LAR: Lock Access Register */ + #define ETB_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS_W @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than + 0xC5ACCE55 will have the affect of removing write access. */ + + #define ETB_LAR_ACCESS_W_Pos (0UL) /*!< Position of ACCESS_W field. */ + #define ETB_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETB_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field. */ + + +/* ETB_LSR: Lock Status Register */ + #define ETB_LSR_ResetValue (0x00000003UL) /*!< Reset value of LSR register. */ + +/* LOCKEXIST @Bit 0 : Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an + external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */ + + #define ETB_LSR_LOCKEXIST_Pos (0UL) /*!< Position of LOCKEXIST field. */ + #define ETB_LSR_LOCKEXIST_Msk (0x1UL << ETB_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field. */ + +/* LOCKGRANT @Bit 1 : Returns the current status of the Lock. This bit reads as 0 when read from an external debugger + (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */ + + #define ETB_LSR_LOCKGRANT_Pos (1UL) /*!< Position of LOCKGRANT field. */ + #define ETB_LSR_LOCKGRANT_Msk (0x1UL << ETB_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field. */ + +/* LOCKTYPE @Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */ + #define ETB_LSR_LOCKTYPE_Pos (2UL) /*!< Position of LOCKTYPE field. */ + #define ETB_LSR_LOCKTYPE_Msk (0x1UL << ETB_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field. */ + + +/* ETB_AUTHSTATUS: Authentication Status Register */ + #define ETB_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Indicates the security level for non-secure invasive debug */ + #define ETB_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ETB_AUTHSTATUS_NSID_Msk (0x3UL << ETB_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + +/* NSNID @Bits 2..3 : Indicates the security level for non-secure non-invasive debug */ + #define ETB_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ETB_AUTHSTATUS_NSNID_Msk (0x3UL << ETB_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + +/* SID @Bits 4..5 : Indicates the security level for secure invasive debug */ + #define ETB_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ETB_AUTHSTATUS_SID_Msk (0x3UL << ETB_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + +/* SNID @Bits 6..7 : Indicates the security level for secure non-invasive debug */ + #define ETB_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ETB_AUTHSTATUS_SNID_Msk (0x3UL << ETB_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + + +/* ETB_DEVID: Device Configuration Register */ + #define ETB_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register. */ + +/* EXTMUXNUM @Bits 0..4 : When non-zero this value indicates the type/number of ATB multiplexing present on the input to the + ATB. */ + + #define ETB_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */ + #define ETB_DEVID_EXTMUXNUM_Msk (0x1FUL << ETB_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */ + +/* RAMCLK @Bit 5 : This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atclk. */ + #define ETB_DEVID_RAMCLK_Pos (5UL) /*!< Position of RAMCLK field. */ + #define ETB_DEVID_RAMCLK_Msk (0x1UL << ETB_DEVID_RAMCLK_Pos) /*!< Bit mask of RAMCLK field. */ + + +/* ETB_DEVTYPE: Device Type Identifier Register */ + #define ETB_DEVTYPE_ResetValue (0x00000021UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR_TYPE @Bits 0..3 : Major classification grouping for this debug/trace component */ + #define ETB_DEVTYPE_MAJOR_TYPE_Pos (0UL) /*!< Position of MAJOR_TYPE field. */ + #define ETB_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETB_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field. */ + +/* SUB_TYPE @Bits 4..7 : Sub-classification within the major category */ + #define ETB_DEVTYPE_SUB_TYPE_Pos (4UL) /*!< Position of SUB_TYPE field. */ + #define ETB_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETB_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field. */ + + +/* ETB_PERIPHID4: Peripheral ID4 Register */ + #define ETB_PERIPHID4_ResetValue (0x00000004UL) /*!< Reset value of PERIPHID4 register. */ + +/* DES_2 @Bits 0..3 : JEDEC continuation code indicating the designer of the component (along with the identity code) */ + #define ETB_PERIPHID4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ + #define ETB_PERIPHID4_DES_2_Msk (0xFUL << ETB_PERIPHID4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ + +/* SIZE @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component + in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read + as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */ + + #define ETB_PERIPHID4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ + #define ETB_PERIPHID4_SIZE_Msk (0xFUL << ETB_PERIPHID4_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* ETB_PERIPHID0: Peripheral ID0 Register */ + #define ETB_PERIPHID0_ResetValue (0x00000007UL) /*!< Reset value of PERIPHID0 register. */ + +/* PART_0 @Bits 0..7 : Bits [7:0] of the component's part number. This is selected by the designer of the component. */ + #define ETB_PERIPHID0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ + #define ETB_PERIPHID0_PART_0_Msk (0xFFUL << ETB_PERIPHID0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ + + +/* ETB_PERIPHID1: Peripheral ID1 Register */ + #define ETB_PERIPHID1_ResetValue (0x000000B9UL) /*!< Reset value of PERIPHID1 register. */ + +/* PART_1 @Bits 0..3 : Bits [11:8] of the component's part number. This is selected by the designer of the component. */ + #define ETB_PERIPHID1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ + #define ETB_PERIPHID1_PART_1_Msk (0xFUL << ETB_PERIPHID1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ + +/* DES_0 @Bits 4..7 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the continuation + code) */ + + #define ETB_PERIPHID1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ + #define ETB_PERIPHID1_DES_0_Msk (0xFUL << ETB_PERIPHID1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ + + +/* ETB_PERIPHID2: Peripheral ID2 Register */ + #define ETB_PERIPHID2_ResetValue (0x0000004BUL) /*!< Reset value of PERIPHID2 register. */ + +/* DES_1 @Bits 0..2 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the continuation + code) */ + + #define ETB_PERIPHID2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ + #define ETB_PERIPHID2_DES_1_Msk (0x7UL << ETB_PERIPHID2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ + +/* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used */ + #define ETB_PERIPHID2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ + #define ETB_PERIPHID2_JEDEC_Msk (0x1UL << ETB_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ + +/* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This + only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the + exact major/minor revision. */ + + #define ETB_PERIPHID2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ + #define ETB_PERIPHID2_REVISION_Msk (0xFUL << ETB_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field. */ + + +/* ETB_PERIPHID3: Peripheral ID3 Register */ + #define ETB_PERIPHID3_ResetValue (0x00000000UL) /*!< Reset value of PERIPHID3 register. */ + +/* CMOD @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the + component. In most cases this field is zero. */ + + #define ETB_PERIPHID3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ + #define ETB_PERIPHID3_CMOD_Msk (0xFUL << ETB_PERIPHID3_CMOD_Pos) /*!< Bit mask of CMOD field. */ + +/* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after + implementation. In most cases this field is zero. It is recommended that component designers ensure this + field can be changed by a metal fix if required, for example by driving it from registers that reset to + zero. */ + + #define ETB_PERIPHID3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ + #define ETB_PERIPHID3_REVAND_Msk (0xFUL << ETB_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field. */ + + +/* ETB_COMPID0: Component ID0 Register */ + #define ETB_COMPID0_ResetValue (0x0000000DUL) /*!< Reset value of COMPID0 register. */ + +/* PRMBL_0 @Bits 0..7 : Contains bits [7:0] of the component identification */ + #define ETB_COMPID0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ + #define ETB_COMPID0_PRMBL_0_Msk (0xFFUL << ETB_COMPID0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ + + +/* ETB_COMPID1: Component ID1 Register */ + #define ETB_COMPID1_ResetValue (0x00000090UL) /*!< Reset value of COMPID1 register. */ + +/* PRMBL_1 @Bits 0..3 : Contains bits [11:8] of the component identification */ + #define ETB_COMPID1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ + #define ETB_COMPID1_PRMBL_1_Msk (0xFUL << ETB_COMPID1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ + +/* CLASS @Bits 4..7 : Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the + component identification. */ + + #define ETB_COMPID1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ + #define ETB_COMPID1_CLASS_Msk (0xFUL << ETB_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field. */ + + +/* ETB_COMPID2: Component ID2 Register */ + #define ETB_COMPID2_ResetValue (0x00000005UL) /*!< Reset value of COMPID2 register. */ + +/* PRMBL_2 @Bits 0..7 : Contains bits [23:16] of the component identification */ + #define ETB_COMPID2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ + #define ETB_COMPID2_PRMBL_2_Msk (0xFFUL << ETB_COMPID2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ + + +/* ETB_COMPID3: Component ID3 Register */ + #define ETB_COMPID3_ResetValue (0x000000B1UL) /*!< Reset value of COMPID3 register. */ + +/* PRMBL_3 @Bits 0..7 : Contains bits [31:24] of the component identification */ + #define ETB_COMPID3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ + #define ETB_COMPID3_PRMBL_3_Msk (0xFFUL << ETB_COMPID3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ETM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct ETM ======================================================== */ +/** + * @brief Embedded Trace Macrocell + */ + typedef struct { /*!< ETM Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t TRCPRGCTLR; /*!< (@ 0x00000004) Enables the trace unit. */ + __IOM uint32_t TRCPROCSELR; /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes when + the trace unit is enabled or not idle. Before writing + to this register, ensure that TRCSTATR.IDLE == 1 so + that the trace unit can synchronize with the chosen PE. + Implemented if TRCIDR3.NUMPROC is greater than zero.*/ + __IOM uint32_t TRCSTATR; /*!< (@ 0x0000000C) Idle status bit */ + __IOM uint32_t TRCCONFIGR; /*!< (@ 0x00000010) Controls the tracing options This register must always + be programmed as part of trace unit initialization. + Might ignore writes when the trace unit is enabled or + not idle.*/ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t TRCEVENTCTL0R; /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If the + selected event occurs a trace element is generated in + the trace stream according to the settings in + TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.*/ + __IOM uint32_t TRCEVENTCTL1R; /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R + selects. This register must always be programmed as + part of trace unit initialization. Might ignore writes + when the trace unit is enabled or not idle.*/ + __IM uint32_t RESERVED2; + __IOM uint32_t TRCSTALLCTLR; /*!< (@ 0x0000002C) Enables trace unit functionality that prevents trace + unit buffer overflows. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed + if TRCIDR3.STALLCTL == 1.*/ + __IOM uint32_t TRCTSCTLR; /*!< (@ 0x00000030) Controls the insertion of global timestamps in the + trace streams. When the selected event is triggered, + the trace unit inserts a global timestamp into the + trace streams. Might ignore writes when the trace unit + is enabled or not idle. Must be programmed if + TRCCONFIGR.TS == 1.*/ + __IOM uint32_t TRCSYNCPR; /*!< (@ 0x00000034) Controls how often trace synchronization requests + occur. Might ignore writes when the trace unit is + enabled or not idle. If writes are permitted then the + register must be programmed.*/ + __IOM uint32_t TRCCCCTLR; /*!< (@ 0x00000038) Sets the threshold value for cycle counting. Might + ignore writes when the trace unit is enabled or not + idle. Must be programmed if TRCCONFIGR.CCI==1.*/ + __IOM uint32_t TRCBBCTLR; /*!< (@ 0x0000003C) Controls which regions in the memory map are enabled to + use branch broadcasting. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed + if TRCCONFIGR.BB == 1.*/ + __IOM uint32_t TRCTRACEIDR; /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data trace + is enabled then it also sets the trace ID for data + trace, to (trace ID for instruction trace) + 1. This + register must always be programmed as part of trace + unit initialization. Might ignore writes when the trace + unit is enabled or not idle.*/ + __IOM uint32_t TRCQCTLR; /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore + writes when the trace unit is enabled or not idle. This + register must be programmed if it is implemented and + TRCCONFIGR.QE is set to any value other than 0b00.*/ + __IM uint32_t RESERVED3[14]; + __IOM uint32_t TRCVICTLR; /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore + writes when the trace unit is enabled or not idle. Only + returns stable data when TRCSTATR.PMSTABLE == 1. Must + be programmed, particularly to set the value of the + SSSTATUS bit, which sets the state of the start/stop + logic.*/ + __IOM uint32_t TRCVIIECTLR; /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes when the + trace unit is enabled or not idle. This register must + be programmed when one or more address comparators are + implemented.*/ + __IOM uint32_t TRCVISSCTLR; /*!< (@ 0x00000088) Use this to set, or read, the single address + comparators that control the ViewInst start/stop logic. + The start/stop logic is active for an instruction which + causes a start and remains active up to and including + an instruction which causes a stop, and then the + start/stop logic becomes inactive. Might ignore writes + when the trace unit is enabled or not idle. If + implemented then this register must be programmed.*/ + __IOM uint32_t TRCVIPCSSCTLR; /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator inputs + can control the ViewInst start/stop logic. Might ignore + writes when the trace unit is enabled or not idle. If + implemented then this register must be programmed.*/ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t TRCVDCTLR; /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes when + the trace unit is enabled or not idle. This register + must be programmed when data tracing is enabled, that + is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == + 1.*/ + __IOM uint32_t TRCVDSACCTLR; /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore writes + when the trace unit is enabled or not idle. This + register must be programmed when one or more address + comparators are implemented.*/ + __IOM uint32_t TRCVDARCCTLR; /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore writes + when the trace unit is enabled or not idle. This + register must be programmed when one or more address + comparators are implemented.*/ + __IM uint32_t RESERVED5[21]; + __IOM uint32_t TRCSEQEVR[3]; /*!< (@ 0x00000100) Moves the sequencer state according to programmed + events. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all + sequencer state transitions must be programmed with a + valid event.*/ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t TRCSEQRSTEVR; /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed event + occurs. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all + sequencer state transitions must be programmed with a + valid event.*/ + __IOM uint32_t TRCSEQSTR; /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. Might + ignore writes when the trace unit is enabled or not + idle. Only returns stable data when TRCSTATR.PMSTABLE + == 1. When the sequencer is used, all sequencer state + transitions must be programmed with a valid event.*/ + __IOM uint32_t TRCEXTINSELR; /*!< (@ 0x00000120) Use this to set, or read, which external inputs are + resources to the trace unit. Might ignore writes when + the trace unit is enabled or not idle. Only returns + stable data when TRCSTATR.PMSTABLE == 1. When the + sequencer is used, all sequencer state transitions must + be programmed with a valid event.*/ + __IM uint32_t RESERVED7[7]; + __IOM uint32_t TRCCNTRLDVR[4]; /*!< (@ 0x00000140) This sets or returns the reload count value for counter + n. Might ignore writes when the trace unit is enabled + or not idle.*/ + __IOM uint32_t TRCCNTCTLR[4]; /*!< (@ 0x00000150) Controls the operation of counter n. Might ignore + writes when the trace unit is enabled or not idle.*/ + __IOM uint32_t TRCCNTVR[4]; /*!< (@ 0x00000160) This sets or returns the value of counter n. The count + value is only stable when TRCSTATR.PMSTABLE == 1. If + software uses counter n then it must write to this + register to set the initial counter value. Might ignore + writes when the trace unit is enabled or not idle.*/ + __IM uint32_t RESERVED8[36]; + __IOM uint32_t TRCRSCTLR[32]; /*!< (@ 0x00000200) Controls the selection of the resources in the trace + unit. Might ignore writes when the trace unit is + enabled or not idle. If software selects a + non-implemented resource then CONSTRAINED UNPREDICTABLE + behavior of the resource selector occurs, so the + resource selector might fire unexpectedly or might not + fire. Reads of the TRCRSCTLRn might return UNKNOWN.*/ + __IOM uint32_t TRCSSCCR0; /*!< (@ 0x00000280) Controls the single-shot comparator. */ + __IM uint32_t RESERVED9[7]; + __IOM uint32_t TRCSSCSR0; /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators. + TRCSSCSR0 is sensitive toinstruction addresses.*/ + __IM uint32_t RESERVED10[7]; + __IOM uint32_t TRCSSPCICR0; /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot + control.*/ + __IM uint32_t RESERVED11[19]; + __IOM uint32_t TRCPDCR; /*!< (@ 0x00000310) Controls the single-shot comparator. */ + __IOM uint32_t TRCPDSR; /*!< (@ 0x00000314) Indicates the power down status of the ETM. */ + __IM uint32_t RESERVED12[755]; + __IOM uint32_t TRCITATBIDR; /*!< (@ 0x00000EE4) Sets the state of output pins. */ + __IM uint32_t RESERVED13[3]; + __IOM uint32_t TRCITIATBINR; /*!< (@ 0x00000EF4) Reads the state of the input pins. */ + __IM uint32_t RESERVED14; + __IOM uint32_t TRCITIATBOUTR; /*!< (@ 0x00000EFC) Sets the state of the output pins. */ + __IOM uint32_t TRCITCTRL; /*!< (@ 0x00000F00) Enables topology detection or integration testing, by + putting ETM-M33 into integration mode.*/ + __IM uint32_t RESERVED15[39]; + __IOM uint32_t TRCCLAIMSET; /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the number of + claim tag bits implemented.*/ + __IOM uint32_t TRCCLAIMCLR; /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the current + value of the claim tag.*/ + __IM uint32_t RESERVED16[4]; + __IOM uint32_t TRCAUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t TRCDEVARCH; /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 + component*/ + __IM uint32_t RESERVED17[3]; + __IM uint32_t TRCDEVTYPE; /*!< (@ 0x00000FCC) Controls the single-shot comparator. */ + __IOM uint32_t TRCPIDR[8]; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IOM uint32_t TRCCIDR[4]; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + } NRF_ETM_Type; /*!< Size = 4096 (0x1000) */ + +/* ETM_TRCPRGCTLR: Enables the trace unit. */ + #define ETM_TRCPRGCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCPRGCTLR register. */ + +/* EN @Bit 0 : Trace unit enable bit */ + #define ETM_TRCPRGCTLR_EN_Pos (0UL) /*!< Position of EN field. */ + #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field. */ + #define ETM_TRCPRGCTLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ETM_TRCPRGCTLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no + trace is generated.*/ + #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ + + +/* ETM_TRCPROCSELR: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing + to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. + Implemented if TRCIDR3.NUMPROC is greater than zero. */ + + #define ETM_TRCPROCSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCPROCSELR register. */ + +/* PROCSEL @Bits 0..4 : PE select bits that select the PE to trace. */ + #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL) /*!< Position of PROCSEL field. */ + #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field. */ + + +/* ETM_TRCSTATR: Idle status bit */ + #define ETM_TRCSTATR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTATR register. */ + +/* IDLE @Bit 0 : Trace unit enable bit */ + #define ETM_TRCSTATR_IDLE_Pos (0UL) /*!< Position of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ + #define ETM_TRCSTATR_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ + #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL) /*!< The trace unit is not idle. */ + #define ETM_TRCSTATR_IDLE_Idle (0x1UL) /*!< The trace unit is idle. */ + +/* PMSTABLE @Bit 1 : Programmers' model stable bit */ + #define ETM_TRCSTATR_PMSTABLE_Pos (1UL) /*!< Position of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Min (0x0UL) /*!< Min enumerator value of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_Max (0x1UL) /*!< Max enumerator value of PMSTABLE field. */ + #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL) /*!< The programmers' model is not stable. */ + #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL) /*!< The programmers' model is stable. */ + + +/* ETM_TRCCONFIGR: Controls the tracing options This register must always be programmed as part of trace unit initialization. + Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCCONFIGR_ResetValue (0x00000000UL) /*!< Reset value of TRCCONFIGR register. */ + +/* LOADASP0INST @Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. + */ + + #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL) /*!< Position of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Min (0x0UL) /*!< Min enumerator value of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Max (0x1UL) /*!< Max enumerator value of LOADASP0INST field. */ + #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL) /*!< Do not trace load instructions as P0 instructions. */ + #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL) /*!< Trace load instructions as P0 instructions. */ + +/* STOREASP0INST @Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL) /*!< Position of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Min (0x0UL) /*!< Min enumerator value of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Max (0x1UL) /*!< Max enumerator value of STOREASP0INST field. */ + #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL) /*!< Do not trace store instructions as P0 instructions. */ + #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL) /*!< Trace store instructions as P0 instructions. */ + +/* BB @Bit 3 : Branch broadcast mode bit. */ + #define ETM_TRCCONFIGR_BB_Pos (3UL) /*!< Position of BB field. */ + #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field. */ + #define ETM_TRCCONFIGR_BB_Min (0x0UL) /*!< Min enumerator value of BB field. */ + #define ETM_TRCCONFIGR_BB_Max (0x1UL) /*!< Max enumerator value of BB field. */ + #define ETM_TRCCONFIGR_BB_Disabled (0x0UL) /*!< Branch broadcast mode is disabled. */ + #define ETM_TRCCONFIGR_BB_Enabled (0x1UL) /*!< Branch broadcast mode is enabled. */ + +/* CCI @Bit 4 : Cycle counting instruction trace bit. */ + #define ETM_TRCCONFIGR_CCI_Pos (4UL) /*!< Position of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Min (0x0UL) /*!< Min enumerator value of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Max (0x1UL) /*!< Max enumerator value of CCI field. */ + #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL) /*!< Cycle counting in the instruction trace is disabled. */ + #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL) /*!< Cycle counting in the instruction trace is enabled. */ + +/* CID @Bit 6 : Context ID tracing bit. */ + #define ETM_TRCCONFIGR_CID_Pos (6UL) /*!< Position of CID field. */ + #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field. */ + #define ETM_TRCCONFIGR_CID_Min (0x0UL) /*!< Min enumerator value of CID field. */ + #define ETM_TRCCONFIGR_CID_Max (0x1UL) /*!< Max enumerator value of CID field. */ + #define ETM_TRCCONFIGR_CID_Disabled (0x0UL) /*!< Context ID tracing is disabled. */ + #define ETM_TRCCONFIGR_CID_Enabled (0x1UL) /*!< Context ID tracing is enabled. */ + +/* VMID @Bit 7 : Virtual context identifier tracing bit. */ + #define ETM_TRCCONFIGR_VMID_Pos (7UL) /*!< Position of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Min (0x0UL) /*!< Min enumerator value of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Max (0x1UL) /*!< Max enumerator value of VMID field. */ + #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL) /*!< Virtual context identifier tracing is disabled. */ + #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL) /*!< Virtual context identifier tracing is enabled. */ + +/* COND @Bits 8..10 : Conditional instruction tracing bit. */ + #define ETM_TRCCONFIGR_COND_Pos (8UL) /*!< Position of COND field. */ + #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field. */ + #define ETM_TRCCONFIGR_COND_Min (0x0UL) /*!< Min enumerator value of COND field. */ + #define ETM_TRCCONFIGR_COND_Max (0x7UL) /*!< Max enumerator value of COND field. */ + #define ETM_TRCCONFIGR_COND_Disabled (0x0UL) /*!< Conditional instruction tracing is disabled. */ + #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL) /*!< Conditional load instructions are traced. */ + #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL) /*!< Conditional store instructions are traced. */ + #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL) /*!< Conditional load and store instructions are traced. */ + #define ETM_TRCCONFIGR_COND_All (0x7UL) /*!< All conditional instructions are traced. */ + +/* TS @Bit 11 : Global timestamp tracing bit. */ + #define ETM_TRCCONFIGR_TS_Pos (11UL) /*!< Position of TS field. */ + #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field. */ + #define ETM_TRCCONFIGR_TS_Min (0x0UL) /*!< Min enumerator value of TS field. */ + #define ETM_TRCCONFIGR_TS_Max (0x1UL) /*!< Max enumerator value of TS field. */ + #define ETM_TRCCONFIGR_TS_Disabled (0x0UL) /*!< Global timestamp tracing is disabled. */ + #define ETM_TRCCONFIGR_TS_Enabled (0x1UL) /*!< Global timestamp tracing is enabled. */ + +/* RS @Bit 12 : Return stack enable bit. */ + #define ETM_TRCCONFIGR_RS_Pos (12UL) /*!< Position of RS field. */ + #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field. */ + #define ETM_TRCCONFIGR_RS_Min (0x0UL) /*!< Min enumerator value of RS field. */ + #define ETM_TRCCONFIGR_RS_Max (0x1UL) /*!< Max enumerator value of RS field. */ + #define ETM_TRCCONFIGR_RS_Disabled (0x0UL) /*!< Return stack is disabled. */ + #define ETM_TRCCONFIGR_RS_Enabled (0x1UL) /*!< Return stack is enabled. */ + +/* QE @Bits 13..14 : Q element enable field. */ + #define ETM_TRCCONFIGR_QE_Pos (13UL) /*!< Position of QE field. */ + #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field. */ + #define ETM_TRCCONFIGR_QE_Min (0x0UL) /*!< Min enumerator value of QE field. */ + #define ETM_TRCCONFIGR_QE_Max (0x3UL) /*!< Max enumerator value of QE field. */ + #define ETM_TRCCONFIGR_QE_Disabled (0x0UL) /*!< Q elements are disabled. */ + #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements + without instruction counts are disabled.*/ + #define ETM_TRCCONFIGR_QE_Enabled (0x3UL) /*!< Q elements with and without instruction counts are enabled. */ + +/* VMIDOPT @Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace + generation and in the Virtual context identifier comparators. */ + + #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL) /*!< Position of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Min (0x0UL) /*!< Min enumerator value of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_Max (0x1UL) /*!< Max enumerator value of VMIDOPT field. */ + #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL) /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context + identifier larger than the VTTBR_EL2.VMID, the upper unused bits are + always zero. If the trace unit supports a Virtual context identifier + larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit + Virtual context identifier, bits [15:8] of the trace unit Virtual + context identifier are always zero.*/ + #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used. */ + +/* DA @Bit 16 : Data address tracing bit. */ + #define ETM_TRCCONFIGR_DA_Pos (16UL) /*!< Position of DA field. */ + #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field. */ + #define ETM_TRCCONFIGR_DA_Min (0x0UL) /*!< Min enumerator value of DA field. */ + #define ETM_TRCCONFIGR_DA_Max (0x1UL) /*!< Max enumerator value of DA field. */ + #define ETM_TRCCONFIGR_DA_Disabled (0x0UL) /*!< Data address tracing is disabled. */ + #define ETM_TRCCONFIGR_DA_Enabled (0x1UL) /*!< Data address tracing is enabled. */ + +/* DV @Bit 17 : Data value tracing bit. */ + #define ETM_TRCCONFIGR_DV_Pos (17UL) /*!< Position of DV field. */ + #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field. */ + #define ETM_TRCCONFIGR_DV_Min (0x0UL) /*!< Min enumerator value of DV field. */ + #define ETM_TRCCONFIGR_DV_Max (0x1UL) /*!< Max enumerator value of DV field. */ + #define ETM_TRCCONFIGR_DV_Disabled (0x0UL) /*!< Data value tracing is disabled. */ + #define ETM_TRCCONFIGR_DV_Enabled (0x1UL) /*!< Data value tracing is enabled. */ + + +/* ETM_TRCEVENTCTL0R: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the + trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */ + + #define ETM_TRCEVENTCTL0R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL0R register. */ + +/* EVENT @Bits 0..7 : Select which event should generate trace elements. */ + #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCEVENTCTL0R_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCEVENTCTL1R: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as + part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCEVENTCTL1R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL1R register. */ + +/* INSTEN0 @Bit 0 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Pos (0UL) /*!< Position of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN0_Pos) /*!< Bit mask of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Min (0x0UL) /*!< Min enumerator value of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Max (0x1UL) /*!< Max enumerator value of INSTEN0 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN0_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 0, in the + instruction trace stream.*/ + +/* INSTEN1 @Bit 1 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Pos (1UL) /*!< Position of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN1_Pos) /*!< Bit mask of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Min (0x0UL) /*!< Min enumerator value of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Max (0x1UL) /*!< Max enumerator value of INSTEN1 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN1_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 1, in the + instruction trace stream.*/ + +/* INSTEN2 @Bit 2 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Pos (2UL) /*!< Position of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN2_Pos) /*!< Bit mask of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Min (0x0UL) /*!< Min enumerator value of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Max (0x1UL) /*!< Max enumerator value of INSTEN2 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN2_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 2, in the + instruction trace stream.*/ + +/* INSTEN3 @Bit 3 : Instruction event enable field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Pos (3UL) /*!< Position of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN3_Pos) /*!< Bit mask of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Min (0x0UL) /*!< Min enumerator value of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Max (0x1UL) /*!< Max enumerator value of INSTEN3 field. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ + #define ETM_TRCEVENTCTL1R_INSTEN3_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 3, in the + instruction trace stream.*/ + +/* DATAEN @Bit 4 : Data event enable bit. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL) /*!< Position of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Min (0x0UL) /*!< Min enumerator value of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Max (0x1UL) /*!< Max enumerator value of DATAEN field. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL) /*!< The trace unit does not generate an Event element if event 0 occurs. */ + #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL) /*!< The trace unit generates an Event element in the data trace stream if + event 0 occurs.*/ + +/* ATB @Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */ + #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL) /*!< Position of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Min (0x0UL) /*!< Min enumerator value of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Max (0x1UL) /*!< Max enumerator value of ATB field. */ + #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL) /*!< ATB trigger is disabled. */ + #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL) /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented + then when event 0 occurs the trace unit generates an ATB event.*/ + +/* LPOVERRIDE @Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL) /*!< Position of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Min (0x0UL) /*!< Min enumerator value of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Max (0x1UL) /*!< Max enumerator value of LPOVERRIDE field. */ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the + trace unit is enabled to enter low-power state.*/ + #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to + a low-power state does not affect the trace unit resources or trace + generation.*/ + + +/* ETM_TRCSTALLCTLR: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */ + + #define ETM_TRCSTALLCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTALLCTLR register. */ + +/* LEVEL @Bits 0..3 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global + timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction + trace stream, although the cumulative cycle count remains correct. */ + + #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */ + #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field. */ + #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL) /*!< Zero invasion. This setting has a greater risk of a FIFO overflow */ + #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL) /*!< Maximum invasion occurs but there is less risk of a FIFO overflow. */ + +/* ISTALL @Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is + less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL) /*!< Position of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Min (0x0UL) /*!< Min enumerator value of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Max (0x1UL) /*!< Max enumerator value of ISTALL field. */ + #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ + #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ + +/* DSTALL @Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than + LEVEL. */ + + #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL) /*!< Position of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Min (0x0UL) /*!< Min enumerator value of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Max (0x1UL) /*!< Max enumerator value of DSTALL field. */ + #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ + #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ + +/* INSTPRIORITY @Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the + instruction trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL) /*!< Position of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Min (0x0UL) /*!< Min enumerator value of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Max (0x1UL) /*!< Max enumerator value of INSTPRIORITY field. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace. */ + #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might + prioritize instruction trace by preventing output of data trace, or + other means which ensure that the instruction trace has a higher + priority than the data trace.*/ + +/* DATADISCARDLOAD @Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the + data trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD + field.*/ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Min (0x0UL) /*!< Min enumerator value of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Max (0x1UL) /*!< Max enumerator value of DATADISCARDLOAD field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ + #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with + data loads.*/ + +/* DATADISCARDSTORE @Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the + data trace buffer space is less than LEVEL. */ + + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of + DATADISCARDSTORE field.*/ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Min (0x0UL) /*!< Min enumerator value of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Max (0x1UL) /*!< Max enumerator value of DATADISCARDSTORE field. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ + #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with + data stores.*/ + +/* NOOVERFLOW @Bit 13 : Trace overflow prevention bit. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL) /*!< Position of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Min (0x0UL) /*!< Min enumerator value of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Max (0x1UL) /*!< Max enumerator value of NOOVERFLOW field. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled. */ + #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant + performance impact.*/ + + +/* ETM_TRCTSCTLR: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the + trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is + enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */ + + #define ETM_TRCTSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCTSCTLR register. */ + +/* EVENT @Bits 0..7 : Select which event should generate time stamps. */ + #define ETM_TRCTSCTLR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCTSCTLR_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCSYNCPR: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or + not idle. If writes are permitted then the register must be programmed. */ + + #define ETM_TRCSYNCPR_ResetValue (0x00000000UL) /*!< Reset value of TRCSYNCPR register. */ + +/* PERIOD @Bits 0..4 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before + a trace synchronization request occurs. The number of bytes is always a power of two, calculated by + 2^PERIOD */ + + #define ETM_TRCSYNCPR_PERIOD_Pos (0UL) /*!< Position of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Min (0x00UL) /*!< Min value of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Max (0x1FUL) /*!< Max size of PERIOD field. */ + #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL) /*!< Trace synchronization requests are disabled. This setting does not + disable other types of trace synchronization request.*/ + + +/* ETM_TRCCCCTLR: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. + Must be programmed if TRCCONFIGR.CCI==1. */ + + #define ETM_TRCCCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCCCTLR register. */ + +/* THRESHOLD @Bits 0..11 : Sets the threshold value for instruction trace cycle counting. */ + #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL) /*!< Position of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Min (0x000UL) /*!< Min value of THRESHOLD field. */ + #define ETM_TRCCCCTLR_THRESHOLD_Max (0x7FFUL) /*!< Max size of THRESHOLD field. */ + + +/* ETM_TRCBBCTLR: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the + trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */ + + #define ETM_TRCBBCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCBBCTLR register. */ + +/* RANGE0 @Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[0] controls the selection of address range + comparator pair 0. */ + + #define ETM_TRCBBCTLR_RANGE0_Pos (0UL) /*!< Position of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Min (0x0UL) /*!< Min enumerator value of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Max (0x1UL) /*!< Max enumerator value of RANGE0 field. */ + #define ETM_TRCBBCTLR_RANGE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE0_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE1 @Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[1] controls the selection of address range + comparator pair 1. */ + + #define ETM_TRCBBCTLR_RANGE1_Pos (1UL) /*!< Position of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Min (0x0UL) /*!< Min enumerator value of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Max (0x1UL) /*!< Max enumerator value of RANGE1 field. */ + #define ETM_TRCBBCTLR_RANGE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE1_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE2 @Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[2] controls the selection of address range + comparator pair 2. */ + + #define ETM_TRCBBCTLR_RANGE2_Pos (2UL) /*!< Position of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Min (0x0UL) /*!< Min enumerator value of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Max (0x1UL) /*!< Max enumerator value of RANGE2 field. */ + #define ETM_TRCBBCTLR_RANGE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE2_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE3 @Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[3] controls the selection of address range + comparator pair 3. */ + + #define ETM_TRCBBCTLR_RANGE3_Pos (3UL) /*!< Position of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Min (0x0UL) /*!< Min enumerator value of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Max (0x1UL) /*!< Max enumerator value of RANGE3 field. */ + #define ETM_TRCBBCTLR_RANGE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE3_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE4 @Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[4] controls the selection of address range + comparator pair 4. */ + + #define ETM_TRCBBCTLR_RANGE4_Pos (4UL) /*!< Position of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Min (0x0UL) /*!< Min enumerator value of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Max (0x1UL) /*!< Max enumerator value of RANGE4 field. */ + #define ETM_TRCBBCTLR_RANGE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE4_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE5 @Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[5] controls the selection of address range + comparator pair 5. */ + + #define ETM_TRCBBCTLR_RANGE5_Pos (5UL) /*!< Position of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Min (0x0UL) /*!< Min enumerator value of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Max (0x1UL) /*!< Max enumerator value of RANGE5 field. */ + #define ETM_TRCBBCTLR_RANGE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE5_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE6 @Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[6] controls the selection of address range + comparator pair 6. */ + + #define ETM_TRCBBCTLR_RANGE6_Pos (6UL) /*!< Position of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Min (0x0UL) /*!< Min enumerator value of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Max (0x1UL) /*!< Max enumerator value of RANGE6 field. */ + #define ETM_TRCBBCTLR_RANGE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE6_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + +/* RANGE7 @Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each + field represents an address range comparator pair, so field[7] controls the selection of address range + comparator pair 7. */ + + #define ETM_TRCBBCTLR_RANGE7_Pos (7UL) /*!< Position of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Min (0x0UL) /*!< Min enumerator value of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Max (0x1UL) /*!< Max enumerator value of RANGE7 field. */ + #define ETM_TRCBBCTLR_RANGE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected.*/ + #define ETM_TRCBBCTLR_RANGE7_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is + selected.*/ + + +/* ETM_TRCTRACEIDR: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data + trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace + unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCTRACEIDR_ResetValue (0x00000000UL) /*!< Reset value of TRCTRACEIDR register. */ + +/* TRACEID @Bits 0..6 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is + enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */ + + #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL) /*!< Position of TRACEID field. */ + #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field. */ + + +/* ETM_TRCQCTLR: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */ + + #define ETM_TRCQCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCQCTLR register. */ + +/* RANGE0 @Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE0_Pos (0UL) /*!< Position of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Msk (0x1UL << ETM_TRCQCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Min (0x0UL) /*!< Min enumerator value of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Max (0x1UL) /*!< Max enumerator value of RANGE0 field. */ + #define ETM_TRCQCTLR_RANGE0_Disabled (0x0UL) /*!< Address range comparator 0 is disabled. */ + #define ETM_TRCQCTLR_RANGE0_Enabled (0x1UL) /*!< Address range comparator 0 is selected for use. */ + +/* RANGE1 @Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE1_Pos (1UL) /*!< Position of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Msk (0x1UL << ETM_TRCQCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Min (0x0UL) /*!< Min enumerator value of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Max (0x1UL) /*!< Max enumerator value of RANGE1 field. */ + #define ETM_TRCQCTLR_RANGE1_Disabled (0x0UL) /*!< Address range comparator 1 is disabled. */ + #define ETM_TRCQCTLR_RANGE1_Enabled (0x1UL) /*!< Address range comparator 1 is selected for use. */ + +/* RANGE2 @Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE2_Pos (2UL) /*!< Position of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Msk (0x1UL << ETM_TRCQCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Min (0x0UL) /*!< Min enumerator value of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Max (0x1UL) /*!< Max enumerator value of RANGE2 field. */ + #define ETM_TRCQCTLR_RANGE2_Disabled (0x0UL) /*!< Address range comparator 2 is disabled. */ + #define ETM_TRCQCTLR_RANGE2_Enabled (0x1UL) /*!< Address range comparator 2 is selected for use. */ + +/* RANGE3 @Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE3_Pos (3UL) /*!< Position of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Msk (0x1UL << ETM_TRCQCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Min (0x0UL) /*!< Min enumerator value of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Max (0x1UL) /*!< Max enumerator value of RANGE3 field. */ + #define ETM_TRCQCTLR_RANGE3_Disabled (0x0UL) /*!< Address range comparator 3 is disabled. */ + #define ETM_TRCQCTLR_RANGE3_Enabled (0x1UL) /*!< Address range comparator 3 is selected for use. */ + +/* RANGE4 @Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE4_Pos (4UL) /*!< Position of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Msk (0x1UL << ETM_TRCQCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Min (0x0UL) /*!< Min enumerator value of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Max (0x1UL) /*!< Max enumerator value of RANGE4 field. */ + #define ETM_TRCQCTLR_RANGE4_Disabled (0x0UL) /*!< Address range comparator 4 is disabled. */ + #define ETM_TRCQCTLR_RANGE4_Enabled (0x1UL) /*!< Address range comparator 4 is selected for use. */ + +/* RANGE5 @Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE5_Pos (5UL) /*!< Position of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Msk (0x1UL << ETM_TRCQCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Min (0x0UL) /*!< Min enumerator value of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Max (0x1UL) /*!< Max enumerator value of RANGE5 field. */ + #define ETM_TRCQCTLR_RANGE5_Disabled (0x0UL) /*!< Address range comparator 5 is disabled. */ + #define ETM_TRCQCTLR_RANGE5_Enabled (0x1UL) /*!< Address range comparator 5 is selected for use. */ + +/* RANGE6 @Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE6_Pos (6UL) /*!< Position of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Msk (0x1UL << ETM_TRCQCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Min (0x0UL) /*!< Min enumerator value of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Max (0x1UL) /*!< Max enumerator value of RANGE6 field. */ + #define ETM_TRCQCTLR_RANGE6_Disabled (0x0UL) /*!< Address range comparator 6 is disabled. */ + #define ETM_TRCQCTLR_RANGE6_Enabled (0x1UL) /*!< Address range comparator 6 is selected for use. */ + +/* RANGE7 @Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */ + #define ETM_TRCQCTLR_RANGE7_Pos (7UL) /*!< Position of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Msk (0x1UL << ETM_TRCQCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Min (0x0UL) /*!< Min enumerator value of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Max (0x1UL) /*!< Max enumerator value of RANGE7 field. */ + #define ETM_TRCQCTLR_RANGE7_Disabled (0x0UL) /*!< Address range comparator 7 is disabled. */ + #define ETM_TRCQCTLR_RANGE7_Enabled (0x1UL) /*!< Address range comparator 7 is selected for use. */ + +/* MODE @Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate address ranges where the + trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to + generate Q elements: */ + + #define ETM_TRCQCTLR_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field. */ + #define ETM_TRCQCTLR_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define ETM_TRCQCTLR_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define ETM_TRCQCTLR_MODE_Exclude (0x0UL) /*!< Exclude mode. The address range comparators selected by the RANGE + field indicate address ranges where the trace unit cannot generate Q + elements. If no ranges are selected, Q elements are permitted across + the entire memory map.*/ + #define ETM_TRCQCTLR_MODE_Include (0x1UL) /*!< Include mode. The address range comparators selected by the RANGE + field indicate address ranges where the trace unit can generate Q + elements. If all the implemented bits in RANGE are set to 0 then Q + elements are disabled.*/ + + +/* ETM_TRCVICTLR: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only + returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the + SSSTATUS bit, which sets the state of the start/stop logic. */ + + #define ETM_TRCVICTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVICTLR register. */ + +/* EVENT_SEL @Bits 0..4 : Select which resource number should be filtered. */ + #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL) /*!< Position of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Min (0x0UL) /*!< Min enumerator value of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Max (0x1UL) /*!< Max enumerator value of EVENT_SEL field. */ + #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL) /*!< This event is not filtered. */ + #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL) /*!< This event is filtered. */ + +/* SSSTATUS @Bit 9 : When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. */ + #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL) /*!< Position of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Min (0x0UL) /*!< Min enumerator value of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Max (0x1UL) /*!< Max enumerator value of SSSTATUS field. */ + #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL) /*!< The start/stop logic is in the stopped state. */ + #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL) /*!< The start/stop logic is in the started state. */ + +/* TRCRESET @Bit 10 : Controls whether a trace unit must trace a Reset exception. */ + #define ETM_TRCVICTLR_TRCRESET_Pos (10UL) /*!< Position of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Min (0x0UL) /*!< Min enumerator value of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Max (0x1UL) /*!< Max enumerator value of TRCRESET field. */ + #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL) /*!< The trace unit does not trace a Reset exception unless it traces the + exception or instruction immediately prior to the Reset exception.*/ + #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL) /*!< The trace unit always traces a Reset exception. */ + +/* TRCERR @Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */ + #define ETM_TRCVICTLR_TRCERR_Pos (11UL) /*!< Position of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Min (0x0UL) /*!< Min enumerator value of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Max (0x1UL) /*!< Max enumerator value of TRCERR field. */ + #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL) /*!< The trace unit does not trace a System error exception unless it + traces the exception or instruction immediately prior to the System + error exception.*/ + #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL) /*!< The trace unit always traces a System error exception, regardless of + the value of ViewInst.*/ + +/* EXLEVEL0_S @Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 0. */ + + #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL) /*!< Position of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL0_S field. */ + #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 0.*/ + #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 0.*/ + +/* EXLEVEL1_S @Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 1. */ + + #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL) /*!< Position of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL1_S field. */ + #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 1.*/ + #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 1.*/ + +/* EXLEVEL2_S @Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 2. */ + + #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL) /*!< Position of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL2_S field. */ + #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 2.*/ + #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 2.*/ + +/* EXLEVEL3_S @Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 3. */ + + #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL) /*!< Position of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Min (0x0UL) /*!< Min enumerator value of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Max (0x1UL) /*!< Max enumerator value of EXLEVEL3_S field. */ + #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, + for Exception level 3.*/ + #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for + Exception level 3.*/ + +/* EXLEVEL0_NS @Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 0. */ + + #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL) /*!< Position of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL0_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 0.*/ + #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 0.*/ + +/* EXLEVEL1_NS @Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 1. */ + + #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL) /*!< Position of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL1_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 1.*/ + #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 1.*/ + +/* EXLEVEL2_NS @Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 2. */ + + #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL) /*!< Position of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL2_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 2.*/ + #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 2.*/ + +/* EXLEVEL3_NS @Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding + Exception level 3. */ + + #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL) /*!< Position of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Min (0x0UL) /*!< Min enumerator value of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Max (0x1UL) /*!< Max enumerator value of EXLEVEL3_NS field. */ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure + state, for Exception level 3.*/ + #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for + Exception level 3.*/ + + +/* ETM_TRCVIIECTLR: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must + be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVIIECTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIIECTLR register. */ + +/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVIIECTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVIIECTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVIIECTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVIIECTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVIIECTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVIIECTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVIIECTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is + selected for ViewInst include control.*/ + +/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. + */ + + #define ETM_TRCVIIECTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVIIECTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected for ViewInst include control.*/ + #define ETM_TRCVIIECTLR_INCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is + selected for ViewInst include control.*/ + +/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is + selected for ViewInst exclude control.*/ + +/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude + control. */ + + #define ETM_TRCVIIECTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVIIECTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not + selected for ViewInst exclude control.*/ + #define ETM_TRCVIIECTLR_EXCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is + selected for ViewInst exclude control.*/ + + +/* ETM_TRCVISSCTLR: Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The + start/stop logic is active for an instruction which causes a start and remains active up to and including + an instruction which causes a stop, and then the start/stop logic becomes inactive. Might ignore writes + when the trace unit is enabled or not idle. If implemented then this register must be programmed. */ + + #define ETM_TRCVISSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVISSCTLR register. */ + +/* START0 @Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START0_Pos (0UL) /*!< Position of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Msk (0x1UL << ETM_TRCVISSCTLR_START0_Pos) /*!< Bit mask of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Min (0x0UL) /*!< Min enumerator value of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Max (0x1UL) /*!< Max enumerator value of START0 field. */ + #define ETM_TRCVISSCTLR_START0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a start resource. */ + +/* START1 @Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START1_Pos (1UL) /*!< Position of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Msk (0x1UL << ETM_TRCVISSCTLR_START1_Pos) /*!< Bit mask of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Min (0x0UL) /*!< Min enumerator value of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Max (0x1UL) /*!< Max enumerator value of START1 field. */ + #define ETM_TRCVISSCTLR_START1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a start resource. */ + +/* START2 @Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START2_Pos (2UL) /*!< Position of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Msk (0x1UL << ETM_TRCVISSCTLR_START2_Pos) /*!< Bit mask of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Min (0x0UL) /*!< Min enumerator value of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Max (0x1UL) /*!< Max enumerator value of START2 field. */ + #define ETM_TRCVISSCTLR_START2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a start resource. */ + +/* START3 @Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START3_Pos (3UL) /*!< Position of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Msk (0x1UL << ETM_TRCVISSCTLR_START3_Pos) /*!< Bit mask of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Min (0x0UL) /*!< Min enumerator value of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Max (0x1UL) /*!< Max enumerator value of START3 field. */ + #define ETM_TRCVISSCTLR_START3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a start resource. */ + +/* START4 @Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START4_Pos (4UL) /*!< Position of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Msk (0x1UL << ETM_TRCVISSCTLR_START4_Pos) /*!< Bit mask of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Min (0x0UL) /*!< Min enumerator value of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Max (0x1UL) /*!< Max enumerator value of START4 field. */ + #define ETM_TRCVISSCTLR_START4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a start resource. */ + +/* START5 @Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START5_Pos (5UL) /*!< Position of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Msk (0x1UL << ETM_TRCVISSCTLR_START5_Pos) /*!< Bit mask of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Min (0x0UL) /*!< Min enumerator value of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Max (0x1UL) /*!< Max enumerator value of START5 field. */ + #define ETM_TRCVISSCTLR_START5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a start resource. */ + +/* START6 @Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START6_Pos (6UL) /*!< Position of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Msk (0x1UL << ETM_TRCVISSCTLR_START6_Pos) /*!< Bit mask of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Min (0x0UL) /*!< Min enumerator value of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Max (0x1UL) /*!< Max enumerator value of START6 field. */ + #define ETM_TRCVISSCTLR_START6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a start resource. */ + +/* START7 @Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + starting trace. */ + + #define ETM_TRCVISSCTLR_START7_Pos (7UL) /*!< Position of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Msk (0x1UL << ETM_TRCVISSCTLR_START7_Pos) /*!< Bit mask of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Min (0x0UL) /*!< Min enumerator value of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Max (0x1UL) /*!< Max enumerator value of START7 field. */ + #define ETM_TRCVISSCTLR_START7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a start resource.*/ + #define ETM_TRCVISSCTLR_START7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a start resource. */ + +/* STOP0 @Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP0_Pos (16UL) /*!< Position of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Min (0x0UL) /*!< Min enumerator value of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Max (0x1UL) /*!< Max enumerator value of STOP0 field. */ + #define ETM_TRCVISSCTLR_STOP0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a stop resource. */ + +/* STOP1 @Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP1_Pos (17UL) /*!< Position of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Min (0x0UL) /*!< Min enumerator value of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Max (0x1UL) /*!< Max enumerator value of STOP1 field. */ + #define ETM_TRCVISSCTLR_STOP1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a stop resource. */ + +/* STOP2 @Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP2_Pos (18UL) /*!< Position of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Min (0x0UL) /*!< Min enumerator value of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Max (0x1UL) /*!< Max enumerator value of STOP2 field. */ + #define ETM_TRCVISSCTLR_STOP2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a stop resource. */ + +/* STOP3 @Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP3_Pos (19UL) /*!< Position of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Min (0x0UL) /*!< Min enumerator value of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Max (0x1UL) /*!< Max enumerator value of STOP3 field. */ + #define ETM_TRCVISSCTLR_STOP3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a stop resource. */ + +/* STOP4 @Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP4_Pos (20UL) /*!< Position of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Min (0x0UL) /*!< Min enumerator value of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Max (0x1UL) /*!< Max enumerator value of STOP4 field. */ + #define ETM_TRCVISSCTLR_STOP4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a stop resource. */ + +/* STOP5 @Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP5_Pos (21UL) /*!< Position of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Min (0x0UL) /*!< Min enumerator value of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Max (0x1UL) /*!< Max enumerator value of STOP5 field. */ + #define ETM_TRCVISSCTLR_STOP5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a stop resource. */ + +/* STOP6 @Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP6_Pos (22UL) /*!< Position of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Min (0x0UL) /*!< Min enumerator value of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Max (0x1UL) /*!< Max enumerator value of STOP6 field. */ + #define ETM_TRCVISSCTLR_STOP6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a stop resource. */ + +/* STOP7 @Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of + stopping trace */ + + #define ETM_TRCVISSCTLR_STOP7_Pos (23UL) /*!< Position of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Min (0x0UL) /*!< Min enumerator value of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Max (0x1UL) /*!< Max enumerator value of STOP7 field. */ + #define ETM_TRCVISSCTLR_STOP7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a stop resource. */ + #define ETM_TRCVISSCTLR_STOP7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a stop resource. */ + + +/* ETM_TRCVIPCSSCTLR: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might + ignore writes when the trace unit is enabled or not idle. If implemented then this register must be + programmed. */ + + #define ETM_TRCVIPCSSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIPCSSCTLR register. */ + +/* START0 @Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START0_Pos (0UL) /*!< Position of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START0_Pos) /*!< Bit mask of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Min (0x0UL) /*!< Min enumerator value of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Max (0x1UL) /*!< Max enumerator value of START0 field. */ + #define ETM_TRCVIPCSSCTLR_START0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a start resource. */ + +/* START1 @Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START1_Pos (1UL) /*!< Position of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START1_Pos) /*!< Bit mask of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Min (0x0UL) /*!< Min enumerator value of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Max (0x1UL) /*!< Max enumerator value of START1 field. */ + #define ETM_TRCVIPCSSCTLR_START1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a start resource. */ + +/* START2 @Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START2_Pos (2UL) /*!< Position of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START2_Pos) /*!< Bit mask of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Min (0x0UL) /*!< Min enumerator value of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Max (0x1UL) /*!< Max enumerator value of START2 field. */ + #define ETM_TRCVIPCSSCTLR_START2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a start resource. */ + +/* START3 @Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START3_Pos (3UL) /*!< Position of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START3_Pos) /*!< Bit mask of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Min (0x0UL) /*!< Min enumerator value of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Max (0x1UL) /*!< Max enumerator value of START3 field. */ + #define ETM_TRCVIPCSSCTLR_START3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a start resource. */ + +/* START4 @Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START4_Pos (4UL) /*!< Position of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START4_Pos) /*!< Bit mask of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Min (0x0UL) /*!< Min enumerator value of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Max (0x1UL) /*!< Max enumerator value of START4 field. */ + #define ETM_TRCVIPCSSCTLR_START4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a start resource. */ + +/* START5 @Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START5_Pos (5UL) /*!< Position of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START5_Pos) /*!< Bit mask of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Min (0x0UL) /*!< Min enumerator value of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Max (0x1UL) /*!< Max enumerator value of START5 field. */ + #define ETM_TRCVIPCSSCTLR_START5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a start resource. */ + +/* START6 @Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START6_Pos (6UL) /*!< Position of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START6_Pos) /*!< Bit mask of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Min (0x0UL) /*!< Min enumerator value of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Max (0x1UL) /*!< Max enumerator value of START6 field. */ + #define ETM_TRCVIPCSSCTLR_START6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a start resource. */ + +/* START7 @Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting + trace */ + + #define ETM_TRCVIPCSSCTLR_START7_Pos (7UL) /*!< Position of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START7_Pos) /*!< Bit mask of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Min (0x0UL) /*!< Min enumerator value of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Max (0x1UL) /*!< Max enumerator value of START7 field. */ + #define ETM_TRCVIPCSSCTLR_START7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a start + resource.*/ + #define ETM_TRCVIPCSSCTLR_START7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a start resource. */ + +/* STOP0 @Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP0_Pos (16UL) /*!< Position of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Min (0x0UL) /*!< Min enumerator value of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Max (0x1UL) /*!< Max enumerator value of STOP0 field. */ + #define ETM_TRCVIPCSSCTLR_STOP0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a stop resource. */ + +/* STOP1 @Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP1_Pos (17UL) /*!< Position of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Min (0x0UL) /*!< Min enumerator value of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Max (0x1UL) /*!< Max enumerator value of STOP1 field. */ + #define ETM_TRCVIPCSSCTLR_STOP1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a stop resource. */ + +/* STOP2 @Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP2_Pos (18UL) /*!< Position of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Min (0x0UL) /*!< Min enumerator value of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Max (0x1UL) /*!< Max enumerator value of STOP2 field. */ + #define ETM_TRCVIPCSSCTLR_STOP2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a stop resource. */ + +/* STOP3 @Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP3_Pos (19UL) /*!< Position of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Min (0x0UL) /*!< Min enumerator value of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Max (0x1UL) /*!< Max enumerator value of STOP3 field. */ + #define ETM_TRCVIPCSSCTLR_STOP3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a stop resource. */ + +/* STOP4 @Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP4_Pos (20UL) /*!< Position of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Min (0x0UL) /*!< Min enumerator value of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Max (0x1UL) /*!< Max enumerator value of STOP4 field. */ + #define ETM_TRCVIPCSSCTLR_STOP4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a stop resource. */ + +/* STOP5 @Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP5_Pos (21UL) /*!< Position of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Min (0x0UL) /*!< Min enumerator value of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Max (0x1UL) /*!< Max enumerator value of STOP5 field. */ + #define ETM_TRCVIPCSSCTLR_STOP5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a stop resource. */ + +/* STOP6 @Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP6_Pos (22UL) /*!< Position of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Min (0x0UL) /*!< Min enumerator value of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Max (0x1UL) /*!< Max enumerator value of STOP6 field. */ + #define ETM_TRCVIPCSSCTLR_STOP6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a stop resource. */ + +/* STOP7 @Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping + trace. */ + + #define ETM_TRCVIPCSSCTLR_STOP7_Pos (23UL) /*!< Position of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Min (0x0UL) /*!< Min enumerator value of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Max (0x1UL) /*!< Max enumerator value of STOP7 field. */ + #define ETM_TRCVIPCSSCTLR_STOP7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a stop resource.*/ + #define ETM_TRCVIPCSSCTLR_STOP7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a stop resource. */ + + +/* ETM_TRCVDCTLR: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register + must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == + 1. */ + + #define ETM_TRCVDCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDCTLR register. */ + +/* EVENT0 @Bit 0 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT0_Pos (0UL) /*!< Position of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT0_Pos) /*!< Bit mask of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Min (0x0UL) /*!< Min enumerator value of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Max (0x1UL) /*!< Max enumerator value of EVENT0 field. */ + #define ETM_TRCVDCTLR_EVENT0_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT0_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT1 @Bit 1 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT1_Pos (1UL) /*!< Position of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Min (0x0UL) /*!< Min enumerator value of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Max (0x1UL) /*!< Max enumerator value of EVENT1 field. */ + #define ETM_TRCVDCTLR_EVENT1_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT1_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT2 @Bit 2 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT2_Pos (2UL) /*!< Position of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT2_Pos) /*!< Bit mask of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Min (0x0UL) /*!< Min enumerator value of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Max (0x1UL) /*!< Max enumerator value of EVENT2 field. */ + #define ETM_TRCVDCTLR_EVENT2_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT2_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT3 @Bit 3 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT3_Pos (3UL) /*!< Position of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT3_Pos) /*!< Bit mask of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Min (0x0UL) /*!< Min enumerator value of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Max (0x1UL) /*!< Max enumerator value of EVENT3 field. */ + #define ETM_TRCVDCTLR_EVENT3_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT3_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT4 @Bit 4 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT4_Pos (4UL) /*!< Position of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT4_Pos) /*!< Bit mask of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Min (0x0UL) /*!< Min enumerator value of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Max (0x1UL) /*!< Max enumerator value of EVENT4 field. */ + #define ETM_TRCVDCTLR_EVENT4_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT4_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT5 @Bit 5 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT5_Pos (5UL) /*!< Position of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT5_Pos) /*!< Bit mask of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Min (0x0UL) /*!< Min enumerator value of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Max (0x1UL) /*!< Max enumerator value of EVENT5 field. */ + #define ETM_TRCVDCTLR_EVENT5_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT5_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT6 @Bit 6 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT6_Pos (6UL) /*!< Position of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT6_Pos) /*!< Bit mask of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Min (0x0UL) /*!< Min enumerator value of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Max (0x1UL) /*!< Max enumerator value of EVENT6 field. */ + #define ETM_TRCVDCTLR_EVENT6_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT6_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* EVENT7 @Bit 7 : Event unit enable bit. */ + #define ETM_TRCVDCTLR_EVENT7_Pos (7UL) /*!< Position of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT7_Pos) /*!< Bit mask of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Min (0x0UL) /*!< Min enumerator value of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Max (0x1UL) /*!< Max enumerator value of EVENT7 field. */ + #define ETM_TRCVDCTLR_EVENT7_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ + #define ETM_TRCVDCTLR_EVENT7_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ + +/* SPREL @Bits 8..9 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */ + #define ETM_TRCVDCTLR_SPREL_Pos (8UL) /*!< Position of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Min (0x0UL) /*!< Min enumerator value of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Max (0x3UL) /*!< Max enumerator value of SPREL field. */ + #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of SP-relative transfers. */ + #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL) /*!< The trace unit does not trace the address portion of SP-relative + transfers. If data value tracing is enabled then the trace unit + generates a P1 data address element.*/ + #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL) /*!< The trace unit does not trace the address or value portions of + SP-relative transfers.*/ + +/* PCREL @Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */ + #define ETM_TRCVDCTLR_PCREL_Pos (10UL) /*!< Position of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Min (0x0UL) /*!< Min enumerator value of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Max (0x1UL) /*!< Max enumerator value of PCREL field. */ + #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of PC-relative transfers. */ + #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL) /*!< The trace unit does not trace the address or value portions of + PC-relative transfers.*/ + +/* TBI @Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */ + #define ETM_TRCVDCTLR_TBI_Pos (11UL) /*!< Position of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Min (0x0UL) /*!< Min enumerator value of TBI field. */ + #define ETM_TRCVDCTLR_TBI_Max (0x1UL) /*!< Max enumerator value of TBI field. */ + #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL) /*!< The trace unit assigns bits[63:56] to have the same value as bit[55] + of the data address, that is, it sign-extends the value.*/ + #define ETM_TRCVDCTLR_TBI_Copy (0x1UL) /*!< The trace unit assigns bits[63:56] to have the same value as + bits[63:56] of the data address.*/ + +/* TRCEXDATA @Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and + Armv8-M PEs. */ + + #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL) /*!< Position of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Min (0x0UL) /*!< Min enumerator value of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Max (0x1UL) /*!< Max enumerator value of TRCEXDATA field. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL) /*!< Exception and exception return data transfers are not traced. */ + #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL) /*!< Exception and exception return data transfers are traced if the other + aspects of ViewData indicate that the data transfers must be traced.*/ + + +/* ETM_TRCVDSACCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVDSACCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDSACCTLR register. */ + +/* INCLUDE0 @Bit 0 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE0_Enabled (0x1UL) /*!< The single address comparator 0, is selected for ViewData include + control.*/ + +/* INCLUDE1 @Bit 1 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE1_Enabled (0x1UL) /*!< The single address comparator 1, is selected for ViewData include + control.*/ + +/* INCLUDE2 @Bit 2 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE2_Enabled (0x1UL) /*!< The single address comparator 2, is selected for ViewData include + control.*/ + +/* INCLUDE3 @Bit 3 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE3_Enabled (0x1UL) /*!< The single address comparator 3, is selected for ViewData include + control.*/ + +/* INCLUDE4 @Bit 4 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE4_Enabled (0x1UL) /*!< The single address comparator 4, is selected for ViewData include + control.*/ + +/* INCLUDE5 @Bit 5 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE5_Enabled (0x1UL) /*!< The single address comparator 5, is selected for ViewData include + control.*/ + +/* INCLUDE6 @Bit 6 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE6_Enabled (0x1UL) /*!< The single address comparator 6, is selected for ViewData include + control.*/ + +/* INCLUDE7 @Bit 7 : Selects which single address comparators are in use with ViewData include control. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_INCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include + control.*/ + #define ETM_TRCVDSACCTLR_INCLUDE7_Enabled (0x1UL) /*!< The single address comparator 7, is selected for ViewData include + control.*/ + +/* EXCLUDE0 @Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE0_Enabled (0x1UL) /*!< The single address comparator 0, s selected for ViewData exclude + control.*/ + +/* EXCLUDE1 @Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE1_Enabled (0x1UL) /*!< The single address comparator 1, s selected for ViewData exclude + control.*/ + +/* EXCLUDE2 @Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE2_Enabled (0x1UL) /*!< The single address comparator 2, s selected for ViewData exclude + control.*/ + +/* EXCLUDE3 @Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE3_Enabled (0x1UL) /*!< The single address comparator 3, s selected for ViewData exclude + control.*/ + +/* EXCLUDE4 @Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE4_Enabled (0x1UL) /*!< The single address comparator 4, s selected for ViewData exclude + control.*/ + +/* EXCLUDE5 @Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE5_Enabled (0x1UL) /*!< The single address comparator 5, s selected for ViewData exclude + control.*/ + +/* EXCLUDE6 @Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE6_Enabled (0x1UL) /*!< The single address comparator 6, s selected for ViewData exclude + control.*/ + +/* EXCLUDE7 @Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude + control.*/ + #define ETM_TRCVDSACCTLR_EXCLUDE7_Enabled (0x1UL) /*!< The single address comparator 7, s selected for ViewData exclude + control.*/ + + +/* ETM_TRCVDARCCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This + register must be programmed when one or more address comparators are implemented. */ + + #define ETM_TRCVDARCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDARCCTLR register. */ + +/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE0_Pos (0UL) /*!< Position of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Min (0x0UL) /*!< Min enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Max (0x1UL) /*!< Max enumerator value of INCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, is selected + for ViewData include control.*/ + +/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE1_Pos (1UL) /*!< Position of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Min (0x0UL) /*!< Min enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Max (0x1UL) /*!< Max enumerator value of INCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, is selected + for ViewData include control.*/ + +/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE2_Pos (2UL) /*!< Position of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Min (0x0UL) /*!< Min enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Max (0x1UL) /*!< Max enumerator value of INCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, is selected + for ViewData include control.*/ + +/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE3_Pos (3UL) /*!< Position of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Min (0x0UL) /*!< Min enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Max (0x1UL) /*!< Max enumerator value of INCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, is selected + for ViewData include control.*/ + +/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE4_Pos (4UL) /*!< Position of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Min (0x0UL) /*!< Min enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Max (0x1UL) /*!< Max enumerator value of INCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, is selected + for ViewData include control.*/ + +/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE5_Pos (5UL) /*!< Position of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Min (0x0UL) /*!< Min enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Max (0x1UL) /*!< Max enumerator value of INCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, is selected + for ViewData include control.*/ + +/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE6_Pos (6UL) /*!< Position of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Min (0x0UL) /*!< Min enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Max (0x1UL) /*!< Max enumerator value of INCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, is selected + for ViewData include control.*/ + +/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. + */ + + #define ETM_TRCVDARCCTLR_INCLUDE7_Pos (7UL) /*!< Position of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Min (0x0UL) /*!< Min enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Max (0x1UL) /*!< Max enumerator value of INCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not + selected for ViewData include control.*/ + #define ETM_TRCVDARCCTLR_INCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, is selected + for ViewData include control.*/ + +/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE0_Pos (16UL) /*!< Position of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Min (0x0UL) /*!< Min enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Max (0x1UL) /*!< Max enumerator value of EXCLUDE0 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE1_Pos (17UL) /*!< Position of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Min (0x0UL) /*!< Min enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Max (0x1UL) /*!< Max enumerator value of EXCLUDE1 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE2_Pos (18UL) /*!< Position of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Min (0x0UL) /*!< Min enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Max (0x1UL) /*!< Max enumerator value of EXCLUDE2 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE3_Pos (19UL) /*!< Position of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Min (0x0UL) /*!< Min enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Max (0x1UL) /*!< Max enumerator value of EXCLUDE3 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE4_Pos (20UL) /*!< Position of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Min (0x0UL) /*!< Min enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Max (0x1UL) /*!< Max enumerator value of EXCLUDE4 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE5_Pos (21UL) /*!< Position of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Min (0x0UL) /*!< Min enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Max (0x1UL) /*!< Max enumerator value of EXCLUDE5 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE6_Pos (22UL) /*!< Position of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Min (0x0UL) /*!< Min enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Max (0x1UL) /*!< Max enumerator value of EXCLUDE6 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, s selected + for ViewData exclude control.*/ + +/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude + control. */ + + #define ETM_TRCVDARCCTLR_EXCLUDE7_Pos (23UL) /*!< Position of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Min (0x0UL) /*!< Min enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Max (0x1UL) /*!< Max enumerator value of EXCLUDE7 field. */ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not + selected for ViewData exclude control.*/ + #define ETM_TRCVDARCCTLR_EXCLUDE7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, s selected + for ViewData exclude control.*/ + + +/* ETM_TRCSEQEVR: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled + or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid + event. */ + + #define ETM_TRCSEQEVR_MaxCount (3UL) /*!< Max size of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_MaxIndex (2UL) /*!< Max index of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_MinIndex (0UL) /*!< Min index of TRCSEQEVR[3] array. */ + #define ETM_TRCSEQEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQEVR[3] register. */ + +/* F0 @Bit 0 : Forward field. */ + #define ETM_TRCSEQEVR_F0_Pos (0UL) /*!< Position of F0 field. */ + #define ETM_TRCSEQEVR_F0_Msk (0x1UL << ETM_TRCSEQEVR_F0_Pos) /*!< Bit mask of F0 field. */ + #define ETM_TRCSEQEVR_F0_Min (0x0UL) /*!< Min enumerator value of F0 field. */ + #define ETM_TRCSEQEVR_F0_Max (0x1UL) /*!< Max enumerator value of F0 field. */ + #define ETM_TRCSEQEVR_F0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F1 @Bit 1 : Forward field. */ + #define ETM_TRCSEQEVR_F1_Pos (1UL) /*!< Position of F1 field. */ + #define ETM_TRCSEQEVR_F1_Msk (0x1UL << ETM_TRCSEQEVR_F1_Pos) /*!< Bit mask of F1 field. */ + #define ETM_TRCSEQEVR_F1_Min (0x0UL) /*!< Min enumerator value of F1 field. */ + #define ETM_TRCSEQEVR_F1_Max (0x1UL) /*!< Max enumerator value of F1 field. */ + #define ETM_TRCSEQEVR_F1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F2 @Bit 2 : Forward field. */ + #define ETM_TRCSEQEVR_F2_Pos (2UL) /*!< Position of F2 field. */ + #define ETM_TRCSEQEVR_F2_Msk (0x1UL << ETM_TRCSEQEVR_F2_Pos) /*!< Bit mask of F2 field. */ + #define ETM_TRCSEQEVR_F2_Min (0x0UL) /*!< Min enumerator value of F2 field. */ + #define ETM_TRCSEQEVR_F2_Max (0x1UL) /*!< Max enumerator value of F2 field. */ + #define ETM_TRCSEQEVR_F2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F3 @Bit 3 : Forward field. */ + #define ETM_TRCSEQEVR_F3_Pos (3UL) /*!< Position of F3 field. */ + #define ETM_TRCSEQEVR_F3_Msk (0x1UL << ETM_TRCSEQEVR_F3_Pos) /*!< Bit mask of F3 field. */ + #define ETM_TRCSEQEVR_F3_Min (0x0UL) /*!< Min enumerator value of F3 field. */ + #define ETM_TRCSEQEVR_F3_Max (0x1UL) /*!< Max enumerator value of F3 field. */ + #define ETM_TRCSEQEVR_F3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F4 @Bit 4 : Forward field. */ + #define ETM_TRCSEQEVR_F4_Pos (4UL) /*!< Position of F4 field. */ + #define ETM_TRCSEQEVR_F4_Msk (0x1UL << ETM_TRCSEQEVR_F4_Pos) /*!< Bit mask of F4 field. */ + #define ETM_TRCSEQEVR_F4_Min (0x0UL) /*!< Min enumerator value of F4 field. */ + #define ETM_TRCSEQEVR_F4_Max (0x1UL) /*!< Max enumerator value of F4 field. */ + #define ETM_TRCSEQEVR_F4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F5 @Bit 5 : Forward field. */ + #define ETM_TRCSEQEVR_F5_Pos (5UL) /*!< Position of F5 field. */ + #define ETM_TRCSEQEVR_F5_Msk (0x1UL << ETM_TRCSEQEVR_F5_Pos) /*!< Bit mask of F5 field. */ + #define ETM_TRCSEQEVR_F5_Min (0x0UL) /*!< Min enumerator value of F5 field. */ + #define ETM_TRCSEQEVR_F5_Max (0x1UL) /*!< Max enumerator value of F5 field. */ + #define ETM_TRCSEQEVR_F5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F6 @Bit 6 : Forward field. */ + #define ETM_TRCSEQEVR_F6_Pos (6UL) /*!< Position of F6 field. */ + #define ETM_TRCSEQEVR_F6_Msk (0x1UL << ETM_TRCSEQEVR_F6_Pos) /*!< Bit mask of F6 field. */ + #define ETM_TRCSEQEVR_F6_Min (0x0UL) /*!< Min enumerator value of F6 field. */ + #define ETM_TRCSEQEVR_F6_Max (0x1UL) /*!< Max enumerator value of F6 field. */ + #define ETM_TRCSEQEVR_F6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* F7 @Bit 7 : Forward field. */ + #define ETM_TRCSEQEVR_F7_Pos (7UL) /*!< Position of F7 field. */ + #define ETM_TRCSEQEVR_F7_Msk (0x1UL << ETM_TRCSEQEVR_F7_Pos) /*!< Bit mask of F7 field. */ + #define ETM_TRCSEQEVR_F7_Min (0x0UL) /*!< Min enumerator value of F7 field. */ + #define ETM_TRCSEQEVR_F7_Max (0x1UL) /*!< Max enumerator value of F7 field. */ + #define ETM_TRCSEQEVR_F7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_F7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to + state n+1.*/ + +/* B0 @Bit 8 : Backward field. */ + #define ETM_TRCSEQEVR_B0_Pos (8UL) /*!< Position of B0 field. */ + #define ETM_TRCSEQEVR_B0_Msk (0x1UL << ETM_TRCSEQEVR_B0_Pos) /*!< Bit mask of B0 field. */ + #define ETM_TRCSEQEVR_B0_Min (0x0UL) /*!< Min enumerator value of B0 field. */ + #define ETM_TRCSEQEVR_B0_Max (0x1UL) /*!< Max enumerator value of B0 field. */ + #define ETM_TRCSEQEVR_B0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B1 @Bit 9 : Backward field. */ + #define ETM_TRCSEQEVR_B1_Pos (9UL) /*!< Position of B1 field. */ + #define ETM_TRCSEQEVR_B1_Msk (0x1UL << ETM_TRCSEQEVR_B1_Pos) /*!< Bit mask of B1 field. */ + #define ETM_TRCSEQEVR_B1_Min (0x0UL) /*!< Min enumerator value of B1 field. */ + #define ETM_TRCSEQEVR_B1_Max (0x1UL) /*!< Max enumerator value of B1 field. */ + #define ETM_TRCSEQEVR_B1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B2 @Bit 10 : Backward field. */ + #define ETM_TRCSEQEVR_B2_Pos (10UL) /*!< Position of B2 field. */ + #define ETM_TRCSEQEVR_B2_Msk (0x1UL << ETM_TRCSEQEVR_B2_Pos) /*!< Bit mask of B2 field. */ + #define ETM_TRCSEQEVR_B2_Min (0x0UL) /*!< Min enumerator value of B2 field. */ + #define ETM_TRCSEQEVR_B2_Max (0x1UL) /*!< Max enumerator value of B2 field. */ + #define ETM_TRCSEQEVR_B2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B3 @Bit 11 : Backward field. */ + #define ETM_TRCSEQEVR_B3_Pos (11UL) /*!< Position of B3 field. */ + #define ETM_TRCSEQEVR_B3_Msk (0x1UL << ETM_TRCSEQEVR_B3_Pos) /*!< Bit mask of B3 field. */ + #define ETM_TRCSEQEVR_B3_Min (0x0UL) /*!< Min enumerator value of B3 field. */ + #define ETM_TRCSEQEVR_B3_Max (0x1UL) /*!< Max enumerator value of B3 field. */ + #define ETM_TRCSEQEVR_B3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B4 @Bit 12 : Backward field. */ + #define ETM_TRCSEQEVR_B4_Pos (12UL) /*!< Position of B4 field. */ + #define ETM_TRCSEQEVR_B4_Msk (0x1UL << ETM_TRCSEQEVR_B4_Pos) /*!< Bit mask of B4 field. */ + #define ETM_TRCSEQEVR_B4_Min (0x0UL) /*!< Min enumerator value of B4 field. */ + #define ETM_TRCSEQEVR_B4_Max (0x1UL) /*!< Max enumerator value of B4 field. */ + #define ETM_TRCSEQEVR_B4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B5 @Bit 13 : Backward field. */ + #define ETM_TRCSEQEVR_B5_Pos (13UL) /*!< Position of B5 field. */ + #define ETM_TRCSEQEVR_B5_Msk (0x1UL << ETM_TRCSEQEVR_B5_Pos) /*!< Bit mask of B5 field. */ + #define ETM_TRCSEQEVR_B5_Min (0x0UL) /*!< Min enumerator value of B5 field. */ + #define ETM_TRCSEQEVR_B5_Max (0x1UL) /*!< Max enumerator value of B5 field. */ + #define ETM_TRCSEQEVR_B5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B6 @Bit 14 : Backward field. */ + #define ETM_TRCSEQEVR_B6_Pos (14UL) /*!< Position of B6 field. */ + #define ETM_TRCSEQEVR_B6_Msk (0x1UL << ETM_TRCSEQEVR_B6_Pos) /*!< Bit mask of B6 field. */ + #define ETM_TRCSEQEVR_B6_Min (0x0UL) /*!< Min enumerator value of B6 field. */ + #define ETM_TRCSEQEVR_B6_Max (0x1UL) /*!< Max enumerator value of B6 field. */ + #define ETM_TRCSEQEVR_B6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + +/* B7 @Bit 15 : Backward field. */ + #define ETM_TRCSEQEVR_B7_Pos (15UL) /*!< Position of B7 field. */ + #define ETM_TRCSEQEVR_B7_Msk (0x1UL << ETM_TRCSEQEVR_B7_Pos) /*!< Bit mask of B7 field. */ + #define ETM_TRCSEQEVR_B7_Min (0x0UL) /*!< Min enumerator value of B7 field. */ + #define ETM_TRCSEQEVR_B7_Max (0x1UL) /*!< Max enumerator value of B7 field. */ + #define ETM_TRCSEQEVR_B7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ + #define ETM_TRCSEQEVR_B7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to + state n.*/ + + +/* ETM_TRCSEQRSTEVR: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is + enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a + valid event. */ + + #define ETM_TRCSEQRSTEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQRSTEVR register. */ + +/* EVENT @Bits 0..7 : Select which event should reset the sequencer. */ + #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Min (0x00UL) /*!< Min value of EVENT field. */ + #define ETM_TRCSEQRSTEVR_EVENT_Max (0xFFUL) /*!< Max size of EVENT field. */ + + +/* ETM_TRCSEQSTR: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. + Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state + transitions must be programmed with a valid event. */ + + #define ETM_TRCSEQSTR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQSTR register. */ + +/* STATE @Bits 0..1 : Sets or returns the state of the sequencer. */ + #define ETM_TRCSEQSTR_STATE_Pos (0UL) /*!< Position of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define ETM_TRCSEQSTR_STATE_Max (0x3UL) /*!< Max enumerator value of STATE field. */ + #define ETM_TRCSEQSTR_STATE_State0 (0x0UL) /*!< The sequencer is in state 0. */ + #define ETM_TRCSEQSTR_STATE_State1 (0x1UL) /*!< The sequencer is in state 1. */ + #define ETM_TRCSEQSTR_STATE_State2 (0x2UL) /*!< The sequencer is in state 2. */ + #define ETM_TRCSEQSTR_STATE_State3 (0x3UL) /*!< The sequencer is in state 3. */ + + +/* ETM_TRCEXTINSELR: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when + the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the + sequencer is used, all sequencer state transitions must be programmed with a valid event. */ + + #define ETM_TRCEXTINSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCEXTINSELR register. */ + +/* SEL0 @Bits 0..7 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL0_Pos (0UL) /*!< Position of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL0_Pos) /*!< Bit mask of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Min (0x00UL) /*!< Min value of SEL0 field. */ + #define ETM_TRCEXTINSELR_SEL0_Max (0xFFUL) /*!< Max size of SEL0 field. */ + +/* SEL1 @Bits 8..15 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL1_Pos (8UL) /*!< Position of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL1_Pos) /*!< Bit mask of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Min (0x00UL) /*!< Min value of SEL1 field. */ + #define ETM_TRCEXTINSELR_SEL1_Max (0xFFUL) /*!< Max size of SEL1 field. */ + +/* SEL2 @Bits 16..23 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL2_Pos (16UL) /*!< Position of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL2_Pos) /*!< Bit mask of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Min (0x00UL) /*!< Min value of SEL2 field. */ + #define ETM_TRCEXTINSELR_SEL2_Max (0xFFUL) /*!< Max size of SEL2 field. */ + +/* SEL3 @Bits 24..31 : Each field in this collection selects an external input as a resource for the trace unit. */ + #define ETM_TRCEXTINSELR_SEL3_Pos (24UL) /*!< Position of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL3_Pos) /*!< Bit mask of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Min (0x00UL) /*!< Min value of SEL3 field. */ + #define ETM_TRCEXTINSELR_SEL3_Max (0xFFUL) /*!< Max size of SEL3 field. */ + + +/* ETM_TRCCNTRLDVR: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is + enabled or not idle. */ + + #define ETM_TRCCNTRLDVR_MaxCount (4UL) /*!< Max size of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_MaxIndex (3UL) /*!< Max index of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_MinIndex (0UL) /*!< Min index of TRCCNTRLDVR[4] array. */ + #define ETM_TRCCNTRLDVR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTRLDVR[4] register. */ + +/* VALUE @Bits 0..15 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit + copies the VALUEn field into counter n. */ + + #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Min (0x0000UL) /*!< Min value of VALUE field. */ + #define ETM_TRCCNTRLDVR_VALUE_Max (0xFFFFUL) /*!< Max size of VALUE field. */ + + +/* ETM_TRCCNTCTLR: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */ + #define ETM_TRCCNTCTLR_MaxCount (4UL) /*!< Max size of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_MaxIndex (3UL) /*!< Max index of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_MinIndex (0UL) /*!< Min index of TRCCNTCTLR[4] array. */ + #define ETM_TRCCNTCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTCTLR[4] register. */ + +/* CNTEVENT @Bits 0..7 : Selects an event, that when it occurs causes counter n to decrement. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL) /*!< Position of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Min (0x00UL) /*!< Min value of CNTEVENT field. */ + #define ETM_TRCCNTCTLR_CNTEVENT_Max (0xFFUL) /*!< Max size of CNTEVENT field. */ + +/* RLDEVENT @Bits 8..15 : Selects an event, that when it occurs causes a reload event for counter n. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL) /*!< Position of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Min (0x00UL) /*!< Min value of RLDEVENT field. */ + #define ETM_TRCCNTCTLR_RLDEVENT_Max (0xFFUL) /*!< Max size of RLDEVENT field. */ + +/* RLDSELF @Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */ + #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL) /*!< Position of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Min (0x0UL) /*!< Min enumerator value of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Max (0x1UL) /*!< Max enumerator value of RLDSELF field. */ + #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL) /*!< The counter is in Normal mode. */ + #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL) /*!< The counter is in Self-reload mode. */ + +/* CNTCHAIN @Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs + for counter n-1. */ + + #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL) /*!< Position of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Min (0x0UL) /*!< Min enumerator value of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Max (0x1UL) /*!< Max enumerator value of CNTCHAIN field. */ + #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL) /*!< Counter n does not decrement when a reload event for counter n-1 + occurs.*/ + #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL) /*!< Counter n decrements when a reload event for counter n-1 occurs. This + concatenates counter n and counter n-1, to provide a larger count + value.*/ + + +/* ETM_TRCCNTVR: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If + software uses counter n then it must write to this register to set the initial counter value. Might ignore + writes when the trace unit is enabled or not idle. */ + + #define ETM_TRCCNTVR_MaxCount (4UL) /*!< Max size of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_MaxIndex (3UL) /*!< Max index of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_MinIndex (0UL) /*!< Min index of TRCCNTVR[4] array. */ + #define ETM_TRCCNTVR_ResetValue (0x00000000UL) /*!< Reset value of TRCCNTVR[4] register. */ + +/* VALUE @Bits 0..15 : Contains the count value of counter n. */ + #define ETM_TRCCNTVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Min (0x0000UL) /*!< Min value of VALUE field. */ + #define ETM_TRCCNTVR_VALUE_Max (0xFFFFUL) /*!< Max size of VALUE field. */ + + +/* ETM_TRCRSCTLR: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled + or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the + resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the + TRCRSCTLRn might return UNKNOWN. */ + + #define ETM_TRCRSCTLR_MaxCount (30UL) /*!< Max size of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_MaxIndex (31UL) /*!< Max index of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_MinIndex (2UL) /*!< Min index of TRCRSCTLR[32] array. */ + #define ETM_TRCRSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCRSCTLR[32] register. */ + +/* EN @Bit 0 : Trace unit enable bit */ + #define ETM_TRCRSCTLR_EN_Pos (0UL) /*!< Position of EN field. */ + #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field. */ + #define ETM_TRCRSCTLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define ETM_TRCRSCTLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define ETM_TRCRSCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no + trace is generated.*/ + #define ETM_TRCRSCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ + + +/* ETM_TRCSSCCR0: Controls the single-shot comparator. */ + #define ETM_TRCSSCCR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSCCR0 register. */ + +/* RST @Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to + be detected */ + + #define ETM_TRCSSCCR0_RST_Pos (24UL) /*!< Position of RST field. */ + #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field. */ + #define ETM_TRCSSCCR0_RST_Min (0x0UL) /*!< Min enumerator value of RST field. */ + #define ETM_TRCSSCCR0_RST_Max (0x1UL) /*!< Max enumerator value of RST field. */ + #define ETM_TRCSSCCR0_RST_Disabled (0x0UL) /*!< Multiple matches can not be detected. */ + #define ETM_TRCSSCCR0_RST_Enabled (0x1UL) /*!< Multiple matches can occur. */ + + +/* ETM_TRCSSCSR0: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */ + #define ETM_TRCSSCSR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSCSR0 register. */ + +/* INST @Bit 0 : Instruction address comparator support */ + #define ETM_TRCSSCSR0_INST_Pos (0UL) /*!< Position of INST field. */ + #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field. */ + #define ETM_TRCSSCSR0_INST_Min (0x0UL) /*!< Min enumerator value of INST field. */ + #define ETM_TRCSSCSR0_INST_Max (0x1UL) /*!< Max enumerator value of INST field. */ + #define ETM_TRCSSCSR0_INST_False (0x0UL) /*!< Single-shot instruction address comparisons not supported. */ + #define ETM_TRCSSCSR0_INST_True (0x1UL) /*!< Single-shot instruction address comparisons supported. */ + +/* DA @Bit 1 : Data address comparator support */ + #define ETM_TRCSSCSR0_DA_Pos (1UL) /*!< Position of DA field. */ + #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field. */ + #define ETM_TRCSSCSR0_DA_Min (0x0UL) /*!< Min enumerator value of DA field. */ + #define ETM_TRCSSCSR0_DA_Max (0x1UL) /*!< Max enumerator value of DA field. */ + #define ETM_TRCSSCSR0_DA_False (0x0UL) /*!< Data address comparisons not supported. */ + #define ETM_TRCSSCSR0_DA_True (0x1UL) /*!< Data address comparisons supported. */ + +/* DV @Bit 2 : Data value comparator support */ + #define ETM_TRCSSCSR0_DV_Pos (2UL) /*!< Position of DV field. */ + #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field. */ + #define ETM_TRCSSCSR0_DV_Min (0x0UL) /*!< Min enumerator value of DV field. */ + #define ETM_TRCSSCSR0_DV_Max (0x1UL) /*!< Max enumerator value of DV field. */ + #define ETM_TRCSSCSR0_DV_False (0x0UL) /*!< Data value comparisons not supported. */ + #define ETM_TRCSSCSR0_DV_True (0x1UL) /*!< Data value comparisons supported. */ + +/* PC @Bit 3 : Process counter value comparator support */ + #define ETM_TRCSSCSR0_PC_Pos (3UL) /*!< Position of PC field. */ + #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field. */ + #define ETM_TRCSSCSR0_PC_Min (0x0UL) /*!< Min enumerator value of PC field. */ + #define ETM_TRCSSCSR0_PC_Max (0x1UL) /*!< Max enumerator value of PC field. */ + #define ETM_TRCSSCSR0_PC_False (0x0UL) /*!< Process counter value comparisons not supported. */ + #define ETM_TRCSSCSR0_PC_True (0x1UL) /*!< Process counter value comparisons supported. */ + +/* STATUS @Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */ + #define ETM_TRCSSCSR0_STATUS_Pos (31UL) /*!< Position of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL) /*!< Match has not occurred. */ + #define ETM_TRCSSCSR0_STATUS_Match (0x1UL) /*!< Match has occurred at least once. */ + + +/* ETM_TRCSSPCICR0: Selects the processor comparator inputs for Single-shot control. */ + #define ETM_TRCSSPCICR0_ResetValue (0x00000000UL) /*!< Reset value of TRCSSPCICR0 register. */ + +/* PC0 @Bit 0 : Selects processor comparator 0 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC0_Pos (0UL) /*!< Position of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Msk (0x1UL << ETM_TRCSSPCICR0_PC0_Pos) /*!< Bit mask of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Min (0x0UL) /*!< Min enumerator value of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Max (0x1UL) /*!< Max enumerator value of PC0 field. */ + #define ETM_TRCSSPCICR0_PC0_Disabled (0x0UL) /*!< Processor comparator 0 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC0_Enabled (0x1UL) /*!< Processor comparator 0 is selected for Single-shot control. */ + +/* PC1 @Bit 1 : Selects processor comparator 1 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC1_Pos (1UL) /*!< Position of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Msk (0x1UL << ETM_TRCSSPCICR0_PC1_Pos) /*!< Bit mask of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Min (0x0UL) /*!< Min enumerator value of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Max (0x1UL) /*!< Max enumerator value of PC1 field. */ + #define ETM_TRCSSPCICR0_PC1_Disabled (0x0UL) /*!< Processor comparator 1 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC1_Enabled (0x1UL) /*!< Processor comparator 1 is selected for Single-shot control. */ + +/* PC2 @Bit 2 : Selects processor comparator 2 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC2_Pos (2UL) /*!< Position of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Msk (0x1UL << ETM_TRCSSPCICR0_PC2_Pos) /*!< Bit mask of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Min (0x0UL) /*!< Min enumerator value of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Max (0x1UL) /*!< Max enumerator value of PC2 field. */ + #define ETM_TRCSSPCICR0_PC2_Disabled (0x0UL) /*!< Processor comparator 2 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC2_Enabled (0x1UL) /*!< Processor comparator 2 is selected for Single-shot control. */ + +/* PC3 @Bit 3 : Selects processor comparator 3 inputs for Single-shot control */ + #define ETM_TRCSSPCICR0_PC3_Pos (3UL) /*!< Position of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Msk (0x1UL << ETM_TRCSSPCICR0_PC3_Pos) /*!< Bit mask of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Min (0x0UL) /*!< Min enumerator value of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Max (0x1UL) /*!< Max enumerator value of PC3 field. */ + #define ETM_TRCSSPCICR0_PC3_Disabled (0x0UL) /*!< Processor comparator 3 is not selected for Single-shot control. */ + #define ETM_TRCSSPCICR0_PC3_Enabled (0x1UL) /*!< Processor comparator 3 is selected for Single-shot control. */ + + +/* ETM_TRCPDCR: Controls the single-shot comparator. */ + #define ETM_TRCPDCR_ResetValue (0x00000000UL) /*!< Reset value of TRCPDCR register. */ + +/* PU @Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */ + #define ETM_TRCPDCR_PU_Pos (24UL) /*!< Position of PU field. */ + #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field. */ + #define ETM_TRCPDCR_PU_Min (0x0UL) /*!< Min enumerator value of PU field. */ + #define ETM_TRCPDCR_PU_Max (0x1UL) /*!< Max enumerator value of PU field. */ + #define ETM_TRCPDCR_PU_Disabled (0x0UL) /*!< Power not requested. */ + #define ETM_TRCPDCR_PU_Enabled (0x1UL) /*!< Power requested. */ + + +/* ETM_TRCPDSR: Indicates the power down status of the ETM. */ + #define ETM_TRCPDSR_ResetValue (0x00000000UL) /*!< Reset value of TRCPDSR register. */ + +/* POWER @Bit 0 : Indicates ETM is powered up */ + #define ETM_TRCPDSR_POWER_Pos (0UL) /*!< Position of POWER field. */ + #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field. */ + #define ETM_TRCPDSR_POWER_Min (0x0UL) /*!< Min enumerator value of POWER field. */ + #define ETM_TRCPDSR_POWER_Max (0x1UL) /*!< Max enumerator value of POWER field. */ + #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL) /*!< ETM is not powered up. All registers are not accessible. */ + #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL) /*!< ETM is powered up. All registers are accessible. */ + +/* STICKYPD @Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that + programming state has been lost. It is cleared after a read of the TRCPDSR */ + + #define ETM_TRCPDSR_STICKYPD_Pos (1UL) /*!< Position of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Min (0x0UL) /*!< Min enumerator value of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_Max (0x1UL) /*!< Max enumerator value of STICKYPD field. */ + #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last + read.*/ + #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL) /*!< Trace register power has been removed since the TRCPDSR was last + read.*/ + + +/* ETM_TRCITATBIDR: Sets the state of output pins. */ + #define ETM_TRCITATBIDR_ResetValue (0x00000000UL) /*!< Reset value of TRCITATBIDR register. */ + +/* ID0 @Bit 0 : Drives the ATIDMI[0] output pin. */ + #define ETM_TRCITATBIDR_ID0_Pos (0UL) /*!< Position of ID0 field. */ + #define ETM_TRCITATBIDR_ID0_Msk (0x1UL << ETM_TRCITATBIDR_ID0_Pos) /*!< Bit mask of ID0 field. */ + +/* ID1 @Bit 1 : Drives the ATIDMI[1] output pin. */ + #define ETM_TRCITATBIDR_ID1_Pos (1UL) /*!< Position of ID1 field. */ + #define ETM_TRCITATBIDR_ID1_Msk (0x1UL << ETM_TRCITATBIDR_ID1_Pos) /*!< Bit mask of ID1 field. */ + +/* ID2 @Bit 2 : Drives the ATIDMI[2] output pin. */ + #define ETM_TRCITATBIDR_ID2_Pos (2UL) /*!< Position of ID2 field. */ + #define ETM_TRCITATBIDR_ID2_Msk (0x1UL << ETM_TRCITATBIDR_ID2_Pos) /*!< Bit mask of ID2 field. */ + +/* ID3 @Bit 3 : Drives the ATIDMI[3] output pin. */ + #define ETM_TRCITATBIDR_ID3_Pos (3UL) /*!< Position of ID3 field. */ + #define ETM_TRCITATBIDR_ID3_Msk (0x1UL << ETM_TRCITATBIDR_ID3_Pos) /*!< Bit mask of ID3 field. */ + +/* ID4 @Bit 4 : Drives the ATIDMI[4] output pin. */ + #define ETM_TRCITATBIDR_ID4_Pos (4UL) /*!< Position of ID4 field. */ + #define ETM_TRCITATBIDR_ID4_Msk (0x1UL << ETM_TRCITATBIDR_ID4_Pos) /*!< Bit mask of ID4 field. */ + +/* ID5 @Bit 5 : Drives the ATIDMI[5] output pin. */ + #define ETM_TRCITATBIDR_ID5_Pos (5UL) /*!< Position of ID5 field. */ + #define ETM_TRCITATBIDR_ID5_Msk (0x1UL << ETM_TRCITATBIDR_ID5_Pos) /*!< Bit mask of ID5 field. */ + +/* ID6 @Bit 6 : Drives the ATIDMI[6] output pin. */ + #define ETM_TRCITATBIDR_ID6_Pos (6UL) /*!< Position of ID6 field. */ + #define ETM_TRCITATBIDR_ID6_Msk (0x1UL << ETM_TRCITATBIDR_ID6_Pos) /*!< Bit mask of ID6 field. */ + + +/* ETM_TRCITIATBINR: Reads the state of the input pins. */ + #define ETM_TRCITIATBINR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBINR register. */ + +/* ATVALID @Bit 0 : Returns the value of the ATVALIDMI input pin. */ + #define ETM_TRCITIATBINR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + +/* AFREADY @Bit 1 : Returns the value of the AFREADYMI input pin. */ + #define ETM_TRCITIATBINR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ + #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + + +/* ETM_TRCITIATBOUTR: Sets the state of the output pins. */ + #define ETM_TRCITIATBOUTR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBOUTR register. */ + +/* ATVALID @Bit 0 : Drives the ATVALIDMI output pin. */ + #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + +/* AFREADY @Bit 1 : Drives the AFREADYMI output pin. */ + #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ + #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + + +/* ETM_TRCITCTRL: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */ + #define ETM_TRCITCTRL_ResetValue (0x00000000UL) /*!< Reset value of TRCITCTRL register. */ + +/* IME @Bit 0 : Integration mode enable */ + #define ETM_TRCITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ + #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field. */ + #define ETM_TRCITCTRL_IME_Min (0x0UL) /*!< Min enumerator value of IME field. */ + #define ETM_TRCITCTRL_IME_Max (0x1UL) /*!< Max enumerator value of IME field. */ + #define ETM_TRCITCTRL_IME_Disabled (0x0UL) /*!< ETM is not in integration mode. */ + #define ETM_TRCITCTRL_IME_Enabled (0x1UL) /*!< ETM is in integration mode. */ + + +/* ETM_TRCCLAIMSET: Sets bits in the claim tag and determines the number of claim tag bits implemented. */ + #define ETM_TRCCLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of TRCCLAIMSET register. */ + +/* SET0 @Bit 0 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET0_Pos (0UL) /*!< Position of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Msk (0x1UL << ETM_TRCCLAIMSET_SET0_Pos) /*!< Bit mask of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Min (0x0UL) /*!< Min enumerator value of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_Max (0x1UL) /*!< Max enumerator value of SET0 field. */ + #define ETM_TRCCLAIMSET_SET0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ + #define ETM_TRCCLAIMSET_SET0_Set (0x1UL) /*!< Claim tag 0 is set. */ + #define ETM_TRCCLAIMSET_SET0_Claim (0x1UL) /*!< Set claim tag 0. */ + +/* SET1 @Bit 1 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET1_Pos (1UL) /*!< Position of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Msk (0x1UL << ETM_TRCCLAIMSET_SET1_Pos) /*!< Bit mask of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Min (0x0UL) /*!< Min enumerator value of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_Max (0x1UL) /*!< Max enumerator value of SET1 field. */ + #define ETM_TRCCLAIMSET_SET1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ + #define ETM_TRCCLAIMSET_SET1_Set (0x1UL) /*!< Claim tag 1 is set. */ + #define ETM_TRCCLAIMSET_SET1_Claim (0x1UL) /*!< Set claim tag 1. */ + +/* SET2 @Bit 2 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET2_Pos (2UL) /*!< Position of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Msk (0x1UL << ETM_TRCCLAIMSET_SET2_Pos) /*!< Bit mask of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Min (0x0UL) /*!< Min enumerator value of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_Max (0x1UL) /*!< Max enumerator value of SET2 field. */ + #define ETM_TRCCLAIMSET_SET2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ + #define ETM_TRCCLAIMSET_SET2_Set (0x1UL) /*!< Claim tag 2 is set. */ + #define ETM_TRCCLAIMSET_SET2_Claim (0x1UL) /*!< Set claim tag 2. */ + +/* SET3 @Bit 3 : Claim tag set register */ + #define ETM_TRCCLAIMSET_SET3_Pos (3UL) /*!< Position of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Msk (0x1UL << ETM_TRCCLAIMSET_SET3_Pos) /*!< Bit mask of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Min (0x0UL) /*!< Min enumerator value of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_Max (0x1UL) /*!< Max enumerator value of SET3 field. */ + #define ETM_TRCCLAIMSET_SET3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ + #define ETM_TRCCLAIMSET_SET3_Set (0x1UL) /*!< Claim tag 3 is set. */ + #define ETM_TRCCLAIMSET_SET3_Claim (0x1UL) /*!< Set claim tag 3. */ + + +/* ETM_TRCCLAIMCLR: Clears bits in the claim tag and determines the current value of the claim tag. */ + #define ETM_TRCCLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of TRCCLAIMCLR register. */ + +/* CLR0 @Bit 0 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR0_Pos (0UL) /*!< Position of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR0_Pos) /*!< Bit mask of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Min (0x0UL) /*!< Min enumerator value of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_Max (0x1UL) /*!< Max enumerator value of CLR0 field. */ + #define ETM_TRCCLAIMCLR_CLR0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ + #define ETM_TRCCLAIMCLR_CLR0_Set (0x1UL) /*!< Claim tag 0 is set. */ + #define ETM_TRCCLAIMCLR_CLR0_Clear (0x1UL) /*!< Clear claim tag 0. */ + +/* CLR1 @Bit 1 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR1_Pos (1UL) /*!< Position of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR1_Pos) /*!< Bit mask of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Min (0x0UL) /*!< Min enumerator value of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_Max (0x1UL) /*!< Max enumerator value of CLR1 field. */ + #define ETM_TRCCLAIMCLR_CLR1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ + #define ETM_TRCCLAIMCLR_CLR1_Set (0x1UL) /*!< Claim tag 1 is set. */ + #define ETM_TRCCLAIMCLR_CLR1_Clear (0x1UL) /*!< Clear claim tag 1. */ + +/* CLR2 @Bit 2 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR2_Pos (2UL) /*!< Position of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR2_Pos) /*!< Bit mask of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Min (0x0UL) /*!< Min enumerator value of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_Max (0x1UL) /*!< Max enumerator value of CLR2 field. */ + #define ETM_TRCCLAIMCLR_CLR2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ + #define ETM_TRCCLAIMCLR_CLR2_Set (0x1UL) /*!< Claim tag 2 is set. */ + #define ETM_TRCCLAIMCLR_CLR2_Clear (0x1UL) /*!< Clear claim tag 2. */ + +/* CLR3 @Bit 3 : Claim tag clear register */ + #define ETM_TRCCLAIMCLR_CLR3_Pos (3UL) /*!< Position of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR3_Pos) /*!< Bit mask of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Min (0x0UL) /*!< Min enumerator value of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_Max (0x1UL) /*!< Max enumerator value of CLR3 field. */ + #define ETM_TRCCLAIMCLR_CLR3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ + #define ETM_TRCCLAIMCLR_CLR3_Set (0x1UL) /*!< Claim tag 3 is set. */ + #define ETM_TRCCLAIMCLR_CLR3_Clear (0x1UL) /*!< Clear claim tag 3. */ + + +/* ETM_TRCAUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define ETM_TRCAUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TRCAUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define ETM_TRCAUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* ETM_TRCDEVARCH: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */ + #define ETM_TRCDEVARCH_ResetValue (0x00000000UL) /*!< Reset value of TRCDEVARCH register. */ + +/* ARCHID @Bits 0..15 : Architecture ID */ + #define ETM_TRCDEVARCH_ARCHID_Pos (0UL) /*!< Position of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Min (0x4A13UL) /*!< Min enumerator value of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_Max (0x4A13UL) /*!< Max enumerator value of ARCHID field. */ + #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL) /*!< Component is an ETMv4 component */ + +/* REVISION @Bits 16..19 : Architecture revision */ + #define ETM_TRCDEVARCH_REVISION_Pos (16UL) /*!< Position of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Min (0x2UL) /*!< Min enumerator value of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_Max (0x2UL) /*!< Max enumerator value of REVISION field. */ + #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL) /*!< Component is part of architecture 4.2 */ + +/* PRESENT @Bit 20 : This register is implemented */ + #define ETM_TRCDEVARCH_PRESENT_Pos (20UL) /*!< Position of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL) /*!< The register is not implemented. */ + #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL) /*!< The register is implemented. */ + +/* ARCHITECT @Bits 21..31 : Defines the architect of the component */ + #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL) /*!< Position of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Min (0x23BUL) /*!< Min enumerator value of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Max (0x23BUL) /*!< Max enumerator value of ARCHITECT field. */ + #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL) /*!< This peripheral was architected by Arm. */ + + +/* ETM_TRCDEVTYPE: Controls the single-shot comparator. */ + #define ETM_TRCDEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of TRCDEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Min (0x3UL) /*!< Min enumerator value of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_Max (0x3UL) /*!< Max enumerator value of MAJOR field. */ + #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL) /*!< Peripheral is a trace source. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define ETM_TRCDEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Min (0x1UL) /*!< Min enumerator value of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_Max (0x1UL) /*!< Max enumerator value of SUB field. */ + #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL) /*!< Peripheral is a processor trace source. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ETR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct ETR ======================================================== */ +/** + * @brief Embedded Trace Router + */ + typedef struct { /*!< ETR Structure */ + __IM uint32_t RESERVED; + __IOM uint32_t RSZ; /*!< (@ 0x00000004) RAM Size register */ + __IM uint32_t RESERVED1; + __IM uint32_t STS; /*!< (@ 0x0000000C) Status Register */ + __IM uint32_t RRD; /*!< (@ 0x00000010) RAM Read Data Register */ + __IOM uint32_t RRP; /*!< (@ 0x00000014) RAM Read Pointer Register */ + __IOM uint32_t RWP; /*!< (@ 0x00000018) RAM Write Pointer Register */ + __IOM uint32_t TRG; /*!< (@ 0x0000001C) Trigger Counter Register */ + __IOM uint32_t CTL; /*!< (@ 0x00000020) Control Register */ + __OM uint32_t RWD; /*!< (@ 0x00000024) RAM Write Data Register */ + __IOM uint32_t MODE; /*!< (@ 0x00000028) Mode Register */ + __IM uint32_t LBUFLEVEL; /*!< (@ 0x0000002C) Latched Buffer Fill Level */ + __IM uint32_t CBUFLEVEL; /*!< (@ 0x00000030) Current Buffer Fill Level */ + __IOM uint32_t BUFWM; /*!< (@ 0x00000034) Buffer Level Water Mark */ + __IOM uint32_t RRPHI; /*!< (@ 0x00000038) RAM Read Pointer High Register */ + __IOM uint32_t RWPHI; /*!< (@ 0x0000003C) RAM Write Pointer High Register */ + __IM uint32_t RESERVED2[52]; + __IOM uint32_t AXICTL; /*!< (@ 0x00000110) AXI Control Register */ + __IM uint32_t RESERVED3; + __IOM uint32_t DBALO; /*!< (@ 0x00000118) Data Buffer Address Low Register */ + __IOM uint32_t DBAHI; /*!< (@ 0x0000011C) Data Buffer Address High Register */ + __IM uint32_t RESERVED4[120]; + __IM uint32_t FFSR; /*!< (@ 0x00000300) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< (@ 0x00000304) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< (@ 0x00000308) Periodic Synchronization Counter Register */ + __IM uint32_t RESERVED5[756]; + __OM uint32_t ITATBMCTR0; /*!< (@ 0x00000EDC) Integration Test ATB Master Interface Control 0 + Register*/ + __OM uint32_t ITMISCOP0; /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 0 */ + __IM uint32_t RESERVED6; + __IM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register */ + __IM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0 */ + __OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Integration Test ATB Control 2 Register */ + __IM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) Integration Test ATB Control 1 Register */ + __IM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) Integration Test ATB Control 0 Register */ + __IM uint32_t RESERVED7; + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Integration Mode Control Register */ + __IM uint32_t RESERVED8[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Claim Tag Set Register */ + __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Claim Tag Clear Register */ + __IM uint32_t RESERVED9[2]; + __OM uint32_t LAR; /*!< (@ 0x00000FB0) Lock Access Register */ + __IM uint32_t LSR; /*!< (@ 0x00000FB4) Lock Status Register */ + __IM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Authentication Status Register */ + __IM uint32_t RESERVED10[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier Register */ + __IM uint32_t PERIPHID4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ + __IM uint32_t RESERVED11[3]; + __IM uint32_t PERIPHID0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ + __IM uint32_t PERIPHID1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ + __IM uint32_t PERIPHID2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ + __IM uint32_t PERIPHID3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ + __IM uint32_t COMPID0; /*!< (@ 0x00000FF0) Component ID0 Register */ + __IM uint32_t COMPID1; /*!< (@ 0x00000FF4) Component ID1 Register */ + __IM uint32_t COMPID2; /*!< (@ 0x00000FF8) Component ID2 Register */ + __IM uint32_t COMPID3; /*!< (@ 0x00000FFC) Component ID3 Register */ + } NRF_ETR_Type; /*!< Size = 4096 (0x1000) */ + +/* ETR_RSZ: RAM Size register */ + #define ETR_RSZ_ResetValue (0x00000000UL) /*!< Reset value of RSZ register. */ + +/* RSZ @Bits 0..30 : Size of the RAM in 32-bit words. */ + #define ETR_RSZ_RSZ_Pos (0UL) /*!< Position of RSZ field. */ + #define ETR_RSZ_RSZ_Msk (0x7FFFFFFFUL << ETR_RSZ_RSZ_Pos) /*!< Bit mask of RSZ field. */ + + +/* ETR_STS: Status Register */ + #define ETR_STS_ResetValue (0x0000000CUL) /*!< Reset value of STS register. */ + +/* FULL @Bit 0 : This bit can be used to help determine how much of the trace buffer contains valid data. */ + #define ETR_STS_FULL_Pos (0UL) /*!< Position of FULL field. */ + #define ETR_STS_FULL_Msk (0x1UL << ETR_STS_FULL_Pos) /*!< Bit mask of FULL field. */ + +/* TRIGGERED @Bit 1 : The Triggered bit is set when trace capture is in progress and the TMC has detected a trigger event. */ + #define ETR_STS_TRIGGERED_Pos (1UL) /*!< Position of TRIGGERED field. */ + #define ETR_STS_TRIGGERED_Msk (0x1UL << ETR_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */ + +/* TMCREADY @Bit 2 : TMC ready */ + #define ETR_STS_TMCREADY_Pos (2UL) /*!< Position of TMCREADY field. */ + #define ETR_STS_TMCREADY_Msk (0x1UL << ETR_STS_TMCREADY_Pos) /*!< Bit mask of TMCREADY field. */ + +/* FTEMPTY @Bit 3 : This bit is set when trace capture has stopped, and all internal pipelines and buffers have drained. */ + #define ETR_STS_FTEMPTY_Pos (3UL) /*!< Position of FTEMPTY field. */ + #define ETR_STS_FTEMPTY_Msk (0x1UL << ETR_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field. */ + +/* EMPTY @Bit 4 : If set, this bit indicates that the TMC does not contain any valid trace data in the trace memory. */ + #define ETR_STS_EMPTY_Pos (4UL) /*!< Position of EMPTY field. */ + #define ETR_STS_EMPTY_Msk (0x1UL << ETR_STS_EMPTY_Pos) /*!< Bit mask of EMPTY field. */ + +/* MEMERR @Bit 5 : This bit indicates that an error has occurred on the AXI master interface. */ + #define ETR_STS_MEMERR_Pos (5UL) /*!< Position of MEMERR field. */ + #define ETR_STS_MEMERR_Msk (0x1UL << ETR_STS_MEMERR_Pos) /*!< Bit mask of MEMERR field. */ + + +/* ETR_RRD: RAM Read Data Register */ + #define ETR_RRD_ResetValue (0x00000000UL) /*!< Reset value of RRD register. */ + +/* RRD @Bits 0..31 : Reads return data from Trace RAM */ + #define ETR_RRD_RRD_Pos (0UL) /*!< Position of RRD field. */ + #define ETR_RRD_RRD_Msk (0xFFFFFFFFUL << ETR_RRD_RRD_Pos) /*!< Bit mask of RRD field. */ + + +/* ETR_RRP: RAM Read Pointer Register */ + #define ETR_RRP_ResetValue (0x00000000UL) /*!< Reset value of RRP register. */ + +/* RRP @Bits 0..8 : This value represents the location in trace memory that will be accessed on a subsequent RRD read. */ + #define ETR_RRP_RRP_Pos (0UL) /*!< Position of RRP field. */ + #define ETR_RRP_RRP_Msk (0x1FFUL << ETR_RRP_RRP_Pos) /*!< Bit mask of RRP field. */ + + +/* ETR_RWP: RAM Write Pointer Register */ + #define ETR_RWP_ResetValue (0x00000000UL) /*!< Reset value of RWP register. */ + +/* RWP @Bits 0..31 : This value represents the location in trace memory that will be accessed on a subsequent write to the trace + memory. */ + + #define ETR_RWP_RWP_Pos (0UL) /*!< Position of RWP field. */ + #define ETR_RWP_RWP_Msk (0xFFFFFFFFUL << ETR_RWP_RWP_Pos) /*!< Bit mask of RWP field. */ + + +/* ETR_TRG: Trigger Counter Register */ + #define ETR_TRG_ResetValue (0x00000000UL) /*!< Reset value of TRG register. */ + +/* TRG @Bits 0..31 : This count represents the number of 32-bit words between a TRIGIN/trigger packet and a trigger event. */ + #define ETR_TRG_TRG_Pos (0UL) /*!< Position of TRG field. */ + #define ETR_TRG_TRG_Msk (0xFFFFFFFFUL << ETR_TRG_TRG_Pos) /*!< Bit mask of TRG field. */ + + +/* ETR_CTL: Control Register */ + #define ETR_CTL_ResetValue (0x00000000UL) /*!< Reset value of CTL register. */ + +/* TRACECAPTEN @Bit 0 : Setting this bit to 1 enables the TMC to capture trace data. */ + #define ETR_CTL_TRACECAPTEN_Pos (0UL) /*!< Position of TRACECAPTEN field. */ + #define ETR_CTL_TRACECAPTEN_Msk (0x1UL << ETR_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field. */ + + +/* ETR_RWD: RAM Write Data Register */ + #define ETR_RWD_ResetValue (0x00000000UL) /*!< Reset value of RWD register. */ + +/* RWD @Bits 0..31 : Data written to this register is placed in the Trace RAM. */ + #define ETR_RWD_RWD_Pos (0UL) /*!< Position of RWD field. */ + #define ETR_RWD_RWD_Msk (0xFFFFFFFFUL << ETR_RWD_RWD_Pos) /*!< Bit mask of RWD field. */ + + +/* ETR_MODE: Mode Register */ + #define ETR_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : Selects the operating mode. */ + #define ETR_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define ETR_MODE_MODE_Msk (0x3UL << ETR_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define ETR_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define ETR_MODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define ETR_MODE_MODE_CIRCULARBUF (0x0UL) /*!< Circular Buffer mode */ + #define ETR_MODE_MODE_FIFO (0x1UL) /*!< Software FIFO mode */ + + +/* ETR_LBUFLEVEL: Latched Buffer Fill Level */ + #define ETR_LBUFLEVEL_ResetValue (0x00000000UL) /*!< Reset value of LBUFLEVEL register. */ + +/* LBUFLEVEL @Bits 0..30 : Indicates the maximum fill level of the trace memory in 32-bit words since this register was last + read. */ + + #define ETR_LBUFLEVEL_LBUFLEVEL_Pos (0UL) /*!< Position of LBUFLEVEL field. */ + #define ETR_LBUFLEVEL_LBUFLEVEL_Msk (0x7FFFFFFFUL << ETR_LBUFLEVEL_LBUFLEVEL_Pos) /*!< Bit mask of LBUFLEVEL field. */ + + +/* ETR_CBUFLEVEL: Current Buffer Fill Level */ + #define ETR_CBUFLEVEL_ResetValue (0x00000000UL) /*!< Reset value of CBUFLEVEL register. */ + +/* CBUFLEVEL @Bits 0..7 : Indicates the current fill level of the trace memory in 32-bit words. */ + #define ETR_CBUFLEVEL_CBUFLEVEL_Pos (0UL) /*!< Position of CBUFLEVEL field. */ + #define ETR_CBUFLEVEL_CBUFLEVEL_Msk (0xFFUL << ETR_CBUFLEVEL_CBUFLEVEL_Pos) /*!< Bit mask of CBUFLEVEL field. */ + + +/* ETR_BUFWM: Buffer Level Water Mark */ + #define ETR_BUFWM_ResetValue (0x00000000UL) /*!< Reset value of BUFWM register. */ + +/* BUFWM @Bits 0..6 : Indicates the desired threshold vacancy level in 32-bit words in the trace memory. */ + #define ETR_BUFWM_BUFWM_Pos (0UL) /*!< Position of BUFWM field. */ + #define ETR_BUFWM_BUFWM_Msk (0x7FUL << ETR_BUFWM_BUFWM_Pos) /*!< Bit mask of BUFWM field. */ + + +/* ETR_RRPHI: RAM Read Pointer High Register */ + #define ETR_RRPHI_ResetValue (0x00000000UL) /*!< Reset value of RRPHI register. */ + +/* RRPHI @Bits 0..7 : Bits[39:32] of the read pointer */ + #define ETR_RRPHI_RRPHI_Pos (0UL) /*!< Position of RRPHI field. */ + #define ETR_RRPHI_RRPHI_Msk (0xFFUL << ETR_RRPHI_RRPHI_Pos) /*!< Bit mask of RRPHI field. */ + + +/* ETR_RWPHI: RAM Write Pointer High Register */ + #define ETR_RWPHI_ResetValue (0x00000000UL) /*!< Reset value of RWPHI register. */ + +/* RWPHI @Bits 0..7 : Bits[39:32] of the write pointer */ + #define ETR_RWPHI_RWPHI_Pos (0UL) /*!< Position of RWPHI field. */ + #define ETR_RWPHI_RWPHI_Msk (0xFFUL << ETR_RWPHI_RWPHI_Pos) /*!< Bit mask of RWPHI field. */ + + +/* ETR_AXICTL: AXI Control Register */ + #define ETR_AXICTL_ResetValue (0x00000000UL) /*!< Reset value of AXICTL register. */ + +/* PROTCTRLBIT0 @Bit 0 : This bit controls the value driven on ARPROTM[0]/AWPROTM[0] on the AXI interface when performing AXI + transfers. */ + + #define ETR_AXICTL_PROTCTRLBIT0_Pos (0UL) /*!< Position of PROTCTRLBIT0 field. */ + #define ETR_AXICTL_PROTCTRLBIT0_Msk (0x1UL << ETR_AXICTL_PROTCTRLBIT0_Pos) /*!< Bit mask of PROTCTRLBIT0 field. */ + +/* PROTCTRLBIT1 @Bit 1 : This bit controls the value driven on ARPROTM[1]/AWPROTM[1] on the AXI interface when performing AXI + transfers. */ + + #define ETR_AXICTL_PROTCTRLBIT1_Pos (1UL) /*!< Position of PROTCTRLBIT1 field. */ + #define ETR_AXICTL_PROTCTRLBIT1_Msk (0x1UL << ETR_AXICTL_PROTCTRLBIT1_Pos) /*!< Bit mask of PROTCTRLBIT1 field. */ + +/* CACHECTRLBIT0 @Bit 2 : This bit controls the value driven on the ARCACHEM[0]/AWCACHEM[0] signal on the AXI interface when + performing AXI transfers. */ + + #define ETR_AXICTL_CACHECTRLBIT0_Pos (2UL) /*!< Position of CACHECTRLBIT0 field. */ + #define ETR_AXICTL_CACHECTRLBIT0_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT0_Pos) /*!< Bit mask of CACHECTRLBIT0 field. */ + +/* CACHECTRLBIT1 @Bit 3 : This bit controls the value driven on the ARCACHEM[1]/AWCACHEM[1] signal on the AXI interface when + performing AXI transfers. */ + + #define ETR_AXICTL_CACHECTRLBIT1_Pos (3UL) /*!< Position of CACHECTRLBIT1 field. */ + #define ETR_AXICTL_CACHECTRLBIT1_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT1_Pos) /*!< Bit mask of CACHECTRLBIT1 field. */ + +/* CACHECTRLBIT2 @Bit 4 : This bit controls the value driven on the ARCACHEM[2]/AWCACHEM[2] signal on the AXI interface when + performing AXI transfers. */ + + #define ETR_AXICTL_CACHECTRLBIT2_Pos (4UL) /*!< Position of CACHECTRLBIT2 field. */ + #define ETR_AXICTL_CACHECTRLBIT2_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT2_Pos) /*!< Bit mask of CACHECTRLBIT2 field. */ + +/* CACHECTRLBIT3 @Bit 5 : This bit controls the value driven on the ARCACHEM[3]/AWCACHEM[3] signal on the AXI interface when + performing AXI transfers. */ + + #define ETR_AXICTL_CACHECTRLBIT3_Pos (5UL) /*!< Position of CACHECTRLBIT3 field. */ + #define ETR_AXICTL_CACHECTRLBIT3_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT3_Pos) /*!< Bit mask of CACHECTRLBIT3 field. */ + +/* SCATTERGATHERMODE @Bit 7 : This bit indicates whether trace memory is accessed as a single buffer in system memory or as a + linked-list based scatter-gather memory. */ + + #define ETR_AXICTL_SCATTERGATHERMODE_Pos (7UL) /*!< Position of SCATTERGATHERMODE field. */ + #define ETR_AXICTL_SCATTERGATHERMODE_Msk (0x1UL << ETR_AXICTL_SCATTERGATHERMODE_Pos) /*!< Bit mask of SCATTERGATHERMODE + field.*/ + +/* WRBURSTLEN @Bits 8..11 : This field indicates the maximum number of data transfers that can occur within each burst initiated + by the TMC on the AXI interface. */ + + #define ETR_AXICTL_WRBURSTLEN_Pos (8UL) /*!< Position of WRBURSTLEN field. */ + #define ETR_AXICTL_WRBURSTLEN_Msk (0xFUL << ETR_AXICTL_WRBURSTLEN_Pos) /*!< Bit mask of WRBURSTLEN field. */ + + +/* ETR_DBALO: Data Buffer Address Low Register */ + #define ETR_DBALO_ResetValue (0x00000000UL) /*!< Reset value of DBALO register. */ + +/* BUFADDRLO @Bits 0..31 : Holds the lower 32 bits of the 40-bit address used to locate the trace buffer in system memory */ + #define ETR_DBALO_BUFADDRLO_Pos (0UL) /*!< Position of BUFADDRLO field. */ + #define ETR_DBALO_BUFADDRLO_Msk (0xFFFFFFFFUL << ETR_DBALO_BUFADDRLO_Pos) /*!< Bit mask of BUFADDRLO field. */ + + +/* ETR_DBAHI: Data Buffer Address High Register */ + #define ETR_DBAHI_ResetValue (0x00000000UL) /*!< Reset value of DBAHI register. */ + +/* BUFADDRHI @Bits 0..7 : Holds the upper 8 bits of the 40-bit address used to locate the trace buffer in system memory */ + #define ETR_DBAHI_BUFADDRHI_Pos (0UL) /*!< Position of BUFADDRHI field. */ + #define ETR_DBAHI_BUFADDRHI_Msk (0xFFUL << ETR_DBAHI_BUFADDRHI_Pos) /*!< Bit mask of BUFADDRHI field. */ + + +/* ETR_FFSR: Formatter and Flush Status Register */ + #define ETR_FFSR_ResetValue (0x00000002UL) /*!< Reset value of FFSR register. */ + +/* FLINPROG @Bit 0 : This bit indicates whether the TMC is currently processing a flush on the ATB slave port. This bit reflects + the status of the AFVALIDS output. The flush initiation is controlled by the flush-control bits in the FFCR + register. */ + + #define ETR_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */ + #define ETR_FFSR_FLINPROG_Msk (0x1UL << ETR_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */ + +/* FTSTOPPED @Bit 1 : This bit behaves the same way as the FtEmpty bit in the STS register, 0x00C. */ + #define ETR_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */ + #define ETR_FFSR_FTSTOPPED_Msk (0x1UL << ETR_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */ + + +/* ETR_FFCR: Formatter and Flush Control Register */ + #define ETR_FFCR_ResetValue (0x00000000UL) /*!< Reset value of FFCR register. */ + +/* ENFT @Bit 0 : If this bit is set, formatting is enabled. */ + #define ETR_FFCR_ENFT_Pos (0UL) /*!< Position of ENFT field. */ + #define ETR_FFCR_ENFT_Msk (0x1UL << ETR_FFCR_ENFT_Pos) /*!< Bit mask of ENFT field. */ + +/* ENTI @Bit 1 : Setting this bit enables the insertion of triggers in the formatted trace stream. */ + #define ETR_FFCR_ENTI_Pos (1UL) /*!< Position of ENTI field. */ + #define ETR_FFCR_ENTI_Msk (0x1UL << ETR_FFCR_ENTI_Pos) /*!< Bit mask of ENTI field. */ + +/* FONFLIN @Bit 4 : Setting this bit enables the detection of transitions on the FLUSHIN input by the TMC. */ + #define ETR_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */ + #define ETR_FFCR_FONFLIN_Msk (0x1UL << ETR_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */ + +/* FONTRIGEVT @Bit 5 : Setting this bit generates a flush when a Trigger event occurs. */ + #define ETR_FFCR_FONTRIGEVT_Pos (5UL) /*!< Position of FONTRIGEVT field. */ + #define ETR_FFCR_FONTRIGEVT_Msk (0x1UL << ETR_FFCR_FONTRIGEVT_Pos) /*!< Bit mask of FONTRIGEVT field. */ + +/* FLUSHMAN @Bit 6 : Manually generate a flush of the system. */ + #define ETR_FFCR_FLUSHMAN_Pos (6UL) /*!< Position of FLUSHMAN field. */ + #define ETR_FFCR_FLUSHMAN_Msk (0x1UL << ETR_FFCR_FLUSHMAN_Pos) /*!< Bit mask of FLUSHMAN field. */ + +/* TRIGONTRIGIN @Bit 8 : If this bit is set, a trigger is indicated on the trace stream when a rising edge is detected on the + TRIGIN input. */ + + #define ETR_FFCR_TRIGONTRIGIN_Pos (8UL) /*!< Position of TRIGONTRIGIN field. */ + #define ETR_FFCR_TRIGONTRIGIN_Msk (0x1UL << ETR_FFCR_TRIGONTRIGIN_Pos) /*!< Bit mask of TRIGONTRIGIN field. */ + +/* TRIGONTRIGEVT @Bit 9 : If this bit is set, a trigger is indicated on the output trace stream when a Trigger Event occurs. */ + #define ETR_FFCR_TRIGONTRIGEVT_Pos (9UL) /*!< Position of TRIGONTRIGEVT field. */ + #define ETR_FFCR_TRIGONTRIGEVT_Msk (0x1UL << ETR_FFCR_TRIGONTRIGEVT_Pos) /*!< Bit mask of TRIGONTRIGEVT field. */ + +/* TRIGONFL @Bit 10 : If this bit is set, a trigger is indicated on the trace stream on AFREADYS being returned. */ + #define ETR_FFCR_TRIGONFL_Pos (10UL) /*!< Position of TRIGONFL field. */ + #define ETR_FFCR_TRIGONFL_Msk (0x1UL << ETR_FFCR_TRIGONFL_Pos) /*!< Bit mask of TRIGONFL field. */ + +/* STOPONFL @Bit 12 : If this bit is set, the formatter is stopped on completion of a flush operation. */ + #define ETR_FFCR_STOPONFL_Pos (12UL) /*!< Position of STOPONFL field. */ + #define ETR_FFCR_STOPONFL_Msk (0x1UL << ETR_FFCR_STOPONFL_Pos) /*!< Bit mask of STOPONFL field. */ + +/* STOPONTRIGEVT @Bit 13 : If this bit is set, the formatter is stopped when a Trigger Event has been observed. */ + #define ETR_FFCR_STOPONTRIGEVT_Pos (13UL) /*!< Position of STOPONTRIGEVT field. */ + #define ETR_FFCR_STOPONTRIGEVT_Msk (0x1UL << ETR_FFCR_STOPONTRIGEVT_Pos) /*!< Bit mask of STOPONTRIGEVT field. */ + +/* DRAINBUFFER @Bit 14 : This bit is used to enable draining of the trace data through the ATB Master interface after the + formatter has stopped. */ + + #define ETR_FFCR_DRAINBUFFER_Pos (14UL) /*!< Position of DRAINBUFFER field. */ + #define ETR_FFCR_DRAINBUFFER_Msk (0x1UL << ETR_FFCR_DRAINBUFFER_Pos) /*!< Bit mask of DRAINBUFFER field. */ + + +/* ETR_PSCR: Periodic Synchronization Counter Register */ + #define ETR_PSCR_ResetValue (0x00000000UL) /*!< Reset value of PSCR register. */ + +/* PSCOUNT @Bits 0..4 : The reload value of the Synchronization Counter */ + #define ETR_PSCR_PSCOUNT_Pos (0UL) /*!< Position of PSCOUNT field. */ + #define ETR_PSCR_PSCOUNT_Msk (0x1FUL << ETR_PSCR_PSCOUNT_Pos) /*!< Bit mask of PSCOUNT field. */ + + +/* ETR_ITATBMCTR0: Integration Test ATB Master Interface Control 0 Register */ + #define ETR_ITATBMCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBMCTR0 register. */ + +/* ATVALIDM @Bit 0 : Set the value of ATVALIDM output */ + #define ETR_ITATBMCTR0_ATVALIDM_Pos (0UL) /*!< Position of ATVALIDM field. */ + #define ETR_ITATBMCTR0_ATVALIDM_Msk (0x1UL << ETR_ITATBMCTR0_ATVALIDM_Pos) /*!< Bit mask of ATVALIDM field. */ + +/* AFREADYM @Bit 1 : Set the value of AFREADYM output */ + #define ETR_ITATBMCTR0_AFREADYM_Pos (1UL) /*!< Position of AFREADYM field. */ + #define ETR_ITATBMCTR0_AFREADYM_Msk (0x1UL << ETR_ITATBMCTR0_AFREADYM_Pos) /*!< Bit mask of AFREADYM field. */ + +/* ATBYTESM @Bits 8..9 : Control the value of ATBYTESM output from TMC. The value written to this field is driven on the + ATBYTESM output of the TMC. */ + + #define ETR_ITATBMCTR0_ATBYTESM_Pos (8UL) /*!< Position of ATBYTESM field. */ + #define ETR_ITATBMCTR0_ATBYTESM_Msk (0x3UL << ETR_ITATBMCTR0_ATBYTESM_Pos) /*!< Bit mask of ATBYTESM field. */ + + +/* ETR_ITMISCOP0: Integration Test Miscellaneous Output Register 0 */ + #define ETR_ITMISCOP0_ResetValue (0x00000000UL) /*!< Reset value of ITMISCOP0 register. */ + +/* ACQCOMP @Bit 0 : Set the value of the ACQCOMP output. */ + #define ETR_ITMISCOP0_ACQCOMP_Pos (0UL) /*!< Position of ACQCOMP field. */ + #define ETR_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETR_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */ + +/* FULL @Bit 1 : Set the value of the FULL output. */ + #define ETR_ITMISCOP0_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define ETR_ITMISCOP0_FULL_Msk (0x1UL << ETR_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field. */ + + +/* ETR_ITTRFLIN: Integration Test Trigger In and Flush In Register */ + #define ETR_ITTRFLIN_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLIN register. */ + +/* TRIGIN @Bit 0 : Read the value of the TRIGIN input. */ + #define ETR_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */ + #define ETR_ITTRFLIN_TRIGIN_Msk (0x1UL << ETR_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ + +/* FLUSHIN @Bit 1 : Read the value of the FLUSHIN input. */ + #define ETR_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */ + #define ETR_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETR_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */ + + +/* ETR_ITATBDATA0: Integration Test ATB Data Register 0 */ + #define ETR_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register. */ + +/* ATDATASBIT0 @Bit 0 : Read the value of ATDATAS[0] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT0_Pos (0UL) /*!< Position of ATDATASBIT0 field. */ + #define ETR_ITATBDATA0_ATDATASBIT0_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT0_Pos) /*!< Bit mask of ATDATASBIT0 field. */ + +/* ATDATASBIT7 @Bit 1 : Read the value of ATDATAS[7] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT7_Pos (1UL) /*!< Position of ATDATASBIT7 field. */ + #define ETR_ITATBDATA0_ATDATASBIT7_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT7_Pos) /*!< Bit mask of ATDATASBIT7 field. */ + +/* ATDATASBIT15 @Bit 2 : Read the value of ATDATAS[15] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT15_Pos (2UL) /*!< Position of ATDATASBIT15 field. */ + #define ETR_ITATBDATA0_ATDATASBIT15_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT15_Pos) /*!< Bit mask of ATDATASBIT15 field. */ + +/* ATDATASBIT23 @Bit 3 : Read the value of ATDATAS[23] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT23_Pos (3UL) /*!< Position of ATDATASBIT23 field. */ + #define ETR_ITATBDATA0_ATDATASBIT23_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT23_Pos) /*!< Bit mask of ATDATASBIT23 field. */ + +/* ATDATASBIT31 @Bit 4 : Read the value of ATDATAS[31] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT31_Pos (4UL) /*!< Position of ATDATASBIT31 field. */ + #define ETR_ITATBDATA0_ATDATASBIT31_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT31_Pos) /*!< Bit mask of ATDATASBIT31 field. */ + +/* ATDATASBIT39 @Bit 5 : Read the value of ATDATAS[39] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT39_Pos (5UL) /*!< Position of ATDATASBIT39 field. */ + #define ETR_ITATBDATA0_ATDATASBIT39_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT39_Pos) /*!< Bit mask of ATDATASBIT39 field. */ + +/* ATDATASBIT47 @Bit 6 : Read the value of ATDATAS[47] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT47_Pos (6UL) /*!< Position of ATDATASBIT47 field. */ + #define ETR_ITATBDATA0_ATDATASBIT47_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT47_Pos) /*!< Bit mask of ATDATASBIT47 field. */ + +/* ATDATASBIT55 @Bit 7 : Read the value of ATDATAS[55] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT55_Pos (7UL) /*!< Position of ATDATASBIT55 field. */ + #define ETR_ITATBDATA0_ATDATASBIT55_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT55_Pos) /*!< Bit mask of ATDATASBIT55 field. */ + +/* ATDATASBIT63 @Bit 8 : Read the value of ATDATAS[63] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT63_Pos (8UL) /*!< Position of ATDATASBIT63 field. */ + #define ETR_ITATBDATA0_ATDATASBIT63_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT63_Pos) /*!< Bit mask of ATDATASBIT63 field. */ + +/* ATDATASBIT71 @Bit 9 : Read the value of ATDATAS[71] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT71_Pos (9UL) /*!< Position of ATDATASBIT71 field. */ + #define ETR_ITATBDATA0_ATDATASBIT71_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT71_Pos) /*!< Bit mask of ATDATASBIT71 field. */ + +/* ATDATASBIT79 @Bit 10 : Read the value of ATDATAS[79] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT79_Pos (10UL) /*!< Position of ATDATASBIT79 field. */ + #define ETR_ITATBDATA0_ATDATASBIT79_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT79_Pos) /*!< Bit mask of ATDATASBIT79 field. */ + +/* ATDATASBIT87 @Bit 11 : Read the value of ATDATAS[87] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT87_Pos (11UL) /*!< Position of ATDATASBIT87 field. */ + #define ETR_ITATBDATA0_ATDATASBIT87_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT87_Pos) /*!< Bit mask of ATDATASBIT87 field. */ + +/* ATDATASBIT95 @Bit 12 : Read the value of ATDATAS[95] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT95_Pos (12UL) /*!< Position of ATDATASBIT95 field. */ + #define ETR_ITATBDATA0_ATDATASBIT95_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT95_Pos) /*!< Bit mask of ATDATASBIT95 field. */ + +/* ATDATASBIT103 @Bit 13 : Read the value of ATDATAS[103] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT103_Pos (13UL) /*!< Position of ATDATASBIT103 field. */ + #define ETR_ITATBDATA0_ATDATASBIT103_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT103_Pos) /*!< Bit mask of ATDATASBIT103 field. */ + +/* ATDATASBIT111 @Bit 14 : Read the value of ATDATAS[111] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT111_Pos (14UL) /*!< Position of ATDATASBIT111 field. */ + #define ETR_ITATBDATA0_ATDATASBIT111_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT111_Pos) /*!< Bit mask of ATDATASBIT111 field. */ + +/* ATDATASBIT119 @Bit 15 : Read the value of ATDATAS[119] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT119_Pos (15UL) /*!< Position of ATDATASBIT119 field. */ + #define ETR_ITATBDATA0_ATDATASBIT119_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT119_Pos) /*!< Bit mask of ATDATASBIT119 field. */ + +/* ATDATASBIT127 @Bit 16 : Read the value of ATDATAS[127] input to TMC */ + #define ETR_ITATBDATA0_ATDATASBIT127_Pos (16UL) /*!< Position of ATDATASBIT127 field. */ + #define ETR_ITATBDATA0_ATDATASBIT127_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT127_Pos) /*!< Bit mask of ATDATASBIT127 field. */ + + +/* ETR_ITATBCTR2: Integration Test ATB Control 2 Register */ + #define ETR_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register. */ + +/* ATREADYS @Bit 0 : Set the value of ATREADYS output */ + #define ETR_ITATBCTR2_ATREADYS_Pos (0UL) /*!< Position of ATREADYS field. */ + #define ETR_ITATBCTR2_ATREADYS_Msk (0x1UL << ETR_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */ + +/* AFVALIDS @Bit 1 : Set the value of AFVALIDS output */ + #define ETR_ITATBCTR2_AFVALIDS_Pos (1UL) /*!< Position of AFVALIDS field. */ + #define ETR_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETR_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field. */ + +/* SYNCREQS @Bit 2 : Set the value of SYNCREQS output */ + #define ETR_ITATBCTR2_SYNCREQS_Pos (2UL) /*!< Position of SYNCREQS field. */ + #define ETR_ITATBCTR2_SYNCREQS_Msk (0x1UL << ETR_ITATBCTR2_SYNCREQS_Pos) /*!< Bit mask of SYNCREQS field. */ + + +/* ETR_ITATBCTR1: Integration Test ATB Control 1 Register */ + #define ETR_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register. */ + +/* ATIDS @Bits 0..6 : Read the value of ATIDS input to TMC */ + #define ETR_ITATBCTR1_ATIDS_Pos (0UL) /*!< Position of ATIDS field. */ + #define ETR_ITATBCTR1_ATIDS_Msk (0x7FUL << ETR_ITATBCTR1_ATIDS_Pos) /*!< Bit mask of ATIDS field. */ + + +/* ETR_ITATBCTR0: Integration Test ATB Control 0 Register */ + #define ETR_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALIDS @Bit 0 : Read the value of ATVALIDS input to TMC */ + #define ETR_ITATBCTR0_ATVALIDS_Pos (0UL) /*!< Position of ATVALIDS field. */ + #define ETR_ITATBCTR0_ATVALIDS_Msk (0x1UL << ETR_ITATBCTR0_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field. */ + +/* AFREADYS @Bit 1 : Read the value of AFREADYS input to TMC */ + #define ETR_ITATBCTR0_AFREADYS_Pos (1UL) /*!< Position of AFREADYS field. */ + #define ETR_ITATBCTR0_AFREADYS_Msk (0x1UL << ETR_ITATBCTR0_AFREADYS_Pos) /*!< Bit mask of AFREADYS field. */ + +/* ATBYTESS @Bits 8..9 : Read the value of ATBYTESS input to TMC */ + #define ETR_ITATBCTR0_ATBYTESS_Pos (8UL) /*!< Position of ATBYTESS field. */ + #define ETR_ITATBCTR0_ATBYTESS_Msk (0x3UL << ETR_ITATBCTR0_ATBYTESS_Pos) /*!< Bit mask of ATBYTESS field. */ + + +/* ETR_ITCTRL: Integration Mode Control Register */ + #define ETR_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* INTEGRATION_MODE @Bit 0 : Allows the component to switch from functional mode to integration mode or back. */ + #define ETR_ITCTRL_INTEGRATION_MODE_Pos (0UL) /*!< Position of INTEGRATION_MODE field. */ + #define ETR_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETR_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field. */ + + +/* ETR_CLAIMSET: Claim Tag Set Register */ + #define ETR_CLAIMSET_ResetValue (0x0000000FUL) /*!< Reset value of CLAIMSET register. */ + +/* CLAIMSET @Bits 0..3 : This claim tag bit is implemented */ + #define ETR_CLAIMSET_CLAIMSET_Pos (0UL) /*!< Position of CLAIMSET field. */ + #define ETR_CLAIMSET_CLAIMSET_Msk (0xFUL << ETR_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field. */ + + +/* ETR_CLAIMCLR: Claim Tag Clear Register */ + #define ETR_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* CLAIMCLR @Bits 0..3 : The value present reflects the current setting of the Claim Tag. */ + #define ETR_CLAIMCLR_CLAIMCLR_Pos (0UL) /*!< Position of CLAIMCLR field. */ + #define ETR_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETR_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field. */ + + +/* ETR_LAR: Lock Access Register */ + #define ETR_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS_W @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than + 0xC5ACCE55 will have the affect of removing write access. */ + + #define ETR_LAR_ACCESS_W_Pos (0UL) /*!< Position of ACCESS_W field. */ + #define ETR_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETR_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field. */ + + +/* ETR_LSR: Lock Status Register */ + #define ETR_LSR_ResetValue (0x00000003UL) /*!< Reset value of LSR register. */ + +/* LOCKEXIST @Bit 0 : Indicates that a lock control mechanism exists for this device. */ + #define ETR_LSR_LOCKEXIST_Pos (0UL) /*!< Position of LOCKEXIST field. */ + #define ETR_LSR_LOCKEXIST_Msk (0x1UL << ETR_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field. */ + +/* LOCKGRANT @Bit 1 : Returns the current status of the Lock. */ + #define ETR_LSR_LOCKGRANT_Pos (1UL) /*!< Position of LOCKGRANT field. */ + #define ETR_LSR_LOCKGRANT_Msk (0x1UL << ETR_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field. */ + +/* LOCKTYPE @Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */ + #define ETR_LSR_LOCKTYPE_Pos (2UL) /*!< Position of LOCKTYPE field. */ + #define ETR_LSR_LOCKTYPE_Msk (0x1UL << ETR_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field. */ + #define ETR_LSR_LOCKTYPE_Min (0x0UL) /*!< Min enumerator value of LOCKTYPE field. */ + #define ETR_LSR_LOCKTYPE_Max (0x0UL) /*!< Max enumerator value of LOCKTYPE field. */ + #define ETR_LSR_LOCKTYPE_32BIT (0x0UL) /*!< This component implements a 32-bit Lock Access Register */ + + +/* ETR_AUTHSTATUS: Authentication Status Register */ + #define ETR_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Indicates the security level for non-secure invasive debug */ + #define ETR_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define ETR_AUTHSTATUS_NSID_Msk (0x3UL << ETR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define ETR_AUTHSTATUS_NSID_Min (0x2UL) /*!< Min enumerator value of NSID field. */ + #define ETR_AUTHSTATUS_NSID_Max (0x3UL) /*!< Max enumerator value of NSID field. */ + #define ETR_AUTHSTATUS_NSID_DISABLED (0x2UL) /*!< Functionality disabled. This return value occurs when DBGEN is LOW. */ + #define ETR_AUTHSTATUS_NSID_ENABLED (0x3UL) /*!< Functionality enabled. This return value occurs when DBGEN is HIGH. */ + +/* NSNID @Bits 2..3 : Indicates the security level for non-secure non-invasive debug */ + #define ETR_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define ETR_AUTHSTATUS_NSNID_Msk (0x3UL << ETR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define ETR_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define ETR_AUTHSTATUS_NSNID_Max (0x0UL) /*!< Max enumerator value of NSNID field. */ + #define ETR_AUTHSTATUS_NSNID_NONE (0x0UL) /*!< Functionality not implemented or controlled elsewhere. */ + +/* SID @Bits 4..5 : Indicates the security level for secure invasive debug */ + #define ETR_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define ETR_AUTHSTATUS_SID_Msk (0x3UL << ETR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define ETR_AUTHSTATUS_SID_Min (0x2UL) /*!< Min enumerator value of SID field. */ + #define ETR_AUTHSTATUS_SID_Max (0x3UL) /*!< Max enumerator value of SID field. */ + #define ETR_AUTHSTATUS_SID_DISABLED (0x2UL) /*!< Functionality disabled. This return value occurs when DBGEN is LOW or + SPIDEN is LOW.*/ + #define ETR_AUTHSTATUS_SID_ENABLED (0x3UL) /*!< Functionality enabled. This return value occurs when DBGEN and SPIDEN + are HIGH.*/ + +/* SNID @Bits 6..7 : Indicates the security level for secure non-invasive debug */ + #define ETR_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define ETR_AUTHSTATUS_SNID_Msk (0x3UL << ETR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define ETR_AUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define ETR_AUTHSTATUS_SNID_Max (0x0UL) /*!< Max enumerator value of SNID field. */ + #define ETR_AUTHSTATUS_SNID_NONE (0x0UL) /*!< Functionality not implemented or controlled elsewhere. */ + + +/* ETR_DEVID: Device Configuration Register */ + #define ETR_DEVID_ResetValue (0x00000300UL) /*!< Reset value of DEVID register. */ + +/* ATBINPORTCOUNT @Bits 0..4 : This value indicates the type/number of ATB multiplexing present on the input ATB. */ + #define ETR_DEVID_ATBINPORTCOUNT_Pos (0UL) /*!< Position of ATBINPORTCOUNT field. */ + #define ETR_DEVID_ATBINPORTCOUNT_Msk (0x1FUL << ETR_DEVID_ATBINPORTCOUNT_Pos) /*!< Bit mask of ATBINPORTCOUNT field. */ + +/* CLKSCHEME @Bit 5 : This value indicates the TMC RAM clocking scheme used, ie. whether the TMC RAM operates synchronously or + asynchronously to CLK. */ + + #define ETR_DEVID_CLKSCHEME_Pos (5UL) /*!< Position of CLKSCHEME field. */ + #define ETR_DEVID_CLKSCHEME_Msk (0x1UL << ETR_DEVID_CLKSCHEME_Pos) /*!< Bit mask of CLKSCHEME field. */ + #define ETR_DEVID_CLKSCHEME_Min (0x0UL) /*!< Min enumerator value of CLKSCHEME field. */ + #define ETR_DEVID_CLKSCHEME_Max (0x0UL) /*!< Max enumerator value of CLKSCHEME field. */ + #define ETR_DEVID_CLKSCHEME_SYNC (0x0UL) /*!< The TMC RAM operates synchronously to CLK. */ + +/* CONFIGTYPE @Bits 6..7 : This value indicates TMC configuration type. */ + #define ETR_DEVID_CONFIGTYPE_Pos (6UL) /*!< Position of CONFIGTYPE field. */ + #define ETR_DEVID_CONFIGTYPE_Msk (0x3UL << ETR_DEVID_CONFIGTYPE_Pos) /*!< Bit mask of CONFIGTYPE field. */ + #define ETR_DEVID_CONFIGTYPE_Min (0x0UL) /*!< Min enumerator value of CONFIGTYPE field. */ + #define ETR_DEVID_CONFIGTYPE_Max (0x2UL) /*!< Max enumerator value of CONFIGTYPE field. */ + #define ETR_DEVID_CONFIGTYPE_ETB (0x0UL) /*!< (unspecified) */ + #define ETR_DEVID_CONFIGTYPE_ETR (0x1UL) /*!< (unspecified) */ + #define ETR_DEVID_CONFIGTYPE_ETF (0x2UL) /*!< (unspecified) */ + +/* MEMWIDTH @Bits 8..10 : This value indicates the width of the Memory interface databus. */ + #define ETR_DEVID_MEMWIDTH_Pos (8UL) /*!< Position of MEMWIDTH field. */ + #define ETR_DEVID_MEMWIDTH_Msk (0x7UL << ETR_DEVID_MEMWIDTH_Pos) /*!< Bit mask of MEMWIDTH field. */ + #define ETR_DEVID_MEMWIDTH_Min (0x2UL) /*!< Min enumerator value of MEMWIDTH field. */ + #define ETR_DEVID_MEMWIDTH_Max (0x5UL) /*!< Max enumerator value of MEMWIDTH field. */ + #define ETR_DEVID_MEMWIDTH_32BIT (0x2UL) /*!< Memory interface databus is 32 bits wide. */ + #define ETR_DEVID_MEMWIDTH_64BIT (0x3UL) /*!< Memory interface databus is 64 bits wide. */ + #define ETR_DEVID_MEMWIDTH_128BIT (0x4UL) /*!< Memory interface databus is 128 bits wide. */ + #define ETR_DEVID_MEMWIDTH_256BIT (0x5UL) /*!< Memory interface databus is 256 bits wide. */ + +/* WBUF_DEPTH @Bits 11..13 : This value indicates, in powers of two, the number of entries in the Write buffer. Each entry is of + size ATB_DATA_WIDTH. */ + + #define ETR_DEVID_WBUF_DEPTH_Pos (11UL) /*!< Position of WBUF_DEPTH field. */ + #define ETR_DEVID_WBUF_DEPTH_Msk (0x7UL << ETR_DEVID_WBUF_DEPTH_Pos) /*!< Bit mask of WBUF_DEPTH field. */ + #define ETR_DEVID_WBUF_DEPTH_Min (0x2UL) /*!< Min enumerator value of WBUF_DEPTH field. */ + #define ETR_DEVID_WBUF_DEPTH_Max (0x5UL) /*!< Max enumerator value of WBUF_DEPTH field. */ + #define ETR_DEVID_WBUF_DEPTH_4ENTRIES (0x2UL) /*!< Depth of the Write buffer is 4 entries. */ + #define ETR_DEVID_WBUF_DEPTH_8ENTRIES (0x3UL) /*!< Depth of the Write buffer is 8 entries. */ + #define ETR_DEVID_WBUF_DEPTH_16ENTRIES (0x4UL) /*!< Depth of the Write buffer is 16 entries. */ + #define ETR_DEVID_WBUF_DEPTH_32ENTRIES (0x5UL) /*!< Depth of the Write buffer is 32 entries. */ + + +/* ETR_DEVTYPE: Device Type Identifier Register */ + #define ETR_DEVTYPE_ResetValue (0x00000021UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR_TYPE @Bits 0..3 : Major classification grouping for this debug/trace component */ + #define ETR_DEVTYPE_MAJOR_TYPE_Pos (0UL) /*!< Position of MAJOR_TYPE field. */ + #define ETR_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETR_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field. */ + #define ETR_DEVTYPE_MAJOR_TYPE_Min (0x1UL) /*!< Min enumerator value of MAJOR_TYPE field. */ + #define ETR_DEVTYPE_MAJOR_TYPE_Max (0x1UL) /*!< Max enumerator value of MAJOR_TYPE field. */ + #define ETR_DEVTYPE_MAJOR_TYPE_SINK (0x1UL) /*!< This component is a trace sink. */ + +/* SUB_TYPE @Bits 4..7 : Sub-classification within the major category */ + #define ETR_DEVTYPE_SUB_TYPE_Pos (4UL) /*!< Position of SUB_TYPE field. */ + #define ETR_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETR_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field. */ + #define ETR_DEVTYPE_SUB_TYPE_Min (0x2UL) /*!< Min enumerator value of SUB_TYPE field. */ + #define ETR_DEVTYPE_SUB_TYPE_Max (0x2UL) /*!< Max enumerator value of SUB_TYPE field. */ + #define ETR_DEVTYPE_SUB_TYPE (0x2UL) /*!< This component captures the trace data into RAM that can be drained + through APB.*/ + + +/* ETR_PERIPHID4: Peripheral ID4 Register */ + #define ETR_PERIPHID4_ResetValue (0x00000004UL) /*!< Reset value of PERIPHID4 register. */ + +/* JEP106_CONT @Bits 0..3 : JEDEC continuation code indicating the designer of the component (along with the identity code) */ + #define ETR_PERIPHID4_JEP106_CONT_Pos (0UL) /*!< Position of JEP106_CONT field. */ + #define ETR_PERIPHID4_JEP106_CONT_Msk (0xFUL << ETR_PERIPHID4_JEP106_CONT_Pos) /*!< Bit mask of JEP106_CONT field. */ + +/* FOURKB_COUNT @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this + component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then + this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */ + + #define ETR_PERIPHID4_FOURKB_COUNT_Pos (4UL) /*!< Position of FOURKB_COUNT field. */ + #define ETR_PERIPHID4_FOURKB_COUNT_Msk (0xFUL << ETR_PERIPHID4_FOURKB_COUNT_Pos) /*!< Bit mask of FOURKB_COUNT field. */ + + +/* ETR_PERIPHID0: Peripheral ID0 Register */ + #define ETR_PERIPHID0_ResetValue (0x00000061UL) /*!< Reset value of PERIPHID0 register. */ + +/* PART_NUMBER_BITS7TO0 @Bits 0..7 : Bits [7:0] of the component's part number. This is selected by the designer of the + component. */ + + #define ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Pos (0UL) /*!< Position of PART_NUMBER_BITS7TO0 field. */ + #define ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Msk (0xFFUL << ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Pos) /*!< Bit mask of + PART_NUMBER_BITS7TO0 field.*/ + + +/* ETR_PERIPHID1: Peripheral ID1 Register */ + #define ETR_PERIPHID1_ResetValue (0x000000B9UL) /*!< Reset value of PERIPHID1 register. */ + +/* PART_NUMBER_BITS11TO8 @Bits 0..3 : Bits [11:8] of the component's part number. This is selected by the designer of the + component. */ + + #define ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Pos (0UL) /*!< Position of PART_NUMBER_BITS11TO8 field. */ + #define ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Msk (0xFUL << ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Pos) /*!< Bit mask of + PART_NUMBER_BITS11TO8 field.*/ + +/* JEP106_BITS3TO0 @Bits 4..7 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the + continuation code) */ + + #define ETR_PERIPHID1_JEP106_BITS3TO0_Pos (4UL) /*!< Position of JEP106_BITS3TO0 field. */ + #define ETR_PERIPHID1_JEP106_BITS3TO0_Msk (0xFUL << ETR_PERIPHID1_JEP106_BITS3TO0_Pos) /*!< Bit mask of JEP106_BITS3TO0 + field.*/ + + +/* ETR_PERIPHID2: Peripheral ID2 Register */ + #define ETR_PERIPHID2_ResetValue (0x0000001BUL) /*!< Reset value of PERIPHID2 register. */ + +/* JEP106_BITS6TO4 @Bits 0..2 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the + continuation code) */ + + #define ETR_PERIPHID2_JEP106_BITS6TO4_Pos (0UL) /*!< Position of JEP106_BITS6TO4 field. */ + #define ETR_PERIPHID2_JEP106_BITS6TO4_Msk (0x7UL << ETR_PERIPHID2_JEP106_BITS6TO4_Pos) /*!< Bit mask of JEP106_BITS6TO4 + field.*/ + +/* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used */ + #define ETR_PERIPHID2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ + #define ETR_PERIPHID2_JEDEC_Msk (0x1UL << ETR_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ + +/* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This + only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the + exact major/minor revision. */ + + #define ETR_PERIPHID2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ + #define ETR_PERIPHID2_REVISION_Msk (0xFUL << ETR_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field. */ + + +/* ETR_PERIPHID3: Peripheral ID3 Register */ + #define ETR_PERIPHID3_ResetValue (0x00000000UL) /*!< Reset value of PERIPHID3 register. */ + +/* CUSTOMER_MODIFIED @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the + behavior of the component. In most cases this field is zero. */ + + #define ETR_PERIPHID3_CUSTOMER_MODIFIED_Pos (0UL) /*!< Position of CUSTOMER_MODIFIED field. */ + #define ETR_PERIPHID3_CUSTOMER_MODIFIED_Msk (0xFUL << ETR_PERIPHID3_CUSTOMER_MODIFIED_Pos) /*!< Bit mask of CUSTOMER_MODIFIED + field.*/ + +/* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after + implementation. In most cases this field is zero. It is recommended that component designers ensure this + field can be changed by a metal fix if required, for example by driving it from registers that reset to + zero. */ + + #define ETR_PERIPHID3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ + #define ETR_PERIPHID3_REVAND_Msk (0xFUL << ETR_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field. */ + + +/* ETR_COMPID0: Component ID0 Register */ + #define ETR_COMPID0_ResetValue (0x0000000DUL) /*!< Reset value of COMPID0 register. */ + +/* PREAMBLE @Bits 0..7 : Contains bits [7:0] of the component identification */ + #define ETR_COMPID0_PREAMBLE_Pos (0UL) /*!< Position of PREAMBLE field. */ + #define ETR_COMPID0_PREAMBLE_Msk (0xFFUL << ETR_COMPID0_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field. */ + + +/* ETR_COMPID1: Component ID1 Register */ + #define ETR_COMPID1_ResetValue (0x00000090UL) /*!< Reset value of COMPID1 register. */ + +/* PREAMBLE @Bits 0..3 : Contains bits [11:8] of the component identification */ + #define ETR_COMPID1_PREAMBLE_Pos (0UL) /*!< Position of PREAMBLE field. */ + #define ETR_COMPID1_PREAMBLE_Msk (0xFUL << ETR_COMPID1_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field. */ + +/* CLASS @Bits 4..7 : Class of the component. E.g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component + identification. */ + + #define ETR_COMPID1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ + #define ETR_COMPID1_CLASS_Msk (0xFUL << ETR_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field. */ + + +/* ETR_COMPID2: Component ID2 Register */ + #define ETR_COMPID2_ResetValue (0x00000005UL) /*!< Reset value of COMPID2 register. */ + +/* PREAMBLE @Bits 0..7 : Contains bits [23:16] of the component identification */ + #define ETR_COMPID2_PREAMBLE_Pos (0UL) /*!< Position of PREAMBLE field. */ + #define ETR_COMPID2_PREAMBLE_Msk (0xFFUL << ETR_COMPID2_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field. */ + + +/* ETR_COMPID3: Component ID3 Register */ + #define ETR_COMPID3_ResetValue (0x000000B1UL) /*!< Reset value of COMPID3 register. */ + +/* PREAMBLE @Bits 0..7 : Contains bits [31:24] of the component identification */ + #define ETR_COMPID3_PREAMBLE_Pos (0UL) /*!< Position of PREAMBLE field. */ + #define ETR_COMPID3_PREAMBLE_Msk (0xFFUL << ETR_COMPID3_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ EXMIF ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct EXMIF_EXTCONF1 ================================================== */ +/** + * @brief EXTCONF1 [EXMIF_EXTCONF1] Configuration for external memory device 1. + */ +typedef struct { + __IOM uint32_t OFFSET; /*!< (@ 0x00000000) Address offset for external memory device 1. */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Upper address range for external memory device 1. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000010) Enable or disable external memory access. */ +} NRF_EXMIF_EXTCONF1_Type; /*!< Size = 20 (0x014) */ + +/* EXMIF_EXTCONF1_OFFSET: Address offset for external memory device 1. */ + #define EXMIF_EXTCONF1_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register. */ + +/* OFFSET @Bits 0..31 : External memory Offset. */ + #define EXMIF_EXTCONF1_OFFSET_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define EXMIF_EXTCONF1_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF1_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + #define EXMIF_EXTCONF1_OFFSET_OFFSET_Min (0x00000000UL) /*!< Min value of OFFSET field. */ + #define EXMIF_EXTCONF1_OFFSET_OFFSET_Max (0xFFFFFFFFUL) /*!< Max size of OFFSET field. */ + + +/* EXMIF_EXTCONF1_SIZE: Upper address range for external memory device 1. */ + #define EXMIF_EXTCONF1_SIZE_ResetValue (0x0FFFFFFFUL) /*!< Reset value of SIZE register. */ + +/* SIZE @Bits 0..31 : Upper limit address. */ + #define EXMIF_EXTCONF1_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ + #define EXMIF_EXTCONF1_SIZE_SIZE_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF1_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + #define EXMIF_EXTCONF1_SIZE_SIZE_Min (0x00000000UL) /*!< Min value of SIZE field. */ + #define EXMIF_EXTCONF1_SIZE_SIZE_Max (0xFFFFFFFFUL) /*!< Max size of SIZE field. */ + + +/* EXMIF_EXTCONF1_ENABLE: Enable or disable external memory access. */ + #define EXMIF_EXTCONF1_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable external memory access from AXI interface. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Msk (0x1UL << EXMIF_EXTCONF1_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable external memory. */ + #define EXMIF_EXTCONF1_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable external memory. */ + + + +/* ================================================== Struct EXMIF_EXTCONF2 ================================================== */ +/** + * @brief EXTCONF2 [EXMIF_EXTCONF2] Configuration for external memory device 2. + */ +typedef struct { + __IOM uint32_t OFFSET; /*!< (@ 0x00000000) Address offset for external memory device 2. */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Upper address range for external memory device 2. */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000018) Enable or disable external memory access. */ +} NRF_EXMIF_EXTCONF2_Type; /*!< Size = 28 (0x01C) */ + +/* EXMIF_EXTCONF2_OFFSET: Address offset for external memory device 2. */ + #define EXMIF_EXTCONF2_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register. */ + +/* OFFSET @Bits 0..31 : External memory Offset. */ + #define EXMIF_EXTCONF2_OFFSET_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define EXMIF_EXTCONF2_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF2_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + #define EXMIF_EXTCONF2_OFFSET_OFFSET_Min (0x00000000UL) /*!< Min value of OFFSET field. */ + #define EXMIF_EXTCONF2_OFFSET_OFFSET_Max (0xFFFFFFFFUL) /*!< Max size of OFFSET field. */ + + +/* EXMIF_EXTCONF2_SIZE: Upper address range for external memory device 2. */ + #define EXMIF_EXTCONF2_SIZE_ResetValue (0x0FFFFFFFUL) /*!< Reset value of SIZE register. */ + +/* SIZE @Bits 0..31 : Upper limit address. */ + #define EXMIF_EXTCONF2_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ + #define EXMIF_EXTCONF2_SIZE_SIZE_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF2_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + #define EXMIF_EXTCONF2_SIZE_SIZE_Min (0x00000000UL) /*!< Min value of SIZE field. */ + #define EXMIF_EXTCONF2_SIZE_SIZE_Max (0xFFFFFFFFUL) /*!< Max size of SIZE field. */ + + +/* EXMIF_EXTCONF2_ENABLE: Enable or disable external memory access. */ + #define EXMIF_EXTCONF2_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable external memory access from AXI interface. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Msk (0x1UL << EXMIF_EXTCONF2_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable external memory. */ + #define EXMIF_EXTCONF2_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable external memory. */ + + + +/* ============================================== Struct EXMIF_CORE_SSICADDRESS ============================================== */ +/** + * @brief SSICADDRESS [EXMIF_CORE_SSICADDRESS] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) This register controls the serial data transfer. */ + __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) This register exists only when the DWC_ssi is + configured as a master device.*/ + __IOM uint32_t SSIENR; /*!< (@ 0x00000008) This register enables and disables the DWC_ssi. */ + __IOM uint32_t MWCR; /*!< (@ 0x0000000C) This register controls the direction of the data word + for the half-duplex Microwire serial protocol.*/ + __IOM uint32_t SER; /*!< (@ 0x00000010) This register is valid only when the DWC_ssi is + configured as a master device.*/ + __IOM uint32_t BAUDR; /*!< (@ 0x00000014) This register is valid only when the DWC_ssi is + configured as a master device.*/ + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) This register controls the threshold value for the + transmit FIFO memory..*/ + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) This register controls the threshold value for the + receive FIFO memory..*/ + __IOM uint32_t TXFLR; /*!< (@ 0x00000020) This register contains the number of valid data entries + in the transmit FIFO memory.*/ + __IOM uint32_t RXFLR; /*!< (@ 0x00000024) This register contains the number of valid data entries + in the receive FIFO memory.*/ + __IOM uint32_t SR; /*!< (@ 0x00000028) This is a read-only register used to indicate the + current transfer status, FIFO status, and any + transmission/reception errors that may have occurred.*/ + __IOM uint32_t IMR; /*!< (@ 0x0000002C) This read/write register masks or enables all + interrupts generated by the DWC_ssi.*/ + __IOM uint32_t ISR; /*!< (@ 0x00000030) This register reports the status of the DWC_ssi + interrupts after they have been masked.*/ + __IOM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + __IOM uint32_t TXEICR; /*!< (@ 0x00000038) Transmit FIFO Error Interrupt Clear Register */ + __IOM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */ + __IOM uint32_t RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register */ + __IOM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ + __IOM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t IDR; /*!< (@ 0x00000058) This register contains the peripherals identification + code, which is written into the register at + configuration time using coreConsultant.*/ + __IOM uint32_t SSICVERSIONID; /*!< (@ 0x0000005C) This read-only register stores the specific DWC_ssi + component version.*/ + __IOM uint32_t DR[36]; /*!< (@ 0x00000060) The DWC_ssi data register is a 32-bit read/write buffer + for the transmit/receive FIFOs.*/ + __IOM uint32_t RXSAMPLEDELAY; /*!< (@ 0x000000F0) This register is only valid when the DWC_ssi is + configured with rxd sample delay logic + (SSIC_HAS_RX_SAMPLE_DELAY==1).*/ + __IOM uint32_t SPICTRLR0; /*!< (@ 0x000000F4) This register is used to control the serial data + transfer in enhanced SPI mode of operation.*/ + __IOM uint32_t DDRDRIVEEDGE; /*!< (@ 0x000000F8) This Register is valid only when SSIC_HAS_DDR is equal + to 1.*/ + __IOM uint32_t XIPMODEBITS; /*!< (@ 0x000000FC) This register carries the mode bits which are sent in + the XIP mode of operation after address phase.*/ +} NRF_EXMIF_CORE_SSICADDRESS_Type; /*!< Size = 256 (0x100) */ + +/* EXMIF_CORE_SSICADDRESS_CTRLR0: This register controls the serial data transfer. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_ResetValue (0x00004007UL) /*!< Reset value of CTRLR0 register. */ + +/* DFS @Bits 0..4 : Data Frame Size. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Pos (0UL) /*!< Position of DFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Pos) /*!< Bit mask of DFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Min (0x0UL) /*!< Min enumerator value of DFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Max (0x1FUL) /*!< Max enumerator value of DFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_01_BIT (0x00UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_02_BIT (0x01UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_03_BIT (0x02UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_04_BIT (0x03UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_05_BIT (0x04UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_06_BIT (0x05UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_07_BIT (0x06UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_08_BIT (0x07UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_09_BIT (0x08UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_10_BIT (0x09UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_11_BIT (0x0AUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_12_BIT (0x0BUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_13_BIT (0x0CUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_14_BIT (0x0DUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_15_BIT (0x0EUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_16_BIT (0x0FUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_17_BIT (0x10UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_18_BIT (0x11UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_19_BIT (0x12UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_20_BIT (0x13UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_21_BIT (0x14UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_22_BIT (0x15UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_23_BIT (0x16UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_24_BIT (0x17UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_25_BIT (0x18UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_26_BIT (0x19UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_27_BIT (0x1AUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_28_BIT (0x1BUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_29_BIT (0x1CUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_30_BIT (0x1DUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_31_BIT (0x1EUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_32_BIT (0x1FUL) /*!< (unspecified) */ + +/* FRF @Bits 6..7 : Frame Format. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Pos (6UL) /*!< Position of FRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Pos) /*!< Bit mask of FRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Min (0x0UL) /*!< Min enumerator value of FRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Max (0x2UL) /*!< Max enumerator value of FRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_SPI (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_SSP (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_MICROWIRE (0x2UL) /*!< (unspecified) */ + +/* SCPH @Bit 8 : Serial Clock Phase. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Pos (8UL) /*!< Position of SCPH field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Pos) /*!< Bit mask of SCPH field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Min (0x0UL) /*!< Min enumerator value of SCPH field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Max (0x1UL) /*!< Max enumerator value of SCPH field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_MIDDLE_BIT (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_START_BIT (0x1UL) /*!< (unspecified) */ + +/* SCPOL @Bit 9 : Serial Clock Polarity. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Pos (9UL) /*!< Position of SCPOL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Pos) /*!< Bit mask of SCPOL + field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Min (0x0UL) /*!< Min enumerator value of SCPOL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Max (0x1UL) /*!< Max enumerator value of SCPOL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_INACTIVE_HIGH (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_INACTIVE_LOW (0x1UL) /*!< (unspecified) */ + +/* TMOD @Bits 10..11 : Transfer Mode. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Pos (10UL) /*!< Position of TMOD field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Pos) /*!< Bit mask of TMOD field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Min (0x0UL) /*!< Min enumerator value of TMOD field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Max (0x3UL) /*!< Max enumerator value of TMOD field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_TX_AND_RX (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_TX_ONLY (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_RX_ONLY (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_EEPROM_READ (0x3UL) /*!< (unspecified) */ + +/* SLVOE @Bit 12 : Slave Output Enable. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Pos (12UL) /*!< Position of SLVOE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Pos) /*!< Bit mask of SLVOE + field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Min (0x0UL) /*!< Min enumerator value of SLVOE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Max (0x1UL) /*!< Max enumerator value of SLVOE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_ENABLED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_DISABLED (0x1UL) /*!< (unspecified) */ + +/* SRL @Bit 13 : Shift Register Loop. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Pos (13UL) /*!< Position of SRL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Pos) /*!< Bit mask of SRL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Min (0x0UL) /*!< Min enumerator value of SRL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Max (0x1UL) /*!< Max enumerator value of SRL field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_NORMAL_MODE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_TESTING_MODE (0x1UL) /*!< (unspecified) */ + +/* SSTE @Bit 14 : Slave Select Toggle Enable. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Pos (14UL) /*!< Position of SSTE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Pos) /*!< Bit mask of SSTE field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Min (0x0UL) /*!< Min enumerator value of SSTE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Max (0x1UL) /*!< Max enumerator value of SSTE field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_TOGGLE_DISABLE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_TOGGLE_EN (0x1UL) /*!< (unspecified) */ + +/* CFS @Bits 16..19 : Control Frame Size. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Pos (16UL) /*!< Position of CFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Msk (0xFUL << EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Pos) /*!< Bit mask of CFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Min (0x0UL) /*!< Min enumerator value of CFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Max (0xFUL) /*!< Max enumerator value of CFS field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_01_BIT (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_02_BIT (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_03_BIT (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_04_BIT (0x3UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_05_BIT (0x4UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_06_BIT (0x5UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_07_BIT (0x6UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_08_BIT (0x7UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_09_BIT (0x8UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_10_BIT (0x9UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_11_BIT (0xAUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_12_BIT (0xBUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_13_BIT (0xCUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_14_BIT (0xDUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_15_BIT (0xEUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_16_BIT (0xFUL) /*!< (unspecified) */ + +/* SPIFRF @Bits 22..23 : SPI Frame Format */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Pos (22UL) /*!< Position of SPIFRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Pos) /*!< Bit mask of SPIFRF + field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Min (0x0UL) /*!< Min enumerator value of SPIFRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Max (0x3UL) /*!< Max enumerator value of SPIFRF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_STANDARD (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_DUAL (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_QUAD (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_OCTAL (0x3UL) /*!< (unspecified) */ + +/* SPIHYPERBUSEN @Bit 24 : SPI Hyperbus Frame format enable. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Pos (24UL) /*!< Position of SPIHYPERBUSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Pos) /*!< Bit + mask of SPIHYPERBUSEN field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Min (0x0UL) /*!< Min enumerator value of SPIHYPERBUSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Max (0x1UL) /*!< Max enumerator value of SPIHYPERBUSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_DISABLE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_ENABLE (0x1UL) /*!< (unspecified) */ + +/* SPIDWSEN @Bit 25 : Enable Dynamic wait states in SPI mode of operation. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Pos (25UL) /*!< Position of SPIDWSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Pos) /*!< Bit mask of + SPIDWSEN field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Min (0x0UL) /*!< Min enumerator value of SPIDWSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Max (0x1UL) /*!< Max enumerator value of SPIDWSEN field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_DISABLE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_ENABLE (0x1UL) /*!< (unspecified) */ + +/* SSIISMST @Bit 31 : This field selects if DWC_ssi is working in Master or Slave mode */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Pos (31UL) /*!< Position of SSIISMST field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Pos) /*!< Bit mask of + SSIISMST field.*/ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Min (0x0UL) /*!< Min enumerator value of SSIISMST field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Max (0x1UL) /*!< Max enumerator value of SSIISMST field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_SLAVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_MASTER (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_CTRLR1: This register exists only when the DWC_ssi is configured as a master device. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR1_ResetValue (0x00000000UL) /*!< Reset value of CTRLR1 register. */ + +/* NDF @Bits 0..15 : Number of Data Frames. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Pos (0UL) /*!< Position of NDF field. */ + #define EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Pos) /*!< Bit mask of NDF field.*/ + + +/* EXMIF_CORE_SSICADDRESS_SSIENR: This register enables and disables the DWC_ssi. */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_ResetValue (0x00000000UL) /*!< Reset value of SSIENR register. */ + +/* SSICEN @Bit 0 : SSI Enable. */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Pos (0UL) /*!< Position of SSICEN field. */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Pos) /*!< Bit mask of SSICEN + field.*/ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Min (0x0UL) /*!< Min enumerator value of SSICEN field. */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Max (0x1UL) /*!< Max enumerator value of SSICEN field. */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_DISABLE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_MWCR: This register controls the direction of the data word for the half-duplex Microwire serial + protocol. */ + + #define EXMIF_CORE_SSICADDRESS_MWCR_ResetValue (0x00000000UL) /*!< Reset value of MWCR register. */ + +/* MWMOD @Bit 0 : Microwire Transfer Mode. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Pos (0UL) /*!< Position of MWMOD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Pos) /*!< Bit mask of MWMOD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Min (0x0UL) /*!< Min enumerator value of MWMOD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Max (0x1UL) /*!< Max enumerator value of MWMOD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_NON_SEQUENTIAL (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_SEQUENTIAL (0x1UL) /*!< (unspecified) */ + +/* MDD @Bit 1 : Microwire Control. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Pos (1UL) /*!< Position of MDD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MDD_Pos) /*!< Bit mask of MDD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Min (0x0UL) /*!< Min enumerator value of MDD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Max (0x1UL) /*!< Max enumerator value of MDD field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_RECEIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_TRANSMIT (0x1UL) /*!< (unspecified) */ + +/* MHS @Bit 2 : Microwire Handshaking. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Pos (2UL) /*!< Position of MHS field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MHS_Pos) /*!< Bit mask of MHS field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Min (0x0UL) /*!< Min enumerator value of MHS field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Max (0x1UL) /*!< Max enumerator value of MHS field. */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_DISABLE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_SER: This register is valid only when the DWC_ssi is configured as a master device. */ + #define EXMIF_CORE_SSICADDRESS_SER_ResetValue (0x00000000UL) /*!< Reset value of SER register. */ + +/* SER @Bits 0..1 : Slave Select Enable Flag. */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_Pos (0UL) /*!< Position of SER field. */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SER_SER_Pos) /*!< Bit mask of SER field. */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_Min (0x0UL) /*!< Min enumerator value of SER field. */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_Max (0x1UL) /*!< Max enumerator value of SER field. */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_NOTSELECTED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SER_SER_SELECTED (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_BAUDR: This register is valid only when the DWC_ssi is configured as a master device. */ + #define EXMIF_CORE_SSICADDRESS_BAUDR_ResetValue (0x00000000UL) /*!< Reset value of BAUDR register. */ + +/* SCKDV @Bits 1..15 : SSI Clock Divider. */ + #define EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Pos (1UL) /*!< Position of SCKDV field. */ + #define EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Msk (0x7FFFUL << EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Pos) /*!< Bit mask of SCKDV + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_TXFTLR: This register controls the threshold value for the transmit FIFO memory.. */ + #define EXMIF_CORE_SSICADDRESS_TXFTLR_ResetValue (0x00000000UL) /*!< Reset value of TXFTLR register. */ + +/* TFT @Bits 0..4 : Transmit FIFO Threshold. */ + #define EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Pos (0UL) /*!< Position of TFT field. */ + #define EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Pos) /*!< Bit mask of TFT field. */ + +/* TXFTHR @Bits 16..20 : Transfer start FIFO level. */ + #define EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Pos (16UL) /*!< Position of TXFTHR field. */ + #define EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Pos) /*!< Bit mask of TXFTHR + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_RXFTLR: This register controls the threshold value for the receive FIFO memory.. */ + #define EXMIF_CORE_SSICADDRESS_RXFTLR_ResetValue (0x00000000UL) /*!< Reset value of RXFTLR register. */ + +/* RFT @Bits 0..4 : Receive FIFO Threshold. */ + #define EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Pos (0UL) /*!< Position of RFT field. */ + #define EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Pos) /*!< Bit mask of RFT field. */ + + +/* EXMIF_CORE_SSICADDRESS_TXFLR: This register contains the number of valid data entries in the transmit FIFO memory. */ + #define EXMIF_CORE_SSICADDRESS_TXFLR_ResetValue (0x00000000UL) /*!< Reset value of TXFLR register. */ + +/* TXTFL @Bits 0..5 : Transmit FIFO Level. */ + #define EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Pos (0UL) /*!< Position of TXTFL field. */ + #define EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Msk (0x3FUL << EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Pos) /*!< Bit mask of TXTFL + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_RXFLR: This register contains the number of valid data entries in the receive FIFO memory. */ + #define EXMIF_CORE_SSICADDRESS_RXFLR_ResetValue (0x00000000UL) /*!< Reset value of RXFLR register. */ + +/* RXTFL @Bits 0..5 : Receive FIFO Level. */ + #define EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Pos (0UL) /*!< Position of RXTFL field. */ + #define EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Msk (0x3FUL << EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Pos) /*!< Bit mask of RXTFL + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_SR: This is a read-only register used to indicate the current transfer status, FIFO status, and any + transmission/reception errors that may have occurred. */ + + #define EXMIF_CORE_SSICADDRESS_SR_ResetValue (0x00000006UL) /*!< Reset value of SR register. */ + +/* BUSY @Bit 0 : SSI Busy Flag. */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Pos (0UL) /*!< Position of BUSY field. */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_BUSY_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* TFNF @Bit 1 : Transmit FIFO Not Full. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Pos (1UL) /*!< Position of TFNF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TFNF_Pos) /*!< Bit mask of TFNF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Min (0x0UL) /*!< Min enumerator value of TFNF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Max (0x1UL) /*!< Max enumerator value of TFNF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_FULL (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_TFNF_NOT_FULL (0x1UL) /*!< (unspecified) */ + +/* TFE @Bit 2 : Transmit FIFO Empty. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_Pos (2UL) /*!< Position of TFE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TFE_Pos) /*!< Bit mask of TFE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_Min (0x0UL) /*!< Min enumerator value of TFE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_Max (0x1UL) /*!< Max enumerator value of TFE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_NOT_EMPTY (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_TFE_EMPTY (0x1UL) /*!< (unspecified) */ + +/* RFNE @Bit 3 : Receive FIFO Not Empty. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Pos (3UL) /*!< Position of RFNE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_RFNE_Pos) /*!< Bit mask of RFNE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Min (0x0UL) /*!< Min enumerator value of RFNE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Max (0x1UL) /*!< Max enumerator value of RFNE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_EMPTY (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_RFNE_NOT_EMPTY (0x1UL) /*!< (unspecified) */ + +/* RFF @Bit 4 : Receive FIFO Full. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_Pos (4UL) /*!< Position of RFF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_RFF_Pos) /*!< Bit mask of RFF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_Min (0x0UL) /*!< Min enumerator value of RFF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_Max (0x1UL) /*!< Max enumerator value of RFF field. */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_NOT_FULL (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_RFF_FULL (0x1UL) /*!< (unspecified) */ + +/* TXE @Bit 5 : Transmission Error. */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_Pos (5UL) /*!< Position of TXE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TXE_Pos) /*!< Bit mask of TXE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_Min (0x0UL) /*!< Min enumerator value of TXE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_Max (0x1UL) /*!< Max enumerator value of TXE field. */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_NO_ERROR (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_TXE_TX_ERROR (0x1UL) /*!< (unspecified) */ + +/* DCOL @Bit 6 : Data Collision Error. */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Pos (6UL) /*!< Position of DCOL field. */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_DCOL_Pos) /*!< Bit mask of DCOL field. */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Min (0x0UL) /*!< Min enumerator value of DCOL field. */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Max (0x1UL) /*!< Max enumerator value of DCOL field. */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_NO_ERROR_CONDITION (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SR_DCOL_TX_COLLISION_ERROR (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_IMR: This read/write register masks or enables all interrupts generated by the DWC_ssi. */ + #define EXMIF_CORE_SSICADDRESS_IMR_ResetValue (0x000000FFUL) /*!< Reset value of IMR register. */ + +/* TXEIM @Bit 0 : Transmit FIFO Empty Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Pos (0UL) /*!< Position of TXEIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Pos) /*!< Bit mask of TXEIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Min (0x0UL) /*!< Min enumerator value of TXEIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Max (0x1UL) /*!< Max enumerator value of TXEIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* TXOIM @Bit 1 : Transmit FIFO Overflow Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Pos (1UL) /*!< Position of TXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Pos) /*!< Bit mask of TXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Min (0x0UL) /*!< Min enumerator value of TXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Max (0x1UL) /*!< Max enumerator value of TXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* RXUIM @Bit 2 : Receive FIFO Underflow Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Pos (2UL) /*!< Position of RXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Pos) /*!< Bit mask of RXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Min (0x0UL) /*!< Min enumerator value of RXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Max (0x1UL) /*!< Max enumerator value of RXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* RXOIM @Bit 3 : Receive FIFO Overflow Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Pos (3UL) /*!< Position of RXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Pos) /*!< Bit mask of RXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Min (0x0UL) /*!< Min enumerator value of RXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Max (0x1UL) /*!< Max enumerator value of RXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* RXFIM @Bit 4 : Receive FIFO Full Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Pos (4UL) /*!< Position of RXFIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Pos) /*!< Bit mask of RXFIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Min (0x0UL) /*!< Min enumerator value of RXFIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Max (0x1UL) /*!< Max enumerator value of RXFIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_MASKED (0x0UL) /*!< ssi_rxf_intr interrupt is masked */ + #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_UNMASKED (0x1UL) /*!< ssi_rxf_intr interrupt is not masked */ + +/* MSTIM @Bit 5 : Multi-Master Contention Interrupt Mask. */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Pos (5UL) /*!< Position of MSTIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Pos) /*!< Bit mask of MSTIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Min (0x0UL) /*!< Min enumerator value of MSTIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Max (0x1UL) /*!< Max enumerator value of MSTIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* XRXOIM @Bit 6 : XIP Receive FIFO Overflow Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Pos (6UL) /*!< Position of XRXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Pos) /*!< Bit mask of XRXOIM field.*/ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Min (0x0UL) /*!< Min enumerator value of XRXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Max (0x1UL) /*!< Max enumerator value of XRXOIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* TXUIM @Bit 7 : Transmit FIFO Underflow Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Pos (7UL) /*!< Position of TXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Pos) /*!< Bit mask of TXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Min (0x0UL) /*!< Min enumerator value of TXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Max (0x1UL) /*!< Max enumerator value of TXUIM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_UNMASKED (0x1UL) /*!< (unspecified) */ + +/* DONEM @Bit 11 : SSI Done Interrupt Mask */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Pos (11UL) /*!< Position of DONEM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_DONEM_Pos) /*!< Bit mask of DONEM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Min (0x0UL) /*!< Min enumerator value of DONEM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Max (0x1UL) /*!< Max enumerator value of DONEM field. */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_MASKED (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_UNMASKED (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_ISR: This register reports the status of the DWC_ssi interrupts after they have been masked. */ + #define EXMIF_CORE_SSICADDRESS_ISR_ResetValue (0x00000000UL) /*!< Reset value of ISR register. */ + +/* TXEIS @Bit 0 : Transmit FIFO Empty Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Pos (0UL) /*!< Position of TXEIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Pos) /*!< Bit mask of TXEIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Min (0x0UL) /*!< Min enumerator value of TXEIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Max (0x1UL) /*!< Max enumerator value of TXEIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* TXOIS @Bit 1 : Transmit FIFO Overflow Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Pos (1UL) /*!< Position of TXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Pos) /*!< Bit mask of TXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Min (0x0UL) /*!< Min enumerator value of TXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Max (0x1UL) /*!< Max enumerator value of TXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXUIS @Bit 2 : Receive FIFO Underflow Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Pos (2UL) /*!< Position of RXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Pos) /*!< Bit mask of RXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Min (0x0UL) /*!< Min enumerator value of RXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Max (0x1UL) /*!< Max enumerator value of RXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXOIS @Bit 3 : Receive FIFO Overflow Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Pos (3UL) /*!< Position of RXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Pos) /*!< Bit mask of RXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Min (0x0UL) /*!< Min enumerator value of RXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Max (0x1UL) /*!< Max enumerator value of RXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXFIS @Bit 4 : Receive FIFO Full Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Pos (4UL) /*!< Position of RXFIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Pos) /*!< Bit mask of RXFIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Min (0x0UL) /*!< Min enumerator value of RXFIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Max (0x1UL) /*!< Max enumerator value of RXFIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* MSTIS @Bit 5 : Multi-Master Contention Interrupt Status. */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Pos (5UL) /*!< Position of MSTIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Pos) /*!< Bit mask of MSTIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Min (0x0UL) /*!< Min enumerator value of MSTIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Max (0x1UL) /*!< Max enumerator value of MSTIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* XRXOIS @Bit 6 : XIP Receive FIFO Overflow Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Pos (6UL) /*!< Position of XRXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Pos) /*!< Bit mask of XRXOIS field.*/ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Min (0x0UL) /*!< Min enumerator value of XRXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Max (0x1UL) /*!< Max enumerator value of XRXOIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* TXUIS @Bit 7 : Transmit FIFO Underflow Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Pos (7UL) /*!< Position of TXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Pos) /*!< Bit mask of TXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Min (0x0UL) /*!< Min enumerator value of TXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Max (0x1UL) /*!< Max enumerator value of TXUIS field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* DONES @Bit 11 : SSI Done Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Pos (11UL) /*!< Position of DONES field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_DONES_Pos) /*!< Bit mask of DONES field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Min (0x0UL) /*!< Min enumerator value of DONES field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Max (0x1UL) /*!< Max enumerator value of DONES field. */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_ISR_DONES_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_RISR: Raw Interrupt Status Register */ + #define EXMIF_CORE_SSICADDRESS_RISR_ResetValue (0x00000000UL) /*!< Reset value of RISR register. */ + +/* TXEIR @Bit 0 : Transmit FIFO Empty Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Pos (0UL) /*!< Position of TXEIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Pos) /*!< Bit mask of TXEIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Min (0x0UL) /*!< Min enumerator value of TXEIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Max (0x1UL) /*!< Max enumerator value of TXEIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* TXOIR @Bit 1 : Transmit FIFO Overflow Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Pos (1UL) /*!< Position of TXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Pos) /*!< Bit mask of TXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Min (0x0UL) /*!< Min enumerator value of TXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Max (0x1UL) /*!< Max enumerator value of TXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXUIR @Bit 2 : Receive FIFO Underflow Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Pos (2UL) /*!< Position of RXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Pos) /*!< Bit mask of RXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Min (0x0UL) /*!< Min enumerator value of RXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Max (0x1UL) /*!< Max enumerator value of RXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXOIR @Bit 3 : Receive FIFO Overflow Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Pos (3UL) /*!< Position of RXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Pos) /*!< Bit mask of RXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Min (0x0UL) /*!< Min enumerator value of RXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Max (0x1UL) /*!< Max enumerator value of RXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RXFIR @Bit 4 : Receive FIFO Full Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Pos (4UL) /*!< Position of RXFIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Pos) /*!< Bit mask of RXFIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Min (0x0UL) /*!< Min enumerator value of RXFIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Max (0x1UL) /*!< Max enumerator value of RXFIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* MSTIR @Bit 5 : Multi-Master Contention Raw Interrupt Status. */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Pos (5UL) /*!< Position of MSTIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Pos) /*!< Bit mask of MSTIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Min (0x0UL) /*!< Min enumerator value of MSTIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Max (0x1UL) /*!< Max enumerator value of MSTIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* XRXOIR @Bit 6 : XIP Receive FIFO Overflow Raw Interrupt Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Pos (6UL) /*!< Position of XRXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Pos) /*!< Bit mask of XRXOIR + field.*/ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Min (0x0UL) /*!< Min enumerator value of XRXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Max (0x1UL) /*!< Max enumerator value of XRXOIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* TXUIR @Bit 7 : Transmit FIFO Underflow Interrupt Raw Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Pos (7UL) /*!< Position of TXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Pos) /*!< Bit mask of TXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Min (0x0UL) /*!< Min enumerator value of TXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Max (0x1UL) /*!< Max enumerator value of TXUIR field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* DONER @Bit 11 : SSI Done Interrupt Raw Status */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Pos (11UL) /*!< Position of DONER field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_DONER_Pos) /*!< Bit mask of DONER field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Min (0x0UL) /*!< Min enumerator value of DONER field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Max (0x1UL) /*!< Max enumerator value of DONER field. */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_INACTIVE (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_RISR_DONER_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* EXMIF_CORE_SSICADDRESS_TXEICR: Transmit FIFO Error Interrupt Clear Register */ + #define EXMIF_CORE_SSICADDRESS_TXEICR_ResetValue (0x00000000UL) /*!< Reset value of TXEICR register. */ + +/* TXEICR @Bit 0 : Clear Transmit FIFO Overflow/Underflow Interrupt. */ + #define EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Pos (0UL) /*!< Position of TXEICR field. */ + #define EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Pos) /*!< Bit mask of TXEICR + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_RXOICR: Receive FIFO Overflow Interrupt Clear Register */ + #define EXMIF_CORE_SSICADDRESS_RXOICR_ResetValue (0x00000000UL) /*!< Reset value of RXOICR register. */ + +/* RXOICR @Bit 0 : Clear Receive FIFO Overflow Interrupt. */ + #define EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Pos (0UL) /*!< Position of RXOICR field. */ + #define EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Pos) /*!< Bit mask of RXOICR + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_RXUICR: Receive FIFO Underflow Interrupt Clear Register */ + #define EXMIF_CORE_SSICADDRESS_RXUICR_ResetValue (0x00000000UL) /*!< Reset value of RXUICR register. */ + +/* RXUICR @Bit 0 : Clear Receive FIFO Underflow Interrupt. */ + #define EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Pos (0UL) /*!< Position of RXUICR field. */ + #define EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Pos) /*!< Bit mask of RXUICR + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_MSTICR: Multi-Master Interrupt Clear Register */ + #define EXMIF_CORE_SSICADDRESS_MSTICR_ResetValue (0x00000000UL) /*!< Reset value of MSTICR register. */ + +/* MSTICR @Bit 0 : Clear Multi-Master Contention Interrupt. */ + #define EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Pos (0UL) /*!< Position of MSTICR field. */ + #define EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Pos) /*!< Bit mask of MSTICR + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_ICR: Interrupt Clear Register */ + #define EXMIF_CORE_SSICADDRESS_ICR_ResetValue (0x00000000UL) /*!< Reset value of ICR register. */ + +/* ICR @Bit 0 : Clear Interrupts. */ + #define EXMIF_CORE_SSICADDRESS_ICR_ICR_Pos (0UL) /*!< Position of ICR field. */ + #define EXMIF_CORE_SSICADDRESS_ICR_ICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ICR_ICR_Pos) /*!< Bit mask of ICR field. */ + + +/* EXMIF_CORE_SSICADDRESS_IDR: This register contains the peripherals identification code, which is written into the register at + configuration time using coreConsultant. */ + + #define EXMIF_CORE_SSICADDRESS_IDR_ResetValue (0x00010003UL) /*!< Reset value of IDR register. */ + +/* IDCODE @Bits 0..31 : Identification code. */ + #define EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Pos (0UL) /*!< Position of IDCODE field. */ + #define EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Pos) /*!< Bit mask of IDCODE + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_SSICVERSIONID: This read-only register stores the specific DWC_ssi component version. */ + #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_ResetValue (0x3130332AUL) /*!< Reset value of SSICVERSIONID register. */ + +/* SSICCOMPVERSION @Bits 0..31 : Contains the hex representation of the Synopsys component version. */ + #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Pos (0UL) /*!< Position of SSICCOMPVERSION field. */ + #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Pos) + /*!< Bit mask of SSICCOMPVERSION field.*/ + + +/* EXMIF_CORE_SSICADDRESS_DR: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. */ + #define EXMIF_CORE_SSICADDRESS_DR_MaxCount (36UL) /*!< Max size of DR[36] array. */ + #define EXMIF_CORE_SSICADDRESS_DR_MaxIndex (35UL) /*!< Max index of DR[36] array. */ + #define EXMIF_CORE_SSICADDRESS_DR_MinIndex (0UL) /*!< Min index of DR[36] array. */ + #define EXMIF_CORE_SSICADDRESS_DR_ResetValue (0x00000000UL) /*!< Reset value of DR[36] register. */ + +/* DR @Bits 0..31 : Data Register. */ + #define EXMIF_CORE_SSICADDRESS_DR_DR_Pos (0UL) /*!< Position of DR field. */ + #define EXMIF_CORE_SSICADDRESS_DR_DR_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_DR_DR_Pos) /*!< Bit mask of DR field. */ + + +/* EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY: This register is only valid when the DWC_ssi is configured with rxd sample delay logic + (SSIC_HAS_RX_SAMPLE_DELAY==1). */ + + #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_ResetValue (0x00000000UL) /*!< Reset value of RXSAMPLEDELAY register. */ + +/* RSD @Bits 0..7 : Receive Data (rxd) Sample Delay. */ + #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Pos (0UL) /*!< Position of RSD field. */ + #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Pos) /*!< Bit mask of + RSD field.*/ + +/* SE @Bit 16 : Receive Data (rxd) Sampling Edge. */ + #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Pos (16UL) /*!< Position of SE field. */ + #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Pos) /*!< Bit mask of SE + field.*/ + + +/* EXMIF_CORE_SSICADDRESS_SPICTRLR0: This register is used to control the serial data transfer in enhanced SPI mode of + operation. */ + + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ResetValue (0x00000A00UL) /*!< Reset value of SPICTRLR0 register. */ + +/* TRANSTYPE @Bits 0..1 : Address and instruction transfer format. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Pos (0UL) /*!< Position of TRANSTYPE field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Pos) /*!< Bit mask + of TRANSTYPE field.*/ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Min (0x0UL) /*!< Min enumerator value of TRANSTYPE field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Max (0x3UL) /*!< Max enumerator value of TRANSTYPE field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT1 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT2 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT3 (0x3UL) /*!< (unspecified) */ + +/* ADDRL @Bits 2..5 : This bit defines Length of Address to be transmitted. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Pos (2UL) /*!< Position of ADDRL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Msk (0xFUL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Pos) /*!< Bit mask of + ADDRL field.*/ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Min (0x0UL) /*!< Min enumerator value of ADDRL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Max (0xFUL) /*!< Max enumerator value of ADDRL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L12 (0x3UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L16 (0x4UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L20 (0x5UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L24 (0x6UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L28 (0x7UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L32 (0x8UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L36 (0x9UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L40 (0xAUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L44 (0xBUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L48 (0xCUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L52 (0xDUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L56 (0xEUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L60 (0xFUL) /*!< (unspecified) */ + +/* XIPMDBITEN @Bit 7 : Mode bits enable in XIP mode. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Pos (7UL) /*!< Position of XIPMDBITEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Pos) /*!< Bit + mask of XIPMDBITEN field.*/ + +/* INSTL @Bits 8..9 : Dual/Quad/Octal mode instruction length in bits. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Pos (8UL) /*!< Position of INSTL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Pos) /*!< Bit mask of + INSTL field.*/ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Min (0x0UL) /*!< Min enumerator value of INSTL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Max (0x3UL) /*!< Max enumerator value of INSTL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L16 (0x3UL) /*!< (unspecified) */ + +/* WAITCYCLES @Bits 11..15 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Pos (11UL) /*!< Position of WAITCYCLES field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Pos) /*!< Bit + mask of WAITCYCLES field.*/ + +/* SPIDDREN @Bit 16 : SPI DDR Enable bit. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Pos (16UL) /*!< Position of SPIDDREN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Pos) /*!< Bit mask + of SPIDDREN field.*/ + +/* INSTDDREN @Bit 17 : Instruction DDR Enable bit. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Pos (17UL) /*!< Position of INSTDDREN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Pos) /*!< Bit mask + of INSTDDREN field.*/ + +/* SPIRXDSEN @Bit 18 : Read data strobe enable bit. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Pos (18UL) /*!< Position of SPIRXDSEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Pos) /*!< Bit mask + of SPIRXDSEN field.*/ + +/* XIPDFSHC @Bit 19 : Fix DFS for XIP transfers. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Pos (19UL) /*!< Position of XIPDFSHC field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Pos) /*!< Bit mask + of XIPDFSHC field.*/ + +/* XIPINSTEN @Bit 20 : XIP instruction enable bit. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Pos (20UL) /*!< Position of XIPINSTEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Pos) /*!< Bit mask + of XIPINSTEN field.*/ + +/* SSICXIPCONTXFEREN @Bit 21 : Enable continuous transfer in XIP mode. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Pos (21UL) /*!< Position of SSICXIPCONTXFEREN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Pos) + /*!< Bit mask of SSICXIPCONTXFEREN field.*/ + +/* SPIDMEN @Bit 24 : SPI data mask enable bit. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Pos (24UL) /*!< Position of SPIDMEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Pos) /*!< Bit mask of + SPIDMEN field.*/ + +/* SPIRXDSSIGEN @Bit 25 : Enable rxds signaling during address and command phase of Hyperbus transfer. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Pos (25UL) /*!< Position of SPIRXDSSIGEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Pos) /*!< + Bit mask of SPIRXDSSIGEN field.*/ + +/* XIPMBL @Bits 26..27 : XIP Mode bits length. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Pos (26UL) /*!< Position of XIPMBL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Pos) /*!< Bit mask of + XIPMBL field.*/ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Min (0x0UL) /*!< Min enumerator value of XIPMBL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Max (0x3UL) /*!< Max enumerator value of XIPMBL field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_2 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_16 (0x3UL) /*!< (unspecified) */ + +/* XIPPREFETCHEN @Bit 29 : Enables XIP pre-fetch functionality in DWC_ssi. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Pos (29UL) /*!< Position of XIPPREFETCHEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Pos) /*!< + Bit mask of XIPPREFETCHEN field.*/ + +/* CLKSTRETCHEN @Bit 30 : Enables clock stretching capability in SPI transfers. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Pos (30UL) /*!< Position of CLKSTRETCHEN field. */ + #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Pos) /*!< + Bit mask of CLKSTRETCHEN field.*/ + + +/* EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE: This Register is valid only when SSIC_HAS_DDR is equal to 1. */ + #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_ResetValue (0x00000000UL) /*!< Reset value of DDRDRIVEEDGE register. */ + +/* TDE @Bits 0..7 : TXD Drive edge register which decided the driving edge of transmit data. */ + #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Pos (0UL) /*!< Position of TDE field. */ + #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Pos) /*!< Bit mask of + TDE field.*/ + + +/* EXMIF_CORE_SSICADDRESS_XIPMODEBITS: This register carries the mode bits which are sent in the XIP mode of operation after + address phase. */ + + #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_ResetValue (0x00000000UL) /*!< Reset value of XIPMODEBITS register. */ + +/* XIPMDBITS @Bits 0..15 : XIP mode bits to be sent after address phase of XIP transfer. */ + #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Pos (0UL) /*!< Position of XIPMDBITS field. */ + #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Pos) /*!< + Bit mask of XIPMDBITS field.*/ + + + +/* ============================================ Struct EXMIF_CORE_SSICXIPADDRESS ============================================= */ +/** + * @brief SSICXIPADDRESS [EXMIF_CORE_SSICXIPADDRESS] (unspecified) + */ +typedef struct { + __IOM uint32_t XIPINCRINST; /*!< (@ 0x00000000) This Register is valid only when SSIC_XIP_EN is equal + to 1.*/ + __IOM uint32_t XIPWRAPINST; /*!< (@ 0x00000004) This Register is valid only when SSIC_XIP_EN is equal + to 1.*/ + __IOM uint32_t XIPCTRL; /*!< (@ 0x00000008) This Register is valid only when SSIC_CONCURRENT_XIP_EN + is equal to 1.*/ + __IM uint32_t RESERVED; + __IOM uint32_t XRXOICR; /*!< (@ 0x00000010) XIP Receive FIFO Overflow Interrupt Clear Register */ + __IM uint32_t RESERVED1[11]; + __IOM uint32_t XIPWRITEINCRINST; /*!< (@ 0x00000040) This Register is valid only when both + SSIC_XIP_WRITE_REG_EN is set to 1.*/ + __IOM uint32_t XIPWRITEWRAPINST; /*!< (@ 0x00000044) This Register is valid only when both + SSIC_XIP_WRITE_REG_EN is set to 1.*/ + __IOM uint32_t XIPWRITECTRL; /*!< (@ 0x00000048) This Register is valid only when SSIC_XIP_WRITE_REG_EN + is equal to 1.*/ +} NRF_EXMIF_CORE_SSICXIPADDRESS_Type; /*!< Size = 76 (0x04C) */ + +/* EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST: This Register is valid only when SSIC_XIP_EN is equal to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_ResetValue (0x00000000UL) /*!< Reset value of XIPINCRINST register. */ + +/* INCRINST @Bits 0..15 : XIP INCR transfer opcode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Pos (0UL) /*!< Position of INCRINST field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Pos) + /*!< Bit mask of INCRINST field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST: This Register is valid only when SSIC_XIP_EN is equal to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRAPINST register. */ + +/* WRAPINST @Bits 0..15 : XIP WRAP transfer opcode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Pos (0UL) /*!< Position of WRAPINST field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Pos) + /*!< Bit mask of WRAPINST field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XIPCTRL: This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ResetValue (0x08000401UL) /*!< Reset value of XIPCTRL register. */ + +/* FRF @Bits 0..1 : SPI Frame Format */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Pos (0UL) /*!< Position of FRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Pos) /*!< Bit mask of FRF + field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Min (0x0UL) /*!< Min enumerator value of FRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Max (0x3UL) /*!< Max enumerator value of FRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_RSVD (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_DUAL (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_QUAD (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_OCTAL (0x3UL) /*!< (unspecified) */ + +/* TRANSTYPE @Bits 2..3 : Address and instruction transfer format. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Pos (2UL) /*!< Position of TRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Pos) /*!< Bit + mask of TRANSTYPE field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Min (0x0UL) /*!< Min enumerator value of TRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Max (0x3UL) /*!< Max enumerator value of TRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT1 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT2 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT3 (0x3UL) /*!< (unspecified) */ + +/* ADDRL @Bits 4..7 : This bit defines Length of Address to be transmitted. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Pos (4UL) /*!< Position of ADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Msk (0xFUL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Pos) /*!< Bit mask of + ADDRL field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Min (0x0UL) /*!< Min enumerator value of ADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Max (0xFUL) /*!< Max enumerator value of ADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L12 (0x3UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L16 (0x4UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L20 (0x5UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L24 (0x6UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L28 (0x7UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L32 (0x8UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L36 (0x9UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L40 (0xAUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L44 (0xBUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L48 (0xCUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L52 (0xDUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L56 (0xEUL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L60 (0xFUL) /*!< (unspecified) */ + +/* INSTL @Bits 9..10 : Dual/Quad/Octal mode instruction length in bits. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Pos (9UL) /*!< Position of INSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Pos) /*!< Bit mask of + INSTL field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Min (0x0UL) /*!< Min enumerator value of INSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Max (0x3UL) /*!< Max enumerator value of INSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L16 (0x3UL) /*!< (unspecified) */ + +/* MDBITSEN @Bit 12 : Mode bits enable in XIP mode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Pos (12UL) /*!< Position of MDBITSEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Pos) /*!< Bit mask + of MDBITSEN field.*/ + +/* WAITCYCLES @Bits 13..17 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Pos (13UL) /*!< Position of WAITCYCLES field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Pos) /*!< Bit + mask of WAITCYCLES field.*/ + +/* DFSHC @Bit 18 : Fix DFS for XIP transfers. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Pos (18UL) /*!< Position of DFSHC field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Pos) /*!< Bit mask of + DFSHC field.*/ + +/* DDREN @Bit 19 : SPI DDR Enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Pos (19UL) /*!< Position of DDREN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Pos) /*!< Bit mask of + DDREN field.*/ + +/* INSTDDREN @Bit 20 : Instruction DDR Enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Pos (20UL) /*!< Position of INSTDDREN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Pos) /*!< Bit + mask of INSTDDREN field.*/ + +/* RXDSEN @Bit 21 : Read data strobe enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Pos (21UL) /*!< Position of RXDSEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Pos) /*!< Bit mask of + RXDSEN field.*/ + +/* INSTEN @Bit 22 : XIP instruction enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Pos (22UL) /*!< Position of INSTEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Pos) /*!< Bit mask of + INSTEN field.*/ + +/* CONTXFEREN @Bit 23 : Enable continuous transfer in XIP mode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Pos (23UL) /*!< Position of CONTXFEREN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Pos) /*!< Bit + mask of CONTXFEREN field.*/ + +/* XIPHYPERBUSEN @Bit 24 : SPI Hyperbus Frame format enable for XIP transfers. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Pos (24UL) /*!< Position of XIPHYPERBUSEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Pos) + /*!< Bit mask of XIPHYPERBUSEN field.*/ + +/* RXDSSIGEN @Bit 25 : Enable rxds signaling during address and command phase of Hyperbus transfer. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Pos (25UL) /*!< Position of RXDSSIGEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Pos) /*!< Bit + mask of RXDSSIGEN field.*/ + +/* XIPMBL @Bits 26..27 : XIP Mode bits length. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Pos (26UL) /*!< Position of XIPMBL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Pos) /*!< Bit mask of + XIPMBL field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Min (0x0UL) /*!< Min enumerator value of XIPMBL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Max (0x3UL) /*!< Max enumerator value of XIPMBL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_2 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_16 (0x3UL) /*!< (unspecified) */ + +/* XIPPREFETCHEN @Bit 29 : Enables XIP pre-fetch functionality in DWC_ssi. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Pos (29UL) /*!< Position of XIPPREFETCHEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Pos) + /*!< Bit mask of XIPPREFETCHEN field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XRXOICR: XIP Receive FIFO Overflow Interrupt Clear Register */ + #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_ResetValue (0x00000000UL) /*!< Reset value of XRXOICR register. */ + +/* XRXOICR @Bit 0 : Clear XIP Receive FIFO Overflow Interrupt. */ + #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Pos (0UL) /*!< Position of XRXOICR field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Pos) /*!< Bit mask + of XRXOICR field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST: This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRITEINCRINST register. */ + +/* INCRWRITEINST @Bits 0..15 : XIP Write INCR transfer opcode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Pos (0UL) /*!< Position of INCRWRITEINST field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Pos) + /*!< Bit mask of INCRWRITEINST field.*/ + +/* RSVDINCRINST16TO31 @Bits 16..31 : Reserved bits - Read Only */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Pos (16UL) /*!< Position of RSVDINCRINST16TO31 field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Pos) + /*!< Bit mask of RSVDINCRINST16TO31 field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST: This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRITEWRAPINST register. */ + +/* WRAPWRITEINST @Bits 0..15 : XIP Write WRAP transfer opcode. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Pos (0UL) /*!< Position of WRAPWRITEINST field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Pos) + /*!< Bit mask of WRAPWRITEINST field.*/ + +/* RSVDWRAPINST16TO31 @Bits 16..31 : Reserved bits - Read Only */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Pos (16UL) /*!< Position of RSVDWRAPINST16TO31 field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Pos) + /*!< Bit mask of RSVDWRAPINST16TO31 field.*/ + + +/* EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL: This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_ResetValue (0x00000002UL) /*!< Reset value of XIPWRITECTRL register. */ + +/* WRFRF @Bits 0..1 : SPI Frame Format */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Pos (0UL) /*!< Position of WRFRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Pos) /*!< Bit + mask of WRFRF field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Min (0x0UL) /*!< Min enumerator value of WRFRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Max (0x3UL) /*!< Max enumerator value of WRFRF field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_RSVD (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_DUAL (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_QUAD (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_OCTAL (0x3UL) /*!< (unspecified) */ + +/* WRTRANSTYPE @Bits 2..3 : Address and instruction transfer format. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Pos (2UL) /*!< Position of WRTRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Pos) + /*!< Bit mask of WRTRANSTYPE field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Min (0x0UL) /*!< Min enumerator value of WRTRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Max (0x3UL) /*!< Max enumerator value of WRTRANSTYPE field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT1 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT2 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT3 (0x3UL) /*!< (unspecified) */ + +/* WRADDRL @Bits 4..7 : This bit defines Length of Address to be transmitted. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Pos (4UL) /*!< Position of WRADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Msk (0xFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Pos) /*!< + Bit mask of WRADDRL field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Min (0x0UL) /*!< Min enumerator value of WRADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Max (0x8UL) /*!< Max enumerator value of WRADDRL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L12 (0x3UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L16 (0x4UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L20 (0x5UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L24 (0x6UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L28 (0x7UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L32 (0x8UL) /*!< (unspecified) */ + +/* WRINSTL @Bits 8..9 : Dual/Quad/Octal mode instruction length in bits. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Pos (8UL) /*!< Position of WRINSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Pos) /*!< + Bit mask of WRINSTL field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Min (0x0UL) /*!< Min enumerator value of WRINSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Max (0x3UL) /*!< Max enumerator value of WRINSTL field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L0 (0x0UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L4 (0x1UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L8 (0x2UL) /*!< (unspecified) */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L16 (0x3UL) /*!< (unspecified) */ + +/* WRSPIDDREN @Bit 10 : SPI DDR Enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Pos (10UL) /*!< Position of WRSPIDDREN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Pos) + /*!< Bit mask of WRSPIDDREN field.*/ + +/* WRINSTDDREN @Bit 11 : Instruction DDR Enable bit. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Pos (11UL) /*!< Position of WRINSTDDREN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Pos) + /*!< Bit mask of WRINSTDDREN field.*/ + +/* XIPWRHYPERBUSEN @Bit 12 : SPI Hyperbus Frame format enable for XIP Write transfers. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Pos (12UL) /*!< Position of XIPWRHYPERBUSEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Pos) + /*!< Bit mask of XIPWRHYPERBUSEN field.*/ + +/* XIPWRRXDSSIGEN @Bit 13 : Enable rxds signaling during address and command phase of Hyperbus transfer. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Pos (13UL) /*!< Position of XIPWRRXDSSIGEN field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Pos) + /*!< Bit mask of XIPWRRXDSSIGEN field.*/ + +/* RSVDXIPWRITECTRL14TO15 @Bits 14..15 : Reserved bits - Read Only */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Pos (14UL) /*!< Position of RSVDXIPWRITECTRL14TO15 + field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Pos) + /*!< Bit mask of RSVDXIPWRITECTRL14TO15 field.*/ + +/* XIPWRWAITCYCLES @Bits 16..20 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Pos (16UL) /*!< Position of XIPWRWAITCYCLES field. */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Pos) + /*!< Bit mask of XIPWRWAITCYCLES field.*/ + +/* RSVDXIPWRITECTRL21TO31 @Bits 21..31 : Reserved bits - Read Only */ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Pos (21UL) /*!< Position of RSVDXIPWRITECTRL21TO31 + field.*/ + #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Msk (0x7FFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Pos) + /*!< Bit mask of RSVDXIPWRITECTRL21TO31 field.*/ + + + +/* ==================================================== Struct EXMIF_CORE ==================================================== */ +/** + * @brief CORE [EXMIF_CORE] (unspecified) + */ +typedef struct { + __IOM NRF_EXMIF_CORE_SSICADDRESS_Type SSICADDRESS; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_EXMIF_CORE_SSICXIPADDRESS_Type SSICXIPADDRESS; /*!< (@ 0x00000100) (unspecified) */ +} NRF_EXMIF_CORE_Type; /*!< Size = 332 (0x14C) */ + +/* ====================================================== Struct EXMIF ======================================================= */ +/** + * @brief External Memory Interface + */ + typedef struct { /*!< EXMIF Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start operation. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop operation. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t LOCKEDACCESS; /*!< (@ 0x00000014) Enable or disable locked APB access to serial memory + controller.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t RESET; /*!< (@ 0x0000001C) Reset the external memory. */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_CORE; /*!< (@ 0x00000100) Event indicating that interrupt triggered at EXMIF + core*/ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Event indicating that the START task is completed and + the EXMIF has started.*/ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[60]; + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM NRF_EXMIF_EXTCONF1_Type EXTCONF1; /*!< (@ 0x00000400) Configuration for external memory device 1. */ + struct { + __IM uint32_t RESERVED5[2]; + __IOM NRF_EXMIF_EXTCONF2_Type EXTCONF2; /*!< (@ 0x00000408) Configuration for external memory device 2. */ + }; + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + __IM uint32_t RESERVED6[55]; + __IOM NRF_EXMIF_CORE_Type CORE; /*!< (@ 0x00000500) (unspecified) */ + } NRF_EXMIF_Type; /*!< Size = 1612 (0x64C) */ + +/* EXMIF_TASKS_START: Start operation. */ + #define EXMIF_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start operation. */ + #define EXMIF_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define EXMIF_TASKS_START_TASKS_START_Msk (0x1UL << EXMIF_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define EXMIF_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define EXMIF_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define EXMIF_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* EXMIF_TASKS_STOP: Stop operation. */ + #define EXMIF_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop operation. */ + #define EXMIF_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define EXMIF_TASKS_STOP_TASKS_STOP_Msk (0x1UL << EXMIF_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define EXMIF_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define EXMIF_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define EXMIF_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* EXMIF_LOCKEDACCESS: Enable or disable locked APB access to serial memory controller. */ + #define EXMIF_LOCKEDACCESS_ResetValue (0x00000000UL) /*!< Reset value of LOCKEDACCESS register. */ + +/* ENABLE @Bit 0 : Enable or disable locked APB access to SSI. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Msk (0x1UL << EXMIF_LOCKEDACCESS_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Disabled (0x0UL) /*!< Disable locked APB access. */ + #define EXMIF_LOCKEDACCESS_ENABLE_Enabled (0x1UL) /*!< Enable locked APB access. */ + + +/* EXMIF_RESET: Reset the external memory. */ + #define EXMIF_RESET_ResetValue (0x00000000UL) /*!< Reset value of RESET register. */ + +/* RESET @Bit 0 : (unspecified) */ + #define EXMIF_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ + #define EXMIF_RESET_RESET_Msk (0x1UL << EXMIF_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ + #define EXMIF_RESET_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define EXMIF_RESET_RESET_Max (0x1UL) /*!< Max enumerator value of RESET field. */ + #define EXMIF_RESET_RESET_Clear (0x0UL) /*!< Reset is cleared. */ + #define EXMIF_RESET_RESET_Set (0x1UL) /*!< Reset is set. */ + + +/* EXMIF_EVENTS_CORE: Event indicating that interrupt triggered at EXMIF core */ + #define EXMIF_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE register. */ + +/* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at EXMIF core */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_Pos (0UL) /*!< Position of EVENTS_CORE field. */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << EXMIF_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated */ + #define EXMIF_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated */ + + +/* EXMIF_EVENTS_STARTED: Event indicating that the START task is completed and the EXMIF has started. */ + #define EXMIF_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : Event indicating that the START task is completed and the EXMIF has started. */ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << EXMIF_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define EXMIF_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* EXMIF_INTEN: Enable or disable interrupt */ + #define EXMIF_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CORE @Bit 0 : Enable or disable interrupt for event CORE */ + #define EXMIF_INTEN_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define EXMIF_INTEN_CORE_Msk (0x1UL << EXMIF_INTEN_CORE_Pos) /*!< Bit mask of CORE field. */ + #define EXMIF_INTEN_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define EXMIF_INTEN_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define EXMIF_INTEN_CORE_Disabled (0x0UL) /*!< Disable */ + #define EXMIF_INTEN_CORE_Enabled (0x1UL) /*!< Enable */ + +/* STARTED @Bit 1 : Enable or disable interrupt for event STARTED */ + #define EXMIF_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define EXMIF_INTEN_STARTED_Msk (0x1UL << EXMIF_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define EXMIF_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define EXMIF_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define EXMIF_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define EXMIF_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + + +/* EXMIF_INTENSET: Enable interrupt */ + #define EXMIF_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */ + #define EXMIF_INTENSET_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define EXMIF_INTENSET_CORE_Msk (0x1UL << EXMIF_INTENSET_CORE_Pos) /*!< Bit mask of CORE field. */ + #define EXMIF_INTENSET_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define EXMIF_INTENSET_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define EXMIF_INTENSET_CORE_Set (0x1UL) /*!< Enable */ + #define EXMIF_INTENSET_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define EXMIF_INTENSET_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 1 : Write '1' to enable interrupt for event STARTED */ + #define EXMIF_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define EXMIF_INTENSET_STARTED_Msk (0x1UL << EXMIF_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define EXMIF_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define EXMIF_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define EXMIF_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define EXMIF_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define EXMIF_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* EXMIF_INTENCLR: Disable interrupt */ + #define EXMIF_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */ + #define EXMIF_INTENCLR_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define EXMIF_INTENCLR_CORE_Msk (0x1UL << EXMIF_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field. */ + #define EXMIF_INTENCLR_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define EXMIF_INTENCLR_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define EXMIF_INTENCLR_CORE_Clear (0x1UL) /*!< Disable */ + #define EXMIF_INTENCLR_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define EXMIF_INTENCLR_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 1 : Write '1' to disable interrupt for event STARTED */ + #define EXMIF_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define EXMIF_INTENCLR_STARTED_Msk (0x1UL << EXMIF_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define EXMIF_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define EXMIF_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define EXMIF_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define EXMIF_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define EXMIF_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* EXMIF_INTPEND: Pending interrupts */ + #define EXMIF_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* CORE @Bit 0 : Read pending status of interrupt for event CORE */ + #define EXMIF_INTPEND_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define EXMIF_INTPEND_CORE_Msk (0x1UL << EXMIF_INTPEND_CORE_Pos) /*!< Bit mask of CORE field. */ + #define EXMIF_INTPEND_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define EXMIF_INTPEND_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define EXMIF_INTPEND_CORE_NotPending (0x0UL) /*!< Read: Not pending */ + #define EXMIF_INTPEND_CORE_Pending (0x1UL) /*!< Read: Pending */ + +/* STARTED @Bit 1 : Read pending status of interrupt for event STARTED */ + #define EXMIF_INTPEND_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define EXMIF_INTPEND_STARTED_Msk (0x1UL << EXMIF_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define EXMIF_INTPEND_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define EXMIF_INTPEND_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define EXMIF_INTPEND_STARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define EXMIF_INTPEND_STARTED_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct FICR_BLE ===================================================== */ +/** + * @brief BLE [FICR_BLE] (unspecified) + */ +typedef struct { + __IM uint32_t ADDRTYPE; /*!< (@ 0x00000000) Device address type. */ + __IM uint32_t ADDR[2]; /*!< (@ 0x00000004) 48 bit device address. */ + __IM uint32_t ER[4]; /*!< (@ 0x0000000C) Encryption Root. */ + __IM uint32_t IR[4]; /*!< (@ 0x0000001C) Identity Root. */ +} NRF_FICR_BLE_Type; /*!< Size = 44 (0x02C) */ + +/* FICR_BLE_ADDRTYPE: Device address type. */ + #define FICR_BLE_ADDRTYPE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDRTYPE register. */ + +/* TYPE @Bit 0 : Device address type. */ + #define FICR_BLE_ADDRTYPE_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define FICR_BLE_ADDRTYPE_TYPE_Msk (0x1UL << FICR_BLE_ADDRTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define FICR_BLE_ADDRTYPE_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define FICR_BLE_ADDRTYPE_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define FICR_BLE_ADDRTYPE_TYPE_Public (0x0UL) /*!< Public address. */ + #define FICR_BLE_ADDRTYPE_TYPE_Random (0x1UL) /*!< Random address. */ + + +/* FICR_BLE_ADDR: 48 bit device address. */ + #define FICR_BLE_ADDR_MaxCount (2UL) /*!< Max size of ADDR[2] array. */ + #define FICR_BLE_ADDR_MaxIndex (1UL) /*!< Max index of ADDR[2] array. */ + #define FICR_BLE_ADDR_MinIndex (0UL) /*!< Min index of ADDR[2] array. */ + #define FICR_BLE_ADDR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDR[2] register. */ + +/* ADDR @Bits 0..31 : Device address [n]. */ + #define FICR_BLE_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define FICR_BLE_ADDR_ADDR_Msk (0xFFFFFFFFUL << FICR_BLE_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* FICR_BLE_ER: Encryption Root. */ + #define FICR_BLE_ER_MaxCount (4UL) /*!< Max size of ER[4] array. */ + #define FICR_BLE_ER_MaxIndex (3UL) /*!< Max index of ER[4] array. */ + #define FICR_BLE_ER_MinIndex (0UL) /*!< Min index of ER[4] array. */ + #define FICR_BLE_ER_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ER[4] register. */ + +/* ER @Bits 0..31 : Encryption root word [n]. */ + #define FICR_BLE_ER_ER_Pos (0UL) /*!< Position of ER field. */ + #define FICR_BLE_ER_ER_Msk (0xFFFFFFFFUL << FICR_BLE_ER_ER_Pos) /*!< Bit mask of ER field. */ + + +/* FICR_BLE_IR: Identity Root. */ + #define FICR_BLE_IR_MaxCount (4UL) /*!< Max size of IR[4] array. */ + #define FICR_BLE_IR_MaxIndex (3UL) /*!< Max index of IR[4] array. */ + #define FICR_BLE_IR_MinIndex (0UL) /*!< Min index of IR[4] array. */ + #define FICR_BLE_IR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of IR[4] register. */ + +/* IR @Bits 0..31 : Identity root word [n]. */ + #define FICR_BLE_IR_IR_Pos (0UL) /*!< Position of IR field. */ + #define FICR_BLE_IR_IR_Msk (0xFFFFFFFFUL << FICR_BLE_IR_IR_Pos) /*!< Bit mask of IR field. */ + + + +/* ==================================================== Struct FICR_INFO ===================================================== */ +/** + * @brief INFO [FICR_INFO] Device info + */ +typedef struct { + __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ + __IM uint32_t PART; /*!< (@ 0x00000004) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000008) Part Variant, Hardware version and Production + configuration*/ + __IM uint32_t PACKAGE; /*!< (@ 0x0000000C) Package option */ + __IM uint32_t RAM; /*!< (@ 0x00000010) RAM variant */ + __IM uint32_t MRAM; /*!< (@ 0x00000014) MRAM variant */ + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000018) Code memory page size in bytes */ + __IM uint32_t CODESIZE; /*!< (@ 0x0000001C) Code memory size */ + __IM uint32_t DEVICETYPE; /*!< (@ 0x00000020) Device type */ +} NRF_FICR_INFO_Type; /*!< Size = 36 (0x024) */ + +/* FICR_INFO_CONFIGID: Configuration identifier */ + #define FICR_INFO_CONFIGID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIGID register. */ + +/* HWID @Bits 0..15 : Identification number for the HW */ + #define FICR_INFO_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ + #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ + + +/* FICR_INFO_PART: Part code */ + #define FICR_INFO_PART_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PART register. */ + +/* PART @Bits 0..31 : Part code */ + #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ + #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ + #define FICR_INFO_PART_PART_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PART field. */ + #define FICR_INFO_PART_PART_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PART field. */ + #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_VARIANT: Part Variant, Hardware version and Production configuration */ + #define FICR_INFO_VARIANT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VARIANT register. */ + +/* VARIANT @Bits 0..31 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ + #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Min (0xFFFFFFFFUL) /*!< Min enumerator value of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Max (0xFFFFFFFFUL) /*!< Max enumerator value of VARIANT field. */ + #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_PACKAGE: Package option */ + #define FICR_INFO_PACKAGE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PACKAGE register. */ + +/* PACKAGE @Bits 0..31 : Package option */ + #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PACKAGE field. */ + #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_RAM: RAM variant */ + #define FICR_INFO_RAM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RAM register. */ + +/* RAM @Bits 0..31 : RAM variant */ + #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ + #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ + #define FICR_INFO_RAM_RAM_Min (0xFFFFFFFFUL) /*!< Min enumerator value of RAM field. */ + #define FICR_INFO_RAM_RAM_Max (0xFFFFFFFFUL) /*!< Max enumerator value of RAM field. */ + #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_MRAM: MRAM variant */ + #define FICR_INFO_MRAM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MRAM register. */ + +/* MRAM @Bits 0..31 : MRAM variant */ + #define FICR_INFO_MRAM_MRAM_Pos (0UL) /*!< Position of MRAM field. */ + #define FICR_INFO_MRAM_MRAM_Msk (0xFFFFFFFFUL << FICR_INFO_MRAM_MRAM_Pos) /*!< Bit mask of MRAM field. */ + #define FICR_INFO_MRAM_MRAM_Min (0xFFFFFFFFUL) /*!< Min enumerator value of MRAM field. */ + #define FICR_INFO_MRAM_MRAM_Max (0xFFFFFFFFUL) /*!< Max enumerator value of MRAM field. */ + #define FICR_INFO_MRAM_MRAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_CODEPAGESIZE: Code memory page size in bytes */ + #define FICR_INFO_CODEPAGESIZE_ResetValue (0x00001000UL) /*!< Reset value of CODEPAGESIZE register. */ + +/* CODEPAGESIZE @Bits 0..31 : Code memory page size in bytes */ + #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ + #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of + CODEPAGESIZE field.*/ + #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of CODEPAGESIZE field. */ + #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of CODEPAGESIZE field. */ + #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_CODESIZE: Code memory size */ + #define FICR_INFO_CODESIZE_ResetValue (0x00000100UL) /*!< Reset value of CODESIZE register. */ + +/* CODESIZE @Bits 0..31 : Code memory size in number of pages */ + #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ + #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + #define FICR_INFO_CODESIZE_CODESIZE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of CODESIZE field. */ + #define FICR_INFO_CODESIZE_CODESIZE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of CODESIZE field. */ + #define FICR_INFO_CODESIZE_CODESIZE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + + +/* FICR_INFO_DEVICETYPE: Device type */ + #define FICR_INFO_DEVICETYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVICETYPE register. */ + +/* DEVICETYPE @Bits 0..31 : Device type */ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE + field.*/ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_Min (0x0UL) /*!< Min enumerator value of DEVICETYPE field. */ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of DEVICETYPE field. */ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE */ + #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */ + + + +/* =========================================== Struct FICR_SIPINFO_OVERRIDE_LFOSC ============================================ */ +/** + * @brief LFOSC [FICR_SIPINFO_OVERRIDE_LFOSC] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) LF oscillator configuration. Note. This configuration + overrides corresponding LF oscillator configuration in + BICR when set.*/ + __IOM uint32_t LFXOCONFIG; /*!< (@ 0x00000004) LFXO configuration. Note. This configuration overrides + corresponding LFXO configuration in BICR when set.*/ + __IOM uint32_t LFXOCAL; /*!< (@ 0x00000008) LFXO calibration needed. Must be written to 0xFFFFFFFF + after any modification of the LFXO board circuit, load + capacitance, or crystal swap. Note. This configuration + overrides corresponding LFXO calibration in BICR when + set.*/ + __IOM uint32_t LFRCAUTOCALCONFIG; /*!< (@ 0x0000000C) LFRC autocalibration configuration. Note. This + configuration overrides corresponding LFRC + autocalibration configuration in BICR when set.*/ +} NRF_FICR_SIPINFO_OVERRIDE_LFOSC_Type; /*!< Size = 16 (0x010) */ + +/* FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG: LF oscillator configuration. Note. This configuration overrides corresponding LF + oscillator configuration in BICR when set. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* SRC @Bits 0..3 : LF oscillator source. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Msk (0xFUL << FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Pos) /*!< Bit mask of SRC + field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Max (0xFUL) /*!< Max enumerator value of SRC field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Unconfigured (0xFUL) /*!< LF oscillator source is unconfigured. Default will be + used.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_LFXO (0x0UL) /*!< Use LFXO as source for the LF oscillator. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_LFRC (0x1UL) /*!< Use LFRC as source for the LF oscillator. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_LFLPRC (0x2UL) /*!< Use LFLPRC as source for the LF oscillator. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG_SRC_Synth (0x3UL) /*!< Use LF Synth as source for the LF oscillator. */ + + +/* FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG: LFXO configuration. Note. This configuration overrides corresponding LFXO + configuration in BICR when set. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCONFIG register. */ + +/* ACCURACY @Bits 0..3 : LFXO crystal or external signal accuracy. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Pos (0UL) /*!< Position of ACCURACY field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Msk (0xFUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Pos) + /*!< Bit mask of ACCURACY field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Min (0x0UL) /*!< Min enumerator value of ACCURACY field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Max (0xFUL) /*!< Max enumerator value of ACCURACY field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_Unconfigured (0xFUL) /*!< The accuracy is unconfigured. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_500ppm (0x0UL) /*!< LFXO crystal or external signal has an accuracy of + 500 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_250ppm (0x1UL) /*!< LFXO crystal or external signal has an accuracy of + 250 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_150ppm (0x2UL) /*!< LFXO crystal or external signal has an accuracy of + 150 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_100ppm (0x3UL) /*!< LFXO crystal or external signal has an accuracy of + 100 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_75ppm (0x4UL) /*!< LFXO crystal or external signal has an accuracy of + 75 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_50ppm (0x5UL) /*!< LFXO crystal or external signal has an accuracy of + 50 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_30ppm (0x6UL) /*!< LFXO crystal or external signal has an accuracy of + 30 ppm.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_ACCURACY_20ppm (0x7UL) /*!< LFXO crystal or external signal has an accuracy of + 20 ppm.*/ + +/* MODE @Bits 4..6 : LFXO mode. LFXO will not start unless MODE is configured. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Pos (4UL) /*!< Position of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Msk (0x7UL << FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Pos) /*!< Bit + mask of MODE field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Max (0x7UL) /*!< Max enumerator value of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_Pierce (0x0UL) /*!< LFXO Pierce mode. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_PIXO (0x1UL) /*!< LFXO PIXO mode. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_ExtSine (0x2UL) /*!< LFXO in external sine wave mode. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_MODE_ExtSquare (0x3UL) /*!< LFXO in external square wave mode. */ + +/* LOADCAP @Bits 8..15 : Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Pos (8UL) /*!< Position of LOADCAP field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Msk (0xFFUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Pos) /*!< + Bit mask of LOADCAP field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Min (0x0UL) /*!< Min enumerator value of LOADCAP field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Max (0xFFUL) /*!< Max enumerator value of LOADCAP field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_Unconfigured (0xFFUL) /*!< The built-in load capacitors is + unconfigured. LFXO will not start unless LOADCAP is + configured.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_LOADCAP_External (0x00UL) /*!< Do not use the built-in load capacitors, only + external capacitors will be used.*/ + +/* TIME @Bits 16..27 : LFXO startup time in ms. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Pos (16UL) /*!< Position of TIME field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Msk (0xFFFUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Pos) /*!< Bit + mask of TIME field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Min (0xFFFUL) /*!< Min enumerator value of TIME field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Max (0xFFFUL) /*!< Max enumerator value of TIME field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG_TIME_Unconfigured (0xFFFUL) /*!< Startup time has not been configured. */ + + +/* FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL: LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the + LFXO board circuit, load capacitance, or crystal swap. Note. This configuration + overrides corresponding LFXO calibration in BICR when set. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCAL register. */ + +/* LFXOCAL @Bits 0..31 : LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board + circuit, load capacitance, or crystal swap. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Pos (0UL) /*!< Position of LFXOCAL field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Msk (0xFFFFFFFFUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Pos) /*!< + Bit mask of LFXOCAL field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of LFXOCAL field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of LFXOCAL field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL_LFXOCAL_Calibrate (0xFFFFFFFFUL) /*!< Calibrate the LFXO at startup. */ + + +/* FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG: LFRC autocalibration configuration. Note. This configuration overrides + corresponding LFRC autocalibration configuration in BICR when set. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFRCAUTOCALCONFIG + register.*/ + +/* TEMPINTERVAL @Bits 0..6 : Temperature measurement interval in 0.25 s steps. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos (0UL) /*!< Position of TEMPINTERVAL field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Msk (0x7FUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos) + /*!< Bit mask of TEMPINTERVAL field.*/ + +/* TEMPDELTA @Bits 8..13 : Temperature delta that should trigger a calibration in 0.25 degrees steps. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos (8UL) /*!< Position of TEMPDELTA field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Msk (0x3FUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos) + /*!< Bit mask of TEMPDELTA field.*/ + +/* INTERVALMAXNO @Bits 16..20 : Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature + changes. */ + + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos (16UL) /*!< Position of INTERVALMAXNO field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Msk (0x1FUL << FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos) + /*!< Bit mask of INTERVALMAXNO field.*/ + +/* ENABLE @Bit 31 : LFRC.AUTOCALCONFIG register enable. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Msk (0x1UL << FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos) + /*!< Bit mask of ENABLE field.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Enabled (0x0UL) /*!< LFRC.AUTOCALCONFIG register has been + configured and can be used.*/ + #define FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Disabled (0x1UL) /*!< LFRC.AUTOCALCONFIG register has not been + configured and cannot be used.*/ + + + +/* ========================================== Struct FICR_SIPINFO_OVERRIDE_HFXO64M =========================================== */ +/** + * @brief HFXO64M [FICR_SIPINFO_OVERRIDE_HFXO64M] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) HFXO64M configuration. Note. This configuration + overrides corresponding XO configuration in BICR when + set.*/ + __IM uint32_t RESERVED; +} NRF_FICR_SIPINFO_OVERRIDE_HFXO64M_Type; /*!< Size = 8 (0x008) */ + +/* FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG: HFXO64M configuration. Note. This configuration overrides corresponding XO + configuration in BICR when set. */ + + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* MODE @Bits 0..2 : HFXO64M mode. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Msk (0x7UL << FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Pos) /*!< Bit mask + of MODE field.*/ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Max (0x7UL) /*!< Max enumerator value of MODE field. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Normal (0x0UL) /*!< Normal operating mode. */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_TCXO (0x1UL) /*!< TCXO/bypass mode */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Crystal2 (0x2UL) /*!< Reserved value */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Crystal3 (0x3UL) /*!< Reserved value */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Crystal4 (0x4UL) /*!< Reserved value */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Crystal5 (0x5UL) /*!< Reserved value */ + #define FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG_MODE_Crystal6 (0x6UL) /*!< Reserved value */ + + + +/* ============================================== Struct FICR_SIPINFO_OVERRIDE =============================================== */ +/** + * @brief OVERRIDE [FICR_SIPINFO_OVERRIDE] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_SIPINFO_OVERRIDE_LFOSC_Type LFOSC; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_FICR_SIPINFO_OVERRIDE_HFXO64M_Type HFXO64M; /*!< (@ 0x00000010) (unspecified) */ +} NRF_FICR_SIPINFO_OVERRIDE_Type; /*!< Size = 24 (0x018) */ + + +/* =================================================== Struct FICR_SIPINFO =================================================== */ +/** + * @brief SIPINFO [FICR_SIPINFO] SIP-specific device info + */ +typedef struct { + __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ + __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) SIP hardware revision, encoded in ASCII, ex B0A or B1A*/ + __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */ + __IM uint32_t PMICVERSION; /*!< (@ 0x0000000C) PMIC version */ + __IM uint8_t TESTSITE[4]; /*!< (@ 0x00000010) Test site, in ascii */ + __IM uint32_t LOT; /*!< (@ 0x00000014) Lot number + test index in hex format (number digits + 0-9).*/ + __IM uint8_t TESTPROGRAMID[4]; /*!< (@ 0x00000018) Test program id, in ascii */ + __IM uint32_t OSATPARTNO; /*!< (@ 0x0000001C) OSAT part number */ + __IM uint8_t HWBUILDVERSION[4]; /*!< (@ 0x00000020) OSAT production build version */ + __IOM NRF_FICR_SIPINFO_OVERRIDE_Type OVERRIDE; /*!< (@ 0x00000024) (unspecified) */ +} NRF_FICR_SIPINFO_Type; /*!< Size = 60 (0x03C) */ + +/* FICR_SIPINFO_PARTNO: SIP part number */ + #define FICR_SIPINFO_PARTNO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PARTNO register. */ + +/* PARTNO @Bits 0..31 : (unspecified) */ + #define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */ + #define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */ + + +/* FICR_SIPINFO_HWREVISION: SIP hardware revision, encoded in ASCII, ex B0A or B1A */ + #define FICR_SIPINFO_HWREVISION_MaxCount (4UL) /*!< Max size of HWREVISION[4] array. */ + #define FICR_SIPINFO_HWREVISION_MaxIndex (3UL) /*!< Max index of HWREVISION[4] array. */ + #define FICR_SIPINFO_HWREVISION_MinIndex (0UL) /*!< Min index of HWREVISION[4] array. */ + #define FICR_SIPINFO_HWREVISION_ResetValue (0xFFUL) /*!< Reset value of HWREVISION[4] register. */ + +/* HWREVISION @Bits 0..7 : (unspecified) */ + #define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */ + #define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION + field.*/ + + +/* FICR_SIPINFO_VARIANT: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA */ + #define FICR_SIPINFO_VARIANT_MaxCount (4UL) /*!< Max size of VARIANT[4] array. */ + #define FICR_SIPINFO_VARIANT_MaxIndex (3UL) /*!< Max index of VARIANT[4] array. */ + #define FICR_SIPINFO_VARIANT_MinIndex (0UL) /*!< Min index of VARIANT[4] array. */ + #define FICR_SIPINFO_VARIANT_ResetValue (0xFFUL) /*!< Reset value of VARIANT[4] register. */ + +/* VARIANT @Bits 0..7 : (unspecified) */ + #define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ + #define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ + + +/* FICR_SIPINFO_PMICVERSION: PMIC version */ + #define FICR_SIPINFO_PMICVERSION_ResetValue (0x00000000UL) /*!< Reset value of PMICVERSION register. */ + +/* PMICVERSION @Bits 0..31 : PMIC version, incremental code */ + #define FICR_SIPINFO_PMICVERSION_PMICVERSION_Pos (0UL) /*!< Position of PMICVERSION field. */ + #define FICR_SIPINFO_PMICVERSION_PMICVERSION_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PMICVERSION_PMICVERSION_Pos) /*!< Bit mask of + PMICVERSION field.*/ + + +/* FICR_SIPINFO_LOT: Lot number + test index in hex format (number digits 0-9). */ + #define FICR_SIPINFO_LOT_ResetValue (0x00000000UL) /*!< Reset value of LOT register. */ + +/* LOTID @Bits 0..23 : Lot number in hex format */ + #define FICR_SIPINFO_LOT_LOTID_Pos (0UL) /*!< Position of LOTID field. */ + #define FICR_SIPINFO_LOT_LOTID_Msk (0xFFFFFFUL << FICR_SIPINFO_LOT_LOTID_Pos) /*!< Bit mask of LOTID field. */ + +/* TESTID @Bits 24..31 : Test ID in hex format */ + #define FICR_SIPINFO_LOT_TESTID_Pos (24UL) /*!< Position of TESTID field. */ + #define FICR_SIPINFO_LOT_TESTID_Msk (0xFFUL << FICR_SIPINFO_LOT_TESTID_Pos) /*!< Bit mask of TESTID field. */ + + +/* FICR_SIPINFO_OSATPARTNO: OSAT part number */ + #define FICR_SIPINFO_OSATPARTNO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OSATPARTNO register. */ + +/* OSATPARTNO @Bits 0..31 : (unspecified) */ + #define FICR_SIPINFO_OSATPARTNO_OSATPARTNO_Pos (0UL) /*!< Position of OSATPARTNO field. */ + #define FICR_SIPINFO_OSATPARTNO_OSATPARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_OSATPARTNO_OSATPARTNO_Pos) /*!< Bit mask of + OSATPARTNO field.*/ + + + +/* ============================================== Struct FICR_TRIM_GLOBAL_SAADC ============================================== */ +/** + * @brief SAADC [FICR_TRIM_GLOBAL_SAADC] (unspecified) + */ +typedef struct { + __IM uint32_t CALVREF; /*!< (@ 0x00000000) Trim value for GLOBAL.SAADC.CALVREF */ + __IM uint32_t CALGAIN[3]; /*!< (@ 0x00000004) Trim value for GLOBAL.SAADC.CALGAIN */ + __IM uint32_t CALOFFSET; /*!< (@ 0x00000010) Trim value for GLOBAL.SAADC.CALOFFSET */ + __IM uint32_t LINCALCOEFF[6]; /*!< (@ 0x00000014) Trim value for GLOBAL.SAADC.LINCALCOEFF */ + __IM uint32_t CALIREF; /*!< (@ 0x0000002C) Trim value for GLOBAL.SAADC.CALIREF */ + __IM uint32_t CALVREFTC; /*!< (@ 0x00000030) Trim value for GLOBAL.SAADC.CALVREFTC */ +} NRF_FICR_TRIM_GLOBAL_SAADC_Type; /*!< Size = 52 (0x034) */ + +/* FICR_TRIM_GLOBAL_SAADC_CALVREF: Trim value for GLOBAL.SAADC.CALVREF */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALVREF register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + + +/* FICR_TRIM_GLOBAL_SAADC_CALGAIN: Trim value for GLOBAL.SAADC.CALGAIN */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MaxCount (3UL) /*!< Max size of CALGAIN[3] array. */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MaxIndex (2UL) /*!< Max index of CALGAIN[3] array. */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MinIndex (0UL) /*!< Min index of CALGAIN[3] array. */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALGAIN[3] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + + +/* FICR_TRIM_GLOBAL_SAADC_CALOFFSET: Trim value for GLOBAL.SAADC.CALOFFSET */ + #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALOFFSET register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + + +/* FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF: Trim value for GLOBAL.SAADC.LINCALCOEFF */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MaxCount (6UL) /*!< Max size of LINCALCOEFF[6] array. */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MaxIndex (5UL) /*!< Max index of LINCALCOEFF[6] array. */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MinIndex (0UL) /*!< Min index of LINCALCOEFF[6] array. */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LINCALCOEFF[6] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Pos) /*!< Bit + mask of VALUE field.*/ + + +/* FICR_TRIM_GLOBAL_SAADC_CALIREF: Trim value for GLOBAL.SAADC.CALIREF */ + #define FICR_TRIM_GLOBAL_SAADC_CALIREF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALIREF register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + + +/* FICR_TRIM_GLOBAL_SAADC_CALVREFTC: Trim value for GLOBAL.SAADC.CALVREFTC */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALVREFTC register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + + + +/* =========================================== Struct FICR_TRIM_GLOBAL_CANPLL_TRIM =========================================== */ +/** + * @brief TRIM [FICR_TRIM_GLOBAL_CANPLL_TRIM] (unspecified) + */ +typedef struct { + __IM uint32_t CTUNE; /*!< (@ 0x00000000) Trim value for GLOBAL.CANPLL.TRIM.CTUNE */ +} NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_Type; /*!< Size = 4 (0x004) */ + +/* FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE: Trim value for GLOBAL.CANPLL.TRIM.CTUNE */ + #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CTUNE register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Pos) /*!< Bit + mask of VALUE field.*/ + + + +/* ============================================= Struct FICR_TRIM_GLOBAL_CANPLL ============================================== */ +/** + * @brief CANPLL [FICR_TRIM_GLOBAL_CANPLL] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_Type TRIM; /*!< (@ 0x00000000) (unspecified) */ +} NRF_FICR_TRIM_GLOBAL_CANPLL_Type; /*!< Size = 4 (0x004) */ + + +/* ============================================== Struct FICR_TRIM_GLOBAL_COMP =============================================== */ +/** + * @brief COMP [FICR_TRIM_GLOBAL_COMP] (unspecified) + */ +typedef struct { + __IM uint32_t REFTRIM; /*!< (@ 0x00000000) Trim value for GLOBAL.COMP.REFTRIM */ + __IM uint32_t RESERVED; +} NRF_FICR_TRIM_GLOBAL_COMP_Type; /*!< Size = 8 (0x008) */ + +/* FICR_TRIM_GLOBAL_COMP_REFTRIM: Trim value for GLOBAL.COMP.REFTRIM */ + #define FICR_TRIM_GLOBAL_COMP_REFTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REFTRIM register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Pos) /*!< Bit mask of + VALUE field.*/ + + + +/* ================================================= Struct FICR_TRIM_GLOBAL ================================================= */ +/** + * @brief GLOBAL [FICR_TRIM_GLOBAL] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_GLOBAL_SAADC_Type SAADC; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[2]; + __IOM NRF_FICR_TRIM_GLOBAL_CANPLL_Type CANPLL; /*!< (@ 0x0000003C) (unspecified) */ + __IM uint32_t RESERVED1[3]; + __IOM NRF_FICR_TRIM_GLOBAL_COMP_Type COMP; /*!< (@ 0x0000004C) (unspecified) */ +} NRF_FICR_TRIM_GLOBAL_Type; /*!< Size = 84 (0x054) */ + + +/* ========================================= Struct FICR_TRIM_APPLICATION_HSFLL_TRIM ========================================= */ +/** + * @brief TRIM [FICR_TRIM_APPLICATION_HSFLL_TRIM] (unspecified) + */ +typedef struct { + __IM uint32_t VSUP; /*!< (@ 0x00000000) Trim value for APPLICATION.HSFLL.TRIM.VSUP */ + __IM uint32_t COARSE[6]; /*!< (@ 0x00000004) Trim value for APPLICATION.HSFLL.TRIM.COARSE */ + __IM uint32_t FINE[6]; /*!< (@ 0x0000001C) Trim value for APPLICATION.HSFLL.TRIM.FINE */ +} NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_Type; /*!< Size = 52 (0x034) */ + +/* FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP: Trim value for APPLICATION.HSFLL.TRIM.VSUP */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VSUP register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Pos) /*!< + Bit mask of VALUE field.*/ + + +/* FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE: Trim value for APPLICATION.HSFLL.TRIM.COARSE */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MaxCount (6UL) /*!< Max size of COARSE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MaxIndex (5UL) /*!< Max index of COARSE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MinIndex (0UL) /*!< Min index of COARSE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of COARSE[6] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Pos) + /*!< Bit mask of VALUE field.*/ + + +/* FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE: Trim value for APPLICATION.HSFLL.TRIM.FINE */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MaxCount (6UL) /*!< Max size of FINE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MaxIndex (5UL) /*!< Max index of FINE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MinIndex (0UL) /*!< Min index of FINE[6] array. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FINE[6] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Pos) /*!< + Bit mask of VALUE field.*/ + + + +/* =========================================== Struct FICR_TRIM_APPLICATION_HSFLL ============================================ */ +/** + * @brief HSFLL [FICR_TRIM_APPLICATION_HSFLL] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_Type TRIM; /*!< (@ 0x00000000) (unspecified) */ +} NRF_FICR_TRIM_APPLICATION_HSFLL_Type; /*!< Size = 52 (0x034) */ + + +/* ===================================== Struct FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE ====================================== */ +/** + * @brief BLOCKTYPE [FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE] (unspecified) + */ +typedef struct { + __IM uint32_t TRIM; /*!< (@ 0x00000000) Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM */ +} NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_Type; /*!< Size = 4 (0x004) */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MaxCount (4UL) /*!< Size of BLOCKTYPE[4] array. */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MaxIndex (3UL) /*!< Max index of BLOCKTYPE[4] array. */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MinIndex (0UL) /*!< Min index of BLOCKTYPE[4] array. */ + +/* FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM: Trim value for APPLICATION.MEMCONF.BLOCKTYPE[n].TRIM */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TRIM register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos) + /*!< Bit mask of VALUE field.*/ + + + +/* ========================================== Struct FICR_TRIM_APPLICATION_MEMCONF =========================================== */ +/** + * @brief MEMCONF [FICR_TRIM_APPLICATION_MEMCONF] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[4]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_FICR_TRIM_APPLICATION_MEMCONF_Type; /*!< Size = 16 (0x010) */ + + +/* ============================================== Struct FICR_TRIM_APPLICATION =============================================== */ +/** + * @brief APPLICATION [FICR_TRIM_APPLICATION] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_APPLICATION_HSFLL_Type HSFLL; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_FICR_TRIM_APPLICATION_MEMCONF_Type MEMCONF; /*!< (@ 0x00000034) (unspecified) */ +} NRF_FICR_TRIM_APPLICATION_Type; /*!< Size = 68 (0x044) */ + + +/* ========================================== Struct FICR_TRIM_RADIOCORE_HSFLL_TRIM ========================================== */ +/** + * @brief TRIM [FICR_TRIM_RADIOCORE_HSFLL_TRIM] (unspecified) + */ +typedef struct { + __IM uint32_t VSUP; /*!< (@ 0x00000000) Trim value for RADIOCORE.HSFLL.TRIM.VSUP */ + __IM uint32_t COARSE[6]; /*!< (@ 0x00000004) Trim value for RADIOCORE.HSFLL.TRIM.COARSE */ + __IM uint32_t FINE[6]; /*!< (@ 0x0000001C) Trim value for RADIOCORE.HSFLL.TRIM.FINE */ +} NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_Type; /*!< Size = 52 (0x034) */ + +/* FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP: Trim value for RADIOCORE.HSFLL.TRIM.VSUP */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VSUP register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Pos) /*!< Bit + mask of VALUE field.*/ + + +/* FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE: Trim value for RADIOCORE.HSFLL.TRIM.COARSE */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MaxCount (6UL) /*!< Max size of COARSE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MaxIndex (5UL) /*!< Max index of COARSE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MinIndex (0UL) /*!< Min index of COARSE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of COARSE[6] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Pos) /*!< + Bit mask of VALUE field.*/ + + +/* FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE: Trim value for RADIOCORE.HSFLL.TRIM.FINE */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MaxCount (6UL) /*!< Max size of FINE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MaxIndex (5UL) /*!< Max index of FINE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MinIndex (0UL) /*!< Min index of FINE[6] array. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FINE[6] register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Pos) /*!< Bit + mask of VALUE field.*/ + + + +/* ============================================ Struct FICR_TRIM_RADIOCORE_HSFLL ============================================= */ +/** + * @brief HSFLL [FICR_TRIM_RADIOCORE_HSFLL] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_Type TRIM; /*!< (@ 0x00000000) (unspecified) */ +} NRF_FICR_TRIM_RADIOCORE_HSFLL_Type; /*!< Size = 52 (0x034) */ + + +/* ====================================== Struct FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE ======================================= */ +/** + * @brief BLOCKTYPE [FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE] (unspecified) + */ +typedef struct { + __IM uint32_t TRIM; /*!< (@ 0x00000000) Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM */ +} NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_Type; /*!< Size = 4 (0x004) */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MaxCount (4UL) /*!< Size of BLOCKTYPE[4] array. */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MaxIndex (3UL) /*!< Max index of BLOCKTYPE[4] array. */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MinIndex (0UL) /*!< Min index of BLOCKTYPE[4] array. */ + +/* FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM: Trim value for RADIOCORE.MEMCONF.BLOCKTYPE[n].TRIM */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TRIM register. */ + +/* VALUE @Bits 0..31 : Trim value */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos) + /*!< Bit mask of VALUE field.*/ + + + +/* =========================================== Struct FICR_TRIM_RADIOCORE_MEMCONF ============================================ */ +/** + * @brief MEMCONF [FICR_TRIM_RADIOCORE_MEMCONF] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[4]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_FICR_TRIM_RADIOCORE_MEMCONF_Type; /*!< Size = 16 (0x010) */ + + +/* =============================================== Struct FICR_TRIM_RADIOCORE ================================================ */ +/** + * @brief RADIOCORE [FICR_TRIM_RADIOCORE] (unspecified) + */ +typedef struct { + __IOM NRF_FICR_TRIM_RADIOCORE_HSFLL_Type HSFLL; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_FICR_TRIM_RADIOCORE_MEMCONF_Type MEMCONF; /*!< (@ 0x00000034) (unspecified) */ + __IM uint32_t RESERVED[11]; +} NRF_FICR_TRIM_RADIOCORE_Type; /*!< Size = 112 (0x070) */ + + +/* ==================================================== Struct FICR_TRIM ===================================================== */ +/** + * @brief TRIM [FICR_TRIM] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[145]; + __IOM NRF_FICR_TRIM_GLOBAL_Type GLOBAL; /*!< (@ 0x00000244) (unspecified) */ + __IOM NRF_FICR_TRIM_APPLICATION_Type APPLICATION; /*!< (@ 0x00000298) (unspecified) */ + __IOM NRF_FICR_TRIM_RADIOCORE_Type RADIOCORE; /*!< (@ 0x000002DC) (unspecified) */ + __IM uint32_t RESERVED1[231]; +} NRF_FICR_TRIM_Type; /*!< Size = 1768 (0x6E8) */ + +/* ======================================================= Struct FICR ======================================================= */ +/** + * @brief Factory Information Configuration Registers + */ + typedef struct { /*!< FICR Structure */ + __IM uint32_t RESERVED[3]; + __IOM NRF_FICR_BLE_Type BLE; /*!< (@ 0x0000000C) (unspecified) */ + __IM uint32_t RESERVED1[6]; + __IOM NRF_FICR_INFO_Type INFO; /*!< (@ 0x00000050) Device info */ + __IM uint32_t RESERVED2[3]; + __IOM NRF_FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000080) SIP-specific device info */ + __IM uint32_t RESERVED3[17]; + __IOM NRF_FICR_TRIM_Type TRIM; /*!< (@ 0x00000100) (unspecified) */ + } NRF_FICR_Type; /*!< Size = 2024 (0x7E8) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct GPIO_PORTCNF =================================================== */ +/** + * @brief PORTCNF [GPIO_PORTCNF] (unspecified) + */ +typedef struct { + __IOM uint32_t DRIVECTRL; /*!< (@ 0x00000000) Drive control for impedance matching of the pins in + this port*/ +} NRF_GPIO_PORTCNF_Type; /*!< Size = 4 (0x004) */ + +/* GPIO_PORTCNF_DRIVECTRL: Drive control for impedance matching of the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_ResetValue (0x00000000UL) /*!< Reset value of DRIVECTRL register. */ + +/* IMPEDANCE50 @Bit 0 : Enable 50 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Pos (0UL) /*!< Position of IMPEDANCE50 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Pos) /*!< Bit mask of IMPEDANCE50 + field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE50 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE50 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Enable (0x1UL) /*!< Enable */ + +/* IMPEDANCE100 @Bit 1 : Enable 100 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Pos (1UL) /*!< Position of IMPEDANCE100 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Pos) /*!< Bit mask of + IMPEDANCE100 field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE100 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE100 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Enable (0x1UL) /*!< Enable */ + +/* IMPEDANCE200 @Bit 2 : Enable 200 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Pos (2UL) /*!< Position of IMPEDANCE200 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Pos) /*!< Bit mask of + IMPEDANCE200 field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE200 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE200 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Enable (0x1UL) /*!< Enable */ + +/* IMPEDANCE400 @Bit 3 : Enable 400 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Pos (3UL) /*!< Position of IMPEDANCE400 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Pos) /*!< Bit mask of + IMPEDANCE400 field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE400 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE400 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Enable (0x1UL) /*!< Enable */ + +/* IMPEDANCE800 @Bit 4 : Enable 800 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Pos (4UL) /*!< Position of IMPEDANCE800 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Pos) /*!< Bit mask of + IMPEDANCE800 field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE800 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE800 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Enable (0x1UL) /*!< Enable */ + +/* IMPEDANCE1600 @Bit 5 : Enable 1600 ohms impedance to the pins in this port */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Pos (5UL) /*!< Position of IMPEDANCE1600 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Pos) /*!< Bit mask of + IMPEDANCE1600 field.*/ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE1600 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE1600 field. */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Disable (0x0UL) /*!< Disabled */ + #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Enable (0x1UL) /*!< Enable */ + + +/* ======================================================= Struct GPIO ======================================================= */ +/** + * @brief GPIO Port + */ + typedef struct { /*!< GPIO Structure */ + __IOM uint32_t OUT; /*!< (@ 0x00000000) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000004) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x00000008) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x0000000C) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000010) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000014) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x00000018) DIR clear register */ + __IM uint32_t RESERVED; + __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that have met + the criteria set in the PIN_CNF[n].SENSE registers*/ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior and + LDETECT mode*/ + __IOM uint32_t RETAIN; /*!< (@ 0x00000028) Enable retention for those GPIO registers marked as + retained*/ + __IM uint32_t RESERVED1; + __IOM NRF_GPIO_PORTCNF_Type PORTCNF; /*!< (@ 0x00000030) (unspecified) */ + __IM uint32_t RESERVED2[19]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000080) Pin n configuration of GPIO pin */ + } NRF_GPIO_Type; /*!< Size = 256 (0x100) */ + +/* GPIO_OUT: Write GPIO port */ + #define GPIO_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUT_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUT_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUT_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUT_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUT_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUT_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUT_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUT_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUT_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUT_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUT_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUT_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUT_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUT_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUT_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUT_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUT_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUT_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUT_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUT_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUT_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUT_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUT_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUT_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUT_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUT_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUT_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUT_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUT_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUT_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUT_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUT_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUT_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUT_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUT_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUT_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUT_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUT_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUT_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUT_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUT_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUT_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUT_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUT_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUT_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUT_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUT_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUT_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUT_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUT_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUT_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUT_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUT_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUT_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUT_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUT_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUT_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUT_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUT_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUT_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUT_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUT_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUT_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUT_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */ + #define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */ + + +/* GPIO_OUTSET: Set individual bits in GPIO port */ + #define GPIO_OUTSET_ResetValue (0x00000000UL) /*!< Reset value of OUTSET register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + + +/* GPIO_OUTCLR: Clear individual bits in GPIO port */ + #define GPIO_OUTCLR_ResetValue (0x00000000UL) /*!< Reset value of OUTCLR register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ + #define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */ + #define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + + +/* GPIO_IN: Read GPIO port */ + #define GPIO_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_IN_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_IN_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_IN_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_IN_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_IN_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_IN_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_IN_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_IN_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_IN_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_IN_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_IN_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_IN_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_IN_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_IN_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_IN_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_IN_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_IN_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_IN_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_IN_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_IN_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_IN_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_IN_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_IN_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_IN_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_IN_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_IN_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_IN_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_IN_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_IN_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_IN_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_IN_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_IN_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_IN_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_IN_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_IN_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_IN_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_IN_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_IN_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_IN_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_IN_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_IN_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_IN_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_IN_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_IN_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_IN_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_IN_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_IN_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_IN_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_IN_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_IN_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_IN_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_IN_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_IN_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_IN_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_IN_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_IN_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_IN_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_IN_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_IN_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_IN_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_IN_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_IN_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_IN_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_IN_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */ + #define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */ + + +/* GPIO_DIR: Direction of GPIO pins */ + #define GPIO_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register. */ + +/* PIN0 @Bit 0 : Pin 0 */ + #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */ + +/* PIN1 @Bit 1 : Pin 1 */ + #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */ + +/* PIN2 @Bit 2 : Pin 2 */ + #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */ + +/* PIN3 @Bit 3 : Pin 3 */ + #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */ + +/* PIN4 @Bit 4 : Pin 4 */ + #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */ + +/* PIN5 @Bit 5 : Pin 5 */ + #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */ + +/* PIN6 @Bit 6 : Pin 6 */ + #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */ + +/* PIN7 @Bit 7 : Pin 7 */ + #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */ + +/* PIN8 @Bit 8 : Pin 8 */ + #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */ + +/* PIN9 @Bit 9 : Pin 9 */ + #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */ + +/* PIN10 @Bit 10 : Pin 10 */ + #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */ + +/* PIN11 @Bit 11 : Pin 11 */ + #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */ + +/* PIN12 @Bit 12 : Pin 12 */ + #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */ + +/* PIN13 @Bit 13 : Pin 13 */ + #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */ + +/* PIN14 @Bit 14 : Pin 14 */ + #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */ + +/* PIN15 @Bit 15 : Pin 15 */ + #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */ + +/* PIN16 @Bit 16 : Pin 16 */ + #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */ + +/* PIN17 @Bit 17 : Pin 17 */ + #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */ + +/* PIN18 @Bit 18 : Pin 18 */ + #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */ + +/* PIN19 @Bit 19 : Pin 19 */ + #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */ + +/* PIN20 @Bit 20 : Pin 20 */ + #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */ + +/* PIN21 @Bit 21 : Pin 21 */ + #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */ + +/* PIN22 @Bit 22 : Pin 22 */ + #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */ + +/* PIN23 @Bit 23 : Pin 23 */ + #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */ + +/* PIN24 @Bit 24 : Pin 24 */ + #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */ + +/* PIN25 @Bit 25 : Pin 25 */ + #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */ + +/* PIN26 @Bit 26 : Pin 26 */ + #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */ + +/* PIN27 @Bit 27 : Pin 27 */ + #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */ + +/* PIN28 @Bit 28 : Pin 28 */ + #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */ + +/* PIN29 @Bit 29 : Pin 29 */ + #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */ + +/* PIN30 @Bit 30 : Pin 30 */ + #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */ + +/* PIN31 @Bit 31 : Pin 31 */ + #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */ + #define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */ + + +/* GPIO_DIRSET: DIR set register */ + #define GPIO_DIRSET_ResetValue (0x00000000UL) /*!< Reset value of DIRSET register. */ + +/* PIN0 @Bit 0 : Set as output pin 0 */ + #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Set as output pin 1 */ + #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Set as output pin 2 */ + #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Set as output pin 3 */ + #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Set as output pin 4 */ + #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Set as output pin 5 */ + #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Set as output pin 6 */ + #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Set as output pin 7 */ + #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Set as output pin 8 */ + #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Set as output pin 9 */ + #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Set as output pin 10 */ + #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Set as output pin 11 */ + #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Set as output pin 12 */ + #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Set as output pin 13 */ + #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Set as output pin 14 */ + #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Set as output pin 15 */ + #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Set as output pin 16 */ + #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Set as output pin 17 */ + #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Set as output pin 18 */ + #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Set as output pin 19 */ + #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Set as output pin 20 */ + #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Set as output pin 21 */ + #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Set as output pin 22 */ + #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Set as output pin 23 */ + #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Set as output pin 24 */ + #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Set as output pin 25 */ + #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Set as output pin 26 */ + #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Set as output pin 27 */ + #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Set as output pin 28 */ + #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Set as output pin 29 */ + #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Set as output pin 30 */ + #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Set as output pin 31 */ + #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + + +/* GPIO_DIRCLR: DIR clear register */ + #define GPIO_DIRCLR_ResetValue (0x00000000UL) /*!< Reset value of DIRCLR register. */ + +/* PIN0 @Bit 0 : Set as input pin 0 */ + #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN1 @Bit 1 : Set as input pin 1 */ + #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN2 @Bit 2 : Set as input pin 2 */ + #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN3 @Bit 3 : Set as input pin 3 */ + #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN4 @Bit 4 : Set as input pin 4 */ + #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN5 @Bit 5 : Set as input pin 5 */ + #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN6 @Bit 6 : Set as input pin 6 */ + #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN7 @Bit 7 : Set as input pin 7 */ + #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN8 @Bit 8 : Set as input pin 8 */ + #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN9 @Bit 9 : Set as input pin 9 */ + #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN10 @Bit 10 : Set as input pin 10 */ + #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN11 @Bit 11 : Set as input pin 11 */ + #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN12 @Bit 12 : Set as input pin 12 */ + #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN13 @Bit 13 : Set as input pin 13 */ + #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN14 @Bit 14 : Set as input pin 14 */ + #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN15 @Bit 15 : Set as input pin 15 */ + #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN16 @Bit 16 : Set as input pin 16 */ + #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN17 @Bit 17 : Set as input pin 17 */ + #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN18 @Bit 18 : Set as input pin 18 */ + #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN19 @Bit 19 : Set as input pin 19 */ + #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN20 @Bit 20 : Set as input pin 20 */ + #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN21 @Bit 21 : Set as input pin 21 */ + #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN22 @Bit 22 : Set as input pin 22 */ + #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN23 @Bit 23 : Set as input pin 23 */ + #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN24 @Bit 24 : Set as input pin 24 */ + #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN25 @Bit 25 : Set as input pin 25 */ + #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN26 @Bit 26 : Set as input pin 26 */ + #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN27 @Bit 27 : Set as input pin 27 */ + #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN28 @Bit 28 : Set as input pin 28 */ + #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN29 @Bit 29 : Set as input pin 29 */ + #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN30 @Bit 30 : Set as input pin 30 */ + #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* PIN31 @Bit 31 : Set as input pin 31 */ + #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */ + #define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */ + #define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + + +/* GPIO_LATCH: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + #define GPIO_LATCH_ResetValue (0x00000000UL) /*!< Reset value of LATCH register. */ + +/* PIN0 @Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define GPIO_LATCH_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define GPIO_LATCH_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN1 @Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define GPIO_LATCH_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define GPIO_LATCH_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN2 @Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define GPIO_LATCH_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define GPIO_LATCH_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN3 @Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define GPIO_LATCH_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define GPIO_LATCH_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN4 @Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define GPIO_LATCH_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define GPIO_LATCH_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN5 @Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define GPIO_LATCH_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define GPIO_LATCH_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN6 @Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define GPIO_LATCH_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define GPIO_LATCH_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN7 @Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define GPIO_LATCH_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define GPIO_LATCH_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN8 @Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define GPIO_LATCH_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define GPIO_LATCH_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN9 @Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define GPIO_LATCH_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define GPIO_LATCH_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN10 @Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define GPIO_LATCH_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define GPIO_LATCH_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN11 @Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define GPIO_LATCH_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define GPIO_LATCH_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN12 @Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define GPIO_LATCH_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define GPIO_LATCH_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN13 @Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define GPIO_LATCH_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define GPIO_LATCH_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN14 @Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define GPIO_LATCH_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define GPIO_LATCH_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN15 @Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define GPIO_LATCH_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define GPIO_LATCH_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN16 @Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define GPIO_LATCH_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define GPIO_LATCH_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN17 @Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define GPIO_LATCH_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define GPIO_LATCH_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN18 @Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define GPIO_LATCH_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define GPIO_LATCH_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN19 @Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define GPIO_LATCH_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define GPIO_LATCH_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN20 @Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define GPIO_LATCH_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define GPIO_LATCH_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN21 @Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define GPIO_LATCH_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define GPIO_LATCH_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN22 @Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define GPIO_LATCH_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define GPIO_LATCH_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN23 @Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define GPIO_LATCH_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define GPIO_LATCH_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN24 @Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define GPIO_LATCH_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define GPIO_LATCH_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN25 @Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define GPIO_LATCH_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define GPIO_LATCH_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN26 @Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define GPIO_LATCH_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define GPIO_LATCH_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN27 @Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define GPIO_LATCH_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define GPIO_LATCH_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN28 @Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define GPIO_LATCH_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define GPIO_LATCH_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN29 @Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define GPIO_LATCH_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define GPIO_LATCH_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN30 @Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define GPIO_LATCH_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define GPIO_LATCH_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */ + +/* PIN31 @Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ + #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define GPIO_LATCH_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define GPIO_LATCH_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */ + #define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */ + + +/* GPIO_DETECTMODE: Select between default DETECT signal behavior and LDETECT mode */ + #define GPIO_DETECTMODE_ResetValue (0x00000000UL) /*!< Reset value of DETECTMODE register. */ + +/* DETECTMODE @Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ + #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Min (0x0UL) /*!< Min enumerator value of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Max (0x1UL) /*!< Max enumerator value of DETECTMODE field. */ + #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ + #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ + + +/* GPIO_RETAIN: Enable retention for those GPIO registers marked as retained */ + #define GPIO_RETAIN_ResetValue (0x0000000CUL) /*!< Reset value of RETAIN register. */ + +/* APPLICAION @Bit 2 : Enable retention for GPIO registers for Application domain */ + #define GPIO_RETAIN_APPLICAION_Pos (2UL) /*!< Position of APPLICAION field. */ + #define GPIO_RETAIN_APPLICAION_Msk (0x1UL << GPIO_RETAIN_APPLICAION_Pos) /*!< Bit mask of APPLICAION field. */ + #define GPIO_RETAIN_APPLICAION_Min (0x0UL) /*!< Min enumerator value of APPLICAION field. */ + #define GPIO_RETAIN_APPLICAION_Max (0x1UL) /*!< Max enumerator value of APPLICAION field. */ + #define GPIO_RETAIN_APPLICAION_Disabled (0x0UL) /*!< Retention disabled */ + #define GPIO_RETAIN_APPLICAION_Enabled (0x1UL) /*!< Retention enabled */ + +/* RADIOCORE @Bit 3 : Enable retention for GPIO registers for Radio core */ + #define GPIO_RETAIN_RADIOCORE_Pos (3UL) /*!< Position of RADIOCORE field. */ + #define GPIO_RETAIN_RADIOCORE_Msk (0x1UL << GPIO_RETAIN_RADIOCORE_Pos) /*!< Bit mask of RADIOCORE field. */ + #define GPIO_RETAIN_RADIOCORE_Min (0x0UL) /*!< Min enumerator value of RADIOCORE field. */ + #define GPIO_RETAIN_RADIOCORE_Max (0x1UL) /*!< Max enumerator value of RADIOCORE field. */ + #define GPIO_RETAIN_RADIOCORE_Disabled (0x0UL) /*!< Retention disabled */ + #define GPIO_RETAIN_RADIOCORE_Enabled (0x1UL) /*!< Retention enabled */ + + +/* GPIO_PIN_CNF: Pin n configuration of GPIO pin */ + #define GPIO_PIN_CNF_MaxCount (32UL) /*!< Max size of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_MaxIndex (31UL) /*!< Max index of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_MinIndex (0UL) /*!< Min index of PIN_CNF[32] array. */ + #define GPIO_PIN_CNF_ResetValue (0x00000002UL) /*!< Reset value of PIN_CNF[32] register. */ + +/* DIR @Bit 0 : Pin direction. Same physical register as DIR register */ + #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ + #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ + #define GPIO_PIN_CNF_DIR_Min (0x0UL) /*!< Min enumerator value of DIR field. */ + #define GPIO_PIN_CNF_DIR_Max (0x1UL) /*!< Max enumerator value of DIR field. */ + #define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */ + #define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */ + +/* INPUT @Bit 1 : Connect or disconnect input buffer */ + #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Min (0x0UL) /*!< Min enumerator value of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Max (0x1UL) /*!< Max enumerator value of INPUT field. */ + #define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */ + #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */ + +/* PULL @Bits 2..3 : Pull configuration */ + #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ + #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ + #define GPIO_PIN_CNF_PULL_Min (0x0UL) /*!< Min enumerator value of PULL field. */ + #define GPIO_PIN_CNF_PULL_Max (0x3UL) /*!< Max enumerator value of PULL field. */ + #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ + #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ + #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ + +/* DRIVE0 @Bits 8..9 : Drive configuration for '0' */ + #define GPIO_PIN_CNF_DRIVE0_Pos (8UL) /*!< Position of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Msk (0x3UL << GPIO_PIN_CNF_DRIVE0_Pos) /*!< Bit mask of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Min (0x0UL) /*!< Min enumerator value of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_Max (0x3UL) /*!< Max enumerator value of DRIVE0 field. */ + #define GPIO_PIN_CNF_DRIVE0_S0 (0x0UL) /*!< Standard '0' */ + #define GPIO_PIN_CNF_DRIVE0_H0 (0x1UL) /*!< High drive '0' */ + #define GPIO_PIN_CNF_DRIVE0_D0 (0x2UL) /*!< Disconnect '0'(normally used for wired-or connections) */ + #define GPIO_PIN_CNF_DRIVE0_E0 (0x3UL) /*!< Extra high drive '0' */ + +/* DRIVE1 @Bits 10..11 : Drive configuration for '1' */ + #define GPIO_PIN_CNF_DRIVE1_Pos (10UL) /*!< Position of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Msk (0x3UL << GPIO_PIN_CNF_DRIVE1_Pos) /*!< Bit mask of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Min (0x0UL) /*!< Min enumerator value of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_Max (0x3UL) /*!< Max enumerator value of DRIVE1 field. */ + #define GPIO_PIN_CNF_DRIVE1_S1 (0x0UL) /*!< Standard '1' */ + #define GPIO_PIN_CNF_DRIVE1_H1 (0x1UL) /*!< High drive '1' */ + #define GPIO_PIN_CNF_DRIVE1_D1 (0x2UL) /*!< Disconnect '1'(normally used for wired-or connections) */ + #define GPIO_PIN_CNF_DRIVE1_E1 (0x3UL) /*!< Extra high drive '1' */ + +/* SENSE @Bits 16..17 : Pin sensing mechanism */ + #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Min (0x0UL) /*!< Min enumerator value of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Max (0x3UL) /*!< Max enumerator value of SENSE field. */ + #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */ + #define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */ + #define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */ + +/* CLOCKPIN @Bit 31 : Enable clock on the pin. */ + #define GPIO_PIN_CNF_CLOCKPIN_Pos (31UL) /*!< Position of CLOCKPIN field. */ + #define GPIO_PIN_CNF_CLOCKPIN_Msk (0x1UL << GPIO_PIN_CNF_CLOCKPIN_Pos) /*!< Bit mask of CLOCKPIN field. */ + #define GPIO_PIN_CNF_CLOCKPIN_Min (0x0UL) /*!< Min enumerator value of CLOCKPIN field. */ + #define GPIO_PIN_CNF_CLOCKPIN_Max (0x1UL) /*!< Max enumerator value of CLOCKPIN field. */ + #define GPIO_PIN_CNF_CLOCKPIN_Disabled (0x0UL) /*!< Clock disabled */ + #define GPIO_PIN_CNF_CLOCKPIN_Enabled (0x1UL) /*!< Clock enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct GPIOTE_EVENTS_PORT ================================================ */ +/** + * @brief EVENTS_PORT [GPIOTE_EVENTS_PORT] Peripheral events. + */ +typedef struct { + __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Non-secure port event from owner n */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Secure port event from owner n */ +} NRF_GPIOTE_EVENTS_PORT_Type; /*!< Size = 8 (0x008) */ + #define GPIOTE_EVENTS_PORT_MaxCount (4UL) /*!< Size of EVENTS_PORT[4] array. */ + #define GPIOTE_EVENTS_PORT_MaxIndex (3UL) /*!< Max index of EVENTS_PORT[4] array. */ + #define GPIOTE_EVENTS_PORT_MinIndex (0UL) /*!< Min index of EVENTS_PORT[4] array. */ + +/* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event from owner n */ + #define GPIOTE_EVENTS_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register. */ + +/* NONSECURE @Bit 0 : Non-secure port event from owner n */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos (0UL) /*!< Position of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos) /*!< Bit mask of + NONSECURE field.*/ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Min (0x0UL) /*!< Min enumerator value of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Max (0x1UL) /*!< Max enumerator value of NONSECURE field. */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Generated (0x1UL) /*!< Event generated */ + + +/* GPIOTE_EVENTS_PORT_SECURE: Secure port event from owner n */ + #define GPIOTE_EVENTS_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register. */ + +/* SECURE @Bit 0 : Secure port event from owner n */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos (0UL) /*!< Position of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Generated (0x1UL) /*!< Event generated */ + + + +/* =============================================== Struct GPIOTE_PUBLISH_PORT ================================================ */ +/** + * @brief PUBLISH_PORT [GPIOTE_PUBLISH_PORT] Publish configuration for events + */ +typedef struct { + __IOM uint32_t NONSECURE; /*!< (@ 0x00000000) Publish configuration for event PORT[n].NONSECURE */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Publish configuration for event PORT[n].SECURE */ +} NRF_GPIOTE_PUBLISH_PORT_Type; /*!< Size = 8 (0x008) */ + #define GPIOTE_PUBLISH_PORT_MaxCount (4UL) /*!< Size of PUBLISH_PORT[4] array. */ + #define GPIOTE_PUBLISH_PORT_MaxIndex (3UL) /*!< Max index of PUBLISH_PORT[4] array. */ + #define GPIOTE_PUBLISH_PORT_MinIndex (0UL) /*!< Min index of PUBLISH_PORT[4] array. */ + +/* GPIOTE_PUBLISH_PORT_NONSECURE: Publish configuration for event PORT[n].NONSECURE */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].NONSECURE will publish to */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GPIOTE_PUBLISH_PORT_SECURE: Publish configuration for event PORT[n].SECURE */ + #define GPIOTE_PUBLISH_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].SECURE will publish to */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_SECURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_PORT_SECURE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* ====================================================== Struct GPIOTE ====================================================== */ +/** + * @brief GPIO Tasks and Events + */ + typedef struct { /*!< GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is configured in CONFIG[n].POLARITY.*/ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is to set it high.*/ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Task for writing to pin specified in CONFIG[n].PSEL. + Action on pin is to set it low.*/ + __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Subscribe configuration for task OUT[n] */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Subscribe configuration for task SET[n] */ + __IM uint32_t RESERVED3[4]; + __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Subscribe configuration for task CLR[n] */ + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Event from pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED4[8]; + __IOM NRF_GPIOTE_EVENTS_PORT_Type EVENTS_PORT[4]; /*!< (@ 0x00000140) Peripheral events. */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Publish configuration for event IN[n] */ + __IM uint32_t RESERVED6[8]; + __IOM NRF_GPIOTE_PUBLISH_PORT_Type PUBLISH_PORT[4]; /*!< (@ 0x000001C0) Publish configuration for events */ + __IM uint32_t RESERVED7[73]; + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t INTENSET2; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t INTENCLR2; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED10[2]; + __IOM uint32_t INTENSET3; /*!< (@ 0x00000334) Enable interrupt */ + __IOM uint32_t INTENCLR3; /*!< (@ 0x00000338) Disable interrupt */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t INTENSET4; /*!< (@ 0x00000344) Enable interrupt */ + __IOM uint32_t INTENCLR4; /*!< (@ 0x00000348) Disable interrupt */ + __IM uint32_t RESERVED12[2]; + __IOM uint32_t INTENSET5; /*!< (@ 0x00000354) Enable interrupt */ + __IOM uint32_t INTENCLR5; /*!< (@ 0x00000358) Disable interrupt */ + __IM uint32_t RESERVED13[2]; + __IOM uint32_t INTENSET6; /*!< (@ 0x00000364) Enable interrupt */ + __IOM uint32_t INTENCLR6; /*!< (@ 0x00000368) Disable interrupt */ + __IM uint32_t RESERVED14[102]; + __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) with + rising or falling edge detection on the pin.*/ + __IM uint32_t RESERVED15[2]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Configuration for OUT[n], SET[n], and CLR[n] tasks and + IN[n] event*/ + } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + +/* GPIOTE_TASKS_OUT: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + #define GPIOTE_TASKS_OUT_MaxCount (8UL) /*!< Max size of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_MaxIndex (7UL) /*!< Max index of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_MinIndex (0UL) /*!< Min index of TASKS_OUT[8] array. */ + #define GPIOTE_TASKS_OUT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_OUT[8] register. */ + +/* TASKS_OUT @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Min (0x1UL) /*!< Min enumerator value of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Max (0x1UL) /*!< Max enumerator value of TASKS_OUT field. */ + #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_TASKS_SET: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + #define GPIOTE_TASKS_SET_MaxCount (8UL) /*!< Max size of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_MaxIndex (7UL) /*!< Max index of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_MinIndex (0UL) /*!< Min index of TASKS_SET[8] array. */ + #define GPIOTE_TASKS_SET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SET[8] register. */ + +/* TASKS_SET @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Min (0x1UL) /*!< Min enumerator value of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Max (0x1UL) /*!< Max enumerator value of TASKS_SET field. */ + #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_TASKS_CLR: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + #define GPIOTE_TASKS_CLR_MaxCount (8UL) /*!< Max size of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_MaxIndex (7UL) /*!< Max index of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_MinIndex (0UL) /*!< Min index of TASKS_CLR[8] array. */ + #define GPIOTE_TASKS_CLR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLR[8] register. */ + +/* TASKS_CLR @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLR field. */ + #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */ + + +/* GPIOTE_SUBSCRIBE_OUT: Subscribe configuration for task OUT[n] */ + #define GPIOTE_SUBSCRIBE_OUT_MaxCount (8UL) /*!< Max size of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_MinIndex (0UL) /*!< Min index of SUBSCRIBE_OUT[8] array. */ + #define GPIOTE_SUBSCRIBE_OUT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_OUT[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task OUT[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_SUBSCRIBE_SET: Subscribe configuration for task SET[n] */ + #define GPIOTE_SUBSCRIBE_SET_MaxCount (8UL) /*!< Max size of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_MinIndex (0UL) /*!< Min index of SUBSCRIBE_SET[8] array. */ + #define GPIOTE_SUBSCRIBE_SET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SET[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SET[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_SET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_SUBSCRIBE_CLR: Subscribe configuration for task CLR[n] */ + #define GPIOTE_SUBSCRIBE_CLR_MaxCount (8UL) /*!< Max size of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CLR[8] array. */ + #define GPIOTE_SUBSCRIBE_CLR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLR[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLR[n] will subscribe to */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GPIOTE_EVENTS_IN: Event from pin specified in CONFIG[n].PSEL */ + #define GPIOTE_EVENTS_IN_MaxCount (8UL) /*!< Max size of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_MaxIndex (7UL) /*!< Max index of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_MinIndex (0UL) /*!< Min index of EVENTS_IN[8] array. */ + #define GPIOTE_EVENTS_IN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_IN[8] register. */ + +/* EVENTS_IN @Bit 0 : Event from pin specified in CONFIG[n].PSEL */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Min (0x0UL) /*!< Min enumerator value of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Max (0x1UL) /*!< Max enumerator value of EVENTS_IN field. */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */ + #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */ + + +/* GPIOTE_PUBLISH_IN: Publish configuration for event IN[n] */ + #define GPIOTE_PUBLISH_IN_MaxCount (8UL) /*!< Max size of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_MaxIndex (7UL) /*!< Max index of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_MinIndex (0UL) /*!< Min index of PUBLISH_IN[8] array. */ + #define GPIOTE_PUBLISH_IN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_IN[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event IN[n] will publish to */ + #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GPIOTE_PUBLISH_IN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GPIOTE_INTENSET0: Enable interrupt */ + #define GPIOTE_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET0_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Msk (0x1UL << GPIOTE_INTENSET0_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET0_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET0_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Msk (0x1UL << GPIOTE_INTENSET0_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET0_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET0_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Msk (0x1UL << GPIOTE_INTENSET0_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET0_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET0_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Msk (0x1UL << GPIOTE_INTENSET0_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET0_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET0_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Msk (0x1UL << GPIOTE_INTENSET0_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET0_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET0_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Msk (0x1UL << GPIOTE_INTENSET0_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET0_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET0_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Msk (0x1UL << GPIOTE_INTENSET0_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET0_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET0_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Msk (0x1UL << GPIOTE_INTENSET0_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET0_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET0_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET0_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET0_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET0_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET0_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET0_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET0_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET0_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET0_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET0_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET0_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET0_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET0_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET0_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET0_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET0_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET0_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET0_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET0_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR0: Disable interrupt */ + #define GPIOTE_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR0_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Msk (0x1UL << GPIOTE_INTENCLR0_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR0_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR0_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Msk (0x1UL << GPIOTE_INTENCLR0_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR0_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR0_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Msk (0x1UL << GPIOTE_INTENCLR0_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR0_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR0_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Msk (0x1UL << GPIOTE_INTENCLR0_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR0_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR0_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Msk (0x1UL << GPIOTE_INTENCLR0_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR0_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR0_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Msk (0x1UL << GPIOTE_INTENCLR0_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR0_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR0_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Msk (0x1UL << GPIOTE_INTENCLR0_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR0_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR0_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Msk (0x1UL << GPIOTE_INTENCLR0_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR0_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR0_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET1: Enable interrupt */ + #define GPIOTE_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET1_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Msk (0x1UL << GPIOTE_INTENSET1_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET1_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET1_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Msk (0x1UL << GPIOTE_INTENSET1_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET1_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET1_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Msk (0x1UL << GPIOTE_INTENSET1_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET1_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET1_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Msk (0x1UL << GPIOTE_INTENSET1_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET1_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET1_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Msk (0x1UL << GPIOTE_INTENSET1_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET1_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET1_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Msk (0x1UL << GPIOTE_INTENSET1_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET1_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET1_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Msk (0x1UL << GPIOTE_INTENSET1_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET1_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET1_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Msk (0x1UL << GPIOTE_INTENSET1_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET1_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET1_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET1_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET1_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET1_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET1_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET1_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET1_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET1_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET1_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET1_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET1_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET1_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET1_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET1_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET1_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET1_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET1_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET1_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET1_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR1: Disable interrupt */ + #define GPIOTE_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR1_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Msk (0x1UL << GPIOTE_INTENCLR1_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR1_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR1_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Msk (0x1UL << GPIOTE_INTENCLR1_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR1_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR1_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Msk (0x1UL << GPIOTE_INTENCLR1_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR1_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR1_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Msk (0x1UL << GPIOTE_INTENCLR1_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR1_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR1_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Msk (0x1UL << GPIOTE_INTENCLR1_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR1_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR1_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Msk (0x1UL << GPIOTE_INTENCLR1_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR1_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR1_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Msk (0x1UL << GPIOTE_INTENCLR1_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR1_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR1_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Msk (0x1UL << GPIOTE_INTENCLR1_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR1_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR1_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET2: Enable interrupt */ + #define GPIOTE_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET2_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET2_IN0_Msk (0x1UL << GPIOTE_INTENSET2_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET2_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET2_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET2_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET2_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET2_IN1_Msk (0x1UL << GPIOTE_INTENSET2_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET2_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET2_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET2_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET2_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET2_IN2_Msk (0x1UL << GPIOTE_INTENSET2_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET2_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET2_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET2_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET2_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET2_IN3_Msk (0x1UL << GPIOTE_INTENSET2_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET2_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET2_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET2_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET2_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET2_IN4_Msk (0x1UL << GPIOTE_INTENSET2_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET2_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET2_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET2_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET2_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET2_IN5_Msk (0x1UL << GPIOTE_INTENSET2_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET2_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET2_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET2_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET2_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET2_IN6_Msk (0x1UL << GPIOTE_INTENSET2_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET2_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET2_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET2_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET2_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET2_IN7_Msk (0x1UL << GPIOTE_INTENSET2_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET2_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET2_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET2_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET2_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET2_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET2_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET2_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET2_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET2_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET2_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET2_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET2_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET2_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET2_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET2_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET2_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET2_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET2_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET2_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET2_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET2_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET2_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET2_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET2_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET2_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR2: Disable interrupt */ + #define GPIOTE_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR2_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR2_IN0_Msk (0x1UL << GPIOTE_INTENCLR2_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR2_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR2_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR2_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR2_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR2_IN1_Msk (0x1UL << GPIOTE_INTENCLR2_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR2_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR2_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR2_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR2_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR2_IN2_Msk (0x1UL << GPIOTE_INTENCLR2_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR2_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR2_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR2_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR2_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR2_IN3_Msk (0x1UL << GPIOTE_INTENCLR2_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR2_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR2_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR2_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR2_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR2_IN4_Msk (0x1UL << GPIOTE_INTENCLR2_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR2_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR2_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR2_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR2_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR2_IN5_Msk (0x1UL << GPIOTE_INTENCLR2_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR2_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR2_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR2_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR2_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR2_IN6_Msk (0x1UL << GPIOTE_INTENCLR2_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR2_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR2_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR2_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR2_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR2_IN7_Msk (0x1UL << GPIOTE_INTENCLR2_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR2_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR2_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR2_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR2_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET3: Enable interrupt */ + #define GPIOTE_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET3_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET3_IN0_Msk (0x1UL << GPIOTE_INTENSET3_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET3_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET3_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET3_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET3_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET3_IN1_Msk (0x1UL << GPIOTE_INTENSET3_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET3_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET3_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET3_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET3_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET3_IN2_Msk (0x1UL << GPIOTE_INTENSET3_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET3_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET3_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET3_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET3_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET3_IN3_Msk (0x1UL << GPIOTE_INTENSET3_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET3_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET3_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET3_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET3_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET3_IN4_Msk (0x1UL << GPIOTE_INTENSET3_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET3_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET3_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET3_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET3_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET3_IN5_Msk (0x1UL << GPIOTE_INTENSET3_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET3_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET3_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET3_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET3_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET3_IN6_Msk (0x1UL << GPIOTE_INTENSET3_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET3_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET3_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET3_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET3_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET3_IN7_Msk (0x1UL << GPIOTE_INTENSET3_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET3_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET3_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET3_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET3_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET3_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET3_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET3_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET3_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET3_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET3_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET3_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET3_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET3_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET3_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET3_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET3_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET3_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET3_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET3_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET3_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET3_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET3_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET3_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET3_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET3_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR3: Disable interrupt */ + #define GPIOTE_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR3_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR3_IN0_Msk (0x1UL << GPIOTE_INTENCLR3_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR3_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR3_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR3_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR3_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR3_IN1_Msk (0x1UL << GPIOTE_INTENCLR3_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR3_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR3_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR3_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR3_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR3_IN2_Msk (0x1UL << GPIOTE_INTENCLR3_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR3_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR3_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR3_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR3_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR3_IN3_Msk (0x1UL << GPIOTE_INTENCLR3_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR3_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR3_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR3_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR3_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR3_IN4_Msk (0x1UL << GPIOTE_INTENCLR3_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR3_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR3_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR3_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR3_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR3_IN5_Msk (0x1UL << GPIOTE_INTENCLR3_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR3_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR3_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR3_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR3_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR3_IN6_Msk (0x1UL << GPIOTE_INTENCLR3_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR3_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR3_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR3_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR3_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR3_IN7_Msk (0x1UL << GPIOTE_INTENCLR3_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR3_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR3_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR3_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR3_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET4: Enable interrupt */ + #define GPIOTE_INTENSET4_ResetValue (0x00000000UL) /*!< Reset value of INTENSET4 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET4_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET4_IN0_Msk (0x1UL << GPIOTE_INTENSET4_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET4_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET4_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET4_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET4_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET4_IN1_Msk (0x1UL << GPIOTE_INTENSET4_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET4_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET4_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET4_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET4_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET4_IN2_Msk (0x1UL << GPIOTE_INTENSET4_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET4_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET4_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET4_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET4_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET4_IN3_Msk (0x1UL << GPIOTE_INTENSET4_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET4_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET4_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET4_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET4_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET4_IN4_Msk (0x1UL << GPIOTE_INTENSET4_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET4_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET4_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET4_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET4_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET4_IN5_Msk (0x1UL << GPIOTE_INTENSET4_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET4_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET4_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET4_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET4_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET4_IN6_Msk (0x1UL << GPIOTE_INTENSET4_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET4_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET4_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET4_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET4_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET4_IN7_Msk (0x1UL << GPIOTE_INTENSET4_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET4_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET4_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET4_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET4_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET4_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET4_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET4_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET4_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET4_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET4_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET4_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET4_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET4_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET4_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET4_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET4_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET4_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET4_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET4_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET4_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET4_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET4_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET4_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET4_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET4_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR4: Disable interrupt */ + #define GPIOTE_INTENCLR4_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR4 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR4_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR4_IN0_Msk (0x1UL << GPIOTE_INTENCLR4_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR4_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR4_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR4_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR4_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR4_IN1_Msk (0x1UL << GPIOTE_INTENCLR4_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR4_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR4_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR4_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR4_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR4_IN2_Msk (0x1UL << GPIOTE_INTENCLR4_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR4_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR4_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR4_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR4_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR4_IN3_Msk (0x1UL << GPIOTE_INTENCLR4_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR4_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR4_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR4_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR4_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR4_IN4_Msk (0x1UL << GPIOTE_INTENCLR4_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR4_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR4_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR4_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR4_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR4_IN5_Msk (0x1UL << GPIOTE_INTENCLR4_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR4_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR4_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR4_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR4_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR4_IN6_Msk (0x1UL << GPIOTE_INTENCLR4_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR4_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR4_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR4_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR4_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR4_IN7_Msk (0x1UL << GPIOTE_INTENCLR4_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR4_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR4_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR4_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR4_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET5: Enable interrupt */ + #define GPIOTE_INTENSET5_ResetValue (0x00000000UL) /*!< Reset value of INTENSET5 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET5_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET5_IN0_Msk (0x1UL << GPIOTE_INTENSET5_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET5_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET5_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET5_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET5_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET5_IN1_Msk (0x1UL << GPIOTE_INTENSET5_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET5_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET5_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET5_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET5_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET5_IN2_Msk (0x1UL << GPIOTE_INTENSET5_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET5_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET5_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET5_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET5_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET5_IN3_Msk (0x1UL << GPIOTE_INTENSET5_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET5_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET5_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET5_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET5_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET5_IN4_Msk (0x1UL << GPIOTE_INTENSET5_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET5_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET5_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET5_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET5_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET5_IN5_Msk (0x1UL << GPIOTE_INTENSET5_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET5_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET5_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET5_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET5_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET5_IN6_Msk (0x1UL << GPIOTE_INTENSET5_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET5_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET5_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET5_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET5_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET5_IN7_Msk (0x1UL << GPIOTE_INTENSET5_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET5_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET5_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET5_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET5_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET5_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET5_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET5_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET5_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET5_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET5_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET5_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET5_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET5_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET5_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET5_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET5_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET5_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET5_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET5_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET5_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET5_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET5_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET5_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET5_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET5_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR5: Disable interrupt */ + #define GPIOTE_INTENCLR5_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR5 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR5_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR5_IN0_Msk (0x1UL << GPIOTE_INTENCLR5_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR5_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR5_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR5_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR5_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR5_IN1_Msk (0x1UL << GPIOTE_INTENCLR5_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR5_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR5_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR5_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR5_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR5_IN2_Msk (0x1UL << GPIOTE_INTENCLR5_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR5_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR5_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR5_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR5_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR5_IN3_Msk (0x1UL << GPIOTE_INTENCLR5_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR5_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR5_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR5_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR5_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR5_IN4_Msk (0x1UL << GPIOTE_INTENCLR5_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR5_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR5_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR5_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR5_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR5_IN5_Msk (0x1UL << GPIOTE_INTENCLR5_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR5_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR5_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR5_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR5_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR5_IN6_Msk (0x1UL << GPIOTE_INTENCLR5_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR5_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR5_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR5_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR5_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR5_IN7_Msk (0x1UL << GPIOTE_INTENCLR5_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR5_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR5_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR5_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR5_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENSET6: Enable interrupt */ + #define GPIOTE_INTENSET6_ResetValue (0x00000000UL) /*!< Reset value of INTENSET6 register. */ + +/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */ + #define GPIOTE_INTENSET6_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENSET6_IN0_Msk (0x1UL << GPIOTE_INTENSET6_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENSET6_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENSET6_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENSET6_IN0_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */ + #define GPIOTE_INTENSET6_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENSET6_IN1_Msk (0x1UL << GPIOTE_INTENSET6_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENSET6_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENSET6_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENSET6_IN1_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */ + #define GPIOTE_INTENSET6_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENSET6_IN2_Msk (0x1UL << GPIOTE_INTENSET6_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENSET6_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENSET6_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENSET6_IN2_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */ + #define GPIOTE_INTENSET6_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENSET6_IN3_Msk (0x1UL << GPIOTE_INTENSET6_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENSET6_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENSET6_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENSET6_IN3_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */ + #define GPIOTE_INTENSET6_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENSET6_IN4_Msk (0x1UL << GPIOTE_INTENSET6_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENSET6_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENSET6_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENSET6_IN4_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */ + #define GPIOTE_INTENSET6_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENSET6_IN5_Msk (0x1UL << GPIOTE_INTENSET6_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENSET6_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENSET6_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENSET6_IN5_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */ + #define GPIOTE_INTENSET6_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENSET6_IN6_Msk (0x1UL << GPIOTE_INTENSET6_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENSET6_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENSET6_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENSET6_IN6_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */ + #define GPIOTE_INTENSET6_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENSET6_IN7_Msk (0x1UL << GPIOTE_INTENSET6_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENSET6_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENSET6_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENSET6_IN7_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENSET6_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENSET6_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENSET6_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET6_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENSET6_PORT0SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENSET6_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENSET6_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENSET6_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET6_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENSET6_PORT1SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENSET6_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENSET6_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENSET6_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET6_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENSET6_PORT2SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENSET6_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENSET6_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENSET6_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET6_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENSET6_PORT3SECURE_Set (0x1UL) /*!< Enable */ + #define GPIOTE_INTENSET6_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENSET6_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_INTENCLR6: Disable interrupt */ + #define GPIOTE_INTENCLR6_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR6 register. */ + +/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */ + #define GPIOTE_INTENCLR6_IN0_Pos (0UL) /*!< Position of IN0 field. */ + #define GPIOTE_INTENCLR6_IN0_Msk (0x1UL << GPIOTE_INTENCLR6_IN0_Pos) /*!< Bit mask of IN0 field. */ + #define GPIOTE_INTENCLR6_IN0_Min (0x0UL) /*!< Min enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR6_IN0_Max (0x1UL) /*!< Max enumerator value of IN0 field. */ + #define GPIOTE_INTENCLR6_IN0_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */ + #define GPIOTE_INTENCLR6_IN1_Pos (1UL) /*!< Position of IN1 field. */ + #define GPIOTE_INTENCLR6_IN1_Msk (0x1UL << GPIOTE_INTENCLR6_IN1_Pos) /*!< Bit mask of IN1 field. */ + #define GPIOTE_INTENCLR6_IN1_Min (0x0UL) /*!< Min enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR6_IN1_Max (0x1UL) /*!< Max enumerator value of IN1 field. */ + #define GPIOTE_INTENCLR6_IN1_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */ + #define GPIOTE_INTENCLR6_IN2_Pos (2UL) /*!< Position of IN2 field. */ + #define GPIOTE_INTENCLR6_IN2_Msk (0x1UL << GPIOTE_INTENCLR6_IN2_Pos) /*!< Bit mask of IN2 field. */ + #define GPIOTE_INTENCLR6_IN2_Min (0x0UL) /*!< Min enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR6_IN2_Max (0x1UL) /*!< Max enumerator value of IN2 field. */ + #define GPIOTE_INTENCLR6_IN2_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */ + #define GPIOTE_INTENCLR6_IN3_Pos (3UL) /*!< Position of IN3 field. */ + #define GPIOTE_INTENCLR6_IN3_Msk (0x1UL << GPIOTE_INTENCLR6_IN3_Pos) /*!< Bit mask of IN3 field. */ + #define GPIOTE_INTENCLR6_IN3_Min (0x0UL) /*!< Min enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR6_IN3_Max (0x1UL) /*!< Max enumerator value of IN3 field. */ + #define GPIOTE_INTENCLR6_IN3_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */ + #define GPIOTE_INTENCLR6_IN4_Pos (4UL) /*!< Position of IN4 field. */ + #define GPIOTE_INTENCLR6_IN4_Msk (0x1UL << GPIOTE_INTENCLR6_IN4_Pos) /*!< Bit mask of IN4 field. */ + #define GPIOTE_INTENCLR6_IN4_Min (0x0UL) /*!< Min enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR6_IN4_Max (0x1UL) /*!< Max enumerator value of IN4 field. */ + #define GPIOTE_INTENCLR6_IN4_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */ + #define GPIOTE_INTENCLR6_IN5_Pos (5UL) /*!< Position of IN5 field. */ + #define GPIOTE_INTENCLR6_IN5_Msk (0x1UL << GPIOTE_INTENCLR6_IN5_Pos) /*!< Bit mask of IN5 field. */ + #define GPIOTE_INTENCLR6_IN5_Min (0x0UL) /*!< Min enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR6_IN5_Max (0x1UL) /*!< Max enumerator value of IN5 field. */ + #define GPIOTE_INTENCLR6_IN5_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */ + #define GPIOTE_INTENCLR6_IN6_Pos (6UL) /*!< Position of IN6 field. */ + #define GPIOTE_INTENCLR6_IN6_Msk (0x1UL << GPIOTE_INTENCLR6_IN6_Pos) /*!< Bit mask of IN6 field. */ + #define GPIOTE_INTENCLR6_IN6_Min (0x0UL) /*!< Min enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR6_IN6_Max (0x1UL) /*!< Max enumerator value of IN6 field. */ + #define GPIOTE_INTENCLR6_IN6_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */ + #define GPIOTE_INTENCLR6_IN7_Pos (7UL) /*!< Position of IN7 field. */ + #define GPIOTE_INTENCLR6_IN7_Msk (0x1UL << GPIOTE_INTENCLR6_IN7_Pos) /*!< Bit mask of IN7 field. */ + #define GPIOTE_INTENCLR6_IN7_Min (0x0UL) /*!< Min enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR6_IN7_Max (0x1UL) /*!< Max enumerator value of IN7 field. */ + #define GPIOTE_INTENCLR6_IN7_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_IN7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_IN7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE + field.*/ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Pos (17UL) /*!< Position of PORT0SECURE field. */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field. */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Min (0x0UL) /*!< Min enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Max (0x1UL) /*!< Max enumerator value of PORT0SECURE field. */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE + field.*/ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Pos (19UL) /*!< Position of PORT1SECURE field. */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field. */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Min (0x0UL) /*!< Min enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Max (0x1UL) /*!< Max enumerator value of PORT1SECURE field. */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE + field.*/ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Pos (21UL) /*!< Position of PORT2SECURE field. */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field. */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Min (0x0UL) /*!< Min enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Max (0x1UL) /*!< Max enumerator value of PORT2SECURE field. */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE + field.*/ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field. */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Pos (23UL) /*!< Position of PORT3SECURE field. */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field. */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Min (0x0UL) /*!< Min enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Max (0x1UL) /*!< Max enumerator value of PORT3SECURE field. */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Clear (0x1UL) /*!< Disable */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled */ + #define GPIOTE_INTENCLR6_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GPIOTE_LATENCY: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */ + #define GPIOTE_LATENCY_ResetValue (0x00000001UL) /*!< Reset value of LATENCY register. */ + +/* LATENCY @Bit 0 : Latency setting */ + #define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */ + #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */ + #define GPIOTE_LATENCY_LATENCY_Min (0x0UL) /*!< Min enumerator value of LATENCY field. */ + #define GPIOTE_LATENCY_LATENCY_Max (0x1UL) /*!< Max enumerator value of LATENCY field. */ + #define GPIOTE_LATENCY_LATENCY_LowPower (0x0UL) /*!< Low power setting */ + #define GPIOTE_LATENCY_LATENCY_LowLatency (0x1UL) /*!< Low latency setting */ + + +/* GPIOTE_CONFIG: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ + #define GPIOTE_CONFIG_MaxCount (8UL) /*!< Max size of CONFIG[8] array. */ + #define GPIOTE_CONFIG_MaxIndex (7UL) /*!< Max index of CONFIG[8] array. */ + #define GPIOTE_CONFIG_MinIndex (0UL) /*!< Min index of CONFIG[8] array. */ + #define GPIOTE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG[8] register. */ + +/* MODE @Bits 0..1 : Mode */ + #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define GPIOTE_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define GPIOTE_CONFIG_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE + module.*/ + #define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */ + #define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */ + +/* PSEL @Bits 4..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ + #define GPIOTE_CONFIG_PSEL_Pos (4UL) /*!< Position of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Min (0x00UL) /*!< Min value of PSEL field. */ + #define GPIOTE_CONFIG_PSEL_Max (0x1FUL) /*!< Max size of PSEL field. */ + +/* PORT @Bits 9..12 : Port number */ + #define GPIOTE_CONFIG_PORT_Pos (9UL) /*!< Position of PORT field. */ + #define GPIOTE_CONFIG_PORT_Msk (0xFUL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ + #define GPIOTE_CONFIG_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define GPIOTE_CONFIG_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* POLARITY @Bits 16..17 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event + mode: Operation on input that shall trigger IN[n] event. */ + + #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Min (0x0UL) /*!< Min enumerator value of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_Max (0x3UL) /*!< Max enumerator value of POLARITY field. */ + #define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] + event generated on pin activity.*/ + #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event + when rising edge on pin.*/ + #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] + event when falling edge on pin.*/ + #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any + change on pin.*/ + +/* OUTINIT @Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: + No effect. */ + + #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Min (0x0UL) /*!< Min enumerator value of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Max (0x1UL) /*!< Max enumerator value of OUTINIT field. */ + #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */ + #define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GPR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct GPR ======================================================== */ +/** + * @brief Granular Power Requester + */ + typedef struct { /*!< GPR Structure */ + __IOM uint32_t CPWRUPREQ; /*!< (@ 0x00000000) Debug Power Request Register */ + __IM uint32_t CPWRUPACK; /*!< (@ 0x00000004) Debug Power Acknowledge Register */ + __IM uint32_t RESERVED[958]; + __IM uint32_t ITCTRL; /*!< (@ 0x00000F00) Integration Mode Control Register */ + __IM uint32_t RESERVED1[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Claim Tag Set Register */ + __IM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Claim Tag Clear Register */ + __IM uint32_t RESERVED2[2]; + __OM uint32_t LOCKACCESS; /*!< (@ 0x00000FB0) Lock Access Register */ + __IM uint32_t LOCKSTATUS; /*!< (@ 0x00000FB4) Lock Status Register */ + __IM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Authentication Status Register */ + __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture Register */ + __IM uint32_t RESERVED3[2]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier Register */ + __IM uint32_t PERIPHID4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ + __IM uint32_t RESERVED4[3]; + __IM uint32_t PERIPHID0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ + __IM uint32_t PERIPHID1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ + __IM uint32_t PERIPHID2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ + __IM uint32_t PERIPHID3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ + __IM uint32_t COMPID0; /*!< (@ 0x00000FF0) Component ID0 Register */ + __IM uint32_t COMPID1; /*!< (@ 0x00000FF4) Component ID1 Register */ + __IM uint32_t COMPID2; /*!< (@ 0x00000FF8) Component ID2 Register */ + __IM uint32_t COMPID3; /*!< (@ 0x00000FFC) Component ID3 Register */ + } NRF_GPR_Type; /*!< Size = 4096 (0x1000) */ + +/* GPR_CPWRUPREQ: Debug Power Request Register */ + #define GPR_CPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of CPWRUPREQ register. */ + +/* CPWRUPREQ_BIT0 @Bit 0 : Bit 0 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT0_Pos (0UL) /*!< Position of CPWRUPREQ_BIT0 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT0_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT0_Pos) /*!< Bit mask of CPWRUPREQ_BIT0 field. */ + +/* CPWRUPREQ_BIT1 @Bit 1 : Bit 1 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT1_Pos (1UL) /*!< Position of CPWRUPREQ_BIT1 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT1_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT1_Pos) /*!< Bit mask of CPWRUPREQ_BIT1 field. */ + +/* CPWRUPREQ_BIT2 @Bit 2 : Bit 2 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT2_Pos (2UL) /*!< Position of CPWRUPREQ_BIT2 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT2_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT2_Pos) /*!< Bit mask of CPWRUPREQ_BIT2 field. */ + +/* CPWRUPREQ_BIT3 @Bit 3 : Bit 3 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT3_Pos (3UL) /*!< Position of CPWRUPREQ_BIT3 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT3_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT3_Pos) /*!< Bit mask of CPWRUPREQ_BIT3 field. */ + +/* CPWRUPREQ_BIT4 @Bit 4 : Bit 4 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT4_Pos (4UL) /*!< Position of CPWRUPREQ_BIT4 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT4_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT4_Pos) /*!< Bit mask of CPWRUPREQ_BIT4 field. */ + +/* CPWRUPREQ_BIT5 @Bit 5 : Bit 5 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT5_Pos (5UL) /*!< Position of CPWRUPREQ_BIT5 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT5_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT5_Pos) /*!< Bit mask of CPWRUPREQ_BIT5 field. */ + +/* CPWRUPREQ_BIT6 @Bit 6 : Bit 6 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT6_Pos (6UL) /*!< Position of CPWRUPREQ_BIT6 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT6_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT6_Pos) /*!< Bit mask of CPWRUPREQ_BIT6 field. */ + +/* CPWRUPREQ_BIT7 @Bit 7 : Bit 7 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT7_Pos (7UL) /*!< Position of CPWRUPREQ_BIT7 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT7_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT7_Pos) /*!< Bit mask of CPWRUPREQ_BIT7 field. */ + +/* CPWRUPREQ_BIT8 @Bit 8 : Bit 8 of the cpwrupreq output port. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT8_Pos (8UL) /*!< Position of CPWRUPREQ_BIT8 field. */ + #define GPR_CPWRUPREQ_CPWRUPREQ_BIT8_Msk (0x1UL << GPR_CPWRUPREQ_CPWRUPREQ_BIT8_Pos) /*!< Bit mask of CPWRUPREQ_BIT8 field. */ + + +/* GPR_CPWRUPACK: Debug Power Acknowledge Register */ + #define GPR_CPWRUPACK_ResetValue (0x00000000UL) /*!< Reset value of CPWRUPACK register. */ + +/* CPWRUPACK_BIT0 @Bit 0 : Bit 0 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT0_Pos (0UL) /*!< Position of CPWRUPACK_BIT0 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT0_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT0_Pos) /*!< Bit mask of CPWRUPACK_BIT0 field. */ + +/* CPWRUPACK_BIT1 @Bit 1 : Bit 1 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT1_Pos (1UL) /*!< Position of CPWRUPACK_BIT1 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT1_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT1_Pos) /*!< Bit mask of CPWRUPACK_BIT1 field. */ + +/* CPWRUPACK_BIT2 @Bit 2 : Bit 2 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT2_Pos (2UL) /*!< Position of CPWRUPACK_BIT2 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT2_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT2_Pos) /*!< Bit mask of CPWRUPACK_BIT2 field. */ + +/* CPWRUPACK_BIT3 @Bit 3 : Bit 3 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT3_Pos (3UL) /*!< Position of CPWRUPACK_BIT3 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT3_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT3_Pos) /*!< Bit mask of CPWRUPACK_BIT3 field. */ + +/* CPWRUPACK_BIT4 @Bit 4 : Bit 4 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT4_Pos (4UL) /*!< Position of CPWRUPACK_BIT4 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT4_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT4_Pos) /*!< Bit mask of CPWRUPACK_BIT4 field. */ + +/* CPWRUPACK_BIT5 @Bit 5 : Bit 5 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT5_Pos (5UL) /*!< Position of CPWRUPACK_BIT5 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT5_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT5_Pos) /*!< Bit mask of CPWRUPACK_BIT5 field. */ + +/* CPWRUPACK_BIT6 @Bit 6 : Bit 6 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT6_Pos (6UL) /*!< Position of CPWRUPACK_BIT6 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT6_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT6_Pos) /*!< Bit mask of CPWRUPACK_BIT6 field. */ + +/* CPWRUPACK_BIT7 @Bit 7 : Bit 7 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT7_Pos (7UL) /*!< Position of CPWRUPACK_BIT7 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT7_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT7_Pos) /*!< Bit mask of CPWRUPACK_BIT7 field. */ + +/* CPWRUPACK_BIT8 @Bit 8 : Bit 8 of the cpwrupack input port. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT8_Pos (8UL) /*!< Position of CPWRUPACK_BIT8 field. */ + #define GPR_CPWRUPACK_CPWRUPACK_BIT8_Msk (0x1UL << GPR_CPWRUPACK_CPWRUPACK_BIT8_Pos) /*!< Bit mask of CPWRUPACK_BIT8 field. */ + + +/* GPR_ITCTRL: Integration Mode Control Register */ + #define GPR_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* INTEGRATION_MODE @Bit 0 : When you read this register, CXGPR returns a zero because no integration functionality is + implemented. */ + + #define GPR_ITCTRL_INTEGRATION_MODE_Pos (0UL) /*!< Position of INTEGRATION_MODE field. */ + #define GPR_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << GPR_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field. */ + + +/* GPR_CLAIMSET: Claim Tag Set Register */ + #define GPR_CLAIMSET_ResetValue (0x0000000FUL) /*!< Reset value of CLAIMSET register. */ + +/* CLAIMSET @Bits 0..3 : On Read for each bit 1 means claim tag bit implemented. On Write for each bit 0 has no effect, 1 sets + the relevant bit of the claim tag */ + + #define GPR_CLAIMSET_CLAIMSET_Pos (0UL) /*!< Position of CLAIMSET field. */ + #define GPR_CLAIMSET_CLAIMSET_Msk (0xFUL << GPR_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field. */ + + +/* GPR_CLAIMCLR: Claim Tag Clear Register */ + #define GPR_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* CLAIMCLR @Bits 0..3 : The value present reflects the present value of the Claim Tag. */ + #define GPR_CLAIMCLR_CLAIMCLR_Pos (0UL) /*!< Position of CLAIMCLR field. */ + #define GPR_CLAIMCLR_CLAIMCLR_Msk (0xFUL << GPR_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field. */ + + +/* GPR_LOCKACCESS: Lock Access Register */ + #define GPR_LOCKACCESS_ResetValue (0x00000000UL) /*!< Reset value of LOCKACCESS register. */ + +/* LOCKACCESS @Bits 0..31 : When you write 0xC5ACCE55, subsequent write operations to this device are enabled. Any other value + disables subsequent write operations. */ + + #define GPR_LOCKACCESS_LOCKACCESS_Pos (0UL) /*!< Position of LOCKACCESS field. */ + #define GPR_LOCKACCESS_LOCKACCESS_Msk (0xFFFFFFFFUL << GPR_LOCKACCESS_LOCKACCESS_Pos) /*!< Bit mask of LOCKACCESS field. */ + + +/* GPR_LOCKSTATUS: Lock Status Register */ + #define GPR_LOCKSTATUS_ResetValue (0x00000003UL) /*!< Reset value of LOCKSTATUS register. */ + +/* LOCKEXIST @Bit 0 : Indicates that a lock control mechanism is present in this device. */ + #define GPR_LOCKSTATUS_LOCKEXIST_Pos (0UL) /*!< Position of LOCKEXIST field. */ + #define GPR_LOCKSTATUS_LOCKEXIST_Msk (0x1UL << GPR_LOCKSTATUS_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field. */ + +/* LOCKGRANT @Bit 1 : Returns the present lock status of the device. */ + #define GPR_LOCKSTATUS_LOCKGRANT_Pos (1UL) /*!< Position of LOCKGRANT field. */ + #define GPR_LOCKSTATUS_LOCKGRANT_Msk (0x1UL << GPR_LOCKSTATUS_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field. */ + +/* LOCKTYPE @Bit 2 : Indicates that the Lock Access Register is implemented as 32-bit. */ + #define GPR_LOCKSTATUS_LOCKTYPE_Pos (2UL) /*!< Position of LOCKTYPE field. */ + #define GPR_LOCKSTATUS_LOCKTYPE_Msk (0x1UL << GPR_LOCKSTATUS_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field. */ + + +/* GPR_AUTHSTATUS: Authentication Status Register */ + #define GPR_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Indicates the security level for Non-Secure Invasive Debug. */ + #define GPR_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define GPR_AUTHSTATUS_NSID_Msk (0x3UL << GPR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + +/* NSNID @Bits 2..3 : Indicates the security level for Non-Secure Non-Invasive Debug. */ + #define GPR_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define GPR_AUTHSTATUS_NSNID_Msk (0x3UL << GPR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + +/* SID @Bits 4..5 : Indicates the security level for Secure Invasive Debug. */ + #define GPR_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define GPR_AUTHSTATUS_SID_Msk (0x3UL << GPR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + +/* SNID @Bits 6..7 : Indicates the security level for Secure Non-Invasive Debug. */ + #define GPR_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define GPR_AUTHSTATUS_SNID_Msk (0x3UL << GPR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + + +/* GPR_DEVARCH: Device Architecture Register */ + #define GPR_DEVARCH_ResetValue (0x47700A34UL) /*!< Reset value of DEVARCH register. */ + +/* ARCHID @Bits 0..15 : Indicates the architecture of the component. */ + #define GPR_DEVARCH_ARCHID_Pos (0UL) /*!< Position of ARCHID field. */ + #define GPR_DEVARCH_ARCHID_Msk (0xFFFFUL << GPR_DEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field. */ + +/* REVISION @Bits 16..19 : Indicates the revision of the architecture. */ + #define GPR_DEVARCH_REVISION_Pos (16UL) /*!< Position of REVISION field. */ + #define GPR_DEVARCH_REVISION_Msk (0xFUL << GPR_DEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field. */ + +/* PRESENT @Bit 20 : Indicates whether the DEVARCH register is present. */ + #define GPR_DEVARCH_PRESENT_Pos (20UL) /*!< Position of PRESENT field. */ + #define GPR_DEVARCH_PRESENT_Msk (0x1UL << GPR_DEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + +/* ARCHITECT @Bits 21..31 : Indicates the JEP106 code pf the architect who specifies the architecture of the component. Bits + [31:28] are the JEP106 continuation code. Bits [27:21] are the JEP106 identity code. */ + + #define GPR_DEVARCH_ARCHITECT_Pos (21UL) /*!< Position of ARCHITECT field. */ + #define GPR_DEVARCH_ARCHITECT_Msk (0x7FFUL << GPR_DEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field. */ + + +/* GPR_DEVID: Device Configuration Register */ + #define GPR_DEVID_ResetValue (0x00000001UL) /*!< Reset value of DEVID register. */ + +/* CPWRUPM_COUNT @Bits 0..5 : The value present in this field indicates the number of CPWRUP master interfaces available in + CXGPR. Permitted range of values: 0x1 to 0x20. */ + + #define GPR_DEVID_CPWRUPM_COUNT_Pos (0UL) /*!< Position of CPWRUPM_COUNT field. */ + #define GPR_DEVID_CPWRUPM_COUNT_Msk (0x3FUL << GPR_DEVID_CPWRUPM_COUNT_Pos) /*!< Bit mask of CPWRUPM_COUNT field. */ + + +/* GPR_DEVTYPE: Device Type Identifier Register */ + #define GPR_DEVTYPE_ResetValue (0x00000034UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR_TYPE @Bits 0..3 : Major classification of the type of the debug component as specified in the CoreSight Architecture + Specification for this debug and trace component. */ + + #define GPR_DEVTYPE_MAJOR_TYPE_Pos (0UL) /*!< Position of MAJOR_TYPE field. */ + #define GPR_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << GPR_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field. */ + +/* SUB_TYPE @Bits 4..7 : Sub-classification of the type of the debug component as specified in the CoreSight Architecture + Specification within the major classification as specified in the Major_Type field. */ + + #define GPR_DEVTYPE_SUB_TYPE_Pos (4UL) /*!< Position of SUB_TYPE field. */ + #define GPR_DEVTYPE_SUB_TYPE_Msk (0xFUL << GPR_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field. */ + + +/* GPR_PERIPHID4: Peripheral ID4 Register */ + #define GPR_PERIPHID4_ResetValue (0x00000004UL) /*!< Reset value of PERIPHID4 register. */ + +/* DES_2 @Bits 0..3 : This is the JEDEC JEP106 continuation code. This code along with, bits[6:4] of the identity code defined + in PERIPHID0 register. and with bits[3:0] of the identity code defined in PERIPHID1 register, gives the + designer of the component. */ + + #define GPR_PERIPHID4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ + #define GPR_PERIPHID4_DES_2_Msk (0xFUL << GPR_PERIPHID4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ + +/* SIZE @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size in powers of two of the memory window that + this component uses from the standard 4KB. If a component only requires the standard 4KB size then this + reads as 0x0, for 8KB: 0x1, 16KB:0x2, 32KB: 0x3, until 128MB. */ + + #define GPR_PERIPHID4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ + #define GPR_PERIPHID4_SIZE_Msk (0xFUL << GPR_PERIPHID4_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* GPR_PERIPHID0: Peripheral ID0 Register */ + #define GPR_PERIPHID0_ResetValue (0x000000A4UL) /*!< Reset value of PERIPHID0 register. */ + +/* PART_0 @Bits 0..7 : Bits [7:0] of the components 12 bit part number. The designer of the component assigns this part number. + */ + + #define GPR_PERIPHID0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ + #define GPR_PERIPHID0_PART_0_Msk (0xFFUL << GPR_PERIPHID0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ + + +/* GPR_PERIPHID1: Peripheral ID1 Register */ + #define GPR_PERIPHID1_ResetValue (0x000000B9UL) /*!< Reset value of PERIPHID1 register. */ + +/* PART_1 @Bits 0..3 : Bits[11:8] of the components 12 bit part number. The designer of the component assigns this part number. + */ + + #define GPR_PERIPHID1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ + #define GPR_PERIPHID1_PART_1_Msk (0xFUL << GPR_PERIPHID1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ + +/* DES_0 @Bits 4..7 : Bits[3:0] of the JEDEC JEP106 identity code. This code, along with bits[6:4] of the identity code defined + in PERIPHID2 register and the continuation code defined in PERIPHID4 register, gives the designer of the + component. */ + + #define GPR_PERIPHID1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ + #define GPR_PERIPHID1_DES_0_Msk (0xFUL << GPR_PERIPHID1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ + + +/* GPR_PERIPHID2: Peripheral ID2 Register */ + #define GPR_PERIPHID2_ResetValue (0x0000000BUL) /*!< Reset value of PERIPHID2 register. */ + +/* DES_1 @Bits 0..2 : Bits[6:4] of the JEDEC JEP106 identity code. This code, along with bits[3:0] of the identity code defined + in PERIPHID1 register and the continuation code defined in PERIPHID4 register, gives the designer of the + component. */ + + #define GPR_PERIPHID2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ + #define GPR_PERIPHID2_DES_1_Msk (0x7UL << GPR_PERIPHID2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ + +/* JEDEC @Bit 3 : Always set. Indicates if the JEDEC assigned designer ID is used. */ + #define GPR_PERIPHID2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ + #define GPR_PERIPHID2_JEDEC_Msk (0x1UL << GPR_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ + +/* REVISION @Bits 4..7 : An incremental value starting from 0x0 for the first revision of this component. This increases by 1 + for both major and minor revisions and is used to identify the major or minor revisions. */ + + #define GPR_PERIPHID2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ + #define GPR_PERIPHID2_REVISION_Msk (0xFUL << GPR_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field. */ + + +/* GPR_PERIPHID3: Peripheral ID3 Register */ + #define GPR_PERIPHID3_ResetValue (0x00000000UL) /*!< Reset value of PERIPHID3 register. */ + +/* CMOD @Bits 0..3 : Indicates if the customer modified the behavior of the component. In most cases, this field might be zero. + The customer changes this value on modifications to this component. */ + + #define GPR_PERIPHID3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ + #define GPR_PERIPHID3_CMOD_Msk (0xFUL << GPR_PERIPHID3_CMOD_Pos) /*!< Bit mask of CMOD field. */ + +/* REVAND @Bits 4..7 : Indicates minor errata fixes specific to the revision of the component being used, for example metal + fixes after implementation. In most cases, this field might be zero. ARM recommends that the component + designers ensure that a metal fix can change this field if required, for example, by driving it from + registers that reset to zero. */ + + #define GPR_PERIPHID3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ + #define GPR_PERIPHID3_REVAND_Msk (0xFUL << GPR_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field. */ + + +/* GPR_COMPID0: Component ID0 Register */ + #define GPR_COMPID0_ResetValue (0x0000000DUL) /*!< Reset value of COMPID0 register. */ + +/* PRMBL_0 @Bits 0..7 : Contains bits[7:0] of the component identification code. */ + #define GPR_COMPID0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ + #define GPR_COMPID0_PRMBL_0_Msk (0xFFUL << GPR_COMPID0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ + + +/* GPR_COMPID1: Component ID1 Register */ + #define GPR_COMPID1_ResetValue (0x00000090UL) /*!< Reset value of COMPID1 register. */ + +/* PRMBL_1 @Bits 0..3 : Contains bits [11:8] of the component identification */ + #define GPR_COMPID1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ + #define GPR_COMPID1_PRMBL_1_Msk (0xFUL << GPR_COMPID1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ + +/* CLASS @Bits 4..7 : Class of the component, for example, if the component is a ROM table or a generic CoreSight component. + Contains bits[15:12] of the component identification code. */ + + #define GPR_COMPID1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ + #define GPR_COMPID1_CLASS_Msk (0xFUL << GPR_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field. */ + + +/* GPR_COMPID2: Component ID2 Register */ + #define GPR_COMPID2_ResetValue (0x00000005UL) /*!< Reset value of COMPID2 register. */ + +/* PRMBL_2 @Bits 0..7 : Contains bits [23:16] of the component identification */ + #define GPR_COMPID2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ + #define GPR_COMPID2_PRMBL_2_Msk (0xFFUL << GPR_COMPID2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ + + +/* GPR_COMPID3: Component ID3 Register */ + #define GPR_COMPID3_ResetValue (0x000000B1UL) /*!< Reset value of COMPID3 register. */ + +/* PRMBL_3 @Bits 0..7 : Contains bits [31:24] of the component identification */ + #define GPR_COMPID3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ + #define GPR_COMPID3_PRMBL_3_Msk (0xFFUL << GPR_COMPID3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ GRTC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct GRTC_CC ====================================================== */ +/** + * @brief CC [GRTC_CC] (unspecified) + */ +typedef struct { + __IOM uint32_t CCL; /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n] */ + __IOM uint32_t CCH; /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n] */ + __IOM uint32_t CCADD; /*!< (@ 0x00000008) Count to add to CC[n] when this register is written. */ + __IOM uint32_t CCEN; /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n] */ +} NRF_GRTC_CC_Type; /*!< Size = 16 (0x010) */ + #define GRTC_CC_MaxCount (16UL) /*!< Size of CC[16] array. */ + #define GRTC_CC_MaxIndex (15UL) /*!< Max index of CC[16] array. */ + #define GRTC_CC_MinIndex (0UL) /*!< Min index of CC[16] array. */ + +/* GRTC_CC_CCL: The lower 32-bits of Capture/Compare register CC[n] */ + #define GRTC_CC_CCL_ResetValue (0x00000000UL) /*!< Reset value of CCL register. */ + +/* CCL @Bits 0..31 : Capture/Compare low value in 1 us */ + #define GRTC_CC_CCL_CCL_Pos (0UL) /*!< Position of CCL field. */ + #define GRTC_CC_CCL_CCL_Msk (0xFFFFFFFFUL << GRTC_CC_CCL_CCL_Pos) /*!< Bit mask of CCL field. */ + + +/* GRTC_CC_CCH: The higher 32-bits of Capture/Compare register CC[n] */ + #define GRTC_CC_CCH_ResetValue (0x00000000UL) /*!< Reset value of CCH register. */ + +/* CCH @Bits 0..19 : Capture/Compare high value in 1 us */ + #define GRTC_CC_CCH_CCH_Pos (0UL) /*!< Position of CCH field. */ + #define GRTC_CC_CCH_CCH_Msk (0xFFFFFUL << GRTC_CC_CCH_CCH_Pos) /*!< Bit mask of CCH field. */ + + +/* GRTC_CC_CCADD: Count to add to CC[n] when this register is written. */ + #define GRTC_CC_CCADD_ResetValue (0x00000000UL) /*!< Reset value of CCADD register. */ + +/* VALUE @Bits 0..30 : Count to add to CC[n] */ + #define GRTC_CC_CCADD_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_CC_CCADD_VALUE_Msk (0x7FFFFFFFUL << GRTC_CC_CCADD_VALUE_Pos) /*!< Bit mask of VALUE field. */ + +/* REFERENCE @Bit 31 : Configure the Capture/Compare register */ + #define GRTC_CC_CCADD_REFERENCE_Pos (31UL) /*!< Position of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Msk (0x1UL << GRTC_CC_CCADD_REFERENCE_Pos) /*!< Bit mask of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Min (0x0UL) /*!< Min enumerator value of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_Max (0x1UL) /*!< Max enumerator value of REFERENCE field. */ + #define GRTC_CC_CCADD_REFERENCE_SYSCOUNTER (0x0UL) /*!< Adds SYSCOUNTER value. */ + #define GRTC_CC_CCADD_REFERENCE_CC (0x1UL) /*!< Adds CC value. */ + + +/* GRTC_CC_CCEN: Configure Capture/Compare register CC[n] */ + #define GRTC_CC_CCEN_ResetValue (0x00000000UL) /*!< Reset value of CCEN register. */ + +/* ACTIVE @Bit 0 : Configure the Capture/Compare register */ + #define GRTC_CC_CCEN_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Msk (0x1UL << GRTC_CC_CCEN_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define GRTC_CC_CCEN_ACTIVE_Disable (0x0UL) /*!< Capture/Compare register CC[n] Disabled. */ + #define GRTC_CC_CCEN_ACTIVE_Enable (0x1UL) /*!< Capture/Compare register CC[n] enabled. */ + + + +/* ================================================= Struct GRTC_SYSCOUNTER ================================================== */ +/** + * @brief SYSCOUNTER [GRTC_SYSCOUNTER] (unspecified) + */ +typedef struct { + __IM uint32_t SYSCOUNTERL; /*!< (@ 0x00000000) The lower 32-bits of the SYSCOUNTER for index [n] */ + __IM uint32_t SYSCOUNTERH; /*!< (@ 0x00000004) The higher 20-bits of the SYSCOUNTER for index [n] */ + __IOM uint32_t ACTIVE; /*!< (@ 0x00000008) Request to keep the SYSCOUNTER in the active state and + prevent going to sleep for index [n]*/ + __IM uint32_t RESERVED; +} NRF_GRTC_SYSCOUNTER_Type; /*!< Size = 16 (0x010) */ + #define GRTC_SYSCOUNTER_MaxCount (16UL) /*!< Size of SYSCOUNTER[16] array. */ + #define GRTC_SYSCOUNTER_MaxIndex (15UL) /*!< Max index of SYSCOUNTER[16] array. */ + #define GRTC_SYSCOUNTER_MinIndex (0UL) /*!< Min index of SYSCOUNTER[16] array. */ + +/* GRTC_SYSCOUNTER_SYSCOUNTERL: The lower 32-bits of the SYSCOUNTER for index [n] */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTERL register. */ + +/* VALUE @Bits 0..31 : The lower 32-bits of the SYSCOUNTER value. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk (0xFFFFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + + +/* GRTC_SYSCOUNTER_SYSCOUNTERH: The higher 20-bits of the SYSCOUNTER for index [n] */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_ResetValue (0x40000000UL) /*!< Reset value of SYSCOUNTERH register. */ + +/* VALUE @Bits 0..19 : The higher 20-bits of the SYSCOUNTER value. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk (0xFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos) /*!< Bit mask of VALUE + field.*/ + +/* BUSY @Bit 30 : SYSCOUNTER busy status */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos (30UL) /*!< Position of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Ready (0x0UL) /*!< SYSCOUNTER is ready for read */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Busy (0x1UL) /*!< SYSCOUNTER is busy, so not ready for read (value returned in the + VALUE field of this register is not valid)*/ + +/* OVERFLOW @Bit 31 : The SYSCOUNTERL overflow indication after reading it. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos (31UL) /*!< Position of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW + field.*/ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_NoOverflow (0x0UL) /*!< SYSCOUNTERL is not overflown */ + #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Overflow (0x1UL) /*!< SYSCOUNTERL overflown */ + + +/* GRTC_SYSCOUNTER_ACTIVE: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] */ + #define GRTC_SYSCOUNTER_ACTIVE_ResetValue (0x00000000UL) /*!< Reset value of ACTIVE register. */ + +/* ACTIVE @Bit 0 : Keep SYSCOUNTER in active state */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk (0x1UL << GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + + +/* ======================================================= Struct GRTC ======================================================= */ +/** + * @brief Global Real-time counter + */ + typedef struct { /*!< GRTC Structure */ + __OM uint32_t TASKS_CAPTURE[16]; /*!< (@ 0x00000000) Capture the counter value to CC[n] register */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_PWMSTART; /*!< (@ 0x0000006C) Start the PWM */ + __OM uint32_t TASKS_PWMSTOP; /*!< (@ 0x00000070) Stop the PWM */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t SUBSCRIBE_CAPTURE[16]; /*!< (@ 0x00000080) Subscribe configuration for task CAPTURE[n] */ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t EVENTS_COMPARE[16]; /*!< (@ 0x00000100) Compare event on CC[n] match */ + __IM uint32_t RESERVED3[9]; + __IOM uint32_t EVENTS_RTCOMPARESYNC; /*!< (@ 0x00000164) Synchronize always-on LFCLK clock domain */ + __IOM uint32_t EVENTS_SYSCOUNTERVALID; /*!< (@ 0x00000168) The SYSCOUNTER is in active state and value is valid */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x0000016C) Event on end of each PWM period */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t PUBLISH_COMPARE[16]; /*!< (@ 0x00000180) Publish configuration for event COMPARE[n] */ + __IM uint32_t RESERVED5[16]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t INTEN0; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND0; /*!< (@ 0x0000030C) Pending interrupts */ + __IOM uint32_t INTEN1; /*!< (@ 0x00000310) Enable or disable interrupt */ + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t INTPEND1; /*!< (@ 0x0000031C) Pending interrupts */ + __IOM uint32_t INTEN2; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t INTENSET2; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t INTENCLR2; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t INTPEND2; /*!< (@ 0x0000032C) Pending interrupts */ + __IOM uint32_t INTEN3; /*!< (@ 0x00000330) Enable or disable interrupt */ + __IOM uint32_t INTENSET3; /*!< (@ 0x00000334) Enable interrupt */ + __IOM uint32_t INTENCLR3; /*!< (@ 0x00000338) Disable interrupt */ + __IM uint32_t INTPEND3; /*!< (@ 0x0000033C) Pending interrupts */ + __IOM uint32_t INTEN4; /*!< (@ 0x00000340) Enable or disable interrupt */ + __IOM uint32_t INTENSET4; /*!< (@ 0x00000344) Enable interrupt */ + __IOM uint32_t INTENCLR4; /*!< (@ 0x00000348) Disable interrupt */ + __IM uint32_t INTPEND4; /*!< (@ 0x0000034C) Pending interrupts */ + __IOM uint32_t INTEN5; /*!< (@ 0x00000350) Enable or disable interrupt */ + __IOM uint32_t INTENSET5; /*!< (@ 0x00000354) Enable interrupt */ + __IOM uint32_t INTENCLR5; /*!< (@ 0x00000358) Disable interrupt */ + __IM uint32_t INTPEND5; /*!< (@ 0x0000035C) Pending interrupts */ + __IOM uint32_t INTEN6; /*!< (@ 0x00000360) Enable or disable interrupt */ + __IOM uint32_t INTENSET6; /*!< (@ 0x00000364) Enable interrupt */ + __IOM uint32_t INTENCLR6; /*!< (@ 0x00000368) Disable interrupt */ + __IM uint32_t INTPEND6; /*!< (@ 0x0000036C) Pending interrupts */ + __IOM uint32_t INTEN7; /*!< (@ 0x00000370) Enable or disable interrupt */ + __IOM uint32_t INTENSET7; /*!< (@ 0x00000374) Enable interrupt */ + __IOM uint32_t INTENCLR7; /*!< (@ 0x00000378) Disable interrupt */ + __IM uint32_t INTPEND7; /*!< (@ 0x0000037C) Pending interrupts */ + __IOM uint32_t INTEN8; /*!< (@ 0x00000380) Enable or disable interrupt */ + __IOM uint32_t INTENSET8; /*!< (@ 0x00000384) Enable interrupt */ + __IOM uint32_t INTENCLR8; /*!< (@ 0x00000388) Disable interrupt */ + __IM uint32_t INTPEND8; /*!< (@ 0x0000038C) Pending interrupts */ + __IOM uint32_t INTEN9; /*!< (@ 0x00000390) Enable or disable interrupt */ + __IOM uint32_t INTENSET9; /*!< (@ 0x00000394) Enable interrupt */ + __IOM uint32_t INTENCLR9; /*!< (@ 0x00000398) Disable interrupt */ + __IM uint32_t INTPEND9; /*!< (@ 0x0000039C) Pending interrupts */ + __IOM uint32_t INTEN10; /*!< (@ 0x000003A0) Enable or disable interrupt */ + __IOM uint32_t INTENSET10; /*!< (@ 0x000003A4) Enable interrupt */ + __IOM uint32_t INTENCLR10; /*!< (@ 0x000003A8) Disable interrupt */ + __IM uint32_t INTPEND10; /*!< (@ 0x000003AC) Pending interrupts */ + __IOM uint32_t INTEN11; /*!< (@ 0x000003B0) Enable or disable interrupt */ + __IOM uint32_t INTENSET11; /*!< (@ 0x000003B4) Enable interrupt */ + __IOM uint32_t INTENCLR11; /*!< (@ 0x000003B8) Disable interrupt */ + __IM uint32_t INTPEND11; /*!< (@ 0x000003BC) Pending interrupts */ + __IOM uint32_t INTEN12; /*!< (@ 0x000003C0) Enable or disable interrupt */ + __IOM uint32_t INTENSET12; /*!< (@ 0x000003C4) Enable interrupt */ + __IOM uint32_t INTENCLR12; /*!< (@ 0x000003C8) Disable interrupt */ + __IM uint32_t INTPEND12; /*!< (@ 0x000003CC) Pending interrupts */ + __IOM uint32_t INTEN13; /*!< (@ 0x000003D0) Enable or disable interrupt */ + __IOM uint32_t INTENSET13; /*!< (@ 0x000003D4) Enable interrupt */ + __IOM uint32_t INTENCLR13; /*!< (@ 0x000003D8) Disable interrupt */ + __IM uint32_t INTPEND13; /*!< (@ 0x000003DC) Pending interrupts */ + __IOM uint32_t INTEN14; /*!< (@ 0x000003E0) Enable or disable interrupt */ + __IOM uint32_t INTENSET14; /*!< (@ 0x000003E4) Enable interrupt */ + __IOM uint32_t INTENCLR14; /*!< (@ 0x000003E8) Disable interrupt */ + __IM uint32_t INTPEND14; /*!< (@ 0x000003EC) Pending interrupts */ + __IOM uint32_t INTEN15; /*!< (@ 0x000003F0) Enable or disable interrupt */ + __IOM uint32_t INTENSET15; /*!< (@ 0x000003F4) Enable interrupt */ + __IOM uint32_t INTENCLR15; /*!< (@ 0x000003F8) Disable interrupt */ + __IM uint32_t INTPEND15; /*!< (@ 0x000003FC) Pending interrupts */ + __IOM uint32_t EVTEN; /*!< (@ 0x00000400) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000404) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000408) Disable event routing */ + __IM uint32_t RESERVED7[65]; + __IOM uint32_t MODE; /*!< (@ 0x00000510) Counter mode selection */ + __IM uint32_t RESERVED8[3]; + __IOM NRF_GRTC_CC_Type CC[16]; /*!< (@ 0x00000520) (unspecified) */ + __IM uint32_t RESERVED9[32]; + __IOM uint32_t KEEPRUNNING; /*!< (@ 0x000006A0) Request to keep the SYSCOUNTER in the active state and + prevent going to sleep*/ + __IOM uint32_t TIMEOUT; /*!< (@ 0x000006A4) Timeout after all CPUs gone into sleep state to stop + the SYSCOUNTER*/ + __IOM uint32_t INTERVAL; /*!< (@ 0x000006A8) Count to add to CC[0] when the event EVENTS_COMPARE[0] + triggers.*/ + __IM uint32_t RESERVED10[25]; + __IOM uint32_t PWMCONFIG; /*!< (@ 0x00000710) PWM configuration. */ + __IOM uint32_t CLKOUT; /*!< (@ 0x00000714) Configuration of clock output */ + __IOM uint32_t CLKCFG; /*!< (@ 0x00000718) Clock Configuration */ + __IM uint32_t RESERVED11; + __IOM NRF_GRTC_SYSCOUNTER_Type SYSCOUNTER[16]; /*!< (@ 0x00000720) (unspecified) */ + } NRF_GRTC_Type; /*!< Size = 2080 (0x820) */ + +/* GRTC_TASKS_CAPTURE: Capture the counter value to CC[n] register */ + #define GRTC_TASKS_CAPTURE_MaxCount (16UL) /*!< Max size of TASKS_CAPTURE[16] array. */ + #define GRTC_TASKS_CAPTURE_MaxIndex (15UL) /*!< Max index of TASKS_CAPTURE[16] array. */ + #define GRTC_TASKS_CAPTURE_MinIndex (0UL) /*!< Min index of TASKS_CAPTURE[16] array. */ + #define GRTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[16] register. */ + +/* TASKS_CAPTURE @Bit 0 : Capture the counter value to CC[n] register */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE + field.*/ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field. */ + #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_PWMSTART: Start the PWM */ + #define GRTC_TASKS_PWMSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTART register. */ + +/* TASKS_PWMSTART @Bit 0 : Start the PWM */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos (0UL) /*!< Position of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Msk (0x1UL << GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos) /*!< Bit mask of + TASKS_PWMSTART field.*/ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTART field. */ + #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_TASKS_PWMSTOP: Stop the PWM */ + #define GRTC_TASKS_PWMSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTOP register. */ + +/* TASKS_PWMSTOP @Bit 0 : Stop the PWM */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos (0UL) /*!< Position of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Msk (0x1UL << GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos) /*!< Bit mask of TASKS_PWMSTOP + field.*/ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTOP field. */ + #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* GRTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */ + #define GRTC_SUBSCRIBE_CAPTURE_MaxCount (16UL) /*!< Max size of SUBSCRIBE_CAPTURE[16] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_MaxIndex (15UL) /*!< Max index of SUBSCRIBE_CAPTURE[16] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CAPTURE[16] array. */ + #define GRTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << GRTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define GRTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* GRTC_EVENTS_COMPARE: Compare event on CC[n] match */ + #define GRTC_EVENTS_COMPARE_MaxCount (16UL) /*!< Max size of EVENTS_COMPARE[16] array. */ + #define GRTC_EVENTS_COMPARE_MaxIndex (15UL) /*!< Max index of EVENTS_COMPARE[16] array. */ + #define GRTC_EVENTS_COMPARE_MinIndex (0UL) /*!< Min index of EVENTS_COMPARE[16] array. */ + #define GRTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[16] register. */ + +/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of + EVENTS_COMPARE field.*/ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field. */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_RTCOMPARESYNC: Synchronize always-on LFCLK clock domain */ + #define GRTC_EVENTS_RTCOMPARESYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RTCOMPARESYNC register. */ + +/* EVENTS_RTCOMPARESYNC @Bit 0 : Synchronize always-on LFCLK clock domain */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos (0UL) /*!< Position of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Msk (0x1UL << GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos) /*!< + Bit mask of EVENTS_RTCOMPARESYNC field.*/ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of EVENTS_RTCOMPARESYNC field. */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_SYSCOUNTERVALID: The SYSCOUNTER is in active state and value is valid */ + #define GRTC_EVENTS_SYSCOUNTERVALID_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYSCOUNTERVALID register. */ + +/* EVENTS_SYSCOUNTERVALID @Bit 0 : The SYSCOUNTER is in active state and value is valid */ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Pos (0UL) /*!< Position of EVENTS_SYSCOUNTERVALID field. */ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Msk (0x1UL << GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Pos) + /*!< Bit mask of EVENTS_SYSCOUNTERVALID field.*/ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of EVENTS_SYSCOUNTERVALID + field.*/ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of EVENTS_SYSCOUNTERVALID + field.*/ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_EVENTS_PWMPERIODEND: Event on end of each PWM period */ + #define GRTC_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register. */ + +/* EVENTS_PWMPERIODEND @Bit 0 : Event on end of each PWM period */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit + mask of EVENTS_PWMPERIODEND field.*/ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field. */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ + + +/* GRTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */ + #define GRTC_PUBLISH_COMPARE_MaxCount (16UL) /*!< Max size of PUBLISH_COMPARE[16] array. */ + #define GRTC_PUBLISH_COMPARE_MaxIndex (15UL) /*!< Max index of PUBLISH_COMPARE[16] array. */ + #define GRTC_PUBLISH_COMPARE_MinIndex (0UL) /*!< Min index of PUBLISH_COMPARE[16] array. */ + #define GRTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define GRTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define GRTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Msk (0x1UL << GRTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define GRTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define GRTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* GRTC_INTEN0: Enable or disable interrupt */ + #define GRTC_INTEN0_ResetValue (0x00000000UL) /*!< Reset value of INTEN0 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Msk (0x1UL << GRTC_INTEN0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN0_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Msk (0x1UL << GRTC_INTEN0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN0_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Msk (0x1UL << GRTC_INTEN0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN0_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Msk (0x1UL << GRTC_INTEN0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN0_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Msk (0x1UL << GRTC_INTEN0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN0_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Msk (0x1UL << GRTC_INTEN0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN0_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Msk (0x1UL << GRTC_INTEN0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN0_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Msk (0x1UL << GRTC_INTEN0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN0_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Msk (0x1UL << GRTC_INTEN0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN0_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Msk (0x1UL << GRTC_INTEN0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN0_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Msk (0x1UL << GRTC_INTEN0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN0_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Msk (0x1UL << GRTC_INTEN0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN0_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN0_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN0_COMPARE12_Msk (0x1UL << GRTC_INTEN0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN0_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN0_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN0_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN0_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN0_COMPARE13_Msk (0x1UL << GRTC_INTEN0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN0_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN0_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN0_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN0_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN0_COMPARE14_Msk (0x1UL << GRTC_INTEN0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN0_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN0_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN0_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN0_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN0_COMPARE15_Msk (0x1UL << GRTC_INTEN0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN0_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN0_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN0_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN0_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN0_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET0: Enable interrupt */ + #define GRTC_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Msk (0x1UL << GRTC_INTENSET0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET0_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Msk (0x1UL << GRTC_INTENSET0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET0_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Msk (0x1UL << GRTC_INTENSET0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET0_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Msk (0x1UL << GRTC_INTENSET0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET0_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Msk (0x1UL << GRTC_INTENSET0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET0_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Msk (0x1UL << GRTC_INTENSET0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET0_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Msk (0x1UL << GRTC_INTENSET0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET0_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Msk (0x1UL << GRTC_INTENSET0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET0_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Msk (0x1UL << GRTC_INTENSET0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET0_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Msk (0x1UL << GRTC_INTENSET0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET0_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Msk (0x1UL << GRTC_INTENSET0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET0_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Msk (0x1UL << GRTC_INTENSET0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET0_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET0_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET0_COMPARE12_Msk (0x1UL << GRTC_INTENSET0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET0_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET0_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET0_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET0_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET0_COMPARE13_Msk (0x1UL << GRTC_INTENSET0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET0_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET0_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET0_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET0_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET0_COMPARE14_Msk (0x1UL << GRTC_INTENSET0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET0_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET0_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET0_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET0_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET0_COMPARE15_Msk (0x1UL << GRTC_INTENSET0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET0_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET0_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET0_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET0_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR0: Disable interrupt */ + #define GRTC_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Msk (0x1UL << GRTC_INTENCLR0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR0_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Msk (0x1UL << GRTC_INTENCLR0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR0_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Msk (0x1UL << GRTC_INTENCLR0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR0_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Msk (0x1UL << GRTC_INTENCLR0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR0_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Msk (0x1UL << GRTC_INTENCLR0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR0_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Msk (0x1UL << GRTC_INTENCLR0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR0_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Msk (0x1UL << GRTC_INTENCLR0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR0_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Msk (0x1UL << GRTC_INTENCLR0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR0_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Msk (0x1UL << GRTC_INTENCLR0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR0_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Msk (0x1UL << GRTC_INTENCLR0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR0_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Msk (0x1UL << GRTC_INTENCLR0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR0_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Msk (0x1UL << GRTC_INTENCLR0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR0_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR0_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR0_COMPARE12_Msk (0x1UL << GRTC_INTENCLR0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR0_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR0_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR0_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR0_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR0_COMPARE13_Msk (0x1UL << GRTC_INTENCLR0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR0_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR0_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR0_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR0_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR0_COMPARE14_Msk (0x1UL << GRTC_INTENCLR0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR0_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR0_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR0_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR0_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR0_COMPARE15_Msk (0x1UL << GRTC_INTENCLR0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR0_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR0_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR0_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR0_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND0: Pending interrupts */ + #define GRTC_INTPEND0_ResetValue (0x00000000UL) /*!< Reset value of INTPEND0 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND0_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Msk (0x1UL << GRTC_INTPEND0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND0_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND0_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Msk (0x1UL << GRTC_INTPEND0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND0_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND0_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Msk (0x1UL << GRTC_INTPEND0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND0_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND0_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Msk (0x1UL << GRTC_INTPEND0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND0_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND0_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Msk (0x1UL << GRTC_INTPEND0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND0_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND0_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Msk (0x1UL << GRTC_INTPEND0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND0_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND0_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Msk (0x1UL << GRTC_INTPEND0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND0_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND0_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Msk (0x1UL << GRTC_INTPEND0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND0_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND0_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Msk (0x1UL << GRTC_INTPEND0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND0_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND0_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Msk (0x1UL << GRTC_INTPEND0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND0_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND0_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Msk (0x1UL << GRTC_INTPEND0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND0_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND0_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Msk (0x1UL << GRTC_INTPEND0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND0_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND0_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND0_COMPARE12_Msk (0x1UL << GRTC_INTPEND0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND0_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND0_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND0_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND0_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND0_COMPARE13_Msk (0x1UL << GRTC_INTPEND0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND0_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND0_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND0_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND0_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND0_COMPARE14_Msk (0x1UL << GRTC_INTPEND0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND0_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND0_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND0_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND0_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND0_COMPARE15_Msk (0x1UL << GRTC_INTPEND0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND0_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND0_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND0_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND0_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND0_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND0_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND0_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND0_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND0_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN1: Enable or disable interrupt */ + #define GRTC_INTEN1_ResetValue (0x00000000UL) /*!< Reset value of INTEN1 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Msk (0x1UL << GRTC_INTEN1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN1_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Msk (0x1UL << GRTC_INTEN1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN1_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Msk (0x1UL << GRTC_INTEN1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN1_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Msk (0x1UL << GRTC_INTEN1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN1_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Msk (0x1UL << GRTC_INTEN1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN1_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Msk (0x1UL << GRTC_INTEN1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN1_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Msk (0x1UL << GRTC_INTEN1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN1_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Msk (0x1UL << GRTC_INTEN1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN1_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Msk (0x1UL << GRTC_INTEN1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN1_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Msk (0x1UL << GRTC_INTEN1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN1_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Msk (0x1UL << GRTC_INTEN1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN1_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Msk (0x1UL << GRTC_INTEN1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN1_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN1_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN1_COMPARE12_Msk (0x1UL << GRTC_INTEN1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN1_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN1_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN1_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN1_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN1_COMPARE13_Msk (0x1UL << GRTC_INTEN1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN1_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN1_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN1_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN1_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN1_COMPARE14_Msk (0x1UL << GRTC_INTEN1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN1_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN1_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN1_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN1_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN1_COMPARE15_Msk (0x1UL << GRTC_INTEN1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN1_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN1_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN1_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN1_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN1_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET1: Enable interrupt */ + #define GRTC_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Msk (0x1UL << GRTC_INTENSET1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET1_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Msk (0x1UL << GRTC_INTENSET1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET1_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Msk (0x1UL << GRTC_INTENSET1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET1_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Msk (0x1UL << GRTC_INTENSET1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET1_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Msk (0x1UL << GRTC_INTENSET1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET1_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Msk (0x1UL << GRTC_INTENSET1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET1_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Msk (0x1UL << GRTC_INTENSET1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET1_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Msk (0x1UL << GRTC_INTENSET1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET1_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Msk (0x1UL << GRTC_INTENSET1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET1_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Msk (0x1UL << GRTC_INTENSET1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET1_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Msk (0x1UL << GRTC_INTENSET1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET1_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Msk (0x1UL << GRTC_INTENSET1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET1_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET1_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET1_COMPARE12_Msk (0x1UL << GRTC_INTENSET1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET1_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET1_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET1_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET1_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET1_COMPARE13_Msk (0x1UL << GRTC_INTENSET1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET1_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET1_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET1_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET1_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET1_COMPARE14_Msk (0x1UL << GRTC_INTENSET1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET1_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET1_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET1_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET1_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET1_COMPARE15_Msk (0x1UL << GRTC_INTENSET1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET1_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET1_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET1_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET1_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR1: Disable interrupt */ + #define GRTC_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Msk (0x1UL << GRTC_INTENCLR1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR1_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Msk (0x1UL << GRTC_INTENCLR1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR1_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Msk (0x1UL << GRTC_INTENCLR1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR1_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Msk (0x1UL << GRTC_INTENCLR1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR1_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Msk (0x1UL << GRTC_INTENCLR1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR1_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Msk (0x1UL << GRTC_INTENCLR1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR1_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Msk (0x1UL << GRTC_INTENCLR1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR1_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Msk (0x1UL << GRTC_INTENCLR1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR1_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Msk (0x1UL << GRTC_INTENCLR1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR1_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Msk (0x1UL << GRTC_INTENCLR1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR1_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Msk (0x1UL << GRTC_INTENCLR1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR1_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Msk (0x1UL << GRTC_INTENCLR1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR1_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR1_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR1_COMPARE12_Msk (0x1UL << GRTC_INTENCLR1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR1_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR1_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR1_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR1_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR1_COMPARE13_Msk (0x1UL << GRTC_INTENCLR1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR1_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR1_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR1_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR1_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR1_COMPARE14_Msk (0x1UL << GRTC_INTENCLR1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR1_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR1_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR1_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR1_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR1_COMPARE15_Msk (0x1UL << GRTC_INTENCLR1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR1_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR1_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR1_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR1_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND1: Pending interrupts */ + #define GRTC_INTPEND1_ResetValue (0x00000000UL) /*!< Reset value of INTPEND1 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND1_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Msk (0x1UL << GRTC_INTPEND1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND1_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND1_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Msk (0x1UL << GRTC_INTPEND1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND1_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND1_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Msk (0x1UL << GRTC_INTPEND1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND1_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND1_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Msk (0x1UL << GRTC_INTPEND1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND1_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND1_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Msk (0x1UL << GRTC_INTPEND1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND1_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND1_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Msk (0x1UL << GRTC_INTPEND1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND1_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND1_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Msk (0x1UL << GRTC_INTPEND1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND1_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND1_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Msk (0x1UL << GRTC_INTPEND1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND1_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND1_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Msk (0x1UL << GRTC_INTPEND1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND1_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND1_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Msk (0x1UL << GRTC_INTPEND1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND1_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND1_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Msk (0x1UL << GRTC_INTPEND1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND1_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND1_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Msk (0x1UL << GRTC_INTPEND1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND1_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND1_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND1_COMPARE12_Msk (0x1UL << GRTC_INTPEND1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND1_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND1_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND1_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND1_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND1_COMPARE13_Msk (0x1UL << GRTC_INTPEND1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND1_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND1_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND1_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND1_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND1_COMPARE14_Msk (0x1UL << GRTC_INTPEND1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND1_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND1_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND1_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND1_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND1_COMPARE15_Msk (0x1UL << GRTC_INTPEND1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND1_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND1_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND1_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND1_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND1_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND1_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND1_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND1_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND1_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN2: Enable or disable interrupt */ + #define GRTC_INTEN2_ResetValue (0x00000000UL) /*!< Reset value of INTEN2 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Msk (0x1UL << GRTC_INTEN2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN2_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Msk (0x1UL << GRTC_INTEN2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN2_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Msk (0x1UL << GRTC_INTEN2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN2_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Msk (0x1UL << GRTC_INTEN2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN2_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Msk (0x1UL << GRTC_INTEN2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN2_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Msk (0x1UL << GRTC_INTEN2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN2_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Msk (0x1UL << GRTC_INTEN2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN2_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Msk (0x1UL << GRTC_INTEN2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN2_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Msk (0x1UL << GRTC_INTEN2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN2_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Msk (0x1UL << GRTC_INTEN2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN2_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Msk (0x1UL << GRTC_INTEN2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN2_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Msk (0x1UL << GRTC_INTEN2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN2_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN2_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN2_COMPARE12_Msk (0x1UL << GRTC_INTEN2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN2_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN2_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN2_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN2_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN2_COMPARE13_Msk (0x1UL << GRTC_INTEN2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN2_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN2_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN2_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN2_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN2_COMPARE14_Msk (0x1UL << GRTC_INTEN2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN2_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN2_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN2_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN2_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN2_COMPARE15_Msk (0x1UL << GRTC_INTEN2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN2_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN2_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN2_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN2_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN2_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET2: Enable interrupt */ + #define GRTC_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Msk (0x1UL << GRTC_INTENSET2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET2_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Msk (0x1UL << GRTC_INTENSET2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET2_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Msk (0x1UL << GRTC_INTENSET2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET2_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Msk (0x1UL << GRTC_INTENSET2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET2_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Msk (0x1UL << GRTC_INTENSET2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET2_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Msk (0x1UL << GRTC_INTENSET2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET2_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Msk (0x1UL << GRTC_INTENSET2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET2_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Msk (0x1UL << GRTC_INTENSET2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET2_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Msk (0x1UL << GRTC_INTENSET2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET2_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Msk (0x1UL << GRTC_INTENSET2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET2_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Msk (0x1UL << GRTC_INTENSET2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET2_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Msk (0x1UL << GRTC_INTENSET2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET2_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET2_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET2_COMPARE12_Msk (0x1UL << GRTC_INTENSET2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET2_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET2_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET2_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET2_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET2_COMPARE13_Msk (0x1UL << GRTC_INTENSET2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET2_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET2_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET2_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET2_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET2_COMPARE14_Msk (0x1UL << GRTC_INTENSET2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET2_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET2_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET2_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET2_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET2_COMPARE15_Msk (0x1UL << GRTC_INTENSET2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET2_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET2_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET2_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET2_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR2: Disable interrupt */ + #define GRTC_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Msk (0x1UL << GRTC_INTENCLR2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR2_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Msk (0x1UL << GRTC_INTENCLR2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR2_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Msk (0x1UL << GRTC_INTENCLR2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR2_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Msk (0x1UL << GRTC_INTENCLR2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR2_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Msk (0x1UL << GRTC_INTENCLR2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR2_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Msk (0x1UL << GRTC_INTENCLR2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR2_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Msk (0x1UL << GRTC_INTENCLR2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR2_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Msk (0x1UL << GRTC_INTENCLR2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR2_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Msk (0x1UL << GRTC_INTENCLR2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR2_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Msk (0x1UL << GRTC_INTENCLR2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR2_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Msk (0x1UL << GRTC_INTENCLR2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR2_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Msk (0x1UL << GRTC_INTENCLR2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR2_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR2_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR2_COMPARE12_Msk (0x1UL << GRTC_INTENCLR2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR2_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR2_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR2_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR2_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR2_COMPARE13_Msk (0x1UL << GRTC_INTENCLR2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR2_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR2_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR2_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR2_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR2_COMPARE14_Msk (0x1UL << GRTC_INTENCLR2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR2_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR2_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR2_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR2_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR2_COMPARE15_Msk (0x1UL << GRTC_INTENCLR2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR2_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR2_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR2_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR2_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND2: Pending interrupts */ + #define GRTC_INTPEND2_ResetValue (0x00000000UL) /*!< Reset value of INTPEND2 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND2_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Msk (0x1UL << GRTC_INTPEND2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND2_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND2_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Msk (0x1UL << GRTC_INTPEND2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND2_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND2_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Msk (0x1UL << GRTC_INTPEND2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND2_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND2_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Msk (0x1UL << GRTC_INTPEND2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND2_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND2_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Msk (0x1UL << GRTC_INTPEND2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND2_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND2_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Msk (0x1UL << GRTC_INTPEND2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND2_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND2_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Msk (0x1UL << GRTC_INTPEND2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND2_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND2_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Msk (0x1UL << GRTC_INTPEND2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND2_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND2_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Msk (0x1UL << GRTC_INTPEND2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND2_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND2_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Msk (0x1UL << GRTC_INTPEND2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND2_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND2_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Msk (0x1UL << GRTC_INTPEND2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND2_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND2_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Msk (0x1UL << GRTC_INTPEND2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND2_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND2_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND2_COMPARE12_Msk (0x1UL << GRTC_INTPEND2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND2_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND2_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND2_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND2_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND2_COMPARE13_Msk (0x1UL << GRTC_INTPEND2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND2_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND2_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND2_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND2_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND2_COMPARE14_Msk (0x1UL << GRTC_INTPEND2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND2_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND2_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND2_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND2_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND2_COMPARE15_Msk (0x1UL << GRTC_INTPEND2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND2_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND2_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND2_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND2_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND2_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND2_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND2_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND2_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND2_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN3: Enable or disable interrupt */ + #define GRTC_INTEN3_ResetValue (0x00000000UL) /*!< Reset value of INTEN3 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Msk (0x1UL << GRTC_INTEN3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN3_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Msk (0x1UL << GRTC_INTEN3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN3_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Msk (0x1UL << GRTC_INTEN3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN3_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Msk (0x1UL << GRTC_INTEN3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN3_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Msk (0x1UL << GRTC_INTEN3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN3_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Msk (0x1UL << GRTC_INTEN3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN3_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Msk (0x1UL << GRTC_INTEN3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN3_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Msk (0x1UL << GRTC_INTEN3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN3_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Msk (0x1UL << GRTC_INTEN3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN3_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Msk (0x1UL << GRTC_INTEN3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN3_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Msk (0x1UL << GRTC_INTEN3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN3_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Msk (0x1UL << GRTC_INTEN3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN3_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN3_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN3_COMPARE12_Msk (0x1UL << GRTC_INTEN3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN3_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN3_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN3_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN3_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN3_COMPARE13_Msk (0x1UL << GRTC_INTEN3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN3_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN3_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN3_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN3_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN3_COMPARE14_Msk (0x1UL << GRTC_INTEN3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN3_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN3_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN3_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN3_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN3_COMPARE15_Msk (0x1UL << GRTC_INTEN3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN3_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN3_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN3_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN3_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN3_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET3: Enable interrupt */ + #define GRTC_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Msk (0x1UL << GRTC_INTENSET3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET3_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Msk (0x1UL << GRTC_INTENSET3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET3_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Msk (0x1UL << GRTC_INTENSET3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET3_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Msk (0x1UL << GRTC_INTENSET3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET3_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Msk (0x1UL << GRTC_INTENSET3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET3_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Msk (0x1UL << GRTC_INTENSET3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET3_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Msk (0x1UL << GRTC_INTENSET3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET3_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Msk (0x1UL << GRTC_INTENSET3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET3_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Msk (0x1UL << GRTC_INTENSET3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET3_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Msk (0x1UL << GRTC_INTENSET3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET3_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Msk (0x1UL << GRTC_INTENSET3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET3_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Msk (0x1UL << GRTC_INTENSET3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET3_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET3_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET3_COMPARE12_Msk (0x1UL << GRTC_INTENSET3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET3_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET3_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET3_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET3_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET3_COMPARE13_Msk (0x1UL << GRTC_INTENSET3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET3_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET3_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET3_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET3_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET3_COMPARE14_Msk (0x1UL << GRTC_INTENSET3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET3_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET3_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET3_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET3_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET3_COMPARE15_Msk (0x1UL << GRTC_INTENSET3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET3_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET3_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET3_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET3_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR3: Disable interrupt */ + #define GRTC_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Msk (0x1UL << GRTC_INTENCLR3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR3_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Msk (0x1UL << GRTC_INTENCLR3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR3_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Msk (0x1UL << GRTC_INTENCLR3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR3_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Msk (0x1UL << GRTC_INTENCLR3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR3_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Msk (0x1UL << GRTC_INTENCLR3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR3_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Msk (0x1UL << GRTC_INTENCLR3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR3_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Msk (0x1UL << GRTC_INTENCLR3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR3_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Msk (0x1UL << GRTC_INTENCLR3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR3_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Msk (0x1UL << GRTC_INTENCLR3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR3_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Msk (0x1UL << GRTC_INTENCLR3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR3_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Msk (0x1UL << GRTC_INTENCLR3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR3_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Msk (0x1UL << GRTC_INTENCLR3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR3_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR3_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR3_COMPARE12_Msk (0x1UL << GRTC_INTENCLR3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR3_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR3_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR3_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR3_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR3_COMPARE13_Msk (0x1UL << GRTC_INTENCLR3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR3_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR3_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR3_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR3_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR3_COMPARE14_Msk (0x1UL << GRTC_INTENCLR3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR3_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR3_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR3_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR3_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR3_COMPARE15_Msk (0x1UL << GRTC_INTENCLR3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR3_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR3_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR3_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR3_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND3: Pending interrupts */ + #define GRTC_INTPEND3_ResetValue (0x00000000UL) /*!< Reset value of INTPEND3 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND3_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Msk (0x1UL << GRTC_INTPEND3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND3_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND3_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Msk (0x1UL << GRTC_INTPEND3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND3_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND3_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Msk (0x1UL << GRTC_INTPEND3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND3_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND3_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Msk (0x1UL << GRTC_INTPEND3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND3_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND3_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Msk (0x1UL << GRTC_INTPEND3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND3_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND3_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Msk (0x1UL << GRTC_INTPEND3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND3_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND3_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Msk (0x1UL << GRTC_INTPEND3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND3_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND3_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Msk (0x1UL << GRTC_INTPEND3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND3_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND3_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Msk (0x1UL << GRTC_INTPEND3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND3_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND3_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Msk (0x1UL << GRTC_INTPEND3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND3_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND3_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Msk (0x1UL << GRTC_INTPEND3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND3_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND3_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Msk (0x1UL << GRTC_INTPEND3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND3_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND3_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND3_COMPARE12_Msk (0x1UL << GRTC_INTPEND3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND3_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND3_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND3_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND3_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND3_COMPARE13_Msk (0x1UL << GRTC_INTPEND3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND3_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND3_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND3_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND3_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND3_COMPARE14_Msk (0x1UL << GRTC_INTPEND3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND3_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND3_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND3_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND3_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND3_COMPARE15_Msk (0x1UL << GRTC_INTPEND3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND3_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND3_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND3_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND3_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND3_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND3_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND3_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND3_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND3_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN4: Enable or disable interrupt */ + #define GRTC_INTEN4_ResetValue (0x00000000UL) /*!< Reset value of INTEN4 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN4_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN4_COMPARE0_Msk (0x1UL << GRTC_INTEN4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN4_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN4_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN4_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN4_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN4_COMPARE1_Msk (0x1UL << GRTC_INTEN4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN4_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN4_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN4_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN4_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN4_COMPARE2_Msk (0x1UL << GRTC_INTEN4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN4_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN4_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN4_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN4_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN4_COMPARE3_Msk (0x1UL << GRTC_INTEN4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN4_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN4_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN4_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN4_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN4_COMPARE4_Msk (0x1UL << GRTC_INTEN4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN4_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN4_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN4_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN4_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN4_COMPARE5_Msk (0x1UL << GRTC_INTEN4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN4_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN4_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN4_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN4_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN4_COMPARE6_Msk (0x1UL << GRTC_INTEN4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN4_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN4_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN4_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN4_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN4_COMPARE7_Msk (0x1UL << GRTC_INTEN4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN4_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN4_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN4_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN4_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN4_COMPARE8_Msk (0x1UL << GRTC_INTEN4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN4_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN4_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN4_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN4_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN4_COMPARE9_Msk (0x1UL << GRTC_INTEN4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN4_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN4_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN4_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN4_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN4_COMPARE10_Msk (0x1UL << GRTC_INTEN4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN4_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN4_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN4_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN4_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN4_COMPARE11_Msk (0x1UL << GRTC_INTEN4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN4_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN4_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN4_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN4_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN4_COMPARE12_Msk (0x1UL << GRTC_INTEN4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN4_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN4_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN4_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN4_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN4_COMPARE13_Msk (0x1UL << GRTC_INTEN4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN4_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN4_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN4_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN4_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN4_COMPARE14_Msk (0x1UL << GRTC_INTEN4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN4_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN4_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN4_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN4_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN4_COMPARE15_Msk (0x1UL << GRTC_INTEN4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN4_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN4_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN4_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN4_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN4_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN4_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN4_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN4_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN4_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN4_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN4_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN4_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN4_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN4_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN4_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN4_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET4: Enable interrupt */ + #define GRTC_INTENSET4_ResetValue (0x00000000UL) /*!< Reset value of INTENSET4 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET4_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET4_COMPARE0_Msk (0x1UL << GRTC_INTENSET4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET4_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET4_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET4_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET4_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET4_COMPARE1_Msk (0x1UL << GRTC_INTENSET4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET4_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET4_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET4_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET4_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET4_COMPARE2_Msk (0x1UL << GRTC_INTENSET4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET4_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET4_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET4_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET4_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET4_COMPARE3_Msk (0x1UL << GRTC_INTENSET4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET4_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET4_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET4_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET4_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET4_COMPARE4_Msk (0x1UL << GRTC_INTENSET4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET4_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET4_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET4_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET4_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET4_COMPARE5_Msk (0x1UL << GRTC_INTENSET4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET4_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET4_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET4_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET4_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET4_COMPARE6_Msk (0x1UL << GRTC_INTENSET4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET4_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET4_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET4_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET4_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET4_COMPARE7_Msk (0x1UL << GRTC_INTENSET4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET4_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET4_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET4_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET4_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET4_COMPARE8_Msk (0x1UL << GRTC_INTENSET4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET4_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET4_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET4_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET4_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET4_COMPARE9_Msk (0x1UL << GRTC_INTENSET4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET4_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET4_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET4_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET4_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET4_COMPARE10_Msk (0x1UL << GRTC_INTENSET4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET4_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET4_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET4_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET4_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET4_COMPARE11_Msk (0x1UL << GRTC_INTENSET4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET4_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET4_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET4_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET4_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET4_COMPARE12_Msk (0x1UL << GRTC_INTENSET4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET4_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET4_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET4_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET4_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET4_COMPARE13_Msk (0x1UL << GRTC_INTENSET4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET4_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET4_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET4_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET4_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET4_COMPARE14_Msk (0x1UL << GRTC_INTENSET4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET4_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET4_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET4_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET4_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET4_COMPARE15_Msk (0x1UL << GRTC_INTENSET4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET4_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET4_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET4_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET4_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET4_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET4_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET4_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET4_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET4_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET4_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET4_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET4_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR4: Disable interrupt */ + #define GRTC_INTENCLR4_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR4 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR4_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR4_COMPARE0_Msk (0x1UL << GRTC_INTENCLR4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR4_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR4_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR4_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR4_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR4_COMPARE1_Msk (0x1UL << GRTC_INTENCLR4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR4_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR4_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR4_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR4_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR4_COMPARE2_Msk (0x1UL << GRTC_INTENCLR4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR4_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR4_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR4_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR4_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR4_COMPARE3_Msk (0x1UL << GRTC_INTENCLR4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR4_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR4_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR4_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR4_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR4_COMPARE4_Msk (0x1UL << GRTC_INTENCLR4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR4_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR4_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR4_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR4_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR4_COMPARE5_Msk (0x1UL << GRTC_INTENCLR4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR4_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR4_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR4_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR4_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR4_COMPARE6_Msk (0x1UL << GRTC_INTENCLR4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR4_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR4_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR4_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR4_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR4_COMPARE7_Msk (0x1UL << GRTC_INTENCLR4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR4_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR4_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR4_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR4_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR4_COMPARE8_Msk (0x1UL << GRTC_INTENCLR4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR4_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR4_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR4_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR4_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR4_COMPARE9_Msk (0x1UL << GRTC_INTENCLR4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR4_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR4_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR4_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR4_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR4_COMPARE10_Msk (0x1UL << GRTC_INTENCLR4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR4_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR4_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR4_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR4_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR4_COMPARE11_Msk (0x1UL << GRTC_INTENCLR4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR4_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR4_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR4_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR4_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR4_COMPARE12_Msk (0x1UL << GRTC_INTENCLR4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR4_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR4_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR4_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR4_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR4_COMPARE13_Msk (0x1UL << GRTC_INTENCLR4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR4_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR4_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR4_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR4_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR4_COMPARE14_Msk (0x1UL << GRTC_INTENCLR4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR4_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR4_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR4_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR4_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR4_COMPARE15_Msk (0x1UL << GRTC_INTENCLR4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR4_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR4_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR4_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR4_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR4_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR4_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR4_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR4_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR4_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR4_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR4_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR4_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND4: Pending interrupts */ + #define GRTC_INTPEND4_ResetValue (0x00000000UL) /*!< Reset value of INTPEND4 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND4_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND4_COMPARE0_Msk (0x1UL << GRTC_INTPEND4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND4_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND4_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND4_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND4_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND4_COMPARE1_Msk (0x1UL << GRTC_INTPEND4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND4_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND4_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND4_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND4_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND4_COMPARE2_Msk (0x1UL << GRTC_INTPEND4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND4_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND4_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND4_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND4_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND4_COMPARE3_Msk (0x1UL << GRTC_INTPEND4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND4_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND4_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND4_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND4_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND4_COMPARE4_Msk (0x1UL << GRTC_INTPEND4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND4_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND4_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND4_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND4_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND4_COMPARE5_Msk (0x1UL << GRTC_INTPEND4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND4_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND4_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND4_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND4_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND4_COMPARE6_Msk (0x1UL << GRTC_INTPEND4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND4_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND4_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND4_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND4_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND4_COMPARE7_Msk (0x1UL << GRTC_INTPEND4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND4_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND4_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND4_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND4_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND4_COMPARE8_Msk (0x1UL << GRTC_INTPEND4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND4_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND4_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND4_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND4_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND4_COMPARE9_Msk (0x1UL << GRTC_INTPEND4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND4_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND4_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND4_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND4_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND4_COMPARE10_Msk (0x1UL << GRTC_INTPEND4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND4_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND4_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND4_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND4_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND4_COMPARE11_Msk (0x1UL << GRTC_INTPEND4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND4_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND4_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND4_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND4_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND4_COMPARE12_Msk (0x1UL << GRTC_INTPEND4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND4_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND4_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND4_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND4_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND4_COMPARE13_Msk (0x1UL << GRTC_INTPEND4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND4_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND4_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND4_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND4_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND4_COMPARE14_Msk (0x1UL << GRTC_INTPEND4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND4_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND4_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND4_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND4_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND4_COMPARE15_Msk (0x1UL << GRTC_INTPEND4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND4_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND4_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND4_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND4_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND4_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND4_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND4_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND4_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND4_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND4_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND4_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND4_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND4_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND4_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND4_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND4_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND4_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND4_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN5: Enable or disable interrupt */ + #define GRTC_INTEN5_ResetValue (0x00000000UL) /*!< Reset value of INTEN5 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN5_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN5_COMPARE0_Msk (0x1UL << GRTC_INTEN5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN5_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN5_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN5_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN5_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN5_COMPARE1_Msk (0x1UL << GRTC_INTEN5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN5_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN5_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN5_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN5_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN5_COMPARE2_Msk (0x1UL << GRTC_INTEN5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN5_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN5_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN5_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN5_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN5_COMPARE3_Msk (0x1UL << GRTC_INTEN5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN5_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN5_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN5_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN5_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN5_COMPARE4_Msk (0x1UL << GRTC_INTEN5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN5_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN5_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN5_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN5_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN5_COMPARE5_Msk (0x1UL << GRTC_INTEN5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN5_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN5_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN5_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN5_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN5_COMPARE6_Msk (0x1UL << GRTC_INTEN5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN5_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN5_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN5_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN5_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN5_COMPARE7_Msk (0x1UL << GRTC_INTEN5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN5_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN5_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN5_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN5_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN5_COMPARE8_Msk (0x1UL << GRTC_INTEN5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN5_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN5_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN5_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN5_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN5_COMPARE9_Msk (0x1UL << GRTC_INTEN5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN5_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN5_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN5_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN5_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN5_COMPARE10_Msk (0x1UL << GRTC_INTEN5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN5_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN5_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN5_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN5_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN5_COMPARE11_Msk (0x1UL << GRTC_INTEN5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN5_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN5_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN5_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN5_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN5_COMPARE12_Msk (0x1UL << GRTC_INTEN5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN5_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN5_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN5_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN5_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN5_COMPARE13_Msk (0x1UL << GRTC_INTEN5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN5_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN5_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN5_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN5_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN5_COMPARE14_Msk (0x1UL << GRTC_INTEN5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN5_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN5_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN5_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN5_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN5_COMPARE15_Msk (0x1UL << GRTC_INTEN5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN5_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN5_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN5_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN5_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN5_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN5_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN5_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN5_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN5_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN5_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN5_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN5_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN5_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN5_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN5_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN5_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET5: Enable interrupt */ + #define GRTC_INTENSET5_ResetValue (0x00000000UL) /*!< Reset value of INTENSET5 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET5_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET5_COMPARE0_Msk (0x1UL << GRTC_INTENSET5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET5_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET5_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET5_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET5_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET5_COMPARE1_Msk (0x1UL << GRTC_INTENSET5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET5_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET5_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET5_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET5_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET5_COMPARE2_Msk (0x1UL << GRTC_INTENSET5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET5_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET5_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET5_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET5_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET5_COMPARE3_Msk (0x1UL << GRTC_INTENSET5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET5_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET5_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET5_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET5_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET5_COMPARE4_Msk (0x1UL << GRTC_INTENSET5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET5_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET5_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET5_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET5_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET5_COMPARE5_Msk (0x1UL << GRTC_INTENSET5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET5_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET5_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET5_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET5_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET5_COMPARE6_Msk (0x1UL << GRTC_INTENSET5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET5_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET5_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET5_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET5_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET5_COMPARE7_Msk (0x1UL << GRTC_INTENSET5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET5_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET5_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET5_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET5_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET5_COMPARE8_Msk (0x1UL << GRTC_INTENSET5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET5_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET5_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET5_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET5_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET5_COMPARE9_Msk (0x1UL << GRTC_INTENSET5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET5_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET5_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET5_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET5_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET5_COMPARE10_Msk (0x1UL << GRTC_INTENSET5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET5_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET5_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET5_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET5_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET5_COMPARE11_Msk (0x1UL << GRTC_INTENSET5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET5_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET5_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET5_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET5_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET5_COMPARE12_Msk (0x1UL << GRTC_INTENSET5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET5_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET5_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET5_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET5_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET5_COMPARE13_Msk (0x1UL << GRTC_INTENSET5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET5_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET5_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET5_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET5_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET5_COMPARE14_Msk (0x1UL << GRTC_INTENSET5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET5_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET5_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET5_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET5_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET5_COMPARE15_Msk (0x1UL << GRTC_INTENSET5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET5_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET5_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET5_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET5_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET5_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET5_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET5_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET5_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET5_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET5_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET5_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET5_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR5: Disable interrupt */ + #define GRTC_INTENCLR5_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR5 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR5_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR5_COMPARE0_Msk (0x1UL << GRTC_INTENCLR5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR5_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR5_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR5_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR5_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR5_COMPARE1_Msk (0x1UL << GRTC_INTENCLR5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR5_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR5_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR5_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR5_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR5_COMPARE2_Msk (0x1UL << GRTC_INTENCLR5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR5_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR5_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR5_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR5_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR5_COMPARE3_Msk (0x1UL << GRTC_INTENCLR5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR5_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR5_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR5_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR5_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR5_COMPARE4_Msk (0x1UL << GRTC_INTENCLR5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR5_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR5_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR5_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR5_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR5_COMPARE5_Msk (0x1UL << GRTC_INTENCLR5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR5_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR5_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR5_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR5_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR5_COMPARE6_Msk (0x1UL << GRTC_INTENCLR5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR5_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR5_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR5_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR5_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR5_COMPARE7_Msk (0x1UL << GRTC_INTENCLR5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR5_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR5_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR5_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR5_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR5_COMPARE8_Msk (0x1UL << GRTC_INTENCLR5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR5_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR5_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR5_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR5_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR5_COMPARE9_Msk (0x1UL << GRTC_INTENCLR5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR5_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR5_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR5_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR5_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR5_COMPARE10_Msk (0x1UL << GRTC_INTENCLR5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR5_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR5_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR5_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR5_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR5_COMPARE11_Msk (0x1UL << GRTC_INTENCLR5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR5_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR5_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR5_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR5_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR5_COMPARE12_Msk (0x1UL << GRTC_INTENCLR5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR5_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR5_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR5_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR5_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR5_COMPARE13_Msk (0x1UL << GRTC_INTENCLR5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR5_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR5_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR5_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR5_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR5_COMPARE14_Msk (0x1UL << GRTC_INTENCLR5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR5_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR5_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR5_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR5_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR5_COMPARE15_Msk (0x1UL << GRTC_INTENCLR5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR5_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR5_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR5_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR5_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR5_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR5_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR5_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR5_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR5_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR5_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR5_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR5_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND5: Pending interrupts */ + #define GRTC_INTPEND5_ResetValue (0x00000000UL) /*!< Reset value of INTPEND5 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND5_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND5_COMPARE0_Msk (0x1UL << GRTC_INTPEND5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND5_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND5_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND5_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND5_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND5_COMPARE1_Msk (0x1UL << GRTC_INTPEND5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND5_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND5_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND5_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND5_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND5_COMPARE2_Msk (0x1UL << GRTC_INTPEND5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND5_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND5_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND5_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND5_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND5_COMPARE3_Msk (0x1UL << GRTC_INTPEND5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND5_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND5_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND5_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND5_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND5_COMPARE4_Msk (0x1UL << GRTC_INTPEND5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND5_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND5_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND5_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND5_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND5_COMPARE5_Msk (0x1UL << GRTC_INTPEND5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND5_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND5_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND5_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND5_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND5_COMPARE6_Msk (0x1UL << GRTC_INTPEND5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND5_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND5_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND5_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND5_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND5_COMPARE7_Msk (0x1UL << GRTC_INTPEND5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND5_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND5_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND5_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND5_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND5_COMPARE8_Msk (0x1UL << GRTC_INTPEND5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND5_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND5_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND5_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND5_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND5_COMPARE9_Msk (0x1UL << GRTC_INTPEND5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND5_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND5_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND5_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND5_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND5_COMPARE10_Msk (0x1UL << GRTC_INTPEND5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND5_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND5_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND5_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND5_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND5_COMPARE11_Msk (0x1UL << GRTC_INTPEND5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND5_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND5_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND5_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND5_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND5_COMPARE12_Msk (0x1UL << GRTC_INTPEND5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND5_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND5_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND5_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND5_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND5_COMPARE13_Msk (0x1UL << GRTC_INTPEND5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND5_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND5_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND5_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND5_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND5_COMPARE14_Msk (0x1UL << GRTC_INTPEND5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND5_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND5_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND5_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND5_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND5_COMPARE15_Msk (0x1UL << GRTC_INTPEND5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND5_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND5_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND5_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND5_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND5_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND5_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND5_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND5_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND5_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND5_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND5_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND5_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND5_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND5_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND5_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND5_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND5_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND5_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN6: Enable or disable interrupt */ + #define GRTC_INTEN6_ResetValue (0x00000000UL) /*!< Reset value of INTEN6 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN6_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN6_COMPARE0_Msk (0x1UL << GRTC_INTEN6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN6_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN6_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN6_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN6_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN6_COMPARE1_Msk (0x1UL << GRTC_INTEN6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN6_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN6_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN6_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN6_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN6_COMPARE2_Msk (0x1UL << GRTC_INTEN6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN6_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN6_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN6_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN6_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN6_COMPARE3_Msk (0x1UL << GRTC_INTEN6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN6_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN6_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN6_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN6_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN6_COMPARE4_Msk (0x1UL << GRTC_INTEN6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN6_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN6_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN6_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN6_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN6_COMPARE5_Msk (0x1UL << GRTC_INTEN6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN6_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN6_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN6_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN6_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN6_COMPARE6_Msk (0x1UL << GRTC_INTEN6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN6_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN6_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN6_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN6_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN6_COMPARE7_Msk (0x1UL << GRTC_INTEN6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN6_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN6_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN6_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN6_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN6_COMPARE8_Msk (0x1UL << GRTC_INTEN6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN6_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN6_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN6_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN6_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN6_COMPARE9_Msk (0x1UL << GRTC_INTEN6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN6_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN6_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN6_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN6_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN6_COMPARE10_Msk (0x1UL << GRTC_INTEN6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN6_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN6_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN6_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN6_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN6_COMPARE11_Msk (0x1UL << GRTC_INTEN6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN6_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN6_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN6_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN6_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN6_COMPARE12_Msk (0x1UL << GRTC_INTEN6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN6_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN6_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN6_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN6_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN6_COMPARE13_Msk (0x1UL << GRTC_INTEN6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN6_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN6_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN6_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN6_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN6_COMPARE14_Msk (0x1UL << GRTC_INTEN6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN6_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN6_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN6_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN6_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN6_COMPARE15_Msk (0x1UL << GRTC_INTEN6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN6_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN6_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN6_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN6_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN6_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN6_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN6_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN6_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN6_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN6_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN6_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN6_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN6_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN6_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN6_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN6_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET6: Enable interrupt */ + #define GRTC_INTENSET6_ResetValue (0x00000000UL) /*!< Reset value of INTENSET6 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET6_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET6_COMPARE0_Msk (0x1UL << GRTC_INTENSET6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET6_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET6_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET6_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET6_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET6_COMPARE1_Msk (0x1UL << GRTC_INTENSET6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET6_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET6_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET6_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET6_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET6_COMPARE2_Msk (0x1UL << GRTC_INTENSET6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET6_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET6_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET6_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET6_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET6_COMPARE3_Msk (0x1UL << GRTC_INTENSET6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET6_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET6_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET6_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET6_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET6_COMPARE4_Msk (0x1UL << GRTC_INTENSET6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET6_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET6_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET6_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET6_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET6_COMPARE5_Msk (0x1UL << GRTC_INTENSET6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET6_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET6_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET6_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET6_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET6_COMPARE6_Msk (0x1UL << GRTC_INTENSET6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET6_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET6_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET6_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET6_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET6_COMPARE7_Msk (0x1UL << GRTC_INTENSET6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET6_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET6_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET6_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET6_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET6_COMPARE8_Msk (0x1UL << GRTC_INTENSET6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET6_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET6_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET6_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET6_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET6_COMPARE9_Msk (0x1UL << GRTC_INTENSET6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET6_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET6_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET6_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET6_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET6_COMPARE10_Msk (0x1UL << GRTC_INTENSET6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET6_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET6_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET6_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET6_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET6_COMPARE11_Msk (0x1UL << GRTC_INTENSET6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET6_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET6_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET6_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET6_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET6_COMPARE12_Msk (0x1UL << GRTC_INTENSET6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET6_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET6_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET6_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET6_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET6_COMPARE13_Msk (0x1UL << GRTC_INTENSET6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET6_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET6_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET6_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET6_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET6_COMPARE14_Msk (0x1UL << GRTC_INTENSET6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET6_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET6_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET6_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET6_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET6_COMPARE15_Msk (0x1UL << GRTC_INTENSET6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET6_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET6_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET6_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET6_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET6_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET6_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET6_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET6_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET6_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET6_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET6_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET6_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR6: Disable interrupt */ + #define GRTC_INTENCLR6_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR6 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR6_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR6_COMPARE0_Msk (0x1UL << GRTC_INTENCLR6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR6_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR6_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR6_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR6_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR6_COMPARE1_Msk (0x1UL << GRTC_INTENCLR6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR6_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR6_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR6_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR6_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR6_COMPARE2_Msk (0x1UL << GRTC_INTENCLR6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR6_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR6_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR6_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR6_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR6_COMPARE3_Msk (0x1UL << GRTC_INTENCLR6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR6_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR6_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR6_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR6_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR6_COMPARE4_Msk (0x1UL << GRTC_INTENCLR6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR6_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR6_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR6_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR6_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR6_COMPARE5_Msk (0x1UL << GRTC_INTENCLR6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR6_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR6_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR6_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR6_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR6_COMPARE6_Msk (0x1UL << GRTC_INTENCLR6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR6_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR6_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR6_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR6_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR6_COMPARE7_Msk (0x1UL << GRTC_INTENCLR6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR6_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR6_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR6_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR6_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR6_COMPARE8_Msk (0x1UL << GRTC_INTENCLR6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR6_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR6_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR6_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR6_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR6_COMPARE9_Msk (0x1UL << GRTC_INTENCLR6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR6_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR6_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR6_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR6_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR6_COMPARE10_Msk (0x1UL << GRTC_INTENCLR6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR6_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR6_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR6_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR6_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR6_COMPARE11_Msk (0x1UL << GRTC_INTENCLR6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR6_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR6_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR6_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR6_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR6_COMPARE12_Msk (0x1UL << GRTC_INTENCLR6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR6_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR6_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR6_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR6_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR6_COMPARE13_Msk (0x1UL << GRTC_INTENCLR6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR6_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR6_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR6_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR6_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR6_COMPARE14_Msk (0x1UL << GRTC_INTENCLR6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR6_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR6_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR6_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR6_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR6_COMPARE15_Msk (0x1UL << GRTC_INTENCLR6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR6_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR6_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR6_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR6_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR6_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR6_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR6_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR6_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR6_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR6_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR6_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR6_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND6: Pending interrupts */ + #define GRTC_INTPEND6_ResetValue (0x00000000UL) /*!< Reset value of INTPEND6 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND6_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND6_COMPARE0_Msk (0x1UL << GRTC_INTPEND6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND6_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND6_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND6_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND6_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND6_COMPARE1_Msk (0x1UL << GRTC_INTPEND6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND6_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND6_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND6_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND6_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND6_COMPARE2_Msk (0x1UL << GRTC_INTPEND6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND6_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND6_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND6_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND6_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND6_COMPARE3_Msk (0x1UL << GRTC_INTPEND6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND6_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND6_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND6_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND6_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND6_COMPARE4_Msk (0x1UL << GRTC_INTPEND6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND6_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND6_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND6_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND6_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND6_COMPARE5_Msk (0x1UL << GRTC_INTPEND6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND6_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND6_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND6_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND6_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND6_COMPARE6_Msk (0x1UL << GRTC_INTPEND6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND6_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND6_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND6_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND6_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND6_COMPARE7_Msk (0x1UL << GRTC_INTPEND6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND6_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND6_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND6_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND6_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND6_COMPARE8_Msk (0x1UL << GRTC_INTPEND6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND6_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND6_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND6_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND6_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND6_COMPARE9_Msk (0x1UL << GRTC_INTPEND6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND6_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND6_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND6_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND6_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND6_COMPARE10_Msk (0x1UL << GRTC_INTPEND6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND6_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND6_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND6_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND6_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND6_COMPARE11_Msk (0x1UL << GRTC_INTPEND6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND6_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND6_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND6_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND6_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND6_COMPARE12_Msk (0x1UL << GRTC_INTPEND6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND6_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND6_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND6_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND6_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND6_COMPARE13_Msk (0x1UL << GRTC_INTPEND6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND6_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND6_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND6_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND6_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND6_COMPARE14_Msk (0x1UL << GRTC_INTPEND6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND6_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND6_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND6_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND6_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND6_COMPARE15_Msk (0x1UL << GRTC_INTPEND6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND6_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND6_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND6_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND6_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND6_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND6_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND6_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND6_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND6_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND6_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND6_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND6_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND6_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND6_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND6_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND6_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND6_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND6_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN7: Enable or disable interrupt */ + #define GRTC_INTEN7_ResetValue (0x00000000UL) /*!< Reset value of INTEN7 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN7_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN7_COMPARE0_Msk (0x1UL << GRTC_INTEN7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN7_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN7_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN7_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN7_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN7_COMPARE1_Msk (0x1UL << GRTC_INTEN7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN7_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN7_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN7_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN7_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN7_COMPARE2_Msk (0x1UL << GRTC_INTEN7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN7_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN7_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN7_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN7_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN7_COMPARE3_Msk (0x1UL << GRTC_INTEN7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN7_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN7_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN7_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN7_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN7_COMPARE4_Msk (0x1UL << GRTC_INTEN7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN7_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN7_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN7_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN7_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN7_COMPARE5_Msk (0x1UL << GRTC_INTEN7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN7_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN7_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN7_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN7_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN7_COMPARE6_Msk (0x1UL << GRTC_INTEN7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN7_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN7_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN7_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN7_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN7_COMPARE7_Msk (0x1UL << GRTC_INTEN7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN7_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN7_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN7_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN7_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN7_COMPARE8_Msk (0x1UL << GRTC_INTEN7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN7_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN7_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN7_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN7_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN7_COMPARE9_Msk (0x1UL << GRTC_INTEN7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN7_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN7_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN7_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN7_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN7_COMPARE10_Msk (0x1UL << GRTC_INTEN7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN7_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN7_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN7_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN7_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN7_COMPARE11_Msk (0x1UL << GRTC_INTEN7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN7_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN7_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN7_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN7_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN7_COMPARE12_Msk (0x1UL << GRTC_INTEN7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN7_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN7_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN7_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN7_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN7_COMPARE13_Msk (0x1UL << GRTC_INTEN7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN7_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN7_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN7_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN7_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN7_COMPARE14_Msk (0x1UL << GRTC_INTEN7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN7_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN7_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN7_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN7_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN7_COMPARE15_Msk (0x1UL << GRTC_INTEN7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN7_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN7_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN7_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN7_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN7_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN7_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN7_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN7_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN7_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN7_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN7_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN7_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN7_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN7_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN7_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN7_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET7: Enable interrupt */ + #define GRTC_INTENSET7_ResetValue (0x00000000UL) /*!< Reset value of INTENSET7 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET7_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET7_COMPARE0_Msk (0x1UL << GRTC_INTENSET7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET7_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET7_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET7_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET7_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET7_COMPARE1_Msk (0x1UL << GRTC_INTENSET7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET7_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET7_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET7_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET7_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET7_COMPARE2_Msk (0x1UL << GRTC_INTENSET7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET7_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET7_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET7_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET7_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET7_COMPARE3_Msk (0x1UL << GRTC_INTENSET7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET7_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET7_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET7_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET7_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET7_COMPARE4_Msk (0x1UL << GRTC_INTENSET7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET7_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET7_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET7_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET7_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET7_COMPARE5_Msk (0x1UL << GRTC_INTENSET7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET7_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET7_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET7_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET7_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET7_COMPARE6_Msk (0x1UL << GRTC_INTENSET7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET7_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET7_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET7_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET7_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET7_COMPARE7_Msk (0x1UL << GRTC_INTENSET7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET7_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET7_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET7_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET7_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET7_COMPARE8_Msk (0x1UL << GRTC_INTENSET7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET7_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET7_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET7_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET7_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET7_COMPARE9_Msk (0x1UL << GRTC_INTENSET7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET7_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET7_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET7_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET7_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET7_COMPARE10_Msk (0x1UL << GRTC_INTENSET7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET7_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET7_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET7_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET7_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET7_COMPARE11_Msk (0x1UL << GRTC_INTENSET7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET7_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET7_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET7_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET7_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET7_COMPARE12_Msk (0x1UL << GRTC_INTENSET7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET7_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET7_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET7_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET7_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET7_COMPARE13_Msk (0x1UL << GRTC_INTENSET7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET7_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET7_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET7_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET7_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET7_COMPARE14_Msk (0x1UL << GRTC_INTENSET7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET7_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET7_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET7_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET7_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET7_COMPARE15_Msk (0x1UL << GRTC_INTENSET7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET7_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET7_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET7_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET7_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET7_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET7_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET7_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET7_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET7_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET7_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET7_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET7_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR7: Disable interrupt */ + #define GRTC_INTENCLR7_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR7 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR7_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR7_COMPARE0_Msk (0x1UL << GRTC_INTENCLR7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR7_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR7_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR7_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR7_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR7_COMPARE1_Msk (0x1UL << GRTC_INTENCLR7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR7_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR7_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR7_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR7_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR7_COMPARE2_Msk (0x1UL << GRTC_INTENCLR7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR7_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR7_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR7_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR7_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR7_COMPARE3_Msk (0x1UL << GRTC_INTENCLR7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR7_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR7_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR7_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR7_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR7_COMPARE4_Msk (0x1UL << GRTC_INTENCLR7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR7_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR7_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR7_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR7_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR7_COMPARE5_Msk (0x1UL << GRTC_INTENCLR7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR7_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR7_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR7_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR7_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR7_COMPARE6_Msk (0x1UL << GRTC_INTENCLR7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR7_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR7_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR7_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR7_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR7_COMPARE7_Msk (0x1UL << GRTC_INTENCLR7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR7_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR7_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR7_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR7_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR7_COMPARE8_Msk (0x1UL << GRTC_INTENCLR7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR7_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR7_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR7_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR7_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR7_COMPARE9_Msk (0x1UL << GRTC_INTENCLR7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR7_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR7_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR7_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR7_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR7_COMPARE10_Msk (0x1UL << GRTC_INTENCLR7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR7_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR7_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR7_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR7_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR7_COMPARE11_Msk (0x1UL << GRTC_INTENCLR7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR7_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR7_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR7_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR7_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR7_COMPARE12_Msk (0x1UL << GRTC_INTENCLR7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR7_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR7_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR7_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR7_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR7_COMPARE13_Msk (0x1UL << GRTC_INTENCLR7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR7_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR7_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR7_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR7_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR7_COMPARE14_Msk (0x1UL << GRTC_INTENCLR7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR7_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR7_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR7_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR7_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR7_COMPARE15_Msk (0x1UL << GRTC_INTENCLR7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR7_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR7_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR7_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR7_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR7_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR7_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR7_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR7_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR7_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR7_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR7_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR7_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND7: Pending interrupts */ + #define GRTC_INTPEND7_ResetValue (0x00000000UL) /*!< Reset value of INTPEND7 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND7_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND7_COMPARE0_Msk (0x1UL << GRTC_INTPEND7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND7_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND7_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND7_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND7_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND7_COMPARE1_Msk (0x1UL << GRTC_INTPEND7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND7_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND7_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND7_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND7_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND7_COMPARE2_Msk (0x1UL << GRTC_INTPEND7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND7_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND7_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND7_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND7_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND7_COMPARE3_Msk (0x1UL << GRTC_INTPEND7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND7_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND7_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND7_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND7_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND7_COMPARE4_Msk (0x1UL << GRTC_INTPEND7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND7_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND7_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND7_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND7_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND7_COMPARE5_Msk (0x1UL << GRTC_INTPEND7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND7_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND7_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND7_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND7_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND7_COMPARE6_Msk (0x1UL << GRTC_INTPEND7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND7_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND7_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND7_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND7_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND7_COMPARE7_Msk (0x1UL << GRTC_INTPEND7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND7_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND7_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND7_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND7_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND7_COMPARE8_Msk (0x1UL << GRTC_INTPEND7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND7_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND7_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND7_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND7_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND7_COMPARE9_Msk (0x1UL << GRTC_INTPEND7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND7_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND7_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND7_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND7_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND7_COMPARE10_Msk (0x1UL << GRTC_INTPEND7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND7_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND7_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND7_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND7_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND7_COMPARE11_Msk (0x1UL << GRTC_INTPEND7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND7_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND7_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND7_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND7_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND7_COMPARE12_Msk (0x1UL << GRTC_INTPEND7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND7_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND7_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND7_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND7_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND7_COMPARE13_Msk (0x1UL << GRTC_INTPEND7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND7_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND7_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND7_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND7_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND7_COMPARE14_Msk (0x1UL << GRTC_INTPEND7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND7_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND7_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND7_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND7_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND7_COMPARE15_Msk (0x1UL << GRTC_INTPEND7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND7_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND7_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND7_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND7_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND7_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND7_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND7_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND7_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND7_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND7_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND7_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND7_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND7_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND7_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND7_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND7_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND7_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND7_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN8: Enable or disable interrupt */ + #define GRTC_INTEN8_ResetValue (0x00000000UL) /*!< Reset value of INTEN8 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN8_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN8_COMPARE0_Msk (0x1UL << GRTC_INTEN8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN8_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN8_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN8_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN8_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN8_COMPARE1_Msk (0x1UL << GRTC_INTEN8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN8_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN8_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN8_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN8_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN8_COMPARE2_Msk (0x1UL << GRTC_INTEN8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN8_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN8_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN8_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN8_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN8_COMPARE3_Msk (0x1UL << GRTC_INTEN8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN8_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN8_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN8_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN8_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN8_COMPARE4_Msk (0x1UL << GRTC_INTEN8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN8_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN8_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN8_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN8_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN8_COMPARE5_Msk (0x1UL << GRTC_INTEN8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN8_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN8_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN8_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN8_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN8_COMPARE6_Msk (0x1UL << GRTC_INTEN8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN8_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN8_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN8_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN8_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN8_COMPARE7_Msk (0x1UL << GRTC_INTEN8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN8_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN8_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN8_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN8_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN8_COMPARE8_Msk (0x1UL << GRTC_INTEN8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN8_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN8_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN8_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN8_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN8_COMPARE9_Msk (0x1UL << GRTC_INTEN8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN8_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN8_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN8_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN8_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN8_COMPARE10_Msk (0x1UL << GRTC_INTEN8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN8_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN8_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN8_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN8_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN8_COMPARE11_Msk (0x1UL << GRTC_INTEN8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN8_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN8_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN8_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN8_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN8_COMPARE12_Msk (0x1UL << GRTC_INTEN8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN8_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN8_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN8_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN8_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN8_COMPARE13_Msk (0x1UL << GRTC_INTEN8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN8_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN8_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN8_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN8_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN8_COMPARE14_Msk (0x1UL << GRTC_INTEN8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN8_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN8_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN8_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN8_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN8_COMPARE15_Msk (0x1UL << GRTC_INTEN8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN8_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN8_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN8_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN8_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN8_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN8_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN8_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN8_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN8_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN8_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN8_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN8_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN8_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN8_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN8_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN8_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET8: Enable interrupt */ + #define GRTC_INTENSET8_ResetValue (0x00000000UL) /*!< Reset value of INTENSET8 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET8_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET8_COMPARE0_Msk (0x1UL << GRTC_INTENSET8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET8_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET8_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET8_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET8_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET8_COMPARE1_Msk (0x1UL << GRTC_INTENSET8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET8_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET8_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET8_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET8_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET8_COMPARE2_Msk (0x1UL << GRTC_INTENSET8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET8_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET8_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET8_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET8_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET8_COMPARE3_Msk (0x1UL << GRTC_INTENSET8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET8_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET8_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET8_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET8_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET8_COMPARE4_Msk (0x1UL << GRTC_INTENSET8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET8_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET8_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET8_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET8_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET8_COMPARE5_Msk (0x1UL << GRTC_INTENSET8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET8_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET8_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET8_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET8_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET8_COMPARE6_Msk (0x1UL << GRTC_INTENSET8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET8_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET8_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET8_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET8_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET8_COMPARE7_Msk (0x1UL << GRTC_INTENSET8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET8_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET8_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET8_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET8_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET8_COMPARE8_Msk (0x1UL << GRTC_INTENSET8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET8_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET8_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET8_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET8_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET8_COMPARE9_Msk (0x1UL << GRTC_INTENSET8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET8_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET8_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET8_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET8_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET8_COMPARE10_Msk (0x1UL << GRTC_INTENSET8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET8_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET8_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET8_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET8_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET8_COMPARE11_Msk (0x1UL << GRTC_INTENSET8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET8_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET8_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET8_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET8_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET8_COMPARE12_Msk (0x1UL << GRTC_INTENSET8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET8_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET8_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET8_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET8_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET8_COMPARE13_Msk (0x1UL << GRTC_INTENSET8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET8_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET8_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET8_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET8_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET8_COMPARE14_Msk (0x1UL << GRTC_INTENSET8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET8_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET8_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET8_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET8_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET8_COMPARE15_Msk (0x1UL << GRTC_INTENSET8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET8_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET8_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET8_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET8_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET8_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET8_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET8_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET8_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET8_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET8_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET8_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET8_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR8: Disable interrupt */ + #define GRTC_INTENCLR8_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR8 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR8_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR8_COMPARE0_Msk (0x1UL << GRTC_INTENCLR8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR8_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR8_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR8_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR8_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR8_COMPARE1_Msk (0x1UL << GRTC_INTENCLR8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR8_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR8_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR8_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR8_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR8_COMPARE2_Msk (0x1UL << GRTC_INTENCLR8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR8_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR8_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR8_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR8_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR8_COMPARE3_Msk (0x1UL << GRTC_INTENCLR8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR8_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR8_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR8_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR8_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR8_COMPARE4_Msk (0x1UL << GRTC_INTENCLR8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR8_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR8_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR8_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR8_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR8_COMPARE5_Msk (0x1UL << GRTC_INTENCLR8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR8_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR8_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR8_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR8_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR8_COMPARE6_Msk (0x1UL << GRTC_INTENCLR8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR8_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR8_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR8_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR8_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR8_COMPARE7_Msk (0x1UL << GRTC_INTENCLR8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR8_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR8_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR8_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR8_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR8_COMPARE8_Msk (0x1UL << GRTC_INTENCLR8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR8_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR8_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR8_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR8_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR8_COMPARE9_Msk (0x1UL << GRTC_INTENCLR8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR8_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR8_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR8_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR8_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR8_COMPARE10_Msk (0x1UL << GRTC_INTENCLR8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR8_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR8_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR8_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR8_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR8_COMPARE11_Msk (0x1UL << GRTC_INTENCLR8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR8_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR8_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR8_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR8_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR8_COMPARE12_Msk (0x1UL << GRTC_INTENCLR8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR8_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR8_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR8_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR8_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR8_COMPARE13_Msk (0x1UL << GRTC_INTENCLR8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR8_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR8_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR8_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR8_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR8_COMPARE14_Msk (0x1UL << GRTC_INTENCLR8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR8_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR8_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR8_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR8_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR8_COMPARE15_Msk (0x1UL << GRTC_INTENCLR8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR8_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR8_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR8_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR8_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR8_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR8_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR8_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR8_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR8_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR8_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR8_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR8_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND8: Pending interrupts */ + #define GRTC_INTPEND8_ResetValue (0x00000000UL) /*!< Reset value of INTPEND8 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND8_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND8_COMPARE0_Msk (0x1UL << GRTC_INTPEND8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND8_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND8_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND8_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND8_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND8_COMPARE1_Msk (0x1UL << GRTC_INTPEND8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND8_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND8_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND8_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND8_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND8_COMPARE2_Msk (0x1UL << GRTC_INTPEND8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND8_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND8_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND8_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND8_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND8_COMPARE3_Msk (0x1UL << GRTC_INTPEND8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND8_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND8_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND8_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND8_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND8_COMPARE4_Msk (0x1UL << GRTC_INTPEND8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND8_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND8_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND8_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND8_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND8_COMPARE5_Msk (0x1UL << GRTC_INTPEND8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND8_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND8_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND8_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND8_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND8_COMPARE6_Msk (0x1UL << GRTC_INTPEND8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND8_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND8_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND8_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND8_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND8_COMPARE7_Msk (0x1UL << GRTC_INTPEND8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND8_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND8_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND8_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND8_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND8_COMPARE8_Msk (0x1UL << GRTC_INTPEND8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND8_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND8_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND8_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND8_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND8_COMPARE9_Msk (0x1UL << GRTC_INTPEND8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND8_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND8_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND8_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND8_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND8_COMPARE10_Msk (0x1UL << GRTC_INTPEND8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND8_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND8_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND8_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND8_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND8_COMPARE11_Msk (0x1UL << GRTC_INTPEND8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND8_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND8_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND8_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND8_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND8_COMPARE12_Msk (0x1UL << GRTC_INTPEND8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND8_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND8_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND8_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND8_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND8_COMPARE13_Msk (0x1UL << GRTC_INTPEND8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND8_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND8_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND8_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND8_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND8_COMPARE14_Msk (0x1UL << GRTC_INTPEND8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND8_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND8_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND8_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND8_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND8_COMPARE15_Msk (0x1UL << GRTC_INTPEND8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND8_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND8_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND8_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND8_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND8_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND8_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND8_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND8_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND8_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND8_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND8_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND8_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND8_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND8_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND8_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND8_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND8_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND8_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN9: Enable or disable interrupt */ + #define GRTC_INTEN9_ResetValue (0x00000000UL) /*!< Reset value of INTEN9 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN9_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN9_COMPARE0_Msk (0x1UL << GRTC_INTEN9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN9_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN9_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN9_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN9_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN9_COMPARE1_Msk (0x1UL << GRTC_INTEN9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN9_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN9_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN9_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN9_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN9_COMPARE2_Msk (0x1UL << GRTC_INTEN9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN9_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN9_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN9_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN9_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN9_COMPARE3_Msk (0x1UL << GRTC_INTEN9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN9_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN9_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN9_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN9_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN9_COMPARE4_Msk (0x1UL << GRTC_INTEN9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN9_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN9_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN9_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN9_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN9_COMPARE5_Msk (0x1UL << GRTC_INTEN9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN9_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN9_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN9_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN9_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN9_COMPARE6_Msk (0x1UL << GRTC_INTEN9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN9_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN9_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN9_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN9_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN9_COMPARE7_Msk (0x1UL << GRTC_INTEN9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN9_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN9_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN9_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN9_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN9_COMPARE8_Msk (0x1UL << GRTC_INTEN9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN9_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN9_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN9_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN9_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN9_COMPARE9_Msk (0x1UL << GRTC_INTEN9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN9_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN9_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN9_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN9_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN9_COMPARE10_Msk (0x1UL << GRTC_INTEN9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN9_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN9_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN9_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN9_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN9_COMPARE11_Msk (0x1UL << GRTC_INTEN9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN9_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN9_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN9_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN9_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN9_COMPARE12_Msk (0x1UL << GRTC_INTEN9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN9_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN9_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN9_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN9_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN9_COMPARE13_Msk (0x1UL << GRTC_INTEN9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN9_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN9_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN9_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN9_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN9_COMPARE14_Msk (0x1UL << GRTC_INTEN9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN9_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN9_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN9_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN9_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN9_COMPARE15_Msk (0x1UL << GRTC_INTEN9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN9_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN9_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN9_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN9_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN9_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN9_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN9_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN9_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN9_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN9_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN9_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN9_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN9_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN9_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN9_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN9_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET9: Enable interrupt */ + #define GRTC_INTENSET9_ResetValue (0x00000000UL) /*!< Reset value of INTENSET9 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET9_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET9_COMPARE0_Msk (0x1UL << GRTC_INTENSET9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET9_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET9_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET9_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET9_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET9_COMPARE1_Msk (0x1UL << GRTC_INTENSET9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET9_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET9_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET9_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET9_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET9_COMPARE2_Msk (0x1UL << GRTC_INTENSET9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET9_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET9_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET9_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET9_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET9_COMPARE3_Msk (0x1UL << GRTC_INTENSET9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET9_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET9_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET9_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET9_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET9_COMPARE4_Msk (0x1UL << GRTC_INTENSET9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET9_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET9_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET9_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET9_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET9_COMPARE5_Msk (0x1UL << GRTC_INTENSET9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET9_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET9_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET9_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET9_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET9_COMPARE6_Msk (0x1UL << GRTC_INTENSET9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET9_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET9_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET9_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET9_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET9_COMPARE7_Msk (0x1UL << GRTC_INTENSET9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET9_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET9_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET9_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET9_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET9_COMPARE8_Msk (0x1UL << GRTC_INTENSET9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET9_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET9_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET9_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET9_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET9_COMPARE9_Msk (0x1UL << GRTC_INTENSET9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET9_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET9_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET9_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET9_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET9_COMPARE10_Msk (0x1UL << GRTC_INTENSET9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET9_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET9_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET9_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET9_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET9_COMPARE11_Msk (0x1UL << GRTC_INTENSET9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET9_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET9_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET9_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET9_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET9_COMPARE12_Msk (0x1UL << GRTC_INTENSET9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET9_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET9_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET9_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET9_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET9_COMPARE13_Msk (0x1UL << GRTC_INTENSET9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET9_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET9_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET9_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET9_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET9_COMPARE14_Msk (0x1UL << GRTC_INTENSET9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET9_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET9_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET9_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET9_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET9_COMPARE15_Msk (0x1UL << GRTC_INTENSET9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET9_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET9_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET9_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET9_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET9_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET9_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET9_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET9_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET9_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET9_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET9_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET9_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR9: Disable interrupt */ + #define GRTC_INTENCLR9_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR9 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR9_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR9_COMPARE0_Msk (0x1UL << GRTC_INTENCLR9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR9_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR9_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR9_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR9_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR9_COMPARE1_Msk (0x1UL << GRTC_INTENCLR9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR9_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR9_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR9_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR9_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR9_COMPARE2_Msk (0x1UL << GRTC_INTENCLR9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR9_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR9_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR9_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR9_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR9_COMPARE3_Msk (0x1UL << GRTC_INTENCLR9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR9_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR9_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR9_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR9_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR9_COMPARE4_Msk (0x1UL << GRTC_INTENCLR9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR9_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR9_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR9_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR9_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR9_COMPARE5_Msk (0x1UL << GRTC_INTENCLR9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR9_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR9_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR9_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR9_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR9_COMPARE6_Msk (0x1UL << GRTC_INTENCLR9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR9_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR9_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR9_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR9_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR9_COMPARE7_Msk (0x1UL << GRTC_INTENCLR9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR9_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR9_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR9_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR9_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR9_COMPARE8_Msk (0x1UL << GRTC_INTENCLR9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR9_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR9_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR9_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR9_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR9_COMPARE9_Msk (0x1UL << GRTC_INTENCLR9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR9_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR9_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR9_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR9_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR9_COMPARE10_Msk (0x1UL << GRTC_INTENCLR9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR9_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR9_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR9_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR9_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR9_COMPARE11_Msk (0x1UL << GRTC_INTENCLR9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR9_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR9_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR9_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR9_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR9_COMPARE12_Msk (0x1UL << GRTC_INTENCLR9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR9_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR9_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR9_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR9_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR9_COMPARE13_Msk (0x1UL << GRTC_INTENCLR9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR9_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR9_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR9_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR9_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR9_COMPARE14_Msk (0x1UL << GRTC_INTENCLR9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR9_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR9_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR9_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR9_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR9_COMPARE15_Msk (0x1UL << GRTC_INTENCLR9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR9_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR9_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR9_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR9_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR9_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR9_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR9_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR9_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR9_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR9_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR9_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR9_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND9: Pending interrupts */ + #define GRTC_INTPEND9_ResetValue (0x00000000UL) /*!< Reset value of INTPEND9 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND9_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND9_COMPARE0_Msk (0x1UL << GRTC_INTPEND9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND9_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND9_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND9_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND9_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND9_COMPARE1_Msk (0x1UL << GRTC_INTPEND9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND9_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND9_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND9_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND9_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND9_COMPARE2_Msk (0x1UL << GRTC_INTPEND9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND9_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND9_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND9_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND9_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND9_COMPARE3_Msk (0x1UL << GRTC_INTPEND9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND9_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND9_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND9_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND9_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND9_COMPARE4_Msk (0x1UL << GRTC_INTPEND9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND9_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND9_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND9_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND9_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND9_COMPARE5_Msk (0x1UL << GRTC_INTPEND9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND9_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND9_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND9_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND9_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND9_COMPARE6_Msk (0x1UL << GRTC_INTPEND9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND9_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND9_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND9_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND9_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND9_COMPARE7_Msk (0x1UL << GRTC_INTPEND9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND9_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND9_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND9_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND9_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND9_COMPARE8_Msk (0x1UL << GRTC_INTPEND9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND9_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND9_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND9_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND9_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND9_COMPARE9_Msk (0x1UL << GRTC_INTPEND9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND9_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND9_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND9_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND9_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND9_COMPARE10_Msk (0x1UL << GRTC_INTPEND9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND9_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND9_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND9_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND9_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND9_COMPARE11_Msk (0x1UL << GRTC_INTPEND9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND9_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND9_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND9_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND9_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND9_COMPARE12_Msk (0x1UL << GRTC_INTPEND9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND9_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND9_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND9_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND9_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND9_COMPARE13_Msk (0x1UL << GRTC_INTPEND9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND9_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND9_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND9_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND9_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND9_COMPARE14_Msk (0x1UL << GRTC_INTPEND9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND9_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND9_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND9_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND9_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND9_COMPARE15_Msk (0x1UL << GRTC_INTPEND9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND9_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND9_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND9_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND9_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND9_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND9_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND9_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND9_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND9_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND9_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND9_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND9_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND9_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND9_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND9_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND9_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND9_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND9_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN10: Enable or disable interrupt */ + #define GRTC_INTEN10_ResetValue (0x00000000UL) /*!< Reset value of INTEN10 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN10_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN10_COMPARE0_Msk (0x1UL << GRTC_INTEN10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN10_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN10_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN10_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN10_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN10_COMPARE1_Msk (0x1UL << GRTC_INTEN10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN10_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN10_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN10_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN10_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN10_COMPARE2_Msk (0x1UL << GRTC_INTEN10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN10_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN10_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN10_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN10_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN10_COMPARE3_Msk (0x1UL << GRTC_INTEN10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN10_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN10_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN10_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN10_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN10_COMPARE4_Msk (0x1UL << GRTC_INTEN10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN10_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN10_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN10_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN10_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN10_COMPARE5_Msk (0x1UL << GRTC_INTEN10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN10_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN10_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN10_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN10_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN10_COMPARE6_Msk (0x1UL << GRTC_INTEN10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN10_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN10_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN10_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN10_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN10_COMPARE7_Msk (0x1UL << GRTC_INTEN10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN10_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN10_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN10_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN10_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN10_COMPARE8_Msk (0x1UL << GRTC_INTEN10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN10_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN10_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN10_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN10_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN10_COMPARE9_Msk (0x1UL << GRTC_INTEN10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN10_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN10_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN10_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN10_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN10_COMPARE10_Msk (0x1UL << GRTC_INTEN10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN10_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN10_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN10_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN10_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN10_COMPARE11_Msk (0x1UL << GRTC_INTEN10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN10_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN10_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN10_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN10_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN10_COMPARE12_Msk (0x1UL << GRTC_INTEN10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN10_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN10_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN10_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN10_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN10_COMPARE13_Msk (0x1UL << GRTC_INTEN10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN10_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN10_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN10_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN10_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN10_COMPARE14_Msk (0x1UL << GRTC_INTEN10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN10_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN10_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN10_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN10_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN10_COMPARE15_Msk (0x1UL << GRTC_INTEN10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN10_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN10_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN10_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN10_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN10_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN10_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN10_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN10_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN10_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN10_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN10_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN10_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN10_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN10_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN10_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN10_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET10: Enable interrupt */ + #define GRTC_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET10_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET10_COMPARE0_Msk (0x1UL << GRTC_INTENSET10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET10_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET10_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET10_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET10_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET10_COMPARE1_Msk (0x1UL << GRTC_INTENSET10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET10_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET10_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET10_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET10_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET10_COMPARE2_Msk (0x1UL << GRTC_INTENSET10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET10_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET10_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET10_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET10_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET10_COMPARE3_Msk (0x1UL << GRTC_INTENSET10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET10_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET10_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET10_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET10_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET10_COMPARE4_Msk (0x1UL << GRTC_INTENSET10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET10_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET10_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET10_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET10_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET10_COMPARE5_Msk (0x1UL << GRTC_INTENSET10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET10_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET10_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET10_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET10_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET10_COMPARE6_Msk (0x1UL << GRTC_INTENSET10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET10_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET10_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET10_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET10_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET10_COMPARE7_Msk (0x1UL << GRTC_INTENSET10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET10_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET10_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET10_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET10_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET10_COMPARE8_Msk (0x1UL << GRTC_INTENSET10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET10_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET10_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET10_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET10_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET10_COMPARE9_Msk (0x1UL << GRTC_INTENSET10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET10_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET10_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET10_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET10_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET10_COMPARE10_Msk (0x1UL << GRTC_INTENSET10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET10_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET10_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET10_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET10_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET10_COMPARE11_Msk (0x1UL << GRTC_INTENSET10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET10_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET10_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET10_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET10_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET10_COMPARE12_Msk (0x1UL << GRTC_INTENSET10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET10_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET10_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET10_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET10_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET10_COMPARE13_Msk (0x1UL << GRTC_INTENSET10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET10_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET10_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET10_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET10_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET10_COMPARE14_Msk (0x1UL << GRTC_INTENSET10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET10_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET10_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET10_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET10_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET10_COMPARE15_Msk (0x1UL << GRTC_INTENSET10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET10_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET10_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET10_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET10_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET10_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET10_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET10_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET10_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET10_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET10_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET10_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET10_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR10: Disable interrupt */ + #define GRTC_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR10_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR10_COMPARE0_Msk (0x1UL << GRTC_INTENCLR10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR10_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR10_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR10_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR10_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR10_COMPARE1_Msk (0x1UL << GRTC_INTENCLR10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR10_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR10_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR10_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR10_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR10_COMPARE2_Msk (0x1UL << GRTC_INTENCLR10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR10_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR10_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR10_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR10_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR10_COMPARE3_Msk (0x1UL << GRTC_INTENCLR10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR10_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR10_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR10_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR10_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR10_COMPARE4_Msk (0x1UL << GRTC_INTENCLR10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR10_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR10_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR10_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR10_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR10_COMPARE5_Msk (0x1UL << GRTC_INTENCLR10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR10_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR10_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR10_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR10_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR10_COMPARE6_Msk (0x1UL << GRTC_INTENCLR10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR10_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR10_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR10_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR10_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR10_COMPARE7_Msk (0x1UL << GRTC_INTENCLR10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR10_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR10_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR10_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR10_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR10_COMPARE8_Msk (0x1UL << GRTC_INTENCLR10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR10_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR10_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR10_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR10_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR10_COMPARE9_Msk (0x1UL << GRTC_INTENCLR10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR10_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR10_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR10_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR10_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR10_COMPARE10_Msk (0x1UL << GRTC_INTENCLR10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR10_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR10_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR10_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR10_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR10_COMPARE11_Msk (0x1UL << GRTC_INTENCLR10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR10_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR10_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR10_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR10_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR10_COMPARE12_Msk (0x1UL << GRTC_INTENCLR10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR10_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR10_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR10_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR10_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR10_COMPARE13_Msk (0x1UL << GRTC_INTENCLR10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR10_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR10_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR10_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR10_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR10_COMPARE14_Msk (0x1UL << GRTC_INTENCLR10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR10_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR10_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR10_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR10_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR10_COMPARE15_Msk (0x1UL << GRTC_INTENCLR10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR10_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR10_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR10_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR10_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR10_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR10_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR10_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR10_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR10_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR10_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR10_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR10_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND10: Pending interrupts */ + #define GRTC_INTPEND10_ResetValue (0x00000000UL) /*!< Reset value of INTPEND10 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND10_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND10_COMPARE0_Msk (0x1UL << GRTC_INTPEND10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND10_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND10_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND10_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND10_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND10_COMPARE1_Msk (0x1UL << GRTC_INTPEND10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND10_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND10_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND10_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND10_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND10_COMPARE2_Msk (0x1UL << GRTC_INTPEND10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND10_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND10_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND10_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND10_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND10_COMPARE3_Msk (0x1UL << GRTC_INTPEND10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND10_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND10_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND10_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND10_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND10_COMPARE4_Msk (0x1UL << GRTC_INTPEND10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND10_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND10_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND10_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND10_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND10_COMPARE5_Msk (0x1UL << GRTC_INTPEND10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND10_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND10_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND10_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND10_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND10_COMPARE6_Msk (0x1UL << GRTC_INTPEND10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND10_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND10_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND10_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND10_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND10_COMPARE7_Msk (0x1UL << GRTC_INTPEND10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND10_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND10_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND10_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND10_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND10_COMPARE8_Msk (0x1UL << GRTC_INTPEND10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND10_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND10_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND10_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND10_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND10_COMPARE9_Msk (0x1UL << GRTC_INTPEND10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND10_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND10_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND10_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND10_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND10_COMPARE10_Msk (0x1UL << GRTC_INTPEND10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND10_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND10_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND10_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND10_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND10_COMPARE11_Msk (0x1UL << GRTC_INTPEND10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND10_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND10_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND10_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND10_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND10_COMPARE12_Msk (0x1UL << GRTC_INTPEND10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND10_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND10_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND10_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND10_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND10_COMPARE13_Msk (0x1UL << GRTC_INTPEND10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND10_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND10_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND10_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND10_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND10_COMPARE14_Msk (0x1UL << GRTC_INTPEND10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND10_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND10_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND10_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND10_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND10_COMPARE15_Msk (0x1UL << GRTC_INTPEND10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND10_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND10_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND10_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND10_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND10_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND10_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND10_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND10_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND10_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND10_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND10_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND10_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND10_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND10_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND10_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND10_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND10_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN11: Enable or disable interrupt */ + #define GRTC_INTEN11_ResetValue (0x00000000UL) /*!< Reset value of INTEN11 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN11_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN11_COMPARE0_Msk (0x1UL << GRTC_INTEN11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN11_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN11_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN11_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN11_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN11_COMPARE1_Msk (0x1UL << GRTC_INTEN11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN11_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN11_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN11_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN11_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN11_COMPARE2_Msk (0x1UL << GRTC_INTEN11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN11_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN11_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN11_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN11_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN11_COMPARE3_Msk (0x1UL << GRTC_INTEN11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN11_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN11_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN11_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN11_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN11_COMPARE4_Msk (0x1UL << GRTC_INTEN11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN11_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN11_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN11_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN11_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN11_COMPARE5_Msk (0x1UL << GRTC_INTEN11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN11_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN11_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN11_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN11_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN11_COMPARE6_Msk (0x1UL << GRTC_INTEN11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN11_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN11_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN11_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN11_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN11_COMPARE7_Msk (0x1UL << GRTC_INTEN11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN11_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN11_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN11_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN11_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN11_COMPARE8_Msk (0x1UL << GRTC_INTEN11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN11_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN11_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN11_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN11_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN11_COMPARE9_Msk (0x1UL << GRTC_INTEN11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN11_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN11_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN11_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN11_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN11_COMPARE10_Msk (0x1UL << GRTC_INTEN11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN11_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN11_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN11_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN11_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN11_COMPARE11_Msk (0x1UL << GRTC_INTEN11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN11_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN11_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN11_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN11_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN11_COMPARE12_Msk (0x1UL << GRTC_INTEN11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN11_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN11_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN11_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN11_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN11_COMPARE13_Msk (0x1UL << GRTC_INTEN11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN11_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN11_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN11_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN11_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN11_COMPARE14_Msk (0x1UL << GRTC_INTEN11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN11_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN11_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN11_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN11_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN11_COMPARE15_Msk (0x1UL << GRTC_INTEN11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN11_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN11_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN11_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN11_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN11_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN11_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN11_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN11_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN11_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN11_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN11_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN11_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN11_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN11_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN11_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN11_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET11: Enable interrupt */ + #define GRTC_INTENSET11_ResetValue (0x00000000UL) /*!< Reset value of INTENSET11 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET11_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET11_COMPARE0_Msk (0x1UL << GRTC_INTENSET11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET11_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET11_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET11_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET11_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET11_COMPARE1_Msk (0x1UL << GRTC_INTENSET11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET11_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET11_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET11_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET11_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET11_COMPARE2_Msk (0x1UL << GRTC_INTENSET11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET11_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET11_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET11_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET11_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET11_COMPARE3_Msk (0x1UL << GRTC_INTENSET11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET11_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET11_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET11_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET11_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET11_COMPARE4_Msk (0x1UL << GRTC_INTENSET11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET11_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET11_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET11_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET11_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET11_COMPARE5_Msk (0x1UL << GRTC_INTENSET11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET11_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET11_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET11_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET11_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET11_COMPARE6_Msk (0x1UL << GRTC_INTENSET11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET11_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET11_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET11_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET11_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET11_COMPARE7_Msk (0x1UL << GRTC_INTENSET11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET11_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET11_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET11_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET11_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET11_COMPARE8_Msk (0x1UL << GRTC_INTENSET11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET11_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET11_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET11_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET11_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET11_COMPARE9_Msk (0x1UL << GRTC_INTENSET11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET11_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET11_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET11_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET11_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET11_COMPARE10_Msk (0x1UL << GRTC_INTENSET11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET11_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET11_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET11_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET11_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET11_COMPARE11_Msk (0x1UL << GRTC_INTENSET11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET11_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET11_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET11_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET11_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET11_COMPARE12_Msk (0x1UL << GRTC_INTENSET11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET11_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET11_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET11_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET11_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET11_COMPARE13_Msk (0x1UL << GRTC_INTENSET11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET11_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET11_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET11_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET11_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET11_COMPARE14_Msk (0x1UL << GRTC_INTENSET11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET11_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET11_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET11_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET11_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET11_COMPARE15_Msk (0x1UL << GRTC_INTENSET11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET11_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET11_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET11_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET11_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET11_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET11_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET11_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET11_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET11_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET11_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET11_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET11_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR11: Disable interrupt */ + #define GRTC_INTENCLR11_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR11 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR11_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR11_COMPARE0_Msk (0x1UL << GRTC_INTENCLR11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR11_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR11_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR11_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR11_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR11_COMPARE1_Msk (0x1UL << GRTC_INTENCLR11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR11_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR11_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR11_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR11_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR11_COMPARE2_Msk (0x1UL << GRTC_INTENCLR11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR11_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR11_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR11_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR11_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR11_COMPARE3_Msk (0x1UL << GRTC_INTENCLR11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR11_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR11_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR11_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR11_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR11_COMPARE4_Msk (0x1UL << GRTC_INTENCLR11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR11_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR11_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR11_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR11_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR11_COMPARE5_Msk (0x1UL << GRTC_INTENCLR11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR11_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR11_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR11_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR11_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR11_COMPARE6_Msk (0x1UL << GRTC_INTENCLR11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR11_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR11_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR11_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR11_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR11_COMPARE7_Msk (0x1UL << GRTC_INTENCLR11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR11_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR11_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR11_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR11_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR11_COMPARE8_Msk (0x1UL << GRTC_INTENCLR11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR11_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR11_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR11_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR11_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR11_COMPARE9_Msk (0x1UL << GRTC_INTENCLR11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR11_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR11_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR11_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR11_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR11_COMPARE10_Msk (0x1UL << GRTC_INTENCLR11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR11_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR11_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR11_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR11_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR11_COMPARE11_Msk (0x1UL << GRTC_INTENCLR11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR11_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR11_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR11_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR11_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR11_COMPARE12_Msk (0x1UL << GRTC_INTENCLR11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR11_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR11_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR11_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR11_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR11_COMPARE13_Msk (0x1UL << GRTC_INTENCLR11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR11_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR11_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR11_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR11_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR11_COMPARE14_Msk (0x1UL << GRTC_INTENCLR11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR11_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR11_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR11_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR11_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR11_COMPARE15_Msk (0x1UL << GRTC_INTENCLR11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR11_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR11_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR11_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR11_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR11_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR11_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR11_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR11_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR11_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR11_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR11_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR11_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND11: Pending interrupts */ + #define GRTC_INTPEND11_ResetValue (0x00000000UL) /*!< Reset value of INTPEND11 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND11_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND11_COMPARE0_Msk (0x1UL << GRTC_INTPEND11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND11_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND11_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND11_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND11_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND11_COMPARE1_Msk (0x1UL << GRTC_INTPEND11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND11_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND11_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND11_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND11_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND11_COMPARE2_Msk (0x1UL << GRTC_INTPEND11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND11_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND11_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND11_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND11_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND11_COMPARE3_Msk (0x1UL << GRTC_INTPEND11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND11_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND11_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND11_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND11_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND11_COMPARE4_Msk (0x1UL << GRTC_INTPEND11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND11_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND11_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND11_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND11_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND11_COMPARE5_Msk (0x1UL << GRTC_INTPEND11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND11_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND11_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND11_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND11_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND11_COMPARE6_Msk (0x1UL << GRTC_INTPEND11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND11_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND11_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND11_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND11_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND11_COMPARE7_Msk (0x1UL << GRTC_INTPEND11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND11_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND11_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND11_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND11_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND11_COMPARE8_Msk (0x1UL << GRTC_INTPEND11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND11_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND11_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND11_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND11_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND11_COMPARE9_Msk (0x1UL << GRTC_INTPEND11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND11_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND11_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND11_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND11_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND11_COMPARE10_Msk (0x1UL << GRTC_INTPEND11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND11_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND11_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND11_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND11_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND11_COMPARE11_Msk (0x1UL << GRTC_INTPEND11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND11_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND11_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND11_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND11_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND11_COMPARE12_Msk (0x1UL << GRTC_INTPEND11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND11_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND11_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND11_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND11_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND11_COMPARE13_Msk (0x1UL << GRTC_INTPEND11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND11_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND11_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND11_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND11_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND11_COMPARE14_Msk (0x1UL << GRTC_INTPEND11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND11_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND11_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND11_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND11_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND11_COMPARE15_Msk (0x1UL << GRTC_INTPEND11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND11_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND11_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND11_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND11_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND11_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND11_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND11_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND11_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND11_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND11_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND11_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND11_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND11_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND11_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND11_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND11_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND11_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN12: Enable or disable interrupt */ + #define GRTC_INTEN12_ResetValue (0x00000000UL) /*!< Reset value of INTEN12 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN12_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN12_COMPARE0_Msk (0x1UL << GRTC_INTEN12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN12_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN12_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN12_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN12_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN12_COMPARE1_Msk (0x1UL << GRTC_INTEN12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN12_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN12_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN12_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN12_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN12_COMPARE2_Msk (0x1UL << GRTC_INTEN12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN12_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN12_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN12_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN12_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN12_COMPARE3_Msk (0x1UL << GRTC_INTEN12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN12_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN12_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN12_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN12_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN12_COMPARE4_Msk (0x1UL << GRTC_INTEN12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN12_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN12_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN12_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN12_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN12_COMPARE5_Msk (0x1UL << GRTC_INTEN12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN12_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN12_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN12_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN12_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN12_COMPARE6_Msk (0x1UL << GRTC_INTEN12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN12_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN12_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN12_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN12_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN12_COMPARE7_Msk (0x1UL << GRTC_INTEN12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN12_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN12_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN12_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN12_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN12_COMPARE8_Msk (0x1UL << GRTC_INTEN12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN12_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN12_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN12_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN12_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN12_COMPARE9_Msk (0x1UL << GRTC_INTEN12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN12_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN12_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN12_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN12_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN12_COMPARE10_Msk (0x1UL << GRTC_INTEN12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN12_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN12_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN12_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN12_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN12_COMPARE11_Msk (0x1UL << GRTC_INTEN12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN12_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN12_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN12_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN12_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN12_COMPARE12_Msk (0x1UL << GRTC_INTEN12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN12_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN12_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN12_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN12_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN12_COMPARE13_Msk (0x1UL << GRTC_INTEN12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN12_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN12_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN12_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN12_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN12_COMPARE14_Msk (0x1UL << GRTC_INTEN12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN12_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN12_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN12_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN12_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN12_COMPARE15_Msk (0x1UL << GRTC_INTEN12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN12_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN12_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN12_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN12_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN12_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN12_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN12_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN12_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN12_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN12_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN12_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN12_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN12_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN12_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN12_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN12_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET12: Enable interrupt */ + #define GRTC_INTENSET12_ResetValue (0x00000000UL) /*!< Reset value of INTENSET12 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET12_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET12_COMPARE0_Msk (0x1UL << GRTC_INTENSET12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET12_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET12_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET12_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET12_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET12_COMPARE1_Msk (0x1UL << GRTC_INTENSET12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET12_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET12_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET12_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET12_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET12_COMPARE2_Msk (0x1UL << GRTC_INTENSET12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET12_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET12_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET12_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET12_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET12_COMPARE3_Msk (0x1UL << GRTC_INTENSET12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET12_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET12_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET12_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET12_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET12_COMPARE4_Msk (0x1UL << GRTC_INTENSET12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET12_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET12_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET12_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET12_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET12_COMPARE5_Msk (0x1UL << GRTC_INTENSET12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET12_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET12_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET12_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET12_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET12_COMPARE6_Msk (0x1UL << GRTC_INTENSET12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET12_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET12_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET12_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET12_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET12_COMPARE7_Msk (0x1UL << GRTC_INTENSET12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET12_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET12_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET12_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET12_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET12_COMPARE8_Msk (0x1UL << GRTC_INTENSET12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET12_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET12_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET12_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET12_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET12_COMPARE9_Msk (0x1UL << GRTC_INTENSET12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET12_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET12_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET12_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET12_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET12_COMPARE10_Msk (0x1UL << GRTC_INTENSET12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET12_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET12_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET12_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET12_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET12_COMPARE11_Msk (0x1UL << GRTC_INTENSET12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET12_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET12_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET12_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET12_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET12_COMPARE12_Msk (0x1UL << GRTC_INTENSET12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET12_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET12_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET12_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET12_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET12_COMPARE13_Msk (0x1UL << GRTC_INTENSET12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET12_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET12_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET12_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET12_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET12_COMPARE14_Msk (0x1UL << GRTC_INTENSET12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET12_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET12_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET12_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET12_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET12_COMPARE15_Msk (0x1UL << GRTC_INTENSET12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET12_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET12_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET12_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET12_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET12_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET12_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET12_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET12_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET12_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET12_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET12_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET12_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR12: Disable interrupt */ + #define GRTC_INTENCLR12_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR12 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR12_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR12_COMPARE0_Msk (0x1UL << GRTC_INTENCLR12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR12_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR12_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR12_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR12_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR12_COMPARE1_Msk (0x1UL << GRTC_INTENCLR12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR12_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR12_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR12_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR12_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR12_COMPARE2_Msk (0x1UL << GRTC_INTENCLR12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR12_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR12_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR12_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR12_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR12_COMPARE3_Msk (0x1UL << GRTC_INTENCLR12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR12_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR12_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR12_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR12_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR12_COMPARE4_Msk (0x1UL << GRTC_INTENCLR12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR12_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR12_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR12_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR12_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR12_COMPARE5_Msk (0x1UL << GRTC_INTENCLR12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR12_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR12_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR12_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR12_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR12_COMPARE6_Msk (0x1UL << GRTC_INTENCLR12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR12_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR12_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR12_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR12_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR12_COMPARE7_Msk (0x1UL << GRTC_INTENCLR12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR12_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR12_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR12_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR12_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR12_COMPARE8_Msk (0x1UL << GRTC_INTENCLR12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR12_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR12_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR12_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR12_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR12_COMPARE9_Msk (0x1UL << GRTC_INTENCLR12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR12_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR12_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR12_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR12_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR12_COMPARE10_Msk (0x1UL << GRTC_INTENCLR12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR12_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR12_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR12_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR12_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR12_COMPARE11_Msk (0x1UL << GRTC_INTENCLR12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR12_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR12_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR12_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR12_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR12_COMPARE12_Msk (0x1UL << GRTC_INTENCLR12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR12_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR12_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR12_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR12_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR12_COMPARE13_Msk (0x1UL << GRTC_INTENCLR12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR12_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR12_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR12_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR12_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR12_COMPARE14_Msk (0x1UL << GRTC_INTENCLR12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR12_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR12_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR12_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR12_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR12_COMPARE15_Msk (0x1UL << GRTC_INTENCLR12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR12_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR12_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR12_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR12_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR12_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR12_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR12_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR12_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR12_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR12_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR12_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR12_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND12: Pending interrupts */ + #define GRTC_INTPEND12_ResetValue (0x00000000UL) /*!< Reset value of INTPEND12 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND12_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND12_COMPARE0_Msk (0x1UL << GRTC_INTPEND12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND12_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND12_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND12_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND12_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND12_COMPARE1_Msk (0x1UL << GRTC_INTPEND12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND12_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND12_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND12_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND12_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND12_COMPARE2_Msk (0x1UL << GRTC_INTPEND12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND12_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND12_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND12_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND12_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND12_COMPARE3_Msk (0x1UL << GRTC_INTPEND12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND12_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND12_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND12_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND12_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND12_COMPARE4_Msk (0x1UL << GRTC_INTPEND12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND12_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND12_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND12_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND12_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND12_COMPARE5_Msk (0x1UL << GRTC_INTPEND12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND12_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND12_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND12_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND12_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND12_COMPARE6_Msk (0x1UL << GRTC_INTPEND12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND12_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND12_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND12_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND12_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND12_COMPARE7_Msk (0x1UL << GRTC_INTPEND12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND12_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND12_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND12_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND12_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND12_COMPARE8_Msk (0x1UL << GRTC_INTPEND12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND12_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND12_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND12_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND12_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND12_COMPARE9_Msk (0x1UL << GRTC_INTPEND12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND12_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND12_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND12_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND12_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND12_COMPARE10_Msk (0x1UL << GRTC_INTPEND12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND12_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND12_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND12_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND12_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND12_COMPARE11_Msk (0x1UL << GRTC_INTPEND12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND12_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND12_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND12_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND12_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND12_COMPARE12_Msk (0x1UL << GRTC_INTPEND12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND12_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND12_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND12_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND12_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND12_COMPARE13_Msk (0x1UL << GRTC_INTPEND12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND12_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND12_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND12_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND12_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND12_COMPARE14_Msk (0x1UL << GRTC_INTPEND12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND12_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND12_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND12_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND12_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND12_COMPARE15_Msk (0x1UL << GRTC_INTPEND12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND12_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND12_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND12_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND12_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND12_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND12_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND12_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND12_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND12_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND12_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND12_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND12_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND12_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND12_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND12_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND12_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND12_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN13: Enable or disable interrupt */ + #define GRTC_INTEN13_ResetValue (0x00000000UL) /*!< Reset value of INTEN13 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN13_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN13_COMPARE0_Msk (0x1UL << GRTC_INTEN13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN13_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN13_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN13_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN13_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN13_COMPARE1_Msk (0x1UL << GRTC_INTEN13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN13_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN13_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN13_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN13_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN13_COMPARE2_Msk (0x1UL << GRTC_INTEN13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN13_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN13_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN13_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN13_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN13_COMPARE3_Msk (0x1UL << GRTC_INTEN13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN13_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN13_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN13_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN13_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN13_COMPARE4_Msk (0x1UL << GRTC_INTEN13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN13_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN13_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN13_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN13_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN13_COMPARE5_Msk (0x1UL << GRTC_INTEN13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN13_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN13_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN13_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN13_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN13_COMPARE6_Msk (0x1UL << GRTC_INTEN13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN13_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN13_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN13_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN13_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN13_COMPARE7_Msk (0x1UL << GRTC_INTEN13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN13_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN13_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN13_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN13_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN13_COMPARE8_Msk (0x1UL << GRTC_INTEN13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN13_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN13_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN13_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN13_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN13_COMPARE9_Msk (0x1UL << GRTC_INTEN13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN13_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN13_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN13_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN13_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN13_COMPARE10_Msk (0x1UL << GRTC_INTEN13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN13_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN13_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN13_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN13_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN13_COMPARE11_Msk (0x1UL << GRTC_INTEN13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN13_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN13_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN13_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN13_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN13_COMPARE12_Msk (0x1UL << GRTC_INTEN13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN13_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN13_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN13_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN13_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN13_COMPARE13_Msk (0x1UL << GRTC_INTEN13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN13_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN13_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN13_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN13_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN13_COMPARE14_Msk (0x1UL << GRTC_INTEN13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN13_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN13_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN13_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN13_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN13_COMPARE15_Msk (0x1UL << GRTC_INTEN13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN13_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN13_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN13_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN13_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN13_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN13_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN13_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN13_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN13_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN13_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN13_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN13_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN13_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN13_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN13_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN13_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET13: Enable interrupt */ + #define GRTC_INTENSET13_ResetValue (0x00000000UL) /*!< Reset value of INTENSET13 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET13_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET13_COMPARE0_Msk (0x1UL << GRTC_INTENSET13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET13_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET13_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET13_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET13_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET13_COMPARE1_Msk (0x1UL << GRTC_INTENSET13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET13_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET13_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET13_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET13_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET13_COMPARE2_Msk (0x1UL << GRTC_INTENSET13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET13_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET13_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET13_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET13_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET13_COMPARE3_Msk (0x1UL << GRTC_INTENSET13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET13_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET13_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET13_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET13_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET13_COMPARE4_Msk (0x1UL << GRTC_INTENSET13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET13_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET13_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET13_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET13_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET13_COMPARE5_Msk (0x1UL << GRTC_INTENSET13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET13_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET13_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET13_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET13_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET13_COMPARE6_Msk (0x1UL << GRTC_INTENSET13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET13_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET13_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET13_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET13_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET13_COMPARE7_Msk (0x1UL << GRTC_INTENSET13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET13_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET13_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET13_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET13_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET13_COMPARE8_Msk (0x1UL << GRTC_INTENSET13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET13_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET13_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET13_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET13_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET13_COMPARE9_Msk (0x1UL << GRTC_INTENSET13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET13_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET13_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET13_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET13_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET13_COMPARE10_Msk (0x1UL << GRTC_INTENSET13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET13_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET13_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET13_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET13_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET13_COMPARE11_Msk (0x1UL << GRTC_INTENSET13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET13_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET13_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET13_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET13_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET13_COMPARE12_Msk (0x1UL << GRTC_INTENSET13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET13_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET13_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET13_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET13_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET13_COMPARE13_Msk (0x1UL << GRTC_INTENSET13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET13_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET13_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET13_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET13_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET13_COMPARE14_Msk (0x1UL << GRTC_INTENSET13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET13_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET13_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET13_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET13_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET13_COMPARE15_Msk (0x1UL << GRTC_INTENSET13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET13_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET13_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET13_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET13_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET13_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET13_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET13_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET13_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET13_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET13_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET13_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET13_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR13: Disable interrupt */ + #define GRTC_INTENCLR13_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR13 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR13_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR13_COMPARE0_Msk (0x1UL << GRTC_INTENCLR13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR13_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR13_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR13_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR13_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR13_COMPARE1_Msk (0x1UL << GRTC_INTENCLR13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR13_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR13_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR13_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR13_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR13_COMPARE2_Msk (0x1UL << GRTC_INTENCLR13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR13_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR13_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR13_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR13_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR13_COMPARE3_Msk (0x1UL << GRTC_INTENCLR13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR13_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR13_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR13_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR13_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR13_COMPARE4_Msk (0x1UL << GRTC_INTENCLR13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR13_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR13_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR13_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR13_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR13_COMPARE5_Msk (0x1UL << GRTC_INTENCLR13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR13_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR13_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR13_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR13_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR13_COMPARE6_Msk (0x1UL << GRTC_INTENCLR13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR13_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR13_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR13_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR13_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR13_COMPARE7_Msk (0x1UL << GRTC_INTENCLR13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR13_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR13_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR13_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR13_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR13_COMPARE8_Msk (0x1UL << GRTC_INTENCLR13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR13_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR13_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR13_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR13_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR13_COMPARE9_Msk (0x1UL << GRTC_INTENCLR13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR13_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR13_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR13_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR13_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR13_COMPARE10_Msk (0x1UL << GRTC_INTENCLR13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR13_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR13_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR13_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR13_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR13_COMPARE11_Msk (0x1UL << GRTC_INTENCLR13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR13_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR13_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR13_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR13_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR13_COMPARE12_Msk (0x1UL << GRTC_INTENCLR13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR13_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR13_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR13_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR13_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR13_COMPARE13_Msk (0x1UL << GRTC_INTENCLR13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR13_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR13_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR13_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR13_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR13_COMPARE14_Msk (0x1UL << GRTC_INTENCLR13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR13_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR13_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR13_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR13_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR13_COMPARE15_Msk (0x1UL << GRTC_INTENCLR13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR13_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR13_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR13_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR13_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR13_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR13_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR13_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR13_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR13_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR13_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR13_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR13_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND13: Pending interrupts */ + #define GRTC_INTPEND13_ResetValue (0x00000000UL) /*!< Reset value of INTPEND13 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND13_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND13_COMPARE0_Msk (0x1UL << GRTC_INTPEND13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND13_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND13_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND13_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND13_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND13_COMPARE1_Msk (0x1UL << GRTC_INTPEND13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND13_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND13_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND13_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND13_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND13_COMPARE2_Msk (0x1UL << GRTC_INTPEND13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND13_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND13_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND13_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND13_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND13_COMPARE3_Msk (0x1UL << GRTC_INTPEND13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND13_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND13_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND13_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND13_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND13_COMPARE4_Msk (0x1UL << GRTC_INTPEND13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND13_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND13_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND13_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND13_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND13_COMPARE5_Msk (0x1UL << GRTC_INTPEND13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND13_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND13_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND13_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND13_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND13_COMPARE6_Msk (0x1UL << GRTC_INTPEND13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND13_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND13_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND13_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND13_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND13_COMPARE7_Msk (0x1UL << GRTC_INTPEND13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND13_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND13_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND13_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND13_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND13_COMPARE8_Msk (0x1UL << GRTC_INTPEND13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND13_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND13_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND13_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND13_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND13_COMPARE9_Msk (0x1UL << GRTC_INTPEND13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND13_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND13_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND13_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND13_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND13_COMPARE10_Msk (0x1UL << GRTC_INTPEND13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND13_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND13_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND13_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND13_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND13_COMPARE11_Msk (0x1UL << GRTC_INTPEND13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND13_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND13_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND13_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND13_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND13_COMPARE12_Msk (0x1UL << GRTC_INTPEND13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND13_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND13_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND13_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND13_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND13_COMPARE13_Msk (0x1UL << GRTC_INTPEND13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND13_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND13_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND13_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND13_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND13_COMPARE14_Msk (0x1UL << GRTC_INTPEND13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND13_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND13_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND13_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND13_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND13_COMPARE15_Msk (0x1UL << GRTC_INTPEND13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND13_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND13_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND13_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND13_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND13_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND13_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND13_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND13_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND13_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND13_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND13_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND13_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND13_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND13_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND13_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND13_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND13_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN14: Enable or disable interrupt */ + #define GRTC_INTEN14_ResetValue (0x00000000UL) /*!< Reset value of INTEN14 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN14_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN14_COMPARE0_Msk (0x1UL << GRTC_INTEN14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN14_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN14_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN14_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN14_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN14_COMPARE1_Msk (0x1UL << GRTC_INTEN14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN14_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN14_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN14_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN14_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN14_COMPARE2_Msk (0x1UL << GRTC_INTEN14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN14_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN14_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN14_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN14_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN14_COMPARE3_Msk (0x1UL << GRTC_INTEN14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN14_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN14_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN14_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN14_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN14_COMPARE4_Msk (0x1UL << GRTC_INTEN14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN14_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN14_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN14_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN14_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN14_COMPARE5_Msk (0x1UL << GRTC_INTEN14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN14_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN14_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN14_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN14_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN14_COMPARE6_Msk (0x1UL << GRTC_INTEN14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN14_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN14_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN14_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN14_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN14_COMPARE7_Msk (0x1UL << GRTC_INTEN14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN14_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN14_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN14_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN14_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN14_COMPARE8_Msk (0x1UL << GRTC_INTEN14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN14_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN14_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN14_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN14_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN14_COMPARE9_Msk (0x1UL << GRTC_INTEN14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN14_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN14_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN14_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN14_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN14_COMPARE10_Msk (0x1UL << GRTC_INTEN14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN14_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN14_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN14_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN14_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN14_COMPARE11_Msk (0x1UL << GRTC_INTEN14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN14_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN14_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN14_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN14_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN14_COMPARE12_Msk (0x1UL << GRTC_INTEN14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN14_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN14_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN14_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN14_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN14_COMPARE13_Msk (0x1UL << GRTC_INTEN14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN14_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN14_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN14_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN14_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN14_COMPARE14_Msk (0x1UL << GRTC_INTEN14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN14_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN14_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN14_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN14_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN14_COMPARE15_Msk (0x1UL << GRTC_INTEN14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN14_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN14_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN14_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN14_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN14_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN14_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN14_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN14_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN14_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN14_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN14_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN14_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN14_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN14_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN14_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN14_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET14: Enable interrupt */ + #define GRTC_INTENSET14_ResetValue (0x00000000UL) /*!< Reset value of INTENSET14 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET14_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET14_COMPARE0_Msk (0x1UL << GRTC_INTENSET14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET14_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET14_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET14_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET14_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET14_COMPARE1_Msk (0x1UL << GRTC_INTENSET14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET14_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET14_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET14_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET14_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET14_COMPARE2_Msk (0x1UL << GRTC_INTENSET14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET14_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET14_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET14_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET14_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET14_COMPARE3_Msk (0x1UL << GRTC_INTENSET14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET14_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET14_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET14_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET14_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET14_COMPARE4_Msk (0x1UL << GRTC_INTENSET14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET14_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET14_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET14_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET14_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET14_COMPARE5_Msk (0x1UL << GRTC_INTENSET14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET14_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET14_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET14_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET14_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET14_COMPARE6_Msk (0x1UL << GRTC_INTENSET14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET14_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET14_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET14_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET14_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET14_COMPARE7_Msk (0x1UL << GRTC_INTENSET14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET14_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET14_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET14_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET14_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET14_COMPARE8_Msk (0x1UL << GRTC_INTENSET14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET14_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET14_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET14_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET14_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET14_COMPARE9_Msk (0x1UL << GRTC_INTENSET14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET14_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET14_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET14_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET14_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET14_COMPARE10_Msk (0x1UL << GRTC_INTENSET14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET14_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET14_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET14_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET14_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET14_COMPARE11_Msk (0x1UL << GRTC_INTENSET14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET14_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET14_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET14_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET14_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET14_COMPARE12_Msk (0x1UL << GRTC_INTENSET14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET14_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET14_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET14_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET14_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET14_COMPARE13_Msk (0x1UL << GRTC_INTENSET14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET14_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET14_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET14_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET14_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET14_COMPARE14_Msk (0x1UL << GRTC_INTENSET14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET14_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET14_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET14_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET14_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET14_COMPARE15_Msk (0x1UL << GRTC_INTENSET14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET14_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET14_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET14_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET14_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET14_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET14_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET14_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET14_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET14_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET14_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET14_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET14_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR14: Disable interrupt */ + #define GRTC_INTENCLR14_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR14 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR14_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR14_COMPARE0_Msk (0x1UL << GRTC_INTENCLR14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR14_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR14_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR14_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR14_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR14_COMPARE1_Msk (0x1UL << GRTC_INTENCLR14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR14_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR14_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR14_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR14_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR14_COMPARE2_Msk (0x1UL << GRTC_INTENCLR14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR14_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR14_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR14_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR14_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR14_COMPARE3_Msk (0x1UL << GRTC_INTENCLR14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR14_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR14_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR14_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR14_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR14_COMPARE4_Msk (0x1UL << GRTC_INTENCLR14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR14_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR14_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR14_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR14_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR14_COMPARE5_Msk (0x1UL << GRTC_INTENCLR14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR14_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR14_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR14_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR14_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR14_COMPARE6_Msk (0x1UL << GRTC_INTENCLR14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR14_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR14_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR14_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR14_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR14_COMPARE7_Msk (0x1UL << GRTC_INTENCLR14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR14_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR14_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR14_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR14_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR14_COMPARE8_Msk (0x1UL << GRTC_INTENCLR14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR14_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR14_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR14_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR14_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR14_COMPARE9_Msk (0x1UL << GRTC_INTENCLR14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR14_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR14_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR14_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR14_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR14_COMPARE10_Msk (0x1UL << GRTC_INTENCLR14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR14_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR14_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR14_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR14_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR14_COMPARE11_Msk (0x1UL << GRTC_INTENCLR14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR14_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR14_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR14_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR14_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR14_COMPARE12_Msk (0x1UL << GRTC_INTENCLR14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR14_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR14_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR14_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR14_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR14_COMPARE13_Msk (0x1UL << GRTC_INTENCLR14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR14_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR14_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR14_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR14_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR14_COMPARE14_Msk (0x1UL << GRTC_INTENCLR14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR14_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR14_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR14_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR14_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR14_COMPARE15_Msk (0x1UL << GRTC_INTENCLR14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR14_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR14_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR14_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR14_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR14_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR14_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR14_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR14_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR14_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR14_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR14_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR14_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND14: Pending interrupts */ + #define GRTC_INTPEND14_ResetValue (0x00000000UL) /*!< Reset value of INTPEND14 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND14_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND14_COMPARE0_Msk (0x1UL << GRTC_INTPEND14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND14_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND14_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND14_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND14_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND14_COMPARE1_Msk (0x1UL << GRTC_INTPEND14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND14_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND14_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND14_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND14_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND14_COMPARE2_Msk (0x1UL << GRTC_INTPEND14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND14_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND14_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND14_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND14_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND14_COMPARE3_Msk (0x1UL << GRTC_INTPEND14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND14_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND14_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND14_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND14_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND14_COMPARE4_Msk (0x1UL << GRTC_INTPEND14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND14_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND14_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND14_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND14_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND14_COMPARE5_Msk (0x1UL << GRTC_INTPEND14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND14_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND14_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND14_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND14_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND14_COMPARE6_Msk (0x1UL << GRTC_INTPEND14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND14_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND14_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND14_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND14_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND14_COMPARE7_Msk (0x1UL << GRTC_INTPEND14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND14_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND14_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND14_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND14_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND14_COMPARE8_Msk (0x1UL << GRTC_INTPEND14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND14_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND14_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND14_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND14_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND14_COMPARE9_Msk (0x1UL << GRTC_INTPEND14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND14_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND14_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND14_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND14_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND14_COMPARE10_Msk (0x1UL << GRTC_INTPEND14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND14_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND14_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND14_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND14_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND14_COMPARE11_Msk (0x1UL << GRTC_INTPEND14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND14_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND14_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND14_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND14_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND14_COMPARE12_Msk (0x1UL << GRTC_INTPEND14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND14_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND14_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND14_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND14_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND14_COMPARE13_Msk (0x1UL << GRTC_INTPEND14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND14_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND14_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND14_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND14_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND14_COMPARE14_Msk (0x1UL << GRTC_INTPEND14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND14_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND14_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND14_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND14_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND14_COMPARE15_Msk (0x1UL << GRTC_INTPEND14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND14_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND14_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND14_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND14_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND14_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND14_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND14_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND14_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND14_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND14_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND14_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND14_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND14_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND14_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND14_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND14_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND14_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_INTEN15: Enable or disable interrupt */ + #define GRTC_INTEN15_ResetValue (0x00000000UL) /*!< Reset value of INTEN15 register. */ + +/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */ + #define GRTC_INTEN15_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTEN15_COMPARE0_Msk (0x1UL << GRTC_INTEN15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTEN15_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTEN15_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTEN15_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */ + #define GRTC_INTEN15_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTEN15_COMPARE1_Msk (0x1UL << GRTC_INTEN15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTEN15_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTEN15_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTEN15_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */ + #define GRTC_INTEN15_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTEN15_COMPARE2_Msk (0x1UL << GRTC_INTEN15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTEN15_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTEN15_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTEN15_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */ + #define GRTC_INTEN15_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTEN15_COMPARE3_Msk (0x1UL << GRTC_INTEN15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTEN15_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTEN15_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTEN15_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */ + #define GRTC_INTEN15_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTEN15_COMPARE4_Msk (0x1UL << GRTC_INTEN15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTEN15_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTEN15_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTEN15_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */ + #define GRTC_INTEN15_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTEN15_COMPARE5_Msk (0x1UL << GRTC_INTEN15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTEN15_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTEN15_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTEN15_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */ + #define GRTC_INTEN15_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTEN15_COMPARE6_Msk (0x1UL << GRTC_INTEN15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTEN15_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTEN15_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTEN15_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */ + #define GRTC_INTEN15_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTEN15_COMPARE7_Msk (0x1UL << GRTC_INTEN15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTEN15_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTEN15_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTEN15_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE7_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */ + #define GRTC_INTEN15_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTEN15_COMPARE8_Msk (0x1UL << GRTC_INTEN15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTEN15_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTEN15_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTEN15_COMPARE8_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE8_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */ + #define GRTC_INTEN15_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTEN15_COMPARE9_Msk (0x1UL << GRTC_INTEN15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTEN15_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTEN15_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTEN15_COMPARE9_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE9_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */ + #define GRTC_INTEN15_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTEN15_COMPARE10_Msk (0x1UL << GRTC_INTEN15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTEN15_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTEN15_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTEN15_COMPARE10_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE10_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */ + #define GRTC_INTEN15_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTEN15_COMPARE11_Msk (0x1UL << GRTC_INTEN15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTEN15_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTEN15_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTEN15_COMPARE11_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE11_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */ + #define GRTC_INTEN15_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTEN15_COMPARE12_Msk (0x1UL << GRTC_INTEN15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTEN15_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTEN15_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTEN15_COMPARE12_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE12_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */ + #define GRTC_INTEN15_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTEN15_COMPARE13_Msk (0x1UL << GRTC_INTEN15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTEN15_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTEN15_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTEN15_COMPARE13_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE13_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */ + #define GRTC_INTEN15_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTEN15_COMPARE14_Msk (0x1UL << GRTC_INTEN15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTEN15_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTEN15_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTEN15_COMPARE14_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE14_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */ + #define GRTC_INTEN15_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTEN15_COMPARE15_Msk (0x1UL << GRTC_INTEN15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTEN15_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTEN15_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTEN15_COMPARE15_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_COMPARE15_Enabled (0x1UL) /*!< Enable */ + +/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTEN15_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTEN15_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN15_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTEN15_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN15_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTEN15_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_RTCOMPARESYNC_Enabled (0x1UL) /*!< Enable */ + +/* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */ + #define GRTC_INTEN15_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTEN15_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN15_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTEN15_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN15_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTEN15_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_INTEN15_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_INTENSET15: Enable interrupt */ + #define GRTC_INTENSET15_ResetValue (0x00000000UL) /*!< Reset value of INTENSET15 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */ + #define GRTC_INTENSET15_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENSET15_COMPARE0_Msk (0x1UL << GRTC_INTENSET15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENSET15_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET15_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENSET15_COMPARE0_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */ + #define GRTC_INTENSET15_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENSET15_COMPARE1_Msk (0x1UL << GRTC_INTENSET15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENSET15_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET15_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENSET15_COMPARE1_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */ + #define GRTC_INTENSET15_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENSET15_COMPARE2_Msk (0x1UL << GRTC_INTENSET15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENSET15_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET15_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENSET15_COMPARE2_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */ + #define GRTC_INTENSET15_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENSET15_COMPARE3_Msk (0x1UL << GRTC_INTENSET15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENSET15_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET15_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENSET15_COMPARE3_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */ + #define GRTC_INTENSET15_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENSET15_COMPARE4_Msk (0x1UL << GRTC_INTENSET15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENSET15_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET15_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENSET15_COMPARE4_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */ + #define GRTC_INTENSET15_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENSET15_COMPARE5_Msk (0x1UL << GRTC_INTENSET15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENSET15_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET15_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENSET15_COMPARE5_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */ + #define GRTC_INTENSET15_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENSET15_COMPARE6_Msk (0x1UL << GRTC_INTENSET15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENSET15_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET15_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENSET15_COMPARE6_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */ + #define GRTC_INTENSET15_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENSET15_COMPARE7_Msk (0x1UL << GRTC_INTENSET15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENSET15_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET15_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENSET15_COMPARE7_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */ + #define GRTC_INTENSET15_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENSET15_COMPARE8_Msk (0x1UL << GRTC_INTENSET15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENSET15_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET15_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENSET15_COMPARE8_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */ + #define GRTC_INTENSET15_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENSET15_COMPARE9_Msk (0x1UL << GRTC_INTENSET15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENSET15_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET15_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENSET15_COMPARE9_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */ + #define GRTC_INTENSET15_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENSET15_COMPARE10_Msk (0x1UL << GRTC_INTENSET15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENSET15_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET15_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENSET15_COMPARE10_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */ + #define GRTC_INTENSET15_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENSET15_COMPARE11_Msk (0x1UL << GRTC_INTENSET15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENSET15_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET15_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENSET15_COMPARE11_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */ + #define GRTC_INTENSET15_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENSET15_COMPARE12_Msk (0x1UL << GRTC_INTENSET15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENSET15_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET15_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENSET15_COMPARE12_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */ + #define GRTC_INTENSET15_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENSET15_COMPARE13_Msk (0x1UL << GRTC_INTENSET15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENSET15_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET15_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENSET15_COMPARE13_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */ + #define GRTC_INTENSET15_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENSET15_COMPARE14_Msk (0x1UL << GRTC_INTENSET15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENSET15_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET15_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENSET15_COMPARE14_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */ + #define GRTC_INTENSET15_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENSET15_COMPARE15_Msk (0x1UL << GRTC_INTENSET15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENSET15_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET15_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENSET15_COMPARE15_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET15_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define GRTC_INTENSET15_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENSET15_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET15_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENSET15_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET15_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENSET15_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define GRTC_INTENSET15_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENSET15_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTENCLR15: Disable interrupt */ + #define GRTC_INTENCLR15_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR15 register. */ + +/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */ + #define GRTC_INTENCLR15_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTENCLR15_COMPARE0_Msk (0x1UL << GRTC_INTENCLR15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTENCLR15_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR15_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTENCLR15_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */ + #define GRTC_INTENCLR15_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTENCLR15_COMPARE1_Msk (0x1UL << GRTC_INTENCLR15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTENCLR15_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR15_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTENCLR15_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */ + #define GRTC_INTENCLR15_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTENCLR15_COMPARE2_Msk (0x1UL << GRTC_INTENCLR15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTENCLR15_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR15_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTENCLR15_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */ + #define GRTC_INTENCLR15_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTENCLR15_COMPARE3_Msk (0x1UL << GRTC_INTENCLR15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTENCLR15_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR15_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTENCLR15_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */ + #define GRTC_INTENCLR15_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTENCLR15_COMPARE4_Msk (0x1UL << GRTC_INTENCLR15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTENCLR15_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR15_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTENCLR15_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */ + #define GRTC_INTENCLR15_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTENCLR15_COMPARE5_Msk (0x1UL << GRTC_INTENCLR15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTENCLR15_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR15_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTENCLR15_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */ + #define GRTC_INTENCLR15_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTENCLR15_COMPARE6_Msk (0x1UL << GRTC_INTENCLR15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTENCLR15_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR15_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTENCLR15_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */ + #define GRTC_INTENCLR15_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTENCLR15_COMPARE7_Msk (0x1UL << GRTC_INTENCLR15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTENCLR15_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR15_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTENCLR15_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */ + #define GRTC_INTENCLR15_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTENCLR15_COMPARE8_Msk (0x1UL << GRTC_INTENCLR15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTENCLR15_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR15_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTENCLR15_COMPARE8_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */ + #define GRTC_INTENCLR15_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTENCLR15_COMPARE9_Msk (0x1UL << GRTC_INTENCLR15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTENCLR15_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR15_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTENCLR15_COMPARE9_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */ + #define GRTC_INTENCLR15_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTENCLR15_COMPARE10_Msk (0x1UL << GRTC_INTENCLR15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTENCLR15_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR15_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTENCLR15_COMPARE10_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */ + #define GRTC_INTENCLR15_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTENCLR15_COMPARE11_Msk (0x1UL << GRTC_INTENCLR15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTENCLR15_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR15_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTENCLR15_COMPARE11_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */ + #define GRTC_INTENCLR15_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTENCLR15_COMPARE12_Msk (0x1UL << GRTC_INTENCLR15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTENCLR15_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR15_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTENCLR15_COMPARE12_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */ + #define GRTC_INTENCLR15_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTENCLR15_COMPARE13_Msk (0x1UL << GRTC_INTENCLR15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTENCLR15_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR15_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTENCLR15_COMPARE13_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */ + #define GRTC_INTENCLR15_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTENCLR15_COMPARE14_Msk (0x1UL << GRTC_INTENCLR15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTENCLR15_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR15_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTENCLR15_COMPARE14_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */ + #define GRTC_INTENCLR15_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTENCLR15_COMPARE15_Msk (0x1UL << GRTC_INTENCLR15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTENCLR15_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR15_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTENCLR15_COMPARE15_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_COMPARE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR15_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define GRTC_INTENCLR15_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTENCLR15_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR15_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTENCLR15_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR15_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTENCLR15_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define GRTC_INTENCLR15_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_INTENCLR15_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* GRTC_INTPEND15: Pending interrupts */ + #define GRTC_INTPEND15_ResetValue (0x00000000UL) /*!< Reset value of INTPEND15 register. */ + +/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */ + #define GRTC_INTPEND15_COMPARE0_Pos (0UL) /*!< Position of COMPARE0 field. */ + #define GRTC_INTPEND15_COMPARE0_Msk (0x1UL << GRTC_INTPEND15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define GRTC_INTPEND15_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND15_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define GRTC_INTPEND15_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */ + #define GRTC_INTPEND15_COMPARE1_Pos (1UL) /*!< Position of COMPARE1 field. */ + #define GRTC_INTPEND15_COMPARE1_Msk (0x1UL << GRTC_INTPEND15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define GRTC_INTPEND15_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND15_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define GRTC_INTPEND15_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */ + #define GRTC_INTPEND15_COMPARE2_Pos (2UL) /*!< Position of COMPARE2 field. */ + #define GRTC_INTPEND15_COMPARE2_Msk (0x1UL << GRTC_INTPEND15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define GRTC_INTPEND15_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND15_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define GRTC_INTPEND15_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */ + #define GRTC_INTPEND15_COMPARE3_Pos (3UL) /*!< Position of COMPARE3 field. */ + #define GRTC_INTPEND15_COMPARE3_Msk (0x1UL << GRTC_INTPEND15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define GRTC_INTPEND15_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND15_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define GRTC_INTPEND15_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */ + #define GRTC_INTPEND15_COMPARE4_Pos (4UL) /*!< Position of COMPARE4 field. */ + #define GRTC_INTPEND15_COMPARE4_Msk (0x1UL << GRTC_INTPEND15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define GRTC_INTPEND15_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND15_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define GRTC_INTPEND15_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */ + #define GRTC_INTPEND15_COMPARE5_Pos (5UL) /*!< Position of COMPARE5 field. */ + #define GRTC_INTPEND15_COMPARE5_Msk (0x1UL << GRTC_INTPEND15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define GRTC_INTPEND15_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND15_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define GRTC_INTPEND15_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */ + #define GRTC_INTPEND15_COMPARE6_Pos (6UL) /*!< Position of COMPARE6 field. */ + #define GRTC_INTPEND15_COMPARE6_Msk (0x1UL << GRTC_INTPEND15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define GRTC_INTPEND15_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND15_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define GRTC_INTPEND15_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */ + #define GRTC_INTPEND15_COMPARE7_Pos (7UL) /*!< Position of COMPARE7 field. */ + #define GRTC_INTPEND15_COMPARE7_Msk (0x1UL << GRTC_INTPEND15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define GRTC_INTPEND15_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND15_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define GRTC_INTPEND15_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE7_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */ + #define GRTC_INTPEND15_COMPARE8_Pos (8UL) /*!< Position of COMPARE8 field. */ + #define GRTC_INTPEND15_COMPARE8_Msk (0x1UL << GRTC_INTPEND15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field. */ + #define GRTC_INTPEND15_COMPARE8_Min (0x0UL) /*!< Min enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND15_COMPARE8_Max (0x1UL) /*!< Max enumerator value of COMPARE8 field. */ + #define GRTC_INTPEND15_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE8_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */ + #define GRTC_INTPEND15_COMPARE9_Pos (9UL) /*!< Position of COMPARE9 field. */ + #define GRTC_INTPEND15_COMPARE9_Msk (0x1UL << GRTC_INTPEND15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field. */ + #define GRTC_INTPEND15_COMPARE9_Min (0x0UL) /*!< Min enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND15_COMPARE9_Max (0x1UL) /*!< Max enumerator value of COMPARE9 field. */ + #define GRTC_INTPEND15_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE9_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */ + #define GRTC_INTPEND15_COMPARE10_Pos (10UL) /*!< Position of COMPARE10 field. */ + #define GRTC_INTPEND15_COMPARE10_Msk (0x1UL << GRTC_INTPEND15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field. */ + #define GRTC_INTPEND15_COMPARE10_Min (0x0UL) /*!< Min enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND15_COMPARE10_Max (0x1UL) /*!< Max enumerator value of COMPARE10 field. */ + #define GRTC_INTPEND15_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE10_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */ + #define GRTC_INTPEND15_COMPARE11_Pos (11UL) /*!< Position of COMPARE11 field. */ + #define GRTC_INTPEND15_COMPARE11_Msk (0x1UL << GRTC_INTPEND15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field. */ + #define GRTC_INTPEND15_COMPARE11_Min (0x0UL) /*!< Min enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND15_COMPARE11_Max (0x1UL) /*!< Max enumerator value of COMPARE11 field. */ + #define GRTC_INTPEND15_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE11_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */ + #define GRTC_INTPEND15_COMPARE12_Pos (12UL) /*!< Position of COMPARE12 field. */ + #define GRTC_INTPEND15_COMPARE12_Msk (0x1UL << GRTC_INTPEND15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field. */ + #define GRTC_INTPEND15_COMPARE12_Min (0x0UL) /*!< Min enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND15_COMPARE12_Max (0x1UL) /*!< Max enumerator value of COMPARE12 field. */ + #define GRTC_INTPEND15_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE12_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */ + #define GRTC_INTPEND15_COMPARE13_Pos (13UL) /*!< Position of COMPARE13 field. */ + #define GRTC_INTPEND15_COMPARE13_Msk (0x1UL << GRTC_INTPEND15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field. */ + #define GRTC_INTPEND15_COMPARE13_Min (0x0UL) /*!< Min enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND15_COMPARE13_Max (0x1UL) /*!< Max enumerator value of COMPARE13 field. */ + #define GRTC_INTPEND15_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE13_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */ + #define GRTC_INTPEND15_COMPARE14_Pos (14UL) /*!< Position of COMPARE14 field. */ + #define GRTC_INTPEND15_COMPARE14_Msk (0x1UL << GRTC_INTPEND15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field. */ + #define GRTC_INTPEND15_COMPARE14_Min (0x0UL) /*!< Min enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND15_COMPARE14_Max (0x1UL) /*!< Max enumerator value of COMPARE14 field. */ + #define GRTC_INTPEND15_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE14_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */ + #define GRTC_INTPEND15_COMPARE15_Pos (15UL) /*!< Position of COMPARE15 field. */ + #define GRTC_INTPEND15_COMPARE15_Msk (0x1UL << GRTC_INTPEND15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field. */ + #define GRTC_INTPEND15_COMPARE15_Min (0x0UL) /*!< Min enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND15_COMPARE15_Max (0x1UL) /*!< Max enumerator value of COMPARE15 field. */ + #define GRTC_INTPEND15_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_COMPARE15_Pending (0x1UL) /*!< Read: Pending */ + +/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */ + #define GRTC_INTPEND15_RTCOMPARESYNC_Pos (25UL) /*!< Position of RTCOMPARESYNC field. */ + #define GRTC_INTPEND15_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND15_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field. */ + #define GRTC_INTPEND15_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND15_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of RTCOMPARESYNC field. */ + #define GRTC_INTPEND15_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending */ + +/* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */ + #define GRTC_INTPEND15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID + field.*/ + #define GRTC_INTPEND15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field. */ + #define GRTC_INTPEND15_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */ + #define GRTC_INTPEND15_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_INTPEND15_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND15_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_INTPEND15_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND15_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_INTPEND15_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define GRTC_INTPEND15_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + + +/* GRTC_EVTEN: Enable or disable event routing */ + #define GRTC_EVTEN_ResetValue (0x00000000UL) /*!< Reset value of EVTEN register. */ + +/* PWMPERIODEND @Bit 27 : Enable or disable event routing for event PWMPERIODEND */ + #define GRTC_EVTEN_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Msk (0x1UL << GRTC_EVTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define GRTC_EVTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + + +/* GRTC_EVTENSET: Enable event routing */ + #define GRTC_EVTENSET_ResetValue (0x00000000UL) /*!< Reset value of EVTENSET register. */ + +/* PWMPERIODEND @Bit 27 : Write '1' to enable event routing for event PWMPERIODEND */ + #define GRTC_EVTENSET_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_EVTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + #define GRTC_EVTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + + +/* GRTC_EVTENCLR: Disable event routing */ + #define GRTC_EVTENCLR_ResetValue (0x00000000UL) /*!< Reset value of EVTENCLR register. */ + +/* PWMPERIODEND @Bit 27 : Write '1' to disable event routing for event PWMPERIODEND */ + #define GRTC_EVTENCLR_PWMPERIODEND_Pos (27UL) /*!< Position of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define GRTC_EVTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define GRTC_EVTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + #define GRTC_EVTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + + +/* GRTC_MODE: Counter mode selection */ + #define GRTC_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* AUTOEN @Bit 0 : Automatic enable to keep the SYSCOUNTER active. */ + #define GRTC_MODE_AUTOEN_Pos (0UL) /*!< Position of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Msk (0x1UL << GRTC_MODE_AUTOEN_Pos) /*!< Bit mask of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Min (0x0UL) /*!< Min enumerator value of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Max (0x1UL) /*!< Max enumerator value of AUTOEN field. */ + #define GRTC_MODE_AUTOEN_Default (0x0UL) /*!< Default configuration to keep the SYSCOUNTER active. */ + #define GRTC_MODE_AUTOEN_CpuActive (0x1UL) /*!< In addition to the above mode, any local CPU that is not sleeping keep + the SYSCOUNTER active.*/ + +/* SYSCOUNTEREN @Bit 1 : Enable the SYSCOUNTER */ + #define GRTC_MODE_SYSCOUNTEREN_Pos (1UL) /*!< Position of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Msk (0x1UL << GRTC_MODE_SYSCOUNTEREN_Pos) /*!< Bit mask of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTEREN field. */ + #define GRTC_MODE_SYSCOUNTEREN_Disabled (0x0UL) /*!< SYSCOUNTER disabled */ + #define GRTC_MODE_SYSCOUNTEREN_Enabled (0x1UL) /*!< SYSCOUNTER enabled */ + + +/* GRTC_KEEPRUNNING: Request to keep the SYSCOUNTER in the active state and prevent going to sleep */ + #define GRTC_KEEPRUNNING_ResetValue (0x00000000UL) /*!< Reset value of KEEPRUNNING register. */ + +/* REQUEST0 @Bit 0 : Request from index [0] */ + #define GRTC_KEEPRUNNING_REQUEST0_Pos (0UL) /*!< Position of REQUEST0 field. */ + #define GRTC_KEEPRUNNING_REQUEST0_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST0_Pos) /*!< Bit mask of REQUEST0 field. */ + #define GRTC_KEEPRUNNING_REQUEST0_Min (0x0UL) /*!< Min enumerator value of REQUEST0 field. */ + #define GRTC_KEEPRUNNING_REQUEST0_Max (0x1UL) /*!< Max enumerator value of REQUEST0 field. */ + #define GRTC_KEEPRUNNING_REQUEST0_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST0_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST1 @Bit 1 : Request from index [1] */ + #define GRTC_KEEPRUNNING_REQUEST1_Pos (1UL) /*!< Position of REQUEST1 field. */ + #define GRTC_KEEPRUNNING_REQUEST1_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST1_Pos) /*!< Bit mask of REQUEST1 field. */ + #define GRTC_KEEPRUNNING_REQUEST1_Min (0x0UL) /*!< Min enumerator value of REQUEST1 field. */ + #define GRTC_KEEPRUNNING_REQUEST1_Max (0x1UL) /*!< Max enumerator value of REQUEST1 field. */ + #define GRTC_KEEPRUNNING_REQUEST1_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST1_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST2 @Bit 2 : Request from index [2] */ + #define GRTC_KEEPRUNNING_REQUEST2_Pos (2UL) /*!< Position of REQUEST2 field. */ + #define GRTC_KEEPRUNNING_REQUEST2_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST2_Pos) /*!< Bit mask of REQUEST2 field. */ + #define GRTC_KEEPRUNNING_REQUEST2_Min (0x0UL) /*!< Min enumerator value of REQUEST2 field. */ + #define GRTC_KEEPRUNNING_REQUEST2_Max (0x1UL) /*!< Max enumerator value of REQUEST2 field. */ + #define GRTC_KEEPRUNNING_REQUEST2_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST2_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST3 @Bit 3 : Request from index [3] */ + #define GRTC_KEEPRUNNING_REQUEST3_Pos (3UL) /*!< Position of REQUEST3 field. */ + #define GRTC_KEEPRUNNING_REQUEST3_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST3_Pos) /*!< Bit mask of REQUEST3 field. */ + #define GRTC_KEEPRUNNING_REQUEST3_Min (0x0UL) /*!< Min enumerator value of REQUEST3 field. */ + #define GRTC_KEEPRUNNING_REQUEST3_Max (0x1UL) /*!< Max enumerator value of REQUEST3 field. */ + #define GRTC_KEEPRUNNING_REQUEST3_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST3_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST4 @Bit 4 : Request from index [4] */ + #define GRTC_KEEPRUNNING_REQUEST4_Pos (4UL) /*!< Position of REQUEST4 field. */ + #define GRTC_KEEPRUNNING_REQUEST4_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST4_Pos) /*!< Bit mask of REQUEST4 field. */ + #define GRTC_KEEPRUNNING_REQUEST4_Min (0x0UL) /*!< Min enumerator value of REQUEST4 field. */ + #define GRTC_KEEPRUNNING_REQUEST4_Max (0x1UL) /*!< Max enumerator value of REQUEST4 field. */ + #define GRTC_KEEPRUNNING_REQUEST4_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST4_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST5 @Bit 5 : Request from index [5] */ + #define GRTC_KEEPRUNNING_REQUEST5_Pos (5UL) /*!< Position of REQUEST5 field. */ + #define GRTC_KEEPRUNNING_REQUEST5_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST5_Pos) /*!< Bit mask of REQUEST5 field. */ + #define GRTC_KEEPRUNNING_REQUEST5_Min (0x0UL) /*!< Min enumerator value of REQUEST5 field. */ + #define GRTC_KEEPRUNNING_REQUEST5_Max (0x1UL) /*!< Max enumerator value of REQUEST5 field. */ + #define GRTC_KEEPRUNNING_REQUEST5_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST5_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST6 @Bit 6 : Request from index [6] */ + #define GRTC_KEEPRUNNING_REQUEST6_Pos (6UL) /*!< Position of REQUEST6 field. */ + #define GRTC_KEEPRUNNING_REQUEST6_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST6_Pos) /*!< Bit mask of REQUEST6 field. */ + #define GRTC_KEEPRUNNING_REQUEST6_Min (0x0UL) /*!< Min enumerator value of REQUEST6 field. */ + #define GRTC_KEEPRUNNING_REQUEST6_Max (0x1UL) /*!< Max enumerator value of REQUEST6 field. */ + #define GRTC_KEEPRUNNING_REQUEST6_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST6_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST7 @Bit 7 : Request from index [7] */ + #define GRTC_KEEPRUNNING_REQUEST7_Pos (7UL) /*!< Position of REQUEST7 field. */ + #define GRTC_KEEPRUNNING_REQUEST7_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST7_Pos) /*!< Bit mask of REQUEST7 field. */ + #define GRTC_KEEPRUNNING_REQUEST7_Min (0x0UL) /*!< Min enumerator value of REQUEST7 field. */ + #define GRTC_KEEPRUNNING_REQUEST7_Max (0x1UL) /*!< Max enumerator value of REQUEST7 field. */ + #define GRTC_KEEPRUNNING_REQUEST7_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST7_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST8 @Bit 8 : Request from index [8] */ + #define GRTC_KEEPRUNNING_REQUEST8_Pos (8UL) /*!< Position of REQUEST8 field. */ + #define GRTC_KEEPRUNNING_REQUEST8_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST8_Pos) /*!< Bit mask of REQUEST8 field. */ + #define GRTC_KEEPRUNNING_REQUEST8_Min (0x0UL) /*!< Min enumerator value of REQUEST8 field. */ + #define GRTC_KEEPRUNNING_REQUEST8_Max (0x1UL) /*!< Max enumerator value of REQUEST8 field. */ + #define GRTC_KEEPRUNNING_REQUEST8_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST8_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST9 @Bit 9 : Request from index [9] */ + #define GRTC_KEEPRUNNING_REQUEST9_Pos (9UL) /*!< Position of REQUEST9 field. */ + #define GRTC_KEEPRUNNING_REQUEST9_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST9_Pos) /*!< Bit mask of REQUEST9 field. */ + #define GRTC_KEEPRUNNING_REQUEST9_Min (0x0UL) /*!< Min enumerator value of REQUEST9 field. */ + #define GRTC_KEEPRUNNING_REQUEST9_Max (0x1UL) /*!< Max enumerator value of REQUEST9 field. */ + #define GRTC_KEEPRUNNING_REQUEST9_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST9_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST10 @Bit 10 : Request from index [10] */ + #define GRTC_KEEPRUNNING_REQUEST10_Pos (10UL) /*!< Position of REQUEST10 field. */ + #define GRTC_KEEPRUNNING_REQUEST10_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST10_Pos) /*!< Bit mask of REQUEST10 field. */ + #define GRTC_KEEPRUNNING_REQUEST10_Min (0x0UL) /*!< Min enumerator value of REQUEST10 field. */ + #define GRTC_KEEPRUNNING_REQUEST10_Max (0x1UL) /*!< Max enumerator value of REQUEST10 field. */ + #define GRTC_KEEPRUNNING_REQUEST10_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST10_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST11 @Bit 11 : Request from index [11] */ + #define GRTC_KEEPRUNNING_REQUEST11_Pos (11UL) /*!< Position of REQUEST11 field. */ + #define GRTC_KEEPRUNNING_REQUEST11_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST11_Pos) /*!< Bit mask of REQUEST11 field. */ + #define GRTC_KEEPRUNNING_REQUEST11_Min (0x0UL) /*!< Min enumerator value of REQUEST11 field. */ + #define GRTC_KEEPRUNNING_REQUEST11_Max (0x1UL) /*!< Max enumerator value of REQUEST11 field. */ + #define GRTC_KEEPRUNNING_REQUEST11_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST11_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST12 @Bit 12 : Request from index [12] */ + #define GRTC_KEEPRUNNING_REQUEST12_Pos (12UL) /*!< Position of REQUEST12 field. */ + #define GRTC_KEEPRUNNING_REQUEST12_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST12_Pos) /*!< Bit mask of REQUEST12 field. */ + #define GRTC_KEEPRUNNING_REQUEST12_Min (0x0UL) /*!< Min enumerator value of REQUEST12 field. */ + #define GRTC_KEEPRUNNING_REQUEST12_Max (0x1UL) /*!< Max enumerator value of REQUEST12 field. */ + #define GRTC_KEEPRUNNING_REQUEST12_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST12_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST13 @Bit 13 : Request from index [13] */ + #define GRTC_KEEPRUNNING_REQUEST13_Pos (13UL) /*!< Position of REQUEST13 field. */ + #define GRTC_KEEPRUNNING_REQUEST13_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST13_Pos) /*!< Bit mask of REQUEST13 field. */ + #define GRTC_KEEPRUNNING_REQUEST13_Min (0x0UL) /*!< Min enumerator value of REQUEST13 field. */ + #define GRTC_KEEPRUNNING_REQUEST13_Max (0x1UL) /*!< Max enumerator value of REQUEST13 field. */ + #define GRTC_KEEPRUNNING_REQUEST13_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST13_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST14 @Bit 14 : Request from index [14] */ + #define GRTC_KEEPRUNNING_REQUEST14_Pos (14UL) /*!< Position of REQUEST14 field. */ + #define GRTC_KEEPRUNNING_REQUEST14_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST14_Pos) /*!< Bit mask of REQUEST14 field. */ + #define GRTC_KEEPRUNNING_REQUEST14_Min (0x0UL) /*!< Min enumerator value of REQUEST14 field. */ + #define GRTC_KEEPRUNNING_REQUEST14_Max (0x1UL) /*!< Max enumerator value of REQUEST14 field. */ + #define GRTC_KEEPRUNNING_REQUEST14_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST14_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + +/* REQUEST15 @Bit 15 : Request from index [15] */ + #define GRTC_KEEPRUNNING_REQUEST15_Pos (15UL) /*!< Position of REQUEST15 field. */ + #define GRTC_KEEPRUNNING_REQUEST15_Msk (0x1UL << GRTC_KEEPRUNNING_REQUEST15_Pos) /*!< Bit mask of REQUEST15 field. */ + #define GRTC_KEEPRUNNING_REQUEST15_Min (0x0UL) /*!< Min enumerator value of REQUEST15 field. */ + #define GRTC_KEEPRUNNING_REQUEST15_Max (0x1UL) /*!< Max enumerator value of REQUEST15 field. */ + #define GRTC_KEEPRUNNING_REQUEST15_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep */ + #define GRTC_KEEPRUNNING_REQUEST15_Active (0x1UL) /*!< Keep SYSCOUNTER active */ + + +/* GRTC_TIMEOUT: Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER */ + #define GRTC_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of TIMEOUT register. */ + +/* VALUE @Bits 0..15 : Number of 32Ki cycles */ + #define GRTC_TIMEOUT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_TIMEOUT_VALUE_Msk (0xFFFFUL << GRTC_TIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* GRTC_INTERVAL: Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. */ + #define GRTC_INTERVAL_ResetValue (0x00000000UL) /*!< Reset value of INTERVAL register. */ + +/* VALUE @Bits 0..15 : Count to add to CC[0] */ + #define GRTC_INTERVAL_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define GRTC_INTERVAL_VALUE_Msk (0xFFFFUL << GRTC_INTERVAL_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* GRTC_PWMCONFIG: PWM configuration. */ + #define GRTC_PWMCONFIG_ResetValue (0x00000000UL) /*!< Reset value of PWMCONFIG register. */ + +/* COMPAREVALUE @Bits 0..7 : The PWM compare value */ + #define GRTC_PWMCONFIG_COMPAREVALUE_Pos (0UL) /*!< Position of COMPAREVALUE field. */ + #define GRTC_PWMCONFIG_COMPAREVALUE_Msk (0xFFUL << GRTC_PWMCONFIG_COMPAREVALUE_Pos) /*!< Bit mask of COMPAREVALUE field. */ + + +/* GRTC_CLKOUT: Configuration of clock output */ + #define GRTC_CLKOUT_ResetValue (0x00000000UL) /*!< Reset value of CLKOUT register. */ + +/* CLKOUT32K @Bit 0 : Enable 32Ki clock output on pin */ + #define GRTC_CLKOUT_CLKOUT32K_Pos (0UL) /*!< Position of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Msk (0x1UL << GRTC_CLKOUT_CLKOUT32K_Pos) /*!< Bit mask of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Min (0x0UL) /*!< Min enumerator value of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Max (0x1UL) /*!< Max enumerator value of CLKOUT32K field. */ + #define GRTC_CLKOUT_CLKOUT32K_Disabled (0x0UL) /*!< Disabled */ + #define GRTC_CLKOUT_CLKOUT32K_Enabled (0x1UL) /*!< Enabled */ + +/* CLKOUTFAST @Bit 1 : Enable fast clock output on pin */ + #define GRTC_CLKOUT_CLKOUTFAST_Pos (1UL) /*!< Position of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Msk (0x1UL << GRTC_CLKOUT_CLKOUTFAST_Pos) /*!< Bit mask of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Min (0x0UL) /*!< Min enumerator value of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Max (0x1UL) /*!< Max enumerator value of CLKOUTFAST field. */ + #define GRTC_CLKOUT_CLKOUTFAST_Disabled (0x0UL) /*!< Disabled */ + #define GRTC_CLKOUT_CLKOUTFAST_Enabled (0x1UL) /*!< Enabled */ + + +/* GRTC_CLKCFG: Clock Configuration */ + #define GRTC_CLKCFG_ResetValue (0x00010001UL) /*!< Reset value of CLKCFG register. */ + +/* CLKFASTDIV @Bits 0..7 : Fast clock divisor value of clock output */ + #define GRTC_CLKCFG_CLKFASTDIV_Pos (0UL) /*!< Position of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Msk (0xFFUL << GRTC_CLKCFG_CLKFASTDIV_Pos) /*!< Bit mask of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Min (0x01UL) /*!< Min value of CLKFASTDIV field. */ + #define GRTC_CLKCFG_CLKFASTDIV_Max (0xFFUL) /*!< Max size of CLKFASTDIV field. */ + +/* CLKSEL @Bits 16..17 : GRTC LFCLK clock source selection */ + #define GRTC_CLKCFG_CLKSEL_Pos (16UL) /*!< Position of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Msk (0x3UL << GRTC_CLKCFG_CLKSEL_Pos) /*!< Bit mask of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Min (0x0UL) /*!< Min enumerator value of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_Max (0x1UL) /*!< Max enumerator value of CLKSEL field. */ + #define GRTC_CLKCFG_CLKSEL_LFXO (0x0UL) /*!< GRTC LFCLK clock source is LFXO */ + #define GRTC_CLKCFG_CLKSEL_SystemLFCLK (0x1UL) /*!< GRTC LFCLK clock source is system LFCLK */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ HSFLL ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct HSFLL_FREQM ==================================================== */ +/** + * @brief FREQM [HSFLL_FREQM] (unspecified) + */ +typedef struct { + __IM uint32_t DONE; /*!< (@ 0x00000000) Frequency measurement done status */ + __IM uint32_t ERROR; /*!< (@ 0x00000004) Frequency measurement error status */ + __IM uint32_t MEAS; /*!< (@ 0x00000008) Frequency measurement */ +} NRF_HSFLL_FREQM_Type; /*!< Size = 12 (0x00C) */ + +/* HSFLL_FREQM_DONE: Frequency measurement done status */ + #define HSFLL_FREQM_DONE_ResetValue (0x00000000UL) /*!< Reset value of DONE register. */ + +/* DONE @Bit 0 : Measurement done. */ + #define HSFLL_FREQM_DONE_DONE_Pos (0UL) /*!< Position of DONE field. */ + #define HSFLL_FREQM_DONE_DONE_Msk (0x1UL << HSFLL_FREQM_DONE_DONE_Pos) /*!< Bit mask of DONE field. */ + #define HSFLL_FREQM_DONE_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define HSFLL_FREQM_DONE_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define HSFLL_FREQM_DONE_DONE_InProgress (0x0UL) /*!< Frequency measurement is in progress. */ + #define HSFLL_FREQM_DONE_DONE_Completed (0x1UL) /*!< Frequency measurement is completed. */ + + +/* HSFLL_FREQM_ERROR: Frequency measurement error status */ + #define HSFLL_FREQM_ERROR_ResetValue (0x00000000UL) /*!< Reset value of ERROR register. */ + +/* ERROR @Bit 0 : Trim error status. */ + #define HSFLL_FREQM_ERROR_ERROR_Pos (0UL) /*!< Position of ERROR field. */ + #define HSFLL_FREQM_ERROR_ERROR_Msk (0x1UL << HSFLL_FREQM_ERROR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define HSFLL_FREQM_ERROR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define HSFLL_FREQM_ERROR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define HSFLL_FREQM_ERROR_ERROR_OutsideLimit (0x1UL) /*!< Frequency exceeded the accuracy 2 percent in closed loop mode. */ + #define HSFLL_FREQM_ERROR_ERROR_WithinLimit (0x0UL) /*!< Frequency stayed within accuracy 2 percent in closed loop mode. */ + +/* TRIMUNDERFLOW @Bit 1 : Underflow error status. */ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos (1UL) /*!< Position of TRIMUNDERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Msk (0x1UL << HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos) /*!< Bit mask of TRIMUNDERFLOW + field.*/ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of TRIMUNDERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of TRIMUNDERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_OutsideLimit (0x1UL) /*!< Underflow */ + #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_WithinLimit (0x0UL) /*!< No underflow */ + +/* TRIMOVERFLOW @Bit 2 : Overflow error status. */ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos (2UL) /*!< Position of TRIMOVERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Msk (0x1UL << HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos) /*!< Bit mask of TRIMOVERFLOW field.*/ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Min (0x0UL) /*!< Min enumerator value of TRIMOVERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Max (0x1UL) /*!< Max enumerator value of TRIMOVERFLOW field. */ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_OutsideLimit (0x1UL) /*!< Overflow */ + #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_WithinLimit (0x0UL) /*!< No overflow */ + + +/* HSFLL_FREQM_MEAS: Frequency measurement */ + #define HSFLL_FREQM_MEAS_ResetValue (0x00000000UL) /*!< Reset value of MEAS register. */ + +/* VALUE @Bits 0..7 : Last frequency measurement value. */ + #define HSFLL_FREQM_MEAS_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define HSFLL_FREQM_MEAS_VALUE_Msk (0xFFUL << HSFLL_FREQM_MEAS_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ==================================================== Struct HSFLL_TRIM ==================================================== */ +/** + * @brief TRIM [HSFLL_TRIM] (unspecified) + */ +typedef struct { + __IOM uint32_t VSUP; /*!< (@ 0x00000000) Internal regulator voltage supply level trimming */ + __IOM uint32_t COARSE; /*!< (@ 0x00000004) Coarse frequency trimming */ + __IOM uint32_t FINE; /*!< (@ 0x00000008) Fine frequency trimming */ + __IM uint32_t RESERVED[2]; +} NRF_HSFLL_TRIM_Type; /*!< Size = 20 (0x014) */ + +/* HSFLL_TRIM_VSUP: Internal regulator voltage supply level trimming */ + #define HSFLL_TRIM_VSUP_ResetValue (0x00000010UL) /*!< Reset value of VSUP register. */ + +/* VALUE @Bits 0..4 : Trim value */ + #define HSFLL_TRIM_VSUP_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define HSFLL_TRIM_VSUP_VALUE_Msk (0x1FUL << HSFLL_TRIM_VSUP_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* HSFLL_TRIM_COARSE: Coarse frequency trimming */ + #define HSFLL_TRIM_COARSE_ResetValue (0x00000004UL) /*!< Reset value of COARSE register. */ + +/* VALUE @Bits 0..9 : Coarse frequency trimming value. */ + #define HSFLL_TRIM_COARSE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define HSFLL_TRIM_COARSE_VALUE_Msk (0x3FFUL << HSFLL_TRIM_COARSE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* HSFLL_TRIM_FINE: Fine frequency trimming */ + #define HSFLL_TRIM_FINE_ResetValue (0x0000001EUL) /*!< Reset value of FINE register. */ + +/* VALUE @Bits 0..10 : Fine frequency trimming value */ + #define HSFLL_TRIM_FINE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define HSFLL_TRIM_FINE_VALUE_Msk (0x7FFUL << HSFLL_TRIM_FINE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + + +/* ================================================= Struct HSFLL_CLOCKCTRL ================================================== */ +/** + * @brief CLOCKCTRL [HSFLL_CLOCKCTRL] (unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) Clock control */ + __IOM uint32_t DITHERING; /*!< (@ 0x00000004) Clock dithering configuration */ + __IOM uint32_t MULT; /*!< (@ 0x00000008) Multiplication factor */ + __IOM uint32_t SLEEP; /*!< (@ 0x0000000C) Sleep configuration */ + __IOM uint32_t RETAINFINETRIM; /*!< (@ 0x00000010) Fine trim retain control */ + __IOM uint32_t OVERRIDELOCKED; /*!< (@ 0x00000014) Override the LOCKED signal */ + __IOM uint32_t DITHERINIT; /*!< (@ 0x00000018) Clock dithering, configurable seed */ +} NRF_HSFLL_CLOCKCTRL_Type; /*!< Size = 28 (0x01C) */ + +/* HSFLL_CLOCKCTRL_MODE: Clock control */ + #define HSFLL_CLOCKCTRL_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : The HSFLL operating mode. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Msk (0x3UL << HSFLL_CLOCKCTRL_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Auto (0x0UL) /*!< The PCGC controls the mode automatically. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_OpenLoop (0x1UL) /*!< Open loop mode. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_ClosedLoop (0x2UL) /*!< Closed loop mode. */ + #define HSFLL_CLOCKCTRL_MODE_MODE_Bypass (0x3UL) /*!< Bypass mode. */ + +/* OVERRIDE @Bit 4 : HSFLL override mode. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos (4UL) /*!< Position of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) /*!< Bit mask of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Min (0x0UL) /*!< Min enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Max (0x1UL) /*!< Max enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Disabled (0x0UL) /*!< Override mode disabled. */ + #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled (0x1UL) /*!< Override mode enabled. */ + + +/* HSFLL_CLOCKCTRL_DITHERING: Clock dithering configuration */ + #define HSFLL_CLOCKCTRL_DITHERING_ResetValue (0x00000033UL) /*!< Reset value of DITHERING register. */ + +/* CYCLECOUNT @Bits 0..2 : Cycle count configuration for clock dithering */ + #define HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos (0UL) /*!< Position of CYCLECOUNT field. */ + #define HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk (0x7UL << HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos) /*!< Bit mask of + CYCLECOUNT field.*/ + +/* MAXOFFSET @Bits 4..6 : Maximum offset configuration for clock dithering */ + #define HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos (4UL) /*!< Position of MAXOFFSET field. */ + #define HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk (0x7UL << HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) /*!< Bit mask of MAXOFFSET + field.*/ + +/* EN @Bit 31 : Enable the clock dithering */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Pos (31UL) /*!< Position of EN field. */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Msk (0x1UL << HSFLL_CLOCKCTRL_DITHERING_EN_Pos) /*!< Bit mask of EN field. */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Disabled (0x0UL) /*!< Clock dithering is disabled */ + #define HSFLL_CLOCKCTRL_DITHERING_EN_Enabled (0x1UL) /*!< Clock dithering is enabled */ + + +/* HSFLL_CLOCKCTRL_MULT: Multiplication factor */ + #define HSFLL_CLOCKCTRL_MULT_ResetValue (0x00000006UL) /*!< Reset value of MULT register. */ + +/* VAL @Bits 0..4 : Multiplication factor value. Valid range: 4 to 25. Output frequency is a multiplication of 16 MHz reference + and the multiplication factor. */ + + #define HSFLL_CLOCKCTRL_MULT_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define HSFLL_CLOCKCTRL_MULT_VAL_Msk (0x1FUL << HSFLL_CLOCKCTRL_MULT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* HSFLL_CLOCKCTRL_SLEEP: Sleep configuration */ + #define HSFLL_CLOCKCTRL_SLEEP_ResetValue (0x00000001UL) /*!< Reset value of SLEEP register. */ + +/* MODE @Bit 0 : HSFLL sleep mode. */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Msk (0x1UL << HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) /*!< Bit mask of MODE field. */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Normal (0x0UL) /*!< Normal mode operation */ + #define HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep (0x1UL) /*!< Power down the HSFLL core */ + +/* RETAIN @Bit 1 : Retain. */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos (1UL) /*!< Position of RETAIN field. */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk (0x1UL << HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) /*!< Bit mask of RETAIN field. */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Min (0x0UL) /*!< Min enumerator value of RETAIN field. */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Max (0x1UL) /*!< Max enumerator value of RETAIN field. */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Disabled (0x0UL) /*!< No retention while powered down */ + #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled (0x1UL) /*!< Retain all inputs while powered down */ + + +/* HSFLL_CLOCKCTRL_RETAINFINETRIM: Fine trim retain control */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_ResetValue (0x00000000UL) /*!< Reset value of RETAINFINETRIM register. */ + +/* RETAIN @Bit 0 : Retain control */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos (0UL) /*!< Position of RETAIN field. */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Msk (0x1UL << HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos) /*!< Bit mask of RETAIN + field.*/ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Min (0x0UL) /*!< Min enumerator value of RETAIN field. */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Max (0x1UL) /*!< Max enumerator value of RETAIN field. */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_NoRetain (0x0UL) /*!< No retain. */ + #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Retain (0x1UL) /*!< Retain control when HSFLL goes to open-loop mode. */ + + +/* HSFLL_CLOCKCTRL_OVERRIDELOCKED: Override the LOCKED signal */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_ResetValue (0x00000000UL) /*!< Reset value of OVERRIDELOCKED register. */ + +/* OVERRIDE @Bit 0 : Override */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos (0UL) /*!< Position of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos) /*!< Bit mask of + OVERRIDE field.*/ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Min (0x0UL) /*!< Min enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Max (0x1UL) /*!< Max enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_NoOperation (0x0UL) /*!< No Operation. */ + #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Override (0x1UL) /*!< Override */ + + +/* HSFLL_CLOCKCTRL_DITHERINIT: Clock dithering, configurable seed */ + #define HSFLL_CLOCKCTRL_DITHERINIT_ResetValue (0x00000000UL) /*!< Reset value of DITHERINIT register. */ + +/* SEED @Bits 0..31 : Initial value for the PRBS */ + #define HSFLL_CLOCKCTRL_DITHERINIT_SEED_Pos (0UL) /*!< Position of SEED field. */ + #define HSFLL_CLOCKCTRL_DITHERINIT_SEED_Msk (0xFFFFFFFFUL << HSFLL_CLOCKCTRL_DITHERINIT_SEED_Pos) /*!< Bit mask of SEED + field.*/ + + +/* ====================================================== Struct HSFLL ======================================================= */ +/** + * @brief HSFLL + */ + typedef struct { /*!< HSFLL Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the HSFLL */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the HSFLL */ + __IM uint32_t RESERVED[2]; + __OM uint32_t TASKS_FREQMEAS; /*!< (@ 0x00000010) Start frequency measurement in software-controlled + mode*/ + __OM uint32_t TASKS_FREQCHANGE; /*!< (@ 0x00000014) Trigger frequency change */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) HSFLL started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) HSFLL stopped */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_FREQMDONE; /*!< (@ 0x0000010C) Frequency measurement done */ + __IOM uint32_t EVENTS_FREQCHANGED; /*!< (@ 0x00000110) Frequency change done */ + __IM uint32_t RESERVED3[187]; + __IM uint32_t CLOCKSTATUS; /*!< (@ 0x00000400) Clock status */ + __IM uint32_t RESERVED4[7]; + __IOM NRF_HSFLL_FREQM_Type FREQM; /*!< (@ 0x00000420) (unspecified) */ + __IM uint32_t RESERVED5[5]; + __IOM NRF_HSFLL_TRIM_Type TRIM; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t RESERVED6[3]; + __IOM NRF_HSFLL_CLOCKCTRL_Type CLOCKCTRL; /*!< (@ 0x00000460) (unspecified) */ + __IM uint32_t RESERVED7; + __IOM uint32_t MIRROR; /*!< (@ 0x00000480) Enable LOCK for mirrored registers */ + } NRF_HSFLL_Type; /*!< Size = 1156 (0x484) */ + +/* HSFLL_TASKS_START: Start the HSFLL */ + #define HSFLL_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the HSFLL */ + #define HSFLL_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define HSFLL_TASKS_START_TASKS_START_Msk (0x1UL << HSFLL_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define HSFLL_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define HSFLL_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define HSFLL_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* HSFLL_TASKS_STOP: Stop the HSFLL */ + #define HSFLL_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the HSFLL */ + #define HSFLL_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define HSFLL_TASKS_STOP_TASKS_STOP_Msk (0x1UL << HSFLL_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define HSFLL_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define HSFLL_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define HSFLL_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* HSFLL_TASKS_FREQMEAS: Start frequency measurement in software-controlled mode */ + #define HSFLL_TASKS_FREQMEAS_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQMEAS register. */ + +/* TASKS_FREQMEAS @Bit 0 : Start frequency measurement in software-controlled mode */ + #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Pos (0UL) /*!< Position of TASKS_FREQMEAS field. */ + #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Msk (0x1UL << HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Pos) /*!< Bit mask of + TASKS_FREQMEAS field.*/ + #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQMEAS field. */ + #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQMEAS field. */ + #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Trigger (0x1UL) /*!< Trigger task */ + + +/* HSFLL_TASKS_FREQCHANGE: Trigger frequency change */ + #define HSFLL_TASKS_FREQCHANGE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQCHANGE register. */ + +/* TASKS_FREQCHANGE @Bit 0 : Trigger frequency change */ + #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Pos (0UL) /*!< Position of TASKS_FREQCHANGE field. */ + #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Msk (0x1UL << HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Pos) /*!< Bit mask of + TASKS_FREQCHANGE field.*/ + #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQCHANGE field. */ + #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQCHANGE field. */ + #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Trigger (0x1UL) /*!< Trigger task */ + + +/* HSFLL_EVENTS_STARTED: HSFLL started */ + #define HSFLL_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : HSFLL started */ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << HSFLL_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* HSFLL_EVENTS_STOPPED: HSFLL stopped */ + #define HSFLL_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : HSFLL stopped */ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* HSFLL_EVENTS_FREQMDONE: Frequency measurement done */ + #define HSFLL_EVENTS_FREQMDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FREQMDONE register. */ + +/* EVENTS_FREQMDONE @Bit 0 : Frequency measurement done */ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Pos (0UL) /*!< Position of EVENTS_FREQMDONE field. */ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Msk (0x1UL << HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Pos) /*!< Bit mask of + EVENTS_FREQMDONE field.*/ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_FREQMDONE field. */ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_FREQMDONE field. */ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Generated (0x1UL) /*!< Event generated */ + + +/* HSFLL_EVENTS_FREQCHANGED: Frequency change done */ + #define HSFLL_EVENTS_FREQCHANGED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FREQCHANGED register. */ + +/* EVENTS_FREQCHANGED @Bit 0 : Frequency change done */ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Pos (0UL) /*!< Position of EVENTS_FREQCHANGED field. */ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Msk (0x1UL << HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Pos) /*!< Bit + mask of EVENTS_FREQCHANGED field.*/ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Min (0x0UL) /*!< Min enumerator value of EVENTS_FREQCHANGED field. */ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Max (0x1UL) /*!< Max enumerator value of EVENTS_FREQCHANGED field. */ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_NotGenerated (0x0UL) /*!< Event not generated */ + #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Generated (0x1UL) /*!< Event generated */ + + +/* HSFLL_CLOCKSTATUS: Clock status */ + #define HSFLL_CLOCKSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CLOCKSTATUS register. */ + +/* MODE @Bits 0..1 : The HSFLL operating mode. */ + #define HSFLL_CLOCKSTATUS_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define HSFLL_CLOCKSTATUS_MODE_Msk (0x3UL << HSFLL_CLOCKSTATUS_MODE_Pos) /*!< Bit mask of MODE field. */ + #define HSFLL_CLOCKSTATUS_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define HSFLL_CLOCKSTATUS_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define HSFLL_CLOCKSTATUS_MODE_OpenLoop (0x0UL) /*!< Open loop mode. */ + #define HSFLL_CLOCKSTATUS_MODE_ClosedLoop (0x1UL) /*!< Closed loop mode. */ + #define HSFLL_CLOCKSTATUS_MODE_Bypass (0x2UL) /*!< Bypass mode. */ + +/* OVERRIDE @Bit 4 : HSFLL Override mode. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Pos (4UL) /*!< Position of OVERRIDE field. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKSTATUS_OVERRIDE_Pos) /*!< Bit mask of OVERRIDE field. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Min (0x0UL) /*!< Min enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Max (0x1UL) /*!< Max enumerator value of OVERRIDE field. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Disabled (0x0UL) /*!< Override mode disabled. */ + #define HSFLL_CLOCKSTATUS_OVERRIDE_Enabled (0x1UL) /*!< Override mode enabled. */ + +/* ACCURACY @Bit 9 : Clock accuracy. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_Pos (9UL) /*!< Position of ACCURACY field. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_Msk (0x1UL << HSFLL_CLOCKSTATUS_ACCURACY_Pos) /*!< Bit mask of ACCURACY field. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_Min (0x0UL) /*!< Min enumerator value of ACCURACY field. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_Max (0x1UL) /*!< Max enumerator value of ACCURACY field. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_OutsideLimit (0x0UL) /*!< Clock accuracy is outside 2 percent. */ + #define HSFLL_CLOCKSTATUS_ACCURACY_WithinLimit (0x1UL) /*!< Clock accuracy is within 2 percent. */ + +/* LOCKED @Bit 10 : The HSFLL lock status. */ + #define HSFLL_CLOCKSTATUS_LOCKED_Pos (10UL) /*!< Position of LOCKED field. */ + #define HSFLL_CLOCKSTATUS_LOCKED_Msk (0x1UL << HSFLL_CLOCKSTATUS_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define HSFLL_CLOCKSTATUS_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define HSFLL_CLOCKSTATUS_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define HSFLL_CLOCKSTATUS_LOCKED_NotLocked (0x0UL) /*!< Not locked to reference clock */ + #define HSFLL_CLOCKSTATUS_LOCKED_Locked (0x1UL) /*!< Locked to reference clock. */ + + +/* HSFLL_MIRROR: Enable LOCK for mirrored registers */ + #define HSFLL_MIRROR_ResetValue (0x00000001UL) /*!< Reset value of MIRROR register. */ + +/* LOCK @Bit 0 : Lock for mirrored registers */ + #define HSFLL_MIRROR_LOCK_Pos (0UL) /*!< Position of LOCK field. */ + #define HSFLL_MIRROR_LOCK_Msk (0x1UL << HSFLL_MIRROR_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define HSFLL_MIRROR_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define HSFLL_MIRROR_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define HSFLL_MIRROR_LOCK_Disabled (0x0UL) /*!< Lock disabled */ + #define HSFLL_MIRROR_LOCK_Enabled (0x1UL) /*!< Lock enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct I2S_CONFIG ==================================================== */ +/** + * @brief CONFIG [I2S_CONFIG] (unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) I2S clock generator control */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels */ + __IOM uint32_t CLKCONFIG; /*!< (@ 0x00000028) Clock source selection for the I2S module */ +} NRF_I2S_CONFIG_Type; /*!< Size = 44 (0x02C) */ + +/* I2S_CONFIG_MODE: I2S mode */ + #define I2S_CONFIG_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bit 0 : I2S mode */ + #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define I2S_CONFIG_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define I2S_CONFIG_MODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) + and output on pins defined by PSEL.xxx.*/ + #define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on + pins defined by PSEL.xxx*/ + + +/* I2S_CONFIG_RXEN: Reception (RX) enable */ + #define I2S_CONFIG_RXEN_ResetValue (0x00000000UL) /*!< Reset value of RXEN register. */ + +/* RXEN @Bit 0 : Reception (RX) enable */ + #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ + #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ + #define I2S_CONFIG_RXEN_RXEN_Min (0x0UL) /*!< Min enumerator value of RXEN field. */ + #define I2S_CONFIG_RXEN_RXEN_Max (0x1UL) /*!< Max enumerator value of RXEN field. */ + #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR + address.*/ + #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */ + + +/* I2S_CONFIG_TXEN: Transmission (TX) enable */ + #define I2S_CONFIG_TXEN_ResetValue (0x00000001UL) /*!< Reset value of TXEN register. */ + +/* TXEN @Bit 0 : Transmission (TX) enable */ + #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ + #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ + #define I2S_CONFIG_TXEN_TXEN_Min (0x0UL) /*!< Min enumerator value of TXEN field. */ + #define I2S_CONFIG_TXEN_TXEN_Max (0x1UL) /*!< Max enumerator value of TXEN field. */ + #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD + address.*/ + #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */ + + +/* I2S_CONFIG_MCKEN: Master clock generator enable */ + #define I2S_CONFIG_MCKEN_ResetValue (0x00000001UL) /*!< Reset value of MCKEN register. */ + +/* MCKEN @Bit 0 : Master clock generator enable */ + #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ + #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ + #define I2S_CONFIG_MCKEN_MCKEN_Min (0x0UL) /*!< Min enumerator value of MCKEN field. */ + #define I2S_CONFIG_MCKEN_MCKEN_Max (0x1UL) /*!< Max enumerator value of MCKEN field. */ + #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available + as GPIO).*/ + #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + + +/* I2S_CONFIG_MCKFREQ: I2S clock generator control */ + #define I2S_CONFIG_MCKFREQ_ResetValue (0x20000000UL) /*!< Reset value of MCKFREQ register. */ + +/* MCKFREQ @Bits 0..31 : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 + least significant bits of the register are ignored and shall be set to zero. */ + + #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_Min (0x20C0000UL) /*!< Min enumerator value of MCKFREQ field. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_Max (0x80000000UL) /*!< Max enumerator value of MCKFREQ field. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. */ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.*/ + #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. */ + + +/* I2S_CONFIG_RATIO: MCK / LRCK ratio */ + #define I2S_CONFIG_RATIO_ResetValue (0x00000006UL) /*!< Reset value of RATIO register. */ + +/* RATIO @Bits 0..3 : MCK / LRCK ratio */ + #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ + #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ + #define I2S_CONFIG_RATIO_RATIO_Min (0x0UL) /*!< Min enumerator value of RATIO field. */ + #define I2S_CONFIG_RATIO_RATIO_Max (0x8UL) /*!< Max enumerator value of RATIO field. */ + #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */ + #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */ + #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */ + #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */ + #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */ + #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */ + #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */ + #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */ + #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */ + + +/* I2S_CONFIG_SWIDTH: Sample width */ + #define I2S_CONFIG_SWIDTH_ResetValue (0x00000001UL) /*!< Reset value of SWIDTH register. */ + +/* SWIDTH @Bits 0..2 : Sample and half-frame width */ + #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_Min (0x0UL) /*!< Min enumerator value of SWIDTH field. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_Max (0x7UL) /*!< Max enumerator value of SWIDTH field. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit sample. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit sample. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit sample. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (0x3UL) /*!< 32 bit sample. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (0x4UL) /*!< 8 bit sample in a 16-bit half-frame. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (0x5UL) /*!< 8 bit sample in a 32-bit half-frame. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (0x6UL) /*!< 16 bit sample in a 32-bit half-frame. */ + #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (0x7UL) /*!< 24 bit sample in a 32-bit half-frame. */ + + +/* I2S_CONFIG_ALIGN: Alignment of sample within a frame */ + #define I2S_CONFIG_ALIGN_ResetValue (0x00000000UL) /*!< Reset value of ALIGN register. */ + +/* ALIGN @Bit 0 : Alignment of sample within a frame */ + #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ + #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ + #define I2S_CONFIG_ALIGN_ALIGN_Min (0x0UL) /*!< Min enumerator value of ALIGN field. */ + #define I2S_CONFIG_ALIGN_ALIGN_Max (0x1UL) /*!< Max enumerator value of ALIGN field. */ + #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */ + #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */ + + +/* I2S_CONFIG_FORMAT: Frame format */ + #define I2S_CONFIG_FORMAT_ResetValue (0x00000000UL) /*!< Reset value of FORMAT register. */ + +/* FORMAT @Bit 0 : Frame format */ + #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ + #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ + #define I2S_CONFIG_FORMAT_FORMAT_Min (0x0UL) /*!< Min enumerator value of FORMAT field. */ + #define I2S_CONFIG_FORMAT_FORMAT_Max (0x1UL) /*!< Max enumerator value of FORMAT field. */ + #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */ + #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */ + + +/* I2S_CONFIG_CHANNELS: Enable channels */ + #define I2S_CONFIG_CHANNELS_ResetValue (0x00000000UL) /*!< Reset value of CHANNELS register. */ + +/* CHANNELS @Bits 0..1 : Enable channels */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Min (0x0UL) /*!< Min enumerator value of CHANNELS field. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Max (0x2UL) /*!< Max enumerator value of CHANNELS field. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */ + #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */ + + +/* I2S_CONFIG_CLKCONFIG: Clock source selection for the I2S module */ + #define I2S_CONFIG_CLKCONFIG_ResetValue (0x00000000UL) /*!< Reset value of CLKCONFIG register. */ + +/* CLKSRC @Bit 0 : Clock source selection */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_Pos (0UL) /*!< Position of CLKSRC field. */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) /*!< Bit mask of CLKSRC field. */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_Min (0x0UL) /*!< Min enumerator value of CLKSRC field. */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_Max (0x1UL) /*!< Max enumerator value of CLKSRC field. */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M (0x0UL) /*!< 32MHz peripheral clock */ + #define I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK (0x1UL) /*!< Audio PLL clock */ + +/* BYPASS @Bit 8 : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no + effect. */ + + #define I2S_CONFIG_CLKCONFIG_BYPASS_Pos (8UL) /*!< Position of BYPASS field. */ + #define I2S_CONFIG_CLKCONFIG_BYPASS_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ + #define I2S_CONFIG_CLKCONFIG_BYPASS_Min (0x0UL) /*!< Min enumerator value of BYPASS field. */ + #define I2S_CONFIG_CLKCONFIG_BYPASS_Max (0x1UL) /*!< Max enumerator value of BYPASS field. */ + #define I2S_CONFIG_CLKCONFIG_BYPASS_Disable (0x0UL) /*!< Disable bypass */ + #define I2S_CONFIG_CLKCONFIG_BYPASS_Enable (0x1UL) /*!< Enable bypass */ + + + +/* ===================================================== Struct I2S_RXD ====================================================== */ +/** + * @brief RXD [I2S_RXD] (unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} NRF_I2S_RXD_Type; /*!< Size = 4 (0x004) */ + +/* I2S_RXD_PTR: Receive buffer RAM start address. */ + #define I2S_RXD_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this + address. This address is a word aligned Data RAM address. */ + + #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ===================================================== Struct I2S_TXD ====================================================== */ +/** + * @brief TXD [I2S_TXD] (unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address */ +} NRF_I2S_TXD_Type; /*!< Size = 4 (0x004) */ + +/* I2S_TXD_PTR: Transmit buffer RAM start address */ + #define I2S_TXD_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from + this address. This address is a word aligned Data RAM address. */ + + #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + + +/* ==================================================== Struct I2S_RXTXD ===================================================== */ +/** + * @brief RXTXD [I2S_RXTXD] (unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers */ + __IM uint32_t RESERVED; +} NRF_I2S_RXTXD_Type; /*!< Size = 8 (0x008) */ + +/* I2S_RXTXD_MAXCNT: Size of RXD and TXD buffers */ + #define I2S_RXTXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..13 : Size of RXD and TXD buffers in number of 32 bit words */ + #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + + +/* ===================================================== Struct I2S_PSEL ===================================================== */ +/** + * @brief PSEL [I2S_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal */ +} NRF_I2S_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* I2S_PSEL_MCK: Pin select for MCK signal */ + #define I2S_PSEL_MCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define I2S_PSEL_MCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define I2S_PSEL_MCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define I2S_PSEL_MCK_PORT_Msk (0xFUL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define I2S_PSEL_MCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define I2S_PSEL_MCK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define I2S_PSEL_MCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define I2S_PSEL_MCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* I2S_PSEL_SCK: Pin select for SCK signal */ + #define I2S_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define I2S_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define I2S_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define I2S_PSEL_SCK_PORT_Msk (0xFUL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define I2S_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define I2S_PSEL_SCK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define I2S_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define I2S_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* I2S_PSEL_LRCK: Pin select for LRCK signal */ + #define I2S_PSEL_LRCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LRCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define I2S_PSEL_LRCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define I2S_PSEL_LRCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define I2S_PSEL_LRCK_PORT_Msk (0xFUL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define I2S_PSEL_LRCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define I2S_PSEL_LRCK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define I2S_PSEL_LRCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define I2S_PSEL_LRCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* I2S_PSEL_SDIN: Pin select for SDIN signal */ + #define I2S_PSEL_SDIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDIN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define I2S_PSEL_SDIN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define I2S_PSEL_SDIN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define I2S_PSEL_SDIN_PORT_Msk (0xFUL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define I2S_PSEL_SDIN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define I2S_PSEL_SDIN_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define I2S_PSEL_SDIN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define I2S_PSEL_SDIN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* I2S_PSEL_SDOUT: Pin select for SDOUT signal */ + #define I2S_PSEL_SDOUT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDOUT register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + #define I2S_PSEL_SDOUT_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define I2S_PSEL_SDOUT_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define I2S_PSEL_SDOUT_PORT_Msk (0xFUL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ + #define I2S_PSEL_SDOUT_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define I2S_PSEL_SDOUT_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define I2S_PSEL_SDOUT_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define I2S_PSEL_SDOUT_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* ======================================================= Struct I2S ======================================================== */ +/** + * @brief Inter-IC Sound + */ + typedef struct { /*!< I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering this + task will cause the event STOPPED to be generated.*/ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[31]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started and RX + is enabled, this event will be generated for every + RXTXD.MAXCNT words received on the SDIN pin.*/ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started and TX + is enabled, this event will be generated for every + RXTXD.MAXCNT words that are sent on the SDOUT pin.*/ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x0000011C) Frame start event, generated on the active edge of + LRCK*/ + __IM uint32_t RESERVED4[25]; + __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ + __IM uint32_t RESERVED6; + __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x0000019C) Publish configuration for event FRAMESTART */ + __IM uint32_t RESERVED7[88]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module */ + __IOM NRF_I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) (unspecified) */ + __IM uint32_t RESERVED9[2]; + __IOM NRF_I2S_RXD_Type RXD; /*!< (@ 0x00000538) (unspecified) */ + __IM uint32_t RESERVED10; + __IOM NRF_I2S_TXD_Type TXD; /*!< (@ 0x00000540) (unspecified) */ + __IM uint32_t RESERVED11[3]; + __IOM NRF_I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) (unspecified) */ + __IM uint32_t RESERVED12[2]; + __IOM NRF_I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) (unspecified) */ + } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + +/* I2S_TASKS_START: Starts continuous I2S transfer. Also starts MCK generator when this is enabled */ + #define I2S_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled */ + #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define I2S_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define I2S_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* I2S_TASKS_STOP: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */ + #define I2S_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. + */ + + #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define I2S_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define I2S_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* I2S_SUBSCRIBE_START: Subscribe configuration for task START */ + #define I2S_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* I2S_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define I2S_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* I2S_EVENTS_RXPTRUPD: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX + is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */ + + #define I2S_EVENTS_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXPTRUPD register. */ + +/* EVENTS_RXPTRUPD @Bit 0 : The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and + RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */ + + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of + EVENTS_RXPTRUPD field.*/ + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXPTRUPD field. */ + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXPTRUPD field. */ + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ + #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */ + + +/* I2S_EVENTS_STOPPED: I2S transfer stopped. */ + #define I2S_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : I2S transfer stopped. */ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* I2S_EVENTS_TXPTRUPD: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX + is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ + + #define I2S_EVENTS_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXPTRUPD register. */ + +/* EVENTS_TXPTRUPD @Bit 0 : The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and + TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT + pin. */ + + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of + EVENTS_TXPTRUPD field.*/ + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXPTRUPD field. */ + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXPTRUPD field. */ + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ + #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */ + + +/* I2S_EVENTS_FRAMESTART: Frame start event, generated on the active edge of LRCK */ + #define I2S_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register. */ + +/* EVENTS_FRAMESTART @Bit 0 : Frame start event, generated on the active edge of LRCK */ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of + EVENTS_FRAMESTART field.*/ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field. */ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field. */ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */ + #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated */ + + +/* I2S_PUBLISH_RXPTRUPD: Publish configuration for event RXPTRUPD */ + #define I2S_PUBLISH_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXPTRUPD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXPTRUPD will publish to */ + #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_PUBLISH_RXPTRUPD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_PUBLISH_RXPTRUPD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_PUBLISH_RXPTRUPD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_PUBLISH_RXPTRUPD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* I2S_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define I2S_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* I2S_PUBLISH_TXPTRUPD: Publish configuration for event TXPTRUPD */ + #define I2S_PUBLISH_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXPTRUPD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXPTRUPD will publish to */ + #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_PUBLISH_TXPTRUPD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_PUBLISH_TXPTRUPD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_PUBLISH_TXPTRUPD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_PUBLISH_TXPTRUPD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* I2S_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */ + #define I2S_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */ + #define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define I2S_PUBLISH_FRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define I2S_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ + #define I2S_PUBLISH_FRAMESTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I2S_PUBLISH_FRAMESTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I2S_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define I2S_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* I2S_INTEN: Enable or disable interrupt */ + #define I2S_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* RXPTRUPD @Bit 1 : Enable or disable interrupt for event RXPTRUPD */ + #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define I2S_INTEN_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define I2S_INTEN_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */ + #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 2 : Enable or disable interrupt for event STOPPED */ + #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define I2S_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define I2S_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* TXPTRUPD @Bit 5 : Enable or disable interrupt for event TXPTRUPD */ + #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ + #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define I2S_INTEN_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define I2S_INTEN_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */ + #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */ + +/* FRAMESTART @Bit 7 : Enable or disable interrupt for event FRAMESTART */ + #define I2S_INTEN_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */ + #define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define I2S_INTEN_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define I2S_INTEN_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define I2S_INTEN_FRAMESTART_Disabled (0x0UL) /*!< Disable */ + #define I2S_INTEN_FRAMESTART_Enabled (0x1UL) /*!< Enable */ + + +/* I2S_INTENSET: Enable interrupt */ + #define I2S_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* RXPTRUPD @Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ + #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define I2S_INTENSET_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define I2S_INTENSET_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */ + #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 2 : Write '1' to enable interrupt for event STOPPED */ + #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define I2S_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define I2S_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXPTRUPD @Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ + #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ + #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define I2S_INTENSET_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define I2S_INTENSET_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */ + #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 7 : Write '1' to enable interrupt for event FRAMESTART */ + #define I2S_INTENSET_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */ + #define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define I2S_INTENSET_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define I2S_INTENSET_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define I2S_INTENSET_FRAMESTART_Set (0x1UL) /*!< Enable */ + #define I2S_INTENSET_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENSET_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* I2S_INTENCLR: Disable interrupt */ + #define I2S_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* RXPTRUPD @Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ + #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ + #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ + #define I2S_INTENCLR_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of RXPTRUPD field. */ + #define I2S_INTENCLR_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of RXPTRUPD field. */ + #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */ + #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 2 : Write '1' to disable interrupt for event STOPPED */ + #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ + #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define I2S_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define I2S_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXPTRUPD @Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ + #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ + #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ + #define I2S_INTENCLR_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of TXPTRUPD field. */ + #define I2S_INTENCLR_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of TXPTRUPD field. */ + #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */ + #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 7 : Write '1' to disable interrupt for event FRAMESTART */ + #define I2S_INTENCLR_FRAMESTART_Pos (7UL) /*!< Position of FRAMESTART field. */ + #define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define I2S_INTENCLR_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define I2S_INTENCLR_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define I2S_INTENCLR_FRAMESTART_Clear (0x1UL) /*!< Disable */ + #define I2S_INTENCLR_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define I2S_INTENCLR_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* I2S_ENABLE: Enable I2S module */ + #define I2S_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable I2S module */ + #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define I2S_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define I2S_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ I3C ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct I3C_CDR ====================================================== */ +/** + * @brief CDR [I3C_CDR] (unspecified) + */ +typedef struct { + __IOM uint32_t STARTOFFSET; /*!< (@ 0x00000000) Start offset of recovered clock */ + __IOM uint32_t MAXCYCLERATIO; /*!< (@ 0x00000004) Maximum cycle ratio between SDA/SCL and CDR (clock and + data recovery) clock*/ + __IOM uint32_t MAXSKEW; /*!< (@ 0x00000008) Maximum skew between SCL and SCL in CDR clock cycles */ +} NRF_I3C_CDR_Type; /*!< Size = 12 (0x00C) */ + +/* I3C_CDR_STARTOFFSET: Start offset of recovered clock */ + #define I3C_CDR_STARTOFFSET_ResetValue (0x00000004UL) /*!< Reset value of STARTOFFSET register. */ + +/* VAL @Bits 0..15 : Value */ + #define I3C_CDR_STARTOFFSET_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define I3C_CDR_STARTOFFSET_VAL_Msk (0xFFFFUL << I3C_CDR_STARTOFFSET_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* I3C_CDR_MAXCYCLERATIO: Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock */ + #define I3C_CDR_MAXCYCLERATIO_ResetValue (0x0000001CUL) /*!< Reset value of MAXCYCLERATIO register. */ + +/* VAL @Bits 0..15 : Value */ + #define I3C_CDR_MAXCYCLERATIO_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define I3C_CDR_MAXCYCLERATIO_VAL_Msk (0xFFFFUL << I3C_CDR_MAXCYCLERATIO_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* I3C_CDR_MAXSKEW: Maximum skew between SCL and SCL in CDR clock cycles */ + #define I3C_CDR_MAXSKEW_ResetValue (0x00000005UL) /*!< Reset value of MAXSKEW register. */ + +/* VAL @Bits 0..7 : Value */ + #define I3C_CDR_MAXSKEW_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define I3C_CDR_MAXSKEW_VAL_Msk (0xFFUL << I3C_CDR_MAXSKEW_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/* ======================================================= Struct I3C ======================================================== */ +/** + * @brief I3C + */ + typedef struct { /*!< I3C Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_CORE; /*!< (@ 0x00000100) Event indicating that interrupt triggered at I3C core */ + __IOM uint32_t EVENTS_DMA; /*!< (@ 0x00000104) Event indicating that interrupt triggered at I3C DMA */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000400) Enable I3C peripheral. */ + __IOM NRF_I3C_CDR_Type CDR; /*!< (@ 0x00000404) (unspecified) */ + __IOM uint32_t SLAVEIF0; /*!< (@ 0x00000410) I3C slave interface 0 */ + __IOM uint32_t SLAVEIF1; /*!< (@ 0x00000414) I3C slave interface 1 */ + __IOM uint32_t SLAVEPID0; /*!< (@ 0x00000418) Slave Device Provisioned ID 0 */ + __IOM uint32_t SLAVEPID1; /*!< (@ 0x0000041C) Slave Device Provisioned ID 1 */ + __IOM uint32_t KEEPSDA; /*!< (@ 0x00000420) Enable or disable the SDA high-keeper used for + Master-to-Slave and Slave-to-Master bus hand-off.*/ + __IOM uint32_t KEEPSCL; /*!< (@ 0x00000424) Enable or disable the SCL high-keeper used for + Master-to-Slave and Slave-to-Master bus hand-off.*/ + } NRF_I3C_Type; /*!< Size = 1064 (0x428) */ + +/* I3C_EVENTS_CORE: Event indicating that interrupt triggered at I3C core */ + #define I3C_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE register. */ + +/* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at I3C core */ + #define I3C_EVENTS_CORE_EVENTS_CORE_Pos (0UL) /*!< Position of EVENTS_CORE field. */ + #define I3C_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << I3C_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ + #define I3C_EVENTS_CORE_EVENTS_CORE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ + #define I3C_EVENTS_CORE_EVENTS_CORE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ + #define I3C_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated */ + #define I3C_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated */ + + +/* I3C_EVENTS_DMA: Event indicating that interrupt triggered at I3C DMA */ + #define I3C_EVENTS_DMA_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DMA register. */ + +/* EVENTS_DMA @Bit 0 : Event indicating that interrupt triggered at I3C DMA */ + #define I3C_EVENTS_DMA_EVENTS_DMA_Pos (0UL) /*!< Position of EVENTS_DMA field. */ + #define I3C_EVENTS_DMA_EVENTS_DMA_Msk (0x1UL << I3C_EVENTS_DMA_EVENTS_DMA_Pos) /*!< Bit mask of EVENTS_DMA field. */ + #define I3C_EVENTS_DMA_EVENTS_DMA_Min (0x0UL) /*!< Min enumerator value of EVENTS_DMA field. */ + #define I3C_EVENTS_DMA_EVENTS_DMA_Max (0x1UL) /*!< Max enumerator value of EVENTS_DMA field. */ + #define I3C_EVENTS_DMA_EVENTS_DMA_NotGenerated (0x0UL) /*!< Event not generated */ + #define I3C_EVENTS_DMA_EVENTS_DMA_Generated (0x1UL) /*!< Event generated */ + + +/* I3C_INTEN: Enable or disable interrupt */ + #define I3C_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CORE @Bit 0 : Enable or disable interrupt for event CORE */ + #define I3C_INTEN_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define I3C_INTEN_CORE_Msk (0x1UL << I3C_INTEN_CORE_Pos) /*!< Bit mask of CORE field. */ + #define I3C_INTEN_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define I3C_INTEN_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define I3C_INTEN_CORE_Disabled (0x0UL) /*!< Disable */ + #define I3C_INTEN_CORE_Enabled (0x1UL) /*!< Enable */ + +/* DMA @Bit 1 : Enable or disable interrupt for event DMA */ + #define I3C_INTEN_DMA_Pos (1UL) /*!< Position of DMA field. */ + #define I3C_INTEN_DMA_Msk (0x1UL << I3C_INTEN_DMA_Pos) /*!< Bit mask of DMA field. */ + #define I3C_INTEN_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define I3C_INTEN_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define I3C_INTEN_DMA_Disabled (0x0UL) /*!< Disable */ + #define I3C_INTEN_DMA_Enabled (0x1UL) /*!< Enable */ + + +/* I3C_INTENSET: Enable interrupt */ + #define I3C_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */ + #define I3C_INTENSET_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define I3C_INTENSET_CORE_Msk (0x1UL << I3C_INTENSET_CORE_Pos) /*!< Bit mask of CORE field. */ + #define I3C_INTENSET_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define I3C_INTENSET_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define I3C_INTENSET_CORE_Set (0x1UL) /*!< Enable */ + #define I3C_INTENSET_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define I3C_INTENSET_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMA @Bit 1 : Write '1' to enable interrupt for event DMA */ + #define I3C_INTENSET_DMA_Pos (1UL) /*!< Position of DMA field. */ + #define I3C_INTENSET_DMA_Msk (0x1UL << I3C_INTENSET_DMA_Pos) /*!< Bit mask of DMA field. */ + #define I3C_INTENSET_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define I3C_INTENSET_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define I3C_INTENSET_DMA_Set (0x1UL) /*!< Enable */ + #define I3C_INTENSET_DMA_Disabled (0x0UL) /*!< Read: Disabled */ + #define I3C_INTENSET_DMA_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* I3C_INTENCLR: Disable interrupt */ + #define I3C_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */ + #define I3C_INTENCLR_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define I3C_INTENCLR_CORE_Msk (0x1UL << I3C_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field. */ + #define I3C_INTENCLR_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define I3C_INTENCLR_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define I3C_INTENCLR_CORE_Clear (0x1UL) /*!< Disable */ + #define I3C_INTENCLR_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define I3C_INTENCLR_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMA @Bit 1 : Write '1' to disable interrupt for event DMA */ + #define I3C_INTENCLR_DMA_Pos (1UL) /*!< Position of DMA field. */ + #define I3C_INTENCLR_DMA_Msk (0x1UL << I3C_INTENCLR_DMA_Pos) /*!< Bit mask of DMA field. */ + #define I3C_INTENCLR_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define I3C_INTENCLR_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define I3C_INTENCLR_DMA_Clear (0x1UL) /*!< Disable */ + #define I3C_INTENCLR_DMA_Disabled (0x0UL) /*!< Read: Disabled */ + #define I3C_INTENCLR_DMA_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* I3C_INTPEND: Pending interrupts */ + #define I3C_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* CORE @Bit 0 : Read pending status of interrupt for event CORE */ + #define I3C_INTPEND_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define I3C_INTPEND_CORE_Msk (0x1UL << I3C_INTPEND_CORE_Pos) /*!< Bit mask of CORE field. */ + #define I3C_INTPEND_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define I3C_INTPEND_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define I3C_INTPEND_CORE_NotPending (0x0UL) /*!< Read: Not pending */ + #define I3C_INTPEND_CORE_Pending (0x1UL) /*!< Read: Pending */ + +/* DMA @Bit 1 : Read pending status of interrupt for event DMA */ + #define I3C_INTPEND_DMA_Pos (1UL) /*!< Position of DMA field. */ + #define I3C_INTPEND_DMA_Msk (0x1UL << I3C_INTPEND_DMA_Pos) /*!< Bit mask of DMA field. */ + #define I3C_INTPEND_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define I3C_INTPEND_DMA_Max (0x1UL) /*!< Max enumerator value of DMA field. */ + #define I3C_INTPEND_DMA_NotPending (0x0UL) /*!< Read: Not pending */ + #define I3C_INTPEND_DMA_Pending (0x1UL) /*!< Read: Pending */ + + +/* I3C_ENABLE: Enable I3C peripheral. */ + #define I3C_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* EN @Bit 0 : Enable */ + #define I3C_ENABLE_EN_Pos (0UL) /*!< Position of EN field. */ + #define I3C_ENABLE_EN_Msk (0x1UL << I3C_ENABLE_EN_Pos) /*!< Bit mask of EN field. */ + #define I3C_ENABLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define I3C_ENABLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define I3C_ENABLE_EN_Disabled (0x0UL) /*!< I3C peripheral disabled. */ + #define I3C_ENABLE_EN_Enabled (0x1UL) /*!< I3C peripheral enabled. */ + + +/* I3C_SLAVEIF0: I3C slave interface 0 */ + #define I3C_SLAVEIF0_ResetValue (0x00000000UL) /*!< Reset value of SLAVEIF0 register. */ + +/* MODEI2C @Bit 0 : I2C or I3C mode select signal */ + #define I3C_SLAVEIF0_MODEI2C_Pos (0UL) /*!< Position of MODEI2C field. */ + #define I3C_SLAVEIF0_MODEI2C_Msk (0x1UL << I3C_SLAVEIF0_MODEI2C_Pos) /*!< Bit mask of MODEI2C field. */ + #define I3C_SLAVEIF0_MODEI2C_Min (0x0UL) /*!< Min enumerator value of MODEI2C field. */ + #define I3C_SLAVEIF0_MODEI2C_Max (0x1UL) /*!< Max enumerator value of MODEI2C field. */ + #define I3C_SLAVEIF0_MODEI2C_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3C_SLAVEIF0_MODEI2C_ENABLED (0x1UL) /*!< (unspecified) */ + +/* ACTMODE @Bits 1..2 : Slave activity mode for GETSTATUS CCC */ + #define I3C_SLAVEIF0_ACTMODE_Pos (1UL) /*!< Position of ACTMODE field. */ + #define I3C_SLAVEIF0_ACTMODE_Msk (0x3UL << I3C_SLAVEIF0_ACTMODE_Pos) /*!< Bit mask of ACTMODE field. */ + +/* PENDINGINT @Bits 3..6 : Pending interrupt information for GETSTATUS CCC */ + #define I3C_SLAVEIF0_PENDINGINT_Pos (3UL) /*!< Position of PENDINGINT field. */ + #define I3C_SLAVEIF0_PENDINGINT_Msk (0xFUL << I3C_SLAVEIF0_PENDINGINT_Pos) /*!< Bit mask of PENDINGINT field. */ + +/* STATICADDREN @Bit 7 : Slave static address valid */ + #define I3C_SLAVEIF0_STATICADDREN_Pos (7UL) /*!< Position of STATICADDREN field. */ + #define I3C_SLAVEIF0_STATICADDREN_Msk (0x1UL << I3C_SLAVEIF0_STATICADDREN_Pos) /*!< Bit mask of STATICADDREN field. */ + #define I3C_SLAVEIF0_STATICADDREN_Min (0x0UL) /*!< Min enumerator value of STATICADDREN field. */ + #define I3C_SLAVEIF0_STATICADDREN_Max (0x1UL) /*!< Max enumerator value of STATICADDREN field. */ + #define I3C_SLAVEIF0_STATICADDREN_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3C_SLAVEIF0_STATICADDREN_ENABLED (0x1UL) /*!< (unspecified) */ + +/* STATICADDR @Bits 8..14 : Slave static address */ + #define I3C_SLAVEIF0_STATICADDR_Pos (8UL) /*!< Position of STATICADDR field. */ + #define I3C_SLAVEIF0_STATICADDR_Msk (0x7FUL << I3C_SLAVEIF0_STATICADDR_Pos) /*!< Bit mask of STATICADDR field. */ + +/* SLAVEMAXRDSPEED @Bits 15..17 : Slave maximum read data rate */ + #define I3C_SLAVEIF0_SLAVEMAXRDSPEED_Pos (15UL) /*!< Position of SLAVEMAXRDSPEED field. */ + #define I3C_SLAVEIF0_SLAVEMAXRDSPEED_Msk (0x7UL << I3C_SLAVEIF0_SLAVEMAXRDSPEED_Pos) /*!< Bit mask of SLAVEMAXRDSPEED field. */ + +/* SLAVEMAXWRSPEED @Bits 18..20 : Slave maximum write write rate */ + #define I3C_SLAVEIF0_SLAVEMAXWRSPEED_Pos (18UL) /*!< Position of SLAVEMAXWRSPEED field. */ + #define I3C_SLAVEIF0_SLAVEMAXWRSPEED_Msk (0x7UL << I3C_SLAVEIF0_SLAVEMAXWRSPEED_Pos) /*!< Bit mask of SLAVEMAXWRSPEED field. */ + +/* SLAVECLKDATATURNTIME @Bits 21..23 : Slave maximum clock data turnaround time */ + #define I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Pos (21UL) /*!< Position of SLAVECLKDATATURNTIME field. */ + #define I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Msk (0x7UL << I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Pos) /*!< Bit mask of + SLAVECLKDATATURNTIME field.*/ + +/* SLAVEDCR @Bits 24..31 : Device Characteristic Register value */ + #define I3C_SLAVEIF0_SLAVEDCR_Pos (24UL) /*!< Position of SLAVEDCR field. */ + #define I3C_SLAVEIF0_SLAVEDCR_Msk (0xFFUL << I3C_SLAVEIF0_SLAVEDCR_Pos) /*!< Bit mask of SLAVEDCR field. */ + + +/* I3C_SLAVEIF1: I3C slave interface 1 */ + #define I3C_SLAVEIF1_ResetValue (0x00000000UL) /*!< Reset value of SLAVEIF1 register. */ + +/* WAKEUP @Bit 0 : Slave wakeup signal */ + #define I3C_SLAVEIF1_WAKEUP_Pos (0UL) /*!< Position of WAKEUP field. */ + #define I3C_SLAVEIF1_WAKEUP_Msk (0x1UL << I3C_SLAVEIF1_WAKEUP_Pos) /*!< Bit mask of WAKEUP field. */ + #define I3C_SLAVEIF1_WAKEUP_Min (0x0UL) /*!< Min enumerator value of WAKEUP field. */ + #define I3C_SLAVEIF1_WAKEUP_Max (0x1UL) /*!< Max enumerator value of WAKEUP field. */ + #define I3C_SLAVEIF1_WAKEUP_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3C_SLAVEIF1_WAKEUP_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3C_SLAVEPID0: Slave Device Provisioned ID 0 */ + #define I3C_SLAVEPID0_ResetValue (0x00000000UL) /*!< Reset value of SLAVEPID0 register. */ + +/* ADDMEANING @Bits 0..11 : Additional Meaning */ + #define I3C_SLAVEPID0_ADDMEANING_Pos (0UL) /*!< Position of ADDMEANING field. */ + #define I3C_SLAVEPID0_ADDMEANING_Msk (0xFFFUL << I3C_SLAVEPID0_ADDMEANING_Pos) /*!< Bit mask of ADDMEANING field. */ + +/* INSTANCEID @Bits 12..15 : Instance ID */ + #define I3C_SLAVEPID0_INSTANCEID_Pos (12UL) /*!< Position of INSTANCEID field. */ + #define I3C_SLAVEPID0_INSTANCEID_Msk (0xFUL << I3C_SLAVEPID0_INSTANCEID_Pos) /*!< Bit mask of INSTANCEID field. */ + +/* PARTID @Bits 16..31 : Part ID */ + #define I3C_SLAVEPID0_PARTID_Pos (16UL) /*!< Position of PARTID field. */ + #define I3C_SLAVEPID0_PARTID_Msk (0xFFFFUL << I3C_SLAVEPID0_PARTID_Pos) /*!< Bit mask of PARTID field. */ + + +/* I3C_SLAVEPID1: Slave Device Provisioned ID 1 */ + #define I3C_SLAVEPID1_ResetValue (0x00000000UL) /*!< Reset value of SLAVEPID1 register. */ + +/* PROVID @Bit 0 : Provisional ID Type Selector */ + #define I3C_SLAVEPID1_PROVID_Pos (0UL) /*!< Position of PROVID field. */ + #define I3C_SLAVEPID1_PROVID_Msk (0x1UL << I3C_SLAVEPID1_PROVID_Pos) /*!< Bit mask of PROVID field. */ + +/* MIPIMID @Bits 1..15 : MIPI Manufacturer ID */ + #define I3C_SLAVEPID1_MIPIMID_Pos (1UL) /*!< Position of MIPIMID field. */ + #define I3C_SLAVEPID1_MIPIMID_Msk (0x7FFFUL << I3C_SLAVEPID1_MIPIMID_Pos) /*!< Bit mask of MIPIMID field. */ + + +/* I3C_KEEPSDA: Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. */ + #define I3C_KEEPSDA_ResetValue (0x00000000UL) /*!< Reset value of KEEPSDA register. */ + +/* ENABLE @Bit 0 : Enable or disable the SDA high-keeper */ + #define I3C_KEEPSDA_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define I3C_KEEPSDA_ENABLE_Msk (0x1UL << I3C_KEEPSDA_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define I3C_KEEPSDA_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define I3C_KEEPSDA_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define I3C_KEEPSDA_ENABLE_Disabled (0x0UL) /*!< High-keeper disabled. */ + #define I3C_KEEPSDA_ENABLE_Enabled (0x1UL) /*!< High-keeper enabled. */ + + +/* I3C_KEEPSCL: Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. */ + #define I3C_KEEPSCL_ResetValue (0x00000000UL) /*!< Reset value of KEEPSCL register. */ + +/* ENABLE @Bit 0 : Enable or disable the SCL high-keeper */ + #define I3C_KEEPSCL_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define I3C_KEEPSCL_ENABLE_Msk (0x1UL << I3C_KEEPSCL_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define I3C_KEEPSCL_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define I3C_KEEPSCL_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define I3C_KEEPSCL_ENABLE_Disabled (0x0UL) /*!< High-keeper disabled. */ + #define I3C_KEEPSCL_ENABLE_Enabled (0x1UL) /*!< High-keeper enabled. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ I3CCORE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================ Struct I3CCORE_CORE_DEVCHARTABLE ============================================= */ +/** + * @brief DEVCHARTABLE [I3CCORE_CORE_DEVCHARTABLE] (unspecified) + */ +typedef struct { + __IOM uint32_t LOC1; /*!< (@ 0x00000000) Device Characteristic Table Location-1 of Device [n] */ + __IOM uint32_t LOC2; /*!< (@ 0x00000004) Device Characteristic Table Location-2 of Device [n] */ + __IOM uint32_t LOC3; /*!< (@ 0x00000008) Device Characteristic Table Location-3 of Device [n] */ + __IOM uint32_t LOC4; /*!< (@ 0x0000000C) Device Characteristic Table Location-4 of Device [n] */ +} NRF_I3CCORE_CORE_DEVCHARTABLE_Type; /*!< Size = 16 (0x010) */ + #define I3CCORE_CORE_DEVCHARTABLE_MaxCount (10UL) /*!< Size of DEVCHARTABLE[10] array. */ + #define I3CCORE_CORE_DEVCHARTABLE_MaxIndex (9UL) /*!< Max index of DEVCHARTABLE[10] array. */ + #define I3CCORE_CORE_DEVCHARTABLE_MinIndex (0UL) /*!< Min index of DEVCHARTABLE[10] array. */ + +/* I3CCORE_CORE_DEVCHARTABLE_LOC1: Device Characteristic Table Location-1 of Device [n] */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC1_ResetValue (0x00000000UL) /*!< Reset value of LOC1 register. */ + +/* LSBPROVISIONALID @Bits 0..31 : The LSB 32-bit value of Provisional-ID */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Pos (0UL) /*!< Position of LSBPROVISIONALID field. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Msk (0xFFFFFFFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Pos) + /*!< Bit mask of LSBPROVISIONALID field.*/ + + +/* I3CCORE_CORE_DEVCHARTABLE_LOC2: Device Characteristic Table Location-2 of Device [n] */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC2_ResetValue (0x00000000UL) /*!< Reset value of LOC2 register. */ + +/* MSBPROVISIONALID @Bits 0..15 : The MSB 16-bit value of Provisional-ID */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Pos (0UL) /*!< Position of MSBPROVISIONALID field. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Msk (0xFFFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Pos) + /*!< Bit mask of MSBPROVISIONALID field.*/ + + +/* I3CCORE_CORE_DEVCHARTABLE_LOC3: Device Characteristic Table Location-3 of Device [n] */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC3_ResetValue (0x00000000UL) /*!< Reset value of LOC3 register. */ + +/* DCR @Bits 0..7 : Device Characteristic Value */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Pos (0UL) /*!< Position of DCR field. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Pos) /*!< Bit mask of DCR field.*/ + +/* BCR @Bits 8..15 : Bus Characteristic Value */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Pos (8UL) /*!< Position of BCR field. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Pos) /*!< Bit mask of BCR field.*/ + + +/* I3CCORE_CORE_DEVCHARTABLE_LOC4: Device Characteristic Table Location-4 of Device [n] */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC4_ResetValue (0x00000000UL) /*!< Reset value of LOC4 register. */ + +/* DEVDYNAMICADDR @Bits 0..7 : Device Dynamic Address assigned. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Pos (0UL) /*!< Position of DEVDYNAMICADDR field. */ + #define I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Pos) /*!< + Bit mask of DEVDYNAMICADDR field.*/ + + + +/* =================================================== Struct I3CCORE_CORE =================================================== */ +/** + * @brief CORE [I3CCORE_CORE] (unspecified) + */ +typedef struct { + __IOM uint32_t DEVICECTRL; /*!< (@ 0x00000000) DWC_mipi_i3c control Register */ + __IOM uint32_t DEVICEADDR; /*!< (@ 0x00000004) In the master mode of operation this Register is used + to program the Device Dynamic Addresses and its + respective valid bit.*/ + __IOM uint32_t HWCAPABILITY; /*!< (@ 0x00000008) Hardware Capability register */ + __IOM uint32_t COMMANDQUEUEPORT; /*!< (@ 0x0000000C) Command Queue Port. */ + __IOM uint32_t RESPONSEQUEUEPORT; /*!< (@ 0x00000010) Response Queue Port */ + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM uint32_t RXDATAPORT; /*!< (@ 0x00000014) Receive Data Port Register */ + __IOM uint32_t TXDATAPORT; /*!< (@ 0x00000014) Transmit Data Port Register */ + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM uint32_t IBIQUEUEDATA; /*!< (@ 0x00000018) In-Band Interrupt Queue Data Register */ + __IOM uint32_t IBIQUEUESTATUS; /*!< (@ 0x00000018) In-Band Interrupt Queue Status Register */ + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + __IOM uint32_t QUEUETHLDCTRL; /*!< (@ 0x0000001C) Queue Threshold Control Register */ + __IOM uint32_t DATABUFFERTHLDCTRL; /*!< (@ 0x00000020) Data Buffer Threshold Control Register */ + __IOM uint32_t IBIQUEUECTRL; /*!< (@ 0x00000024) This Register is used to control whether or not to + intimate the application if an IBI request is rejected + (Nacked).*/ + __IM uint32_t RESERVED; + __IOM uint32_t IBIMRREQREJECT; /*!< (@ 0x0000002C) IBI Master Request Rejection Control Register. */ + __IOM uint32_t IBISIRREQREJECT; /*!< (@ 0x00000030) IBI SIR Request Rejection Control */ + __IOM uint32_t RESETCTRL; /*!< (@ 0x00000034) This Register is used for general software reset and + for individual buffer reset.*/ + __IOM uint32_t SLVEVENTSTATUS; /*!< (@ 0x00000038) This register indicates the status/values of some + events/controls that are relavant to slave mode of + operation.*/ + __IOM uint32_t INTRSTATUS; /*!< (@ 0x0000003C) Interrupt Status Register */ + __IOM uint32_t INTRSTATUSEN; /*!< (@ 0x00000040) Interrupt Status Enable Register. */ + __IOM uint32_t INTRSIGNALEN; /*!< (@ 0x00000044) Interrupt Signal Enable Register */ + __IOM uint32_t INTRFORCE; /*!< (@ 0x00000048) Interrupt Force Enable Register */ + __IOM uint32_t QUEUESTATUSLEVEL; /*!< (@ 0x0000004C) Queue Status Level Register. */ + __IOM uint32_t DATABUFFERSTATUSLEVEL; /*!< (@ 0x00000050) Data Buffer Status Level Register. */ + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM uint32_t PRESENTSTATEM; /*!< (@ 0x00000054) The user can get status of the DWC_mipi_i3c Controller + from this 32-bit read only register (Master).*/ + __IOM uint32_t PRESENTSTATES; /*!< (@ 0x00000054) The user can get status of the DWC_mipi_i3c Controller + from this 32-bit read only register (Slave).*/ + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + __IOM uint32_t CCCDEVICESTATUS; /*!< (@ 0x00000058) Device Operating Status Register. */ + __IOM uint32_t DEVICEADDRTABLEPOINTER; /*!< (@ 0x0000005C) Pointer for Device Address Table */ + __IOM uint32_t DEVCHARTABLEPOINTER; /*!< (@ 0x00000060) Pointer for Device Characteristics Table */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t VENDORSPECIFICREGPOINTER; /*!< (@ 0x0000006C) Pointer for Vendor Specific Registers. */ + __IOM uint32_t SLVMIPIIDVALUE; /*!< (@ 0x00000070) I3C MIPI Manufacturer ID Register. */ + __IOM uint32_t SLVPIDVALUE; /*!< (@ 0x00000074) I3C Normal Provisional ID Register. */ + __IOM uint32_t SLVCHARCTRL; /*!< (@ 0x00000078) I3C Slave Characteristic Register. */ + __IOM uint32_t SLVMAXLEN; /*!< (@ 0x0000007C) I3C Max Write/Read Length Register. */ + __IOM uint32_t MAXREADTURNAROUND; /*!< (@ 0x00000080) MXDS Maximum Read Turnaround Time. */ + __IOM uint32_t MAXDATASPEED; /*!< (@ 0x00000084) The values in this register are returned by the slave + as GETACCMST CCC data.*/ + __IM uint32_t RESERVED2; + __IOM uint32_t SLVINTRREQ; /*!< (@ 0x0000008C) This register is used in slave mode of operation. */ + __IOM uint32_t SLVTSXSYMBLTIMING; /*!< (@ 0x00000090) TSP/TSL Symbol Timing Register */ + __IM uint32_t RESERVED3[7]; + __IOM uint32_t DEVICECTRLEXTENDED; /*!< (@ 0x000000B0) Device Control Extended register. */ + __IOM uint32_t SCLI3CODTIMING; /*!< (@ 0x000000B4) SCL I3C Open Drain Timing Register */ + __IOM uint32_t SCLI3CPPTIMING; /*!< (@ 0x000000B8) SCL I3C Push Pull Timing Register */ + __IOM uint32_t SCLI2CFMTIMING; /*!< (@ 0x000000BC) SCL I2C Fast Mode Timing Register */ + __IOM uint32_t SCLI2CFMPTIMING; /*!< (@ 0x000000C0) SCL I2C Fast Mode Plus Timing Register */ + __IM uint32_t RESERVED4; + __IOM uint32_t SCLEXTLCNTTIMING; /*!< (@ 0x000000C8) SCL Extended Low Count Timing Register. */ + __IOM uint32_t SCLEXTTERMNLCNTTIMING; /*!< (@ 0x000000CC) SCL Termination Bit Low Count Timing Register */ + __IOM uint32_t SDAHOLDSWITCHDLYTIMING; /*!< (@ 0x000000D0) SDA Hold and Mode Switch Delay Timing Register */ + __IOM uint32_t BUSFREEAVAILTIMING; /*!< (@ 0x000000D4) Bus Free and Available Timing Register */ + __IOM uint32_t BUSIDLETIMING; /*!< (@ 0x000000D8) Bus Idle Timing Register */ + __IOM uint32_t SCLLOWMSTEXTTIMEOUT; /*!< (@ 0x000000DC) The SCL Low Master Extended Timeout register is used to + define the duration of the SCL Low Bus Reset Pattern.*/ + __IOM uint32_t I3CVERID; /*!< (@ 0x000000E0) This register reflects the current release number of + DWC_mipi_i3c*/ + __IOM uint32_t I3CVERTYPE; /*!< (@ 0x000000E4) This register reflects the current release type of + DWC_mipi_i3c.*/ + __IOM uint32_t QUEUESIZECAPABILITY; /*!< (@ 0x000000E8) This register reflects the configured size of the Data + Buffer and Queues in DWC_mipi_i3c.*/ + __IM uint32_t RESERVED5[69]; + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM NRF_I3CCORE_CORE_DEVCHARTABLE_Type DEVCHARTABLE[10]; /*!< (@ 0x00000200) (unspecified) */ + __IOM uint32_t SECDEVCHARTABLE[32]; /*!< (@ 0x00000200) Secondary Master Device Characteristic Table Location + of Device [n]*/ + __IM uint32_t RESERVED6[40]; + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + __IM uint32_t RESERVED7[8]; + __IOM uint32_t DEVADDRTABLELOC[10]; /*!< (@ 0x000002C0) Device Address Table of Device [n] */ +} NRF_I3CCORE_CORE_Type; /*!< Size = 744 (0x2E8) */ + +/* I3CCORE_CORE_DEVICECTRL: DWC_mipi_i3c control Register */ + #define I3CCORE_CORE_DEVICECTRL_ResetValue (0x00000000UL) /*!< Reset value of DEVICECTRL register. */ + +/* IBAINCLUDE @Bit 0 : I3C Broadcast Address include */ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Pos (0UL) /*!< Position of IBAINCLUDE field. */ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Pos) /*!< Bit mask of IBAINCLUDE + field.*/ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Min (0x0UL) /*!< Min enumerator value of IBAINCLUDE field. */ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Max (0x1UL) /*!< Max enumerator value of IBAINCLUDE field. */ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_NOT_INCLUDED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_INCLUDED (0x1UL) /*!< (unspecified) */ + +/* I2CSLAVEPRESENT @Bit 7 : I2C Slave Present */ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Pos (7UL) /*!< Position of I2CSLAVEPRESENT field. */ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Pos) /*!< Bit mask of + I2CSLAVEPRESENT field.*/ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Min (0x0UL) /*!< Min enumerator value of I2CSLAVEPRESENT field. */ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Max (0x1UL) /*!< Max enumerator value of I2CSLAVEPRESENT field. */ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_ENABLED (0x1UL) /*!< (unspecified) */ + +/* HOTJOINCTRL @Bit 8 : Hot-Join ACK/NACK Control */ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Pos (8UL) /*!< Position of HOTJOINCTRL field. */ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Pos) /*!< Bit mask of + HOTJOINCTRL field.*/ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Min (0x0UL) /*!< Min enumerator value of HOTJOINCTRL field. */ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Max (0x1UL) /*!< Max enumerator value of HOTJOINCTRL field. */ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_ENABLED (0x1UL) /*!< (unspecified) */ + +/* IDLECNTMULTPLIER @Bits 24..25 : Idle Count Multiplier */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Pos (24UL) /*!< Position of IDLECNTMULTPLIER field. */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Msk (0x3UL << I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Pos) /*!< Bit mask of + IDLECNTMULTPLIER field.*/ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Min (0x0UL) /*!< Min enumerator value of IDLECNTMULTPLIER field. */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Max (0x3UL) /*!< Max enumerator value of IDLECNTMULTPLIER field. */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy4 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy8 (0x3UL) /*!< (unspecified) */ + +/* ADAPTIVEI2CI3C @Bit 27 : This field is used in Slave mode of operation. */ + #define I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Pos (27UL) /*!< Position of ADAPTIVEI2CI3C field. */ + #define I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Pos) /*!< Bit mask of + ADAPTIVEI2CI3C field.*/ + +/* DMAENABLE @Bit 28 : DMA Handshake Interface Enable */ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Pos (28UL) /*!< Position of DMAENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_DMAENABLE_Pos) /*!< Bit mask of DMAENABLE + field.*/ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Min (0x0UL) /*!< Min enumerator value of DMAENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Max (0x1UL) /*!< Max enumerator value of DMAENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_DISABLE (0x0UL) /*!< The DMA handshake control has no significance. */ + #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_ENABLE (0x1UL) /*!< Enables the DMA handshake control to interact with external + DMA.*/ + +/* ABORT @Bit 29 : DWC_mipi_i3c Abort */ + #define I3CCORE_CORE_DEVICECTRL_ABORT_Pos (29UL) /*!< Position of ABORT field. */ + #define I3CCORE_CORE_DEVICECTRL_ABORT_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ABORT_Pos) /*!< Bit mask of ABORT field. */ + +/* RESUME @Bit 30 : DWC_mipi_i3c Resume */ + #define I3CCORE_CORE_DEVICECTRL_RESUME_Pos (30UL) /*!< Position of RESUME field. */ + #define I3CCORE_CORE_DEVICECTRL_RESUME_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_RESUME_Pos) /*!< Bit mask of RESUME field. */ + +/* ENABLE @Bit 31 : Controls whether or not DWC_mipi_i3c is enabled. */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_DISABLE (0x0UL) /*!< Disables the DWC_mipi_i3c controller */ + #define I3CCORE_CORE_DEVICECTRL_ENABLE_ENABLE (0x1UL) /*!< Enables the DWC_mipi_i3c controller. */ + + +/* I3CCORE_CORE_DEVICEADDR: In the master mode of operation this Register is used to program the Device Dynamic Addresses and + its respective valid bit. */ + + #define I3CCORE_CORE_DEVICEADDR_ResetValue (0x80000000UL) /*!< Reset value of DEVICEADDR register. */ + +/* STATICADDR @Bits 0..6 : Device Static Address. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDR_Pos (0UL) /*!< Position of STATICADDR field. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVICEADDR_STATICADDR_Pos) /*!< Bit mask of STATICADDR + field.*/ + +/* STATICADDRVALID @Bit 15 : Static Address Valid. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Pos (15UL) /*!< Position of STATICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Msk (0x1UL << I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Pos) /*!< Bit mask of + STATICADDRVALID field.*/ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Min (0x0UL) /*!< Min enumerator value of STATICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Max (0x1UL) /*!< Max enumerator value of STATICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_INVALID (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_VALID (0x1UL) /*!< (unspecified) */ + +/* DYNAMICADDR @Bits 16..22 : Device Dynamic Address. */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Pos (16UL) /*!< Position of DYNAMICADDR field. */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Pos) /*!< Bit mask of + DYNAMICADDR field.*/ + +/* DYNAMICADDRVALID @Bit 31 : Dynamic Address Valid */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Pos (31UL) /*!< Position of DYNAMICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Msk (0x1UL << I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Pos) /*!< Bit mask of + DYNAMICADDRVALID field.*/ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Min (0x0UL) /*!< Min enumerator value of DYNAMICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Max (0x1UL) /*!< Max enumerator value of DYNAMICADDRVALID field. */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_INVALID (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_VALID (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_CORE_HWCAPABILITY: Hardware Capability register */ + #define I3CCORE_CORE_HWCAPABILITY_ResetValue (0x000E187BUL) /*!< Reset value of HWCAPABILITY register. */ + +/* DEVICEROLECONFIG @Bits 0..2 : Reflects the IC_DEVICE_ROLE Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Pos (0UL) /*!< Position of DEVICEROLECONFIG field. */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Msk (0x7UL << I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Pos) /*!< Bit mask + of DEVICEROLECONFIG field.*/ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Min (0x1UL) /*!< Min enumerator value of DEVICEROLECONFIG field. */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Max (0x4UL) /*!< Max enumerator value of DEVICEROLECONFIG field. */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_MASTER (0x1UL) /*!< Master Only */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_PMASTERSLAVE (0x2UL) /*!< Programmable Master-Slave */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_SECONDARYMASTER (0x3UL) /*!< Secondary Master */ + #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_SLAVE (0x4UL) /*!< Slave Only */ + +/* HDRDDREN @Bit 3 : Reflects the IC_SPEED_HDR_DDR Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Pos (3UL) /*!< Position of HDRDDREN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Pos) /*!< Bit mask of HDRDDREN + field.*/ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Min (0x0UL) /*!< Min enumerator value of HDRDDREN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Max (0x1UL) /*!< Max enumerator value of HDRDDREN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_NOTSUPPORTED (0x0UL) /*!< HDR-DDR not supported */ + #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_SUPPORTED (0x1UL) /*!< HDR-DDR supported */ + +/* HDRTSEN @Bit 4 : Reflects the IC_SPEED_HDR_TS Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Pos (4UL) /*!< Position of HDRTSEN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Pos) /*!< Bit mask of HDRTSEN + field.*/ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Min (0x0UL) /*!< Min enumerator value of HDRTSEN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Max (0x1UL) /*!< Max enumerator value of HDRTSEN field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_NOTSUPPORTED (0x0UL) /*!< HDR-TS not supported */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_SUPPORTED (0x1UL) /*!< HDR-TS supported */ + +/* CLOCKPERIOD @Bits 5..10 : Reflects the IC_CLK_PERIOD Configurable Parameter */ + #define I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Pos (5UL) /*!< Position of CLOCKPERIOD field. */ + #define I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Msk (0x3FUL << I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Pos) /*!< Bit mask of + CLOCKPERIOD field.*/ + +/* HDRTXCLOCKPERIOD @Bits 11..16 : Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Pos (11UL) /*!< Position of HDRTXCLOCKPERIOD field. */ + #define I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Msk (0x3FUL << I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Pos) /*!< Bit + mask of HDRTXCLOCKPERIOD field.*/ + +/* DMAEN @Bit 17 : Reflects the IC_HAS_DMA Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_DMAEN_Pos (17UL) /*!< Position of DMAEN field. */ + #define I3CCORE_CORE_HWCAPABILITY_DMAEN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_DMAEN_Pos) /*!< Bit mask of DMAEN field. */ + +/* SLVHJCAP @Bit 18 : Reflects the IC_SLV_HJ Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Pos (18UL) /*!< Position of SLVHJCAP field. */ + #define I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Pos) /*!< Bit mask of SLVHJCAP + field.*/ + +/* SLVIBICAP @Bit 19 : Reflects the IC_SLV_IBI Configurable Parameter. */ + #define I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Pos (19UL) /*!< Position of SLVIBICAP field. */ + #define I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Pos) /*!< Bit mask of SLVIBICAP + field.*/ + + +/* I3CCORE_CORE_COMMANDQUEUEPORT: Command Queue Port. */ + #define I3CCORE_CORE_COMMANDQUEUEPORT_ResetValue (0x00000000UL) /*!< Reset value of COMMANDQUEUEPORT register. */ + +/* COMMAND @Bits 0..31 : 32 bit command */ + #define I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Pos (0UL) /*!< Position of COMMAND field. */ + #define I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Msk (0xFFFFFFFFUL << I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Pos) /*!< Bit mask of + COMMAND field.*/ + + +/* I3CCORE_CORE_RESPONSEQUEUEPORT: Response Queue Port */ + #define I3CCORE_CORE_RESPONSEQUEUEPORT_ResetValue (0x00000000UL) /*!< Reset value of RESPONSEQUEUEPORT register. */ + +/* RESPONSE @Bits 0..31 : 32 bit Response */ + #define I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ + #define I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Msk (0xFFFFFFFFUL << I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Pos) /*!< Bit + mask of RESPONSE field.*/ + + +/* I3CCORE_CORE_RXDATAPORT: Receive Data Port Register */ + #define I3CCORE_CORE_RXDATAPORT_ResetValue (0x00000000UL) /*!< Reset value of RXDATAPORT register. */ + +/* RXDATAPORT @Bits 0..31 : Receive Data Port. */ + #define I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Pos (0UL) /*!< Position of RXDATAPORT field. */ + #define I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Pos) /*!< Bit mask of + RXDATAPORT field.*/ + + +/* I3CCORE_CORE_TXDATAPORT: Transmit Data Port Register */ + #define I3CCORE_CORE_TXDATAPORT_ResetValue (0x00000000UL) /*!< Reset value of TXDATAPORT register. */ + +/* TXDATAPORT @Bits 0..31 : Transmit Data Port */ + #define I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Pos (0UL) /*!< Position of TXDATAPORT field. */ + #define I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Pos) /*!< Bit mask of + TXDATAPORT field.*/ + + +/* I3CCORE_CORE_IBIQUEUEDATA: In-Band Interrupt Queue Data Register */ + #define I3CCORE_CORE_IBIQUEUEDATA_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUEDATA register. */ + +/* IBIDATA @Bits 0..31 : In-Band Interrupt Data */ + #define I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Pos (0UL) /*!< Position of IBIDATA field. */ + #define I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Pos) /*!< Bit mask of IBIDATA + field.*/ + + +/* I3CCORE_CORE_IBIQUEUESTATUS: In-Band Interrupt Queue Status Register */ + #define I3CCORE_CORE_IBIQUEUESTATUS_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUESTATUS register. */ + +/* DATALENGTH @Bits 0..7 : In-Band Interrupt data length. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Pos (0UL) /*!< Position of DATALENGTH field. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Msk (0xFFUL << I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Pos) /*!< Bit mask of + DATALENGTH field.*/ + +/* IBIID @Bits 8..15 : IBI Identifier. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Pos (8UL) /*!< Position of IBIID field. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Msk (0xFFUL << I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Pos) /*!< Bit mask of IBIID field.*/ + +/* IBIACK @Bit 31 : The acknowledge bit of the IBI Received Status (IBISTS) bitfield. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Pos (31UL) /*!< Position of IBIACK field. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Msk (0x1UL << I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Pos) /*!< Bit mask of IBIACK + field.*/ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Min (0x0UL) /*!< Min enumerator value of IBIACK field. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Max (0x1UL) /*!< Max enumerator value of IBIACK field. */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_ACK (0x0UL) /*!< Responded with ACK */ + #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_NACK (0x1UL) /*!< Responded with NACK */ + + +/* I3CCORE_CORE_QUEUETHLDCTRL: Queue Threshold Control Register */ + #define I3CCORE_CORE_QUEUETHLDCTRL_ResetValue (0x01000101UL) /*!< Reset value of QUEUETHLDCTRL register. */ + +/* CMDEMPTYBUFTHLD @Bits 0..7 : Command Buffer Empty Threshold Value. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Pos (0UL) /*!< Position of CMDEMPTYBUFTHLD field. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Pos) /*!< Bit + mask of CMDEMPTYBUFTHLD field.*/ + +/* RESPBUFTHLD @Bits 8..15 : Response Buffer Threshold Value. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Pos (8UL) /*!< Position of RESPBUFTHLD field. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Pos) /*!< Bit mask of + RESPBUFTHLD field.*/ + +/* IBISTATUSTHLD @Bits 24..31 : In-Band Interrupt Status Threshold Value. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Pos (24UL) /*!< Position of IBISTATUSTHLD field. */ + #define I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Pos) /*!< Bit mask of + IBISTATUSTHLD field.*/ + + +/* I3CCORE_CORE_DATABUFFERTHLDCTRL: Data Buffer Threshold Control Register */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_ResetValue (0x01010101UL) /*!< Reset value of DATABUFFERTHLDCTRL register. */ + +/* TXEMPTYBUFTHLD @Bits 0..2 : Transmit Buffer Threshold Value */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Pos (0UL) /*!< Position of TXEMPTYBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Pos) /*!< + Bit mask of TXEMPTYBUFTHLD field.*/ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Min (0x0UL) /*!< Min enumerator value of TXEMPTYBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Max (0x5UL) /*!< Max enumerator value of TXEMPTYBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD14 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD18 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD116 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD132 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD164 (0x5UL) /*!< (unspecified) */ + +/* RXBUFTHLD @Bits 8..10 : Receive Buffer Threshold Value */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Pos (8UL) /*!< Position of RXBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Pos) /*!< Bit mask + of RXBUFTHLD field.*/ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Min (0x0UL) /*!< Min enumerator value of RXBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Max (0x5UL) /*!< Max enumerator value of RXBUFTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified) */ + +/* TXSTARTTHLD @Bits 16..18 : Transfer Start Threshold Value */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Pos (16UL) /*!< Position of TXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Pos) /*!< Bit + mask of TXSTARTTHLD field.*/ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Min (0x0UL) /*!< Min enumerator value of TXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Max (0x5UL) /*!< Max enumerator value of TXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified) */ + +/* RXSTARTTHLD @Bits 24..26 : Receive Start Threshold Value */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Pos (24UL) /*!< Position of RXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Pos) /*!< Bit + mask of RXSTARTTHLD field.*/ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Min (0x0UL) /*!< Min enumerator value of RXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Max (0x5UL) /*!< Max enumerator value of RXSTARTTHLD field. */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_CORE_IBIQUEUECTRL: This Register is used to control whether or not to intimate the application if an IBI request is + rejected (Nacked). */ + + #define I3CCORE_CORE_IBIQUEUECTRL_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUECTRL register. */ + +/* NOTIFYHJREJECTED @Bit 0 : Notify Rejected Hot-Join Control. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Pos (0UL) /*!< Position of NOTIFYHJREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Pos) /*!< Bit mask + of NOTIFYHJREJECTED field.*/ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYHJREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYHJREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_ENABLED (0x1UL) /*!< (unspecified) */ + +/* NOTIFYMRREJECTED @Bit 1 : Notify Rejected Master Request Control. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Pos (1UL) /*!< Position of NOTIFYMRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Pos) /*!< Bit mask + of NOTIFYMRREJECTED field.*/ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYMRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYMRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_DISABLED (0x0UL) /*!< Suppress passing the IBI Status to the IBI FIFO + (hence not notifying the application) when a MR + Request is NACKed and auto-disabled based on the + IBI_MR_REQ_REJECT Register.*/ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_ENABLED (0x1UL) /*!< Writes IBI Status to the IBI FIFO (hence notifying the + application) when a MR Request is NACKed and + auto-disabled based on the IBI_MR_REQ_REJECT + Register.*/ + +/* NOTIFYSIRREJECTED @Bit 3 : Notify Rejected Slave Interrupt Request Control. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Pos (3UL) /*!< Position of NOTIFYSIRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Pos) /*!< Bit + mask of NOTIFYSIRREJECTED field.*/ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYSIRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYSIRREJECTED field. */ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_DISABLED (0x0UL) /*!< Suppress passing the IBI Status to the IBI FIFO + (hence not notifying the application) when a Slave + Interrupt Request is NACKed and auto-disabled based + on the IBI_SIR_REQ_REJECT Register.*/ + #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_ENABLED (0x1UL) /*!< Writes IBI Status to the IBI FIFO (hence notifying + the application) when a Slave Interrupt Request is + NACKed and auto-disabled based on the + IBI_SIR_REQ_REJECT Register.*/ + + +/* I3CCORE_CORE_IBIMRREQREJECT: IBI Master Request Rejection Control Register. */ + #define I3CCORE_CORE_IBIMRREQREJECT_ResetValue (0x00000000UL) /*!< Reset value of IBIMRREQREJECT register. */ + +/* MRREQREJECT @Bits 0..31 : In-band Master Request Reject. */ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Pos (0UL) /*!< Position of MRREQREJECT field. */ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Pos) /*!< Bit + mask of MRREQREJECT field.*/ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Min (0x0UL) /*!< Min enumerator value of MRREQREJECT field. */ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Max (0x1UL) /*!< Max enumerator value of MRREQREJECT field. */ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_ACK (0x00000000UL) /*!< ACK Master Request. */ + #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_NACK (0x00000001UL) /*!< NACK and send Directed DISEC CCC to disable the + interrupting slave.*/ + + +/* I3CCORE_CORE_IBISIRREQREJECT: IBI SIR Request Rejection Control */ + #define I3CCORE_CORE_IBISIRREQREJECT_ResetValue (0x00000000UL) /*!< Reset value of IBISIRREQREJECT register. */ + +/* SIRREQREJECT @Bits 0..31 : In-band Slave Interrupt Request Reject */ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Pos (0UL) /*!< Position of SIRREQREJECT field. */ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Pos) /*!< Bit + mask of SIRREQREJECT field.*/ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Min (0x0UL) /*!< Min enumerator value of SIRREQREJECT field. */ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Max (0x1UL) /*!< Max enumerator value of SIRREQREJECT field. */ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_ACK (0x00000000UL) /*!< ACK the SIR Request. */ + #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_NACK (0x00000001UL) /*!< NACK and send directed auto disable CCC. */ + + +/* I3CCORE_CORE_RESETCTRL: This Register is used for general software reset and for individual buffer reset. */ + #define I3CCORE_CORE_RESETCTRL_ResetValue (0x00000000UL) /*!< Reset value of RESETCTRL register. */ + +/* SOFTRST @Bit 0 : Core Software Reset. */ + #define I3CCORE_CORE_RESETCTRL_SOFTRST_Pos (0UL) /*!< Position of SOFTRST field. */ + #define I3CCORE_CORE_RESETCTRL_SOFTRST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_SOFTRST_Pos) /*!< Bit mask of SOFTRST field. */ + +/* CMDQUEUERST @Bit 1 : Command Queue Software Reset */ + #define I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Pos (1UL) /*!< Position of CMDQUEUERST field. */ + #define I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Pos) /*!< Bit mask of CMDQUEUERST + field.*/ + +/* RESPQUEUERST @Bit 2 : Response Queue Software Reset */ + #define I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Pos (2UL) /*!< Position of RESPQUEUERST field. */ + #define I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Pos) /*!< Bit mask of + RESPQUEUERST field.*/ + +/* TXFIFORST @Bit 3 : Transmit Buffer Software Reset */ + #define I3CCORE_CORE_RESETCTRL_TXFIFORST_Pos (3UL) /*!< Position of TXFIFORST field. */ + #define I3CCORE_CORE_RESETCTRL_TXFIFORST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_TXFIFORST_Pos) /*!< Bit mask of TXFIFORST + field.*/ + +/* RXFIFORST @Bit 4 : Receive Buffer Software Reset. */ + #define I3CCORE_CORE_RESETCTRL_RXFIFORST_Pos (4UL) /*!< Position of RXFIFORST field. */ + #define I3CCORE_CORE_RESETCTRL_RXFIFORST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_RXFIFORST_Pos) /*!< Bit mask of RXFIFORST + field.*/ + +/* IBIQUEUERST @Bit 5 : IBI Queue Software Reset. */ + #define I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Pos (5UL) /*!< Position of IBIQUEUERST field. */ + #define I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Pos) /*!< Bit mask of IBIQUEUERST + field.*/ + +/* BUSRESETTYPE @Bits 29..30 : Bus Reset type */ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Pos (29UL) /*!< Position of BUSRESETTYPE field. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Msk (0x3UL << I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Pos) /*!< Bit mask of + BUSRESETTYPE field.*/ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Min (0x0UL) /*!< Min enumerator value of BUSRESETTYPE field. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Max (0x3UL) /*!< Max enumerator value of BUSRESETTYPE field. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_EXIT (0x0UL) /*!< Exit Pattern. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_SCL_LOW_RESET (0x3UL) /*!< SCL_LOW_RESET Pattern. */ + +/* BUSRESET @Bit 31 : Bus Reset. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESET_Pos (31UL) /*!< Position of BUSRESET field. */ + #define I3CCORE_CORE_RESETCTRL_BUSRESET_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_BUSRESET_Pos) /*!< Bit mask of BUSRESET field. */ + + +/* I3CCORE_CORE_SLVEVENTSTATUS: This register indicates the status/values of some events/controls that are relavant to slave + mode of operation. */ + + #define I3CCORE_CORE_SLVEVENTSTATUS_ResetValue (0x0000000BUL) /*!< Reset value of SLVEVENTSTATUS register. */ + +/* SIREN @Bit 0 : Slave Interrupt Request Enable. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Pos (0UL) /*!< Position of SIREN field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Pos) /*!< Bit mask of SIREN field. */ + +/* MREN @Bit 1 : Master Request Enable. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MREN_Pos (1UL) /*!< Position of MREN field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MREN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MREN_Pos) /*!< Bit mask of MREN field. */ + +/* HJEN @Bit 3 : Hot-Join Interrupt Enable */ + #define I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Pos (3UL) /*!< Position of HJEN field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Pos) /*!< Bit mask of HJEN field. */ + +/* ACTIVITYSTATE @Bits 4..5 : Activity State Status. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Pos (4UL) /*!< Position of ACTIVITYSTATE field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Msk (0x3UL << I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Pos) /*!< Bit mask + of ACTIVITYSTATE field.*/ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Min (0x0UL) /*!< Min enumerator value of ACTIVITYSTATE field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Max (0x3UL) /*!< Max enumerator value of ACTIVITYSTATE field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS3 (0x3UL) /*!< (unspecified) */ + +/* MRLUPDATED @Bit 6 : MRL Updated Status. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Pos (6UL) /*!< Position of MRLUPDATED field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Pos) /*!< Bit mask of + MRLUPDATED field.*/ + +/* MWLUPDATED @Bit 7 : MWL Updated Status. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Pos (7UL) /*!< Position of MWLUPDATED field. */ + #define I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Pos) /*!< Bit mask of + MWLUPDATED field.*/ + + +/* I3CCORE_CORE_INTRSTATUS: Interrupt Status Register */ + #define I3CCORE_CORE_INTRSTATUS_ResetValue (0x00000000UL) /*!< Reset value of INTRSTATUS register. */ + +/* TXTHLDSTS @Bit 0 : Transmit Buffer Threshold Status */ + #define I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Pos (0UL) /*!< Position of TXTHLDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Pos) /*!< Bit mask of TXTHLDSTS + field.*/ + +/* RXTHLDSTS @Bit 1 : Receive Buffer Threshold Status. */ + #define I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Pos (1UL) /*!< Position of RXTHLDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Pos) /*!< Bit mask of RXTHLDSTS + field.*/ + +/* IBITHLDSTS @Bit 2 : IBI Buffer Threshold Status. */ + #define I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Pos (2UL) /*!< Position of IBITHLDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Pos) /*!< Bit mask of IBITHLDSTS + field.*/ + +/* CMDQUEUEREADYSTS @Bit 3 : Command Queue Ready. */ + #define I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Pos (3UL) /*!< Position of CMDQUEUEREADYSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Pos) /*!< Bit mask of + CMDQUEUEREADYSTS field.*/ + +/* RESPREADYSTS @Bit 4 : Response Queue Ready Status. */ + #define I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Pos (4UL) /*!< Position of RESPREADYSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Pos) /*!< Bit mask of + RESPREADYSTS field.*/ + +/* TRANSFERABORTSTS @Bit 5 : Transfer Abort Status. */ + #define I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Pos (5UL) /*!< Position of TRANSFERABORTSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Pos) /*!< Bit mask of + TRANSFERABORTSTS field.*/ + +/* CCCUPDATEDSTS @Bit 6 : CCC Table Updated Status. */ + #define I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Pos (6UL) /*!< Position of CCCUPDATEDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Pos) /*!< Bit mask of + CCCUPDATEDSTS field.*/ + +/* DYNADDRASSGNSTS @Bit 8 : Dynamic Address Assigned Status. */ + #define I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Pos (8UL) /*!< Position of DYNADDRASSGNSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Pos) /*!< Bit mask of + DYNADDRASSGNSTS field.*/ + +/* TRANSFERERRSTS @Bit 9 : Transfer Error Status. */ + #define I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Pos (9UL) /*!< Position of TRANSFERERRSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Pos) /*!< Bit mask of + TRANSFERERRSTS field.*/ + +/* DEFSLVSTS @Bit 10 : Define Slave CCC Received Status. */ + #define I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Pos (10UL) /*!< Position of DEFSLVSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Pos) /*!< Bit mask of DEFSLVSTS + field.*/ + +/* READREQRECVSTS @Bit 11 : Read Request Received. */ + #define I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Pos (11UL) /*!< Position of READREQRECVSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Pos) /*!< Bit mask of + READREQRECVSTS field.*/ + +/* IBIUPDATEDSTS @Bit 12 : IBI status is updated. */ + #define I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Pos (12UL) /*!< Position of IBIUPDATEDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Pos) /*!< Bit mask of + IBIUPDATEDSTS field.*/ + +/* BUSOWNERUPDATEDSTS @Bit 13 : This interrupt is set when the role of the controller changes from being a Master to Slave or + vice versa. */ + + #define I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSTS field. */ + #define I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Pos) /*!< Bit mask + of BUSOWNERUPDATEDSTS field.*/ + +/* BUSRESETDONESTS @Bit 15 : Bus Reset Pattern Generation Done Status. */ + #define I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Pos (15UL) /*!< Position of BUSRESETDONESTS field. */ + #define I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Pos) /*!< Bit mask of + BUSRESETDONESTS field.*/ + + +/* I3CCORE_CORE_INTRSTATUSEN: Interrupt Status Enable Register. */ + #define I3CCORE_CORE_INTRSTATUSEN_ResetValue (0x00000000UL) /*!< Reset value of INTRSTATUSEN register. */ + +/* TXTHLDSTSEN @Bit 0 : Transmit Buffer Threshold Status Enable. */ + #define I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Pos (0UL) /*!< Position of TXTHLDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Pos) /*!< Bit mask of + TXTHLDSTSEN field.*/ + +/* RXTHLDSTSEN @Bit 1 : Receive Buffer Threshold Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Pos (1UL) /*!< Position of RXTHLDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Pos) /*!< Bit mask of + RXTHLDSTSEN field.*/ + +/* IBITHLDSTSEN @Bit 2 : IBI Buffer Threshold Status Enable. */ + #define I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Pos (2UL) /*!< Position of IBITHLDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Pos) /*!< Bit mask of + IBITHLDSTSEN field.*/ + +/* CMDQUEUEREADYSTSEN @Bit 3 : Command Queue Ready Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Pos (3UL) /*!< Position of CMDQUEUEREADYSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Pos) /*!< Bit + mask of CMDQUEUEREADYSTSEN field.*/ + +/* RESPREADYSTSEN @Bit 4 : Response Queue Ready Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Pos (4UL) /*!< Position of RESPREADYSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Pos) /*!< Bit mask of + RESPREADYSTSEN field.*/ + +/* TRANSFERABORTSTSEN @Bit 5 : Transfer Abort Status Enable. */ + #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Pos (5UL) /*!< Position of TRANSFERABORTSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Pos) /*!< Bit + mask of TRANSFERABORTSTSEN field.*/ + +/* CCCUPDATEDSTSEN @Bit 6 : CCC Table Updated Status Enable. */ + #define I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Pos (6UL) /*!< Position of CCCUPDATEDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Pos) /*!< Bit mask + of CCCUPDATEDSTSEN field.*/ + +/* DYNADDRASSGNSTSEN @Bit 8 : Dynamic Address Assigned Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Pos (8UL) /*!< Position of DYNADDRASSGNSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Pos) /*!< Bit + mask of DYNADDRASSGNSTSEN field.*/ + +/* TRANSFERERRSTSEN @Bit 9 : Transfer Error Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Pos (9UL) /*!< Position of TRANSFERERRSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Pos) /*!< Bit mask + of TRANSFERERRSTSEN field.*/ + +/* DEFSLVSTSEN @Bit 10 : Define Slave CCC Received Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Pos (10UL) /*!< Position of DEFSLVSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Pos) /*!< Bit mask of + DEFSLVSTSEN field.*/ + +/* READREQRECVSTSEN @Bit 11 : Read Request Received Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Pos (11UL) /*!< Position of READREQRECVSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Pos) /*!< Bit mask + of READREQRECVSTSEN field.*/ + +/* IBIUPDATEDSTSEN @Bit 12 : IBI Updated Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Pos (12UL) /*!< Position of IBIUPDATEDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Pos) /*!< Bit mask + of IBIUPDATEDSTSEN field.*/ + +/* BUSOWNERUPDATEDSTSEN @Bit 13 : Bus owner Updated Status Enable */ + #define I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Pos) /*!< + Bit mask of BUSOWNERUPDATEDSTSEN field.*/ + +/* BUSRESETDONESTSEN @Bit 15 : Bus Reset Pattern Generation Done Status Enable. */ + #define I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Pos (15UL) /*!< Position of BUSRESETDONESTSEN field. */ + #define I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Pos) /*!< Bit + mask of BUSRESETDONESTSEN field.*/ + + +/* I3CCORE_CORE_INTRSIGNALEN: Interrupt Signal Enable Register */ + #define I3CCORE_CORE_INTRSIGNALEN_ResetValue (0x00000000UL) /*!< Reset value of INTRSIGNALEN register. */ + +/* TXTHLDSIGNALEN @Bit 0 : Transmit Buffer Threshold Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Pos (0UL) /*!< Position of TXTHLDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Pos) /*!< Bit mask of + TXTHLDSIGNALEN field.*/ + +/* RXTHLDSIGNALEN @Bit 1 : Receive Buffer Threshold Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Pos (1UL) /*!< Position of RXTHLDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Pos) /*!< Bit mask of + RXTHLDSIGNALEN field.*/ + +/* IBITHLDSIGNALEN @Bit 2 : IBI Buffer Threshold Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Pos (2UL) /*!< Position of IBITHLDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Pos) /*!< Bit mask + of IBITHLDSIGNALEN field.*/ + +/* CMDQUEUEREADYSIGNALEN @Bit 3 : Command Queue Ready Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Pos (3UL) /*!< Position of CMDQUEUEREADYSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Pos) + /*!< Bit mask of CMDQUEUEREADYSIGNALEN field.*/ + +/* RESPREADYSIGNALEN @Bit 4 : Response Queue Ready Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Pos (4UL) /*!< Position of RESPREADYSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Pos) /*!< Bit + mask of RESPREADYSIGNALEN field.*/ + +/* TRANSFERABORTSIGNALEN @Bit 5 : Transfer Abort Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Pos (5UL) /*!< Position of TRANSFERABORTSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Pos) + /*!< Bit mask of TRANSFERABORTSIGNALEN field.*/ + +/* CCCUPDATEDSIGNALEN @Bit 6 : CCC Table Updated Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Pos (6UL) /*!< Position of CCCUPDATEDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Pos) /*!< Bit + mask of CCCUPDATEDSIGNALEN field.*/ + +/* DYNADDRASSGNSIGNALEN @Bit 8 : Dynamic Address Assigned Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Pos (8UL) /*!< Position of DYNADDRASSGNSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Pos) /*!< + Bit mask of DYNADDRASSGNSIGNALEN field.*/ + +/* TRANSFERERRSIGNALEN @Bit 9 : Transfer Error Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Pos (9UL) /*!< Position of TRANSFERERRSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Pos) /*!< + Bit mask of TRANSFERERRSIGNALEN field.*/ + +/* DEFSLVSIGNALEN @Bit 10 : Define Slave CCC Received Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Pos (10UL) /*!< Position of DEFSLVSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Pos) /*!< Bit mask of + DEFSLVSIGNALEN field.*/ + +/* READREQRECVSIGNALEN @Bit 11 : Read Request Received Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Pos (11UL) /*!< Position of READREQRECVSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Pos) /*!< + Bit mask of READREQRECVSIGNALEN field.*/ + +/* IBIUPDATEDSIGNALEN @Bit 12 : IBI Updated Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Pos (12UL) /*!< Position of IBIUPDATEDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Pos) /*!< Bit + mask of IBIUPDATEDSIGNALEN field.*/ + +/* BUSOWNERUPDATEDSIGNALEN @Bit 13 : Bus owner Updated Signal Enable */ + #define I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Pos) + /*!< Bit mask of BUSOWNERUPDATEDSIGNALEN field.*/ + +/* BUSRESETDONESIGNALEN @Bit 15 : Bus Reset Pattern Generation Done Signal Enable. */ + #define I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Pos (15UL) /*!< Position of BUSRESETDONESIGNALEN field. */ + #define I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Pos) /*!< + Bit mask of BUSRESETDONESIGNALEN field.*/ + + +/* I3CCORE_CORE_INTRFORCE: Interrupt Force Enable Register */ + #define I3CCORE_CORE_INTRFORCE_ResetValue (0x00000000UL) /*!< Reset value of INTRFORCE register. */ + +/* TXTHLDFORCEEN @Bit 0 : Transmit Buffer Threshold Force Enable */ + #define I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Pos (0UL) /*!< Position of TXTHLDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Pos) /*!< Bit mask of + TXTHLDFORCEEN field.*/ + +/* RXTHLDFORCEEN @Bit 1 : Receive Buffer Threshold Force Enable */ + #define I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Pos (1UL) /*!< Position of RXTHLDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Pos) /*!< Bit mask of + RXTHLDFORCEEN field.*/ + +/* IBITHLDFORCEEN @Bit 2 : IBI Buffer Threshold Force Enable */ + #define I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Pos (2UL) /*!< Position of IBITHLDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Pos) /*!< Bit mask of + IBITHLDFORCEEN field.*/ + +/* CMDQUEUEREADYFORCEEN @Bit 3 : Command Queue Ready Force Enable */ + #define I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Pos (3UL) /*!< Position of CMDQUEUEREADYFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Pos) /*!< Bit + mask of CMDQUEUEREADYFORCEEN field.*/ + +/* RESPREADYFORCEEN @Bit 4 : Response Queue Ready Force Enable */ + #define I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Pos (4UL) /*!< Position of RESPREADYFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Pos) /*!< Bit mask of + RESPREADYFORCEEN field.*/ + +/* TRANSFERABORTFORCEEN @Bit 5 : Transfer Abort Force Enable */ + #define I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Pos (5UL) /*!< Position of TRANSFERABORTFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Pos) /*!< Bit + mask of TRANSFERABORTFORCEEN field.*/ + +/* CCCUPDATEDFORCEEN @Bit 6 : CCC Table Updated Force Enable */ + #define I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Pos (6UL) /*!< Position of CCCUPDATEDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Pos) /*!< Bit mask of + CCCUPDATEDFORCEEN field.*/ + +/* DYNADDRASSGNFORCEEN @Bit 8 : Dynamic Address Assigned Force Enable */ + #define I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Pos (8UL) /*!< Position of DYNADDRASSGNFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Pos) /*!< Bit mask + of DYNADDRASSGNFORCEEN field.*/ + +/* TRANSFERERRFORCEEN @Bit 9 : Transfer Error Force Enable */ + #define I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Pos (9UL) /*!< Position of TRANSFERERRFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Pos) /*!< Bit mask + of TRANSFERERRFORCEEN field.*/ + +/* DEFSLVFORCEEN @Bit 10 : Define Slave CCC Received Force Enable */ + #define I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Pos (10UL) /*!< Position of DEFSLVFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Pos) /*!< Bit mask of + DEFSLVFORCEEN field.*/ + +/* READREQFORCEEN @Bit 11 : Read Request Received Force Enable */ + #define I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Pos (11UL) /*!< Position of READREQFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Pos) /*!< Bit mask of + READREQFORCEEN field.*/ + +/* IBIUPDATEDFORCEEN @Bit 12 : IBI Updated Force Enable */ + #define I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Pos (12UL) /*!< Position of IBIUPDATEDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Pos) /*!< Bit mask of + IBIUPDATEDFORCEEN field.*/ + +/* BUSOWNERUPDATEDFORCEEN @Bit 13 : Bus owner Updated Force Enable */ + #define I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Pos) /*!< + Bit mask of BUSOWNERUPDATEDFORCEEN field.*/ + +/* BUSRESETDONEFORCEEN @Bit 15 : Bus Reset Pattern Generation Done Force Enable. */ + #define I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Pos (15UL) /*!< Position of BUSRESETDONEFORCEEN field. */ + #define I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Pos) /*!< Bit mask + of BUSRESETDONEFORCEEN field.*/ + + +/* I3CCORE_CORE_QUEUESTATUSLEVEL: Queue Status Level Register. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_ResetValue (0x00000010UL) /*!< Reset value of QUEUESTATUSLEVEL register. */ + +/* CMDQUEUEEMPTYLOC @Bits 0..7 : Command Queue Empty Locations. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Pos (0UL) /*!< Position of CMDQUEUEEMPTYLOC field. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Pos) /*!< + Bit mask of CMDQUEUEEMPTYLOC field.*/ + +/* RESPBUFBLR @Bits 8..15 : Response Buffer Level Value. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Pos (8UL) /*!< Position of RESPBUFBLR field. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Pos) /*!< Bit mask of + RESPBUFBLR field.*/ + +/* IBIBUFBLR @Bits 16..23 : IBI Buffer Level Value. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Pos (16UL) /*!< Position of IBIBUFBLR field. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Pos) /*!< Bit mask of + IBIBUFBLR field.*/ + +/* IBISTSCNT @Bits 24..28 : IBI Buffer Status Count. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Pos (24UL) /*!< Position of IBISTSCNT field. */ + #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Msk (0x1FUL << I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Pos) /*!< Bit mask of + IBISTSCNT field.*/ + + +/* I3CCORE_CORE_DATABUFFERSTATUSLEVEL: Data Buffer Status Level Register. */ + #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_ResetValue (0x00000040UL) /*!< Reset value of DATABUFFERSTATUSLEVEL register. */ + +/* TXBUFEMPTYLOC @Bits 0..7 : Transmit Buffer Empty Level Value. */ + #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Pos (0UL) /*!< Position of TXBUFEMPTYLOC field. */ + #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Msk (0xFFUL << I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Pos) + /*!< Bit mask of TXBUFEMPTYLOC field.*/ + +/* RXBUFBLR @Bits 16..23 : Receive Buffer Level Value. */ + #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Pos (16UL) /*!< Position of RXBUFBLR field. */ + #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Msk (0xFFUL << I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Pos) /*!< Bit + mask of RXBUFBLR field.*/ + + +/* I3CCORE_CORE_PRESENTSTATEM: The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register + (Master). */ + + #define I3CCORE_CORE_PRESENTSTATEM_ResetValue (0x10000003UL) /*!< Reset value of PRESENTSTATEM register. */ + +/* SCLLINESIGNALLEVEL @Bit 0 : This bit is used to check the SCL line level to recover from errors and for debugging. */ + #define I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Pos (0UL) /*!< Position of SCLLINESIGNALLEVEL field. */ + #define I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Pos) /*!< + Bit mask of SCLLINESIGNALLEVEL field.*/ + +/* SDALINESIGNALLEVEL @Bit 1 : This bit is used to check the SDA line level to recover from errors and for debugging. */ + #define I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Pos (1UL) /*!< Position of SDALINESIGNALLEVEL field. */ + #define I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Pos) /*!< + Bit mask of SDALINESIGNALLEVEL field.*/ + +/* CURRENTMASTER @Bit 2 : This Bit is used to check whether the Master is Current Master or not. */ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Pos (2UL) /*!< Position of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Pos) /*!< Bit mask of + CURRENTMASTER field.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Min (0x0UL) /*!< Min enumerator value of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Max (0x1UL) /*!< Max enumerator value of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_NOT_BUS_OWNER (0x0UL) /*!< Master is not Current Master */ + #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_BUS_OWNER (0x1UL) /*!< Master is Current Master */ + +/* CMTFRSTS @Bits 8..13 : Transfer Type Status */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Pos (8UL) /*!< Position of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Pos) /*!< Bit mask of CMTFRSTS + field.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Max (0xFUL) /*!< Max enumerator value of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_IDLE (0x00UL) /*!< Controller is in Idle state, waiting for commands from + application or Slave initated In-band Interrupt.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_BCCCWTRANSFER (0x01UL) /*!< Broadcast CCC Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DCCCWTRANSFER (0x02UL) /*!< Directed CCC Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DCCCRTRANSFER (0x03UL) /*!< Directed CCC Read Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_ENTDAATRANSFER (0x04UL) /*!< ENTDAA Address Assignment Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SETDASATRANSFER (0x05UL) /*!< SETDASA Address Assignment Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRWTRANSFER (0x06UL) /*!< Private I3C SDR Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRRTRANSFER (0x07UL) /*!< Private I3C SDR Read Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRWTRANSFERI2C (0x08UL) /*!< Private I2C SDR Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRRTRANSFERI2C (0x09UL) /*!< Private I2C SDR Read Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_TSWTRANSFER (0x0AUL) /*!< Private HDR Ternary Symbol(TS) Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_TSRTRANSFER (0x0BUL) /*!< Private HDR Ternary Symbol(TS) Read Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DDRWTRANSFER (0x0CUL) /*!< Private HDR Double-Data Rate(DDR) Write Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DDRRTRANSFER (0x0DUL) /*!< Private HDR Double-Data Rate(DDR) Read Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_IBITRANSFER (0x0EUL) /*!< Servicing In-Band Interrupt Transfer. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_HALT (0x0FUL) /*!< Halt state. Controller is in Halt State, waiting for the + application to resume through DEVICE_CTRL Register.*/ + +/* CMTFRSTSTS @Bits 16..21 : Current Master Transfer State Status. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Pos (16UL) /*!< Position of CMTFRSTSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Pos) /*!< Bit mask of + CMTFRSTSTS field.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Max (0x13UL) /*!< Max enumerator value of CMTFRSTSTS field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_IDLE (0x00UL) /*!< Controller is Idle state, waiting for commands from + application or Slave initated In-band Interrupt.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_START (0x01UL) /*!< START Generation State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RESTART (0x02UL) /*!< RESTART Generation State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_STOP (0x03UL) /*!< STOP Genration State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_STARTH (0x04UL) /*!< START Hold Generation for the Slave Initiated START State.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_BWADDRGEN (0x05UL) /*!< Broadcast Write Address Header(7h7E,W) Generation + State.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_BRADDRGEN (0x06UL) /*!< Broadcast Read Address Header(7h7E,R) Generation State.*/ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_DAA (0x07UL) /*!< Dynamic Address Assignment State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_ADDRGEN (0x08UL) /*!< Slave Address Generation State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_CCCBYTEGEN (0x0BUL) /*!< CCC Byte Generation State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_HDRCMDGEN (0x0CUL) /*!< HDR Command Generation State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_WTRANSFER (0x0DUL) /*!< Write Data Transfer State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RTRANSFER (0x0EUL) /*!< Read Data Transfer State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RIBI (0x0FUL) /*!< In-Band Interrupt(SIR) Read Data State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_IBIAUTODISABLE (0x10UL) /*!< In-Band Interrupt Auto-Disable State */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_DDRCRCGEN (0x11UL) /*!< HDR-DDR CRC Data Generation/Receive State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_CLKEXTEND (0x12UL) /*!< Clock Extension State. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_HALT (0x13UL) /*!< Halt State. */ + +/* CMDTID @Bits 24..27 : This field reflects the Transaction-ID of the current executing command. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMDTID_Pos (24UL) /*!< Position of CMDTID field. */ + #define I3CCORE_CORE_PRESENTSTATEM_CMDTID_Msk (0xFUL << I3CCORE_CORE_PRESENTSTATEM_CMDTID_Pos) /*!< Bit mask of CMDTID field.*/ + +/* MASTERIDLE @Bit 28 : This field reflects whether the Master Controller is in Idle state or not. */ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Pos (28UL) /*!< Position of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Pos) /*!< Bit mask of + MASTERIDLE field.*/ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Min (0x0UL) /*!< Min enumerator value of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Max (0x1UL) /*!< Max enumerator value of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_MST_NOT_IDLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_MST_IDLE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_CORE_PRESENTSTATES: The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register + (Slave). */ + + #define I3CCORE_CORE_PRESENTSTATES_ResetValue (0x10000003UL) /*!< Reset value of PRESENTSTATES register. */ + +/* SCLLINESIGNALLEVEL @Bit 0 : This bit is used to check the SCL line level to recover from errors and for debugging. */ + #define I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Pos (0UL) /*!< Position of SCLLINESIGNALLEVEL field. */ + #define I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Pos) /*!< + Bit mask of SCLLINESIGNALLEVEL field.*/ + +/* SDALINESIGNALLEVEL @Bit 1 : This bit is used to check the SDA line level to recover from errors and for debugging. */ + #define I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Pos (1UL) /*!< Position of SDALINESIGNALLEVEL field. */ + #define I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Pos) /*!< + Bit mask of SDALINESIGNALLEVEL field.*/ + +/* CURRENTMASTER @Bit 2 : This Bit is used to check whether the Master is Current Master or not. */ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Pos (2UL) /*!< Position of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Pos) /*!< Bit mask of + CURRENTMASTER field.*/ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Min (0x0UL) /*!< Min enumerator value of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Max (0x1UL) /*!< Max enumerator value of CURRENTMASTER field. */ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_NOT_BUS_OWNER (0x0UL) /*!< Master is not Current Master */ + #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_BUS_OWNER (0x1UL) /*!< Master is Current Master */ + +/* CMTFRSTS @Bits 8..13 : Transfer Type Status */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Pos (8UL) /*!< Position of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Pos) /*!< Bit mask of CMTFRSTS + field.*/ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Max (0x6UL) /*!< Max enumerator value of CMTFRSTS field. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEIDLE (0x00UL) /*!< Controller is in Idle state. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEHOTJOIN (0x01UL) /*!< Hot-Join transfer state. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEIBITRANSFER (0x02UL) /*!< IBI transfer state. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEWTRANSFER (0x03UL) /*!< Master write transfer ongoing. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVERPREFETCH (0x04UL) /*!< Read data prefetch state. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVERTRANSFER (0x05UL) /*!< Master read transfer ongoing. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEHALT (0x06UL) /*!< Slave controller in Halt State waiting for resume from + application.*/ + +/* CMTFRSTSTS @Bits 16..21 : Current Master Transfer State Status. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Pos (16UL) /*!< Position of CMTFRSTSTS field. */ + #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Pos) /*!< Bit mask of + CMTFRSTSTS field.*/ + +/* CMDTID @Bits 24..27 : This field reflects the Transaction-ID of the current executing command. */ + #define I3CCORE_CORE_PRESENTSTATES_CMDTID_Pos (24UL) /*!< Position of CMDTID field. */ + #define I3CCORE_CORE_PRESENTSTATES_CMDTID_Msk (0xFUL << I3CCORE_CORE_PRESENTSTATES_CMDTID_Pos) /*!< Bit mask of CMDTID field.*/ + +/* MASTERIDLE @Bit 28 : This field reflects whether the Master Controller is in Idle state or not. */ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Pos (28UL) /*!< Position of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Pos) /*!< Bit mask of + MASTERIDLE field.*/ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Min (0x0UL) /*!< Min enumerator value of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Max (0x1UL) /*!< Max enumerator value of MASTERIDLE field. */ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_MST_NOT_IDLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_MST_IDLE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_CORE_CCCDEVICESTATUS: Device Operating Status Register. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_ResetValue (0x00000000UL) /*!< Reset value of CCCDEVICESTATUS register. */ + +/* PENDINGINTR @Bits 0..3 : Pending Interrupt */ + #define I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Pos (0UL) /*!< Position of PENDINGINTR field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Msk (0xFUL << I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Pos) /*!< Bit mask of + PENDINGINTR field.*/ + +/* PROTOCOLERR @Bit 5 : Protocol Error */ + #define I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Pos (5UL) /*!< Position of PROTOCOLERR field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Pos) /*!< Bit mask of + PROTOCOLERR field.*/ + +/* ACTIVITYMODE @Bits 6..7 : Activity Mode */ + #define I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Pos (6UL) /*!< Position of ACTIVITYMODE field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Msk (0x3UL << I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Pos) /*!< Bit mask + of ACTIVITYMODE field.*/ + +/* UNDERFLOWERR @Bit 8 : Underflow error */ + #define I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Pos (8UL) /*!< Position of UNDERFLOWERR field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Pos) /*!< Bit mask + of UNDERFLOWERR field.*/ + +/* SLAVEBUSY @Bit 9 : Slave Busy */ + #define I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Pos (9UL) /*!< Position of SLAVEBUSY field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Pos) /*!< Bit mask of + SLAVEBUSY field.*/ + +/* OVERFLOWERR @Bit 10 : Overflow Error */ + #define I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Pos (10UL) /*!< Position of OVERFLOWERR field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Pos) /*!< Bit mask of + OVERFLOWERR field.*/ + +/* DATANOTREADY @Bit 11 : Data not ready */ + #define I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Pos (11UL) /*!< Position of DATANOTREADY field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Pos) /*!< Bit mask + of DATANOTREADY field.*/ + +/* BUFFERNOTAVAIL @Bit 12 : Buffer not available */ + #define I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Pos (12UL) /*!< Position of BUFFERNOTAVAIL field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Pos) /*!< Bit + mask of BUFFERNOTAVAIL field.*/ + +/* FRAMEERROR @Bit 13 : Frame Error */ + #define I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Pos (13UL) /*!< Position of FRAMEERROR field. */ + #define I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Pos) /*!< Bit mask of + FRAMEERROR field.*/ + + +/* I3CCORE_CORE_DEVICEADDRTABLEPOINTER: Pointer for Device Address Table */ + #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_ResetValue (0x000A02C0UL) /*!< Reset value of DEVICEADDRTABLEPOINTER register. */ + +/* PDEVADDRTABLESTARTADDR @Bits 0..15 : Start Address of Device Address Table. */ + #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Pos (0UL) /*!< Position of PDEVADDRTABLESTARTADDR field. */ + #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Msk (0xFFFFUL << I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Pos) + /*!< Bit mask of PDEVADDRTABLESTARTADDR field.*/ + +/* DEVADDRTABLEDEPTH @Bits 16..31 : Depth of Device Address Table */ + #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Pos (16UL) /*!< Position of DEVADDRTABLEDEPTH field. */ + #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Msk (0xFFFFUL << I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Pos) + /*!< Bit mask of DEVADDRTABLEDEPTH field.*/ + + +/* I3CCORE_CORE_DEVCHARTABLEPOINTER: Pointer for Device Characteristics Table */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_ResetValue (0x00028200UL) /*!< Reset value of DEVCHARTABLEPOINTER register. */ + +/* PDEVCHARTABLESTARTADDR @Bits 0..11 : Start Address of Device Characteristics Table. */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Pos (0UL) /*!< Position of PDEVCHARTABLESTARTADDR field. */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Msk (0xFFFUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Pos) + /*!< Bit mask of PDEVCHARTABLESTARTADDR field.*/ + +/* DEVCHARTABLEDEPTH @Bits 12..18 : Depth of Device Characteristics Table */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Pos (12UL) /*!< Position of DEVCHARTABLEDEPTH field. */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Msk (0x7FUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Pos) + /*!< Bit mask of DEVCHARTABLEDEPTH field.*/ + +/* PRESENTDEVCHARTABLEINDX @Bits 19..22 : Current index of Device Characteristics Table. */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Pos (19UL) /*!< Position of PRESENTDEVCHARTABLEINDX field. */ + #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Msk (0xFUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Pos) + /*!< Bit mask of PRESENTDEVCHARTABLEINDX field.*/ + + +/* I3CCORE_CORE_VENDORSPECIFICREGPOINTER: Pointer for Vendor Specific Registers. */ + #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_ResetValue (0x000000B0UL) /*!< Reset value of VENDORSPECIFICREGPOINTER + register.*/ + +/* PVENDORREGSTARTADDR @Bits 0..15 : Start Address of Vendor specific registers. */ + #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Pos (0UL) /*!< Position of PVENDORREGSTARTADDR field. */ + #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Msk (0xFFFFUL << I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Pos) + /*!< Bit mask of PVENDORREGSTARTADDR field.*/ + + +/* I3CCORE_CORE_SLVMIPIIDVALUE: I3C MIPI Manufacturer ID Register. */ + #define I3CCORE_CORE_SLVMIPIIDVALUE_ResetValue (0x00000000UL) /*!< Reset value of SLVMIPIIDVALUE register. */ + +/* SLVPROVIDSEL @Bit 0 : Specifies the Provisional ID Type Selector (PID[32]). */ + #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Pos (0UL) /*!< Position of SLVPROVIDSEL field. */ + #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Msk (0x1UL << I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Pos) /*!< Bit mask of + SLVPROVIDSEL field.*/ + +/* SLVMIPIMFGID @Bits 1..15 : Specifies the MIPI Manufacturer ID. */ + #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Pos (1UL) /*!< Position of SLVMIPIMFGID field. */ + #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Msk (0x7FFFUL << I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Pos) /*!< Bit mask + of SLVMIPIMFGID field.*/ + + +/* I3CCORE_CORE_SLVPIDVALUE: I3C Normal Provisional ID Register. */ + #define I3CCORE_CORE_SLVPIDVALUE_ResetValue (0x00000000UL) /*!< Reset value of SLVPIDVALUE register. */ + +/* SLVPIDDCR @Bits 0..11 : Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Pos (0UL) /*!< Position of SLVPIDDCR field. */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Msk (0xFFFUL << I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Pos) /*!< Bit mask of SLVPIDDCR + field.*/ + +/* SLVINSTID @Bits 12..15 : This field is used to program the instance ID of the Slave. */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Pos (12UL) /*!< Position of SLVINSTID field. */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Msk (0xFUL << I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Pos) /*!< Bit mask of SLVINSTID + field.*/ + +/* SLVPARTID @Bits 16..31 : Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Pos (16UL) /*!< Position of SLVPARTID field. */ + #define I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Msk (0xFFFFUL << I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Pos) /*!< Bit mask of SLVPARTID + field.*/ + + +/* I3CCORE_CORE_SLVCHARCTRL: I3C Slave Characteristic Register. */ + #define I3CCORE_CORE_SLVCHARCTRL_ResetValue (0x00070062UL) /*!< Reset value of SLVCHARCTRL register. */ + +/* MAXDATASPEEDLIMIT @Bit 0 : Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). */ + #define I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Pos (0UL) /*!< Position of MAXDATASPEEDLIMIT field. */ + #define I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Pos) /*!< Bit mask + of MAXDATASPEEDLIMIT field.*/ + +/* IBIREQUESTCAPABLE @Bit 1 : IBI Request Capable field in Bus Characteristic Register (BCR[1]). */ + #define I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Pos (1UL) /*!< Position of IBIREQUESTCAPABLE field. */ + #define I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Pos) /*!< Bit mask + of IBIREQUESTCAPABLE field.*/ + +/* IBIPAYLOAD @Bit 2 : IBI Payload field in Bus Characteristic Register (BCR[2]). */ + #define I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Pos (2UL) /*!< Position of IBIPAYLOAD field. */ + #define I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Pos) /*!< Bit mask of IBIPAYLOAD + field.*/ + +/* OFFLINECAPABLE @Bit 3 : Offline Capable field in Bus Characteristic Register (BCR[3]). */ + #define I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Pos (3UL) /*!< Position of OFFLINECAPABLE field. */ + #define I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Pos) /*!< Bit mask of + OFFLINECAPABLE field.*/ + +/* BRIDGEIDENTIFIER @Bit 4 : Bridge Identifier field in Bus Characteristic Register (BCR[4]). */ + #define I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Pos (4UL) /*!< Position of BRIDGEIDENTIFIER field. */ + #define I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Pos) /*!< Bit mask + of BRIDGEIDENTIFIER field.*/ + +/* HDRCAPABLE @Bit 5 : SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). */ + #define I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Pos (5UL) /*!< Position of HDRCAPABLE field. */ + #define I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Pos) /*!< Bit mask of HDRCAPABLE + field.*/ + +/* DEVICEROLE @Bits 6..7 : Device Role field in Bus Characteristic Register (BCR[7:6]). */ + #define I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Pos (6UL) /*!< Position of DEVICEROLE field. */ + #define I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Msk (0x3UL << I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Pos) /*!< Bit mask of DEVICEROLE + field.*/ + +/* DCR @Bits 8..15 : I3C Device Characteristic Value. */ + #define I3CCORE_CORE_SLVCHARCTRL_DCR_Pos (8UL) /*!< Position of DCR field. */ + #define I3CCORE_CORE_SLVCHARCTRL_DCR_Msk (0xFFUL << I3CCORE_CORE_SLVCHARCTRL_DCR_Pos) /*!< Bit mask of DCR field. */ + +/* HDRCAP @Bits 16..23 : I3C Device HDR Capability Register Value. */ + #define I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Pos (16UL) /*!< Position of HDRCAP field. */ + #define I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Msk (0xFFUL << I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Pos) /*!< Bit mask of HDRCAP field. */ + + +/* I3CCORE_CORE_SLVMAXLEN: I3C Max Write/Read Length Register. */ + #define I3CCORE_CORE_SLVMAXLEN_ResetValue (0x00FF00FFUL) /*!< Reset value of SLVMAXLEN register. */ + +/* MWL @Bits 0..15 : I3C Device Max Write Length */ + #define I3CCORE_CORE_SLVMAXLEN_MWL_Pos (0UL) /*!< Position of MWL field. */ + #define I3CCORE_CORE_SLVMAXLEN_MWL_Msk (0xFFFFUL << I3CCORE_CORE_SLVMAXLEN_MWL_Pos) /*!< Bit mask of MWL field. */ + +/* MRL @Bits 16..31 : I3C Device Max Read Length. */ + #define I3CCORE_CORE_SLVMAXLEN_MRL_Pos (16UL) /*!< Position of MRL field. */ + #define I3CCORE_CORE_SLVMAXLEN_MRL_Msk (0xFFFFUL << I3CCORE_CORE_SLVMAXLEN_MRL_Pos) /*!< Bit mask of MRL field. */ + + +/* I3CCORE_CORE_MAXREADTURNAROUND: MXDS Maximum Read Turnaround Time. */ + #define I3CCORE_CORE_MAXREADTURNAROUND_ResetValue (0x00000000UL) /*!< Reset value of MAXREADTURNAROUND register. */ + +/* MXDSMAXRDTURN @Bits 0..23 : Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. */ + #define I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Pos (0UL) /*!< Position of MXDSMAXRDTURN field. */ + #define I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Msk (0xFFFFFFUL << I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Pos) /*!< + Bit mask of MXDSMAXRDTURN field.*/ + + +/* I3CCORE_CORE_MAXDATASPEED: The values in this register are returned by the slave as GETACCMST CCC data. */ + #define I3CCORE_CORE_MAXDATASPEED_ResetValue (0x00000000UL) /*!< Reset value of MAXDATASPEED register. */ + +/* MXDSMAXWRSPEED @Bits 0..2 : Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to + DWC_mipi_i3c Slave device */ + + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Pos (0UL) /*!< Position of MXDSMAXWRSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Pos) /*!< Bit mask of + MXDSMAXWRSPEED field.*/ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Min (0x0UL) /*!< Min enumerator value of MXDSMAXWRSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Max (0x4UL) /*!< Max enumerator value of MXDSMAXWRSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_12M5HZ (0x0UL) /*!< 12.5MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_8MHZ (0x1UL) /*!< 8MHZ */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_6MHZ (0x2UL) /*!< 6MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_4MHZ (0x3UL) /*!< 4MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_2MHZ (0x4UL) /*!< 2MHz */ + +/* MXDSMAXRDSPEED @Bits 8..10 : Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device + to Master Device */ + + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Pos (8UL) /*!< Position of MXDSMAXRDSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Pos) /*!< Bit mask of + MXDSMAXRDSPEED field.*/ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Min (0x0UL) /*!< Min enumerator value of MXDSMAXRDSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Max (0x4UL) /*!< Max enumerator value of MXDSMAXRDSPEED field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_12M5HZ (0x0UL) /*!< 12.5MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_8MHZ (0x1UL) /*!< 8MHZ */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_6MHZ (0x2UL) /*!< 6MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_4MHZ (0x3UL) /*!< 4MHz */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_2MHZ (0x4UL) /*!< 2MHz */ + +/* MXDSCLKDATATURN @Bits 16..18 : Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Pos (16UL) /*!< Position of MXDSCLKDATATURN field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Pos) /*!< Bit mask + of MXDSCLKDATATURN field.*/ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Min (0x0UL) /*!< Min enumerator value of MXDSCLKDATATURN field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Max (0x4UL) /*!< Max enumerator value of MXDSCLKDATATURN field. */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_8NS (0x0UL) /*!< 8ns */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_9NS (0x1UL) /*!< 9ns */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_10NS (0x2UL) /*!< 10ns */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_11NS (0x3UL) /*!< 11ns */ + #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_12NS (0x4UL) /*!< 12ns */ + + +/* I3CCORE_CORE_SLVINTRREQ: This register is used in slave mode of operation. */ + #define I3CCORE_CORE_SLVINTRREQ_ResetValue (0x00000000UL) /*!< Reset value of SLVINTRREQ register. */ + +/* SIR @Bit 0 : Slave Interrupt Request */ + #define I3CCORE_CORE_SLVINTRREQ_SIR_Pos (0UL) /*!< Position of SIR field. */ + #define I3CCORE_CORE_SLVINTRREQ_SIR_Msk (0x1UL << I3CCORE_CORE_SLVINTRREQ_SIR_Pos) /*!< Bit mask of SIR field. */ + +/* SIRCTRL @Bits 1..2 : Slave Interrupt Request Control */ + #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Pos (1UL) /*!< Position of SIRCTRL field. */ + #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Msk (0x3UL << I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Pos) /*!< Bit mask of SIRCTRL field. */ + #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Min (0x0UL) /*!< Min enumerator value of SIRCTRL field. */ + #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Max (0x0UL) /*!< Max enumerator value of SIRCTRL field. */ + #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_SEND (0x0UL) /*!< Send the Assigned Dynamic Address */ + +/* MR @Bit 3 : Master Request */ + #define I3CCORE_CORE_SLVINTRREQ_MR_Pos (3UL) /*!< Position of MR field. */ + #define I3CCORE_CORE_SLVINTRREQ_MR_Msk (0x1UL << I3CCORE_CORE_SLVINTRREQ_MR_Pos) /*!< Bit mask of MR field. */ + +/* IBISTS @Bits 8..9 : IBI Completion Status */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Pos (8UL) /*!< Position of IBISTS field. */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Msk (0x3UL << I3CCORE_CORE_SLVINTRREQ_IBISTS_Pos) /*!< Bit mask of IBISTS field. */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Min (0x1UL) /*!< Min enumerator value of IBISTS field. */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Max (0x3UL) /*!< Max enumerator value of IBISTS field. */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_ACCEPTED (0x1UL) /*!< IBI accepted by the Master (ACK response received) */ + #define I3CCORE_CORE_SLVINTRREQ_IBISTS_NOATTEMPT (0x3UL) /*!< IBI Not Attempted */ + + +/* I3CCORE_CORE_SLVTSXSYMBLTIMING: TSP/TSL Symbol Timing Register */ + #define I3CCORE_CORE_SLVTSXSYMBLTIMING_ResetValue (0x0000003FUL) /*!< Reset value of SLVTSXSYMBLTIMING register. */ + +/* SLVTSXSYMBLCNT @Bits 0..5 : TSP/TSL Symbol Count Value. */ + #define I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Pos (0UL) /*!< Position of SLVTSXSYMBLCNT field. */ + #define I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Msk (0x3FUL << I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Pos) /*!< + Bit mask of SLVTSXSYMBLCNT field.*/ + + +/* I3CCORE_CORE_DEVICECTRLEXTENDED: Device Control Extended register. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_ResetValue (0x00000000UL) /*!< Reset value of DEVICECTRLEXTENDED register. */ + +/* DEVOPERATIONMODE @Bits 0..1 : This bit is used to select the Device Operation Mode before the controller is enabled. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Pos (0UL) /*!< Position of DEVOPERATIONMODE field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Msk (0x3UL << I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Pos) + /*!< Bit mask of DEVOPERATIONMODE field.*/ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Min (0x0UL) /*!< Min enumerator value of DEVOPERATIONMODE field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Max (0x1UL) /*!< Max enumerator value of DEVOPERATIONMODE field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_MASTER (0x0UL) /*!< (unspecified) */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_SLAVE (0x1UL) /*!< (unspecified) */ + +/* REQMSTACKCTRL @Bit 3 : In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current + master. */ + + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Pos (3UL) /*!< Position of REQMSTACKCTRL field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Msk (0x1UL << I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Pos) /*!< + Bit mask of REQMSTACKCTRL field.*/ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Min (0x0UL) /*!< Min enumerator value of REQMSTACKCTRL field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Max (0x1UL) /*!< Max enumerator value of REQMSTACKCTRL field. */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_ACK (0x0UL) /*!< ACK GETACCMST CCC */ + #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_NACK (0x1UL) /*!< NACK GETACCMST CCC */ + + +/* I3CCORE_CORE_SCLI3CODTIMING: SCL I3C Open Drain Timing Register */ + #define I3CCORE_CORE_SCLI3CODTIMING_ResetValue (0x000A0010UL) /*!< Reset value of SCLI3CODTIMING register. */ + +/* I3CODLCNT @Bits 0..7 : I3C Open Drain Low Count. */ + #define I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Pos (0UL) /*!< Position of I3CODLCNT field. */ + #define I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Pos) /*!< Bit mask of + I3CODLCNT field.*/ + +/* I3CODHCNT @Bits 16..23 : I3C Open Drain High Count. */ + #define I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Pos (16UL) /*!< Position of I3CODHCNT field. */ + #define I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Pos) /*!< Bit mask of + I3CODHCNT field.*/ + + +/* I3CCORE_CORE_SCLI3CPPTIMING: SCL I3C Push Pull Timing Register */ + #define I3CCORE_CORE_SCLI3CPPTIMING_ResetValue (0x000A000AUL) /*!< Reset value of SCLI3CPPTIMING register. */ + +/* I3CPPLCNT @Bits 0..7 : I3C Push Pull Low Count. */ + #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Pos (0UL) /*!< Position of I3CPPLCNT field. */ + #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Pos) /*!< Bit mask of + I3CPPLCNT field.*/ + +/* I3CPPHCNT @Bits 16..23 : I3C Push Pull High Count. */ + #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Pos (16UL) /*!< Position of I3CPPHCNT field. */ + #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Pos) /*!< Bit mask of + I3CPPHCNT field.*/ + + +/* I3CCORE_CORE_SCLI2CFMTIMING: SCL I2C Fast Mode Timing Register */ + #define I3CCORE_CORE_SCLI2CFMTIMING_ResetValue (0x00100010UL) /*!< Reset value of SCLI2CFMTIMING register. */ + +/* I2CFMLCNT @Bits 0..15 : I2C Fast Mode Low Count */ + #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Pos (0UL) /*!< Position of I2CFMLCNT field. */ + #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Pos) /*!< Bit mask of + I2CFMLCNT field.*/ + +/* I2CFMHCNT @Bits 16..31 : I2C Fast Mode High Count */ + #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Pos (16UL) /*!< Position of I2CFMHCNT field. */ + #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Pos) /*!< Bit mask of + I2CFMHCNT field.*/ + + +/* I3CCORE_CORE_SCLI2CFMPTIMING: SCL I2C Fast Mode Plus Timing Register */ + #define I3CCORE_CORE_SCLI2CFMPTIMING_ResetValue (0x00100010UL) /*!< Reset value of SCLI2CFMPTIMING register. */ + +/* I2CFMPLCNT @Bits 0..15 : I2C Fast Mode Plus Low Count */ + #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Pos (0UL) /*!< Position of I2CFMPLCNT field. */ + #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Pos) /*!< Bit mask of + I2CFMPLCNT field.*/ + +/* I2CFMPHCNT @Bits 16..23 : I2C Fast Mode Plus High Count */ + #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Pos (16UL) /*!< Position of I2CFMPHCNT field. */ + #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Pos) /*!< Bit mask of + I2CFMPHCNT field.*/ + + +/* I3CCORE_CORE_SCLEXTLCNTTIMING: SCL Extended Low Count Timing Register. */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_ResetValue (0x20202020UL) /*!< Reset value of SCLEXTLCNTTIMING register. */ + +/* I3CEXTLCNT1 @Bits 0..7 : I3C Extended Low Count Register 1 */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Pos (0UL) /*!< Position of I3CEXTLCNT1 field. */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Pos) /*!< Bit mask + of I3CEXTLCNT1 field.*/ + +/* I3CEXTLCNT2 @Bits 8..15 : I3C Extended Low Count Register 2 */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Pos (8UL) /*!< Position of I3CEXTLCNT2 field. */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Pos) /*!< Bit mask + of I3CEXTLCNT2 field.*/ + +/* I3CEXTLCNT3 @Bits 16..23 : I3C Extended Low Count Register 3 */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Pos (16UL) /*!< Position of I3CEXTLCNT3 field. */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Pos) /*!< Bit mask + of I3CEXTLCNT3 field.*/ + +/* I3CEXTLCNT4 @Bits 24..31 : I3C Extended Low Count Register 4 */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Pos (24UL) /*!< Position of I3CEXTLCNT4 field. */ + #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Pos) /*!< Bit mask + of I3CEXTLCNT4 field.*/ + + +/* I3CCORE_CORE_SCLEXTTERMNLCNTTIMING: SCL Termination Bit Low Count Timing Register */ + #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_ResetValue (0x00030000UL) /*!< Reset value of SCLEXTTERMNLCNTTIMING register. */ + +/* I3CEXTTERMNLCNT @Bits 0..3 : I3C Read Termination Bit Low count. */ + #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Pos (0UL) /*!< Position of I3CEXTTERMNLCNT field. */ + #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Msk (0xFUL << I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Pos) + /*!< Bit mask of I3CEXTTERMNLCNT field.*/ + +/* I3CTSSKEWCNT @Bits 16..19 : I3C HDR Ternary Skew Count. */ + #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Pos (16UL) /*!< Position of I3CTSSKEWCNT field. */ + #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Msk (0xFUL << I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Pos) + /*!< Bit mask of I3CTSSKEWCNT field.*/ + + +/* I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING: SDA Hold and Mode Switch Delay Timing Register */ + #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_ResetValue (0x00010000UL) /*!< Reset value of SDAHOLDSWITCHDLYTIMING register. */ + +/* SDATXHOLD @Bits 16..18 : This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with + */ + + #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Pos (16UL) /*!< Position of SDATXHOLD field. */ + #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Msk (0x7UL << I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Pos) /*!< + Bit mask of SDATXHOLD field.*/ + + +/* I3CCORE_CORE_BUSFREEAVAILTIMING: Bus Free and Available Timing Register */ + #define I3CCORE_CORE_BUSFREEAVAILTIMING_ResetValue (0x00200020UL) /*!< Reset value of BUSFREEAVAILTIMING register. */ + +/* BUSFREETIME @Bits 0..15 : This register field is used only in Master mode of operation */ + #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Pos (0UL) /*!< Position of BUSFREETIME field. */ + #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Msk (0xFFFFUL << I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Pos) /*!< Bit + mask of BUSFREETIME field.*/ + +/* BUSAVAILABLETIME @Bits 16..31 : This register field is used only in Slave mode of operation */ + #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Pos (16UL) /*!< Position of BUSAVAILABLETIME field. */ + #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Msk (0xFFFFUL << I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Pos) + /*!< Bit mask of BUSAVAILABLETIME field.*/ + + +/* I3CCORE_CORE_BUSIDLETIMING: Bus Idle Timing Register */ + #define I3CCORE_CORE_BUSIDLETIMING_ResetValue (0x00000020UL) /*!< Reset value of BUSIDLETIMING register. */ + +/* BUSIDLETIME @Bits 0..19 : Bus Idle Count Value. */ + #define I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Pos (0UL) /*!< Position of BUSIDLETIME field. */ + #define I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Msk (0xFFFFFUL << I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Pos) /*!< Bit mask of + BUSIDLETIME field.*/ + + +/* I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT: The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low + Bus Reset Pattern. */ + + #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_ResetValue (0x003567E0UL) /*!< Reset value of SCLLOWMSTEXTTIMEOUT register. */ + +/* SCLLOWMSTTIMEOUTCOUNT @Bits 0..25 : This count defines the number of core clock periods to count for generation of the SCL + Low Bus Reset Pattern. */ + + #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Pos (0UL) /*!< Position of SCLLOWMSTTIMEOUTCOUNT field. */ + #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Msk (0x3FFFFFFUL << I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Pos) + /*!< Bit mask of SCLLOWMSTTIMEOUTCOUNT field.*/ + + +/* I3CCORE_CORE_I3CVERID: This register reflects the current release number of DWC_mipi_i3c */ + #define I3CCORE_CORE_I3CVERID_ResetValue (0x3130302AUL) /*!< Reset value of I3CVERID register. */ + +/* I3CVERID @Bits 0..31 : Current release number */ + #define I3CCORE_CORE_I3CVERID_I3CVERID_Pos (0UL) /*!< Position of I3CVERID field. */ + #define I3CCORE_CORE_I3CVERID_I3CVERID_Msk (0xFFFFFFFFUL << I3CCORE_CORE_I3CVERID_I3CVERID_Pos) /*!< Bit mask of I3CVERID + field.*/ + + +/* I3CCORE_CORE_I3CVERTYPE: This register reflects the current release type of DWC_mipi_i3c. */ + #define I3CCORE_CORE_I3CVERTYPE_ResetValue (0x6C633033UL) /*!< Reset value of I3CVERTYPE register. */ + +/* I3CVERTYPE @Bits 0..31 : Current release type */ + #define I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Pos (0UL) /*!< Position of I3CVERTYPE field. */ + #define I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Msk (0xFFFFFFFFUL << I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Pos) /*!< Bit mask of + I3CVERTYPE field.*/ + + +/* I3CCORE_CORE_QUEUESIZECAPABILITY: This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_ResetValue (0x00022355UL) /*!< Reset value of QUEUESIZECAPABILITY register. */ + +/* TXBUFSIZE @Bits 0..3 : Transmit Data Buffer Size */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Pos (0UL) /*!< Position of TXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Pos) /*!< Bit mask + of TXBUFSIZE field.*/ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Min (0x0UL) /*!< Min enumerator value of TXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Max (0x5UL) /*!< Max enumerator value of TXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_32DWORD (0x4UL) /*!< 32 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_64DWORD (0x5UL) /*!< 64 DWORDS */ + +/* RXBUFSIZE @Bits 4..7 : Receive Data Buffer Size */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Pos (4UL) /*!< Position of RXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Pos) /*!< Bit mask + of RXBUFSIZE field.*/ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Min (0x0UL) /*!< Min enumerator value of RXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Max (0x5UL) /*!< Max enumerator value of RXBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_32DWORD (0x4UL) /*!< 32 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_64DWORD (0x5UL) /*!< 64 DWORDS */ + +/* CMDBUFSIZE @Bits 8..11 : Command Queue Size */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Pos (8UL) /*!< Position of CMDBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Pos) /*!< Bit + mask of CMDBUFSIZE field.*/ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Min (0x0UL) /*!< Min enumerator value of CMDBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Max (0x3UL) /*!< Max enumerator value of CMDBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS */ + +/* RESPBUFSIZE @Bits 12..15 : Response Queue Size */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Pos (12UL) /*!< Position of RESPBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Pos) /*!< Bit + mask of RESPBUFSIZE field.*/ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Min (0x0UL) /*!< Min enumerator value of RESPBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Max (0x3UL) /*!< Max enumerator value of RESPBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS */ + +/* IBIBUFSIZE @Bits 16..19 : IBI Queue Size */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Pos (16UL) /*!< Position of IBIBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Pos) /*!< Bit + mask of IBIBUFSIZE field.*/ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Min (0x0UL) /*!< Min enumerator value of IBIBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Max (0x3UL) /*!< Max enumerator value of IBIBUFSIZE field. */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS */ + #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS */ + + +/* I3CCORE_CORE_SECDEVCHARTABLE: Secondary Master Device Characteristic Table Location of Device [n] */ + #define I3CCORE_CORE_SECDEVCHARTABLE_MaxCount (32UL) /*!< Max size of SECDEVCHARTABLE[32] array. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_MaxIndex (31UL) /*!< Max index of SECDEVCHARTABLE[32] array. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_MinIndex (0UL) /*!< Min index of SECDEVCHARTABLE[32] array. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_ResetValue (0x00000000UL) /*!< Reset value of SECDEVCHARTABLE[32] register. */ + +/* DYNAMICADDR @Bits 0..7 : The Dynamic Addr of Device [n] */ + #define I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Pos (0UL) /*!< Position of DYNAMICADDR field. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Pos) /*!< Bit mask of + DYNAMICADDR field.*/ + +/* DCRTYPE @Bits 8..15 : The DCR TYPE of Device [n] */ + #define I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Pos (8UL) /*!< Position of DCRTYPE field. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Pos) /*!< Bit mask of DCRTYPE + field.*/ + +/* BCRTYPE @Bits 16..23 : The BCR TYPE of Device [n] */ + #define I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Pos (16UL) /*!< Position of BCRTYPE field. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Pos) /*!< Bit mask of BCRTYPE + field.*/ + +/* STATICADDR @Bits 24..31 : The Static Addr of Device [n] */ + #define I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Pos (24UL) /*!< Position of STATICADDR field. */ + #define I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Pos) /*!< Bit mask of + STATICADDR field.*/ + + +/* I3CCORE_CORE_DEVADDRTABLELOC: Device Address Table of Device [n] */ + #define I3CCORE_CORE_DEVADDRTABLELOC_MaxCount (10UL) /*!< Max size of DEVADDRTABLELOC[10] array. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_MaxIndex (9UL) /*!< Max index of DEVADDRTABLELOC[10] array. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_MinIndex (0UL) /*!< Min index of DEVADDRTABLELOC[10] array. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_ResetValue (0x00000000UL) /*!< Reset value of DEVADDRTABLELOC[10] register. */ + +/* DEVSTATICADDR @Bits 0..6 : Device Static Address. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Pos (0UL) /*!< Position of DEVSTATICADDR field. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Pos) /*!< Bit + mask of DEVSTATICADDR field.*/ + +/* DEVDYNAMICADDR @Bits 16..23 : Device Dynamic Address with parity. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Pos (16UL) /*!< Position of DEVDYNAMICADDR field. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Pos) /*!< Bit + mask of DEVDYNAMICADDR field.*/ + +/* DEVNACKRETRYCNT @Bits 29..30 : This field is used to set the Device NACK Retry count for the particular device. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Pos (29UL) /*!< Position of DEVNACKRETRYCNT field. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Msk (0x3UL << I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Pos) /*!< Bit + mask of DEVNACKRETRYCNT field.*/ + +/* LEGACYI2CDEVICE @Bit 31 : Legacy I2C device or not. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Pos (31UL) /*!< Position of LEGACYI2CDEVICE field. */ + #define I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Msk (0x1UL << I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Pos) /*!< Bit + mask of LEGACYI2CDEVICE field.*/ + + + +/* ================================================= Struct I3CCORE_DMA_CH0 ================================================== */ +/** + * @brief CH0 [I3CCORE_DMA_CH0] (unspecified) + */ +typedef struct { + __IOM uint32_t SAR0; /*!< (@ 0x00000000) This register contains the source address of the DMA + transfer.*/ + __IM uint32_t RESERVED; + __IOM uint32_t DAR0; /*!< (@ 0x00000008) This register contains the destination address of the + DMA transfer.*/ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t CTL00; /*!< (@ 0x00000018) This register contains fields that control the DMA + transfer.*/ + __IOM uint32_t CTL01; /*!< (@ 0x0000001C) This register contains fields that control the DMA + transfer.*/ + __IM uint32_t RESERVED2[8]; + __IOM uint32_t CFG0L; /*!< (@ 0x00000040) This register contains fields that configure the DMA + transfer.*/ + __IOM uint32_t CFG0H; /*!< (@ 0x00000044) This register contains fields that configure the DMA + transfer.*/ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t DSR0; /*!< (@ 0x00000050) Destination Scatter register. */ +} NRF_I3CCORE_DMA_CH0_Type; /*!< Size = 84 (0x054) */ + +/* I3CCORE_DMA_CH0_SAR0: This register contains the source address of the DMA transfer. */ + #define I3CCORE_DMA_CH0_SAR0_ResetValue (0x00000000UL) /*!< Reset value of SAR0 register. */ + +/* SAR @Bits 0..31 : Current Source Address of DMA transfer. */ + #define I3CCORE_DMA_CH0_SAR0_SAR_Pos (0UL) /*!< Position of SAR field. */ + #define I3CCORE_DMA_CH0_SAR0_SAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH0_SAR0_SAR_Pos) /*!< Bit mask of SAR field. */ + + +/* I3CCORE_DMA_CH0_DAR0: This register contains the destination address of the DMA transfer. */ + #define I3CCORE_DMA_CH0_DAR0_ResetValue (0x00000000UL) /*!< Reset value of DAR0 register. */ + +/* DAR @Bits 0..31 : Current Destination address of DMA transfer. */ + #define I3CCORE_DMA_CH0_DAR0_DAR_Pos (0UL) /*!< Position of DAR field. */ + #define I3CCORE_DMA_CH0_DAR0_DAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH0_DAR0_DAR_Pos) /*!< Bit mask of DAR field. */ + + +/* I3CCORE_DMA_CH0_CTL00: This register contains fields that control the DMA transfer. */ + #define I3CCORE_DMA_CH0_CTL00_ResetValue (0x02504821UL) /*!< Reset value of CTL00 register. */ + +/* INTEN @Bit 0 : Interrupt Enable Bit. */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_Pos (0UL) /*!< Position of INTEN field. */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_INTEN_Pos) /*!< Bit mask of INTEN field. */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_Min (0x0UL) /*!< Min enumerator value of INTEN field. */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_Max (0x1UL) /*!< Max enumerator value of INTEN field. */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_INTERRUPT_DISABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_INTEN_INTERRUPT_ENABLE (0x1UL) /*!< (unspecified) */ + +/* DSTTRWIDTH @Bits 1..3 : Destination Transfer Width. */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Pos (1UL) /*!< Position of DSTTRWIDTH field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Pos) /*!< Bit mask of DSTTRWIDTH + field.*/ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Min (0x0UL) /*!< Min enumerator value of DSTTRWIDTH field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Max (0x7UL) /*!< Max enumerator value of DSTTRWIDTH field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_7 (0x7UL) /*!< (unspecified) */ + +/* RSVDSRCTRWIDTH @Bits 4..6 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Pos (4UL) /*!< Position of RSVDSRCTRWIDTH field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Pos) /*!< Bit mask of + RSVDSRCTRWIDTH field.*/ + +/* DINC @Bits 7..8 : Destination Address Increment. */ + #define I3CCORE_DMA_CH0_CTL00_DINC_Pos (7UL) /*!< Position of DINC field. */ + #define I3CCORE_DMA_CH0_CTL00_DINC_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_DINC_Pos) /*!< Bit mask of DINC field. */ + #define I3CCORE_DMA_CH0_CTL00_DINC_Min (0x0UL) /*!< Min enumerator value of DINC field. */ + #define I3CCORE_DMA_CH0_CTL00_DINC_Max (0x3UL) /*!< Max enumerator value of DINC field. */ + #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_3 (0x3UL) /*!< (unspecified) */ + +/* SINC @Bits 9..10 : Source Address Increment. */ + #define I3CCORE_DMA_CH0_CTL00_SINC_Pos (9UL) /*!< Position of SINC field. */ + #define I3CCORE_DMA_CH0_CTL00_SINC_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_SINC_Pos) /*!< Bit mask of SINC field. */ + #define I3CCORE_DMA_CH0_CTL00_SINC_Min (0x0UL) /*!< Min enumerator value of SINC field. */ + #define I3CCORE_DMA_CH0_CTL00_SINC_Max (0x3UL) /*!< Max enumerator value of SINC field. */ + #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_3 (0x3UL) /*!< (unspecified) */ + +/* DESTMSIZE @Bits 11..13 : Destination Burst Transaction Length. */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Pos (11UL) /*!< Position of DESTMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Pos) /*!< Bit mask of DESTMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Min (0x0UL) /*!< Min enumerator value of DESTMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Max (0x7UL) /*!< Max enumerator value of DESTMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_7 (0x7UL) /*!< (unspecified) */ + +/* SRCMSIZE @Bits 14..16 : Source Burst Transaction Length. */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Pos (14UL) /*!< Position of SRCMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Pos) /*!< Bit mask of SRCMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Min (0x0UL) /*!< Min enumerator value of SRCMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Max (0x7UL) /*!< Max enumerator value of SRCMSIZE field. */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_7 (0x7UL) /*!< (unspecified) */ + +/* RSVDSRCGATHEREN @Bit 17 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Pos (17UL) /*!< Position of RSVDSRCGATHEREN field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Pos) /*!< Bit mask of + RSVDSRCGATHEREN field.*/ + +/* DSTSCATTEREN @Bit 18 : Destination scatter enable. */ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Pos (18UL) /*!< Position of DSTSCATTEREN field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Pos) /*!< Bit mask of DSTSCATTEREN + field.*/ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Min (0x0UL) /*!< Min enumerator value of DSTSCATTEREN field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Max (0x1UL) /*!< Max enumerator value of DSTSCATTEREN field. */ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_DST_SCATTER_DISABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_DST_SCATTER_ENABLE (0x1UL) /*!< (unspecified) */ + +/* RSVDCTL @Bit 19 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDCTL_Pos (19UL) /*!< Position of RSVDCTL field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDCTL_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDCTL_Pos) /*!< Bit mask of RSVDCTL field. */ + +/* TTFC @Bits 20..22 : Transfer Type and Flow Control. */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_Pos (20UL) /*!< Position of TTFC field. */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_TTFC_Pos) /*!< Bit mask of TTFC field. */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_Min (0x0UL) /*!< Min enumerator value of TTFC field. */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_Max (0x7UL) /*!< Max enumerator value of TTFC field. */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_7 (0x7UL) /*!< (unspecified) */ + +/* RSVDDMS @Bits 23..24 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDDMS_Pos (23UL) /*!< Position of RSVDDMS field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDDMS_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_RSVDDMS_Pos) /*!< Bit mask of RSVDDMS field. */ + +/* RSVDSMS @Bits 25..26 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSMS_Pos (25UL) /*!< Position of RSVDSMS field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDSMS_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_RSVDSMS_Pos) /*!< Bit mask of RSVDSMS field. */ + +/* RSVDLLPDSTEN @Bit 27 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Pos (27UL) /*!< Position of RSVDLLPDSTEN field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Pos) /*!< Bit mask of RSVDLLPDSTEN + field.*/ + +/* RSVDLLPSRCEN @Bit 28 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Pos (28UL) /*!< Position of RSVDLLPSRCEN field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Pos) /*!< Bit mask of RSVDLLPSRCEN + field.*/ + +/* RSVD1CTL @Bits 29..31 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Pos (29UL) /*!< Position of RSVD1CTL field. */ + #define I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Pos) /*!< Bit mask of RSVD1CTL field. */ + + +/* I3CCORE_DMA_CH0_CTL01: This register contains fields that control the DMA transfer. */ + #define I3CCORE_DMA_CH0_CTL01_ResetValue (0x00000002UL) /*!< Reset value of CTL01 register. */ + +/* BLOCKTS @Bits 0..4 : Block Transfer Size. */ + #define I3CCORE_DMA_CH0_CTL01_BLOCKTS_Pos (0UL) /*!< Position of BLOCKTS field. */ + #define I3CCORE_DMA_CH0_CTL01_BLOCKTS_Msk (0x1FUL << I3CCORE_DMA_CH0_CTL01_BLOCKTS_Pos) /*!< Bit mask of BLOCKTS field. */ + +/* RSVD2CTL @Bits 5..11 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Pos (5UL) /*!< Position of RSVD2CTL field. */ + #define I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Msk (0x7FUL << I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Pos) /*!< Bit mask of RSVD2CTL field. */ + +/* DONE @Bit 12 : Done bit. */ + #define I3CCORE_DMA_CH0_CTL01_DONE_Pos (12UL) /*!< Position of DONE field. */ + #define I3CCORE_DMA_CH0_CTL01_DONE_Msk (0x1UL << I3CCORE_DMA_CH0_CTL01_DONE_Pos) /*!< Bit mask of DONE field. */ + #define I3CCORE_DMA_CH0_CTL01_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define I3CCORE_DMA_CH0_CTL01_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define I3CCORE_DMA_CH0_CTL01_DONE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CTL01_DONE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_CH0_CFG0L: This register contains fields that configure the DMA transfer. */ + #define I3CCORE_DMA_CH0_CFG0L_ResetValue (0x00000E00UL) /*!< Reset value of CFG0L register. */ + +/* RSVDCFG @Bits 0..4 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Pos (0UL) /*!< Position of RSVDCFG field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Msk (0x1FUL << I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Pos) /*!< Bit mask of RSVDCFG field. */ + +/* CHPRIOR @Bits 5..7 : Channel Priority. */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Pos (5UL) /*!< Position of CHPRIOR field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Pos) /*!< Bit mask of CHPRIOR field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Min (0x0UL) /*!< Min enumerator value of CHPRIOR field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Max (0x7UL) /*!< Max enumerator value of CHPRIOR field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_7 (0x7UL) /*!< (unspecified) */ + +/* CHSUSP @Bit 8 : Channel Suspend. */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Pos (8UL) /*!< Position of CHSUSP field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_CHSUSP_Pos) /*!< Bit mask of CHSUSP field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Min (0x0UL) /*!< Min enumerator value of CHSUSP field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Max (0x1UL) /*!< Max enumerator value of CHSUSP field. */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_NOT_SUSPENDED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_SUSPENDED (0x1UL) /*!< (unspecified) */ + +/* FIFOEMPTY @Bit 9 : Channel FIFO status. */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Pos (9UL) /*!< Position of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Pos) /*!< Bit mask of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Min (0x0UL) /*!< Min enumerator value of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Max (0x1UL) /*!< Max enumerator value of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_NOT_EMPTY (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_EMPTY (0x1UL) /*!< (unspecified) */ + +/* HSSELDST @Bit 10 : Destination Software or Hardware Handshaking Select. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Pos (10UL) /*!< Position of HSSELDST field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_HSSELDST_Pos) /*!< Bit mask of HSSELDST field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Min (0x0UL) /*!< Min enumerator value of HSSELDST field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Max (0x1UL) /*!< Max enumerator value of HSSELDST field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_HARDWARE_HS (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_SOFTWARE_HS (0x1UL) /*!< (unspecified) */ + +/* HSSELSRC @Bit 11 : Source Software or Hardware Handshaking Select. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Pos (11UL) /*!< Position of HSSELSRC field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Pos) /*!< Bit mask of HSSELSRC field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Min (0x0UL) /*!< Min enumerator value of HSSELSRC field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Max (0x1UL) /*!< Max enumerator value of HSSELSRC field. */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_HARDWARE_HS (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_SOFTWARE_HS (0x1UL) /*!< (unspecified) */ + +/* RSVDLOCKCHL @Bits 12..13 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Pos (12UL) /*!< Position of RSVDLOCKCHL field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Msk (0x3UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Pos) /*!< Bit mask of RSVDLOCKCHL + field.*/ + +/* RSVDLOCKBL @Bits 14..15 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Pos (14UL) /*!< Position of RSVDLOCKBL field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Msk (0x3UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Pos) /*!< Bit mask of RSVDLOCKBL + field.*/ + +/* RSVDLOCKCH @Bit 16 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Pos (16UL) /*!< Position of RSVDLOCKCH field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Pos) /*!< Bit mask of RSVDLOCKCH + field.*/ + +/* RSVDLOCKB @Bit 17 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Pos (17UL) /*!< Position of RSVDLOCKB field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Pos) /*!< Bit mask of RSVDLOCKB field. */ + +/* DSTHSPOL @Bit 18 : Destination Handshaking Interface Polarity. */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Pos (18UL) /*!< Position of DSTHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Pos) /*!< Bit mask of DSTHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Min (0x0UL) /*!< Min enumerator value of DSTHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Max (0x1UL) /*!< Max enumerator value of DSTHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified) */ + +/* SRCHSPOL @Bit 19 : Source Handshaking Interface Polarity. */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Pos (19UL) /*!< Position of SRCHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Pos) /*!< Bit mask of SRCHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Min (0x0UL) /*!< Min enumerator value of SRCHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Max (0x1UL) /*!< Max enumerator value of SRCHSPOL field. */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified) */ + +/* MAXABRST @Bits 20..29 : Maximum AMBA Burst Length. */ + #define I3CCORE_DMA_CH0_CFG0L_MAXABRST_Pos (20UL) /*!< Position of MAXABRST field. */ + #define I3CCORE_DMA_CH0_CFG0L_MAXABRST_Msk (0x3FFUL << I3CCORE_DMA_CH0_CFG0L_MAXABRST_Pos) /*!< Bit mask of MAXABRST field. */ + +/* RSVDRELOADSRC @Bit 30 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Pos (30UL) /*!< Position of RSVDRELOADSRC field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Pos) /*!< Bit mask of + RSVDRELOADSRC field.*/ + +/* RSVDRELOADDST @Bit 31 : Reserved field- read-only */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Pos (31UL) /*!< Position of RSVDRELOADDST field. */ + #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Pos) /*!< Bit mask of + RSVDRELOADDST field.*/ + + +/* I3CCORE_DMA_CH0_CFG0H: This register contains fields that configure the DMA transfer. */ + #define I3CCORE_DMA_CH0_CFG0H_ResetValue (0x00000004UL) /*!< Reset value of CFG0H register. */ + +/* FCMODE @Bit 0 : Flow Control Mode. */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Pos (0UL) /*!< Position of FCMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_FCMODE_Pos) /*!< Bit mask of FCMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Min (0x0UL) /*!< Min enumerator value of FCMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Max (0x1UL) /*!< Max enumerator value of FCMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_FCMODE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0H_FCMODE_FCMODE_1 (0x1UL) /*!< (unspecified) */ + +/* FIFOMODE @Bit 1 : FIFO Mode Select. */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Pos (1UL) /*!< Position of FIFOMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Pos) /*!< Bit mask of FIFOMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Min (0x0UL) /*!< Min enumerator value of FIFOMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Max (0x1UL) /*!< Max enumerator value of FIFOMODE field. */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_FIFO_MODE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_FIFO_MODE_1 (0x1UL) /*!< (unspecified) */ + +/* PROTCTL @Bits 2..4 : Protection Control bits used to drive the AHB HPROT[3:1] bus. */ + #define I3CCORE_DMA_CH0_CFG0H_PROTCTL_Pos (2UL) /*!< Position of PROTCTL field. */ + #define I3CCORE_DMA_CH0_CFG0H_PROTCTL_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_PROTCTL_Pos) /*!< Bit mask of PROTCTL field. */ + +/* RSVDDSUPDEN @Bit 5 : Reserved field- read-only */ + #define I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Pos (5UL) /*!< Position of RSVDDSUPDEN field. */ + #define I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Pos) /*!< Bit mask of RSVDDSUPDEN + field.*/ + +/* RSVDSSUPDEN @Bit 6 : Reserved field- read-only */ + #define I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Pos (6UL) /*!< Position of RSVDSSUPDEN field. */ + #define I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Pos) /*!< Bit mask of RSVDSSUPDEN + field.*/ + +/* SRCPER @Bit 7 : Source Hardware Interface. */ + #define I3CCORE_DMA_CH0_CFG0H_SRCPER_Pos (7UL) /*!< Position of SRCPER field. */ + #define I3CCORE_DMA_CH0_CFG0H_SRCPER_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_SRCPER_Pos) /*!< Bit mask of SRCPER field. */ + +/* RSVD1CFG @Bits 8..10 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Pos (8UL) /*!< Position of RSVD1CFG field. */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Pos) /*!< Bit mask of RSVD1CFG field. */ + +/* DESTPER @Bit 11 : Destination hardware interface. */ + #define I3CCORE_DMA_CH0_CFG0H_DESTPER_Pos (11UL) /*!< Position of DESTPER field. */ + #define I3CCORE_DMA_CH0_CFG0H_DESTPER_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_DESTPER_Pos) /*!< Bit mask of DESTPER field. */ + +/* RSVD2CFG @Bits 12..14 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Pos (12UL) /*!< Position of RSVD2CFG field. */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Pos) /*!< Bit mask of RSVD2CFG field. */ + +/* RSVD3CFG @Bits 15..31 : Reserved field - read-only */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Pos (15UL) /*!< Position of RSVD3CFG field. */ + #define I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Msk (0x1FFFFUL << I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Pos) /*!< Bit mask of RSVD3CFG field.*/ + + +/* I3CCORE_DMA_CH0_DSR0: Destination Scatter register. */ + #define I3CCORE_DMA_CH0_DSR0_ResetValue (0x00000000UL) /*!< Reset value of DSR0 register. */ + +/* DSI @Bits 0..19 : Destination Scatter Interval. */ + #define I3CCORE_DMA_CH0_DSR0_DSI_Pos (0UL) /*!< Position of DSI field. */ + #define I3CCORE_DMA_CH0_DSR0_DSI_Msk (0xFFFFFUL << I3CCORE_DMA_CH0_DSR0_DSI_Pos) /*!< Bit mask of DSI field. */ + +/* DSC @Bits 20..24 : Destination Scatter Count. */ + #define I3CCORE_DMA_CH0_DSR0_DSC_Pos (20UL) /*!< Position of DSC field. */ + #define I3CCORE_DMA_CH0_DSR0_DSC_Msk (0x1FUL << I3CCORE_DMA_CH0_DSR0_DSC_Pos) /*!< Bit mask of DSC field. */ + + + +/* ================================================= Struct I3CCORE_DMA_CH1 ================================================== */ +/** + * @brief CH1 [I3CCORE_DMA_CH1] (unspecified) + */ +typedef struct { + __IOM uint32_t SAR1; /*!< (@ 0x00000000) This register contains the source address of the DMA + transfer.*/ + __IM uint32_t RESERVED; + __IOM uint32_t DAR1; /*!< (@ 0x00000008) This register contains the destination address of the + DMA transfer.*/ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t CTL1L; /*!< (@ 0x00000018) This register contains fields that control the DMA + transfer.*/ + __IOM uint32_t CTL1H; /*!< (@ 0x0000001C) This register contains fields that control the DMA + transfer.*/ + __IM uint32_t RESERVED2[8]; + __IOM uint32_t CFG1L; /*!< (@ 0x00000040) This register contains fields that configure the DMA + transfer.*/ + __IOM uint32_t CFG1H; /*!< (@ 0x00000044) This register contains fields that configure the DMA + transfer.*/ + __IOM uint32_t SGR1; /*!< (@ 0x00000048) Source Gather register */ +} NRF_I3CCORE_DMA_CH1_Type; /*!< Size = 76 (0x04C) */ + +/* I3CCORE_DMA_CH1_SAR1: This register contains the source address of the DMA transfer. */ + #define I3CCORE_DMA_CH1_SAR1_ResetValue (0x00000000UL) /*!< Reset value of SAR1 register. */ + +/* SAR @Bits 0..31 : Current Source Address of DMA transfer. */ + #define I3CCORE_DMA_CH1_SAR1_SAR_Pos (0UL) /*!< Position of SAR field. */ + #define I3CCORE_DMA_CH1_SAR1_SAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH1_SAR1_SAR_Pos) /*!< Bit mask of SAR field. */ + + +/* I3CCORE_DMA_CH1_DAR1: This register contains the destination address of the DMA transfer. */ + #define I3CCORE_DMA_CH1_DAR1_ResetValue (0x00000000UL) /*!< Reset value of DAR1 register. */ + +/* DAR @Bits 0..31 : Current Destination address of DMA transfer. */ + #define I3CCORE_DMA_CH1_DAR1_DAR_Pos (0UL) /*!< Position of DAR field. */ + #define I3CCORE_DMA_CH1_DAR1_DAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH1_DAR1_DAR_Pos) /*!< Bit mask of DAR field. */ + + +/* I3CCORE_DMA_CH1_CTL1L: This register contains fields that control the DMA transfer. */ + #define I3CCORE_DMA_CH1_CTL1L_ResetValue (0x00F04805UL) /*!< Reset value of CTL1L register. */ + +/* INTEN @Bit 0 : Interrupt Enable Bit. */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_Pos (0UL) /*!< Position of INTEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_INTEN_Pos) /*!< Bit mask of INTEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_Min (0x0UL) /*!< Min enumerator value of INTEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_Max (0x1UL) /*!< Max enumerator value of INTEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_INTERRUPT_DISABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_INTEN_INTERRUPT_ENABLE (0x1UL) /*!< (unspecified) */ + +/* RSVDDSTTRWIDTH @Bits 1..3 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Pos (1UL) /*!< Position of RSVDDSTTRWIDTH field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Pos) /*!< Bit mask of + RSVDDSTTRWIDTH field.*/ + +/* SRCTRWIDTH @Bits 4..6 : Source Transfer Width. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Pos (4UL) /*!< Position of SRCTRWIDTH field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Pos) /*!< Bit mask of SRCTRWIDTH + field.*/ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Min (0x0UL) /*!< Min enumerator value of SRCTRWIDTH field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Max (0x7UL) /*!< Max enumerator value of SRCTRWIDTH field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_7 (0x7UL) /*!< (unspecified) */ + +/* DINC @Bits 7..8 : Destination Address Increment. */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_Pos (7UL) /*!< Position of DINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_DINC_Pos) /*!< Bit mask of DINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_Min (0x0UL) /*!< Min enumerator value of DINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_Max (0x3UL) /*!< Max enumerator value of DINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_3 (0x3UL) /*!< (unspecified) */ + +/* SINC @Bits 9..10 : Source Address Increment. */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_Pos (9UL) /*!< Position of SINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_SINC_Pos) /*!< Bit mask of SINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_Min (0x0UL) /*!< Min enumerator value of SINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_Max (0x3UL) /*!< Max enumerator value of SINC field. */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_3 (0x3UL) /*!< (unspecified) */ + +/* DESTMSIZE @Bits 11..13 : Destination Burst Transaction Length. */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Pos (11UL) /*!< Position of DESTMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Pos) /*!< Bit mask of DESTMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Min (0x0UL) /*!< Min enumerator value of DESTMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Max (0x7UL) /*!< Max enumerator value of DESTMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_7 (0x7UL) /*!< (unspecified) */ + +/* SRCMSIZE @Bits 14..16 : Source Burst Transaction Length. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Pos (14UL) /*!< Position of SRCMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Pos) /*!< Bit mask of SRCMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Min (0x0UL) /*!< Min enumerator value of SRCMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Max (0x7UL) /*!< Max enumerator value of SRCMSIZE field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_7 (0x7UL) /*!< (unspecified) */ + +/* SRCGATHEREN @Bit 17 : Source gather enable. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Pos (17UL) /*!< Position of SRCGATHEREN field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Pos) /*!< Bit mask of SRCGATHEREN + field.*/ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Min (0x0UL) /*!< Min enumerator value of SRCGATHEREN field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Max (0x1UL) /*!< Max enumerator value of SRCGATHEREN field. */ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_SRC_GATHER_DISABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_SRC_GATHER_ENABLE (0x1UL) /*!< (unspecified) */ + +/* RSVDDSTSCATTEREN @Bit 18 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Pos (18UL) /*!< Position of RSVDDSTSCATTEREN field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Pos) /*!< Bit mask of + RSVDDSTSCATTEREN field.*/ + +/* RSVDCTL @Bit 19 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Pos (19UL) /*!< Position of RSVDCTL field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Pos) /*!< Bit mask of RSVDCTL field. */ + +/* TTFC @Bits 20..22 : Transfer Type and Flow Control. */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_Pos (20UL) /*!< Position of TTFC field. */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_TTFC_Pos) /*!< Bit mask of TTFC field. */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_Min (0x0UL) /*!< Min enumerator value of TTFC field. */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_Max (0x7UL) /*!< Max enumerator value of TTFC field. */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_7 (0x7UL) /*!< (unspecified) */ + +/* RSVDDMS @Bits 23..24 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Pos (23UL) /*!< Position of RSVDDMS field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Pos) /*!< Bit mask of RSVDDMS field. */ + +/* RSVDSMS @Bits 25..26 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Pos (25UL) /*!< Position of RSVDSMS field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Pos) /*!< Bit mask of RSVDSMS field. */ + +/* RSVDLLPDSTEN @Bit 27 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Pos (27UL) /*!< Position of RSVDLLPDSTEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Pos) /*!< Bit mask of RSVDLLPDSTEN + field.*/ + +/* RSVDLLPSRCEN @Bit 28 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Pos (28UL) /*!< Position of RSVDLLPSRCEN field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Pos) /*!< Bit mask of RSVDLLPSRCEN + field.*/ + +/* RSVD1CTL @Bits 29..31 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Pos (29UL) /*!< Position of RSVD1CTL field. */ + #define I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Pos) /*!< Bit mask of RSVD1CTL field. */ + + +/* I3CCORE_DMA_CH1_CTL1H: This register contains fields that control the DMA transfer. */ + #define I3CCORE_DMA_CH1_CTL1H_ResetValue (0x00000002UL) /*!< Reset value of CTL1H register. */ + +/* BLOCKTS @Bits 0..4 : Block Transfer Size. */ + #define I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Pos (0UL) /*!< Position of BLOCKTS field. */ + #define I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Msk (0x1FUL << I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Pos) /*!< Bit mask of BLOCKTS field. */ + +/* RSVD2CTL @Bits 5..11 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Pos (5UL) /*!< Position of RSVD2CTL field. */ + #define I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Msk (0x7FUL << I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Pos) /*!< Bit mask of RSVD2CTL field. */ + +/* DONE @Bit 12 : Done bit. */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_Pos (12UL) /*!< Position of DONE field. */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1H_DONE_Pos) /*!< Bit mask of DONE field. */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CTL1H_DONE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_CH1_CFG1L: This register contains fields that configure the DMA transfer. */ + #define I3CCORE_DMA_CH1_CFG1L_ResetValue (0x00000E20UL) /*!< Reset value of CFG1L register. */ + +/* RSVDCFG @Bits 0..4 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Pos (0UL) /*!< Position of RSVDCFG field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Msk (0x1FUL << I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Pos) /*!< Bit mask of RSVDCFG field. */ + +/* CHPRIOR @Bits 5..7 : Channel Priority. */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Pos (5UL) /*!< Position of CHPRIOR field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Pos) /*!< Bit mask of CHPRIOR field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Min (0x0UL) /*!< Min enumerator value of CHPRIOR field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Max (0x7UL) /*!< Max enumerator value of CHPRIOR field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_1 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_2 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_3 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_4 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_5 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_6 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_7 (0x7UL) /*!< (unspecified) */ + +/* CHSUSP @Bit 8 : Channel Suspend. */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Pos (8UL) /*!< Position of CHSUSP field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_CHSUSP_Pos) /*!< Bit mask of CHSUSP field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Min (0x0UL) /*!< Min enumerator value of CHSUSP field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Max (0x1UL) /*!< Max enumerator value of CHSUSP field. */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_NOT_SUSPENDED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_SUSPENDED (0x1UL) /*!< (unspecified) */ + +/* FIFOEMPTY @Bit 9 : Channel FIFO status. */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Pos (9UL) /*!< Position of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Pos) /*!< Bit mask of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Min (0x0UL) /*!< Min enumerator value of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Max (0x1UL) /*!< Max enumerator value of FIFOEMPTY field. */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_NOT_EMPTY (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_EMPTY (0x1UL) /*!< (unspecified) */ + +/* HSSELDST @Bit 10 : Destination Software or Hardware Handshaking Select. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Pos (10UL) /*!< Position of HSSELDST field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_HSSELDST_Pos) /*!< Bit mask of HSSELDST field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Min (0x0UL) /*!< Min enumerator value of HSSELDST field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Max (0x1UL) /*!< Max enumerator value of HSSELDST field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_HARDWARE_HS (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_SOFTWARE_HS (0x1UL) /*!< (unspecified) */ + +/* HSSELSRC @Bit 11 : Source Software or Hardware Handshaking Select. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Pos (11UL) /*!< Position of HSSELSRC field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Pos) /*!< Bit mask of HSSELSRC field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Min (0x0UL) /*!< Min enumerator value of HSSELSRC field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Max (0x1UL) /*!< Max enumerator value of HSSELSRC field. */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_HARDWARE_HS (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_SOFTWARE_HS (0x1UL) /*!< (unspecified) */ + +/* RSVDLOCKCHL @Bits 12..13 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Pos (12UL) /*!< Position of RSVDLOCKCHL field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Msk (0x3UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Pos) /*!< Bit mask of RSVDLOCKCHL + field.*/ + +/* RSVDLOCKBL @Bits 14..15 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Pos (14UL) /*!< Position of RSVDLOCKBL field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Msk (0x3UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Pos) /*!< Bit mask of RSVDLOCKBL + field.*/ + +/* RSVDLOCKCH @Bit 16 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Pos (16UL) /*!< Position of RSVDLOCKCH field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Pos) /*!< Bit mask of RSVDLOCKCH + field.*/ + +/* RSVDLOCKB @Bit 17 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Pos (17UL) /*!< Position of RSVDLOCKB field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Pos) /*!< Bit mask of RSVDLOCKB field. */ + +/* DSTHSPOL @Bit 18 : Destination Handshaking Interface Polarity. */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Pos (18UL) /*!< Position of DSTHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Pos) /*!< Bit mask of DSTHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Min (0x0UL) /*!< Min enumerator value of DSTHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Max (0x1UL) /*!< Max enumerator value of DSTHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified) */ + +/* SRCHSPOL @Bit 19 : Source Handshaking Interface Polarity. */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Pos (19UL) /*!< Position of SRCHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Pos) /*!< Bit mask of SRCHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Min (0x0UL) /*!< Min enumerator value of SRCHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Max (0x1UL) /*!< Max enumerator value of SRCHSPOL field. */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified) */ + +/* MAXABRST @Bits 20..29 : Maximum AMBA Burst Length. */ + #define I3CCORE_DMA_CH1_CFG1L_MAXABRST_Pos (20UL) /*!< Position of MAXABRST field. */ + #define I3CCORE_DMA_CH1_CFG1L_MAXABRST_Msk (0x3FFUL << I3CCORE_DMA_CH1_CFG1L_MAXABRST_Pos) /*!< Bit mask of MAXABRST field. */ + +/* RSVDRELOADSRC @Bit 30 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Pos (30UL) /*!< Position of RSVDRELOADSRC field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Pos) /*!< Bit mask of + RSVDRELOADSRC field.*/ + +/* RSVDRELOADDST @Bit 31 : Reserved field- read-only */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Pos (31UL) /*!< Position of RSVDRELOADDST field. */ + #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Pos) /*!< Bit mask of + RSVDRELOADDST field.*/ + + +/* I3CCORE_DMA_CH1_CFG1H: This register contains fields that configure the DMA transfer. */ + #define I3CCORE_DMA_CH1_CFG1H_ResetValue (0x00000004UL) /*!< Reset value of CFG1H register. */ + +/* FCMODE @Bit 0 : Flow Control Mode. */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Pos (0UL) /*!< Position of FCMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_FCMODE_Pos) /*!< Bit mask of FCMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Min (0x0UL) /*!< Min enumerator value of FCMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Max (0x1UL) /*!< Max enumerator value of FCMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_FCMODE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1H_FCMODE_FCMODE_1 (0x1UL) /*!< (unspecified) */ + +/* FIFOMODE @Bit 1 : FIFO Mode Select. */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Pos (1UL) /*!< Position of FIFOMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Pos) /*!< Bit mask of FIFOMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Min (0x0UL) /*!< Min enumerator value of FIFOMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Max (0x1UL) /*!< Max enumerator value of FIFOMODE field. */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_FIFO_MODE_0 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_FIFO_MODE_1 (0x1UL) /*!< (unspecified) */ + +/* PROTCTL @Bits 2..4 : Protection Control bits used to drive the AHB HPROT[3:1] bus. */ + #define I3CCORE_DMA_CH1_CFG1H_PROTCTL_Pos (2UL) /*!< Position of PROTCTL field. */ + #define I3CCORE_DMA_CH1_CFG1H_PROTCTL_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1H_PROTCTL_Pos) /*!< Bit mask of PROTCTL field. */ + +/* RSVDDSUPDEN @Bit 5 : Reserved field- read-only */ + #define I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Pos (5UL) /*!< Position of RSVDDSUPDEN field. */ + #define I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Pos) /*!< Bit mask of RSVDDSUPDEN + field.*/ + +/* RSVDSSUPDEN @Bit 6 : Reserved field- read-only */ + #define I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Pos (6UL) /*!< Position of RSVDSSUPDEN field. */ + #define I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Pos) /*!< Bit mask of RSVDSSUPDEN + field.*/ + +/* SRCPER @Bit 7 : Source Hardware Interface. */ + #define I3CCORE_DMA_CH1_CFG1H_SRCPER_Pos (7UL) /*!< Position of SRCPER field. */ + #define I3CCORE_DMA_CH1_CFG1H_SRCPER_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_SRCPER_Pos) /*!< Bit mask of SRCPER field. */ + +/* RSVD1CFG @Bits 8..10 : Reserved field - read-only */ + #define I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Pos (8UL) /*!< Position of RSVD1CFG field. */ + #define I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Pos) /*!< Bit mask of RSVD1CFG field. */ + +/* DESTPER @Bit 11 : Destination hardware interface. */ + #define I3CCORE_DMA_CH1_CFG1H_DESTPER_Pos (11UL) /*!< Position of DESTPER field. */ + #define I3CCORE_DMA_CH1_CFG1H_DESTPER_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_DESTPER_Pos) /*!< Bit mask of DESTPER field. */ + + +/* I3CCORE_DMA_CH1_SGR1: Source Gather register */ + #define I3CCORE_DMA_CH1_SGR1_ResetValue (0x00000000UL) /*!< Reset value of SGR1 register. */ + +/* SGI @Bits 0..19 : Source Gather Interval. */ + #define I3CCORE_DMA_CH1_SGR1_SGI_Pos (0UL) /*!< Position of SGI field. */ + #define I3CCORE_DMA_CH1_SGR1_SGI_Msk (0xFFFFFUL << I3CCORE_DMA_CH1_SGR1_SGI_Pos) /*!< Bit mask of SGI field. */ + +/* SGC @Bits 20..24 : Source Gather Count. */ + #define I3CCORE_DMA_CH1_SGR1_SGC_Pos (20UL) /*!< Position of SGC field. */ + #define I3CCORE_DMA_CH1_SGR1_SGC_Msk (0x1FUL << I3CCORE_DMA_CH1_SGR1_SGC_Pos) /*!< Bit mask of SGC field. */ + + + +/* ================================================= Struct I3CCORE_DMA_INT ================================================== */ +/** + * @brief INT [I3CCORE_DMA_INT] (unspecified) + */ +typedef struct { + __IOM uint32_t RAWTFR; /*!< (@ 0x00000000) Interrupt events are stored in this Raw Interrupt + Status register before masking.*/ + __IM uint32_t RESERVED; + __IOM uint32_t RAWBLOCK; /*!< (@ 0x00000008) Interrupt events are stored in this Raw Interrupt + Status register before masking.*/ + __IM uint32_t RESERVED1; + __IOM uint32_t RAWSRCTRAN; /*!< (@ 0x00000010) Interrupt events are stored in this Raw Interrupt + Status register before masking.*/ + __IM uint32_t RESERVED2; + __IOM uint32_t RAWDSTTRAN; /*!< (@ 0x00000018) Interrupt events are stored in this Raw Interrupt + Status register before masking.*/ + __IM uint32_t RESERVED3; + __IOM uint32_t RAWERR; /*!< (@ 0x00000020) Interrupt events are stored in this Raw Interrupt + Status register before masking.*/ + __IM uint32_t RESERVED4; + __IOM uint32_t STATUSTFR; /*!< (@ 0x00000028) Channel DMA Transfer complete interrupt event from all + channels is stored in this Interrupt Status register + after masking.*/ + __IM uint32_t RESERVED5; + __IOM uint32_t STATUSBLOCK; /*!< (@ 0x00000030) Channel Block complete interrupt event from all + channels is stored in this Interrupt Status register + after masking.*/ + __IM uint32_t RESERVED6; + __IOM uint32_t STATUSSRCTRAN; /*!< (@ 0x00000038) Channel Source Transaction complete interrupt event + from all channels is stored in this Interrupt Status + register after masking.*/ + __IM uint32_t RESERVED7; + __IOM uint32_t STATUSDSTTRAN; /*!< (@ 0x00000040) Channel destination transaction complete interrupt + event from all channels is stored in this Interrupt + Status register after masking.*/ + __IM uint32_t RESERVED8; + __IOM uint32_t STATUSERR; /*!< (@ 0x00000048) Channel Error interrupt event from all channels is + stored in this Interrupt Status register after + masking.*/ + __IM uint32_t RESERVED9; + __IOM uint32_t MASKTFR; /*!< (@ 0x00000050) The contents of the Raw Status register RawTfr is + masked with the contents of the Mask register MaskTfr.*/ + __IM uint32_t RESERVED10; + __IOM uint32_t MASKBLOCK; /*!< (@ 0x00000058) The contents of the Raw Status register RawBlock is + masked with the contents of the Mask register + MaskBlock.*/ + __IM uint32_t RESERVED11; + __IOM uint32_t MASKSRCTRAN; /*!< (@ 0x00000060) The contents of the Raw Status register RawSrcTran is + masked with the contents of the Mask register + MaskSrcTran.*/ + __IM uint32_t RESERVED12; + __IOM uint32_t MASKDSTTRAN; /*!< (@ 0x00000068) The contents of the Raw Status register RawDstTran is + masked with the contents of the Mask register + MaskDstTran.*/ + __IM uint32_t RESERVED13; + __IOM uint32_t MASKERR; /*!< (@ 0x00000070) The contents of the Raw Status register RawErr is + masked with the contents of the Mask register MaskErr.*/ + __IM uint32_t RESERVED14; + __IOM uint32_t CLEARTFR; /*!< (@ 0x00000078) Each bit in the RawTfr and StatusTfr is cleared on the + same cycle by writing a 1 to the corresponding location + in the this registers.*/ + __IM uint32_t RESERVED15; + __IOM uint32_t CLEARBLOCK; /*!< (@ 0x00000080) Each bit in the RawBlock and StatusBlock is cleared on + the same cycle by writing a 1 to the corresponding + location in the this registers.*/ + __IM uint32_t RESERVED16; + __IOM uint32_t CLEARSRCTRAN; /*!< (@ 0x00000088) Each bit in the RawSrcTran and StatusSrcTran is cleared + on the same cycle by writing a 1 to the corresponding + location in the this registers.*/ + __IM uint32_t RESERVED17; + __IOM uint32_t CLEARDSTTRAN; /*!< (@ 0x00000090) Each bit in the RawDstTran and StatusDstTran is cleared + on the same cycle by writing a 1 to the corresponding + location in the this registers.*/ + __IM uint32_t RESERVED18; + __IOM uint32_t CLEARERR; /*!< (@ 0x00000098) Each bit in the RawErr and StatusErr is cleared on the + same cycle by writing a 1 to the corresponding location + in the this registers.*/ + __IM uint32_t RESERVED19; + __IOM uint32_t STATUSINT; /*!< (@ 0x000000A0) The contents of each of the five Status registers + StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, + StatusErr is ORed to produce a single bit for each + interrupt type in the Combined Status register + (StatusInt).*/ +} NRF_I3CCORE_DMA_INT_Type; /*!< Size = 164 (0x0A4) */ + +/* I3CCORE_DMA_INT_RAWTFR: Interrupt events are stored in this Raw Interrupt Status register before masking. */ + #define I3CCORE_DMA_INT_RAWTFR_ResetValue (0x00000000UL) /*!< Reset value of RAWTFR register. */ + +/* RAW @Bits 0..1 : Raw Status for IntTfr Interrupt */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_Pos (0UL) /*!< Position of RAW field. */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWTFR_RAW_Pos) /*!< Bit mask of RAW field. */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_RAWTFR_RAW_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_RAWBLOCK: Interrupt events are stored in this Raw Interrupt Status register before masking. */ + #define I3CCORE_DMA_INT_RAWBLOCK_ResetValue (0x00000000UL) /*!< Reset value of RAWBLOCK register. */ + +/* RAW @Bits 0..1 : Raw Status for IntBlock Interrupt */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Pos (0UL) /*!< Position of RAW field. */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWBLOCK_RAW_Pos) /*!< Bit mask of RAW field. */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_RAWBLOCK_RAW_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_RAWSRCTRAN: Interrupt events are stored in this Raw Interrupt Status register before masking. */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of RAWSRCTRAN register. */ + +/* RAW @Bits 0..1 : Raw Status for IntSrcTran Interrupt */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Pos (0UL) /*!< Position of RAW field. */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Pos) /*!< Bit mask of RAW field. */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_RAWDSTTRAN: Interrupt events are stored in this Raw Interrupt Status register before masking. */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of RAWDSTTRAN register. */ + +/* RAW @Bits 0..1 : Raw Status for IntDstTran Interrupt */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Pos (0UL) /*!< Position of RAW field. */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Pos) /*!< Bit mask of RAW field. */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_RAWERR: Interrupt events are stored in this Raw Interrupt Status register before masking. */ + #define I3CCORE_DMA_INT_RAWERR_ResetValue (0x00000000UL) /*!< Reset value of RAWERR register. */ + +/* RAW @Bits 0..1 : Raw Status for IntErr Interrupt */ + #define I3CCORE_DMA_INT_RAWERR_RAW_Pos (0UL) /*!< Position of RAW field. */ + #define I3CCORE_DMA_INT_RAWERR_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWERR_RAW_Pos) /*!< Bit mask of RAW field. */ + #define I3CCORE_DMA_INT_RAWERR_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWERR_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field. */ + #define I3CCORE_DMA_INT_RAWERR_RAW_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_RAWERR_RAW_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSTFR: Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status + register after masking. */ + + #define I3CCORE_DMA_INT_STATUSTFR_ResetValue (0x00000000UL) /*!< Reset value of STATUSTFR register. */ + +/* STATUS @Bits 0..1 : Status for IntTfr Interrupt */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSTFR_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSTFR_STATUS_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSBLOCK: Channel Block complete interrupt event from all channels is stored in this Interrupt Status + register after masking. */ + + #define I3CCORE_DMA_INT_STATUSBLOCK_ResetValue (0x00000000UL) /*!< Reset value of STATUSBLOCK register. */ + +/* STATUS @Bits 0..1 : Status for IntBlock Interrupt */ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Pos) /*!< Bit mask of STATUS + field.*/ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSSRCTRAN: Channel Source Transaction complete interrupt event from all channels is stored in this + Interrupt Status register after masking. */ + + #define I3CCORE_DMA_INT_STATUSSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of STATUSSRCTRAN register. */ + +/* STATUS @Bits 0..1 : Status for IntSrcTran Interrupt */ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Pos) /*!< Bit mask of STATUS + field.*/ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSDSTTRAN: Channel destination transaction complete interrupt event from all channels is stored in this + Interrupt Status register after masking. */ + + #define I3CCORE_DMA_INT_STATUSDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of STATUSDSTTRAN register. */ + +/* STATUS @Bits 0..1 : Status for IntDstTran Interrupt */ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Pos) /*!< Bit mask of STATUS + field.*/ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSERR: Channel Error interrupt event from all channels is stored in this Interrupt Status register after + masking. */ + + #define I3CCORE_DMA_INT_STATUSERR_ResetValue (0x00000000UL) /*!< Reset value of STATUSERR register. */ + +/* STATUS @Bits 0..1 : Status for IntErr Interrupt */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSERR_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSERR_STATUS_ACTIVE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_MASKTFR: The contents of the Raw Status register RawTfr is masked with the contents of the Mask register + MaskTfr. */ + + #define I3CCORE_DMA_INT_MASKTFR_ResetValue (0x00000000UL) /*!< Reset value of MASKTFR register. */ + +/* INTMASK @Bits 0..1 : Mask for IntTfr Interrupt */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Pos (0UL) /*!< Position of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKTFR_INTMASK_Pos) /*!< Bit mask of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_MASK (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASK_UNMASK (0x1UL) /*!< (unspecified) */ + +/* RSVDMASKTFR @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Pos (2UL) /*!< Position of RSVDMASKTFR field. */ + #define I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Msk (0x3FUL << I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Pos) /*!< Bit mask of + RSVDMASKTFR field.*/ + +/* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE + field.*/ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_MASKBLOCK: The contents of the Raw Status register RawBlock is masked with the contents of the Mask register + MaskBlock. */ + + #define I3CCORE_DMA_INT_MASKBLOCK_ResetValue (0x00000000UL) /*!< Reset value of MASKBLOCK register. */ + +/* INTMASK @Bits 0..1 : Mask for IntBlock Interrupt */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Pos (0UL) /*!< Position of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Pos) /*!< Bit mask of INTMASK + field.*/ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_MASK (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_UNMASK (0x1UL) /*!< (unspecified) */ + +/* RSVDMASKBLOCK @Bits 2..7 : Reserved field- read-only */ + #define I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Pos (2UL) /*!< Position of RSVDMASKBLOCK field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Msk (0x3FUL << I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Pos) /*!< Bit mask of + RSVDMASKBLOCK field.*/ + +/* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE + field.*/ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_MASKSRCTRAN: The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask + register MaskSrcTran. */ + + #define I3CCORE_DMA_INT_MASKSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of MASKSRCTRAN register. */ + +/* INTMASK @Bits 0..1 : Mask for IntSrcTran Interrupt */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Pos (0UL) /*!< Position of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Pos) /*!< Bit mask of INTMASK + field.*/ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_MASK (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_UNMASK (0x1UL) /*!< (unspecified) */ + +/* RSVDMASKSRCTRAN @Bits 2..7 : Reserved field- read-only */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Pos (2UL) /*!< Position of RSVDMASKSRCTRAN field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Msk (0x3FUL << I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Pos) /*!< Bit + mask of RSVDMASKSRCTRAN field.*/ + +/* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Pos) /*!< Bit mask of + INTMASKWE field.*/ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_MASKDSTTRAN: The contents of the Raw Status register RawDstTran is masked with the contents of the Mask + register MaskDstTran. */ + + #define I3CCORE_DMA_INT_MASKDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of MASKDSTTRAN register. */ + +/* INTMASK @Bits 0..1 : Mask for IntDstTran Interrupt */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Pos (0UL) /*!< Position of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Pos) /*!< Bit mask of INTMASK + field.*/ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_MASK (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_UNMASK (0x1UL) /*!< (unspecified) */ + +/* RSVDMASKDSTTRAN @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Pos (2UL) /*!< Position of RSVDMASKDSTTRAN field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Msk (0x3FUL << I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Pos) /*!< Bit + mask of RSVDMASKDSTTRAN field.*/ + +/* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Pos) /*!< Bit mask of + INTMASKWE field.*/ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_MASKERR: The contents of the Raw Status register RawErr is masked with the contents of the Mask register + MaskErr. */ + + #define I3CCORE_DMA_INT_MASKERR_ResetValue (0x00000000UL) /*!< Reset value of MASKERR register. */ + +/* INTMASK @Bits 0..1 : Mask for IntErr Interrupt */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_Pos (0UL) /*!< Position of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKERR_INTMASK_Pos) /*!< Bit mask of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_MASK (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKERR_INTMASK_UNMASK (0x1UL) /*!< (unspecified) */ + +/* RSVDMASKERR @Bits 2..7 : Reserved field- read-only */ + #define I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Pos (2UL) /*!< Position of RSVDMASKERR field. */ + #define I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Msk (0x3FUL << I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Pos) /*!< Bit mask of + RSVDMASKERR field.*/ + +/* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKERR_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE + field.*/ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field. */ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_CLEARTFR: Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the + corresponding location in the this registers. */ + + #define I3CCORE_DMA_INT_CLEARTFR_ResetValue (0x00000000UL) /*!< Reset value of CLEARTFR register. */ + +/* CLEAR @Bits 0..1 : Clear for IntTfr Interrupt */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARTFR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_CLEAR (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_CLEARBLOCK: Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the + corresponding location in the this registers. */ + + #define I3CCORE_DMA_INT_CLEARBLOCK_ResetValue (0x00000000UL) /*!< Reset value of CLEARBLOCK register. */ + +/* CLEAR @Bits 0..1 : Clear for IntBlock Interrupt */ + #define I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ + + +/* I3CCORE_DMA_INT_CLEARSRCTRAN: Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the + corresponding location in the this registers. */ + + #define I3CCORE_DMA_INT_CLEARSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of CLEARSRCTRAN register. */ + +/* CLEAR @Bits 0..1 : Clear for IntSrcTran Interrupt */ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Pos) /*!< Bit mask of CLEAR + field.*/ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_CLEAR (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_CLEARDSTTRAN: Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the + corresponding location in the this registers. */ + + #define I3CCORE_DMA_INT_CLEARDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of CLEARDSTTRAN register. */ + +/* CLEAR @Bits 0..1 : Clear for IntDstTran Interrupt */ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Pos) /*!< Bit mask of CLEAR + field.*/ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_CLEAR (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_CLEARERR: Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the + corresponding location in the this registers. */ + + #define I3CCORE_DMA_INT_CLEARERR_ResetValue (0x00000000UL) /*!< Reset value of CLEARERR register. */ + +/* CLEAR @Bits 0..1 : Clear for IntErr Interrupt */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARERR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field. */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_CLEARERR_CLEAR_CLEAR (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_INT_STATUSINT: The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, + StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined + Status register (StatusInt). */ + + #define I3CCORE_DMA_INT_STATUSINT_ResetValue (0x00000000UL) /*!< Reset value of STATUSINT register. */ + +/* TFR @Bit 0 : OR of the contents of StatusTfr register */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_Pos (0UL) /*!< Position of TFR field. */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_TFR_Pos) /*!< Bit mask of TFR field. */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_Min (0x0UL) /*!< Min enumerator value of TFR field. */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_Max (0x1UL) /*!< Max enumerator value of TFR field. */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSINT_TFR_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* BLOCK @Bit 1 : OR of the contents of StatusBlock register */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Pos (1UL) /*!< Position of BLOCK field. */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_BLOCK_Pos) /*!< Bit mask of BLOCK field. */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Min (0x0UL) /*!< Min enumerator value of BLOCK field. */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Max (0x1UL) /*!< Max enumerator value of BLOCK field. */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSINT_BLOCK_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* SRCT @Bit 2 : OR of the contents of StatusSrcTran */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_Pos (2UL) /*!< Position of SRCT field. */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_SRCT_Pos) /*!< Bit mask of SRCT field. */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_Min (0x0UL) /*!< Min enumerator value of SRCT field. */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_Max (0x1UL) /*!< Max enumerator value of SRCT field. */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSINT_SRCT_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* DSTT @Bit 3 : OR of the contents of StatusDstTran */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_Pos (3UL) /*!< Position of DSTT field. */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_DSTT_Pos) /*!< Bit mask of DSTT field. */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_Min (0x0UL) /*!< Min enumerator value of DSTT field. */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_Max (0x1UL) /*!< Max enumerator value of DSTT field. */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSINT_DSTT_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* ERR @Bit 4 : OR of the contents of StatusErr */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_Pos (4UL) /*!< Position of ERR field. */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_ERR_Pos) /*!< Bit mask of ERR field. */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_Min (0x0UL) /*!< Min enumerator value of ERR field. */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_Max (0x1UL) /*!< Max enumerator value of ERR field. */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_INT_STATUSINT_ERR_ACTIVE (0x1UL) /*!< (unspecified) */ + + + +/* ============================================= Struct I3CCORE_DMA_SWHANDSHAKE ============================================== */ +/** + * @brief SWHANDSHAKE [I3CCORE_DMA_SWHANDSHAKE] (unspecified) + */ +typedef struct { + __IOM uint32_t REQSRCREG; /*!< (@ 0x00000000) A bit is assigned for each channel in this register. */ + __IM uint32_t RESERVED; + __IOM uint32_t REQDSTREG; /*!< (@ 0x00000008) A bit is assigned for each channel in this register. */ + __IM uint32_t RESERVED1; + __IOM uint32_t SGLRQSRCREG; /*!< (@ 0x00000010) A bit is assigned for each channel in this register. */ + __IM uint32_t RESERVED2; + __IOM uint32_t SGLRQDSTREG; /*!< (@ 0x00000018) A bit is assigned for each channel in this register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t LSTSRCREG; /*!< (@ 0x00000020) A bit is assigned for each channel in this register. */ + __IM uint32_t RESERVED4; + __IOM uint32_t LSTDSTREG; /*!< (@ 0x00000028) A bit is assigned for each channel in this register. */ +} NRF_I3CCORE_DMA_SWHANDSHAKE_Type; /*!< Size = 44 (0x02C) */ + +/* I3CCORE_DMA_SWHANDSHAKE_REQSRCREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_ResetValue (0x00000000UL) /*!< Reset value of REQSRCREG register. */ + +/* SRCREQ @Bits 0..1 : Source Software Transaction Request */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Pos (0UL) /*!< Position of SRCREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Pos) /*!< Bit mask of + SRCREQ field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Min (0x0UL) /*!< Min enumerator value of SRCREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Max (0x1UL) /*!< Max enumerator value of SRCREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RSVDREQSRCREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Pos (2UL) /*!< Position of RSVDREQSRCREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Pos) + /*!< Bit mask of RSVDREQSRCREG field.*/ + +/* SRCREQWE @Bits 8..9 : Source Software Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Pos (8UL) /*!< Position of SRCREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Pos) /*!< Bit mask + of SRCREQWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Min (0x0UL) /*!< Min enumerator value of SRCREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Max (0x1UL) /*!< Max enumerator value of SRCREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_SWHANDSHAKE_REQDSTREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_ResetValue (0x00000000UL) /*!< Reset value of REQDSTREG register. */ + +/* DSTREQ @Bits 0..1 : Destination Software Transaction Request */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Pos (0UL) /*!< Position of DSTREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Pos) /*!< Bit mask of + DSTREQ field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Min (0x0UL) /*!< Min enumerator value of DSTREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Max (0x1UL) /*!< Max enumerator value of DSTREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RSVDREQDSTREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Pos (2UL) /*!< Position of RSVDREQDSTREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Pos) + /*!< Bit mask of RSVDREQDSTREG field.*/ + +/* DSTREQWE @Bits 8..9 : Destination Software Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Pos (8UL) /*!< Position of DSTREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Pos) /*!< Bit mask + of DSTREQWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Min (0x0UL) /*!< Min enumerator value of DSTREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Max (0x1UL) /*!< Max enumerator value of DSTREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_ResetValue (0x00000000UL) /*!< Reset value of SGLRQSRCREG register. */ + +/* SRCSGLREQ @Bits 0..1 : Source Single Transaction Request */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Pos (0UL) /*!< Position of SRCSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Pos) /*!< + Bit mask of SRCSGLREQ field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Min (0x0UL) /*!< Min enumerator value of SRCSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Max (0x1UL) /*!< Max enumerator value of SRCSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RSVDSGLRQSRCREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Pos (2UL) /*!< Position of RSVDSGLRQSRCREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Pos) + /*!< Bit mask of RSVDSGLRQSRCREG field.*/ + +/* SRCSGLREQWE @Bits 8..9 : Source Single Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Pos (8UL) /*!< Position of SRCSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Pos) + /*!< Bit mask of SRCSGLREQWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Min (0x0UL) /*!< Min enumerator value of SRCSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Max (0x1UL) /*!< Max enumerator value of SRCSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_ResetValue (0x00000000UL) /*!< Reset value of SGLRQDSTREG register. */ + +/* DSTSGLREQ @Bits 0..1 : Destination Single Transaction Request */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Pos (0UL) /*!< Position of DSTSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Pos) /*!< + Bit mask of DSTSGLREQ field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Min (0x0UL) /*!< Min enumerator value of DSTSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Max (0x1UL) /*!< Max enumerator value of DSTSGLREQ field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_INACTIVE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_ACTIVE (0x1UL) /*!< (unspecified) */ + +/* RSVDSGLRQDSTREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Pos (2UL) /*!< Position of RSVDSGLRQDSTREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Pos) + /*!< Bit mask of RSVDSGLRQDSTREG field.*/ + +/* DSTSGLREQWE @Bits 8..9 : Destination Single Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Pos (8UL) /*!< Position of DSTSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Pos) + /*!< Bit mask of DSTSGLREQWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Min (0x0UL) /*!< Min enumerator value of DSTSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Max (0x1UL) /*!< Max enumerator value of DSTSGLREQWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_ResetValue (0x00000000UL) /*!< Reset value of LSTSRCREG register. */ + +/* LSTSRC @Bits 0..1 : Source Last Transaction Request register */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Pos (0UL) /*!< Position of LSTSRC field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Pos) /*!< Bit mask of + LSTSRC field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Min (0x0UL) /*!< Min enumerator value of LSTSRC field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Max (0x1UL) /*!< Max enumerator value of LSTSRC field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_NOT_LAST (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_LAST (0x1UL) /*!< (unspecified) */ + +/* RSVDLSTSRCREG @Bits 2..7 : Reserved field- read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Pos (2UL) /*!< Position of RSVDLSTSRCREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Pos) + /*!< Bit mask of RSVDLSTSRCREG field.*/ + +/* LSTSRCWE @Bits 8..9 : Source Last Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Pos (8UL) /*!< Position of LSTSRCWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Pos) /*!< Bit mask + of LSTSRCWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Min (0x0UL) /*!< Min enumerator value of LSTSRCWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Max (0x1UL) /*!< Max enumerator value of LSTSRCWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG: A bit is assigned for each channel in this register. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_ResetValue (0x00000000UL) /*!< Reset value of LSTDSTREG register. */ + +/* LSTDST @Bits 0..1 : Destination Last Transaction Request */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Pos (0UL) /*!< Position of LSTDST field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Pos) /*!< Bit mask of + LSTDST field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Min (0x0UL) /*!< Min enumerator value of LSTDST field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Max (0x1UL) /*!< Max enumerator value of LSTDST field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_NOT_LAST (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_LAST (0x1UL) /*!< (unspecified) */ + +/* RSVDLSTDSTREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Pos (2UL) /*!< Position of RSVDLSTDSTREG field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Pos) + /*!< Bit mask of RSVDLSTDSTREG field.*/ + +/* LSTDSTWE @Bits 8..9 : Source Last Transaction Request write enable */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Pos (8UL) /*!< Position of LSTDSTWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Pos) /*!< Bit mask + of LSTDSTWE field.*/ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Min (0x0UL) /*!< Min enumerator value of LSTDSTWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Max (0x1UL) /*!< Max enumerator value of LSTDSTWE field. */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_ENABLED (0x1UL) /*!< (unspecified) */ + + + +/* ================================================= Struct I3CCORE_DMA_MISC ================================================= */ +/** + * @brief MISC [I3CCORE_DMA_MISC] (unspecified) + */ +typedef struct { + __IOM uint32_t DMACFGREG; /*!< (@ 0x00000000) This register is used to enable the DW_ahb_dmac, which + must be done before any channel activity can begin.*/ + __IM uint32_t RESERVED; + __IOM uint32_t CHENREG; /*!< (@ 0x00000008) This is the DW_ahb_dmac Channel Enable Register. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DMAIDREG; /*!< (@ 0x00000010) This is the DW_ahb_dmac ID register, which is a + read-only register that reads back the + coreConsultant-configured hardcoded ID number, + DMAH_ID_NUM.*/ + __IM uint32_t RESERVED2; + __IOM uint32_t DMATESTREG; /*!< (@ 0x00000018) This register is used to put the AHB slave interface + into test mode, during which the readback value of the + writable registers match the value written, assuming + the DW_ahb_dmac configuration has not optimized the + same registers.*/ + __IM uint32_t RESERVED3; + __IOM uint32_t DMALPTIMEOUTREG; /*!< (@ 0x00000020) This register holds the timeout value of Low Power + Counter.*/ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t DMACOMPPARAMS6L; /*!< (@ 0x00000034) DMA_COMP_PARAMS_6L is a constant read-only register + that contains encoded information about the component + parameter settings for Channel 7.*/ + __IOM uint32_t DMACOMPPARAMS5L; /*!< (@ 0x00000038) DMA_COMP_PARAMS_5 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 5 and Channel 6.*/ + __IOM uint32_t DMACOMPPARAMS5H; /*!< (@ 0x0000003C) DMA_COMP_PARAMS_5 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 5 and Channel 6.*/ + __IOM uint32_t DMACOMPPARAMS4L; /*!< (@ 0x00000040) DMA_COMP_PARAMS_4 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 3 and Channel 4.*/ + __IOM uint32_t DMACOMPPARAMS4H; /*!< (@ 0x00000044) DMA_COMP_PARAMS_4 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 3 and Channel 4.*/ + __IOM uint32_t DMACOMPPARAMS3L; /*!< (@ 0x00000048) DMA_COMP_PARAMS_3 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 1 and Channel 2.*/ + __IOM uint32_t DMACOMPPARAMS3H; /*!< (@ 0x0000004C) DMA_COMP_PARAMS_3 is a constant read-only register that + contains encoded information about the component + parameter settings for Channel 1 and Channel 2.*/ + __IOM uint32_t DMACOMPPARAMS2L; /*!< (@ 0x00000050) DMA_COMP_PARAMS_2 is a constant read-only register that + contains encoded information about the component + parameter settings.*/ + __IOM uint32_t DMACOMPPARAMS2H; /*!< (@ 0x00000054) DMA_COMP_PARAMS_2 is a constant read-only register that + contains encoded information about the component + parameter settings.*/ + __IOM uint32_t DMACOMPPARAMS1L; /*!< (@ 0x00000058) DMA_COMP_PARAMS_1 is a constant read-only register that + contains encoded information about the component + parameter settings.*/ + __IOM uint32_t DMACOMPPARAMS1H; /*!< (@ 0x0000005C) DMA_COMP_PARAMS_1 is a constant read-only register that + contains encoded information about the component + parameter settings.*/ + __IOM uint32_t DMACOMPSID0; /*!< (@ 0x00000060) This is the DW_ahb_dmac Component Version register, + which is a read-only register that specifies the + component type.*/ + __IOM uint32_t DMACOMPSID1; /*!< (@ 0x00000064) This is the DW_ahb_dmac Component Version register, + which is a read-only register that specifies the + version of the packaged component.*/ +} NRF_I3CCORE_DMA_MISC_Type; /*!< Size = 104 (0x068) */ + +/* I3CCORE_DMA_MISC_DMACFGREG: This register is used to enable the DW_ahb_dmac, which must be done before any channel activity + can begin. */ + + #define I3CCORE_DMA_MISC_DMACFGREG_ResetValue (0x00000000UL) /*!< Reset value of DMACFGREG register. */ + +/* DMAEN @Bit 0 : DW_ahb_dmac Enable bit. */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Pos (0UL) /*!< Position of DMAEN field. */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Pos) /*!< Bit mask of DMAEN field. */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Min (0x0UL) /*!< Min enumerator value of DMAEN field. */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Max (0x1UL) /*!< Max enumerator value of DMAEN field. */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_ENABLED (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_CHENREG: This is the DW_ahb_dmac Channel Enable Register. */ + #define I3CCORE_DMA_MISC_CHENREG_ResetValue (0x00000000UL) /*!< Reset value of CHENREG register. */ + +/* CHEN @Bits 0..1 : Channel Enable. */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_Pos (0UL) /*!< Position of CHEN field. */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_Msk (0x3UL << I3CCORE_DMA_MISC_CHENREG_CHEN_Pos) /*!< Bit mask of CHEN field. */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_Min (0x0UL) /*!< Min enumerator value of CHEN field. */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_Max (0x1UL) /*!< Max enumerator value of CHEN field. */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_DISABLED (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_CHENREG_CHEN_ENABLED (0x1UL) /*!< (unspecified) */ + +/* RSVDCHENREG @Bits 2..7 : Reserved field - read-only */ + #define I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Pos (2UL) /*!< Position of RSVDCHENREG field. */ + #define I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Msk (0x3FUL << I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Pos) /*!< Bit mask of + RSVDCHENREG field.*/ + +/* CHENWE @Bits 8..9 : Channel enable register */ + #define I3CCORE_DMA_MISC_CHENREG_CHENWE_Pos (8UL) /*!< Position of CHENWE field. */ + #define I3CCORE_DMA_MISC_CHENREG_CHENWE_Msk (0x3UL << I3CCORE_DMA_MISC_CHENREG_CHENWE_Pos) /*!< Bit mask of CHENWE field. */ + + +/* I3CCORE_DMA_MISC_DMAIDREG: This is the DW_ahb_dmac ID register, which is a read-only register that reads back the + coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. */ + + #define I3CCORE_DMA_MISC_DMAIDREG_ResetValue (0x00000000UL) /*!< Reset value of DMAIDREG register. */ + +/* DMAID @Bits 0..31 : Hardcoded DW_ahb_dmac peripheral ID. */ + #define I3CCORE_DMA_MISC_DMAIDREG_DMAID_Pos (0UL) /*!< Position of DMAID field. */ + #define I3CCORE_DMA_MISC_DMAIDREG_DMAID_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMAIDREG_DMAID_Pos) /*!< Bit mask of DMAID + field.*/ + + +/* I3CCORE_DMA_MISC_DMATESTREG: This register is used to put the AHB slave interface into test mode, during which the readback + value of the writable registers match the value written, assuming the DW_ahb_dmac configuration + has not optimized the same registers. */ + + #define I3CCORE_DMA_MISC_DMATESTREG_ResetValue (0x00000000UL) /*!< Reset value of DMATESTREG register. */ + +/* TESTSLVIF @Bit 0 : DMA Test register */ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Pos (0UL) /*!< Position of TESTSLVIF field. */ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Msk (0x1UL << I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Pos) /*!< Bit mask of + TESTSLVIF field.*/ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Min (0x0UL) /*!< Min enumerator value of TESTSLVIF field. */ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Max (0x1UL) /*!< Max enumerator value of TESTSLVIF field. */ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_NORMAL_MODE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_TEST_MODE (0x1UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMALPTIMEOUTREG: This register holds the timeout value of Low Power Counter. */ + #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_ResetValue (0x00000008UL) /*!< Reset value of DMALPTIMEOUTREG register. */ + +/* DMALPTIMEOUT @Bits 0..3 : This field holds timeout value of low power counter register. */ + #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Pos (0UL) /*!< Position of DMALPTIMEOUT field. */ + #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Msk (0xFUL << I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Pos) /*!< + Bit mask of DMALPTIMEOUT field.*/ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS6L: DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about + the component parameter settings for Channel 7. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS6L register. */ + +/* CH7DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Pos (0UL) /*!< Position of CH7DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Pos) /*!< Bit mask of + CH7DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Min (0x0UL) /*!< Min enumerator value of CH7DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Max (0x6UL) /*!< Max enumerator value of CH7DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_NO_HARDCODE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_256 (0x6UL) /*!< (unspecified) */ + +/* CH7STW @Bits 3..5 : The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Pos (3UL) /*!< Position of CH7STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Pos) /*!< Bit mask of + CH7STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Min (0x0UL) /*!< Min enumerator value of CH7STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Max (0x6UL) /*!< Max enumerator value of CH7STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_NO_HARDCODE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_256 (0x6UL) /*!< (unspecified) */ + +/* CH7STATDST @Bit 6 : The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Pos (6UL) /*!< Position of CH7STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Pos) /*!< Bit + mask of CH7STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Min (0x0UL) /*!< Min enumerator value of CH7STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Max (0x1UL) /*!< Max enumerator value of CH7STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Pos (7UL) /*!< Position of CH7STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Pos) /*!< Bit + mask of CH7STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Min (0x0UL) /*!< Min enumerator value of CH7STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Max (0x1UL) /*!< Max enumerator value of CH7STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Pos (8UL) /*!< Position of CH7DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Pos) /*!< Bit + mask of CH7DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH7DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH7DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Pos (9UL) /*!< Position of CH7SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Pos) /*!< Bit + mask of CH7SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH7SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH7SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Pos (10UL) /*!< Position of CH7LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Pos) /*!< Bit mask + of CH7LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH7LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH7LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Pos (11UL) /*!< Position of CH7MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Pos) /*!< + Bit mask of CH7MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH7MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH7MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Pos (12UL) /*!< Position of CH7CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Pos) /*!< Bit + mask of CH7CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH7CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH7CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH7HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Pos (13UL) /*!< Position of CH7HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Pos) /*!< Bit mask + of CH7HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Min (0x0UL) /*!< Min enumerator value of CH7HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Max (0x1UL) /*!< Max enumerator value of CH7HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH7FC @Bits 14..15 : The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Pos (14UL) /*!< Position of CH7FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Pos) /*!< Bit mask of + CH7FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Min (0x0UL) /*!< Min enumerator value of CH7FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Max (0x3UL) /*!< Max enumerator value of CH7FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH7MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Pos (16UL) /*!< Position of CH7MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Pos) + /*!< Bit mask of CH7MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH7MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH7MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH7DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Pos (19UL) /*!< Position of CH7DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Pos) /*!< Bit mask of + CH7DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Min (0x0UL) /*!< Min enumerator value of CH7DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Max (0x4UL) /*!< Max enumerator value of CH7DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH7LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Pos (22UL) /*!< Position of CH7LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Pos) /*!< Bit mask of + CH7LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Min (0x0UL) /*!< Min enumerator value of CH7LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Max (0x4UL) /*!< Max enumerator value of CH7LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH7SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Pos (25UL) /*!< Position of CH7SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Pos) /*!< Bit mask of + CH7SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Min (0x0UL) /*!< Min enumerator value of CH7SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Max (0x4UL) /*!< Max enumerator value of CH7SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH7FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Pos (28UL) /*!< Position of CH7FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Pos) /*!< + Bit mask of CH7FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH7FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH7FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS5L: DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 5 and Channel 6. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS5L register. */ + +/* CH6DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Pos (0UL) /*!< Position of CH6DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Pos) /*!< Bit mask of + CH6DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Min (0x0UL) /*!< Min enumerator value of CH6DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Max (0x6UL) /*!< Max enumerator value of CH6DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH6STW @Bits 3..5 : The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Pos (3UL) /*!< Position of CH6STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Pos) /*!< Bit mask of + CH6STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Min (0x0UL) /*!< Min enumerator value of CH6STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Max (0x6UL) /*!< Max enumerator value of CH6STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH6STATDST @Bit 6 : The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Pos (6UL) /*!< Position of CH6STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Pos) /*!< Bit + mask of CH6STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Min (0x0UL) /*!< Min enumerator value of CH6STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Max (0x1UL) /*!< Max enumerator value of CH6STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Pos (7UL) /*!< Position of CH6STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Pos) /*!< Bit + mask of CH6STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Min (0x0UL) /*!< Min enumerator value of CH6STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Max (0x1UL) /*!< Max enumerator value of CH6STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Pos (8UL) /*!< Position of CH6DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Pos) /*!< Bit + mask of CH6DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH6DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH6DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6SRCGATEN @Bit 9 : The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Pos (9UL) /*!< Position of CH6SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Pos) /*!< Bit + mask of CH6SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH6SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH6SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Pos (10UL) /*!< Position of CH6LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Pos) /*!< Bit mask + of CH6LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH6LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH6LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Pos (11UL) /*!< Position of CH6MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Pos) /*!< + Bit mask of CH6MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH6MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH6MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Pos (12UL) /*!< Position of CH6CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Pos) /*!< Bit + mask of CH6CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH6CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH6CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH6HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Pos (13UL) /*!< Position of CH6HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Pos) /*!< Bit mask + of CH6HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Min (0x0UL) /*!< Min enumerator value of CH6HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Max (0x1UL) /*!< Max enumerator value of CH6HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH6FC @Bits 14..15 : The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Pos (14UL) /*!< Position of CH6FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Pos) /*!< Bit mask of + CH6FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Min (0x0UL) /*!< Min enumerator value of CH6FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Max (0x3UL) /*!< Max enumerator value of CH6FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH6MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Pos (16UL) /*!< Position of CH6MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Pos) + /*!< Bit mask of CH6MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH6MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH6MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH6DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Pos (19UL) /*!< Position of CH6DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Pos) /*!< Bit mask of + CH6DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Min (0x0UL) /*!< Min enumerator value of CH6DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Max (0x4UL) /*!< Max enumerator value of CH6DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH6LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Pos (22UL) /*!< Position of CH6LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Pos) /*!< Bit mask of + CH6LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Min (0x0UL) /*!< Min enumerator value of CH6LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Max (0x4UL) /*!< Max enumerator value of CH6LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH6SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Pos (25UL) /*!< Position of CH6SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Pos) /*!< Bit mask of + CH6SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Min (0x0UL) /*!< Min enumerator value of CH6SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Max (0x4UL) /*!< Max enumerator value of CH6SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH6FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Pos (28UL) /*!< Position of CH6FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Pos) /*!< + Bit mask of CH6FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH6FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH6FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_IFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS5H: DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 5 and Channel 6. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS5H register. */ + +/* CH5DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Pos (0UL) /*!< Position of CH5DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Pos) /*!< Bit mask of + CH5DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Min (0x0UL) /*!< Min enumerator value of CH5DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Max (0x6UL) /*!< Max enumerator value of CH5DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH5STW @Bits 3..5 : The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Pos (3UL) /*!< Position of CH5STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Pos) /*!< Bit mask of + CH5STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Min (0x0UL) /*!< Min enumerator value of CH5STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Max (0x6UL) /*!< Max enumerator value of CH5STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH5STATDST @Bit 6 : The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Pos (6UL) /*!< Position of CH5STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Pos) /*!< Bit + mask of CH5STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Min (0x0UL) /*!< Min enumerator value of CH5STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Max (0x1UL) /*!< Max enumerator value of CH5STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Pos (7UL) /*!< Position of CH5STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Pos) /*!< Bit + mask of CH5STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Min (0x0UL) /*!< Min enumerator value of CH5STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Max (0x1UL) /*!< Max enumerator value of CH5STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Pos (8UL) /*!< Position of CH5DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Pos) /*!< Bit + mask of CH5DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH5DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH5DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Pos (9UL) /*!< Position of CH5SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Pos) /*!< Bit + mask of CH5SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH5SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH5SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Pos (10UL) /*!< Position of CH5LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Pos) /*!< Bit mask + of CH5LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH5LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH5LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Pos (11UL) /*!< Position of CH5MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Pos) /*!< + Bit mask of CH5MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH5MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH5MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Pos (12UL) /*!< Position of CH5CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Pos) /*!< Bit + mask of CH5CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH5CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH5CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH5HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Pos (13UL) /*!< Position of CH5HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Pos) /*!< Bit mask + of CH5HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Min (0x0UL) /*!< Min enumerator value of CH5HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Max (0x1UL) /*!< Max enumerator value of CH5HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH5FC @Bits 14..15 : The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Pos (14UL) /*!< Position of CH5FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Pos) /*!< Bit mask of + CH5FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Min (0x0UL) /*!< Min enumerator value of CH5FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Max (0x3UL) /*!< Max enumerator value of CH5FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH5MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Pos (16UL) /*!< Position of CH5MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Pos) + /*!< Bit mask of CH5MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH5MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH5MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH5DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Pos (19UL) /*!< Position of CH5DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Pos) /*!< Bit mask of + CH5DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Min (0x0UL) /*!< Min enumerator value of CH5DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Max (0x4UL) /*!< Max enumerator value of CH5DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH5LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Pos (22UL) /*!< Position of CH5LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Pos) /*!< Bit mask of + CH5LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Min (0x0UL) /*!< Min enumerator value of CH5LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Max (0x4UL) /*!< Max enumerator value of CH5LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH5SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Pos (25UL) /*!< Position of CH5SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Pos) /*!< Bit mask of + CH5SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Min (0x0UL) /*!< Min enumerator value of CH5SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Max (0x4UL) /*!< Max enumerator value of CH5SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH5FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Pos (28UL) /*!< Position of CH5FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Pos) /*!< + Bit mask of CH5FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH5FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH5FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS4L: DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 3 and Channel 4. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS4L register. */ + +/* CH4DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Pos (0UL) /*!< Position of CH4DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Pos) /*!< Bit mask of + CH4DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Min (0x0UL) /*!< Min enumerator value of CH4DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Max (0x6UL) /*!< Max enumerator value of CH4DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH4STW @Bits 3..5 : The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Pos (3UL) /*!< Position of CH4STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Pos) /*!< Bit mask of + CH4STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Min (0x0UL) /*!< Min enumerator value of CH4STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Max (0x6UL) /*!< Max enumerator value of CH4STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH4STATDST @Bit 6 : The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Pos (6UL) /*!< Position of CH4STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Pos) /*!< Bit + mask of CH4STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Min (0x0UL) /*!< Min enumerator value of CH4STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Max (0x1UL) /*!< Max enumerator value of CH4STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Pos (7UL) /*!< Position of CH4STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Pos) /*!< Bit + mask of CH4STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Min (0x0UL) /*!< Min enumerator value of CH4STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Max (0x1UL) /*!< Max enumerator value of CH4STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Pos (8UL) /*!< Position of CH4DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Pos) /*!< Bit + mask of CH4DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH4DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH4DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Pos (9UL) /*!< Position of CH4SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Pos) /*!< Bit + mask of CH4SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH4SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH4SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Pos (10UL) /*!< Position of CH4LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Pos) /*!< Bit mask + of CH4LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH4LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH4LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Pos (11UL) /*!< Position of CH4MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Pos) /*!< + Bit mask of CH4MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH4MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH4MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Pos (12UL) /*!< Position of CH4CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Pos) /*!< Bit + mask of CH4CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH4CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH4CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH4HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Pos (13UL) /*!< Position of CH4HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Pos) /*!< Bit mask + of CH4HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Min (0x0UL) /*!< Min enumerator value of CH4HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Max (0x1UL) /*!< Max enumerator value of CH4HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH4FC @Bits 14..15 : The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Pos (14UL) /*!< Position of CH4FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Pos) /*!< Bit mask of + CH4FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Min (0x0UL) /*!< Min enumerator value of CH4FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Max (0x3UL) /*!< Max enumerator value of CH4FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH4MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Pos (16UL) /*!< Position of CH4MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Pos) + /*!< Bit mask of CH4MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH4MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH4MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH4DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Pos (19UL) /*!< Position of CH4DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Pos) /*!< Bit mask of + CH4DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Min (0x0UL) /*!< Min enumerator value of CH4DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Max (0x4UL) /*!< Max enumerator value of CH4DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH4LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Pos (22UL) /*!< Position of CH4LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Pos) /*!< Bit mask of + CH4LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Min (0x0UL) /*!< Min enumerator value of CH4LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Max (0x4UL) /*!< Max enumerator value of CH4LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH4SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Pos (25UL) /*!< Position of CH4SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Pos) /*!< Bit mask of + CH4SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Min (0x0UL) /*!< Min enumerator value of CH4SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Max (0x4UL) /*!< Max enumerator value of CH4SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH4FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Pos (28UL) /*!< Position of CH4FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Pos) /*!< + Bit mask of CH4FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH4FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH4FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS4H: DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 3 and Channel 4. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS4H register. */ + +/* CH3DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Pos (0UL) /*!< Position of CH3DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Pos) /*!< Bit mask of + CH3DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Min (0x0UL) /*!< Min enumerator value of CH3DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Max (0x6UL) /*!< Max enumerator value of CH3DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH3STW @Bits 3..5 : The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Pos (3UL) /*!< Position of CH3STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Pos) /*!< Bit mask of + CH3STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Min (0x0UL) /*!< Min enumerator value of CH3STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Max (0x6UL) /*!< Max enumerator value of CH3STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH3STATDST @Bit 6 : The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Pos (6UL) /*!< Position of CH3STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Pos) /*!< Bit + mask of CH3STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Min (0x0UL) /*!< Min enumerator value of CH3STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Max (0x1UL) /*!< Max enumerator value of CH3STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Pos (7UL) /*!< Position of CH3STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Pos) /*!< Bit + mask of CH3STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Min (0x0UL) /*!< Min enumerator value of CH3STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Max (0x1UL) /*!< Max enumerator value of CH3STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Pos (8UL) /*!< Position of CH3DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Pos) /*!< Bit + mask of CH3DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH3DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH3DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Pos (9UL) /*!< Position of CH3SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Pos) /*!< Bit + mask of CH3SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH3SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH3SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Pos (10UL) /*!< Position of CH3LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Pos) /*!< Bit mask + of CH3LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH3LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH3LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Pos (11UL) /*!< Position of CH3MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Pos) /*!< + Bit mask of CH3MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH3MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH3MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Pos (12UL) /*!< Position of CH3CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Pos) /*!< Bit + mask of CH3CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH3CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH3CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH3HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Pos (13UL) /*!< Position of CH3HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Pos) /*!< Bit mask + of CH3HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Min (0x0UL) /*!< Min enumerator value of CH3HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Max (0x1UL) /*!< Max enumerator value of CH3HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH3FC @Bits 14..15 : The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Pos (14UL) /*!< Position of CH3FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Pos) /*!< Bit mask of + CH3FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Min (0x0UL) /*!< Min enumerator value of CH3FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Max (0x3UL) /*!< Max enumerator value of CH3FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH3MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Pos (16UL) /*!< Position of CH3MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Pos) + /*!< Bit mask of CH3MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH3MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH3MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH3DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Pos (19UL) /*!< Position of CH3DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Pos) /*!< Bit mask of + CH3DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Min (0x0UL) /*!< Min enumerator value of CH3DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Max (0x4UL) /*!< Max enumerator value of CH3DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH3LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Pos (22UL) /*!< Position of CH3LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Pos) /*!< Bit mask of + CH3LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Min (0x0UL) /*!< Min enumerator value of CH3LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Max (0x4UL) /*!< Max enumerator value of CH3LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH3SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Pos (25UL) /*!< Position of CH3SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Pos) /*!< Bit mask of + CH3SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Min (0x0UL) /*!< Min enumerator value of CH3SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Max (0x4UL) /*!< Max enumerator value of CH3SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH3FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Pos (28UL) /*!< Position of CH3FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Pos) /*!< + Bit mask of CH3FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH3FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH3FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS3L: DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 1 and Channel 2. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS3L register. */ + +/* CH2DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Pos (0UL) /*!< Position of CH2DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Pos) /*!< Bit mask of + CH2DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Min (0x0UL) /*!< Min enumerator value of CH2DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Max (0x6UL) /*!< Max enumerator value of CH2DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH2STW @Bits 3..5 : The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Pos (3UL) /*!< Position of CH2STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Pos) /*!< Bit mask of + CH2STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Min (0x0UL) /*!< Min enumerator value of CH2STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Max (0x6UL) /*!< Max enumerator value of CH2STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH2STATDST @Bit 6 : The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Pos (6UL) /*!< Position of CH2STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Pos) /*!< Bit + mask of CH2STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Min (0x0UL) /*!< Min enumerator value of CH2STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Max (0x1UL) /*!< Max enumerator value of CH2STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Pos (7UL) /*!< Position of CH2STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Pos) /*!< Bit + mask of CH2STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Min (0x0UL) /*!< Min enumerator value of CH2STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Max (0x1UL) /*!< Max enumerator value of CH2STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Pos (8UL) /*!< Position of CH2DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Pos) /*!< Bit + mask of CH2DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH2DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH2DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Pos (9UL) /*!< Position of CH2SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Pos) /*!< Bit + mask of CH2SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH2SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH2SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Pos (10UL) /*!< Position of CH2LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Pos) /*!< Bit mask + of CH2LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH2LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH2LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Pos (11UL) /*!< Position of CH2MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Pos) /*!< + Bit mask of CH2MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH2MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH2MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Pos (12UL) /*!< Position of CH2CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Pos) /*!< Bit + mask of CH2CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH2CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH2CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH2HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Pos (13UL) /*!< Position of CH2HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Pos) /*!< Bit mask + of CH2HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Min (0x0UL) /*!< Min enumerator value of CH2HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Max (0x1UL) /*!< Max enumerator value of CH2HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH2FC @Bits 14..15 : The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Pos (14UL) /*!< Position of CH2FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Pos) /*!< Bit mask of + CH2FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Min (0x0UL) /*!< Min enumerator value of CH2FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Max (0x3UL) /*!< Max enumerator value of CH2FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH2MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Pos (16UL) /*!< Position of CH2MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Pos) + /*!< Bit mask of CH2MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH2MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH2MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH2DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Pos (19UL) /*!< Position of CH2DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Pos) /*!< Bit mask of + CH2DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Min (0x0UL) /*!< Min enumerator value of CH2DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Max (0x4UL) /*!< Max enumerator value of CH2DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH2LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Pos (22UL) /*!< Position of CH2LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Pos) /*!< Bit mask of + CH2LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Min (0x0UL) /*!< Min enumerator value of CH2LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Max (0x4UL) /*!< Max enumerator value of CH2LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_PROGRAMMALE (0x4UL) /*!< (unspecified) */ + +/* CH2SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Pos (25UL) /*!< Position of CH2SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Pos) /*!< Bit mask of + CH2SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Min (0x0UL) /*!< Min enumerator value of CH2SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Max (0x4UL) /*!< Max enumerator value of CH2SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_PROGRAMMALE (0x4UL) /*!< (unspecified) */ + +/* CH2FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Pos (28UL) /*!< Position of CH2FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Pos) /*!< + Bit mask of CH2FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH2FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH2FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS3H: DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about + the component parameter settings for Channel 1 and Channel 2. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_ResetValue (0x1109A203UL) /*!< Reset value of DMACOMPPARAMS3H register. */ + +/* CH1DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Pos (0UL) /*!< Position of CH1DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Pos) /*!< Bit mask of + CH1DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Min (0x0UL) /*!< Min enumerator value of CH1DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Max (0x6UL) /*!< Max enumerator value of CH1DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH1STW @Bits 3..5 : The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Pos (3UL) /*!< Position of CH1STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Pos) /*!< Bit mask of + CH1STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Min (0x0UL) /*!< Min enumerator value of CH1STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Max (0x6UL) /*!< Max enumerator value of CH1STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH1STATDST @Bit 6 : The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Pos (6UL) /*!< Position of CH1STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Pos) /*!< Bit + mask of CH1STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Min (0x0UL) /*!< Min enumerator value of CH1STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Max (0x1UL) /*!< Max enumerator value of CH1STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Pos (7UL) /*!< Position of CH1STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Pos) /*!< Bit + mask of CH1STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Min (0x0UL) /*!< Min enumerator value of CH1STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Max (0x1UL) /*!< Max enumerator value of CH1STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Pos (8UL) /*!< Position of CH1DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Pos) /*!< Bit + mask of CH1DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH1DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH1DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Pos (9UL) /*!< Position of CH1SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Pos) /*!< Bit + mask of CH1SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH1SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH1SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Pos (10UL) /*!< Position of CH1LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Pos) /*!< Bit mask + of CH1LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH1LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH1LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Pos (11UL) /*!< Position of CH1MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Pos) /*!< + Bit mask of CH1MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH1MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH1MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Pos (12UL) /*!< Position of CH1CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Pos) /*!< Bit + mask of CH1CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH1CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH1CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH1HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Pos (13UL) /*!< Position of CH1HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Pos) /*!< Bit mask + of CH1HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Min (0x0UL) /*!< Min enumerator value of CH1HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Max (0x1UL) /*!< Max enumerator value of CH1HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH1FC @Bits 14..15 : The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Pos (14UL) /*!< Position of CH1FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Pos) /*!< Bit mask of + CH1FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Min (0x0UL) /*!< Min enumerator value of CH1FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Max (0x3UL) /*!< Max enumerator value of CH1FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH1MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Pos (16UL) /*!< Position of CH1MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Pos) + /*!< Bit mask of CH1MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH1MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH1MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH1DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Pos (19UL) /*!< Position of CH1DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Pos) /*!< Bit mask of + CH1DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Min (0x0UL) /*!< Min enumerator value of CH1DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Max (0x4UL) /*!< Max enumerator value of CH1DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH1LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Pos (22UL) /*!< Position of CH1LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Pos) /*!< Bit mask of + CH1LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Min (0x0UL) /*!< Min enumerator value of CH1LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Max (0x4UL) /*!< Max enumerator value of CH1LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH1SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Pos (25UL) /*!< Position of CH1SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Pos) /*!< Bit mask of + CH1SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Min (0x0UL) /*!< Min enumerator value of CH1SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Max (0x4UL) /*!< Max enumerator value of CH1SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH1FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Pos (28UL) /*!< Position of CH1FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Pos) /*!< + Bit mask of CH1FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH1FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH1FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS2L: DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about + the component parameter settings. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_ResetValue (0x13016118UL) /*!< Reset value of DMACOMPPARAMS2L register. */ + +/* CH0DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Pos (0UL) /*!< Position of CH0DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Pos) /*!< Bit mask of + CH0DTW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Min (0x0UL) /*!< Min enumerator value of CH0DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Max (0x6UL) /*!< Max enumerator value of CH0DTW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH0STW @Bits 3..5 : The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Pos (3UL) /*!< Position of CH0STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Pos) /*!< Bit mask of + CH0STW field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Min (0x0UL) /*!< Min enumerator value of CH0STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Max (0x6UL) /*!< Max enumerator value of CH0STW field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified) */ + +/* CH0STATDST @Bit 6 : The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Pos (6UL) /*!< Position of CH0STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Pos) /*!< Bit + mask of CH0STATDST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Min (0x0UL) /*!< Min enumerator value of CH0STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Max (0x1UL) /*!< Max enumerator value of CH0STATDST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Pos (7UL) /*!< Position of CH0STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Pos) /*!< Bit + mask of CH0STATSRC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Min (0x0UL) /*!< Min enumerator value of CH0STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Max (0x1UL) /*!< Max enumerator value of CH0STATSRC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Pos (8UL) /*!< Position of CH0DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Pos) /*!< Bit + mask of CH0DSTSCAEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH0DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH0DSTSCAEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Pos (9UL) /*!< Position of CH0SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Pos) /*!< Bit + mask of CH0SRCGATEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH0SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH0SRCGATEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Pos (10UL) /*!< Position of CH0LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Pos) /*!< Bit mask + of CH0LOCKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH0LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH0LOCKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Pos (11UL) /*!< Position of CH0MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Pos) /*!< + Bit mask of CH0MULTIBLKEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH0MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH0MULTIBLKEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Pos (12UL) /*!< Position of CH0CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Pos) /*!< Bit + mask of CH0CTLWBEN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH0CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH0CTLWBEN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_TRUE (0x1UL) /*!< (unspecified) */ + +/* CH0HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Pos (13UL) /*!< Position of CH0HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Pos) /*!< Bit mask + of CH0HCLLP field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Min (0x0UL) /*!< Min enumerator value of CH0HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Max (0x1UL) /*!< Max enumerator value of CH0HCLLP field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_HARDCODED (0x1UL) /*!< (unspecified) */ + +/* CH0FC @Bits 14..15 : The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Pos (14UL) /*!< Position of CH0FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Pos) /*!< Bit mask of + CH0FC field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Min (0x0UL) /*!< Min enumerator value of CH0FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Max (0x3UL) /*!< Max enumerator value of CH0FC field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_DMA (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_SRC (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_DST (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_ANY (0x3UL) /*!< (unspecified) */ + +/* CH0MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Pos (16UL) /*!< Position of CH0MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Pos) + /*!< Bit mask of CH0MAXMULTSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH0MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH0MAXMULTSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified) */ + +/* CH0DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Pos (19UL) /*!< Position of CH0DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Pos) /*!< Bit mask of + CH0DMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Min (0x0UL) /*!< Min enumerator value of CH0DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Max (0x4UL) /*!< Max enumerator value of CH0DMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH0LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Pos (22UL) /*!< Position of CH0LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Pos) /*!< Bit mask of + CH0LMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Min (0x0UL) /*!< Min enumerator value of CH0LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Max (0x4UL) /*!< Max enumerator value of CH0LMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH0SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Pos (25UL) /*!< Position of CH0SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Pos) /*!< Bit mask of + CH0SMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Min (0x0UL) /*!< Min enumerator value of CH0SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Max (0x4UL) /*!< Max enumerator value of CH0SMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified) */ + +/* CH0FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Pos (28UL) /*!< Position of CH0FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Pos) /*!< + Bit mask of CH0FIFODEPTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH0FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH0FIFODEPTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS2H: DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about + the component parameter settings. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS2H register. */ + +/* CHOMULTIBLKTYPE @Bits 0..3 : The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Pos (0UL) /*!< Position of CHOMULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Pos) + /*!< Bit mask of CHOMULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CHOMULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CHOMULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH1MULTIBLKTYPE @Bits 4..7 : The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Pos (4UL) /*!< Position of CH1MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Pos) + /*!< Bit mask of CH1MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH1MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH1MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH2MULTIBLKTYPE @Bits 8..11 : The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Pos (8UL) /*!< Position of CH2MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Pos) + /*!< Bit mask of CH2MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH2MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH2MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH3MULTIBLKTYPE @Bits 12..15 : The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Pos (12UL) /*!< Position of CH3MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Pos) + /*!< Bit mask of CH3MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH3MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH3MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH4MULTIBLKTYPE @Bits 16..19 : The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Pos (16UL) /*!< Position of CH4MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Pos) + /*!< Bit mask of CH4MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH4MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH4MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH5MULTIBLKTYPE @Bits 20..23 : The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Pos (20UL) /*!< Position of CH5MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Pos) + /*!< Bit mask of CH5MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH5MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH5MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH6MULTIBLKTYPE @Bits 24..27 : The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Pos (24UL) /*!< Position of CH6MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Pos) + /*!< Bit mask of CH6MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH6MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH6MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + +/* CH7MULTIBLKTYPE @Bits 28..31 : The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Pos (28UL) /*!< Position of CH7MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Pos) + /*!< Bit mask of CH7MULTIBLKTYPE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH7MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH7MULTIBLKTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS1L: DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about + the component parameter settings. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_ResetValue (0x33333333UL) /*!< Reset value of DMACOMPPARAMS1L register. */ + +/* CHOMAXBLKSIZE @Bits 0..3 : The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Pos (0UL) /*!< Position of CHOMAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Pos) /*!< + Bit mask of CHOMAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CHOMAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CHOMAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH1MAXBLKSIZE @Bits 4..7 : The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Pos (4UL) /*!< Position of CH1MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Pos) /*!< + Bit mask of CH1MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH1MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH1MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH2MAXBLKSIZE @Bits 8..11 : The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Pos (8UL) /*!< Position of CH2MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Pos) /*!< + Bit mask of CH2MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH2MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH2MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH3MAXBLKSIZE @Bits 12..15 : The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Pos (12UL) /*!< Position of CH3MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Pos) /*!< + Bit mask of CH3MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH3MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH3MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH4MAXBLKSIZE @Bits 16..19 : The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Pos (16UL) /*!< Position of CH4MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Pos) /*!< + Bit mask of CH4MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH4MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH4MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH5MAXBLKSIZE @Bits 20..23 : The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Pos (20UL) /*!< Position of CH5MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Pos) /*!< + Bit mask of CH5MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH5MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH5MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH6MAXBLKSIZE @Bits 24..27 : The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Pos (24UL) /*!< Position of CH6MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Pos) /*!< + Bit mask of CH6MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH6MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH6MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + +/* CH7MAXBLKSIZE @Bits 28..31 : The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Pos (28UL) /*!< Position of CH7MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Pos) /*!< + Bit mask of CH7MAXBLKSIZE field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH7MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH7MAXBLKSIZE field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified) */ + + +/* I3CCORE_DMA_MISC_DMACOMPPARAMS1H: DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about + the component parameter settings. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ResetValue (0x3120090CUL) /*!< Reset value of DMACOMPPARAMS1H register. */ + +/* BIGENDIAN @Bit 0 : The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Pos (0UL) /*!< Position of BIGENDIAN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Pos) /*!< Bit mask + of BIGENDIAN field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Min (0x0UL) /*!< Min enumerator value of BIGENDIAN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Max (0x1UL) /*!< Max enumerator value of BIGENDIAN field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_TRUE (0x1UL) /*!< (unspecified) */ + +/* INTRIO @Bits 1..2 : The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Pos (1UL) /*!< Position of INTRIO field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Pos) /*!< Bit mask of + INTRIO field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Min (0x0UL) /*!< Min enumerator value of INTRIO field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Max (0x2UL) /*!< Max enumerator value of INTRIO field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_ALL_INT (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_TYPE_INT (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_COMBINED_INT (0x2UL) /*!< (unspecified) */ + +/* MAXABRST @Bit 3 : The value of this register is derived from the DMAH_MABRST coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Pos (3UL) /*!< Position of MAXABRST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Pos) /*!< Bit mask + of MAXABRST field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Min (0x0UL) /*!< Min enumerator value of MAXABRST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Max (0x1UL) /*!< Max enumerator value of MAXABRST field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_TRUE (0x1UL) /*!< (unspecified) */ + +/* RSVDDMACOMPPARAMS1 @Bits 4..7 : Reserved field- read-only */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Pos (4UL) /*!< Position of RSVDDMACOMPPARAMS1 field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Pos) + /*!< Bit mask of RSVDDMACOMPPARAMS1 field.*/ + +/* NUMCHANNELS @Bits 8..10 : The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Pos (8UL) /*!< Position of NUMCHANNELS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Pos) /*!< Bit + mask of NUMCHANNELS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Min (0x0UL) /*!< Min enumerator value of NUMCHANNELS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Max (0x7UL) /*!< Max enumerator value of NUMCHANNELS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_4 (0x3UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_5 (0x4UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_6 (0x5UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_7 (0x6UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_8 (0x7UL) /*!< (unspecified) */ + +/* NUMMASTERINT @Bits 11..12 : The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Pos (11UL) /*!< Position of NUMMASTERINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Pos) /*!< + Bit mask of NUMMASTERINT field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Min (0x0UL) /*!< Min enumerator value of NUMMASTERINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Max (0x3UL) /*!< Max enumerator value of NUMMASTERINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_1 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_2 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_3 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_4 (0x3UL) /*!< (unspecified) */ + +/* SHDATAWIDTH @Bits 13..14 : The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Pos (13UL) /*!< Position of SHDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Pos) /*!< Bit + mask of SHDATAWIDTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of SHDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of SHDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified) */ + +/* M4HDATAWIDTH @Bits 15..16 : The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Pos (15UL) /*!< Position of M4HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Pos) /*!< + Bit mask of M4HDATAWIDTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M4HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M4HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified) */ + +/* M3HDATAWIDTH @Bits 17..18 : The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Pos (17UL) /*!< Position of M3HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Pos) /*!< + Bit mask of M3HDATAWIDTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M3HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M3HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified) */ + +/* M2HDATAWIDTH @Bits 19..20 : The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Pos (19UL) /*!< Position of M2HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Pos) /*!< + Bit mask of M2HDATAWIDTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M2HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M2HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified) */ + +/* M1HDATAWIDTH @Bits 21..22 : The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Pos (21UL) /*!< Position of M1HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Pos) /*!< + Bit mask of M1HDATAWIDTH field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M1HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M1HDATAWIDTH field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified) */ + +/* NUMHSINT @Bits 23..27 : The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Pos (23UL) /*!< Position of NUMHSINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Msk (0x1FUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Pos) /*!< Bit mask + of NUMHSINT field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Min (0x0UL) /*!< Min enumerator value of NUMHSINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Max (0x10UL) /*!< Max enumerator value of NUMHSINT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_0 (0x00UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_1 (0x01UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_2 (0x02UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_3 (0x03UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_4 (0x04UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_5 (0x05UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_6 (0x06UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_7 (0x07UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_8 (0x08UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_9 (0x09UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_a (0x0AUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_b (0x0BUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_c (0x0CUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_d (0x0DUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_e (0x0EUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_f (0x0FUL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_10 (0x10UL) /*!< (unspecified) */ + +/* ADDENCODEDPARAMS @Bit 28 : The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Pos (28UL) /*!< Position of ADDENCODEDPARAMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Pos) + /*!< Bit mask of ADDENCODEDPARAMS field.*/ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Min (0x0UL) /*!< Min enumerator value of ADDENCODEDPARAMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Max (0x1UL) /*!< Max enumerator value of ADDENCODEDPARAMS field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_FALSE (0x0UL) /*!< (unspecified) */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_TRUE (0x1UL) /*!< (unspecified) */ + +/* STATICENDIANSELECT @Bit 29 : The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant + parameter. */ + + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Pos (29UL) /*!< Position of STATICENDIANSELECT field. */ + #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Pos) + /*!< Bit mask of STATICENDIANSELECT field.*/ + + +/* I3CCORE_DMA_MISC_DMACOMPSID0: This is the DW_ahb_dmac Component Version register, which is a read-only register that + specifies the component type. */ + + #define I3CCORE_DMA_MISC_DMACOMPSID0_ResetValue (0x44571110UL) /*!< Reset value of DMACOMPSID0 register. */ + +/* DMACOMPTYPE @Bits 0..31 : DMA Component Type Number = `h44571110. */ + #define I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Pos (0UL) /*!< Position of DMACOMPTYPE field. */ + #define I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Pos) /*!< Bit + mask of DMACOMPTYPE field.*/ + + +/* I3CCORE_DMA_MISC_DMACOMPSID1: This is the DW_ahb_dmac Component Version register, which is a read-only register that + specifies the version of the packaged component. */ + + #define I3CCORE_DMA_MISC_DMACOMPSID1_ResetValue (0x3232322AUL) /*!< Reset value of DMACOMPSID1 register. */ + +/* DMACOMPVERSION @Bits 0..31 : DMA Component Version. */ + #define I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Pos (0UL) /*!< Position of DMACOMPVERSION field. */ + #define I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Pos) /*!< + Bit mask of DMACOMPVERSION field.*/ + + + +/* =================================================== Struct I3CCORE_DMA ==================================================== */ +/** + * @brief DMA [I3CCORE_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_I3CCORE_DMA_CH0_Type CH0; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED; + __IOM NRF_I3CCORE_DMA_CH1_Type CH1; /*!< (@ 0x00000058) (unspecified) */ + __IM uint32_t RESERVED1[135]; + __IOM NRF_I3CCORE_DMA_INT_Type INT; /*!< (@ 0x000002C0) (unspecified) */ + __IM uint32_t RESERVED2; + __IOM NRF_I3CCORE_DMA_SWHANDSHAKE_Type SWHANDSHAKE; /*!< (@ 0x00000368) (unspecified) */ + __IM uint32_t RESERVED3; + __IOM NRF_I3CCORE_DMA_MISC_Type MISC; /*!< (@ 0x00000398) (unspecified) */ +} NRF_I3CCORE_DMA_Type; /*!< Size = 1024 (0x400) */ + +/* ===================================================== Struct I3CCORE ====================================================== */ +/** + * @brief I3CCORE + */ + typedef struct { /*!< I3CCORE Structure */ + __IOM NRF_I3CCORE_CORE_Type CORE; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[390]; + __IOM NRF_I3CCORE_DMA_Type DMA; /*!< (@ 0x00000900) (unspecified) */ + } NRF_I3CCORE_Type; /*!< Size = 3328 (0xD00) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ICACHEDATA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================== Struct ICACHEDATA_SET_WAY_DU =============================================== */ +/** + * @brief DU [ICACHEDATA_SET_WAY_DU] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[2]; /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of + SET[n], WAY[o].*/ +} NRF_ICACHEDATA_SET_WAY_DU_Type; /*!< Size = 8 (0x008) */ + #define ICACHEDATA_SET_WAY_DU_MaxCount (4UL) /*!< Size of DU[4] array. */ + #define ICACHEDATA_SET_WAY_DU_MaxIndex (3UL) /*!< Max index of DU[4] array. */ + #define ICACHEDATA_SET_WAY_DU_MinIndex (0UL) /*!< Min index of DU[4] array. */ + +/* ICACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */ + #define ICACHEDATA_SET_WAY_DU_DATA_MaxCount (2UL) /*!< Max size of DATA[2] array. */ + #define ICACHEDATA_SET_WAY_DU_DATA_MaxIndex (1UL) /*!< Max index of DATA[2] array. */ + #define ICACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL) /*!< Min index of DATA[2] array. */ + #define ICACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[2] register. */ + +/* Data @Bits 0..31 : Data */ + #define ICACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL) /*!< Position of Data field. */ + #define ICACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << ICACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data + field.*/ + + + +/* ================================================ Struct ICACHEDATA_SET_WAY ================================================ */ +/** + * @brief WAY [ICACHEDATA_SET_WAY] (unspecified) + */ +typedef struct { + __IOM NRF_ICACHEDATA_SET_WAY_DU_Type DU[4]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_ICACHEDATA_SET_WAY_Type; /*!< Size = 32 (0x020) */ + #define ICACHEDATA_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define ICACHEDATA_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define ICACHEDATA_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + + +/* ================================================== Struct ICACHEDATA_SET ================================================== */ +/** + * @brief SET [ICACHEDATA_SET] (unspecified) + */ +typedef struct { + __IOM NRF_ICACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_ICACHEDATA_SET_Type; /*!< Size = 64 (0x040) */ + #define ICACHEDATA_SET_MaxCount (1024UL) /*!< Size of SET[1024] array. */ + #define ICACHEDATA_SET_MaxIndex (1023UL) /*!< Max index of SET[1024] array. */ + #define ICACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[1024] array. */ + +/* ==================================================== Struct ICACHEDATA ==================================================== */ +/** + * @brief CACHEDATA + */ + typedef struct { /*!< ICACHEDATA Structure */ + __IOM NRF_ICACHEDATA_SET_Type SET[1024]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_ICACHEDATA_Type; /*!< Size = 65536 (0x10000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ ICACHEINFO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct ICACHEINFO_SET_WAY ================================================ */ +/** + * @brief WAY [ICACHEINFO_SET_WAY] (unspecified) + */ +typedef struct { + __IOM uint32_t INFO; /*!< (@ 0x00000000) Cache information for SET[n], WAY[o]. */ +} NRF_ICACHEINFO_SET_WAY_Type; /*!< Size = 4 (0x004) */ + #define ICACHEINFO_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define ICACHEINFO_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define ICACHEINFO_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + +/* ICACHEINFO_SET_WAY_INFO: Cache information for SET[n], WAY[o]. */ + #define ICACHEINFO_SET_WAY_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* TAG @Bits 0..19 : Cache tag. */ + #define ICACHEINFO_SET_WAY_INFO_TAG_Pos (0UL) /*!< Position of TAG field. */ + #define ICACHEINFO_SET_WAY_INFO_TAG_Msk (0xFFFFFUL << ICACHEINFO_SET_WAY_INFO_TAG_Pos) /*!< Bit mask of TAG field. */ + +/* DUV0 @Bit 24 : Data unit valid info. */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Pos (24UL) /*!< Position of DUV0 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_DUV0_Pos) /*!< Bit mask of DUV0 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Min (0x0UL) /*!< Min enumerator value of DUV0 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Max (0x1UL) /*!< Max enumerator value of DUV0 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Invalid (0x0UL) /*!< Invalid data unit */ + #define ICACHEINFO_SET_WAY_INFO_DUV0_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV1 @Bit 25 : Data unit valid info. */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Pos (25UL) /*!< Position of DUV1 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_DUV1_Pos) /*!< Bit mask of DUV1 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Min (0x0UL) /*!< Min enumerator value of DUV1 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Max (0x1UL) /*!< Max enumerator value of DUV1 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Invalid (0x0UL) /*!< Invalid data unit */ + #define ICACHEINFO_SET_WAY_INFO_DUV1_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV2 @Bit 26 : Data unit valid info. */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Pos (26UL) /*!< Position of DUV2 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_DUV2_Pos) /*!< Bit mask of DUV2 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Min (0x0UL) /*!< Min enumerator value of DUV2 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Max (0x1UL) /*!< Max enumerator value of DUV2 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Invalid (0x0UL) /*!< Invalid data unit */ + #define ICACHEINFO_SET_WAY_INFO_DUV2_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV3 @Bit 27 : Data unit valid info. */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Pos (27UL) /*!< Position of DUV3 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_DUV3_Pos) /*!< Bit mask of DUV3 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Min (0x0UL) /*!< Min enumerator value of DUV3 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Max (0x1UL) /*!< Max enumerator value of DUV3 field. */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Invalid (0x0UL) /*!< Invalid data unit */ + #define ICACHEINFO_SET_WAY_INFO_DUV3_Valid (0x1UL) /*!< Valid data unit */ + +/* D0 @Bit 28 : Dirty status of combined data unit 0 and 1. */ + #define ICACHEINFO_SET_WAY_INFO_D0_Pos (28UL) /*!< Position of D0 field. */ + #define ICACHEINFO_SET_WAY_INFO_D0_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_D0_Pos) /*!< Bit mask of D0 field. */ + #define ICACHEINFO_SET_WAY_INFO_D0_Min (0x0UL) /*!< Min enumerator value of D0 field. */ + #define ICACHEINFO_SET_WAY_INFO_D0_Max (0x1UL) /*!< Max enumerator value of D0 field. */ + #define ICACHEINFO_SET_WAY_INFO_D0_Clean (0x0UL) /*!< Clean data unit */ + #define ICACHEINFO_SET_WAY_INFO_D0_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D1 @Bit 29 : Dirty status of combined data unit 2 and 3. */ + #define ICACHEINFO_SET_WAY_INFO_D1_Pos (29UL) /*!< Position of D1 field. */ + #define ICACHEINFO_SET_WAY_INFO_D1_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_D1_Pos) /*!< Bit mask of D1 field. */ + #define ICACHEINFO_SET_WAY_INFO_D1_Min (0x0UL) /*!< Min enumerator value of D1 field. */ + #define ICACHEINFO_SET_WAY_INFO_D1_Max (0x1UL) /*!< Max enumerator value of D1 field. */ + #define ICACHEINFO_SET_WAY_INFO_D1_Clean (0x0UL) /*!< Clean data unit */ + #define ICACHEINFO_SET_WAY_INFO_D1_Dirty (0x1UL) /*!< Dirty data unit */ + +/* V @Bit 30 : Line valid bit. */ + #define ICACHEINFO_SET_WAY_INFO_V_Pos (30UL) /*!< Position of V field. */ + #define ICACHEINFO_SET_WAY_INFO_V_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_V_Pos) /*!< Bit mask of V field. */ + #define ICACHEINFO_SET_WAY_INFO_V_Min (0x0UL) /*!< Min enumerator value of V field. */ + #define ICACHEINFO_SET_WAY_INFO_V_Max (0x1UL) /*!< Max enumerator value of V field. */ + #define ICACHEINFO_SET_WAY_INFO_V_Invalid (0x0UL) /*!< Invalid cache line */ + #define ICACHEINFO_SET_WAY_INFO_V_Valid (0x1UL) /*!< Valid cache line */ + +/* MRU @Bit 31 : Most recently used way. */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Pos (31UL) /*!< Position of MRU field. */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Msk (0x1UL << ICACHEINFO_SET_WAY_INFO_MRU_Pos) /*!< Bit mask of MRU field. */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Min (0x0UL) /*!< Min enumerator value of MRU field. */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Max (0x1UL) /*!< Max enumerator value of MRU field. */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Way0 (0x0UL) /*!< Way0 was most recently used */ + #define ICACHEINFO_SET_WAY_INFO_MRU_Way1 (0x1UL) /*!< Way1 was most recently used */ + + + +/* ================================================== Struct ICACHEINFO_SET ================================================== */ +/** + * @brief SET [ICACHEINFO_SET] (unspecified) + */ +typedef struct { + __IOM NRF_ICACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_ICACHEINFO_SET_Type; /*!< Size = 8 (0x008) */ + #define ICACHEINFO_SET_MaxCount (1024UL) /*!< Size of SET[1024] array. */ + #define ICACHEINFO_SET_MaxIndex (1023UL) /*!< Max index of SET[1024] array. */ + #define ICACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[1024] array. */ + +/* ==================================================== Struct ICACHEINFO ==================================================== */ +/** + * @brief CACHEINFO + */ + typedef struct { /*!< ICACHEINFO Structure */ + __IOM NRF_ICACHEINFO_SET_Type SET[1024]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_ICACHEINFO_Type; /*!< Size = 8192 (0x2000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ IPCT ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct IPCT_OVERFLOW =================================================== */ +/** + * @brief OVERFLOW [IPCT_OVERFLOW] (unspecified) + */ +typedef struct { + __IOM uint32_t SEND; /*!< (@ 0x00000000) Overflow status for SEND tasks Write 0 to clear */ +} NRF_IPCT_OVERFLOW_Type; /*!< Size = 4 (0x004) */ + +/* IPCT_OVERFLOW_SEND: Overflow status for SEND tasks Write 0 to clear */ + #define IPCT_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register. */ + +/* SEND0 @Bit 0 : Overflow status for SEND[0] task */ + #define IPCT_OVERFLOW_SEND_SEND0_Pos (0UL) /*!< Position of SEND0 field. */ + #define IPCT_OVERFLOW_SEND_SEND0_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field. */ + #define IPCT_OVERFLOW_SEND_SEND0_Min (0x0UL) /*!< Min enumerator value of SEND0 field. */ + #define IPCT_OVERFLOW_SEND_SEND0_Max (0x1UL) /*!< Max enumerator value of SEND0 field. */ + #define IPCT_OVERFLOW_SEND_SEND0_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND1 @Bit 1 : Overflow status for SEND[1] task */ + #define IPCT_OVERFLOW_SEND_SEND1_Pos (1UL) /*!< Position of SEND1 field. */ + #define IPCT_OVERFLOW_SEND_SEND1_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field. */ + #define IPCT_OVERFLOW_SEND_SEND1_Min (0x0UL) /*!< Min enumerator value of SEND1 field. */ + #define IPCT_OVERFLOW_SEND_SEND1_Max (0x1UL) /*!< Max enumerator value of SEND1 field. */ + #define IPCT_OVERFLOW_SEND_SEND1_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND2 @Bit 2 : Overflow status for SEND[2] task */ + #define IPCT_OVERFLOW_SEND_SEND2_Pos (2UL) /*!< Position of SEND2 field. */ + #define IPCT_OVERFLOW_SEND_SEND2_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field. */ + #define IPCT_OVERFLOW_SEND_SEND2_Min (0x0UL) /*!< Min enumerator value of SEND2 field. */ + #define IPCT_OVERFLOW_SEND_SEND2_Max (0x1UL) /*!< Max enumerator value of SEND2 field. */ + #define IPCT_OVERFLOW_SEND_SEND2_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND3 @Bit 3 : Overflow status for SEND[3] task */ + #define IPCT_OVERFLOW_SEND_SEND3_Pos (3UL) /*!< Position of SEND3 field. */ + #define IPCT_OVERFLOW_SEND_SEND3_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field. */ + #define IPCT_OVERFLOW_SEND_SEND3_Min (0x0UL) /*!< Min enumerator value of SEND3 field. */ + #define IPCT_OVERFLOW_SEND_SEND3_Max (0x1UL) /*!< Max enumerator value of SEND3 field. */ + #define IPCT_OVERFLOW_SEND_SEND3_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND4 @Bit 4 : Overflow status for SEND[4] task */ + #define IPCT_OVERFLOW_SEND_SEND4_Pos (4UL) /*!< Position of SEND4 field. */ + #define IPCT_OVERFLOW_SEND_SEND4_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field. */ + #define IPCT_OVERFLOW_SEND_SEND4_Min (0x0UL) /*!< Min enumerator value of SEND4 field. */ + #define IPCT_OVERFLOW_SEND_SEND4_Max (0x1UL) /*!< Max enumerator value of SEND4 field. */ + #define IPCT_OVERFLOW_SEND_SEND4_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND5 @Bit 5 : Overflow status for SEND[5] task */ + #define IPCT_OVERFLOW_SEND_SEND5_Pos (5UL) /*!< Position of SEND5 field. */ + #define IPCT_OVERFLOW_SEND_SEND5_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field. */ + #define IPCT_OVERFLOW_SEND_SEND5_Min (0x0UL) /*!< Min enumerator value of SEND5 field. */ + #define IPCT_OVERFLOW_SEND_SEND5_Max (0x1UL) /*!< Max enumerator value of SEND5 field. */ + #define IPCT_OVERFLOW_SEND_SEND5_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND6 @Bit 6 : Overflow status for SEND[6] task */ + #define IPCT_OVERFLOW_SEND_SEND6_Pos (6UL) /*!< Position of SEND6 field. */ + #define IPCT_OVERFLOW_SEND_SEND6_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field. */ + #define IPCT_OVERFLOW_SEND_SEND6_Min (0x0UL) /*!< Min enumerator value of SEND6 field. */ + #define IPCT_OVERFLOW_SEND_SEND6_Max (0x1UL) /*!< Max enumerator value of SEND6 field. */ + #define IPCT_OVERFLOW_SEND_SEND6_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND7 @Bit 7 : Overflow status for SEND[7] task */ + #define IPCT_OVERFLOW_SEND_SEND7_Pos (7UL) /*!< Position of SEND7 field. */ + #define IPCT_OVERFLOW_SEND_SEND7_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field. */ + #define IPCT_OVERFLOW_SEND_SEND7_Min (0x0UL) /*!< Min enumerator value of SEND7 field. */ + #define IPCT_OVERFLOW_SEND_SEND7_Max (0x1UL) /*!< Max enumerator value of SEND7 field. */ + #define IPCT_OVERFLOW_SEND_SEND7_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND8 @Bit 8 : Overflow status for SEND[8] task */ + #define IPCT_OVERFLOW_SEND_SEND8_Pos (8UL) /*!< Position of SEND8 field. */ + #define IPCT_OVERFLOW_SEND_SEND8_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field. */ + #define IPCT_OVERFLOW_SEND_SEND8_Min (0x0UL) /*!< Min enumerator value of SEND8 field. */ + #define IPCT_OVERFLOW_SEND_SEND8_Max (0x1UL) /*!< Max enumerator value of SEND8 field. */ + #define IPCT_OVERFLOW_SEND_SEND8_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND9 @Bit 9 : Overflow status for SEND[9] task */ + #define IPCT_OVERFLOW_SEND_SEND9_Pos (9UL) /*!< Position of SEND9 field. */ + #define IPCT_OVERFLOW_SEND_SEND9_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field. */ + #define IPCT_OVERFLOW_SEND_SEND9_Min (0x0UL) /*!< Min enumerator value of SEND9 field. */ + #define IPCT_OVERFLOW_SEND_SEND9_Max (0x1UL) /*!< Max enumerator value of SEND9 field. */ + #define IPCT_OVERFLOW_SEND_SEND9_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND10 @Bit 10 : Overflow status for SEND[10] task */ + #define IPCT_OVERFLOW_SEND_SEND10_Pos (10UL) /*!< Position of SEND10 field. */ + #define IPCT_OVERFLOW_SEND_SEND10_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field. */ + #define IPCT_OVERFLOW_SEND_SEND10_Min (0x0UL) /*!< Min enumerator value of SEND10 field. */ + #define IPCT_OVERFLOW_SEND_SEND10_Max (0x1UL) /*!< Max enumerator value of SEND10 field. */ + #define IPCT_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND11 @Bit 11 : Overflow status for SEND[11] task */ + #define IPCT_OVERFLOW_SEND_SEND11_Pos (11UL) /*!< Position of SEND11 field. */ + #define IPCT_OVERFLOW_SEND_SEND11_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field. */ + #define IPCT_OVERFLOW_SEND_SEND11_Min (0x0UL) /*!< Min enumerator value of SEND11 field. */ + #define IPCT_OVERFLOW_SEND_SEND11_Max (0x1UL) /*!< Max enumerator value of SEND11 field. */ + #define IPCT_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND12 @Bit 12 : Overflow status for SEND[12] task */ + #define IPCT_OVERFLOW_SEND_SEND12_Pos (12UL) /*!< Position of SEND12 field. */ + #define IPCT_OVERFLOW_SEND_SEND12_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field. */ + #define IPCT_OVERFLOW_SEND_SEND12_Min (0x0UL) /*!< Min enumerator value of SEND12 field. */ + #define IPCT_OVERFLOW_SEND_SEND12_Max (0x1UL) /*!< Max enumerator value of SEND12 field. */ + #define IPCT_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND13 @Bit 13 : Overflow status for SEND[13] task */ + #define IPCT_OVERFLOW_SEND_SEND13_Pos (13UL) /*!< Position of SEND13 field. */ + #define IPCT_OVERFLOW_SEND_SEND13_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field. */ + #define IPCT_OVERFLOW_SEND_SEND13_Min (0x0UL) /*!< Min enumerator value of SEND13 field. */ + #define IPCT_OVERFLOW_SEND_SEND13_Max (0x1UL) /*!< Max enumerator value of SEND13 field. */ + #define IPCT_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND14 @Bit 14 : Overflow status for SEND[14] task */ + #define IPCT_OVERFLOW_SEND_SEND14_Pos (14UL) /*!< Position of SEND14 field. */ + #define IPCT_OVERFLOW_SEND_SEND14_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field. */ + #define IPCT_OVERFLOW_SEND_SEND14_Min (0x0UL) /*!< Min enumerator value of SEND14 field. */ + #define IPCT_OVERFLOW_SEND_SEND14_Max (0x1UL) /*!< Max enumerator value of SEND14 field. */ + #define IPCT_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + +/* SEND15 @Bit 15 : Overflow status for SEND[15] task */ + #define IPCT_OVERFLOW_SEND_SEND15_Pos (15UL) /*!< Position of SEND15 field. */ + #define IPCT_OVERFLOW_SEND_SEND15_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field. */ + #define IPCT_OVERFLOW_SEND_SEND15_Min (0x0UL) /*!< Min enumerator value of SEND15 field. */ + #define IPCT_OVERFLOW_SEND_SEND15_Max (0x1UL) /*!< Max enumerator value of SEND15 field. */ + #define IPCT_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow has happened */ + #define IPCT_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow has not happened */ + + +/* ======================================================= Struct IPCT ======================================================= */ +/** + * @brief IPCT APB registers + */ + typedef struct { /*!< IPCT Structure */ + __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Trigger event on IPCT source channel n if there are no + active signals present on that channel*/ + __OM uint32_t TASKS_FLUSH[16]; /*!< (@ 0x00000040) Flush IPCT sink channel n. Any pending IPCT signal on + that channel will re-trigger the RECEIVE[n] event. The + flush can happen automatically by configuring the + SHORTS register accordingly.*/ + __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Subscribe configuration for task SEND[n] */ + __IOM uint32_t SUBSCRIBE_FLUSH[16]; /*!< (@ 0x000000C0) Subscribe configuration for task FLUSH[n] */ + __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Event received on IPCT sink channel n */ + __IOM uint32_t EVENTS_READY[16]; /*!< (@ 0x00000140) Event received when hardware handshake of SEND task for + IPCT source channel n is complete and a new signal can + be triggered on that channel.*/ + __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n] */ + __IOM uint32_t PUBLISH_READY[16]; /*!< (@ 0x000001C0) Publish configuration for event READY[n] */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t INTEN0; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET0; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR0; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND0; /*!< (@ 0x0000030C) Pending interrupts */ + __IOM uint32_t INTEN1; /*!< (@ 0x00000310) Enable or disable interrupt */ + __IOM uint32_t INTENSET1; /*!< (@ 0x00000314) Enable interrupt */ + __IOM uint32_t INTENCLR1; /*!< (@ 0x00000318) Disable interrupt */ + __IM uint32_t INTPEND1; /*!< (@ 0x0000031C) Pending interrupts */ + __IOM uint32_t INTEN2; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t INTENSET2; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t INTENCLR2; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t INTPEND2; /*!< (@ 0x0000032C) Pending interrupts */ + __IOM uint32_t INTEN3; /*!< (@ 0x00000330) Enable or disable interrupt */ + __IOM uint32_t INTENSET3; /*!< (@ 0x00000334) Enable interrupt */ + __IOM uint32_t INTENCLR3; /*!< (@ 0x00000338) Disable interrupt */ + __IM uint32_t INTPEND3; /*!< (@ 0x0000033C) Pending interrupts */ + __IOM uint32_t INTEN4; /*!< (@ 0x00000340) Enable or disable interrupt */ + __IOM uint32_t INTENSET4; /*!< (@ 0x00000344) Enable interrupt */ + __IOM uint32_t INTENCLR4; /*!< (@ 0x00000348) Disable interrupt */ + __IM uint32_t INTPEND4; /*!< (@ 0x0000034C) Pending interrupts */ + __IOM uint32_t INTEN5; /*!< (@ 0x00000350) Enable or disable interrupt */ + __IOM uint32_t INTENSET5; /*!< (@ 0x00000354) Enable interrupt */ + __IOM uint32_t INTENCLR5; /*!< (@ 0x00000358) Disable interrupt */ + __IM uint32_t INTPEND5; /*!< (@ 0x0000035C) Pending interrupts */ + __IOM uint32_t INTEN6; /*!< (@ 0x00000360) Enable or disable interrupt */ + __IOM uint32_t INTENSET6; /*!< (@ 0x00000364) Enable interrupt */ + __IOM uint32_t INTENCLR6; /*!< (@ 0x00000368) Disable interrupt */ + __IM uint32_t INTPEND6; /*!< (@ 0x0000036C) Pending interrupts */ + __IOM uint32_t INTEN7; /*!< (@ 0x00000370) Enable or disable interrupt */ + __IOM uint32_t INTENSET7; /*!< (@ 0x00000374) Enable interrupt */ + __IOM uint32_t INTENCLR7; /*!< (@ 0x00000378) Disable interrupt */ + __IM uint32_t INTPEND7; /*!< (@ 0x0000037C) Pending interrupts */ + __IM uint32_t RESERVED1[32]; + __IOM NRF_IPCT_OVERFLOW_Type OVERFLOW; /*!< (@ 0x00000400) (unspecified) */ + } NRF_IPCT_Type; /*!< Size = 1028 (0x404) */ + +/* IPCT_TASKS_SEND: Trigger event on IPCT source channel n if there are no active signals present on that channel */ + #define IPCT_TASKS_SEND_MaxCount (16UL) /*!< Max size of TASKS_SEND[16] array. */ + #define IPCT_TASKS_SEND_MaxIndex (15UL) /*!< Max index of TASKS_SEND[16] array. */ + #define IPCT_TASKS_SEND_MinIndex (0UL) /*!< Min index of TASKS_SEND[16] array. */ + #define IPCT_TASKS_SEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SEND[16] register. */ + +/* TASKS_SEND @Bit 0 : Trigger event on IPCT source channel n if there are no active signals present on that channel */ + #define IPCT_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ + #define IPCT_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPCT_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ + #define IPCT_TASKS_SEND_TASKS_SEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SEND field. */ + #define IPCT_TASKS_SEND_TASKS_SEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SEND field. */ + #define IPCT_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* IPCT_TASKS_FLUSH: Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event. + The flush can happen automatically by configuring the SHORTS register accordingly. */ + + #define IPCT_TASKS_FLUSH_MaxCount (16UL) /*!< Max size of TASKS_FLUSH[16] array. */ + #define IPCT_TASKS_FLUSH_MaxIndex (15UL) /*!< Max index of TASKS_FLUSH[16] array. */ + #define IPCT_TASKS_FLUSH_MinIndex (0UL) /*!< Min index of TASKS_FLUSH[16] array. */ + #define IPCT_TASKS_FLUSH_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSH[16] register. */ + +/* TASKS_FLUSH @Bit 0 : Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event. + The flush can happen automatically by configuring the SHORTS register accordingly. */ + + #define IPCT_TASKS_FLUSH_TASKS_FLUSH_Pos (0UL) /*!< Position of TASKS_FLUSH field. */ + #define IPCT_TASKS_FLUSH_TASKS_FLUSH_Msk (0x1UL << IPCT_TASKS_FLUSH_TASKS_FLUSH_Pos) /*!< Bit mask of TASKS_FLUSH field. */ + #define IPCT_TASKS_FLUSH_TASKS_FLUSH_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSH field. */ + #define IPCT_TASKS_FLUSH_TASKS_FLUSH_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSH field. */ + #define IPCT_TASKS_FLUSH_TASKS_FLUSH_Trigger (0x1UL) /*!< Trigger task */ + + +/* IPCT_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */ + #define IPCT_SUBSCRIBE_SEND_MaxCount (16UL) /*!< Max size of SUBSCRIBE_SEND[16] array. */ + #define IPCT_SUBSCRIBE_SEND_MaxIndex (15UL) /*!< Max index of SUBSCRIBE_SEND[16] array. */ + #define IPCT_SUBSCRIBE_SEND_MinIndex (0UL) /*!< Min index of SUBSCRIBE_SEND[16] array. */ + #define IPCT_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */ + #define IPCT_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define IPCT_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPCT_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define IPCT_SUBSCRIBE_SEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define IPCT_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define IPCT_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define IPCT_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPCT_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ + #define IPCT_SUBSCRIBE_SEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define IPCT_SUBSCRIBE_SEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define IPCT_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define IPCT_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* IPCT_SUBSCRIBE_FLUSH: Subscribe configuration for task FLUSH[n] */ + #define IPCT_SUBSCRIBE_FLUSH_MaxCount (16UL) /*!< Max size of SUBSCRIBE_FLUSH[16] array. */ + #define IPCT_SUBSCRIBE_FLUSH_MaxIndex (15UL) /*!< Max index of SUBSCRIBE_FLUSH[16] array. */ + #define IPCT_SUBSCRIBE_FLUSH_MinIndex (0UL) /*!< Min index of SUBSCRIBE_FLUSH[16] array. */ + #define IPCT_SUBSCRIBE_FLUSH_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_FLUSH[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task FLUSH[n] will subscribe to */ + #define IPCT_SUBSCRIBE_FLUSH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define IPCT_SUBSCRIBE_FLUSH_CHIDX_Msk (0xFFUL << IPCT_SUBSCRIBE_FLUSH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define IPCT_SUBSCRIBE_FLUSH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define IPCT_SUBSCRIBE_FLUSH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Pos (31UL) /*!< Position of EN field. */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Msk (0x1UL << IPCT_SUBSCRIBE_FLUSH_EN_Pos) /*!< Bit mask of EN field. */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define IPCT_SUBSCRIBE_FLUSH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* IPCT_EVENTS_RECEIVE: Event received on IPCT sink channel n */ + #define IPCT_EVENTS_RECEIVE_MaxCount (16UL) /*!< Max size of EVENTS_RECEIVE[16] array. */ + #define IPCT_EVENTS_RECEIVE_MaxIndex (15UL) /*!< Max index of EVENTS_RECEIVE[16] array. */ + #define IPCT_EVENTS_RECEIVE_MinIndex (0UL) /*!< Min index of EVENTS_RECEIVE[16] array. */ + #define IPCT_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[16] register. */ + +/* EVENTS_RECEIVE @Bit 0 : Event received on IPCT sink channel n */ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of + EVENTS_RECEIVE field.*/ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field. */ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field. */ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */ + #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */ + + +/* IPCT_EVENTS_READY: Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new signal + can be triggered on that channel. */ + + #define IPCT_EVENTS_READY_MaxCount (16UL) /*!< Max size of EVENTS_READY[16] array. */ + #define IPCT_EVENTS_READY_MaxIndex (15UL) /*!< Max index of EVENTS_READY[16] array. */ + #define IPCT_EVENTS_READY_MinIndex (0UL) /*!< Min index of EVENTS_READY[16] array. */ + #define IPCT_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY[16] register. */ + +/* EVENTS_READY @Bit 0 : Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new + signal can be triggered on that channel. */ + + #define IPCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define IPCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << IPCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/ + #define IPCT_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define IPCT_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define IPCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define IPCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* IPCT_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */ + #define IPCT_PUBLISH_RECEIVE_MaxCount (16UL) /*!< Max size of PUBLISH_RECEIVE[16] array. */ + #define IPCT_PUBLISH_RECEIVE_MaxIndex (15UL) /*!< Max index of PUBLISH_RECEIVE[16] array. */ + #define IPCT_PUBLISH_RECEIVE_MinIndex (0UL) /*!< Min index of PUBLISH_RECEIVE[16] array. */ + #define IPCT_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */ + #define IPCT_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define IPCT_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPCT_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define IPCT_PUBLISH_RECEIVE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define IPCT_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define IPCT_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ + #define IPCT_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPCT_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ + #define IPCT_PUBLISH_RECEIVE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define IPCT_PUBLISH_RECEIVE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define IPCT_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define IPCT_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* IPCT_PUBLISH_READY: Publish configuration for event READY[n] */ + #define IPCT_PUBLISH_READY_MaxCount (16UL) /*!< Max size of PUBLISH_READY[16] array. */ + #define IPCT_PUBLISH_READY_MaxIndex (15UL) /*!< Max index of PUBLISH_READY[16] array. */ + #define IPCT_PUBLISH_READY_MinIndex (0UL) /*!< Min index of PUBLISH_READY[16] array. */ + #define IPCT_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY[16] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY[n] will publish to */ + #define IPCT_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define IPCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << IPCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define IPCT_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define IPCT_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define IPCT_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define IPCT_PUBLISH_READY_EN_Msk (0x1UL << IPCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define IPCT_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define IPCT_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define IPCT_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define IPCT_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* IPCT_SHORTS: Shortcuts between local events and tasks */ + #define IPCT_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* RECEIVE0_FLUSH0 @Bit 0 : Shortcut between event RECEIVE[0] and task FLUSH[0] */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Pos (0UL) /*!< Position of RECEIVE0_FLUSH0 field. */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Msk (0x1UL << IPCT_SHORTS_RECEIVE0_FLUSH0_Pos) /*!< Bit mask of RECEIVE0_FLUSH0 field. */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0_FLUSH0 field. */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0_FLUSH0 field. */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE0_FLUSH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE1_FLUSH1 @Bit 1 : Shortcut between event RECEIVE[1] and task FLUSH[1] */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Pos (1UL) /*!< Position of RECEIVE1_FLUSH1 field. */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Msk (0x1UL << IPCT_SHORTS_RECEIVE1_FLUSH1_Pos) /*!< Bit mask of RECEIVE1_FLUSH1 field. */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1_FLUSH1 field. */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1_FLUSH1 field. */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE1_FLUSH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE2_FLUSH2 @Bit 2 : Shortcut between event RECEIVE[2] and task FLUSH[2] */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Pos (2UL) /*!< Position of RECEIVE2_FLUSH2 field. */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Msk (0x1UL << IPCT_SHORTS_RECEIVE2_FLUSH2_Pos) /*!< Bit mask of RECEIVE2_FLUSH2 field. */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2_FLUSH2 field. */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2_FLUSH2 field. */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE2_FLUSH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE3_FLUSH3 @Bit 3 : Shortcut between event RECEIVE[3] and task FLUSH[3] */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Pos (3UL) /*!< Position of RECEIVE3_FLUSH3 field. */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Msk (0x1UL << IPCT_SHORTS_RECEIVE3_FLUSH3_Pos) /*!< Bit mask of RECEIVE3_FLUSH3 field. */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3_FLUSH3 field. */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3_FLUSH3 field. */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE3_FLUSH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE4_FLUSH4 @Bit 4 : Shortcut between event RECEIVE[4] and task FLUSH[4] */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Pos (4UL) /*!< Position of RECEIVE4_FLUSH4 field. */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Msk (0x1UL << IPCT_SHORTS_RECEIVE4_FLUSH4_Pos) /*!< Bit mask of RECEIVE4_FLUSH4 field. */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4_FLUSH4 field. */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4_FLUSH4 field. */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE4_FLUSH4_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE5_FLUSH5 @Bit 5 : Shortcut between event RECEIVE[5] and task FLUSH[5] */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Pos (5UL) /*!< Position of RECEIVE5_FLUSH5 field. */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Msk (0x1UL << IPCT_SHORTS_RECEIVE5_FLUSH5_Pos) /*!< Bit mask of RECEIVE5_FLUSH5 field. */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5_FLUSH5 field. */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5_FLUSH5 field. */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE5_FLUSH5_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE6_FLUSH6 @Bit 6 : Shortcut between event RECEIVE[6] and task FLUSH[6] */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Pos (6UL) /*!< Position of RECEIVE6_FLUSH6 field. */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Msk (0x1UL << IPCT_SHORTS_RECEIVE6_FLUSH6_Pos) /*!< Bit mask of RECEIVE6_FLUSH6 field. */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6_FLUSH6 field. */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6_FLUSH6 field. */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE6_FLUSH6_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE7_FLUSH7 @Bit 7 : Shortcut between event RECEIVE[7] and task FLUSH[7] */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Pos (7UL) /*!< Position of RECEIVE7_FLUSH7 field. */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Msk (0x1UL << IPCT_SHORTS_RECEIVE7_FLUSH7_Pos) /*!< Bit mask of RECEIVE7_FLUSH7 field. */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7_FLUSH7 field. */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7_FLUSH7 field. */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE7_FLUSH7_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE8_FLUSH8 @Bit 8 : Shortcut between event RECEIVE[8] and task FLUSH[8] */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Pos (8UL) /*!< Position of RECEIVE8_FLUSH8 field. */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Msk (0x1UL << IPCT_SHORTS_RECEIVE8_FLUSH8_Pos) /*!< Bit mask of RECEIVE8_FLUSH8 field. */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8_FLUSH8 field. */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8_FLUSH8 field. */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE8_FLUSH8_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE9_FLUSH9 @Bit 9 : Shortcut between event RECEIVE[9] and task FLUSH[9] */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Pos (9UL) /*!< Position of RECEIVE9_FLUSH9 field. */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Msk (0x1UL << IPCT_SHORTS_RECEIVE9_FLUSH9_Pos) /*!< Bit mask of RECEIVE9_FLUSH9 field. */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9_FLUSH9 field. */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9_FLUSH9 field. */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE9_FLUSH9_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE10_FLUSH10 @Bit 10 : Shortcut between event RECEIVE[10] and task FLUSH[10] */ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Pos (10UL) /*!< Position of RECEIVE10_FLUSH10 field. */ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Msk (0x1UL << IPCT_SHORTS_RECEIVE10_FLUSH10_Pos) /*!< Bit mask of RECEIVE10_FLUSH10 + field.*/ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10_FLUSH10 field. */ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10_FLUSH10 field. */ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE10_FLUSH10_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE11_FLUSH11 @Bit 11 : Shortcut between event RECEIVE[11] and task FLUSH[11] */ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Pos (11UL) /*!< Position of RECEIVE11_FLUSH11 field. */ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Msk (0x1UL << IPCT_SHORTS_RECEIVE11_FLUSH11_Pos) /*!< Bit mask of RECEIVE11_FLUSH11 + field.*/ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11_FLUSH11 field. */ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11_FLUSH11 field. */ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE11_FLUSH11_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE12_FLUSH12 @Bit 12 : Shortcut between event RECEIVE[12] and task FLUSH[12] */ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Pos (12UL) /*!< Position of RECEIVE12_FLUSH12 field. */ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Msk (0x1UL << IPCT_SHORTS_RECEIVE12_FLUSH12_Pos) /*!< Bit mask of RECEIVE12_FLUSH12 + field.*/ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12_FLUSH12 field. */ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12_FLUSH12 field. */ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE12_FLUSH12_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE13_FLUSH13 @Bit 13 : Shortcut between event RECEIVE[13] and task FLUSH[13] */ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Pos (13UL) /*!< Position of RECEIVE13_FLUSH13 field. */ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Msk (0x1UL << IPCT_SHORTS_RECEIVE13_FLUSH13_Pos) /*!< Bit mask of RECEIVE13_FLUSH13 + field.*/ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13_FLUSH13 field. */ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13_FLUSH13 field. */ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE13_FLUSH13_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE14_FLUSH14 @Bit 14 : Shortcut between event RECEIVE[14] and task FLUSH[14] */ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Pos (14UL) /*!< Position of RECEIVE14_FLUSH14 field. */ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Msk (0x1UL << IPCT_SHORTS_RECEIVE14_FLUSH14_Pos) /*!< Bit mask of RECEIVE14_FLUSH14 + field.*/ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14_FLUSH14 field. */ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14_FLUSH14 field. */ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE14_FLUSH14_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RECEIVE15_FLUSH15 @Bit 15 : Shortcut between event RECEIVE[15] and task FLUSH[15] */ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Pos (15UL) /*!< Position of RECEIVE15_FLUSH15 field. */ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Msk (0x1UL << IPCT_SHORTS_RECEIVE15_FLUSH15_Pos) /*!< Bit mask of RECEIVE15_FLUSH15 + field.*/ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15_FLUSH15 field. */ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15_FLUSH15 field. */ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Disabled (0x0UL) /*!< Disable shortcut */ + #define IPCT_SHORTS_RECEIVE15_FLUSH15_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* IPCT_INTEN0: Enable or disable interrupt */ + #define IPCT_INTEN0_ResetValue (0x00000000UL) /*!< Reset value of INTEN0 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN0_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN0_RECEIVE0_Msk (0x1UL << IPCT_INTEN0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN0_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN0_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN0_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN0_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN0_RECEIVE1_Msk (0x1UL << IPCT_INTEN0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN0_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN0_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN0_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN0_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN0_RECEIVE2_Msk (0x1UL << IPCT_INTEN0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN0_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN0_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN0_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN0_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN0_RECEIVE3_Msk (0x1UL << IPCT_INTEN0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN0_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN0_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN0_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN0_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN0_RECEIVE4_Msk (0x1UL << IPCT_INTEN0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN0_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN0_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN0_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN0_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN0_RECEIVE5_Msk (0x1UL << IPCT_INTEN0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN0_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN0_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN0_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN0_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN0_RECEIVE6_Msk (0x1UL << IPCT_INTEN0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN0_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN0_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN0_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN0_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN0_RECEIVE7_Msk (0x1UL << IPCT_INTEN0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN0_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN0_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN0_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN0_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN0_RECEIVE8_Msk (0x1UL << IPCT_INTEN0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN0_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN0_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN0_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN0_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN0_RECEIVE9_Msk (0x1UL << IPCT_INTEN0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN0_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN0_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN0_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN0_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN0_RECEIVE10_Msk (0x1UL << IPCT_INTEN0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN0_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN0_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN0_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN0_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN0_RECEIVE11_Msk (0x1UL << IPCT_INTEN0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN0_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN0_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN0_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN0_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN0_RECEIVE12_Msk (0x1UL << IPCT_INTEN0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN0_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN0_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN0_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN0_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN0_RECEIVE13_Msk (0x1UL << IPCT_INTEN0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN0_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN0_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN0_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN0_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN0_RECEIVE14_Msk (0x1UL << IPCT_INTEN0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN0_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN0_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN0_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN0_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN0_RECEIVE15_Msk (0x1UL << IPCT_INTEN0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN0_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN0_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN0_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN0_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN0_READY0_Msk (0x1UL << IPCT_INTEN0_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN0_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN0_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN0_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN0_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN0_READY1_Msk (0x1UL << IPCT_INTEN0_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN0_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN0_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN0_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN0_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN0_READY2_Msk (0x1UL << IPCT_INTEN0_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN0_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN0_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN0_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN0_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN0_READY3_Msk (0x1UL << IPCT_INTEN0_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN0_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN0_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN0_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN0_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN0_READY4_Msk (0x1UL << IPCT_INTEN0_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN0_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN0_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN0_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN0_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN0_READY5_Msk (0x1UL << IPCT_INTEN0_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN0_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN0_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN0_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN0_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN0_READY6_Msk (0x1UL << IPCT_INTEN0_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN0_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN0_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN0_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN0_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN0_READY7_Msk (0x1UL << IPCT_INTEN0_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN0_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN0_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN0_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN0_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN0_READY8_Msk (0x1UL << IPCT_INTEN0_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN0_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN0_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN0_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN0_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN0_READY9_Msk (0x1UL << IPCT_INTEN0_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN0_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN0_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN0_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN0_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN0_READY10_Msk (0x1UL << IPCT_INTEN0_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN0_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN0_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN0_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN0_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN0_READY11_Msk (0x1UL << IPCT_INTEN0_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN0_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN0_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN0_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN0_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN0_READY12_Msk (0x1UL << IPCT_INTEN0_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN0_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN0_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN0_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN0_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN0_READY13_Msk (0x1UL << IPCT_INTEN0_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN0_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN0_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN0_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN0_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN0_READY14_Msk (0x1UL << IPCT_INTEN0_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN0_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN0_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN0_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN0_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN0_READY15_Msk (0x1UL << IPCT_INTEN0_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN0_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN0_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN0_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN0_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET0: Enable interrupt */ + #define IPCT_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET0_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET0_RECEIVE0_Msk (0x1UL << IPCT_INTENSET0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET0_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET0_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET0_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET0_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET0_RECEIVE1_Msk (0x1UL << IPCT_INTENSET0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET0_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET0_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET0_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET0_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET0_RECEIVE2_Msk (0x1UL << IPCT_INTENSET0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET0_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET0_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET0_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET0_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET0_RECEIVE3_Msk (0x1UL << IPCT_INTENSET0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET0_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET0_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET0_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET0_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET0_RECEIVE4_Msk (0x1UL << IPCT_INTENSET0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET0_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET0_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET0_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET0_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET0_RECEIVE5_Msk (0x1UL << IPCT_INTENSET0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET0_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET0_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET0_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET0_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET0_RECEIVE6_Msk (0x1UL << IPCT_INTENSET0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET0_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET0_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET0_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET0_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET0_RECEIVE7_Msk (0x1UL << IPCT_INTENSET0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET0_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET0_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET0_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET0_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET0_RECEIVE8_Msk (0x1UL << IPCT_INTENSET0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET0_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET0_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET0_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET0_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET0_RECEIVE9_Msk (0x1UL << IPCT_INTENSET0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET0_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET0_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET0_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET0_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET0_RECEIVE10_Msk (0x1UL << IPCT_INTENSET0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET0_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET0_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET0_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET0_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET0_RECEIVE11_Msk (0x1UL << IPCT_INTENSET0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET0_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET0_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET0_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET0_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET0_RECEIVE12_Msk (0x1UL << IPCT_INTENSET0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET0_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET0_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET0_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET0_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET0_RECEIVE13_Msk (0x1UL << IPCT_INTENSET0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET0_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET0_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET0_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET0_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET0_RECEIVE14_Msk (0x1UL << IPCT_INTENSET0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET0_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET0_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET0_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET0_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET0_RECEIVE15_Msk (0x1UL << IPCT_INTENSET0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET0_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET0_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET0_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET0_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET0_READY0_Msk (0x1UL << IPCT_INTENSET0_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET0_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET0_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET0_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET0_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET0_READY1_Msk (0x1UL << IPCT_INTENSET0_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET0_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET0_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET0_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET0_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET0_READY2_Msk (0x1UL << IPCT_INTENSET0_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET0_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET0_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET0_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET0_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET0_READY3_Msk (0x1UL << IPCT_INTENSET0_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET0_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET0_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET0_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET0_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET0_READY4_Msk (0x1UL << IPCT_INTENSET0_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET0_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET0_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET0_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET0_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET0_READY5_Msk (0x1UL << IPCT_INTENSET0_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET0_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET0_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET0_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET0_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET0_READY6_Msk (0x1UL << IPCT_INTENSET0_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET0_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET0_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET0_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET0_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET0_READY7_Msk (0x1UL << IPCT_INTENSET0_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET0_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET0_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET0_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET0_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET0_READY8_Msk (0x1UL << IPCT_INTENSET0_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET0_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET0_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET0_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET0_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET0_READY9_Msk (0x1UL << IPCT_INTENSET0_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET0_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET0_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET0_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET0_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET0_READY10_Msk (0x1UL << IPCT_INTENSET0_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET0_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET0_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET0_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET0_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET0_READY11_Msk (0x1UL << IPCT_INTENSET0_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET0_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET0_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET0_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET0_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET0_READY12_Msk (0x1UL << IPCT_INTENSET0_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET0_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET0_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET0_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET0_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET0_READY13_Msk (0x1UL << IPCT_INTENSET0_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET0_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET0_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET0_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET0_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET0_READY14_Msk (0x1UL << IPCT_INTENSET0_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET0_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET0_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET0_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET0_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET0_READY15_Msk (0x1UL << IPCT_INTENSET0_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET0_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET0_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET0_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET0_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET0_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR0: Disable interrupt */ + #define IPCT_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR0_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR0_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR0_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR0_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR0_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR0_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR0_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR0_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR0_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR0_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR0_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR0_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR0_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR0_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR0_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR0_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR0_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR0_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR0_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR0_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR0_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR0_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR0_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR0_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR0_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR0_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR0_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR0_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR0_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR0_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR0_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR0_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR0_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR0_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR0_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR0_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR0_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR0_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR0_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR0_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR0_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR0_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR0_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR0_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR0_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR0_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR0_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR0_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR0_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR0_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR0_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR0_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR0_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR0_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR0_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR0_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR0_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR0_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR0_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR0_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR0_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR0_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR0_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR0_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR0_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR0_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR0_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR0_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR0_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR0_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR0_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR0_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR0_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR0_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR0_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR0_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR0_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR0_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR0_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR0_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR0_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR0_READY0_Msk (0x1UL << IPCT_INTENCLR0_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR0_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR0_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR0_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR0_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR0_READY1_Msk (0x1UL << IPCT_INTENCLR0_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR0_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR0_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR0_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR0_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR0_READY2_Msk (0x1UL << IPCT_INTENCLR0_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR0_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR0_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR0_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR0_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR0_READY3_Msk (0x1UL << IPCT_INTENCLR0_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR0_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR0_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR0_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR0_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR0_READY4_Msk (0x1UL << IPCT_INTENCLR0_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR0_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR0_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR0_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR0_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR0_READY5_Msk (0x1UL << IPCT_INTENCLR0_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR0_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR0_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR0_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR0_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR0_READY6_Msk (0x1UL << IPCT_INTENCLR0_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR0_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR0_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR0_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR0_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR0_READY7_Msk (0x1UL << IPCT_INTENCLR0_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR0_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR0_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR0_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR0_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR0_READY8_Msk (0x1UL << IPCT_INTENCLR0_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR0_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR0_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR0_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR0_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR0_READY9_Msk (0x1UL << IPCT_INTENCLR0_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR0_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR0_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR0_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR0_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR0_READY10_Msk (0x1UL << IPCT_INTENCLR0_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR0_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR0_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR0_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR0_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR0_READY11_Msk (0x1UL << IPCT_INTENCLR0_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR0_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR0_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR0_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR0_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR0_READY12_Msk (0x1UL << IPCT_INTENCLR0_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR0_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR0_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR0_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR0_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR0_READY13_Msk (0x1UL << IPCT_INTENCLR0_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR0_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR0_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR0_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR0_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR0_READY14_Msk (0x1UL << IPCT_INTENCLR0_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR0_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR0_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR0_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR0_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR0_READY15_Msk (0x1UL << IPCT_INTENCLR0_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR0_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR0_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR0_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR0_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR0_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND0: Pending interrupts */ + #define IPCT_INTPEND0_ResetValue (0x00000000UL) /*!< Reset value of INTPEND0 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND0_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND0_RECEIVE0_Msk (0x1UL << IPCT_INTPEND0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND0_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND0_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND0_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND0_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND0_RECEIVE1_Msk (0x1UL << IPCT_INTPEND0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND0_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND0_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND0_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND0_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND0_RECEIVE2_Msk (0x1UL << IPCT_INTPEND0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND0_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND0_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND0_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND0_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND0_RECEIVE3_Msk (0x1UL << IPCT_INTPEND0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND0_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND0_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND0_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND0_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND0_RECEIVE4_Msk (0x1UL << IPCT_INTPEND0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND0_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND0_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND0_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND0_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND0_RECEIVE5_Msk (0x1UL << IPCT_INTPEND0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND0_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND0_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND0_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND0_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND0_RECEIVE6_Msk (0x1UL << IPCT_INTPEND0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND0_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND0_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND0_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND0_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND0_RECEIVE7_Msk (0x1UL << IPCT_INTPEND0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND0_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND0_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND0_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND0_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND0_RECEIVE8_Msk (0x1UL << IPCT_INTPEND0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND0_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND0_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND0_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND0_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND0_RECEIVE9_Msk (0x1UL << IPCT_INTPEND0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND0_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND0_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND0_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND0_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND0_RECEIVE10_Msk (0x1UL << IPCT_INTPEND0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND0_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND0_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND0_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND0_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND0_RECEIVE11_Msk (0x1UL << IPCT_INTPEND0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND0_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND0_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND0_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND0_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND0_RECEIVE12_Msk (0x1UL << IPCT_INTPEND0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND0_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND0_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND0_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND0_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND0_RECEIVE13_Msk (0x1UL << IPCT_INTPEND0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND0_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND0_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND0_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND0_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND0_RECEIVE14_Msk (0x1UL << IPCT_INTPEND0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND0_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND0_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND0_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND0_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND0_RECEIVE15_Msk (0x1UL << IPCT_INTPEND0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND0_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND0_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND0_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND0_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND0_READY0_Msk (0x1UL << IPCT_INTPEND0_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND0_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND0_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND0_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND0_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND0_READY1_Msk (0x1UL << IPCT_INTPEND0_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND0_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND0_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND0_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND0_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND0_READY2_Msk (0x1UL << IPCT_INTPEND0_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND0_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND0_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND0_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND0_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND0_READY3_Msk (0x1UL << IPCT_INTPEND0_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND0_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND0_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND0_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND0_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND0_READY4_Msk (0x1UL << IPCT_INTPEND0_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND0_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND0_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND0_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND0_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND0_READY5_Msk (0x1UL << IPCT_INTPEND0_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND0_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND0_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND0_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND0_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND0_READY6_Msk (0x1UL << IPCT_INTPEND0_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND0_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND0_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND0_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND0_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND0_READY7_Msk (0x1UL << IPCT_INTPEND0_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND0_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND0_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND0_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND0_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND0_READY8_Msk (0x1UL << IPCT_INTPEND0_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND0_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND0_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND0_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND0_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND0_READY9_Msk (0x1UL << IPCT_INTPEND0_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND0_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND0_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND0_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND0_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND0_READY10_Msk (0x1UL << IPCT_INTPEND0_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND0_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND0_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND0_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND0_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND0_READY11_Msk (0x1UL << IPCT_INTPEND0_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND0_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND0_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND0_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND0_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND0_READY12_Msk (0x1UL << IPCT_INTPEND0_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND0_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND0_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND0_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND0_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND0_READY13_Msk (0x1UL << IPCT_INTPEND0_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND0_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND0_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND0_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND0_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND0_READY14_Msk (0x1UL << IPCT_INTPEND0_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND0_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND0_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND0_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND0_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND0_READY15_Msk (0x1UL << IPCT_INTPEND0_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND0_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND0_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND0_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND0_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN1: Enable or disable interrupt */ + #define IPCT_INTEN1_ResetValue (0x00000000UL) /*!< Reset value of INTEN1 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN1_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN1_RECEIVE0_Msk (0x1UL << IPCT_INTEN1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN1_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN1_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN1_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN1_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN1_RECEIVE1_Msk (0x1UL << IPCT_INTEN1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN1_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN1_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN1_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN1_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN1_RECEIVE2_Msk (0x1UL << IPCT_INTEN1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN1_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN1_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN1_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN1_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN1_RECEIVE3_Msk (0x1UL << IPCT_INTEN1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN1_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN1_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN1_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN1_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN1_RECEIVE4_Msk (0x1UL << IPCT_INTEN1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN1_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN1_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN1_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN1_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN1_RECEIVE5_Msk (0x1UL << IPCT_INTEN1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN1_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN1_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN1_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN1_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN1_RECEIVE6_Msk (0x1UL << IPCT_INTEN1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN1_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN1_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN1_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN1_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN1_RECEIVE7_Msk (0x1UL << IPCT_INTEN1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN1_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN1_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN1_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN1_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN1_RECEIVE8_Msk (0x1UL << IPCT_INTEN1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN1_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN1_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN1_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN1_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN1_RECEIVE9_Msk (0x1UL << IPCT_INTEN1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN1_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN1_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN1_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN1_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN1_RECEIVE10_Msk (0x1UL << IPCT_INTEN1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN1_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN1_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN1_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN1_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN1_RECEIVE11_Msk (0x1UL << IPCT_INTEN1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN1_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN1_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN1_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN1_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN1_RECEIVE12_Msk (0x1UL << IPCT_INTEN1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN1_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN1_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN1_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN1_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN1_RECEIVE13_Msk (0x1UL << IPCT_INTEN1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN1_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN1_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN1_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN1_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN1_RECEIVE14_Msk (0x1UL << IPCT_INTEN1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN1_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN1_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN1_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN1_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN1_RECEIVE15_Msk (0x1UL << IPCT_INTEN1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN1_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN1_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN1_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN1_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN1_READY0_Msk (0x1UL << IPCT_INTEN1_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN1_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN1_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN1_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN1_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN1_READY1_Msk (0x1UL << IPCT_INTEN1_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN1_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN1_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN1_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN1_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN1_READY2_Msk (0x1UL << IPCT_INTEN1_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN1_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN1_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN1_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN1_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN1_READY3_Msk (0x1UL << IPCT_INTEN1_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN1_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN1_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN1_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN1_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN1_READY4_Msk (0x1UL << IPCT_INTEN1_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN1_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN1_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN1_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN1_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN1_READY5_Msk (0x1UL << IPCT_INTEN1_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN1_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN1_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN1_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN1_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN1_READY6_Msk (0x1UL << IPCT_INTEN1_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN1_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN1_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN1_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN1_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN1_READY7_Msk (0x1UL << IPCT_INTEN1_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN1_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN1_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN1_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN1_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN1_READY8_Msk (0x1UL << IPCT_INTEN1_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN1_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN1_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN1_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN1_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN1_READY9_Msk (0x1UL << IPCT_INTEN1_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN1_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN1_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN1_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN1_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN1_READY10_Msk (0x1UL << IPCT_INTEN1_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN1_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN1_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN1_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN1_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN1_READY11_Msk (0x1UL << IPCT_INTEN1_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN1_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN1_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN1_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN1_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN1_READY12_Msk (0x1UL << IPCT_INTEN1_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN1_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN1_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN1_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN1_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN1_READY13_Msk (0x1UL << IPCT_INTEN1_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN1_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN1_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN1_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN1_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN1_READY14_Msk (0x1UL << IPCT_INTEN1_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN1_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN1_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN1_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN1_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN1_READY15_Msk (0x1UL << IPCT_INTEN1_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN1_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN1_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN1_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN1_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET1: Enable interrupt */ + #define IPCT_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET1_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET1_RECEIVE0_Msk (0x1UL << IPCT_INTENSET1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET1_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET1_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET1_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET1_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET1_RECEIVE1_Msk (0x1UL << IPCT_INTENSET1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET1_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET1_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET1_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET1_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET1_RECEIVE2_Msk (0x1UL << IPCT_INTENSET1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET1_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET1_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET1_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET1_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET1_RECEIVE3_Msk (0x1UL << IPCT_INTENSET1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET1_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET1_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET1_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET1_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET1_RECEIVE4_Msk (0x1UL << IPCT_INTENSET1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET1_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET1_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET1_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET1_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET1_RECEIVE5_Msk (0x1UL << IPCT_INTENSET1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET1_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET1_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET1_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET1_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET1_RECEIVE6_Msk (0x1UL << IPCT_INTENSET1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET1_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET1_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET1_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET1_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET1_RECEIVE7_Msk (0x1UL << IPCT_INTENSET1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET1_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET1_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET1_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET1_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET1_RECEIVE8_Msk (0x1UL << IPCT_INTENSET1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET1_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET1_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET1_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET1_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET1_RECEIVE9_Msk (0x1UL << IPCT_INTENSET1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET1_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET1_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET1_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET1_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET1_RECEIVE10_Msk (0x1UL << IPCT_INTENSET1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET1_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET1_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET1_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET1_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET1_RECEIVE11_Msk (0x1UL << IPCT_INTENSET1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET1_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET1_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET1_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET1_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET1_RECEIVE12_Msk (0x1UL << IPCT_INTENSET1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET1_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET1_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET1_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET1_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET1_RECEIVE13_Msk (0x1UL << IPCT_INTENSET1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET1_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET1_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET1_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET1_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET1_RECEIVE14_Msk (0x1UL << IPCT_INTENSET1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET1_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET1_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET1_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET1_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET1_RECEIVE15_Msk (0x1UL << IPCT_INTENSET1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET1_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET1_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET1_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET1_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET1_READY0_Msk (0x1UL << IPCT_INTENSET1_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET1_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET1_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET1_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET1_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET1_READY1_Msk (0x1UL << IPCT_INTENSET1_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET1_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET1_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET1_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET1_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET1_READY2_Msk (0x1UL << IPCT_INTENSET1_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET1_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET1_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET1_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET1_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET1_READY3_Msk (0x1UL << IPCT_INTENSET1_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET1_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET1_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET1_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET1_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET1_READY4_Msk (0x1UL << IPCT_INTENSET1_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET1_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET1_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET1_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET1_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET1_READY5_Msk (0x1UL << IPCT_INTENSET1_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET1_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET1_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET1_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET1_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET1_READY6_Msk (0x1UL << IPCT_INTENSET1_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET1_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET1_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET1_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET1_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET1_READY7_Msk (0x1UL << IPCT_INTENSET1_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET1_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET1_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET1_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET1_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET1_READY8_Msk (0x1UL << IPCT_INTENSET1_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET1_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET1_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET1_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET1_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET1_READY9_Msk (0x1UL << IPCT_INTENSET1_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET1_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET1_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET1_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET1_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET1_READY10_Msk (0x1UL << IPCT_INTENSET1_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET1_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET1_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET1_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET1_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET1_READY11_Msk (0x1UL << IPCT_INTENSET1_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET1_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET1_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET1_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET1_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET1_READY12_Msk (0x1UL << IPCT_INTENSET1_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET1_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET1_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET1_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET1_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET1_READY13_Msk (0x1UL << IPCT_INTENSET1_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET1_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET1_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET1_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET1_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET1_READY14_Msk (0x1UL << IPCT_INTENSET1_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET1_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET1_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET1_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET1_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET1_READY15_Msk (0x1UL << IPCT_INTENSET1_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET1_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET1_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET1_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET1_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET1_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR1: Disable interrupt */ + #define IPCT_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR1_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR1_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR1_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR1_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR1_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR1_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR1_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR1_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR1_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR1_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR1_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR1_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR1_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR1_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR1_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR1_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR1_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR1_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR1_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR1_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR1_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR1_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR1_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR1_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR1_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR1_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR1_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR1_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR1_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR1_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR1_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR1_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR1_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR1_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR1_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR1_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR1_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR1_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR1_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR1_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR1_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR1_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR1_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR1_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR1_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR1_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR1_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR1_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR1_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR1_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR1_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR1_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR1_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR1_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR1_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR1_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR1_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR1_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR1_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR1_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR1_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR1_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR1_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR1_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR1_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR1_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR1_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR1_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR1_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR1_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR1_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR1_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR1_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR1_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR1_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR1_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR1_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR1_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR1_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR1_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR1_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR1_READY0_Msk (0x1UL << IPCT_INTENCLR1_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR1_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR1_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR1_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR1_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR1_READY1_Msk (0x1UL << IPCT_INTENCLR1_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR1_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR1_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR1_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR1_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR1_READY2_Msk (0x1UL << IPCT_INTENCLR1_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR1_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR1_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR1_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR1_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR1_READY3_Msk (0x1UL << IPCT_INTENCLR1_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR1_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR1_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR1_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR1_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR1_READY4_Msk (0x1UL << IPCT_INTENCLR1_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR1_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR1_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR1_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR1_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR1_READY5_Msk (0x1UL << IPCT_INTENCLR1_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR1_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR1_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR1_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR1_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR1_READY6_Msk (0x1UL << IPCT_INTENCLR1_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR1_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR1_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR1_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR1_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR1_READY7_Msk (0x1UL << IPCT_INTENCLR1_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR1_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR1_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR1_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR1_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR1_READY8_Msk (0x1UL << IPCT_INTENCLR1_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR1_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR1_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR1_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR1_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR1_READY9_Msk (0x1UL << IPCT_INTENCLR1_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR1_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR1_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR1_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR1_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR1_READY10_Msk (0x1UL << IPCT_INTENCLR1_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR1_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR1_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR1_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR1_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR1_READY11_Msk (0x1UL << IPCT_INTENCLR1_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR1_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR1_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR1_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR1_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR1_READY12_Msk (0x1UL << IPCT_INTENCLR1_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR1_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR1_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR1_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR1_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR1_READY13_Msk (0x1UL << IPCT_INTENCLR1_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR1_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR1_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR1_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR1_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR1_READY14_Msk (0x1UL << IPCT_INTENCLR1_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR1_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR1_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR1_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR1_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR1_READY15_Msk (0x1UL << IPCT_INTENCLR1_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR1_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR1_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR1_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR1_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR1_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND1: Pending interrupts */ + #define IPCT_INTPEND1_ResetValue (0x00000000UL) /*!< Reset value of INTPEND1 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND1_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND1_RECEIVE0_Msk (0x1UL << IPCT_INTPEND1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND1_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND1_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND1_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND1_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND1_RECEIVE1_Msk (0x1UL << IPCT_INTPEND1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND1_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND1_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND1_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND1_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND1_RECEIVE2_Msk (0x1UL << IPCT_INTPEND1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND1_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND1_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND1_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND1_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND1_RECEIVE3_Msk (0x1UL << IPCT_INTPEND1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND1_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND1_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND1_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND1_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND1_RECEIVE4_Msk (0x1UL << IPCT_INTPEND1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND1_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND1_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND1_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND1_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND1_RECEIVE5_Msk (0x1UL << IPCT_INTPEND1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND1_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND1_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND1_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND1_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND1_RECEIVE6_Msk (0x1UL << IPCT_INTPEND1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND1_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND1_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND1_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND1_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND1_RECEIVE7_Msk (0x1UL << IPCT_INTPEND1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND1_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND1_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND1_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND1_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND1_RECEIVE8_Msk (0x1UL << IPCT_INTPEND1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND1_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND1_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND1_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND1_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND1_RECEIVE9_Msk (0x1UL << IPCT_INTPEND1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND1_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND1_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND1_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND1_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND1_RECEIVE10_Msk (0x1UL << IPCT_INTPEND1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND1_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND1_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND1_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND1_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND1_RECEIVE11_Msk (0x1UL << IPCT_INTPEND1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND1_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND1_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND1_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND1_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND1_RECEIVE12_Msk (0x1UL << IPCT_INTPEND1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND1_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND1_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND1_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND1_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND1_RECEIVE13_Msk (0x1UL << IPCT_INTPEND1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND1_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND1_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND1_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND1_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND1_RECEIVE14_Msk (0x1UL << IPCT_INTPEND1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND1_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND1_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND1_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND1_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND1_RECEIVE15_Msk (0x1UL << IPCT_INTPEND1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND1_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND1_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND1_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND1_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND1_READY0_Msk (0x1UL << IPCT_INTPEND1_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND1_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND1_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND1_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND1_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND1_READY1_Msk (0x1UL << IPCT_INTPEND1_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND1_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND1_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND1_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND1_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND1_READY2_Msk (0x1UL << IPCT_INTPEND1_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND1_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND1_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND1_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND1_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND1_READY3_Msk (0x1UL << IPCT_INTPEND1_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND1_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND1_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND1_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND1_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND1_READY4_Msk (0x1UL << IPCT_INTPEND1_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND1_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND1_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND1_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND1_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND1_READY5_Msk (0x1UL << IPCT_INTPEND1_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND1_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND1_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND1_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND1_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND1_READY6_Msk (0x1UL << IPCT_INTPEND1_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND1_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND1_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND1_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND1_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND1_READY7_Msk (0x1UL << IPCT_INTPEND1_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND1_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND1_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND1_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND1_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND1_READY8_Msk (0x1UL << IPCT_INTPEND1_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND1_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND1_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND1_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND1_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND1_READY9_Msk (0x1UL << IPCT_INTPEND1_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND1_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND1_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND1_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND1_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND1_READY10_Msk (0x1UL << IPCT_INTPEND1_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND1_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND1_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND1_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND1_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND1_READY11_Msk (0x1UL << IPCT_INTPEND1_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND1_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND1_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND1_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND1_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND1_READY12_Msk (0x1UL << IPCT_INTPEND1_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND1_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND1_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND1_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND1_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND1_READY13_Msk (0x1UL << IPCT_INTPEND1_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND1_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND1_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND1_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND1_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND1_READY14_Msk (0x1UL << IPCT_INTPEND1_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND1_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND1_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND1_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND1_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND1_READY15_Msk (0x1UL << IPCT_INTPEND1_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND1_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND1_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND1_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND1_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN2: Enable or disable interrupt */ + #define IPCT_INTEN2_ResetValue (0x00000000UL) /*!< Reset value of INTEN2 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN2_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN2_RECEIVE0_Msk (0x1UL << IPCT_INTEN2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN2_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN2_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN2_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN2_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN2_RECEIVE1_Msk (0x1UL << IPCT_INTEN2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN2_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN2_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN2_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN2_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN2_RECEIVE2_Msk (0x1UL << IPCT_INTEN2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN2_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN2_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN2_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN2_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN2_RECEIVE3_Msk (0x1UL << IPCT_INTEN2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN2_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN2_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN2_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN2_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN2_RECEIVE4_Msk (0x1UL << IPCT_INTEN2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN2_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN2_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN2_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN2_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN2_RECEIVE5_Msk (0x1UL << IPCT_INTEN2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN2_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN2_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN2_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN2_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN2_RECEIVE6_Msk (0x1UL << IPCT_INTEN2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN2_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN2_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN2_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN2_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN2_RECEIVE7_Msk (0x1UL << IPCT_INTEN2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN2_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN2_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN2_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN2_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN2_RECEIVE8_Msk (0x1UL << IPCT_INTEN2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN2_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN2_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN2_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN2_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN2_RECEIVE9_Msk (0x1UL << IPCT_INTEN2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN2_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN2_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN2_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN2_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN2_RECEIVE10_Msk (0x1UL << IPCT_INTEN2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN2_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN2_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN2_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN2_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN2_RECEIVE11_Msk (0x1UL << IPCT_INTEN2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN2_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN2_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN2_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN2_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN2_RECEIVE12_Msk (0x1UL << IPCT_INTEN2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN2_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN2_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN2_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN2_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN2_RECEIVE13_Msk (0x1UL << IPCT_INTEN2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN2_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN2_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN2_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN2_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN2_RECEIVE14_Msk (0x1UL << IPCT_INTEN2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN2_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN2_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN2_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN2_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN2_RECEIVE15_Msk (0x1UL << IPCT_INTEN2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN2_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN2_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN2_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN2_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN2_READY0_Msk (0x1UL << IPCT_INTEN2_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN2_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN2_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN2_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN2_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN2_READY1_Msk (0x1UL << IPCT_INTEN2_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN2_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN2_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN2_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN2_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN2_READY2_Msk (0x1UL << IPCT_INTEN2_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN2_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN2_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN2_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN2_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN2_READY3_Msk (0x1UL << IPCT_INTEN2_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN2_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN2_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN2_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN2_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN2_READY4_Msk (0x1UL << IPCT_INTEN2_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN2_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN2_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN2_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN2_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN2_READY5_Msk (0x1UL << IPCT_INTEN2_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN2_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN2_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN2_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN2_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN2_READY6_Msk (0x1UL << IPCT_INTEN2_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN2_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN2_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN2_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN2_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN2_READY7_Msk (0x1UL << IPCT_INTEN2_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN2_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN2_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN2_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN2_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN2_READY8_Msk (0x1UL << IPCT_INTEN2_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN2_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN2_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN2_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN2_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN2_READY9_Msk (0x1UL << IPCT_INTEN2_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN2_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN2_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN2_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN2_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN2_READY10_Msk (0x1UL << IPCT_INTEN2_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN2_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN2_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN2_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN2_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN2_READY11_Msk (0x1UL << IPCT_INTEN2_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN2_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN2_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN2_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN2_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN2_READY12_Msk (0x1UL << IPCT_INTEN2_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN2_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN2_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN2_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN2_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN2_READY13_Msk (0x1UL << IPCT_INTEN2_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN2_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN2_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN2_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN2_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN2_READY14_Msk (0x1UL << IPCT_INTEN2_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN2_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN2_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN2_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN2_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN2_READY15_Msk (0x1UL << IPCT_INTEN2_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN2_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN2_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN2_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN2_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET2: Enable interrupt */ + #define IPCT_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET2_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET2_RECEIVE0_Msk (0x1UL << IPCT_INTENSET2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET2_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET2_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET2_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET2_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET2_RECEIVE1_Msk (0x1UL << IPCT_INTENSET2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET2_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET2_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET2_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET2_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET2_RECEIVE2_Msk (0x1UL << IPCT_INTENSET2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET2_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET2_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET2_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET2_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET2_RECEIVE3_Msk (0x1UL << IPCT_INTENSET2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET2_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET2_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET2_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET2_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET2_RECEIVE4_Msk (0x1UL << IPCT_INTENSET2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET2_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET2_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET2_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET2_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET2_RECEIVE5_Msk (0x1UL << IPCT_INTENSET2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET2_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET2_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET2_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET2_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET2_RECEIVE6_Msk (0x1UL << IPCT_INTENSET2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET2_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET2_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET2_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET2_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET2_RECEIVE7_Msk (0x1UL << IPCT_INTENSET2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET2_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET2_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET2_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET2_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET2_RECEIVE8_Msk (0x1UL << IPCT_INTENSET2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET2_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET2_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET2_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET2_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET2_RECEIVE9_Msk (0x1UL << IPCT_INTENSET2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET2_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET2_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET2_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET2_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET2_RECEIVE10_Msk (0x1UL << IPCT_INTENSET2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET2_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET2_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET2_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET2_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET2_RECEIVE11_Msk (0x1UL << IPCT_INTENSET2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET2_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET2_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET2_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET2_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET2_RECEIVE12_Msk (0x1UL << IPCT_INTENSET2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET2_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET2_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET2_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET2_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET2_RECEIVE13_Msk (0x1UL << IPCT_INTENSET2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET2_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET2_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET2_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET2_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET2_RECEIVE14_Msk (0x1UL << IPCT_INTENSET2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET2_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET2_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET2_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET2_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET2_RECEIVE15_Msk (0x1UL << IPCT_INTENSET2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET2_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET2_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET2_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET2_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET2_READY0_Msk (0x1UL << IPCT_INTENSET2_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET2_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET2_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET2_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET2_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET2_READY1_Msk (0x1UL << IPCT_INTENSET2_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET2_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET2_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET2_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET2_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET2_READY2_Msk (0x1UL << IPCT_INTENSET2_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET2_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET2_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET2_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET2_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET2_READY3_Msk (0x1UL << IPCT_INTENSET2_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET2_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET2_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET2_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET2_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET2_READY4_Msk (0x1UL << IPCT_INTENSET2_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET2_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET2_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET2_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET2_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET2_READY5_Msk (0x1UL << IPCT_INTENSET2_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET2_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET2_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET2_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET2_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET2_READY6_Msk (0x1UL << IPCT_INTENSET2_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET2_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET2_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET2_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET2_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET2_READY7_Msk (0x1UL << IPCT_INTENSET2_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET2_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET2_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET2_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET2_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET2_READY8_Msk (0x1UL << IPCT_INTENSET2_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET2_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET2_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET2_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET2_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET2_READY9_Msk (0x1UL << IPCT_INTENSET2_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET2_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET2_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET2_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET2_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET2_READY10_Msk (0x1UL << IPCT_INTENSET2_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET2_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET2_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET2_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET2_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET2_READY11_Msk (0x1UL << IPCT_INTENSET2_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET2_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET2_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET2_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET2_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET2_READY12_Msk (0x1UL << IPCT_INTENSET2_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET2_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET2_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET2_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET2_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET2_READY13_Msk (0x1UL << IPCT_INTENSET2_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET2_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET2_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET2_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET2_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET2_READY14_Msk (0x1UL << IPCT_INTENSET2_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET2_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET2_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET2_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET2_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET2_READY15_Msk (0x1UL << IPCT_INTENSET2_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET2_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET2_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET2_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET2_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET2_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR2: Disable interrupt */ + #define IPCT_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR2_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR2_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR2_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR2_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR2_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR2_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR2_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR2_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR2_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR2_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR2_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR2_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR2_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR2_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR2_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR2_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR2_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR2_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR2_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR2_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR2_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR2_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR2_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR2_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR2_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR2_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR2_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR2_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR2_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR2_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR2_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR2_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR2_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR2_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR2_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR2_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR2_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR2_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR2_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR2_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR2_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR2_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR2_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR2_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR2_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR2_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR2_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR2_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR2_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR2_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR2_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR2_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR2_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR2_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR2_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR2_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR2_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR2_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR2_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR2_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR2_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR2_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR2_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR2_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR2_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR2_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR2_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR2_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR2_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR2_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR2_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR2_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR2_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR2_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR2_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR2_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR2_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR2_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR2_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR2_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR2_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR2_READY0_Msk (0x1UL << IPCT_INTENCLR2_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR2_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR2_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR2_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR2_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR2_READY1_Msk (0x1UL << IPCT_INTENCLR2_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR2_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR2_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR2_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR2_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR2_READY2_Msk (0x1UL << IPCT_INTENCLR2_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR2_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR2_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR2_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR2_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR2_READY3_Msk (0x1UL << IPCT_INTENCLR2_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR2_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR2_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR2_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR2_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR2_READY4_Msk (0x1UL << IPCT_INTENCLR2_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR2_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR2_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR2_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR2_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR2_READY5_Msk (0x1UL << IPCT_INTENCLR2_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR2_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR2_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR2_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR2_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR2_READY6_Msk (0x1UL << IPCT_INTENCLR2_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR2_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR2_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR2_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR2_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR2_READY7_Msk (0x1UL << IPCT_INTENCLR2_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR2_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR2_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR2_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR2_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR2_READY8_Msk (0x1UL << IPCT_INTENCLR2_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR2_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR2_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR2_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR2_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR2_READY9_Msk (0x1UL << IPCT_INTENCLR2_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR2_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR2_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR2_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR2_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR2_READY10_Msk (0x1UL << IPCT_INTENCLR2_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR2_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR2_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR2_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR2_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR2_READY11_Msk (0x1UL << IPCT_INTENCLR2_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR2_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR2_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR2_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR2_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR2_READY12_Msk (0x1UL << IPCT_INTENCLR2_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR2_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR2_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR2_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR2_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR2_READY13_Msk (0x1UL << IPCT_INTENCLR2_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR2_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR2_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR2_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR2_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR2_READY14_Msk (0x1UL << IPCT_INTENCLR2_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR2_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR2_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR2_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR2_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR2_READY15_Msk (0x1UL << IPCT_INTENCLR2_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR2_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR2_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR2_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR2_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR2_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND2: Pending interrupts */ + #define IPCT_INTPEND2_ResetValue (0x00000000UL) /*!< Reset value of INTPEND2 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND2_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND2_RECEIVE0_Msk (0x1UL << IPCT_INTPEND2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND2_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND2_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND2_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND2_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND2_RECEIVE1_Msk (0x1UL << IPCT_INTPEND2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND2_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND2_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND2_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND2_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND2_RECEIVE2_Msk (0x1UL << IPCT_INTPEND2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND2_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND2_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND2_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND2_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND2_RECEIVE3_Msk (0x1UL << IPCT_INTPEND2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND2_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND2_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND2_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND2_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND2_RECEIVE4_Msk (0x1UL << IPCT_INTPEND2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND2_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND2_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND2_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND2_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND2_RECEIVE5_Msk (0x1UL << IPCT_INTPEND2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND2_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND2_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND2_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND2_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND2_RECEIVE6_Msk (0x1UL << IPCT_INTPEND2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND2_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND2_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND2_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND2_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND2_RECEIVE7_Msk (0x1UL << IPCT_INTPEND2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND2_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND2_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND2_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND2_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND2_RECEIVE8_Msk (0x1UL << IPCT_INTPEND2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND2_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND2_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND2_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND2_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND2_RECEIVE9_Msk (0x1UL << IPCT_INTPEND2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND2_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND2_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND2_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND2_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND2_RECEIVE10_Msk (0x1UL << IPCT_INTPEND2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND2_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND2_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND2_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND2_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND2_RECEIVE11_Msk (0x1UL << IPCT_INTPEND2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND2_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND2_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND2_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND2_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND2_RECEIVE12_Msk (0x1UL << IPCT_INTPEND2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND2_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND2_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND2_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND2_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND2_RECEIVE13_Msk (0x1UL << IPCT_INTPEND2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND2_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND2_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND2_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND2_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND2_RECEIVE14_Msk (0x1UL << IPCT_INTPEND2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND2_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND2_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND2_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND2_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND2_RECEIVE15_Msk (0x1UL << IPCT_INTPEND2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND2_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND2_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND2_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND2_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND2_READY0_Msk (0x1UL << IPCT_INTPEND2_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND2_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND2_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND2_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND2_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND2_READY1_Msk (0x1UL << IPCT_INTPEND2_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND2_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND2_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND2_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND2_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND2_READY2_Msk (0x1UL << IPCT_INTPEND2_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND2_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND2_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND2_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND2_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND2_READY3_Msk (0x1UL << IPCT_INTPEND2_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND2_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND2_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND2_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND2_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND2_READY4_Msk (0x1UL << IPCT_INTPEND2_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND2_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND2_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND2_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND2_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND2_READY5_Msk (0x1UL << IPCT_INTPEND2_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND2_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND2_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND2_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND2_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND2_READY6_Msk (0x1UL << IPCT_INTPEND2_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND2_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND2_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND2_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND2_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND2_READY7_Msk (0x1UL << IPCT_INTPEND2_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND2_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND2_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND2_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND2_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND2_READY8_Msk (0x1UL << IPCT_INTPEND2_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND2_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND2_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND2_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND2_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND2_READY9_Msk (0x1UL << IPCT_INTPEND2_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND2_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND2_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND2_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND2_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND2_READY10_Msk (0x1UL << IPCT_INTPEND2_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND2_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND2_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND2_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND2_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND2_READY11_Msk (0x1UL << IPCT_INTPEND2_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND2_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND2_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND2_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND2_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND2_READY12_Msk (0x1UL << IPCT_INTPEND2_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND2_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND2_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND2_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND2_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND2_READY13_Msk (0x1UL << IPCT_INTPEND2_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND2_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND2_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND2_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND2_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND2_READY14_Msk (0x1UL << IPCT_INTPEND2_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND2_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND2_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND2_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND2_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND2_READY15_Msk (0x1UL << IPCT_INTPEND2_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND2_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND2_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND2_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND2_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN3: Enable or disable interrupt */ + #define IPCT_INTEN3_ResetValue (0x00000000UL) /*!< Reset value of INTEN3 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN3_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN3_RECEIVE0_Msk (0x1UL << IPCT_INTEN3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN3_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN3_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN3_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN3_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN3_RECEIVE1_Msk (0x1UL << IPCT_INTEN3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN3_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN3_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN3_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN3_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN3_RECEIVE2_Msk (0x1UL << IPCT_INTEN3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN3_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN3_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN3_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN3_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN3_RECEIVE3_Msk (0x1UL << IPCT_INTEN3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN3_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN3_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN3_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN3_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN3_RECEIVE4_Msk (0x1UL << IPCT_INTEN3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN3_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN3_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN3_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN3_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN3_RECEIVE5_Msk (0x1UL << IPCT_INTEN3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN3_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN3_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN3_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN3_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN3_RECEIVE6_Msk (0x1UL << IPCT_INTEN3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN3_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN3_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN3_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN3_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN3_RECEIVE7_Msk (0x1UL << IPCT_INTEN3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN3_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN3_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN3_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN3_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN3_RECEIVE8_Msk (0x1UL << IPCT_INTEN3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN3_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN3_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN3_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN3_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN3_RECEIVE9_Msk (0x1UL << IPCT_INTEN3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN3_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN3_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN3_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN3_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN3_RECEIVE10_Msk (0x1UL << IPCT_INTEN3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN3_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN3_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN3_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN3_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN3_RECEIVE11_Msk (0x1UL << IPCT_INTEN3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN3_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN3_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN3_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN3_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN3_RECEIVE12_Msk (0x1UL << IPCT_INTEN3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN3_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN3_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN3_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN3_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN3_RECEIVE13_Msk (0x1UL << IPCT_INTEN3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN3_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN3_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN3_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN3_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN3_RECEIVE14_Msk (0x1UL << IPCT_INTEN3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN3_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN3_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN3_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN3_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN3_RECEIVE15_Msk (0x1UL << IPCT_INTEN3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN3_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN3_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN3_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN3_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN3_READY0_Msk (0x1UL << IPCT_INTEN3_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN3_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN3_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN3_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN3_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN3_READY1_Msk (0x1UL << IPCT_INTEN3_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN3_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN3_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN3_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN3_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN3_READY2_Msk (0x1UL << IPCT_INTEN3_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN3_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN3_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN3_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN3_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN3_READY3_Msk (0x1UL << IPCT_INTEN3_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN3_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN3_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN3_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN3_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN3_READY4_Msk (0x1UL << IPCT_INTEN3_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN3_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN3_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN3_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN3_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN3_READY5_Msk (0x1UL << IPCT_INTEN3_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN3_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN3_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN3_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN3_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN3_READY6_Msk (0x1UL << IPCT_INTEN3_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN3_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN3_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN3_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN3_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN3_READY7_Msk (0x1UL << IPCT_INTEN3_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN3_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN3_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN3_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN3_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN3_READY8_Msk (0x1UL << IPCT_INTEN3_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN3_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN3_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN3_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN3_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN3_READY9_Msk (0x1UL << IPCT_INTEN3_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN3_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN3_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN3_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN3_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN3_READY10_Msk (0x1UL << IPCT_INTEN3_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN3_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN3_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN3_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN3_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN3_READY11_Msk (0x1UL << IPCT_INTEN3_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN3_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN3_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN3_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN3_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN3_READY12_Msk (0x1UL << IPCT_INTEN3_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN3_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN3_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN3_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN3_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN3_READY13_Msk (0x1UL << IPCT_INTEN3_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN3_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN3_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN3_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN3_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN3_READY14_Msk (0x1UL << IPCT_INTEN3_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN3_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN3_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN3_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN3_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN3_READY15_Msk (0x1UL << IPCT_INTEN3_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN3_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN3_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN3_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN3_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET3: Enable interrupt */ + #define IPCT_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET3_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET3_RECEIVE0_Msk (0x1UL << IPCT_INTENSET3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET3_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET3_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET3_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET3_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET3_RECEIVE1_Msk (0x1UL << IPCT_INTENSET3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET3_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET3_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET3_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET3_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET3_RECEIVE2_Msk (0x1UL << IPCT_INTENSET3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET3_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET3_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET3_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET3_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET3_RECEIVE3_Msk (0x1UL << IPCT_INTENSET3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET3_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET3_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET3_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET3_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET3_RECEIVE4_Msk (0x1UL << IPCT_INTENSET3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET3_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET3_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET3_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET3_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET3_RECEIVE5_Msk (0x1UL << IPCT_INTENSET3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET3_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET3_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET3_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET3_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET3_RECEIVE6_Msk (0x1UL << IPCT_INTENSET3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET3_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET3_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET3_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET3_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET3_RECEIVE7_Msk (0x1UL << IPCT_INTENSET3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET3_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET3_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET3_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET3_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET3_RECEIVE8_Msk (0x1UL << IPCT_INTENSET3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET3_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET3_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET3_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET3_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET3_RECEIVE9_Msk (0x1UL << IPCT_INTENSET3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET3_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET3_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET3_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET3_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET3_RECEIVE10_Msk (0x1UL << IPCT_INTENSET3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET3_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET3_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET3_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET3_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET3_RECEIVE11_Msk (0x1UL << IPCT_INTENSET3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET3_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET3_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET3_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET3_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET3_RECEIVE12_Msk (0x1UL << IPCT_INTENSET3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET3_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET3_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET3_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET3_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET3_RECEIVE13_Msk (0x1UL << IPCT_INTENSET3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET3_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET3_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET3_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET3_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET3_RECEIVE14_Msk (0x1UL << IPCT_INTENSET3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET3_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET3_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET3_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET3_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET3_RECEIVE15_Msk (0x1UL << IPCT_INTENSET3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET3_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET3_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET3_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET3_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET3_READY0_Msk (0x1UL << IPCT_INTENSET3_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET3_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET3_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET3_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET3_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET3_READY1_Msk (0x1UL << IPCT_INTENSET3_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET3_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET3_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET3_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET3_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET3_READY2_Msk (0x1UL << IPCT_INTENSET3_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET3_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET3_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET3_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET3_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET3_READY3_Msk (0x1UL << IPCT_INTENSET3_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET3_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET3_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET3_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET3_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET3_READY4_Msk (0x1UL << IPCT_INTENSET3_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET3_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET3_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET3_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET3_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET3_READY5_Msk (0x1UL << IPCT_INTENSET3_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET3_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET3_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET3_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET3_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET3_READY6_Msk (0x1UL << IPCT_INTENSET3_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET3_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET3_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET3_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET3_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET3_READY7_Msk (0x1UL << IPCT_INTENSET3_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET3_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET3_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET3_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET3_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET3_READY8_Msk (0x1UL << IPCT_INTENSET3_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET3_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET3_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET3_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET3_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET3_READY9_Msk (0x1UL << IPCT_INTENSET3_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET3_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET3_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET3_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET3_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET3_READY10_Msk (0x1UL << IPCT_INTENSET3_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET3_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET3_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET3_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET3_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET3_READY11_Msk (0x1UL << IPCT_INTENSET3_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET3_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET3_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET3_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET3_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET3_READY12_Msk (0x1UL << IPCT_INTENSET3_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET3_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET3_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET3_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET3_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET3_READY13_Msk (0x1UL << IPCT_INTENSET3_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET3_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET3_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET3_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET3_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET3_READY14_Msk (0x1UL << IPCT_INTENSET3_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET3_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET3_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET3_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET3_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET3_READY15_Msk (0x1UL << IPCT_INTENSET3_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET3_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET3_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET3_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET3_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET3_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR3: Disable interrupt */ + #define IPCT_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR3_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR3_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR3_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR3_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR3_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR3_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR3_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR3_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR3_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR3_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR3_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR3_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR3_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR3_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR3_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR3_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR3_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR3_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR3_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR3_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR3_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR3_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR3_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR3_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR3_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR3_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR3_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR3_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR3_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR3_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR3_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR3_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR3_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR3_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR3_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR3_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR3_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR3_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR3_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR3_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR3_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR3_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR3_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR3_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR3_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR3_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR3_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR3_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR3_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR3_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR3_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR3_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR3_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR3_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR3_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR3_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR3_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR3_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR3_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR3_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR3_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR3_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR3_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR3_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR3_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR3_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR3_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR3_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR3_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR3_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR3_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR3_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR3_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR3_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR3_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR3_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR3_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR3_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR3_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR3_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR3_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR3_READY0_Msk (0x1UL << IPCT_INTENCLR3_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR3_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR3_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR3_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR3_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR3_READY1_Msk (0x1UL << IPCT_INTENCLR3_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR3_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR3_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR3_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR3_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR3_READY2_Msk (0x1UL << IPCT_INTENCLR3_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR3_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR3_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR3_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR3_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR3_READY3_Msk (0x1UL << IPCT_INTENCLR3_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR3_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR3_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR3_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR3_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR3_READY4_Msk (0x1UL << IPCT_INTENCLR3_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR3_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR3_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR3_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR3_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR3_READY5_Msk (0x1UL << IPCT_INTENCLR3_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR3_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR3_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR3_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR3_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR3_READY6_Msk (0x1UL << IPCT_INTENCLR3_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR3_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR3_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR3_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR3_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR3_READY7_Msk (0x1UL << IPCT_INTENCLR3_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR3_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR3_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR3_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR3_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR3_READY8_Msk (0x1UL << IPCT_INTENCLR3_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR3_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR3_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR3_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR3_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR3_READY9_Msk (0x1UL << IPCT_INTENCLR3_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR3_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR3_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR3_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR3_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR3_READY10_Msk (0x1UL << IPCT_INTENCLR3_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR3_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR3_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR3_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR3_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR3_READY11_Msk (0x1UL << IPCT_INTENCLR3_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR3_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR3_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR3_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR3_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR3_READY12_Msk (0x1UL << IPCT_INTENCLR3_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR3_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR3_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR3_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR3_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR3_READY13_Msk (0x1UL << IPCT_INTENCLR3_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR3_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR3_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR3_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR3_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR3_READY14_Msk (0x1UL << IPCT_INTENCLR3_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR3_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR3_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR3_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR3_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR3_READY15_Msk (0x1UL << IPCT_INTENCLR3_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR3_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR3_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR3_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR3_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR3_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND3: Pending interrupts */ + #define IPCT_INTPEND3_ResetValue (0x00000000UL) /*!< Reset value of INTPEND3 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND3_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND3_RECEIVE0_Msk (0x1UL << IPCT_INTPEND3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND3_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND3_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND3_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND3_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND3_RECEIVE1_Msk (0x1UL << IPCT_INTPEND3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND3_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND3_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND3_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND3_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND3_RECEIVE2_Msk (0x1UL << IPCT_INTPEND3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND3_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND3_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND3_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND3_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND3_RECEIVE3_Msk (0x1UL << IPCT_INTPEND3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND3_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND3_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND3_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND3_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND3_RECEIVE4_Msk (0x1UL << IPCT_INTPEND3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND3_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND3_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND3_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND3_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND3_RECEIVE5_Msk (0x1UL << IPCT_INTPEND3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND3_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND3_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND3_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND3_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND3_RECEIVE6_Msk (0x1UL << IPCT_INTPEND3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND3_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND3_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND3_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND3_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND3_RECEIVE7_Msk (0x1UL << IPCT_INTPEND3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND3_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND3_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND3_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND3_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND3_RECEIVE8_Msk (0x1UL << IPCT_INTPEND3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND3_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND3_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND3_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND3_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND3_RECEIVE9_Msk (0x1UL << IPCT_INTPEND3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND3_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND3_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND3_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND3_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND3_RECEIVE10_Msk (0x1UL << IPCT_INTPEND3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND3_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND3_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND3_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND3_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND3_RECEIVE11_Msk (0x1UL << IPCT_INTPEND3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND3_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND3_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND3_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND3_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND3_RECEIVE12_Msk (0x1UL << IPCT_INTPEND3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND3_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND3_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND3_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND3_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND3_RECEIVE13_Msk (0x1UL << IPCT_INTPEND3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND3_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND3_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND3_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND3_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND3_RECEIVE14_Msk (0x1UL << IPCT_INTPEND3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND3_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND3_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND3_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND3_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND3_RECEIVE15_Msk (0x1UL << IPCT_INTPEND3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND3_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND3_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND3_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND3_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND3_READY0_Msk (0x1UL << IPCT_INTPEND3_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND3_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND3_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND3_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND3_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND3_READY1_Msk (0x1UL << IPCT_INTPEND3_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND3_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND3_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND3_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND3_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND3_READY2_Msk (0x1UL << IPCT_INTPEND3_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND3_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND3_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND3_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND3_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND3_READY3_Msk (0x1UL << IPCT_INTPEND3_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND3_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND3_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND3_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND3_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND3_READY4_Msk (0x1UL << IPCT_INTPEND3_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND3_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND3_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND3_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND3_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND3_READY5_Msk (0x1UL << IPCT_INTPEND3_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND3_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND3_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND3_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND3_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND3_READY6_Msk (0x1UL << IPCT_INTPEND3_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND3_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND3_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND3_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND3_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND3_READY7_Msk (0x1UL << IPCT_INTPEND3_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND3_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND3_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND3_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND3_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND3_READY8_Msk (0x1UL << IPCT_INTPEND3_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND3_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND3_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND3_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND3_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND3_READY9_Msk (0x1UL << IPCT_INTPEND3_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND3_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND3_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND3_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND3_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND3_READY10_Msk (0x1UL << IPCT_INTPEND3_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND3_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND3_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND3_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND3_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND3_READY11_Msk (0x1UL << IPCT_INTPEND3_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND3_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND3_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND3_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND3_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND3_READY12_Msk (0x1UL << IPCT_INTPEND3_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND3_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND3_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND3_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND3_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND3_READY13_Msk (0x1UL << IPCT_INTPEND3_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND3_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND3_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND3_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND3_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND3_READY14_Msk (0x1UL << IPCT_INTPEND3_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND3_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND3_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND3_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND3_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND3_READY15_Msk (0x1UL << IPCT_INTPEND3_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND3_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND3_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND3_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND3_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN4: Enable or disable interrupt */ + #define IPCT_INTEN4_ResetValue (0x00000000UL) /*!< Reset value of INTEN4 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN4_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN4_RECEIVE0_Msk (0x1UL << IPCT_INTEN4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN4_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN4_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN4_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN4_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN4_RECEIVE1_Msk (0x1UL << IPCT_INTEN4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN4_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN4_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN4_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN4_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN4_RECEIVE2_Msk (0x1UL << IPCT_INTEN4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN4_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN4_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN4_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN4_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN4_RECEIVE3_Msk (0x1UL << IPCT_INTEN4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN4_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN4_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN4_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN4_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN4_RECEIVE4_Msk (0x1UL << IPCT_INTEN4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN4_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN4_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN4_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN4_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN4_RECEIVE5_Msk (0x1UL << IPCT_INTEN4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN4_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN4_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN4_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN4_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN4_RECEIVE6_Msk (0x1UL << IPCT_INTEN4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN4_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN4_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN4_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN4_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN4_RECEIVE7_Msk (0x1UL << IPCT_INTEN4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN4_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN4_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN4_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN4_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN4_RECEIVE8_Msk (0x1UL << IPCT_INTEN4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN4_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN4_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN4_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN4_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN4_RECEIVE9_Msk (0x1UL << IPCT_INTEN4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN4_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN4_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN4_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN4_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN4_RECEIVE10_Msk (0x1UL << IPCT_INTEN4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN4_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN4_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN4_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN4_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN4_RECEIVE11_Msk (0x1UL << IPCT_INTEN4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN4_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN4_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN4_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN4_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN4_RECEIVE12_Msk (0x1UL << IPCT_INTEN4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN4_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN4_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN4_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN4_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN4_RECEIVE13_Msk (0x1UL << IPCT_INTEN4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN4_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN4_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN4_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN4_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN4_RECEIVE14_Msk (0x1UL << IPCT_INTEN4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN4_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN4_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN4_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN4_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN4_RECEIVE15_Msk (0x1UL << IPCT_INTEN4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN4_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN4_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN4_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN4_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN4_READY0_Msk (0x1UL << IPCT_INTEN4_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN4_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN4_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN4_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN4_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN4_READY1_Msk (0x1UL << IPCT_INTEN4_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN4_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN4_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN4_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN4_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN4_READY2_Msk (0x1UL << IPCT_INTEN4_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN4_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN4_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN4_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN4_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN4_READY3_Msk (0x1UL << IPCT_INTEN4_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN4_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN4_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN4_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN4_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN4_READY4_Msk (0x1UL << IPCT_INTEN4_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN4_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN4_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN4_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN4_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN4_READY5_Msk (0x1UL << IPCT_INTEN4_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN4_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN4_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN4_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN4_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN4_READY6_Msk (0x1UL << IPCT_INTEN4_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN4_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN4_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN4_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN4_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN4_READY7_Msk (0x1UL << IPCT_INTEN4_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN4_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN4_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN4_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN4_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN4_READY8_Msk (0x1UL << IPCT_INTEN4_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN4_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN4_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN4_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN4_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN4_READY9_Msk (0x1UL << IPCT_INTEN4_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN4_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN4_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN4_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN4_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN4_READY10_Msk (0x1UL << IPCT_INTEN4_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN4_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN4_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN4_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN4_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN4_READY11_Msk (0x1UL << IPCT_INTEN4_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN4_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN4_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN4_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN4_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN4_READY12_Msk (0x1UL << IPCT_INTEN4_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN4_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN4_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN4_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN4_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN4_READY13_Msk (0x1UL << IPCT_INTEN4_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN4_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN4_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN4_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN4_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN4_READY14_Msk (0x1UL << IPCT_INTEN4_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN4_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN4_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN4_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN4_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN4_READY15_Msk (0x1UL << IPCT_INTEN4_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN4_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN4_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN4_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN4_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET4: Enable interrupt */ + #define IPCT_INTENSET4_ResetValue (0x00000000UL) /*!< Reset value of INTENSET4 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET4_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET4_RECEIVE0_Msk (0x1UL << IPCT_INTENSET4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET4_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET4_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET4_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET4_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET4_RECEIVE1_Msk (0x1UL << IPCT_INTENSET4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET4_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET4_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET4_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET4_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET4_RECEIVE2_Msk (0x1UL << IPCT_INTENSET4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET4_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET4_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET4_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET4_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET4_RECEIVE3_Msk (0x1UL << IPCT_INTENSET4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET4_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET4_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET4_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET4_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET4_RECEIVE4_Msk (0x1UL << IPCT_INTENSET4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET4_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET4_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET4_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET4_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET4_RECEIVE5_Msk (0x1UL << IPCT_INTENSET4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET4_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET4_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET4_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET4_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET4_RECEIVE6_Msk (0x1UL << IPCT_INTENSET4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET4_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET4_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET4_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET4_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET4_RECEIVE7_Msk (0x1UL << IPCT_INTENSET4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET4_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET4_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET4_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET4_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET4_RECEIVE8_Msk (0x1UL << IPCT_INTENSET4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET4_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET4_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET4_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET4_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET4_RECEIVE9_Msk (0x1UL << IPCT_INTENSET4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET4_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET4_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET4_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET4_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET4_RECEIVE10_Msk (0x1UL << IPCT_INTENSET4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET4_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET4_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET4_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET4_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET4_RECEIVE11_Msk (0x1UL << IPCT_INTENSET4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET4_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET4_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET4_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET4_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET4_RECEIVE12_Msk (0x1UL << IPCT_INTENSET4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET4_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET4_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET4_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET4_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET4_RECEIVE13_Msk (0x1UL << IPCT_INTENSET4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET4_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET4_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET4_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET4_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET4_RECEIVE14_Msk (0x1UL << IPCT_INTENSET4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET4_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET4_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET4_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET4_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET4_RECEIVE15_Msk (0x1UL << IPCT_INTENSET4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET4_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET4_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET4_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET4_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET4_READY0_Msk (0x1UL << IPCT_INTENSET4_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET4_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET4_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET4_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET4_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET4_READY1_Msk (0x1UL << IPCT_INTENSET4_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET4_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET4_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET4_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET4_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET4_READY2_Msk (0x1UL << IPCT_INTENSET4_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET4_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET4_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET4_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET4_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET4_READY3_Msk (0x1UL << IPCT_INTENSET4_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET4_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET4_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET4_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET4_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET4_READY4_Msk (0x1UL << IPCT_INTENSET4_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET4_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET4_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET4_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET4_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET4_READY5_Msk (0x1UL << IPCT_INTENSET4_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET4_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET4_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET4_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET4_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET4_READY6_Msk (0x1UL << IPCT_INTENSET4_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET4_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET4_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET4_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET4_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET4_READY7_Msk (0x1UL << IPCT_INTENSET4_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET4_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET4_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET4_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET4_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET4_READY8_Msk (0x1UL << IPCT_INTENSET4_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET4_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET4_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET4_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET4_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET4_READY9_Msk (0x1UL << IPCT_INTENSET4_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET4_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET4_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET4_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET4_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET4_READY10_Msk (0x1UL << IPCT_INTENSET4_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET4_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET4_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET4_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET4_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET4_READY11_Msk (0x1UL << IPCT_INTENSET4_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET4_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET4_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET4_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET4_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET4_READY12_Msk (0x1UL << IPCT_INTENSET4_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET4_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET4_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET4_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET4_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET4_READY13_Msk (0x1UL << IPCT_INTENSET4_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET4_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET4_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET4_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET4_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET4_READY14_Msk (0x1UL << IPCT_INTENSET4_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET4_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET4_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET4_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET4_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET4_READY15_Msk (0x1UL << IPCT_INTENSET4_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET4_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET4_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET4_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET4_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET4_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR4: Disable interrupt */ + #define IPCT_INTENCLR4_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR4 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR4_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR4_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR4_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR4_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR4_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR4_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR4_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR4_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR4_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR4_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR4_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR4_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR4_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR4_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR4_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR4_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR4_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR4_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR4_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR4_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR4_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR4_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR4_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR4_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR4_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR4_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR4_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR4_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR4_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR4_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR4_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR4_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR4_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR4_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR4_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR4_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR4_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR4_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR4_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR4_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR4_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR4_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR4_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR4_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR4_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR4_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR4_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR4_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR4_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR4_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR4_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR4_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR4_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR4_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR4_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR4_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR4_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR4_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR4_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR4_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR4_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR4_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR4_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR4_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR4_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR4_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR4_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR4_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR4_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR4_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR4_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR4_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR4_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR4_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR4_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR4_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR4_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR4_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR4_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR4_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR4_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR4_READY0_Msk (0x1UL << IPCT_INTENCLR4_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR4_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR4_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR4_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR4_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR4_READY1_Msk (0x1UL << IPCT_INTENCLR4_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR4_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR4_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR4_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR4_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR4_READY2_Msk (0x1UL << IPCT_INTENCLR4_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR4_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR4_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR4_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR4_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR4_READY3_Msk (0x1UL << IPCT_INTENCLR4_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR4_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR4_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR4_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR4_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR4_READY4_Msk (0x1UL << IPCT_INTENCLR4_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR4_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR4_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR4_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR4_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR4_READY5_Msk (0x1UL << IPCT_INTENCLR4_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR4_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR4_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR4_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR4_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR4_READY6_Msk (0x1UL << IPCT_INTENCLR4_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR4_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR4_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR4_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR4_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR4_READY7_Msk (0x1UL << IPCT_INTENCLR4_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR4_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR4_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR4_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR4_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR4_READY8_Msk (0x1UL << IPCT_INTENCLR4_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR4_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR4_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR4_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR4_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR4_READY9_Msk (0x1UL << IPCT_INTENCLR4_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR4_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR4_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR4_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR4_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR4_READY10_Msk (0x1UL << IPCT_INTENCLR4_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR4_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR4_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR4_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR4_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR4_READY11_Msk (0x1UL << IPCT_INTENCLR4_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR4_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR4_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR4_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR4_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR4_READY12_Msk (0x1UL << IPCT_INTENCLR4_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR4_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR4_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR4_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR4_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR4_READY13_Msk (0x1UL << IPCT_INTENCLR4_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR4_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR4_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR4_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR4_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR4_READY14_Msk (0x1UL << IPCT_INTENCLR4_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR4_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR4_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR4_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR4_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR4_READY15_Msk (0x1UL << IPCT_INTENCLR4_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR4_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR4_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR4_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR4_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR4_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND4: Pending interrupts */ + #define IPCT_INTPEND4_ResetValue (0x00000000UL) /*!< Reset value of INTPEND4 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND4_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND4_RECEIVE0_Msk (0x1UL << IPCT_INTPEND4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND4_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND4_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND4_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND4_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND4_RECEIVE1_Msk (0x1UL << IPCT_INTPEND4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND4_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND4_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND4_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND4_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND4_RECEIVE2_Msk (0x1UL << IPCT_INTPEND4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND4_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND4_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND4_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND4_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND4_RECEIVE3_Msk (0x1UL << IPCT_INTPEND4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND4_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND4_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND4_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND4_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND4_RECEIVE4_Msk (0x1UL << IPCT_INTPEND4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND4_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND4_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND4_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND4_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND4_RECEIVE5_Msk (0x1UL << IPCT_INTPEND4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND4_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND4_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND4_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND4_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND4_RECEIVE6_Msk (0x1UL << IPCT_INTPEND4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND4_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND4_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND4_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND4_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND4_RECEIVE7_Msk (0x1UL << IPCT_INTPEND4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND4_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND4_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND4_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND4_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND4_RECEIVE8_Msk (0x1UL << IPCT_INTPEND4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND4_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND4_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND4_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND4_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND4_RECEIVE9_Msk (0x1UL << IPCT_INTPEND4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND4_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND4_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND4_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND4_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND4_RECEIVE10_Msk (0x1UL << IPCT_INTPEND4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND4_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND4_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND4_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND4_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND4_RECEIVE11_Msk (0x1UL << IPCT_INTPEND4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND4_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND4_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND4_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND4_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND4_RECEIVE12_Msk (0x1UL << IPCT_INTPEND4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND4_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND4_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND4_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND4_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND4_RECEIVE13_Msk (0x1UL << IPCT_INTPEND4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND4_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND4_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND4_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND4_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND4_RECEIVE14_Msk (0x1UL << IPCT_INTPEND4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND4_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND4_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND4_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND4_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND4_RECEIVE15_Msk (0x1UL << IPCT_INTPEND4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND4_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND4_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND4_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND4_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND4_READY0_Msk (0x1UL << IPCT_INTPEND4_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND4_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND4_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND4_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND4_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND4_READY1_Msk (0x1UL << IPCT_INTPEND4_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND4_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND4_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND4_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND4_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND4_READY2_Msk (0x1UL << IPCT_INTPEND4_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND4_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND4_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND4_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND4_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND4_READY3_Msk (0x1UL << IPCT_INTPEND4_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND4_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND4_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND4_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND4_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND4_READY4_Msk (0x1UL << IPCT_INTPEND4_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND4_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND4_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND4_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND4_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND4_READY5_Msk (0x1UL << IPCT_INTPEND4_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND4_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND4_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND4_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND4_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND4_READY6_Msk (0x1UL << IPCT_INTPEND4_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND4_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND4_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND4_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND4_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND4_READY7_Msk (0x1UL << IPCT_INTPEND4_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND4_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND4_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND4_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND4_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND4_READY8_Msk (0x1UL << IPCT_INTPEND4_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND4_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND4_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND4_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND4_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND4_READY9_Msk (0x1UL << IPCT_INTPEND4_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND4_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND4_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND4_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND4_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND4_READY10_Msk (0x1UL << IPCT_INTPEND4_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND4_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND4_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND4_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND4_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND4_READY11_Msk (0x1UL << IPCT_INTPEND4_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND4_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND4_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND4_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND4_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND4_READY12_Msk (0x1UL << IPCT_INTPEND4_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND4_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND4_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND4_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND4_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND4_READY13_Msk (0x1UL << IPCT_INTPEND4_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND4_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND4_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND4_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND4_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND4_READY14_Msk (0x1UL << IPCT_INTPEND4_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND4_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND4_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND4_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND4_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND4_READY15_Msk (0x1UL << IPCT_INTPEND4_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND4_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND4_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND4_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND4_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN5: Enable or disable interrupt */ + #define IPCT_INTEN5_ResetValue (0x00000000UL) /*!< Reset value of INTEN5 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN5_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN5_RECEIVE0_Msk (0x1UL << IPCT_INTEN5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN5_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN5_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN5_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN5_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN5_RECEIVE1_Msk (0x1UL << IPCT_INTEN5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN5_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN5_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN5_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN5_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN5_RECEIVE2_Msk (0x1UL << IPCT_INTEN5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN5_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN5_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN5_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN5_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN5_RECEIVE3_Msk (0x1UL << IPCT_INTEN5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN5_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN5_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN5_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN5_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN5_RECEIVE4_Msk (0x1UL << IPCT_INTEN5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN5_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN5_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN5_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN5_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN5_RECEIVE5_Msk (0x1UL << IPCT_INTEN5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN5_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN5_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN5_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN5_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN5_RECEIVE6_Msk (0x1UL << IPCT_INTEN5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN5_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN5_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN5_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN5_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN5_RECEIVE7_Msk (0x1UL << IPCT_INTEN5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN5_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN5_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN5_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN5_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN5_RECEIVE8_Msk (0x1UL << IPCT_INTEN5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN5_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN5_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN5_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN5_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN5_RECEIVE9_Msk (0x1UL << IPCT_INTEN5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN5_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN5_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN5_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN5_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN5_RECEIVE10_Msk (0x1UL << IPCT_INTEN5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN5_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN5_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN5_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN5_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN5_RECEIVE11_Msk (0x1UL << IPCT_INTEN5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN5_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN5_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN5_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN5_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN5_RECEIVE12_Msk (0x1UL << IPCT_INTEN5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN5_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN5_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN5_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN5_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN5_RECEIVE13_Msk (0x1UL << IPCT_INTEN5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN5_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN5_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN5_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN5_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN5_RECEIVE14_Msk (0x1UL << IPCT_INTEN5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN5_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN5_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN5_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN5_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN5_RECEIVE15_Msk (0x1UL << IPCT_INTEN5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN5_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN5_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN5_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN5_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN5_READY0_Msk (0x1UL << IPCT_INTEN5_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN5_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN5_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN5_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN5_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN5_READY1_Msk (0x1UL << IPCT_INTEN5_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN5_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN5_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN5_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN5_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN5_READY2_Msk (0x1UL << IPCT_INTEN5_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN5_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN5_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN5_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN5_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN5_READY3_Msk (0x1UL << IPCT_INTEN5_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN5_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN5_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN5_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN5_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN5_READY4_Msk (0x1UL << IPCT_INTEN5_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN5_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN5_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN5_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN5_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN5_READY5_Msk (0x1UL << IPCT_INTEN5_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN5_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN5_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN5_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN5_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN5_READY6_Msk (0x1UL << IPCT_INTEN5_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN5_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN5_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN5_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN5_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN5_READY7_Msk (0x1UL << IPCT_INTEN5_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN5_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN5_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN5_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN5_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN5_READY8_Msk (0x1UL << IPCT_INTEN5_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN5_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN5_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN5_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN5_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN5_READY9_Msk (0x1UL << IPCT_INTEN5_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN5_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN5_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN5_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN5_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN5_READY10_Msk (0x1UL << IPCT_INTEN5_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN5_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN5_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN5_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN5_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN5_READY11_Msk (0x1UL << IPCT_INTEN5_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN5_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN5_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN5_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN5_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN5_READY12_Msk (0x1UL << IPCT_INTEN5_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN5_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN5_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN5_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN5_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN5_READY13_Msk (0x1UL << IPCT_INTEN5_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN5_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN5_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN5_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN5_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN5_READY14_Msk (0x1UL << IPCT_INTEN5_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN5_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN5_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN5_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN5_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN5_READY15_Msk (0x1UL << IPCT_INTEN5_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN5_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN5_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN5_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN5_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET5: Enable interrupt */ + #define IPCT_INTENSET5_ResetValue (0x00000000UL) /*!< Reset value of INTENSET5 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET5_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET5_RECEIVE0_Msk (0x1UL << IPCT_INTENSET5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET5_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET5_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET5_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET5_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET5_RECEIVE1_Msk (0x1UL << IPCT_INTENSET5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET5_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET5_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET5_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET5_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET5_RECEIVE2_Msk (0x1UL << IPCT_INTENSET5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET5_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET5_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET5_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET5_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET5_RECEIVE3_Msk (0x1UL << IPCT_INTENSET5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET5_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET5_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET5_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET5_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET5_RECEIVE4_Msk (0x1UL << IPCT_INTENSET5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET5_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET5_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET5_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET5_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET5_RECEIVE5_Msk (0x1UL << IPCT_INTENSET5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET5_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET5_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET5_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET5_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET5_RECEIVE6_Msk (0x1UL << IPCT_INTENSET5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET5_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET5_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET5_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET5_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET5_RECEIVE7_Msk (0x1UL << IPCT_INTENSET5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET5_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET5_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET5_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET5_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET5_RECEIVE8_Msk (0x1UL << IPCT_INTENSET5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET5_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET5_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET5_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET5_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET5_RECEIVE9_Msk (0x1UL << IPCT_INTENSET5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET5_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET5_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET5_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET5_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET5_RECEIVE10_Msk (0x1UL << IPCT_INTENSET5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET5_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET5_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET5_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET5_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET5_RECEIVE11_Msk (0x1UL << IPCT_INTENSET5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET5_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET5_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET5_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET5_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET5_RECEIVE12_Msk (0x1UL << IPCT_INTENSET5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET5_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET5_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET5_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET5_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET5_RECEIVE13_Msk (0x1UL << IPCT_INTENSET5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET5_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET5_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET5_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET5_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET5_RECEIVE14_Msk (0x1UL << IPCT_INTENSET5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET5_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET5_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET5_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET5_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET5_RECEIVE15_Msk (0x1UL << IPCT_INTENSET5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET5_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET5_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET5_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET5_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET5_READY0_Msk (0x1UL << IPCT_INTENSET5_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET5_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET5_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET5_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET5_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET5_READY1_Msk (0x1UL << IPCT_INTENSET5_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET5_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET5_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET5_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET5_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET5_READY2_Msk (0x1UL << IPCT_INTENSET5_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET5_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET5_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET5_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET5_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET5_READY3_Msk (0x1UL << IPCT_INTENSET5_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET5_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET5_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET5_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET5_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET5_READY4_Msk (0x1UL << IPCT_INTENSET5_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET5_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET5_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET5_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET5_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET5_READY5_Msk (0x1UL << IPCT_INTENSET5_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET5_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET5_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET5_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET5_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET5_READY6_Msk (0x1UL << IPCT_INTENSET5_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET5_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET5_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET5_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET5_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET5_READY7_Msk (0x1UL << IPCT_INTENSET5_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET5_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET5_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET5_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET5_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET5_READY8_Msk (0x1UL << IPCT_INTENSET5_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET5_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET5_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET5_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET5_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET5_READY9_Msk (0x1UL << IPCT_INTENSET5_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET5_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET5_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET5_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET5_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET5_READY10_Msk (0x1UL << IPCT_INTENSET5_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET5_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET5_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET5_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET5_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET5_READY11_Msk (0x1UL << IPCT_INTENSET5_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET5_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET5_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET5_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET5_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET5_READY12_Msk (0x1UL << IPCT_INTENSET5_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET5_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET5_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET5_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET5_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET5_READY13_Msk (0x1UL << IPCT_INTENSET5_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET5_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET5_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET5_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET5_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET5_READY14_Msk (0x1UL << IPCT_INTENSET5_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET5_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET5_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET5_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET5_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET5_READY15_Msk (0x1UL << IPCT_INTENSET5_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET5_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET5_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET5_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET5_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET5_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR5: Disable interrupt */ + #define IPCT_INTENCLR5_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR5 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR5_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR5_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR5_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR5_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR5_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR5_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR5_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR5_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR5_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR5_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR5_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR5_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR5_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR5_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR5_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR5_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR5_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR5_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR5_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR5_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR5_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR5_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR5_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR5_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR5_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR5_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR5_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR5_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR5_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR5_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR5_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR5_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR5_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR5_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR5_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR5_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR5_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR5_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR5_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR5_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR5_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR5_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR5_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR5_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR5_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR5_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR5_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR5_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR5_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR5_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR5_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR5_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR5_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR5_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR5_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR5_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR5_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR5_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR5_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR5_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR5_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR5_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR5_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR5_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR5_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR5_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR5_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR5_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR5_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR5_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR5_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR5_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR5_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR5_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR5_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR5_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR5_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR5_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR5_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR5_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR5_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR5_READY0_Msk (0x1UL << IPCT_INTENCLR5_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR5_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR5_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR5_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR5_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR5_READY1_Msk (0x1UL << IPCT_INTENCLR5_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR5_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR5_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR5_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR5_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR5_READY2_Msk (0x1UL << IPCT_INTENCLR5_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR5_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR5_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR5_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR5_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR5_READY3_Msk (0x1UL << IPCT_INTENCLR5_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR5_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR5_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR5_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR5_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR5_READY4_Msk (0x1UL << IPCT_INTENCLR5_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR5_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR5_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR5_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR5_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR5_READY5_Msk (0x1UL << IPCT_INTENCLR5_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR5_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR5_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR5_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR5_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR5_READY6_Msk (0x1UL << IPCT_INTENCLR5_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR5_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR5_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR5_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR5_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR5_READY7_Msk (0x1UL << IPCT_INTENCLR5_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR5_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR5_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR5_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR5_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR5_READY8_Msk (0x1UL << IPCT_INTENCLR5_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR5_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR5_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR5_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR5_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR5_READY9_Msk (0x1UL << IPCT_INTENCLR5_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR5_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR5_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR5_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR5_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR5_READY10_Msk (0x1UL << IPCT_INTENCLR5_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR5_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR5_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR5_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR5_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR5_READY11_Msk (0x1UL << IPCT_INTENCLR5_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR5_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR5_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR5_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR5_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR5_READY12_Msk (0x1UL << IPCT_INTENCLR5_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR5_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR5_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR5_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR5_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR5_READY13_Msk (0x1UL << IPCT_INTENCLR5_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR5_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR5_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR5_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR5_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR5_READY14_Msk (0x1UL << IPCT_INTENCLR5_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR5_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR5_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR5_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR5_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR5_READY15_Msk (0x1UL << IPCT_INTENCLR5_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR5_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR5_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR5_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR5_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR5_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND5: Pending interrupts */ + #define IPCT_INTPEND5_ResetValue (0x00000000UL) /*!< Reset value of INTPEND5 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND5_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND5_RECEIVE0_Msk (0x1UL << IPCT_INTPEND5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND5_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND5_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND5_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND5_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND5_RECEIVE1_Msk (0x1UL << IPCT_INTPEND5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND5_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND5_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND5_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND5_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND5_RECEIVE2_Msk (0x1UL << IPCT_INTPEND5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND5_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND5_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND5_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND5_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND5_RECEIVE3_Msk (0x1UL << IPCT_INTPEND5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND5_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND5_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND5_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND5_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND5_RECEIVE4_Msk (0x1UL << IPCT_INTPEND5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND5_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND5_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND5_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND5_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND5_RECEIVE5_Msk (0x1UL << IPCT_INTPEND5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND5_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND5_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND5_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND5_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND5_RECEIVE6_Msk (0x1UL << IPCT_INTPEND5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND5_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND5_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND5_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND5_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND5_RECEIVE7_Msk (0x1UL << IPCT_INTPEND5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND5_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND5_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND5_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND5_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND5_RECEIVE8_Msk (0x1UL << IPCT_INTPEND5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND5_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND5_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND5_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND5_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND5_RECEIVE9_Msk (0x1UL << IPCT_INTPEND5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND5_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND5_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND5_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND5_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND5_RECEIVE10_Msk (0x1UL << IPCT_INTPEND5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND5_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND5_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND5_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND5_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND5_RECEIVE11_Msk (0x1UL << IPCT_INTPEND5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND5_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND5_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND5_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND5_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND5_RECEIVE12_Msk (0x1UL << IPCT_INTPEND5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND5_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND5_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND5_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND5_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND5_RECEIVE13_Msk (0x1UL << IPCT_INTPEND5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND5_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND5_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND5_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND5_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND5_RECEIVE14_Msk (0x1UL << IPCT_INTPEND5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND5_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND5_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND5_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND5_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND5_RECEIVE15_Msk (0x1UL << IPCT_INTPEND5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND5_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND5_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND5_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND5_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND5_READY0_Msk (0x1UL << IPCT_INTPEND5_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND5_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND5_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND5_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND5_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND5_READY1_Msk (0x1UL << IPCT_INTPEND5_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND5_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND5_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND5_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND5_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND5_READY2_Msk (0x1UL << IPCT_INTPEND5_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND5_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND5_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND5_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND5_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND5_READY3_Msk (0x1UL << IPCT_INTPEND5_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND5_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND5_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND5_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND5_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND5_READY4_Msk (0x1UL << IPCT_INTPEND5_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND5_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND5_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND5_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND5_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND5_READY5_Msk (0x1UL << IPCT_INTPEND5_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND5_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND5_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND5_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND5_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND5_READY6_Msk (0x1UL << IPCT_INTPEND5_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND5_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND5_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND5_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND5_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND5_READY7_Msk (0x1UL << IPCT_INTPEND5_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND5_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND5_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND5_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND5_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND5_READY8_Msk (0x1UL << IPCT_INTPEND5_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND5_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND5_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND5_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND5_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND5_READY9_Msk (0x1UL << IPCT_INTPEND5_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND5_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND5_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND5_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND5_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND5_READY10_Msk (0x1UL << IPCT_INTPEND5_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND5_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND5_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND5_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND5_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND5_READY11_Msk (0x1UL << IPCT_INTPEND5_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND5_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND5_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND5_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND5_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND5_READY12_Msk (0x1UL << IPCT_INTPEND5_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND5_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND5_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND5_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND5_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND5_READY13_Msk (0x1UL << IPCT_INTPEND5_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND5_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND5_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND5_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND5_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND5_READY14_Msk (0x1UL << IPCT_INTPEND5_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND5_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND5_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND5_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND5_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND5_READY15_Msk (0x1UL << IPCT_INTPEND5_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND5_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND5_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND5_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND5_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN6: Enable or disable interrupt */ + #define IPCT_INTEN6_ResetValue (0x00000000UL) /*!< Reset value of INTEN6 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN6_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN6_RECEIVE0_Msk (0x1UL << IPCT_INTEN6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN6_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN6_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN6_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN6_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN6_RECEIVE1_Msk (0x1UL << IPCT_INTEN6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN6_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN6_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN6_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN6_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN6_RECEIVE2_Msk (0x1UL << IPCT_INTEN6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN6_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN6_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN6_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN6_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN6_RECEIVE3_Msk (0x1UL << IPCT_INTEN6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN6_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN6_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN6_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN6_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN6_RECEIVE4_Msk (0x1UL << IPCT_INTEN6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN6_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN6_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN6_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN6_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN6_RECEIVE5_Msk (0x1UL << IPCT_INTEN6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN6_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN6_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN6_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN6_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN6_RECEIVE6_Msk (0x1UL << IPCT_INTEN6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN6_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN6_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN6_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN6_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN6_RECEIVE7_Msk (0x1UL << IPCT_INTEN6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN6_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN6_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN6_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN6_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN6_RECEIVE8_Msk (0x1UL << IPCT_INTEN6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN6_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN6_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN6_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN6_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN6_RECEIVE9_Msk (0x1UL << IPCT_INTEN6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN6_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN6_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN6_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN6_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN6_RECEIVE10_Msk (0x1UL << IPCT_INTEN6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN6_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN6_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN6_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN6_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN6_RECEIVE11_Msk (0x1UL << IPCT_INTEN6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN6_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN6_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN6_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN6_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN6_RECEIVE12_Msk (0x1UL << IPCT_INTEN6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN6_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN6_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN6_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN6_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN6_RECEIVE13_Msk (0x1UL << IPCT_INTEN6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN6_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN6_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN6_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN6_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN6_RECEIVE14_Msk (0x1UL << IPCT_INTEN6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN6_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN6_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN6_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN6_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN6_RECEIVE15_Msk (0x1UL << IPCT_INTEN6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN6_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN6_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN6_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN6_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN6_READY0_Msk (0x1UL << IPCT_INTEN6_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN6_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN6_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN6_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN6_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN6_READY1_Msk (0x1UL << IPCT_INTEN6_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN6_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN6_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN6_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN6_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN6_READY2_Msk (0x1UL << IPCT_INTEN6_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN6_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN6_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN6_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN6_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN6_READY3_Msk (0x1UL << IPCT_INTEN6_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN6_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN6_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN6_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN6_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN6_READY4_Msk (0x1UL << IPCT_INTEN6_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN6_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN6_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN6_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN6_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN6_READY5_Msk (0x1UL << IPCT_INTEN6_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN6_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN6_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN6_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN6_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN6_READY6_Msk (0x1UL << IPCT_INTEN6_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN6_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN6_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN6_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN6_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN6_READY7_Msk (0x1UL << IPCT_INTEN6_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN6_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN6_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN6_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN6_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN6_READY8_Msk (0x1UL << IPCT_INTEN6_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN6_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN6_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN6_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN6_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN6_READY9_Msk (0x1UL << IPCT_INTEN6_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN6_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN6_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN6_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN6_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN6_READY10_Msk (0x1UL << IPCT_INTEN6_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN6_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN6_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN6_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN6_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN6_READY11_Msk (0x1UL << IPCT_INTEN6_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN6_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN6_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN6_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN6_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN6_READY12_Msk (0x1UL << IPCT_INTEN6_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN6_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN6_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN6_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN6_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN6_READY13_Msk (0x1UL << IPCT_INTEN6_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN6_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN6_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN6_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN6_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN6_READY14_Msk (0x1UL << IPCT_INTEN6_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN6_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN6_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN6_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN6_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN6_READY15_Msk (0x1UL << IPCT_INTEN6_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN6_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN6_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN6_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN6_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET6: Enable interrupt */ + #define IPCT_INTENSET6_ResetValue (0x00000000UL) /*!< Reset value of INTENSET6 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET6_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET6_RECEIVE0_Msk (0x1UL << IPCT_INTENSET6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET6_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET6_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET6_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET6_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET6_RECEIVE1_Msk (0x1UL << IPCT_INTENSET6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET6_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET6_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET6_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET6_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET6_RECEIVE2_Msk (0x1UL << IPCT_INTENSET6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET6_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET6_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET6_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET6_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET6_RECEIVE3_Msk (0x1UL << IPCT_INTENSET6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET6_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET6_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET6_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET6_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET6_RECEIVE4_Msk (0x1UL << IPCT_INTENSET6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET6_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET6_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET6_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET6_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET6_RECEIVE5_Msk (0x1UL << IPCT_INTENSET6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET6_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET6_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET6_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET6_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET6_RECEIVE6_Msk (0x1UL << IPCT_INTENSET6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET6_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET6_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET6_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET6_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET6_RECEIVE7_Msk (0x1UL << IPCT_INTENSET6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET6_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET6_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET6_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET6_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET6_RECEIVE8_Msk (0x1UL << IPCT_INTENSET6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET6_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET6_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET6_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET6_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET6_RECEIVE9_Msk (0x1UL << IPCT_INTENSET6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET6_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET6_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET6_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET6_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET6_RECEIVE10_Msk (0x1UL << IPCT_INTENSET6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET6_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET6_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET6_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET6_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET6_RECEIVE11_Msk (0x1UL << IPCT_INTENSET6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET6_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET6_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET6_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET6_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET6_RECEIVE12_Msk (0x1UL << IPCT_INTENSET6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET6_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET6_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET6_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET6_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET6_RECEIVE13_Msk (0x1UL << IPCT_INTENSET6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET6_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET6_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET6_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET6_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET6_RECEIVE14_Msk (0x1UL << IPCT_INTENSET6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET6_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET6_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET6_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET6_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET6_RECEIVE15_Msk (0x1UL << IPCT_INTENSET6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET6_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET6_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET6_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET6_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET6_READY0_Msk (0x1UL << IPCT_INTENSET6_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET6_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET6_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET6_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET6_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET6_READY1_Msk (0x1UL << IPCT_INTENSET6_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET6_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET6_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET6_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET6_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET6_READY2_Msk (0x1UL << IPCT_INTENSET6_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET6_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET6_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET6_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET6_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET6_READY3_Msk (0x1UL << IPCT_INTENSET6_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET6_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET6_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET6_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET6_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET6_READY4_Msk (0x1UL << IPCT_INTENSET6_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET6_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET6_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET6_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET6_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET6_READY5_Msk (0x1UL << IPCT_INTENSET6_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET6_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET6_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET6_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET6_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET6_READY6_Msk (0x1UL << IPCT_INTENSET6_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET6_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET6_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET6_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET6_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET6_READY7_Msk (0x1UL << IPCT_INTENSET6_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET6_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET6_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET6_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET6_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET6_READY8_Msk (0x1UL << IPCT_INTENSET6_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET6_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET6_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET6_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET6_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET6_READY9_Msk (0x1UL << IPCT_INTENSET6_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET6_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET6_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET6_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET6_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET6_READY10_Msk (0x1UL << IPCT_INTENSET6_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET6_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET6_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET6_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET6_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET6_READY11_Msk (0x1UL << IPCT_INTENSET6_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET6_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET6_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET6_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET6_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET6_READY12_Msk (0x1UL << IPCT_INTENSET6_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET6_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET6_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET6_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET6_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET6_READY13_Msk (0x1UL << IPCT_INTENSET6_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET6_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET6_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET6_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET6_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET6_READY14_Msk (0x1UL << IPCT_INTENSET6_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET6_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET6_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET6_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET6_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET6_READY15_Msk (0x1UL << IPCT_INTENSET6_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET6_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET6_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET6_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET6_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET6_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR6: Disable interrupt */ + #define IPCT_INTENCLR6_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR6 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR6_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR6_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR6_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR6_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR6_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR6_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR6_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR6_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR6_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR6_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR6_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR6_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR6_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR6_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR6_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR6_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR6_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR6_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR6_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR6_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR6_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR6_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR6_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR6_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR6_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR6_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR6_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR6_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR6_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR6_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR6_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR6_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR6_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR6_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR6_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR6_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR6_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR6_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR6_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR6_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR6_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR6_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR6_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR6_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR6_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR6_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR6_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR6_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR6_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR6_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR6_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR6_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR6_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR6_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR6_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR6_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR6_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR6_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR6_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR6_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR6_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR6_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR6_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR6_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR6_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR6_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR6_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR6_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR6_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR6_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR6_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR6_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR6_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR6_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR6_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR6_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR6_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR6_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR6_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR6_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR6_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR6_READY0_Msk (0x1UL << IPCT_INTENCLR6_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR6_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR6_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR6_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR6_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR6_READY1_Msk (0x1UL << IPCT_INTENCLR6_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR6_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR6_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR6_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR6_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR6_READY2_Msk (0x1UL << IPCT_INTENCLR6_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR6_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR6_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR6_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR6_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR6_READY3_Msk (0x1UL << IPCT_INTENCLR6_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR6_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR6_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR6_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR6_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR6_READY4_Msk (0x1UL << IPCT_INTENCLR6_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR6_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR6_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR6_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR6_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR6_READY5_Msk (0x1UL << IPCT_INTENCLR6_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR6_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR6_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR6_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR6_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR6_READY6_Msk (0x1UL << IPCT_INTENCLR6_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR6_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR6_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR6_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR6_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR6_READY7_Msk (0x1UL << IPCT_INTENCLR6_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR6_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR6_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR6_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR6_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR6_READY8_Msk (0x1UL << IPCT_INTENCLR6_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR6_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR6_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR6_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR6_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR6_READY9_Msk (0x1UL << IPCT_INTENCLR6_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR6_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR6_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR6_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR6_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR6_READY10_Msk (0x1UL << IPCT_INTENCLR6_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR6_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR6_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR6_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR6_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR6_READY11_Msk (0x1UL << IPCT_INTENCLR6_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR6_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR6_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR6_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR6_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR6_READY12_Msk (0x1UL << IPCT_INTENCLR6_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR6_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR6_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR6_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR6_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR6_READY13_Msk (0x1UL << IPCT_INTENCLR6_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR6_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR6_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR6_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR6_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR6_READY14_Msk (0x1UL << IPCT_INTENCLR6_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR6_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR6_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR6_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR6_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR6_READY15_Msk (0x1UL << IPCT_INTENCLR6_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR6_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR6_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR6_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR6_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR6_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND6: Pending interrupts */ + #define IPCT_INTPEND6_ResetValue (0x00000000UL) /*!< Reset value of INTPEND6 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND6_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND6_RECEIVE0_Msk (0x1UL << IPCT_INTPEND6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND6_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND6_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND6_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND6_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND6_RECEIVE1_Msk (0x1UL << IPCT_INTPEND6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND6_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND6_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND6_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND6_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND6_RECEIVE2_Msk (0x1UL << IPCT_INTPEND6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND6_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND6_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND6_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND6_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND6_RECEIVE3_Msk (0x1UL << IPCT_INTPEND6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND6_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND6_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND6_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND6_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND6_RECEIVE4_Msk (0x1UL << IPCT_INTPEND6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND6_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND6_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND6_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND6_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND6_RECEIVE5_Msk (0x1UL << IPCT_INTPEND6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND6_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND6_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND6_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND6_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND6_RECEIVE6_Msk (0x1UL << IPCT_INTPEND6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND6_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND6_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND6_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND6_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND6_RECEIVE7_Msk (0x1UL << IPCT_INTPEND6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND6_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND6_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND6_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND6_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND6_RECEIVE8_Msk (0x1UL << IPCT_INTPEND6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND6_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND6_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND6_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND6_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND6_RECEIVE9_Msk (0x1UL << IPCT_INTPEND6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND6_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND6_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND6_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND6_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND6_RECEIVE10_Msk (0x1UL << IPCT_INTPEND6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND6_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND6_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND6_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND6_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND6_RECEIVE11_Msk (0x1UL << IPCT_INTPEND6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND6_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND6_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND6_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND6_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND6_RECEIVE12_Msk (0x1UL << IPCT_INTPEND6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND6_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND6_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND6_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND6_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND6_RECEIVE13_Msk (0x1UL << IPCT_INTPEND6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND6_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND6_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND6_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND6_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND6_RECEIVE14_Msk (0x1UL << IPCT_INTPEND6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND6_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND6_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND6_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND6_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND6_RECEIVE15_Msk (0x1UL << IPCT_INTPEND6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND6_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND6_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND6_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND6_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND6_READY0_Msk (0x1UL << IPCT_INTPEND6_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND6_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND6_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND6_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND6_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND6_READY1_Msk (0x1UL << IPCT_INTPEND6_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND6_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND6_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND6_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND6_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND6_READY2_Msk (0x1UL << IPCT_INTPEND6_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND6_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND6_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND6_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND6_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND6_READY3_Msk (0x1UL << IPCT_INTPEND6_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND6_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND6_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND6_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND6_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND6_READY4_Msk (0x1UL << IPCT_INTPEND6_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND6_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND6_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND6_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND6_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND6_READY5_Msk (0x1UL << IPCT_INTPEND6_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND6_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND6_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND6_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND6_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND6_READY6_Msk (0x1UL << IPCT_INTPEND6_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND6_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND6_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND6_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND6_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND6_READY7_Msk (0x1UL << IPCT_INTPEND6_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND6_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND6_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND6_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND6_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND6_READY8_Msk (0x1UL << IPCT_INTPEND6_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND6_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND6_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND6_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND6_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND6_READY9_Msk (0x1UL << IPCT_INTPEND6_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND6_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND6_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND6_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND6_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND6_READY10_Msk (0x1UL << IPCT_INTPEND6_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND6_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND6_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND6_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND6_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND6_READY11_Msk (0x1UL << IPCT_INTPEND6_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND6_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND6_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND6_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND6_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND6_READY12_Msk (0x1UL << IPCT_INTPEND6_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND6_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND6_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND6_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND6_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND6_READY13_Msk (0x1UL << IPCT_INTPEND6_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND6_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND6_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND6_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND6_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND6_READY14_Msk (0x1UL << IPCT_INTPEND6_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND6_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND6_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND6_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND6_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND6_READY15_Msk (0x1UL << IPCT_INTPEND6_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND6_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND6_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND6_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND6_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +/* IPCT_INTEN7: Enable or disable interrupt */ + #define IPCT_INTEN7_ResetValue (0x00000000UL) /*!< Reset value of INTEN7 register. */ + +/* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ + #define IPCT_INTEN7_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTEN7_RECEIVE0_Msk (0x1UL << IPCT_INTEN7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTEN7_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN7_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTEN7_RECEIVE0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE0_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ + #define IPCT_INTEN7_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTEN7_RECEIVE1_Msk (0x1UL << IPCT_INTEN7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTEN7_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN7_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTEN7_RECEIVE1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE1_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ + #define IPCT_INTEN7_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTEN7_RECEIVE2_Msk (0x1UL << IPCT_INTEN7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTEN7_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN7_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTEN7_RECEIVE2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE2_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ + #define IPCT_INTEN7_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTEN7_RECEIVE3_Msk (0x1UL << IPCT_INTEN7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTEN7_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN7_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTEN7_RECEIVE3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE3_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ + #define IPCT_INTEN7_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTEN7_RECEIVE4_Msk (0x1UL << IPCT_INTEN7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTEN7_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN7_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTEN7_RECEIVE4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE4_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ + #define IPCT_INTEN7_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTEN7_RECEIVE5_Msk (0x1UL << IPCT_INTEN7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTEN7_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN7_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTEN7_RECEIVE5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE5_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ + #define IPCT_INTEN7_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTEN7_RECEIVE6_Msk (0x1UL << IPCT_INTEN7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTEN7_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN7_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTEN7_RECEIVE6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE6_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ + #define IPCT_INTEN7_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTEN7_RECEIVE7_Msk (0x1UL << IPCT_INTEN7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTEN7_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN7_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTEN7_RECEIVE7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE7_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */ + #define IPCT_INTEN7_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTEN7_RECEIVE8_Msk (0x1UL << IPCT_INTEN7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTEN7_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN7_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTEN7_RECEIVE8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE8_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */ + #define IPCT_INTEN7_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTEN7_RECEIVE9_Msk (0x1UL << IPCT_INTEN7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTEN7_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN7_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTEN7_RECEIVE9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE9_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */ + #define IPCT_INTEN7_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTEN7_RECEIVE10_Msk (0x1UL << IPCT_INTEN7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTEN7_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN7_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTEN7_RECEIVE10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE10_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */ + #define IPCT_INTEN7_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTEN7_RECEIVE11_Msk (0x1UL << IPCT_INTEN7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTEN7_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN7_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTEN7_RECEIVE11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE11_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */ + #define IPCT_INTEN7_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTEN7_RECEIVE12_Msk (0x1UL << IPCT_INTEN7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTEN7_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN7_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTEN7_RECEIVE12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE12_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */ + #define IPCT_INTEN7_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTEN7_RECEIVE13_Msk (0x1UL << IPCT_INTEN7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTEN7_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN7_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTEN7_RECEIVE13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE13_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */ + #define IPCT_INTEN7_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTEN7_RECEIVE14_Msk (0x1UL << IPCT_INTEN7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTEN7_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN7_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTEN7_RECEIVE14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE14_Enabled (0x1UL) /*!< Enable */ + +/* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */ + #define IPCT_INTEN7_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTEN7_RECEIVE15_Msk (0x1UL << IPCT_INTEN7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTEN7_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN7_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTEN7_RECEIVE15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_RECEIVE15_Enabled (0x1UL) /*!< Enable */ + +/* READY0 @Bit 16 : Enable or disable interrupt for event READY[0] */ + #define IPCT_INTEN7_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTEN7_READY0_Msk (0x1UL << IPCT_INTEN7_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTEN7_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTEN7_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTEN7_READY0_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY0_Enabled (0x1UL) /*!< Enable */ + +/* READY1 @Bit 17 : Enable or disable interrupt for event READY[1] */ + #define IPCT_INTEN7_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTEN7_READY1_Msk (0x1UL << IPCT_INTEN7_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTEN7_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTEN7_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTEN7_READY1_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY1_Enabled (0x1UL) /*!< Enable */ + +/* READY2 @Bit 18 : Enable or disable interrupt for event READY[2] */ + #define IPCT_INTEN7_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTEN7_READY2_Msk (0x1UL << IPCT_INTEN7_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTEN7_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTEN7_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTEN7_READY2_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY2_Enabled (0x1UL) /*!< Enable */ + +/* READY3 @Bit 19 : Enable or disable interrupt for event READY[3] */ + #define IPCT_INTEN7_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTEN7_READY3_Msk (0x1UL << IPCT_INTEN7_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTEN7_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTEN7_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTEN7_READY3_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY3_Enabled (0x1UL) /*!< Enable */ + +/* READY4 @Bit 20 : Enable or disable interrupt for event READY[4] */ + #define IPCT_INTEN7_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTEN7_READY4_Msk (0x1UL << IPCT_INTEN7_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTEN7_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTEN7_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTEN7_READY4_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY4_Enabled (0x1UL) /*!< Enable */ + +/* READY5 @Bit 21 : Enable or disable interrupt for event READY[5] */ + #define IPCT_INTEN7_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTEN7_READY5_Msk (0x1UL << IPCT_INTEN7_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTEN7_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTEN7_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTEN7_READY5_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY5_Enabled (0x1UL) /*!< Enable */ + +/* READY6 @Bit 22 : Enable or disable interrupt for event READY[6] */ + #define IPCT_INTEN7_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTEN7_READY6_Msk (0x1UL << IPCT_INTEN7_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTEN7_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTEN7_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTEN7_READY6_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY6_Enabled (0x1UL) /*!< Enable */ + +/* READY7 @Bit 23 : Enable or disable interrupt for event READY[7] */ + #define IPCT_INTEN7_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTEN7_READY7_Msk (0x1UL << IPCT_INTEN7_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTEN7_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTEN7_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTEN7_READY7_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY7_Enabled (0x1UL) /*!< Enable */ + +/* READY8 @Bit 24 : Enable or disable interrupt for event READY[8] */ + #define IPCT_INTEN7_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTEN7_READY8_Msk (0x1UL << IPCT_INTEN7_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTEN7_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTEN7_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTEN7_READY8_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY8_Enabled (0x1UL) /*!< Enable */ + +/* READY9 @Bit 25 : Enable or disable interrupt for event READY[9] */ + #define IPCT_INTEN7_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTEN7_READY9_Msk (0x1UL << IPCT_INTEN7_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTEN7_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTEN7_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTEN7_READY9_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY9_Enabled (0x1UL) /*!< Enable */ + +/* READY10 @Bit 26 : Enable or disable interrupt for event READY[10] */ + #define IPCT_INTEN7_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTEN7_READY10_Msk (0x1UL << IPCT_INTEN7_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTEN7_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTEN7_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTEN7_READY10_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY10_Enabled (0x1UL) /*!< Enable */ + +/* READY11 @Bit 27 : Enable or disable interrupt for event READY[11] */ + #define IPCT_INTEN7_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTEN7_READY11_Msk (0x1UL << IPCT_INTEN7_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTEN7_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTEN7_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTEN7_READY11_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY11_Enabled (0x1UL) /*!< Enable */ + +/* READY12 @Bit 28 : Enable or disable interrupt for event READY[12] */ + #define IPCT_INTEN7_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTEN7_READY12_Msk (0x1UL << IPCT_INTEN7_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTEN7_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTEN7_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTEN7_READY12_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY12_Enabled (0x1UL) /*!< Enable */ + +/* READY13 @Bit 29 : Enable or disable interrupt for event READY[13] */ + #define IPCT_INTEN7_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTEN7_READY13_Msk (0x1UL << IPCT_INTEN7_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTEN7_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTEN7_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTEN7_READY13_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY13_Enabled (0x1UL) /*!< Enable */ + +/* READY14 @Bit 30 : Enable or disable interrupt for event READY[14] */ + #define IPCT_INTEN7_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTEN7_READY14_Msk (0x1UL << IPCT_INTEN7_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTEN7_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTEN7_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTEN7_READY14_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY14_Enabled (0x1UL) /*!< Enable */ + +/* READY15 @Bit 31 : Enable or disable interrupt for event READY[15] */ + #define IPCT_INTEN7_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTEN7_READY15_Msk (0x1UL << IPCT_INTEN7_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTEN7_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTEN7_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTEN7_READY15_Disabled (0x0UL) /*!< Disable */ + #define IPCT_INTEN7_READY15_Enabled (0x1UL) /*!< Enable */ + + +/* IPCT_INTENSET7: Enable interrupt */ + #define IPCT_INTENSET7_ResetValue (0x00000000UL) /*!< Reset value of INTENSET7 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ + #define IPCT_INTENSET7_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENSET7_RECEIVE0_Msk (0x1UL << IPCT_INTENSET7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENSET7_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET7_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENSET7_RECEIVE0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ + #define IPCT_INTENSET7_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENSET7_RECEIVE1_Msk (0x1UL << IPCT_INTENSET7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENSET7_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET7_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENSET7_RECEIVE1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ + #define IPCT_INTENSET7_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENSET7_RECEIVE2_Msk (0x1UL << IPCT_INTENSET7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENSET7_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET7_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENSET7_RECEIVE2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ + #define IPCT_INTENSET7_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENSET7_RECEIVE3_Msk (0x1UL << IPCT_INTENSET7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENSET7_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET7_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENSET7_RECEIVE3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ + #define IPCT_INTENSET7_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENSET7_RECEIVE4_Msk (0x1UL << IPCT_INTENSET7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENSET7_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET7_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENSET7_RECEIVE4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ + #define IPCT_INTENSET7_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENSET7_RECEIVE5_Msk (0x1UL << IPCT_INTENSET7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENSET7_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET7_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENSET7_RECEIVE5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ + #define IPCT_INTENSET7_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENSET7_RECEIVE6_Msk (0x1UL << IPCT_INTENSET7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENSET7_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET7_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENSET7_RECEIVE6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ + #define IPCT_INTENSET7_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENSET7_RECEIVE7_Msk (0x1UL << IPCT_INTENSET7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENSET7_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET7_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENSET7_RECEIVE7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */ + #define IPCT_INTENSET7_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENSET7_RECEIVE8_Msk (0x1UL << IPCT_INTENSET7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENSET7_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET7_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENSET7_RECEIVE8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */ + #define IPCT_INTENSET7_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENSET7_RECEIVE9_Msk (0x1UL << IPCT_INTENSET7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENSET7_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET7_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENSET7_RECEIVE9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */ + #define IPCT_INTENSET7_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENSET7_RECEIVE10_Msk (0x1UL << IPCT_INTENSET7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENSET7_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET7_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENSET7_RECEIVE10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */ + #define IPCT_INTENSET7_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENSET7_RECEIVE11_Msk (0x1UL << IPCT_INTENSET7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENSET7_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET7_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENSET7_RECEIVE11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */ + #define IPCT_INTENSET7_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENSET7_RECEIVE12_Msk (0x1UL << IPCT_INTENSET7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENSET7_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET7_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENSET7_RECEIVE12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */ + #define IPCT_INTENSET7_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENSET7_RECEIVE13_Msk (0x1UL << IPCT_INTENSET7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENSET7_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET7_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENSET7_RECEIVE13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */ + #define IPCT_INTENSET7_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENSET7_RECEIVE14_Msk (0x1UL << IPCT_INTENSET7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENSET7_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET7_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENSET7_RECEIVE14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */ + #define IPCT_INTENSET7_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENSET7_RECEIVE15_Msk (0x1UL << IPCT_INTENSET7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENSET7_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET7_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENSET7_RECEIVE15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to enable interrupt for event READY[0] */ + #define IPCT_INTENSET7_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENSET7_READY0_Msk (0x1UL << IPCT_INTENSET7_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENSET7_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENSET7_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENSET7_READY0_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to enable interrupt for event READY[1] */ + #define IPCT_INTENSET7_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENSET7_READY1_Msk (0x1UL << IPCT_INTENSET7_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENSET7_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENSET7_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENSET7_READY1_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to enable interrupt for event READY[2] */ + #define IPCT_INTENSET7_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENSET7_READY2_Msk (0x1UL << IPCT_INTENSET7_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENSET7_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENSET7_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENSET7_READY2_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to enable interrupt for event READY[3] */ + #define IPCT_INTENSET7_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENSET7_READY3_Msk (0x1UL << IPCT_INTENSET7_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENSET7_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENSET7_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENSET7_READY3_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to enable interrupt for event READY[4] */ + #define IPCT_INTENSET7_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENSET7_READY4_Msk (0x1UL << IPCT_INTENSET7_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENSET7_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENSET7_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENSET7_READY4_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to enable interrupt for event READY[5] */ + #define IPCT_INTENSET7_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENSET7_READY5_Msk (0x1UL << IPCT_INTENSET7_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENSET7_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENSET7_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENSET7_READY5_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to enable interrupt for event READY[6] */ + #define IPCT_INTENSET7_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENSET7_READY6_Msk (0x1UL << IPCT_INTENSET7_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENSET7_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENSET7_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENSET7_READY6_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to enable interrupt for event READY[7] */ + #define IPCT_INTENSET7_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENSET7_READY7_Msk (0x1UL << IPCT_INTENSET7_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENSET7_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENSET7_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENSET7_READY7_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to enable interrupt for event READY[8] */ + #define IPCT_INTENSET7_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENSET7_READY8_Msk (0x1UL << IPCT_INTENSET7_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENSET7_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENSET7_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENSET7_READY8_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to enable interrupt for event READY[9] */ + #define IPCT_INTENSET7_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENSET7_READY9_Msk (0x1UL << IPCT_INTENSET7_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENSET7_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENSET7_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENSET7_READY9_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to enable interrupt for event READY[10] */ + #define IPCT_INTENSET7_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENSET7_READY10_Msk (0x1UL << IPCT_INTENSET7_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENSET7_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENSET7_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENSET7_READY10_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to enable interrupt for event READY[11] */ + #define IPCT_INTENSET7_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENSET7_READY11_Msk (0x1UL << IPCT_INTENSET7_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENSET7_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENSET7_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENSET7_READY11_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to enable interrupt for event READY[12] */ + #define IPCT_INTENSET7_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENSET7_READY12_Msk (0x1UL << IPCT_INTENSET7_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENSET7_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENSET7_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENSET7_READY12_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to enable interrupt for event READY[13] */ + #define IPCT_INTENSET7_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENSET7_READY13_Msk (0x1UL << IPCT_INTENSET7_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENSET7_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENSET7_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENSET7_READY13_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to enable interrupt for event READY[14] */ + #define IPCT_INTENSET7_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENSET7_READY14_Msk (0x1UL << IPCT_INTENSET7_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENSET7_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENSET7_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENSET7_READY14_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to enable interrupt for event READY[15] */ + #define IPCT_INTENSET7_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENSET7_READY15_Msk (0x1UL << IPCT_INTENSET7_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENSET7_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENSET7_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENSET7_READY15_Set (0x1UL) /*!< Enable */ + #define IPCT_INTENSET7_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENSET7_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTENCLR7: Disable interrupt */ + #define IPCT_INTENCLR7_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR7 register. */ + +/* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ + #define IPCT_INTENCLR7_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTENCLR7_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTENCLR7_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR7_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTENCLR7_RECEIVE0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ + #define IPCT_INTENCLR7_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTENCLR7_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTENCLR7_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR7_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTENCLR7_RECEIVE1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ + #define IPCT_INTENCLR7_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTENCLR7_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTENCLR7_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR7_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTENCLR7_RECEIVE2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ + #define IPCT_INTENCLR7_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTENCLR7_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTENCLR7_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR7_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTENCLR7_RECEIVE3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ + #define IPCT_INTENCLR7_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTENCLR7_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTENCLR7_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR7_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTENCLR7_RECEIVE4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ + #define IPCT_INTENCLR7_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTENCLR7_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTENCLR7_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR7_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTENCLR7_RECEIVE5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ + #define IPCT_INTENCLR7_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTENCLR7_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTENCLR7_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR7_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTENCLR7_RECEIVE6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ + #define IPCT_INTENCLR7_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTENCLR7_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTENCLR7_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR7_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTENCLR7_RECEIVE7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */ + #define IPCT_INTENCLR7_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTENCLR7_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTENCLR7_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR7_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTENCLR7_RECEIVE8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */ + #define IPCT_INTENCLR7_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTENCLR7_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTENCLR7_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR7_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTENCLR7_RECEIVE9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */ + #define IPCT_INTENCLR7_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTENCLR7_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTENCLR7_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR7_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTENCLR7_RECEIVE10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */ + #define IPCT_INTENCLR7_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTENCLR7_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTENCLR7_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR7_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTENCLR7_RECEIVE11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */ + #define IPCT_INTENCLR7_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTENCLR7_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTENCLR7_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR7_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTENCLR7_RECEIVE12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */ + #define IPCT_INTENCLR7_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTENCLR7_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTENCLR7_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR7_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTENCLR7_RECEIVE13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */ + #define IPCT_INTENCLR7_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTENCLR7_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTENCLR7_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR7_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTENCLR7_RECEIVE14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */ + #define IPCT_INTENCLR7_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTENCLR7_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTENCLR7_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR7_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTENCLR7_RECEIVE15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_RECEIVE15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_RECEIVE15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY0 @Bit 16 : Write '1' to disable interrupt for event READY[0] */ + #define IPCT_INTENCLR7_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTENCLR7_READY0_Msk (0x1UL << IPCT_INTENCLR7_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTENCLR7_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTENCLR7_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTENCLR7_READY0_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY0_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY1 @Bit 17 : Write '1' to disable interrupt for event READY[1] */ + #define IPCT_INTENCLR7_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTENCLR7_READY1_Msk (0x1UL << IPCT_INTENCLR7_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTENCLR7_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTENCLR7_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTENCLR7_READY1_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY1_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY2 @Bit 18 : Write '1' to disable interrupt for event READY[2] */ + #define IPCT_INTENCLR7_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTENCLR7_READY2_Msk (0x1UL << IPCT_INTENCLR7_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTENCLR7_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTENCLR7_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTENCLR7_READY2_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY2_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY3 @Bit 19 : Write '1' to disable interrupt for event READY[3] */ + #define IPCT_INTENCLR7_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTENCLR7_READY3_Msk (0x1UL << IPCT_INTENCLR7_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTENCLR7_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTENCLR7_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTENCLR7_READY3_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY3_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY4 @Bit 20 : Write '1' to disable interrupt for event READY[4] */ + #define IPCT_INTENCLR7_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTENCLR7_READY4_Msk (0x1UL << IPCT_INTENCLR7_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTENCLR7_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTENCLR7_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTENCLR7_READY4_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY4_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY5 @Bit 21 : Write '1' to disable interrupt for event READY[5] */ + #define IPCT_INTENCLR7_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTENCLR7_READY5_Msk (0x1UL << IPCT_INTENCLR7_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTENCLR7_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTENCLR7_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTENCLR7_READY5_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY5_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY6 @Bit 22 : Write '1' to disable interrupt for event READY[6] */ + #define IPCT_INTENCLR7_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTENCLR7_READY6_Msk (0x1UL << IPCT_INTENCLR7_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTENCLR7_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTENCLR7_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTENCLR7_READY6_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY6_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY7 @Bit 23 : Write '1' to disable interrupt for event READY[7] */ + #define IPCT_INTENCLR7_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTENCLR7_READY7_Msk (0x1UL << IPCT_INTENCLR7_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTENCLR7_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTENCLR7_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTENCLR7_READY7_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY7_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY8 @Bit 24 : Write '1' to disable interrupt for event READY[8] */ + #define IPCT_INTENCLR7_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTENCLR7_READY8_Msk (0x1UL << IPCT_INTENCLR7_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTENCLR7_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTENCLR7_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTENCLR7_READY8_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY8_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY9 @Bit 25 : Write '1' to disable interrupt for event READY[9] */ + #define IPCT_INTENCLR7_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTENCLR7_READY9_Msk (0x1UL << IPCT_INTENCLR7_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTENCLR7_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTENCLR7_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTENCLR7_READY9_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY9_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY10 @Bit 26 : Write '1' to disable interrupt for event READY[10] */ + #define IPCT_INTENCLR7_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTENCLR7_READY10_Msk (0x1UL << IPCT_INTENCLR7_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTENCLR7_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTENCLR7_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTENCLR7_READY10_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY10_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY11 @Bit 27 : Write '1' to disable interrupt for event READY[11] */ + #define IPCT_INTENCLR7_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTENCLR7_READY11_Msk (0x1UL << IPCT_INTENCLR7_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTENCLR7_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTENCLR7_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTENCLR7_READY11_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY11_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY12 @Bit 28 : Write '1' to disable interrupt for event READY[12] */ + #define IPCT_INTENCLR7_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTENCLR7_READY12_Msk (0x1UL << IPCT_INTENCLR7_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTENCLR7_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTENCLR7_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTENCLR7_READY12_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY12_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY13 @Bit 29 : Write '1' to disable interrupt for event READY[13] */ + #define IPCT_INTENCLR7_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTENCLR7_READY13_Msk (0x1UL << IPCT_INTENCLR7_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTENCLR7_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTENCLR7_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTENCLR7_READY13_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY13_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY14 @Bit 30 : Write '1' to disable interrupt for event READY[14] */ + #define IPCT_INTENCLR7_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTENCLR7_READY14_Msk (0x1UL << IPCT_INTENCLR7_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTENCLR7_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTENCLR7_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTENCLR7_READY14_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY14_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READY15 @Bit 31 : Write '1' to disable interrupt for event READY[15] */ + #define IPCT_INTENCLR7_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTENCLR7_READY15_Msk (0x1UL << IPCT_INTENCLR7_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTENCLR7_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTENCLR7_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTENCLR7_READY15_Clear (0x1UL) /*!< Disable */ + #define IPCT_INTENCLR7_READY15_Disabled (0x0UL) /*!< Read: Disabled */ + #define IPCT_INTENCLR7_READY15_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* IPCT_INTPEND7: Pending interrupts */ + #define IPCT_INTPEND7_ResetValue (0x00000000UL) /*!< Reset value of INTPEND7 register. */ + +/* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ + #define IPCT_INTPEND7_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ + #define IPCT_INTPEND7_RECEIVE0_Msk (0x1UL << IPCT_INTPEND7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ + #define IPCT_INTPEND7_RECEIVE0_Min (0x0UL) /*!< Min enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND7_RECEIVE0_Max (0x1UL) /*!< Max enumerator value of RECEIVE0 field. */ + #define IPCT_INTPEND7_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ + #define IPCT_INTPEND7_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ + #define IPCT_INTPEND7_RECEIVE1_Msk (0x1UL << IPCT_INTPEND7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ + #define IPCT_INTPEND7_RECEIVE1_Min (0x0UL) /*!< Min enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND7_RECEIVE1_Max (0x1UL) /*!< Max enumerator value of RECEIVE1 field. */ + #define IPCT_INTPEND7_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ + #define IPCT_INTPEND7_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ + #define IPCT_INTPEND7_RECEIVE2_Msk (0x1UL << IPCT_INTPEND7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ + #define IPCT_INTPEND7_RECEIVE2_Min (0x0UL) /*!< Min enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND7_RECEIVE2_Max (0x1UL) /*!< Max enumerator value of RECEIVE2 field. */ + #define IPCT_INTPEND7_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ + #define IPCT_INTPEND7_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ + #define IPCT_INTPEND7_RECEIVE3_Msk (0x1UL << IPCT_INTPEND7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ + #define IPCT_INTPEND7_RECEIVE3_Min (0x0UL) /*!< Min enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND7_RECEIVE3_Max (0x1UL) /*!< Max enumerator value of RECEIVE3 field. */ + #define IPCT_INTPEND7_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ + #define IPCT_INTPEND7_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ + #define IPCT_INTPEND7_RECEIVE4_Msk (0x1UL << IPCT_INTPEND7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ + #define IPCT_INTPEND7_RECEIVE4_Min (0x0UL) /*!< Min enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND7_RECEIVE4_Max (0x1UL) /*!< Max enumerator value of RECEIVE4 field. */ + #define IPCT_INTPEND7_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ + #define IPCT_INTPEND7_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ + #define IPCT_INTPEND7_RECEIVE5_Msk (0x1UL << IPCT_INTPEND7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ + #define IPCT_INTPEND7_RECEIVE5_Min (0x0UL) /*!< Min enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND7_RECEIVE5_Max (0x1UL) /*!< Max enumerator value of RECEIVE5 field. */ + #define IPCT_INTPEND7_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ + #define IPCT_INTPEND7_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ + #define IPCT_INTPEND7_RECEIVE6_Msk (0x1UL << IPCT_INTPEND7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ + #define IPCT_INTPEND7_RECEIVE6_Min (0x0UL) /*!< Min enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND7_RECEIVE6_Max (0x1UL) /*!< Max enumerator value of RECEIVE6 field. */ + #define IPCT_INTPEND7_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ + #define IPCT_INTPEND7_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ + #define IPCT_INTPEND7_RECEIVE7_Msk (0x1UL << IPCT_INTPEND7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ + #define IPCT_INTPEND7_RECEIVE7_Min (0x0UL) /*!< Min enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND7_RECEIVE7_Max (0x1UL) /*!< Max enumerator value of RECEIVE7 field. */ + #define IPCT_INTPEND7_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */ + #define IPCT_INTPEND7_RECEIVE8_Pos (8UL) /*!< Position of RECEIVE8 field. */ + #define IPCT_INTPEND7_RECEIVE8_Msk (0x1UL << IPCT_INTPEND7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field. */ + #define IPCT_INTPEND7_RECEIVE8_Min (0x0UL) /*!< Min enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND7_RECEIVE8_Max (0x1UL) /*!< Max enumerator value of RECEIVE8 field. */ + #define IPCT_INTPEND7_RECEIVE8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE8_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */ + #define IPCT_INTPEND7_RECEIVE9_Pos (9UL) /*!< Position of RECEIVE9 field. */ + #define IPCT_INTPEND7_RECEIVE9_Msk (0x1UL << IPCT_INTPEND7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field. */ + #define IPCT_INTPEND7_RECEIVE9_Min (0x0UL) /*!< Min enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND7_RECEIVE9_Max (0x1UL) /*!< Max enumerator value of RECEIVE9 field. */ + #define IPCT_INTPEND7_RECEIVE9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE9_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */ + #define IPCT_INTPEND7_RECEIVE10_Pos (10UL) /*!< Position of RECEIVE10 field. */ + #define IPCT_INTPEND7_RECEIVE10_Msk (0x1UL << IPCT_INTPEND7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field. */ + #define IPCT_INTPEND7_RECEIVE10_Min (0x0UL) /*!< Min enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND7_RECEIVE10_Max (0x1UL) /*!< Max enumerator value of RECEIVE10 field. */ + #define IPCT_INTPEND7_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE10_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */ + #define IPCT_INTPEND7_RECEIVE11_Pos (11UL) /*!< Position of RECEIVE11 field. */ + #define IPCT_INTPEND7_RECEIVE11_Msk (0x1UL << IPCT_INTPEND7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field. */ + #define IPCT_INTPEND7_RECEIVE11_Min (0x0UL) /*!< Min enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND7_RECEIVE11_Max (0x1UL) /*!< Max enumerator value of RECEIVE11 field. */ + #define IPCT_INTPEND7_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE11_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */ + #define IPCT_INTPEND7_RECEIVE12_Pos (12UL) /*!< Position of RECEIVE12 field. */ + #define IPCT_INTPEND7_RECEIVE12_Msk (0x1UL << IPCT_INTPEND7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field. */ + #define IPCT_INTPEND7_RECEIVE12_Min (0x0UL) /*!< Min enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND7_RECEIVE12_Max (0x1UL) /*!< Max enumerator value of RECEIVE12 field. */ + #define IPCT_INTPEND7_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE12_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */ + #define IPCT_INTPEND7_RECEIVE13_Pos (13UL) /*!< Position of RECEIVE13 field. */ + #define IPCT_INTPEND7_RECEIVE13_Msk (0x1UL << IPCT_INTPEND7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field. */ + #define IPCT_INTPEND7_RECEIVE13_Min (0x0UL) /*!< Min enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND7_RECEIVE13_Max (0x1UL) /*!< Max enumerator value of RECEIVE13 field. */ + #define IPCT_INTPEND7_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE13_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */ + #define IPCT_INTPEND7_RECEIVE14_Pos (14UL) /*!< Position of RECEIVE14 field. */ + #define IPCT_INTPEND7_RECEIVE14_Msk (0x1UL << IPCT_INTPEND7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field. */ + #define IPCT_INTPEND7_RECEIVE14_Min (0x0UL) /*!< Min enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND7_RECEIVE14_Max (0x1UL) /*!< Max enumerator value of RECEIVE14 field. */ + #define IPCT_INTPEND7_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE14_Pending (0x1UL) /*!< Read: Pending */ + +/* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */ + #define IPCT_INTPEND7_RECEIVE15_Pos (15UL) /*!< Position of RECEIVE15 field. */ + #define IPCT_INTPEND7_RECEIVE15_Msk (0x1UL << IPCT_INTPEND7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field. */ + #define IPCT_INTPEND7_RECEIVE15_Min (0x0UL) /*!< Min enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND7_RECEIVE15_Max (0x1UL) /*!< Max enumerator value of RECEIVE15 field. */ + #define IPCT_INTPEND7_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_RECEIVE15_Pending (0x1UL) /*!< Read: Pending */ + +/* READY0 @Bit 16 : Read pending status of interrupt for event READY[0] */ + #define IPCT_INTPEND7_READY0_Pos (16UL) /*!< Position of READY0 field. */ + #define IPCT_INTPEND7_READY0_Msk (0x1UL << IPCT_INTPEND7_READY0_Pos) /*!< Bit mask of READY0 field. */ + #define IPCT_INTPEND7_READY0_Min (0x0UL) /*!< Min enumerator value of READY0 field. */ + #define IPCT_INTPEND7_READY0_Max (0x1UL) /*!< Max enumerator value of READY0 field. */ + #define IPCT_INTPEND7_READY0_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY0_Pending (0x1UL) /*!< Read: Pending */ + +/* READY1 @Bit 17 : Read pending status of interrupt for event READY[1] */ + #define IPCT_INTPEND7_READY1_Pos (17UL) /*!< Position of READY1 field. */ + #define IPCT_INTPEND7_READY1_Msk (0x1UL << IPCT_INTPEND7_READY1_Pos) /*!< Bit mask of READY1 field. */ + #define IPCT_INTPEND7_READY1_Min (0x0UL) /*!< Min enumerator value of READY1 field. */ + #define IPCT_INTPEND7_READY1_Max (0x1UL) /*!< Max enumerator value of READY1 field. */ + #define IPCT_INTPEND7_READY1_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY1_Pending (0x1UL) /*!< Read: Pending */ + +/* READY2 @Bit 18 : Read pending status of interrupt for event READY[2] */ + #define IPCT_INTPEND7_READY2_Pos (18UL) /*!< Position of READY2 field. */ + #define IPCT_INTPEND7_READY2_Msk (0x1UL << IPCT_INTPEND7_READY2_Pos) /*!< Bit mask of READY2 field. */ + #define IPCT_INTPEND7_READY2_Min (0x0UL) /*!< Min enumerator value of READY2 field. */ + #define IPCT_INTPEND7_READY2_Max (0x1UL) /*!< Max enumerator value of READY2 field. */ + #define IPCT_INTPEND7_READY2_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY2_Pending (0x1UL) /*!< Read: Pending */ + +/* READY3 @Bit 19 : Read pending status of interrupt for event READY[3] */ + #define IPCT_INTPEND7_READY3_Pos (19UL) /*!< Position of READY3 field. */ + #define IPCT_INTPEND7_READY3_Msk (0x1UL << IPCT_INTPEND7_READY3_Pos) /*!< Bit mask of READY3 field. */ + #define IPCT_INTPEND7_READY3_Min (0x0UL) /*!< Min enumerator value of READY3 field. */ + #define IPCT_INTPEND7_READY3_Max (0x1UL) /*!< Max enumerator value of READY3 field. */ + #define IPCT_INTPEND7_READY3_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY3_Pending (0x1UL) /*!< Read: Pending */ + +/* READY4 @Bit 20 : Read pending status of interrupt for event READY[4] */ + #define IPCT_INTPEND7_READY4_Pos (20UL) /*!< Position of READY4 field. */ + #define IPCT_INTPEND7_READY4_Msk (0x1UL << IPCT_INTPEND7_READY4_Pos) /*!< Bit mask of READY4 field. */ + #define IPCT_INTPEND7_READY4_Min (0x0UL) /*!< Min enumerator value of READY4 field. */ + #define IPCT_INTPEND7_READY4_Max (0x1UL) /*!< Max enumerator value of READY4 field. */ + #define IPCT_INTPEND7_READY4_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY4_Pending (0x1UL) /*!< Read: Pending */ + +/* READY5 @Bit 21 : Read pending status of interrupt for event READY[5] */ + #define IPCT_INTPEND7_READY5_Pos (21UL) /*!< Position of READY5 field. */ + #define IPCT_INTPEND7_READY5_Msk (0x1UL << IPCT_INTPEND7_READY5_Pos) /*!< Bit mask of READY5 field. */ + #define IPCT_INTPEND7_READY5_Min (0x0UL) /*!< Min enumerator value of READY5 field. */ + #define IPCT_INTPEND7_READY5_Max (0x1UL) /*!< Max enumerator value of READY5 field. */ + #define IPCT_INTPEND7_READY5_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY5_Pending (0x1UL) /*!< Read: Pending */ + +/* READY6 @Bit 22 : Read pending status of interrupt for event READY[6] */ + #define IPCT_INTPEND7_READY6_Pos (22UL) /*!< Position of READY6 field. */ + #define IPCT_INTPEND7_READY6_Msk (0x1UL << IPCT_INTPEND7_READY6_Pos) /*!< Bit mask of READY6 field. */ + #define IPCT_INTPEND7_READY6_Min (0x0UL) /*!< Min enumerator value of READY6 field. */ + #define IPCT_INTPEND7_READY6_Max (0x1UL) /*!< Max enumerator value of READY6 field. */ + #define IPCT_INTPEND7_READY6_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY6_Pending (0x1UL) /*!< Read: Pending */ + +/* READY7 @Bit 23 : Read pending status of interrupt for event READY[7] */ + #define IPCT_INTPEND7_READY7_Pos (23UL) /*!< Position of READY7 field. */ + #define IPCT_INTPEND7_READY7_Msk (0x1UL << IPCT_INTPEND7_READY7_Pos) /*!< Bit mask of READY7 field. */ + #define IPCT_INTPEND7_READY7_Min (0x0UL) /*!< Min enumerator value of READY7 field. */ + #define IPCT_INTPEND7_READY7_Max (0x1UL) /*!< Max enumerator value of READY7 field. */ + #define IPCT_INTPEND7_READY7_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY7_Pending (0x1UL) /*!< Read: Pending */ + +/* READY8 @Bit 24 : Read pending status of interrupt for event READY[8] */ + #define IPCT_INTPEND7_READY8_Pos (24UL) /*!< Position of READY8 field. */ + #define IPCT_INTPEND7_READY8_Msk (0x1UL << IPCT_INTPEND7_READY8_Pos) /*!< Bit mask of READY8 field. */ + #define IPCT_INTPEND7_READY8_Min (0x0UL) /*!< Min enumerator value of READY8 field. */ + #define IPCT_INTPEND7_READY8_Max (0x1UL) /*!< Max enumerator value of READY8 field. */ + #define IPCT_INTPEND7_READY8_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY8_Pending (0x1UL) /*!< Read: Pending */ + +/* READY9 @Bit 25 : Read pending status of interrupt for event READY[9] */ + #define IPCT_INTPEND7_READY9_Pos (25UL) /*!< Position of READY9 field. */ + #define IPCT_INTPEND7_READY9_Msk (0x1UL << IPCT_INTPEND7_READY9_Pos) /*!< Bit mask of READY9 field. */ + #define IPCT_INTPEND7_READY9_Min (0x0UL) /*!< Min enumerator value of READY9 field. */ + #define IPCT_INTPEND7_READY9_Max (0x1UL) /*!< Max enumerator value of READY9 field. */ + #define IPCT_INTPEND7_READY9_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY9_Pending (0x1UL) /*!< Read: Pending */ + +/* READY10 @Bit 26 : Read pending status of interrupt for event READY[10] */ + #define IPCT_INTPEND7_READY10_Pos (26UL) /*!< Position of READY10 field. */ + #define IPCT_INTPEND7_READY10_Msk (0x1UL << IPCT_INTPEND7_READY10_Pos) /*!< Bit mask of READY10 field. */ + #define IPCT_INTPEND7_READY10_Min (0x0UL) /*!< Min enumerator value of READY10 field. */ + #define IPCT_INTPEND7_READY10_Max (0x1UL) /*!< Max enumerator value of READY10 field. */ + #define IPCT_INTPEND7_READY10_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY10_Pending (0x1UL) /*!< Read: Pending */ + +/* READY11 @Bit 27 : Read pending status of interrupt for event READY[11] */ + #define IPCT_INTPEND7_READY11_Pos (27UL) /*!< Position of READY11 field. */ + #define IPCT_INTPEND7_READY11_Msk (0x1UL << IPCT_INTPEND7_READY11_Pos) /*!< Bit mask of READY11 field. */ + #define IPCT_INTPEND7_READY11_Min (0x0UL) /*!< Min enumerator value of READY11 field. */ + #define IPCT_INTPEND7_READY11_Max (0x1UL) /*!< Max enumerator value of READY11 field. */ + #define IPCT_INTPEND7_READY11_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY11_Pending (0x1UL) /*!< Read: Pending */ + +/* READY12 @Bit 28 : Read pending status of interrupt for event READY[12] */ + #define IPCT_INTPEND7_READY12_Pos (28UL) /*!< Position of READY12 field. */ + #define IPCT_INTPEND7_READY12_Msk (0x1UL << IPCT_INTPEND7_READY12_Pos) /*!< Bit mask of READY12 field. */ + #define IPCT_INTPEND7_READY12_Min (0x0UL) /*!< Min enumerator value of READY12 field. */ + #define IPCT_INTPEND7_READY12_Max (0x1UL) /*!< Max enumerator value of READY12 field. */ + #define IPCT_INTPEND7_READY12_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY12_Pending (0x1UL) /*!< Read: Pending */ + +/* READY13 @Bit 29 : Read pending status of interrupt for event READY[13] */ + #define IPCT_INTPEND7_READY13_Pos (29UL) /*!< Position of READY13 field. */ + #define IPCT_INTPEND7_READY13_Msk (0x1UL << IPCT_INTPEND7_READY13_Pos) /*!< Bit mask of READY13 field. */ + #define IPCT_INTPEND7_READY13_Min (0x0UL) /*!< Min enumerator value of READY13 field. */ + #define IPCT_INTPEND7_READY13_Max (0x1UL) /*!< Max enumerator value of READY13 field. */ + #define IPCT_INTPEND7_READY13_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY13_Pending (0x1UL) /*!< Read: Pending */ + +/* READY14 @Bit 30 : Read pending status of interrupt for event READY[14] */ + #define IPCT_INTPEND7_READY14_Pos (30UL) /*!< Position of READY14 field. */ + #define IPCT_INTPEND7_READY14_Msk (0x1UL << IPCT_INTPEND7_READY14_Pos) /*!< Bit mask of READY14 field. */ + #define IPCT_INTPEND7_READY14_Min (0x0UL) /*!< Min enumerator value of READY14 field. */ + #define IPCT_INTPEND7_READY14_Max (0x1UL) /*!< Max enumerator value of READY14 field. */ + #define IPCT_INTPEND7_READY14_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY14_Pending (0x1UL) /*!< Read: Pending */ + +/* READY15 @Bit 31 : Read pending status of interrupt for event READY[15] */ + #define IPCT_INTPEND7_READY15_Pos (31UL) /*!< Position of READY15 field. */ + #define IPCT_INTPEND7_READY15_Msk (0x1UL << IPCT_INTPEND7_READY15_Pos) /*!< Bit mask of READY15 field. */ + #define IPCT_INTPEND7_READY15_Min (0x0UL) /*!< Min enumerator value of READY15 field. */ + #define IPCT_INTPEND7_READY15_Max (0x1UL) /*!< Max enumerator value of READY15 field. */ + #define IPCT_INTPEND7_READY15_NotPending (0x0UL) /*!< Read: Not pending */ + #define IPCT_INTPEND7_READY15_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ L2CACHEDATA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================== Struct L2CACHEDATA_SET_WAY_DU ============================================== */ +/** + * @brief DU [L2CACHEDATA_SET_WAY_DU] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[4]; /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of + SET[n], WAY[o].*/ +} NRF_L2CACHEDATA_SET_WAY_DU_Type; /*!< Size = 16 (0x010) */ + #define L2CACHEDATA_SET_WAY_DU_MaxCount (4UL) /*!< Size of DU[4] array. */ + #define L2CACHEDATA_SET_WAY_DU_MaxIndex (3UL) /*!< Max index of DU[4] array. */ + #define L2CACHEDATA_SET_WAY_DU_MinIndex (0UL) /*!< Min index of DU[4] array. */ + +/* L2CACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */ + #define L2CACHEDATA_SET_WAY_DU_DATA_MaxCount (4UL) /*!< Max size of DATA[4] array. */ + #define L2CACHEDATA_SET_WAY_DU_DATA_MaxIndex (3UL) /*!< Max index of DATA[4] array. */ + #define L2CACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL) /*!< Min index of DATA[4] array. */ + #define L2CACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[4] register. */ + +/* Data @Bits 0..31 : Data */ + #define L2CACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL) /*!< Position of Data field. */ + #define L2CACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << L2CACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data + field.*/ + + + +/* =============================================== Struct L2CACHEDATA_SET_WAY ================================================ */ +/** + * @brief WAY [L2CACHEDATA_SET_WAY] (unspecified) + */ +typedef struct { + __IOM NRF_L2CACHEDATA_SET_WAY_DU_Type DU[4]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_L2CACHEDATA_SET_WAY_Type; /*!< Size = 64 (0x040) */ + #define L2CACHEDATA_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define L2CACHEDATA_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define L2CACHEDATA_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + + +/* ================================================= Struct L2CACHEDATA_SET ================================================== */ +/** + * @brief SET [L2CACHEDATA_SET] (unspecified) + */ +typedef struct { + __IOM NRF_L2CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_L2CACHEDATA_SET_Type; /*!< Size = 128 (0x080) */ + #define L2CACHEDATA_SET_MaxCount (2048UL) /*!< Size of SET[2048] array. */ + #define L2CACHEDATA_SET_MaxIndex (2047UL) /*!< Max index of SET[2048] array. */ + #define L2CACHEDATA_SET_MinIndex (0UL) /*!< Min index of SET[2048] array. */ + +/* =================================================== Struct L2CACHEDATA ==================================================== */ +/** + * @brief CACHEDATA + */ + typedef struct { /*!< L2CACHEDATA Structure */ + __IOM NRF_L2CACHEDATA_SET_Type SET[2048]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_L2CACHEDATA_Type; /*!< Size = 262144 (0x40000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ L2CACHEINFO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =============================================== Struct L2CACHEINFO_SET_WAY ================================================ */ +/** + * @brief WAY [L2CACHEINFO_SET_WAY] (unspecified) + */ +typedef struct { + __IOM uint32_t INFO; /*!< (@ 0x00000000) Cache information for SET[n], WAY[o]. */ +} NRF_L2CACHEINFO_SET_WAY_Type; /*!< Size = 4 (0x004) */ + #define L2CACHEINFO_SET_WAY_MaxCount (2UL) /*!< Size of WAY[2] array. */ + #define L2CACHEINFO_SET_WAY_MaxIndex (1UL) /*!< Max index of WAY[2] array. */ + #define L2CACHEINFO_SET_WAY_MinIndex (0UL) /*!< Min index of WAY[2] array. */ + +/* L2CACHEINFO_SET_WAY_INFO: Cache information for SET[n], WAY[o]. */ + #define L2CACHEINFO_SET_WAY_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* TAG @Bits 0..14 : Cache tag. */ + #define L2CACHEINFO_SET_WAY_INFO_TAG_Pos (0UL) /*!< Position of TAG field. */ + #define L2CACHEINFO_SET_WAY_INFO_TAG_Msk (0x7FFFUL << L2CACHEINFO_SET_WAY_INFO_TAG_Pos) /*!< Bit mask of TAG field. */ + +/* DUV0 @Bit 24 : Data unit valid info. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Pos (24UL) /*!< Position of DUV0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_DUV0_Pos) /*!< Bit mask of DUV0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Min (0x0UL) /*!< Min enumerator value of DUV0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Max (0x1UL) /*!< Max enumerator value of DUV0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Invalid (0x0UL) /*!< Invalid data unit */ + #define L2CACHEINFO_SET_WAY_INFO_DUV0_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV1 @Bit 25 : Data unit valid info. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Pos (25UL) /*!< Position of DUV1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_DUV1_Pos) /*!< Bit mask of DUV1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Min (0x0UL) /*!< Min enumerator value of DUV1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Max (0x1UL) /*!< Max enumerator value of DUV1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Invalid (0x0UL) /*!< Invalid data unit */ + #define L2CACHEINFO_SET_WAY_INFO_DUV1_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV2 @Bit 26 : Data unit valid info. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Pos (26UL) /*!< Position of DUV2 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_DUV2_Pos) /*!< Bit mask of DUV2 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Min (0x0UL) /*!< Min enumerator value of DUV2 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Max (0x1UL) /*!< Max enumerator value of DUV2 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Invalid (0x0UL) /*!< Invalid data unit */ + #define L2CACHEINFO_SET_WAY_INFO_DUV2_Valid (0x1UL) /*!< Valid data unit */ + +/* DUV3 @Bit 27 : Data unit valid info. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Pos (27UL) /*!< Position of DUV3 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_DUV3_Pos) /*!< Bit mask of DUV3 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Min (0x0UL) /*!< Min enumerator value of DUV3 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Max (0x1UL) /*!< Max enumerator value of DUV3 field. */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Invalid (0x0UL) /*!< Invalid data unit */ + #define L2CACHEINFO_SET_WAY_INFO_DUV3_Valid (0x1UL) /*!< Valid data unit */ + +/* D0 @Bit 28 : Dirty status of combined data unit 0 and 1. */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Pos (28UL) /*!< Position of D0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_D0_Pos) /*!< Bit mask of D0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Min (0x0UL) /*!< Min enumerator value of D0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Max (0x1UL) /*!< Max enumerator value of D0 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Clean (0x0UL) /*!< Clean data unit */ + #define L2CACHEINFO_SET_WAY_INFO_D0_Dirty (0x1UL) /*!< Dirty data unit */ + +/* D1 @Bit 29 : Dirty status of combined data unit 2 and 3. */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Pos (29UL) /*!< Position of D1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_D1_Pos) /*!< Bit mask of D1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Min (0x0UL) /*!< Min enumerator value of D1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Max (0x1UL) /*!< Max enumerator value of D1 field. */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Clean (0x0UL) /*!< Clean data unit */ + #define L2CACHEINFO_SET_WAY_INFO_D1_Dirty (0x1UL) /*!< Dirty data unit */ + +/* V @Bit 30 : Line valid bit. */ + #define L2CACHEINFO_SET_WAY_INFO_V_Pos (30UL) /*!< Position of V field. */ + #define L2CACHEINFO_SET_WAY_INFO_V_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_V_Pos) /*!< Bit mask of V field. */ + #define L2CACHEINFO_SET_WAY_INFO_V_Min (0x0UL) /*!< Min enumerator value of V field. */ + #define L2CACHEINFO_SET_WAY_INFO_V_Max (0x1UL) /*!< Max enumerator value of V field. */ + #define L2CACHEINFO_SET_WAY_INFO_V_Invalid (0x0UL) /*!< Invalid cache line */ + #define L2CACHEINFO_SET_WAY_INFO_V_Valid (0x1UL) /*!< Valid cache line */ + +/* MRU @Bit 31 : Most recently used way. */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Pos (31UL) /*!< Position of MRU field. */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Msk (0x1UL << L2CACHEINFO_SET_WAY_INFO_MRU_Pos) /*!< Bit mask of MRU field. */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Min (0x0UL) /*!< Min enumerator value of MRU field. */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Max (0x1UL) /*!< Max enumerator value of MRU field. */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Way0 (0x0UL) /*!< Way0 was most recently used */ + #define L2CACHEINFO_SET_WAY_INFO_MRU_Way1 (0x1UL) /*!< Way1 was most recently used */ + + + +/* ================================================= Struct L2CACHEINFO_SET ================================================== */ +/** + * @brief SET [L2CACHEINFO_SET] (unspecified) + */ +typedef struct { + __IOM NRF_L2CACHEINFO_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_L2CACHEINFO_SET_Type; /*!< Size = 8 (0x008) */ + #define L2CACHEINFO_SET_MaxCount (2048UL) /*!< Size of SET[2048] array. */ + #define L2CACHEINFO_SET_MaxIndex (2047UL) /*!< Max index of SET[2048] array. */ + #define L2CACHEINFO_SET_MinIndex (0UL) /*!< Min index of SET[2048] array. */ + +/* =================================================== Struct L2CACHEINFO ==================================================== */ +/** + * @brief CACHEINFO + */ + typedef struct { /*!< L2CACHEINFO Structure */ + __IOM NRF_L2CACHEINFO_SET_Type SET[2048]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_L2CACHEINFO_Type; /*!< Size = 16384 (0x4000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct LPCOMP ====================================================== */ +/** + * @brief Low-power comparator + */ + typedef struct { /*!< LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[29]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ + __IM uint32_t RESERVED1[29]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ + __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ + __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ + __IM uint32_t RESERVED3[28]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED5[60]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED7[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED8[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53C) */ + +/* LPCOMP_TASKS_START: Start comparator */ + #define LPCOMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start comparator */ + #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_TASKS_STOP: Stop comparator */ + #define LPCOMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop comparator */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_TASKS_SAMPLE: Sample comparator value */ + #define LPCOMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Sample comparator value */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE + field.*/ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* LPCOMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define LPCOMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define LPCOMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define LPCOMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* LPCOMP_EVENTS_READY: LPCOMP is ready and output is valid */ + #define LPCOMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : LPCOMP is ready and output is valid */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY + field.*/ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_DOWN: Downward crossing */ + #define LPCOMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register. */ + +/* EVENTS_DOWN @Bit 0 : Downward crossing */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field. */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_UP: Upward crossing */ + #define LPCOMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register. */ + +/* EVENTS_UP @Bit 0 : Upward crossing */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Min (0x0UL) /*!< Min enumerator value of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Max (0x1UL) /*!< Max enumerator value of EVENTS_UP field. */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_EVENTS_CROSS: Downward or upward crossing */ + #define LPCOMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register. */ + +/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS + field.*/ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field. */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated */ + #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated */ + + +/* LPCOMP_PUBLISH_READY: Publish configuration for event READY */ + #define LPCOMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_DOWN: Publish configuration for event DOWN */ + #define LPCOMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_DOWN_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_UP: Publish configuration for event UP */ + #define LPCOMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */ + #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_UP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_UP_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_UP_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_UP_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_PUBLISH_CROSS: Publish configuration for event CROSS */ + #define LPCOMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define LPCOMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL) /*!< Position of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define LPCOMP_PUBLISH_CROSS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* LPCOMP_SHORTS: Shortcuts between local events and tasks */ + #define LPCOMP_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */ + #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Min (0x0UL) /*!< Min enumerator value of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Max (0x1UL) /*!< Max enumerator value of READY_SAMPLE field. */ + #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */ + #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Min (0x0UL) /*!< Min enumerator value of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Max (0x1UL) /*!< Max enumerator value of READY_STOP field. */ + #define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */ + #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Min (0x0UL) /*!< Min enumerator value of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Max (0x1UL) /*!< Max enumerator value of DOWN_STOP field. */ + #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */ + #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Min (0x0UL) /*!< Min enumerator value of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Max (0x1UL) /*!< Max enumerator value of UP_STOP field. */ + #define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */ + #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Min (0x0UL) /*!< Min enumerator value of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Max (0x1UL) /*!< Max enumerator value of CROSS_STOP field. */ + #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* LPCOMP_INTEN: Enable or disable interrupt */ + #define LPCOMP_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* READY @Bit 0 : Enable or disable interrupt for event READY */ + #define LPCOMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTEN_READY_Msk (0x1UL << LPCOMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTEN_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTEN_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTEN_READY_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_READY_Enabled (0x1UL) /*!< Enable */ + +/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */ + #define LPCOMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Msk (0x1UL << LPCOMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTEN_DOWN_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_DOWN_Enabled (0x1UL) /*!< Enable */ + +/* UP @Bit 2 : Enable or disable interrupt for event UP */ + #define LPCOMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTEN_UP_Msk (0x1UL << LPCOMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTEN_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTEN_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTEN_UP_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_UP_Enabled (0x1UL) /*!< Enable */ + +/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */ + #define LPCOMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Msk (0x1UL << LPCOMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTEN_CROSS_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_INTEN_CROSS_Enabled (0x1UL) /*!< Enable */ + + +/* LPCOMP_INTENSET: Enable interrupt */ + #define LPCOMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTENSET_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTENSET_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTENSET_READY_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */ + #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTENSET_DOWN_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to enable interrupt for event UP */ + #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTENSET_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTENSET_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTENSET_UP_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */ + #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTENSET_CROSS_Set (0x1UL) /*!< Enable */ + #define LPCOMP_INTENSET_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENSET_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* LPCOMP_INTENCLR: Disable interrupt */ + #define LPCOMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTENCLR_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTENCLR_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTENCLR_READY_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */ + #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTENCLR_DOWN_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL) /*!< Read: Enabled */ + +/* UP @Bit 2 : Write '1' to disable interrupt for event UP */ + #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTENCLR_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTENCLR_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTENCLR_UP_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_UP_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_UP_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */ + #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTENCLR_CROSS_Clear (0x1UL) /*!< Disable */ + #define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL) /*!< Read: Disabled */ + #define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* LPCOMP_INTPEND: Pending interrupts */ + #define LPCOMP_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* READY @Bit 0 : Read pending status of interrupt for event READY */ + #define LPCOMP_INTPEND_READY_Pos (0UL) /*!< Position of READY field. */ + #define LPCOMP_INTPEND_READY_Msk (0x1UL << LPCOMP_INTPEND_READY_Pos) /*!< Bit mask of READY field. */ + #define LPCOMP_INTPEND_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define LPCOMP_INTPEND_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LPCOMP_INTPEND_READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */ + #define LPCOMP_INTPEND_DOWN_Pos (1UL) /*!< Position of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Msk (0x1UL << LPCOMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Min (0x0UL) /*!< Min enumerator value of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_Max (0x1UL) /*!< Max enumerator value of DOWN field. */ + #define LPCOMP_INTPEND_DOWN_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_DOWN_Pending (0x1UL) /*!< Read: Pending */ + +/* UP @Bit 2 : Read pending status of interrupt for event UP */ + #define LPCOMP_INTPEND_UP_Pos (2UL) /*!< Position of UP field. */ + #define LPCOMP_INTPEND_UP_Msk (0x1UL << LPCOMP_INTPEND_UP_Pos) /*!< Bit mask of UP field. */ + #define LPCOMP_INTPEND_UP_Min (0x0UL) /*!< Min enumerator value of UP field. */ + #define LPCOMP_INTPEND_UP_Max (0x1UL) /*!< Max enumerator value of UP field. */ + #define LPCOMP_INTPEND_UP_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_UP_Pending (0x1UL) /*!< Read: Pending */ + +/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */ + #define LPCOMP_INTPEND_CROSS_Pos (3UL) /*!< Position of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Msk (0x1UL << LPCOMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Min (0x0UL) /*!< Min enumerator value of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_Max (0x1UL) /*!< Max enumerator value of CROSS field. */ + #define LPCOMP_INTPEND_CROSS_NotPending (0x0UL) /*!< Read: Not pending */ + #define LPCOMP_INTPEND_CROSS_Pending (0x1UL) /*!< Read: Pending */ + + +/* LPCOMP_RESULT: Compare result */ + #define LPCOMP_RESULT_ResetValue (0x00000000UL) /*!< Reset value of RESULT register. */ + +/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */ + #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Min (0x0UL) /*!< Min enumerator value of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Max (0x1UL) /*!< Max enumerator value of RESULT field. */ + #define LPCOMP_RESULT_RESULT_Below (0x0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-) */ + #define LPCOMP_RESULT_RESULT_Above (0x1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-) */ + + +/* LPCOMP_ENABLE: Enable LPCOMP */ + #define LPCOMP_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..1 : Enable or disable LPCOMP */ + #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* LPCOMP_PSEL: Input pin select */ + #define LPCOMP_PSEL_ResetValue (0x00000000UL) /*!< Reset value of PSEL register. */ + +/* PIN @Bits 0..4 : Analog pin select */ + #define LPCOMP_PSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define LPCOMP_PSEL_PIN_Msk (0x1FUL << LPCOMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define LPCOMP_PSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define LPCOMP_PSEL_PORT_Msk (0xFUL << LPCOMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* LPCOMP_REFSEL: Reference select */ + #define LPCOMP_REFSEL_ResetValue (0x00000004UL) /*!< Reset value of REFSEL register. */ + +/* REFSEL @Bits 0..3 : Reference select */ + #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Max (0xFUL) /*!< Max enumerator value of REFSEL field. */ + #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL) /*!< VDD * 1/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL) /*!< VDD * 2/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL) /*!< VDD * 3/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL) /*!< VDD * 4/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL) /*!< VDD * 5/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL) /*!< VDD * 6/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL) /*!< VDD * 7/8 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_ARef (0x7UL) /*!< External analog reference selected */ + #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL) /*!< VDD * 1/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL) /*!< VDD * 3/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL) /*!< VDD * 5/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL) /*!< VDD * 7/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL) /*!< VDD * 9/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL) /*!< VDD * 11/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL) /*!< VDD * 13/16 selected as reference */ + #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL) /*!< VDD * 15/16 selected as reference */ + + +/* LPCOMP_EXTREFSEL: External reference select */ + #define LPCOMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register. */ + +/* PIN @Bits 0..4 : External analog reference pin select */ + #define LPCOMP_EXTREFSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define LPCOMP_EXTREFSEL_PIN_Msk (0x1FUL << LPCOMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define LPCOMP_EXTREFSEL_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define LPCOMP_EXTREFSEL_PORT_Msk (0xFUL << LPCOMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field. */ + + +/* LPCOMP_ANADETECT: Analog detect configuration */ + #define LPCOMP_ANADETECT_ResetValue (0x00000000UL) /*!< Reset value of ANADETECT register. */ + +/* ANADETECT @Bits 0..1 : Analog detect configuration */ + #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Min (0x0UL) /*!< Min enumerator value of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Max (0x2UL) /*!< Max enumerator value of ANADETECT field. */ + #define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward + crossing*/ + #define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL) /*!< Generate ANADETECT on upward crossing only */ + #define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL) /*!< Generate ANADETECT on downward crossing only */ + + +/* LPCOMP_HYST: Comparator hysteresis enable */ + #define LPCOMP_HYST_ResetValue (0x00000000UL) /*!< Reset value of HYST register. */ + +/* HYST @Bit 0 : Comparator hysteresis enable */ + #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ + #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ + #define LPCOMP_HYST_HYST_Min (0x0UL) /*!< Min enumerator value of HYST field. */ + #define LPCOMP_HYST_HYST_Max (0x1UL) /*!< Max enumerator value of HYST field. */ + #define LPCOMP_HYST_HYST_Disabled (0x0UL) /*!< Comparator hysteresis disabled */ + #define LPCOMP_HYST_HYST_Enabled (0x1UL) /*!< Comparator hysteresis enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ LRCCONF ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================== Struct LRCCONF_TASKS_CONSTLAT ============================================== */ +/** + * @brief TASKS_CONSTLAT [LRCCONF_TASKS_CONSTLAT] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLE; /*!< (@ 0x00000000) Enable constant latency mode */ + __OM uint32_t DISABLE; /*!< (@ 0x00000004) Disable constant latency mode */ +} NRF_LRCCONF_TASKS_CONSTLAT_Type; /*!< Size = 8 (0x008) */ + +/* LRCCONF_TASKS_CONSTLAT_ENABLE: Enable constant latency mode */ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable constant latency mode */ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Msk (0x1UL << LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Min (0x1UL) /*!< Min enumerator value of ENABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_TASKS_CONSTLAT_DISABLE: Disable constant latency mode */ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of DISABLE register. */ + +/* DISABLE @Bit 0 : Disable constant latency mode */ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Msk (0x1UL << LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Pos) /*!< Bit mask of + DISABLE field.*/ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Min (0x1UL) /*!< Min enumerator value of DISABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Max (0x1UL) /*!< Max enumerator value of DISABLE field. */ + #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ============================================= Struct LRCCONF_TASKS_SYSTEMOFF ============================================== */ +/** + * @brief TASKS_SYSTEMOFF [LRCCONF_TASKS_SYSTEMOFF] Peripheral tasks. + */ +typedef struct { + __OM uint32_t NOTREADY; /*!< (@ 0x00000000) Not ready to go to System OFF */ + __OM uint32_t READY; /*!< (@ 0x00000004) Ready to go to System OFF */ +} NRF_LRCCONF_TASKS_SYSTEMOFF_Type; /*!< Size = 8 (0x008) */ + +/* LRCCONF_TASKS_SYSTEMOFF_NOTREADY: Not ready to go to System OFF */ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_ResetValue (0x00000000UL) /*!< Reset value of NOTREADY register. */ + +/* NOTREADY @Bit 0 : Not ready to go to System OFF */ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Pos (0UL) /*!< Position of NOTREADY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Msk (0x1UL << LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Pos) /*!< Bit mask + of NOTREADY field.*/ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Min (0x1UL) /*!< Min enumerator value of NOTREADY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Max (0x1UL) /*!< Max enumerator value of NOTREADY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_TASKS_SYSTEMOFF_READY: Ready to go to System OFF */ + #define LRCCONF_TASKS_SYSTEMOFF_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Ready to go to System OFF */ + #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Msk (0x1UL << LRCCONF_TASKS_SYSTEMOFF_READY_READY_Pos) /*!< Bit mask of READY + field.*/ + #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Min (0x1UL) /*!< Min enumerator value of READY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================= Struct LRCCONF_CLKSTAT ================================================== */ +/** + * @brief CLKSTAT [LRCCONF_CLKSTAT] (unspecified) + */ +typedef struct { + __IOM uint32_t RUN; /*!< (@ 0x00000000) Status indicating that TASKS_REQCLKSRC task has been + triggered for clock [n].*/ + __IOM uint32_t SRC; /*!< (@ 0x00000004) Status indicating clock source for clock [n] */ +} NRF_LRCCONF_CLKSTAT_Type; /*!< Size = 8 (0x008) */ + #define LRCCONF_CLKSTAT_MaxCount (8UL) /*!< Size of CLKSTAT[8] array. */ + #define LRCCONF_CLKSTAT_MaxIndex (7UL) /*!< Max index of CLKSTAT[8] array. */ + #define LRCCONF_CLKSTAT_MinIndex (0UL) /*!< Min index of CLKSTAT[8] array. */ + +/* LRCCONF_CLKSTAT_RUN: Status indicating that TASKS_REQCLKSRC task has been triggered for clock [n]. */ + #define LRCCONF_CLKSTAT_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register. */ + +/* STATUS @Bit 0 : Clock start task triggered or not */ + #define LRCCONF_CLKSTAT_RUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define LRCCONF_CLKSTAT_RUN_STATUS_Msk (0x1UL << LRCCONF_CLKSTAT_RUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define LRCCONF_CLKSTAT_RUN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define LRCCONF_CLKSTAT_RUN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define LRCCONF_CLKSTAT_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ + #define LRCCONF_CLKSTAT_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ + + +/* LRCCONF_CLKSTAT_SRC: Status indicating clock source for clock [n] */ + #define LRCCONF_CLKSTAT_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* SRC @Bit 0 : Clock source status */ + #define LRCCONF_CLKSTAT_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define LRCCONF_CLKSTAT_SRC_SRC_Msk (0x1UL << LRCCONF_CLKSTAT_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + #define LRCCONF_CLKSTAT_SRC_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define LRCCONF_CLKSTAT_SRC_SRC_Max (0x1UL) /*!< Max enumerator value of SRC field. */ + #define LRCCONF_CLKSTAT_SRC_SRC_OpenLoop (0x0UL) /*!< Open loop. */ + #define LRCCONF_CLKSTAT_SRC_SRC_ClosedLoop (0x1UL) /*!< Closed loop. */ + + + +/* ================================================= Struct LRCCONF_CLKCTRL ================================================== */ +/** + * @brief CLKCTRL [LRCCONF_CLKCTRL] (unspecified) + */ +typedef struct { + __IOM uint32_t ALWAYSRUN; /*!< (@ 0x00000000) Force the clock [n] and tree running always */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) Select the clock source for clock [n] */ +} NRF_LRCCONF_CLKCTRL_Type; /*!< Size = 8 (0x008) */ + #define LRCCONF_CLKCTRL_MaxCount (8UL) /*!< Size of CLKCTRL[8] array. */ + #define LRCCONF_CLKCTRL_MaxIndex (7UL) /*!< Max index of CLKCTRL[8] array. */ + #define LRCCONF_CLKCTRL_MinIndex (0UL) /*!< Min index of CLKCTRL[8] array. */ + +/* LRCCONF_CLKCTRL_ALWAYSRUN: Force the clock [n] and tree running always */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_ResetValue (0x00000000UL) /*!< Reset value of ALWAYSRUN register. */ + +/* FORCE @Bit 0 : Force the clock always running */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Pos (0UL) /*!< Position of FORCE field. */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Msk (0x1UL << LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Pos) /*!< Bit mask of FORCE field. */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Min (0x0UL) /*!< Min enumerator value of FORCE field. */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Max (0x1UL) /*!< Max enumerator value of FORCE field. */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Automatic (0x0UL) /*!< Automatic clock control enabled */ + #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_AlwaysRun (0x1UL) /*!< Clock always running */ + + +/* LRCCONF_CLKCTRL_SRC: Select the clock source for clock [n] */ + #define LRCCONF_CLKCTRL_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register. */ + +/* SRC @Bit 0 : Clock source */ + #define LRCCONF_CLKCTRL_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define LRCCONF_CLKCTRL_SRC_SRC_Msk (0x1UL << LRCCONF_CLKCTRL_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + #define LRCCONF_CLKCTRL_SRC_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define LRCCONF_CLKCTRL_SRC_SRC_Max (0x1UL) /*!< Max enumerator value of SRC field. */ + #define LRCCONF_CLKCTRL_SRC_SRC_OpenLoop (0x0UL) /*!< Open loop. */ + #define LRCCONF_CLKCTRL_SRC_SRC_ClosedLoop (0x1UL) /*!< Closed loop. */ + + +/* ===================================================== Struct LRCCONF ====================================================== */ +/** + * @brief LRCCONF + */ + typedef struct { /*!< LRCCONF Structure */ + __OM uint32_t TASKS_REQCLKSRC[8]; /*!< (@ 0x00000000) Request the clock source for clock [n] */ + __OM uint32_t TASKS_STOPREQCLKSRC[8]; /*!< (@ 0x00000020) Stop requesting the clock source for clock [n] */ + __OM NRF_LRCCONF_TASKS_CONSTLAT_Type TASKS_CONSTLAT; /*!< (@ 0x00000040) Peripheral tasks. */ + __OM NRF_LRCCONF_TASKS_SYSTEMOFF_Type TASKS_SYSTEMOFF; /*!< (@ 0x00000048) Peripheral tasks. */ + __OM uint32_t TASKS_REQHFXO; /*!< (@ 0x00000050) Request HFXO */ + __OM uint32_t TASKS_STOPREQHFXO; /*!< (@ 0x00000054) Stop requesting HFXO */ + __IM uint32_t RESERVED[42]; + __IOM uint32_t EVENTS_CLKSRCSTARTED[8]; /*!< (@ 0x00000100) Clock source is started for clock [n] */ + __IOM uint32_t EVENTS_HFXOSTARTED; /*!< (@ 0x00000120) HFXO is started */ + __IM uint32_t RESERVED1[183]; + __IOM NRF_LRCCONF_CLKSTAT_Type CLKSTAT[8]; /*!< (@ 0x00000400) (unspecified) */ + __IOM NRF_LRCCONF_CLKCTRL_Type CLKCTRL[8]; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t CONSTLATSTAT; /*!< (@ 0x00000480) Status of constant latency */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t POWERON; /*!< (@ 0x00000490) Force power domain ON */ + __IOM uint32_t RETAIN; /*!< (@ 0x00000494) Retain power domain */ + __IM uint32_t RESERVED3[26]; + __IOM uint32_t AX2XWAITSTATES[16]; /*!< (@ 0x00000500) AX2X bridge waitstates for the domain [n], where n is + the Domain ID.*/ + } NRF_LRCCONF_Type; /*!< Size = 1344 (0x540) */ + +/* LRCCONF_TASKS_REQCLKSRC: Request the clock source for clock [n] */ + #define LRCCONF_TASKS_REQCLKSRC_MaxCount (8UL) /*!< Max size of TASKS_REQCLKSRC[8] array. */ + #define LRCCONF_TASKS_REQCLKSRC_MaxIndex (7UL) /*!< Max index of TASKS_REQCLKSRC[8] array. */ + #define LRCCONF_TASKS_REQCLKSRC_MinIndex (0UL) /*!< Min index of TASKS_REQCLKSRC[8] array. */ + #define LRCCONF_TASKS_REQCLKSRC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_REQCLKSRC[8] register. */ + +/* TASKS_REQCLKSRC @Bit 0 : Request the clock source for clock [n] */ + #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Pos (0UL) /*!< Position of TASKS_REQCLKSRC field. */ + #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Msk (0x1UL << LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Pos) /*!< Bit mask of + TASKS_REQCLKSRC field.*/ + #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Min (0x1UL) /*!< Min enumerator value of TASKS_REQCLKSRC field. */ + #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Max (0x1UL) /*!< Max enumerator value of TASKS_REQCLKSRC field. */ + #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_TASKS_STOPREQCLKSRC: Stop requesting the clock source for clock [n] */ + #define LRCCONF_TASKS_STOPREQCLKSRC_MaxCount (8UL) /*!< Max size of TASKS_STOPREQCLKSRC[8] array. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_MaxIndex (7UL) /*!< Max index of TASKS_STOPREQCLKSRC[8] array. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_MinIndex (0UL) /*!< Min index of TASKS_STOPREQCLKSRC[8] array. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPREQCLKSRC[8] register. */ + +/* TASKS_STOPREQCLKSRC @Bit 0 : Stop requesting the clock source for clock [n] */ + #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Pos (0UL) /*!< Position of TASKS_STOPREQCLKSRC field. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Msk (0x1UL << LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Pos) + /*!< Bit mask of TASKS_STOPREQCLKSRC field.*/ + #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPREQCLKSRC field. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPREQCLKSRC field. */ + #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_TASKS_REQHFXO: Request HFXO */ + #define LRCCONF_TASKS_REQHFXO_ResetValue (0x00000000UL) /*!< Reset value of TASKS_REQHFXO register. */ + +/* TASKS_REQHFXO @Bit 0 : Request HFXO */ + #define LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Pos (0UL) /*!< Position of TASKS_REQHFXO field. */ + #define LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Msk (0x1UL << LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Pos) /*!< Bit mask of + TASKS_REQHFXO field.*/ + #define LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Min (0x1UL) /*!< Min enumerator value of TASKS_REQHFXO field. */ + #define LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Max (0x1UL) /*!< Max enumerator value of TASKS_REQHFXO field. */ + #define LRCCONF_TASKS_REQHFXO_TASKS_REQHFXO_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_TASKS_STOPREQHFXO: Stop requesting HFXO */ + #define LRCCONF_TASKS_STOPREQHFXO_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPREQHFXO register. */ + +/* TASKS_STOPREQHFXO @Bit 0 : Stop requesting HFXO */ + #define LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Pos (0UL) /*!< Position of TASKS_STOPREQHFXO field. */ + #define LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Msk (0x1UL << LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Pos) /*!< Bit + mask of TASKS_STOPREQHFXO field.*/ + #define LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPREQHFXO field. */ + #define LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPREQHFXO field. */ + #define LRCCONF_TASKS_STOPREQHFXO_TASKS_STOPREQHFXO_Trigger (0x1UL) /*!< Trigger task */ + + +/* LRCCONF_EVENTS_CLKSRCSTARTED: Clock source is started for clock [n] */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_MaxCount (8UL) /*!< Max size of EVENTS_CLKSRCSTARTED[8] array. */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_MaxIndex (7UL) /*!< Max index of EVENTS_CLKSRCSTARTED[8] array. */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_MinIndex (0UL) /*!< Min index of EVENTS_CLKSRCSTARTED[8] array. */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CLKSRCSTARTED[8] register. */ + +/* EVENTS_CLKSRCSTARTED @Bit 0 : Clock source is started for clock [n] */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Pos (0UL) /*!< Position of EVENTS_CLKSRCSTARTED field. */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Msk (0x1UL << LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Pos) + /*!< Bit mask of EVENTS_CLKSRCSTARTED field.*/ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CLKSRCSTARTED + field.*/ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CLKSRCSTARTED + field.*/ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* LRCCONF_EVENTS_HFXOSTARTED: HFXO is started */ + #define LRCCONF_EVENTS_HFXOSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_HFXOSTARTED register. */ + +/* EVENTS_HFXOSTARTED @Bit 0 : HFXO is started */ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFXOSTARTED field. */ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Msk (0x1UL << LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Pos) /*!< + Bit mask of EVENTS_HFXOSTARTED field.*/ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_HFXOSTARTED field. */ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_HFXOSTARTED field. */ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define LRCCONF_EVENTS_HFXOSTARTED_EVENTS_HFXOSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* LRCCONF_CONSTLATSTAT: Status of constant latency */ + #define LRCCONF_CONSTLATSTAT_ResetValue (0x00000000UL) /*!< Reset value of CONSTLATSTAT register. */ + +/* STATUS @Bit 0 : Status */ + #define LRCCONF_CONSTLATSTAT_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define LRCCONF_CONSTLATSTAT_STATUS_Msk (0x1UL << LRCCONF_CONSTLATSTAT_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define LRCCONF_CONSTLATSTAT_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define LRCCONF_CONSTLATSTAT_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define LRCCONF_CONSTLATSTAT_STATUS_Disable (0x0UL) /*!< Constant latency disabled. */ + #define LRCCONF_CONSTLATSTAT_STATUS_Enable (0x1UL) /*!< Constant latency enabled. */ + + +/* LRCCONF_POWERON: Force power domain ON */ + #define LRCCONF_POWERON_ResetValue (0x00000000UL) /*!< Reset value of POWERON register. */ + +/* MAIN @Bit 0 : Force the main power domain ON */ + #define LRCCONF_POWERON_MAIN_Pos (0UL) /*!< Position of MAIN field. */ + #define LRCCONF_POWERON_MAIN_Msk (0x1UL << LRCCONF_POWERON_MAIN_Pos) /*!< Bit mask of MAIN field. */ + #define LRCCONF_POWERON_MAIN_Min (0x0UL) /*!< Min enumerator value of MAIN field. */ + #define LRCCONF_POWERON_MAIN_Max (0x1UL) /*!< Max enumerator value of MAIN field. */ + #define LRCCONF_POWERON_MAIN_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_MAIN_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE0 @Bit 4 : Force the active power domain[0] ON */ + #define LRCCONF_POWERON_ACTIVE0_Pos (4UL) /*!< Position of ACTIVE0 field. */ + #define LRCCONF_POWERON_ACTIVE0_Msk (0x1UL << LRCCONF_POWERON_ACTIVE0_Pos) /*!< Bit mask of ACTIVE0 field. */ + #define LRCCONF_POWERON_ACTIVE0_Min (0x0UL) /*!< Min enumerator value of ACTIVE0 field. */ + #define LRCCONF_POWERON_ACTIVE0_Max (0x1UL) /*!< Max enumerator value of ACTIVE0 field. */ + #define LRCCONF_POWERON_ACTIVE0_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE0_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE1 @Bit 5 : Force the active power domain[1] ON */ + #define LRCCONF_POWERON_ACTIVE1_Pos (5UL) /*!< Position of ACTIVE1 field. */ + #define LRCCONF_POWERON_ACTIVE1_Msk (0x1UL << LRCCONF_POWERON_ACTIVE1_Pos) /*!< Bit mask of ACTIVE1 field. */ + #define LRCCONF_POWERON_ACTIVE1_Min (0x0UL) /*!< Min enumerator value of ACTIVE1 field. */ + #define LRCCONF_POWERON_ACTIVE1_Max (0x1UL) /*!< Max enumerator value of ACTIVE1 field. */ + #define LRCCONF_POWERON_ACTIVE1_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE1_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE2 @Bit 6 : Force the active power domain[2] ON */ + #define LRCCONF_POWERON_ACTIVE2_Pos (6UL) /*!< Position of ACTIVE2 field. */ + #define LRCCONF_POWERON_ACTIVE2_Msk (0x1UL << LRCCONF_POWERON_ACTIVE2_Pos) /*!< Bit mask of ACTIVE2 field. */ + #define LRCCONF_POWERON_ACTIVE2_Min (0x0UL) /*!< Min enumerator value of ACTIVE2 field. */ + #define LRCCONF_POWERON_ACTIVE2_Max (0x1UL) /*!< Max enumerator value of ACTIVE2 field. */ + #define LRCCONF_POWERON_ACTIVE2_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE2_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE3 @Bit 7 : Force the active power domain[3] ON */ + #define LRCCONF_POWERON_ACTIVE3_Pos (7UL) /*!< Position of ACTIVE3 field. */ + #define LRCCONF_POWERON_ACTIVE3_Msk (0x1UL << LRCCONF_POWERON_ACTIVE3_Pos) /*!< Bit mask of ACTIVE3 field. */ + #define LRCCONF_POWERON_ACTIVE3_Min (0x0UL) /*!< Min enumerator value of ACTIVE3 field. */ + #define LRCCONF_POWERON_ACTIVE3_Max (0x1UL) /*!< Max enumerator value of ACTIVE3 field. */ + #define LRCCONF_POWERON_ACTIVE3_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE3_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE4 @Bit 8 : Force the active power domain[4] ON */ + #define LRCCONF_POWERON_ACTIVE4_Pos (8UL) /*!< Position of ACTIVE4 field. */ + #define LRCCONF_POWERON_ACTIVE4_Msk (0x1UL << LRCCONF_POWERON_ACTIVE4_Pos) /*!< Bit mask of ACTIVE4 field. */ + #define LRCCONF_POWERON_ACTIVE4_Min (0x0UL) /*!< Min enumerator value of ACTIVE4 field. */ + #define LRCCONF_POWERON_ACTIVE4_Max (0x1UL) /*!< Max enumerator value of ACTIVE4 field. */ + #define LRCCONF_POWERON_ACTIVE4_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE4_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE5 @Bit 9 : Force the active power domain[5] ON */ + #define LRCCONF_POWERON_ACTIVE5_Pos (9UL) /*!< Position of ACTIVE5 field. */ + #define LRCCONF_POWERON_ACTIVE5_Msk (0x1UL << LRCCONF_POWERON_ACTIVE5_Pos) /*!< Bit mask of ACTIVE5 field. */ + #define LRCCONF_POWERON_ACTIVE5_Min (0x0UL) /*!< Min enumerator value of ACTIVE5 field. */ + #define LRCCONF_POWERON_ACTIVE5_Max (0x1UL) /*!< Max enumerator value of ACTIVE5 field. */ + #define LRCCONF_POWERON_ACTIVE5_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE5_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE6 @Bit 10 : Force the active power domain[6] ON */ + #define LRCCONF_POWERON_ACTIVE6_Pos (10UL) /*!< Position of ACTIVE6 field. */ + #define LRCCONF_POWERON_ACTIVE6_Msk (0x1UL << LRCCONF_POWERON_ACTIVE6_Pos) /*!< Bit mask of ACTIVE6 field. */ + #define LRCCONF_POWERON_ACTIVE6_Min (0x0UL) /*!< Min enumerator value of ACTIVE6 field. */ + #define LRCCONF_POWERON_ACTIVE6_Max (0x1UL) /*!< Max enumerator value of ACTIVE6 field. */ + #define LRCCONF_POWERON_ACTIVE6_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE6_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + +/* ACTIVE7 @Bit 11 : Force the active power domain[7] ON */ + #define LRCCONF_POWERON_ACTIVE7_Pos (11UL) /*!< Position of ACTIVE7 field. */ + #define LRCCONF_POWERON_ACTIVE7_Msk (0x1UL << LRCCONF_POWERON_ACTIVE7_Pos) /*!< Bit mask of ACTIVE7 field. */ + #define LRCCONF_POWERON_ACTIVE7_Min (0x0UL) /*!< Min enumerator value of ACTIVE7 field. */ + #define LRCCONF_POWERON_ACTIVE7_Max (0x1UL) /*!< Max enumerator value of ACTIVE7 field. */ + #define LRCCONF_POWERON_ACTIVE7_Automatic (0x0UL) /*!< Automatic power control enabled */ + #define LRCCONF_POWERON_ACTIVE7_AlwaysOn (0x1UL) /*!< Keep the power domain ON even though there is no request */ + + +/* LRCCONF_RETAIN: Retain power domain */ + #define LRCCONF_RETAIN_ResetValue (0x00000FF1UL) /*!< Reset value of RETAIN register. */ + +/* MAIN @Bit 0 : Retain the main power domain */ + #define LRCCONF_RETAIN_MAIN_Pos (0UL) /*!< Position of MAIN field. */ + #define LRCCONF_RETAIN_MAIN_Msk (0x1UL << LRCCONF_RETAIN_MAIN_Pos) /*!< Bit mask of MAIN field. */ + #define LRCCONF_RETAIN_MAIN_Min (0x0UL) /*!< Min enumerator value of MAIN field. */ + #define LRCCONF_RETAIN_MAIN_Max (0x1UL) /*!< Max enumerator value of MAIN field. */ + #define LRCCONF_RETAIN_MAIN_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_MAIN_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE0 @Bit 4 : Retain the active power domain[0] */ + #define LRCCONF_RETAIN_ACTIVE0_Pos (4UL) /*!< Position of ACTIVE0 field. */ + #define LRCCONF_RETAIN_ACTIVE0_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE0_Pos) /*!< Bit mask of ACTIVE0 field. */ + #define LRCCONF_RETAIN_ACTIVE0_Min (0x0UL) /*!< Min enumerator value of ACTIVE0 field. */ + #define LRCCONF_RETAIN_ACTIVE0_Max (0x1UL) /*!< Max enumerator value of ACTIVE0 field. */ + #define LRCCONF_RETAIN_ACTIVE0_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE0_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE1 @Bit 5 : Retain the active power domain[1] */ + #define LRCCONF_RETAIN_ACTIVE1_Pos (5UL) /*!< Position of ACTIVE1 field. */ + #define LRCCONF_RETAIN_ACTIVE1_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE1_Pos) /*!< Bit mask of ACTIVE1 field. */ + #define LRCCONF_RETAIN_ACTIVE1_Min (0x0UL) /*!< Min enumerator value of ACTIVE1 field. */ + #define LRCCONF_RETAIN_ACTIVE1_Max (0x1UL) /*!< Max enumerator value of ACTIVE1 field. */ + #define LRCCONF_RETAIN_ACTIVE1_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE1_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE2 @Bit 6 : Retain the active power domain[2] */ + #define LRCCONF_RETAIN_ACTIVE2_Pos (6UL) /*!< Position of ACTIVE2 field. */ + #define LRCCONF_RETAIN_ACTIVE2_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE2_Pos) /*!< Bit mask of ACTIVE2 field. */ + #define LRCCONF_RETAIN_ACTIVE2_Min (0x0UL) /*!< Min enumerator value of ACTIVE2 field. */ + #define LRCCONF_RETAIN_ACTIVE2_Max (0x1UL) /*!< Max enumerator value of ACTIVE2 field. */ + #define LRCCONF_RETAIN_ACTIVE2_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE2_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE3 @Bit 7 : Retain the active power domain[3] */ + #define LRCCONF_RETAIN_ACTIVE3_Pos (7UL) /*!< Position of ACTIVE3 field. */ + #define LRCCONF_RETAIN_ACTIVE3_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE3_Pos) /*!< Bit mask of ACTIVE3 field. */ + #define LRCCONF_RETAIN_ACTIVE3_Min (0x0UL) /*!< Min enumerator value of ACTIVE3 field. */ + #define LRCCONF_RETAIN_ACTIVE3_Max (0x1UL) /*!< Max enumerator value of ACTIVE3 field. */ + #define LRCCONF_RETAIN_ACTIVE3_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE3_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE4 @Bit 8 : Retain the active power domain[4] */ + #define LRCCONF_RETAIN_ACTIVE4_Pos (8UL) /*!< Position of ACTIVE4 field. */ + #define LRCCONF_RETAIN_ACTIVE4_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE4_Pos) /*!< Bit mask of ACTIVE4 field. */ + #define LRCCONF_RETAIN_ACTIVE4_Min (0x0UL) /*!< Min enumerator value of ACTIVE4 field. */ + #define LRCCONF_RETAIN_ACTIVE4_Max (0x1UL) /*!< Max enumerator value of ACTIVE4 field. */ + #define LRCCONF_RETAIN_ACTIVE4_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE4_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE5 @Bit 9 : Retain the active power domain[5] */ + #define LRCCONF_RETAIN_ACTIVE5_Pos (9UL) /*!< Position of ACTIVE5 field. */ + #define LRCCONF_RETAIN_ACTIVE5_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE5_Pos) /*!< Bit mask of ACTIVE5 field. */ + #define LRCCONF_RETAIN_ACTIVE5_Min (0x0UL) /*!< Min enumerator value of ACTIVE5 field. */ + #define LRCCONF_RETAIN_ACTIVE5_Max (0x1UL) /*!< Max enumerator value of ACTIVE5 field. */ + #define LRCCONF_RETAIN_ACTIVE5_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE5_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE6 @Bit 10 : Retain the active power domain[6] */ + #define LRCCONF_RETAIN_ACTIVE6_Pos (10UL) /*!< Position of ACTIVE6 field. */ + #define LRCCONF_RETAIN_ACTIVE6_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE6_Pos) /*!< Bit mask of ACTIVE6 field. */ + #define LRCCONF_RETAIN_ACTIVE6_Min (0x0UL) /*!< Min enumerator value of ACTIVE6 field. */ + #define LRCCONF_RETAIN_ACTIVE6_Max (0x1UL) /*!< Max enumerator value of ACTIVE6 field. */ + #define LRCCONF_RETAIN_ACTIVE6_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE6_Enable (0x1UL) /*!< Retain enabled */ + +/* ACTIVE7 @Bit 11 : Retain the active power domain[7] */ + #define LRCCONF_RETAIN_ACTIVE7_Pos (11UL) /*!< Position of ACTIVE7 field. */ + #define LRCCONF_RETAIN_ACTIVE7_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE7_Pos) /*!< Bit mask of ACTIVE7 field. */ + #define LRCCONF_RETAIN_ACTIVE7_Min (0x0UL) /*!< Min enumerator value of ACTIVE7 field. */ + #define LRCCONF_RETAIN_ACTIVE7_Max (0x1UL) /*!< Max enumerator value of ACTIVE7 field. */ + #define LRCCONF_RETAIN_ACTIVE7_Disable (0x0UL) /*!< Retain disabled */ + #define LRCCONF_RETAIN_ACTIVE7_Enable (0x1UL) /*!< Retain enabled */ + + +/* LRCCONF_AX2XWAITSTATES: AX2X bridge waitstates for the domain [n], where n is the Domain ID. */ + #define LRCCONF_AX2XWAITSTATES_MaxCount (16UL) /*!< Max size of AX2XWAITSTATES[16] array. */ + #define LRCCONF_AX2XWAITSTATES_MaxIndex (15UL) /*!< Max index of AX2XWAITSTATES[16] array. */ + #define LRCCONF_AX2XWAITSTATES_MinIndex (0UL) /*!< Min index of AX2XWAITSTATES[16] array. */ + #define LRCCONF_AX2XWAITSTATES_ResetValue (0x00000000UL) /*!< Reset value of AX2XWAITSTATES[16] register. */ + +/* WAITSTATES @Bits 0..2 : Number of waitstates */ + #define LRCCONF_AX2XWAITSTATES_WAITSTATES_Pos (0UL) /*!< Position of WAITSTATES field. */ + #define LRCCONF_AX2XWAITSTATES_WAITSTATES_Msk (0x7UL << LRCCONF_AX2XWAITSTATES_WAITSTATES_Pos) /*!< Bit mask of WAITSTATES + field.*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MCAN ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct MCAN ======================================================= */ +/** + * @brief MCAN + */ + typedef struct { /*!< MCAN Structure */ + __IM uint32_t RESERVED; + __IM uint32_t ENDN; /*!< (@ 0x00000004) Endian Register */ + __IM uint32_t RESERVED1; + __IOM uint32_t DBTP; /*!< (@ 0x0000000C) Data Bit Timing and Prescaler Register */ + __IOM uint32_t TEST; /*!< (@ 0x00000010) Test Register */ + __IOM uint32_t RWD; /*!< (@ 0x00000014) RAM Watchdog */ + __IOM uint32_t CCCR; /*!< (@ 0x00000018) CC Control Register */ + __IOM uint32_t NBTP; /*!< (@ 0x0000001C) Nominal Bit Timing and Prescaler Register */ + __IOM uint32_t TSCC; /*!< (@ 0x00000020) Timestamp Counter Configuration */ + __IOM uint32_t TSCV; /*!< (@ 0x00000024) Timestamp Counter Value */ + __IOM uint32_t TOCC; /*!< (@ 0x00000028) Timeout Counter Configuration */ + __IOM uint32_t TOCV; /*!< (@ 0x0000002C) Timeout Counter Value */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t ECR; /*!< (@ 0x00000040) Error Counter Register */ + __IOM uint32_t PSR; /*!< (@ 0x00000044) Protocol Status Register */ + __IOM uint32_t TDCR; /*!< (@ 0x00000048) Transmitter Delay Compensation Register */ + __IM uint32_t RESERVED3; + __IOM uint32_t IR; /*!< (@ 0x00000050) Interrupt Register */ + __IOM uint32_t IE; /*!< (@ 0x00000054) Interrupt Enable */ + __IOM uint32_t ILS; /*!< (@ 0x00000058) Interrupt Line Select */ + __IOM uint32_t ILE; /*!< (@ 0x0000005C) Interrupt Line Enable */ + __IM uint32_t RESERVED4[8]; + __IOM uint32_t GFC; /*!< (@ 0x00000080) Global Filter Configuration */ + __IOM uint32_t SIDFC; /*!< (@ 0x00000084) Standard ID Filter Configuration */ + __IOM uint32_t XIDFC; /*!< (@ 0x00000088) Extended ID Filter Configuration */ + __IM uint32_t RESERVED5; + __IOM uint32_t XIDAM; /*!< (@ 0x00000090) Extended ID AND Mask */ + __IM uint32_t HPMS; /*!< (@ 0x00000094) High Priority Message Status */ + __IOM uint32_t NDAT1; /*!< (@ 0x00000098) New Data 1 */ + __IOM uint32_t NDAT2; /*!< (@ 0x0000009C) New Data 2 */ + __IOM uint32_t RXF0C; /*!< (@ 0x000000A0) Rx FIFO 0 Configuration */ + __IM uint32_t RXF0S; /*!< (@ 0x000000A4) Rx FIFO 0 Status */ + __IOM uint32_t RXF0A; /*!< (@ 0x000000A8) Rx FIFO 0 Acknowledge */ + __IOM uint32_t RXBC; /*!< (@ 0x000000AC) Rx Buffer Configuration */ + __IOM uint32_t RXF1C; /*!< (@ 0x000000B0) Rx FIFO 1 Configuration */ + __IM uint32_t RXF1S; /*!< (@ 0x000000B4) Rx FIFO 1 Status */ + __IOM uint32_t RXF1A; /*!< (@ 0x000000B8) Rx FIFO 1 Acknowledge */ + __IOM uint32_t RXESC; /*!< (@ 0x000000BC) Rx Buffer / FIFO Element Size Configuration */ + __IOM uint32_t TXBC; /*!< (@ 0x000000C0) Tx Buffer Configuration */ + __IM uint32_t TXFQS; /*!< (@ 0x000000C4) Tx FIFO/Queue Status */ + __IOM uint32_t TXESC; /*!< (@ 0x000000C8) Tx Buffer Element Size Configuration */ + __IM uint32_t TXBRP; /*!< (@ 0x000000CC) Tx Buffer Request Pending */ + __IOM uint32_t TXBAR; /*!< (@ 0x000000D0) Tx Buffer Add Request */ + __IOM uint32_t TXBCR; /*!< (@ 0x000000D4) Tx Buffer Cancellation Request */ + __IM uint32_t TXBTO; /*!< (@ 0x000000D8) Tx Buffer Transmission Occurred */ + __IM uint32_t TXBCF; /*!< (@ 0x000000DC) Tx Buffer Cancellation Finished */ + __IOM uint32_t TXBTIE; /*!< (@ 0x000000E0) Tx Buffer Transmission Interrupt Enable */ + __IOM uint32_t TXBCIE; /*!< (@ 0x000000E4) Tx Buffer Cancellation Finished Interrupt Enable */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t TXEFC; /*!< (@ 0x000000F0) Tx Event FIFO Configuration */ + __IM uint32_t TXEFS; /*!< (@ 0x000000F4) Tx Event FIFO Status */ + __IOM uint32_t TXEFA; /*!< (@ 0x000000F8) Tx Event FIFO Acknowledge */ + } NRF_MCAN_Type; /*!< Size = 252 (0x0FC) */ + +/* MCAN_ENDN: Endian Register */ + #define MCAN_ENDN_ResetValue (0x00000000UL) /*!< Reset value of ENDN register. */ + +/* ETV @Bits 0..31 : Endianness Test Value */ + #define MCAN_ENDN_ETV_Pos (0UL) /*!< Position of ETV field. */ + #define MCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << MCAN_ENDN_ETV_Pos) /*!< Bit mask of ETV field. */ + + +/* MCAN_DBTP: Data Bit Timing and Prescaler Register */ + #define MCAN_DBTP_ResetValue (0x00000000UL) /*!< Reset value of DBTP register. */ + +/* DSJW @Bits 0..3 : Data (Re)Synchronization Jump Width */ + #define MCAN_DBTP_DSJW_Pos (0UL) /*!< Position of DSJW field. */ + #define MCAN_DBTP_DSJW_Msk (0xFUL << MCAN_DBTP_DSJW_Pos) /*!< Bit mask of DSJW field. */ + +/* DTSEG2 @Bits 4..7 : Data time segment after sample point */ + #define MCAN_DBTP_DTSEG2_Pos (4UL) /*!< Position of DTSEG2 field. */ + #define MCAN_DBTP_DTSEG2_Msk (0xFUL << MCAN_DBTP_DTSEG2_Pos) /*!< Bit mask of DTSEG2 field. */ + +/* DTSEG1 @Bits 8..12 : Data time segment before sample point */ + #define MCAN_DBTP_DTSEG1_Pos (8UL) /*!< Position of DTSEG1 field. */ + #define MCAN_DBTP_DTSEG1_Msk (0x1FUL << MCAN_DBTP_DTSEG1_Pos) /*!< Bit mask of DTSEG1 field. */ + +/* DBRP @Bits 16..20 : Data Bit Rate Prescaler */ + #define MCAN_DBTP_DBRP_Pos (16UL) /*!< Position of DBRP field. */ + #define MCAN_DBTP_DBRP_Msk (0x1FUL << MCAN_DBTP_DBRP_Pos) /*!< Bit mask of DBRP field. */ + +/* TDC @Bit 23 : Transmitter Delay Compensation */ + #define MCAN_DBTP_TDC_Pos (23UL) /*!< Position of TDC field. */ + #define MCAN_DBTP_TDC_Msk (0x1UL << MCAN_DBTP_TDC_Pos) /*!< Bit mask of TDC field. */ + #define MCAN_DBTP_TDC_Min (0x0UL) /*!< Min enumerator value of TDC field. */ + #define MCAN_DBTP_TDC_Max (0x1UL) /*!< Max enumerator value of TDC field. */ + #define MCAN_DBTP_TDC_Disabled (0x0UL) /*!< (unspecified) */ + #define MCAN_DBTP_TDC_Enabled (0x1UL) /*!< (unspecified) */ + + +/* MCAN_TEST: Test Register */ + #define MCAN_TEST_ResetValue (0x00000000UL) /*!< Reset value of TEST register. */ + +/* LBCK @Bit 4 : Loop Back Mode */ + #define MCAN_TEST_LBCK_Pos (4UL) /*!< Position of LBCK field. */ + #define MCAN_TEST_LBCK_Msk (0x1UL << MCAN_TEST_LBCK_Pos) /*!< Bit mask of LBCK field. */ + #define MCAN_TEST_LBCK_Min (0x0UL) /*!< Min enumerator value of LBCK field. */ + #define MCAN_TEST_LBCK_Max (0x1UL) /*!< Max enumerator value of LBCK field. */ + #define MCAN_TEST_LBCK_Disabled (0x0UL) /*!< Loop Back Mode is disabled */ + #define MCAN_TEST_LBCK_Enabled (0x1UL) /*!< Loop Back Mode is enabled */ + +/* TX @Bits 5..6 : Control of Transmit Pin */ + #define MCAN_TEST_TX_Pos (5UL) /*!< Position of TX field. */ + #define MCAN_TEST_TX_Msk (0x3UL << MCAN_TEST_TX_Pos) /*!< Bit mask of TX field. */ + #define MCAN_TEST_TX_Min (0x0UL) /*!< Min enumerator value of TX field. */ + #define MCAN_TEST_TX_Max (0x3UL) /*!< Max enumerator value of TX field. */ + #define MCAN_TEST_TX_CanCore (0x0UL) /*!< controlled by the CAN Core, updated at the end of the CAN bit time */ + #define MCAN_TEST_TX_Monitored (0x1UL) /*!< Sample Point can be monitored at pin m_can_tx */ + #define MCAN_TEST_TX_Dominant (0x2UL) /*!< Dominant (0) level at pin m_can_tx */ + #define MCAN_TEST_TX_Recessive (0x3UL) /*!< Recessive (1) at pin m_can_tx */ + +/* RX @Bit 7 : Receive Pin */ + #define MCAN_TEST_RX_Pos (7UL) /*!< Position of RX field. */ + #define MCAN_TEST_RX_Msk (0x1UL << MCAN_TEST_RX_Pos) /*!< Bit mask of RX field. */ + #define MCAN_TEST_RX_Min (0x0UL) /*!< Min enumerator value of RX field. */ + #define MCAN_TEST_RX_Max (0x1UL) /*!< Max enumerator value of RX field. */ + #define MCAN_TEST_RX_Dominant (0x0UL) /*!< The CAN bus is dominant (m_can_rx = 0) */ + #define MCAN_TEST_RX_Recessive (0x1UL) /*!< The CAN bus is recessive (m_can_rx = '1') */ + +/* TXBNP @Bits 8..12 : Tx Buffer Number Prepared */ + #define MCAN_TEST_TXBNP_Pos (8UL) /*!< Position of TXBNP field. */ + #define MCAN_TEST_TXBNP_Msk (0x1FUL << MCAN_TEST_TXBNP_Pos) /*!< Bit mask of TXBNP field. */ + +/* PVAL @Bit 13 : Prepared Valid */ + #define MCAN_TEST_PVAL_Pos (13UL) /*!< Position of PVAL field. */ + #define MCAN_TEST_PVAL_Msk (0x1UL << MCAN_TEST_PVAL_Pos) /*!< Bit mask of PVAL field. */ + #define MCAN_TEST_PVAL_Min (0x0UL) /*!< Min enumerator value of PVAL field. */ + #define MCAN_TEST_PVAL_Max (0x1UL) /*!< Max enumerator value of PVAL field. */ + #define MCAN_TEST_PVAL_NotValid (0x0UL) /*!< Value of TXBNP not valid */ + #define MCAN_TEST_PVAL_Valid (0x1UL) /*!< Value of TXBNP valid */ + +/* TXBNS @Bits 16..20 : Tx Buffer Number Started */ + #define MCAN_TEST_TXBNS_Pos (16UL) /*!< Position of TXBNS field. */ + #define MCAN_TEST_TXBNS_Msk (0x1FUL << MCAN_TEST_TXBNS_Pos) /*!< Bit mask of TXBNS field. */ + +/* SVAL @Bit 21 : Started Valid */ + #define MCAN_TEST_SVAL_Pos (21UL) /*!< Position of SVAL field. */ + #define MCAN_TEST_SVAL_Msk (0x1UL << MCAN_TEST_SVAL_Pos) /*!< Bit mask of SVAL field. */ + #define MCAN_TEST_SVAL_Min (0x0UL) /*!< Min enumerator value of SVAL field. */ + #define MCAN_TEST_SVAL_Max (0x1UL) /*!< Max enumerator value of SVAL field. */ + #define MCAN_TEST_SVAL_NotValid (0x0UL) /*!< Value of TXBNP not valid */ + #define MCAN_TEST_SVAL_Valid (0x1UL) /*!< Value of TXBNP valid */ + + +/* MCAN_RWD: RAM Watchdog */ + #define MCAN_RWD_ResetValue (0x00000000UL) /*!< Reset value of RWD register. */ + +/* WDC @Bits 0..7 : Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. */ + #define MCAN_RWD_WDC_Pos (0UL) /*!< Position of WDC field. */ + #define MCAN_RWD_WDC_Msk (0xFFUL << MCAN_RWD_WDC_Pos) /*!< Bit mask of WDC field. */ + +/* WDV @Bits 8..15 : Actual Message RAM Watchdog Counter Value. */ + #define MCAN_RWD_WDV_Pos (8UL) /*!< Position of WDV field. */ + #define MCAN_RWD_WDV_Msk (0xFFUL << MCAN_RWD_WDV_Pos) /*!< Bit mask of WDV field. */ + + +/* MCAN_CCCR: CC Control Register */ + #define MCAN_CCCR_ResetValue (0x00000000UL) /*!< Reset value of CCCR register. */ + +/* INIT @Bit 0 : Initialization */ + #define MCAN_CCCR_INIT_Pos (0UL) /*!< Position of INIT field. */ + #define MCAN_CCCR_INIT_Msk (0x1UL << MCAN_CCCR_INIT_Pos) /*!< Bit mask of INIT field. */ + #define MCAN_CCCR_INIT_Min (0x0UL) /*!< Min enumerator value of INIT field. */ + #define MCAN_CCCR_INIT_Max (0x1UL) /*!< Max enumerator value of INIT field. */ + #define MCAN_CCCR_INIT_Normal (0x0UL) /*!< Normal Operation */ + #define MCAN_CCCR_INIT_Initialization (0x1UL) /*!< Initialization is started */ + +/* CCE @Bit 1 : Configuration Change Enable */ + #define MCAN_CCCR_CCE_Pos (1UL) /*!< Position of CCE field. */ + #define MCAN_CCCR_CCE_Msk (0x1UL << MCAN_CCCR_CCE_Pos) /*!< Bit mask of CCE field. */ + #define MCAN_CCCR_CCE_Min (0x0UL) /*!< Min enumerator value of CCE field. */ + #define MCAN_CCCR_CCE_Max (0x1UL) /*!< Max enumerator value of CCE field. */ + #define MCAN_CCCR_CCE_Disabled (0x0UL) /*!< The CPU has no write access to the protected configuration registers */ + #define MCAN_CCCR_CCE_Enabled (0x1UL) /*!< The CPU has write access to the protected configuration registers + (while CCCR.INIT = '1')*/ + +/* ASM @Bit 2 : Restricted Operation Mode */ + #define MCAN_CCCR_ASM_Pos (2UL) /*!< Position of ASM field. */ + #define MCAN_CCCR_ASM_Msk (0x1UL << MCAN_CCCR_ASM_Pos) /*!< Bit mask of ASM field. */ + #define MCAN_CCCR_ASM_Min (0x0UL) /*!< Min enumerator value of ASM field. */ + #define MCAN_CCCR_ASM_Max (0x1UL) /*!< Max enumerator value of ASM field. */ + #define MCAN_CCCR_ASM_Disabled (0x0UL) /*!< Normal CAN operation */ + #define MCAN_CCCR_ASM_Enabled (0x1UL) /*!< Restricted Operation Mode active */ + +/* CSA @Bit 3 : Clock Stop Acknowledge */ + #define MCAN_CCCR_CSA_Pos (3UL) /*!< Position of CSA field. */ + #define MCAN_CCCR_CSA_Msk (0x1UL << MCAN_CCCR_CSA_Pos) /*!< Bit mask of CSA field. */ + #define MCAN_CCCR_CSA_Min (0x0UL) /*!< Min enumerator value of CSA field. */ + #define MCAN_CCCR_CSA_Max (0x1UL) /*!< Max enumerator value of CSA field. */ + #define MCAN_CCCR_CSA_Disabled (0x0UL) /*!< No clock stop acknowledged */ + #define MCAN_CCCR_CSA_Enabled (0x1UL) /*!< MCAN may be set in power down by stopping m_can_hclk and m_can_cclk */ + +/* CSR @Bit 4 : Clock Stop Request */ + #define MCAN_CCCR_CSR_Pos (4UL) /*!< Position of CSR field. */ + #define MCAN_CCCR_CSR_Msk (0x1UL << MCAN_CCCR_CSR_Pos) /*!< Bit mask of CSR field. */ + #define MCAN_CCCR_CSR_Min (0x0UL) /*!< Min enumerator value of CSR field. */ + #define MCAN_CCCR_CSR_Max (0x1UL) /*!< Max enumerator value of CSR field. */ + #define MCAN_CCCR_CSR_Disabled (0x0UL) /*!< No clock stop is requested */ + #define MCAN_CCCR_CSR_Enabled (0x1UL) /*!< Clock stop requested. */ + +/* MON @Bit 5 : Bus Monitoring Mode */ + #define MCAN_CCCR_MON_Pos (5UL) /*!< Position of MON field. */ + #define MCAN_CCCR_MON_Msk (0x1UL << MCAN_CCCR_MON_Pos) /*!< Bit mask of MON field. */ + #define MCAN_CCCR_MON_Min (0x0UL) /*!< Min enumerator value of MON field. */ + #define MCAN_CCCR_MON_Max (0x1UL) /*!< Max enumerator value of MON field. */ + #define MCAN_CCCR_MON_Disabled (0x0UL) /*!< Bus Monitoring Mode is disabled */ + #define MCAN_CCCR_MON_Enabled (0x1UL) /*!< Bus Monitoring Mode is enabled */ + +/* DAR @Bit 6 : Disable Automatic Retransmission */ + #define MCAN_CCCR_DAR_Pos (6UL) /*!< Position of DAR field. */ + #define MCAN_CCCR_DAR_Msk (0x1UL << MCAN_CCCR_DAR_Pos) /*!< Bit mask of DAR field. */ + #define MCAN_CCCR_DAR_Min (0x0UL) /*!< Min enumerator value of DAR field. */ + #define MCAN_CCCR_DAR_Max (0x1UL) /*!< Max enumerator value of DAR field. */ + #define MCAN_CCCR_DAR_Enabled (0x0UL) /*!< Automatic retransmission of messages not transmitted successfully + enabled*/ + #define MCAN_CCCR_DAR_Disabled (0x1UL) /*!< Automatic retransmission disabled */ + +/* TEST @Bit 7 : Test Mode Enable */ + #define MCAN_CCCR_TEST_Pos (7UL) /*!< Position of TEST field. */ + #define MCAN_CCCR_TEST_Msk (0x1UL << MCAN_CCCR_TEST_Pos) /*!< Bit mask of TEST field. */ + #define MCAN_CCCR_TEST_Min (0x0UL) /*!< Min enumerator value of TEST field. */ + #define MCAN_CCCR_TEST_Max (0x1UL) /*!< Max enumerator value of TEST field. */ + #define MCAN_CCCR_TEST_Disabled (0x0UL) /*!< Normal operation, register TEST holds reset values */ + #define MCAN_CCCR_TEST_Enabled (0x1UL) /*!< Test Mode, write access to register TEST enabled */ + +/* FDOE @Bit 8 : FD Operation Enable */ + #define MCAN_CCCR_FDOE_Pos (8UL) /*!< Position of FDOE field. */ + #define MCAN_CCCR_FDOE_Msk (0x1UL << MCAN_CCCR_FDOE_Pos) /*!< Bit mask of FDOE field. */ + #define MCAN_CCCR_FDOE_Min (0x0UL) /*!< Min enumerator value of FDOE field. */ + #define MCAN_CCCR_FDOE_Max (0x1UL) /*!< Max enumerator value of FDOE field. */ + #define MCAN_CCCR_FDOE_Disabled (0x0UL) /*!< FD operation disabled */ + #define MCAN_CCCR_FDOE_Enabled (0x1UL) /*!< FD operation enabled */ + +/* BRSE @Bit 9 : Bit Rate Switch Enable */ + #define MCAN_CCCR_BRSE_Pos (9UL) /*!< Position of BRSE field. */ + #define MCAN_CCCR_BRSE_Msk (0x1UL << MCAN_CCCR_BRSE_Pos) /*!< Bit mask of BRSE field. */ + #define MCAN_CCCR_BRSE_Min (0x0UL) /*!< Min enumerator value of BRSE field. */ + #define MCAN_CCCR_BRSE_Max (0x1UL) /*!< Max enumerator value of BRSE field. */ + #define MCAN_CCCR_BRSE_Disabled (0x0UL) /*!< Bit rate switching for transmissions disabled */ + #define MCAN_CCCR_BRSE_Enabled (0x1UL) /*!< Bit rate switching for transmissions enabled */ + +/* WMM @Bit 11 : Wide Message Marker */ + #define MCAN_CCCR_WMM_Pos (11UL) /*!< Position of WMM field. */ + #define MCAN_CCCR_WMM_Msk (0x1UL << MCAN_CCCR_WMM_Pos) /*!< Bit mask of WMM field. */ + #define MCAN_CCCR_WMM_Min (0x0UL) /*!< Min enumerator value of WMM field. */ + #define MCAN_CCCR_WMM_Max (0x1UL) /*!< Max enumerator value of WMM field. */ + #define MCAN_CCCR_WMM_Disabled (0x0UL) /*!< 8-bit Message Marker used */ + #define MCAN_CCCR_WMM_Enabled (0x1UL) /*!< 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event + FIFO*/ + +/* PXHD @Bit 12 : Protocol Exception Handling Disable */ + #define MCAN_CCCR_PXHD_Pos (12UL) /*!< Position of PXHD field. */ + #define MCAN_CCCR_PXHD_Msk (0x1UL << MCAN_CCCR_PXHD_Pos) /*!< Bit mask of PXHD field. */ + #define MCAN_CCCR_PXHD_Min (0x0UL) /*!< Min enumerator value of PXHD field. */ + #define MCAN_CCCR_PXHD_Max (0x1UL) /*!< Max enumerator value of PXHD field. */ + #define MCAN_CCCR_PXHD_Enabled (0x0UL) /*!< Protocol exception handling enabled */ + #define MCAN_CCCR_PXHD_Disabled (0x1UL) /*!< Protocol exception handling disabled */ + +/* EFBI @Bit 13 : Edge Filtering during Bus Integration */ + #define MCAN_CCCR_EFBI_Pos (13UL) /*!< Position of EFBI field. */ + #define MCAN_CCCR_EFBI_Msk (0x1UL << MCAN_CCCR_EFBI_Pos) /*!< Bit mask of EFBI field. */ + #define MCAN_CCCR_EFBI_Min (0x0UL) /*!< Min enumerator value of EFBI field. */ + #define MCAN_CCCR_EFBI_Max (0x1UL) /*!< Max enumerator value of EFBI field. */ + #define MCAN_CCCR_EFBI_Disabled (0x0UL) /*!< Edge filtering disabled */ + #define MCAN_CCCR_EFBI_Enabled (0x1UL) /*!< Two consecutive dominant tq required to detect an edge for hard + synchronization*/ + +/* TXP @Bit 14 : Transmit Pause */ + #define MCAN_CCCR_TXP_Pos (14UL) /*!< Position of TXP field. */ + #define MCAN_CCCR_TXP_Msk (0x1UL << MCAN_CCCR_TXP_Pos) /*!< Bit mask of TXP field. */ + #define MCAN_CCCR_TXP_Min (0x0UL) /*!< Min enumerator value of TXP field. */ + #define MCAN_CCCR_TXP_Max (0x1UL) /*!< Max enumerator value of TXP field. */ + #define MCAN_CCCR_TXP_Disabled (0x0UL) /*!< Transmit pause disabled */ + #define MCAN_CCCR_TXP_Enabled (0x1UL) /*!< Transmit pause enabled */ + +/* NISO @Bit 15 : Non ISO Operation */ + #define MCAN_CCCR_NISO_Pos (15UL) /*!< Position of NISO field. */ + #define MCAN_CCCR_NISO_Msk (0x1UL << MCAN_CCCR_NISO_Pos) /*!< Bit mask of NISO field. */ + #define MCAN_CCCR_NISO_Min (0x0UL) /*!< Min enumerator value of NISO field. */ + #define MCAN_CCCR_NISO_Max (0x1UL) /*!< Max enumerator value of NISO field. */ + #define MCAN_CCCR_NISO_Disabled (0x0UL) /*!< CAN FD frame format according to ISO 11898-1:2015 */ + #define MCAN_CCCR_NISO_Enabled (0x1UL) /*!< CAN FD frame format according to Bosch CAN FD Specification V1.0 */ + + +/* MCAN_NBTP: Nominal Bit Timing and Prescaler Register */ + #define MCAN_NBTP_ResetValue (0x00000000UL) /*!< Reset value of NBTP register. */ + +/* NTSEG2 @Bits 0..6 : Nominal Time segment after sample point */ + #define MCAN_NBTP_NTSEG2_Pos (0UL) /*!< Position of NTSEG2 field. */ + #define MCAN_NBTP_NTSEG2_Msk (0x7FUL << MCAN_NBTP_NTSEG2_Pos) /*!< Bit mask of NTSEG2 field. */ + +/* NTSEG1 @Bits 8..15 : Nominal Time segment before sample point */ + #define MCAN_NBTP_NTSEG1_Pos (8UL) /*!< Position of NTSEG1 field. */ + #define MCAN_NBTP_NTSEG1_Msk (0xFFUL << MCAN_NBTP_NTSEG1_Pos) /*!< Bit mask of NTSEG1 field. */ + +/* NBRP @Bits 16..24 : Nominal Bit Rate Prescaler */ + #define MCAN_NBTP_NBRP_Pos (16UL) /*!< Position of NBRP field. */ + #define MCAN_NBTP_NBRP_Msk (0x1FFUL << MCAN_NBTP_NBRP_Pos) /*!< Bit mask of NBRP field. */ + +/* NSJW @Bits 25..31 : Nominal (Re)Synchronization Jump Width */ + #define MCAN_NBTP_NSJW_Pos (25UL) /*!< Position of NSJW field. */ + #define MCAN_NBTP_NSJW_Msk (0x7FUL << MCAN_NBTP_NSJW_Pos) /*!< Bit mask of NSJW field. */ + + +/* MCAN_TSCC: Timestamp Counter Configuration */ + #define MCAN_TSCC_ResetValue (0x00000000UL) /*!< Reset value of TSCC register. */ + +/* TSS @Bits 0..1 : Timestamp Select */ + #define MCAN_TSCC_TSS_Pos (0UL) /*!< Position of TSS field. */ + #define MCAN_TSCC_TSS_Msk (0x3UL << MCAN_TSCC_TSS_Pos) /*!< Bit mask of TSS field. */ + #define MCAN_TSCC_TSS_Min (0x0UL) /*!< Min enumerator value of TSS field. */ + #define MCAN_TSCC_TSS_Max (0x3UL) /*!< Max enumerator value of TSS field. */ + #define MCAN_TSCC_TSS_Zero (0x0UL) /*!< Timestamp counter value always 0x0000 */ + #define MCAN_TSCC_TSS_Increment (0x1UL) /*!< Timestamp counter value incremented according to TCP */ + #define MCAN_TSCC_TSS_External (0x2UL) /*!< External timestamp counter value used */ + #define MCAN_TSCC_TSS_Zero0 (0x3UL) /*!< Same as Zero */ + +/* TCP @Bits 16..19 : Timestamp Counter Prescaler */ + #define MCAN_TSCC_TCP_Pos (16UL) /*!< Position of TCP field. */ + #define MCAN_TSCC_TCP_Msk (0xFUL << MCAN_TSCC_TCP_Pos) /*!< Bit mask of TCP field. */ + + +/* MCAN_TSCV: Timestamp Counter Value */ + #define MCAN_TSCV_ResetValue (0x00000000UL) /*!< Reset value of TSCV register. */ + +/* TSC @Bits 0..15 : Timestamp Counter */ + #define MCAN_TSCV_TSC_Pos (0UL) /*!< Position of TSC field. */ + #define MCAN_TSCV_TSC_Msk (0xFFFFUL << MCAN_TSCV_TSC_Pos) /*!< Bit mask of TSC field. */ + + +/* MCAN_TOCC: Timeout Counter Configuration */ + #define MCAN_TOCC_ResetValue (0x00000000UL) /*!< Reset value of TOCC register. */ + +/* ETOC @Bit 0 : Enable Timeout Counter */ + #define MCAN_TOCC_ETOC_Pos (0UL) /*!< Position of ETOC field. */ + #define MCAN_TOCC_ETOC_Msk (0x1UL << MCAN_TOCC_ETOC_Pos) /*!< Bit mask of ETOC field. */ + #define MCAN_TOCC_ETOC_Min (0x0UL) /*!< Min enumerator value of ETOC field. */ + #define MCAN_TOCC_ETOC_Max (0x1UL) /*!< Max enumerator value of ETOC field. */ + #define MCAN_TOCC_ETOC_Disabled (0x0UL) /*!< Timeout Counter disabled */ + #define MCAN_TOCC_ETOC_Enabled (0x1UL) /*!< Timeout Counter enabled */ + +/* TOS @Bits 1..2 : Timeout Select */ + #define MCAN_TOCC_TOS_Pos (1UL) /*!< Position of TOS field. */ + #define MCAN_TOCC_TOS_Msk (0x3UL << MCAN_TOCC_TOS_Pos) /*!< Bit mask of TOS field. */ + #define MCAN_TOCC_TOS_Min (0x0UL) /*!< Min enumerator value of TOS field. */ + #define MCAN_TOCC_TOS_Max (0x3UL) /*!< Max enumerator value of TOS field. */ + #define MCAN_TOCC_TOS_Continuous (0x0UL) /*!< Continuous operation */ + #define MCAN_TOCC_TOS_TxEvent (0x1UL) /*!< Timeout controlled by Tx Event FIFO */ + #define MCAN_TOCC_TOS_RxFifo0 (0x2UL) /*!< Timeout controlled by Rx FIFO 0 */ + #define MCAN_TOCC_TOS_RxFifo1 (0x3UL) /*!< Timeout controlled by Rx FIFO 1 */ + +/* TOP @Bits 16..31 : Timeout Period */ + #define MCAN_TOCC_TOP_Pos (16UL) /*!< Position of TOP field. */ + #define MCAN_TOCC_TOP_Msk (0xFFFFUL << MCAN_TOCC_TOP_Pos) /*!< Bit mask of TOP field. */ + + +/* MCAN_TOCV: Timeout Counter Value */ + #define MCAN_TOCV_ResetValue (0x00000000UL) /*!< Reset value of TOCV register. */ + +/* TOC @Bits 0..15 : Timeout Counter */ + #define MCAN_TOCV_TOC_Pos (0UL) /*!< Position of TOC field. */ + #define MCAN_TOCV_TOC_Msk (0xFFFFUL << MCAN_TOCV_TOC_Pos) /*!< Bit mask of TOC field. */ + + +/* MCAN_ECR: Error Counter Register */ + #define MCAN_ECR_ResetValue (0x00000000UL) /*!< Reset value of ECR register. */ + +/* TEC @Bits 0..7 : Transmit Error Counter */ + #define MCAN_ECR_TEC_Pos (0UL) /*!< Position of TEC field. */ + #define MCAN_ECR_TEC_Msk (0xFFUL << MCAN_ECR_TEC_Pos) /*!< Bit mask of TEC field. */ + +/* REC @Bits 8..14 : Receive Error Counter */ + #define MCAN_ECR_REC_Pos (8UL) /*!< Position of REC field. */ + #define MCAN_ECR_REC_Msk (0x7FUL << MCAN_ECR_REC_Pos) /*!< Bit mask of REC field. */ + +/* RP @Bit 15 : Receive Error Passive */ + #define MCAN_ECR_RP_Pos (15UL) /*!< Position of RP field. */ + #define MCAN_ECR_RP_Msk (0x1UL << MCAN_ECR_RP_Pos) /*!< Bit mask of RP field. */ + #define MCAN_ECR_RP_Min (0x0UL) /*!< Min enumerator value of RP field. */ + #define MCAN_ECR_RP_Max (0x1UL) /*!< Max enumerator value of RP field. */ + #define MCAN_ECR_RP_Below (0x0UL) /*!< The Receive Error Counter is below the error passive level of 128 */ + #define MCAN_ECR_RP_Reached (0x1UL) /*!< The Receive Error Counter has reached the error passive level of 128 */ + +/* CEL @Bits 16..23 : CAN Error Logging */ + #define MCAN_ECR_CEL_Pos (16UL) /*!< Position of CEL field. */ + #define MCAN_ECR_CEL_Msk (0xFFUL << MCAN_ECR_CEL_Pos) /*!< Bit mask of CEL field. */ + + +/* MCAN_PSR: Protocol Status Register */ + #define MCAN_PSR_ResetValue (0x00000000UL) /*!< Reset value of PSR register. */ + +/* LEC @Bits 0..2 : Last Error Code */ + #define MCAN_PSR_LEC_Pos (0UL) /*!< Position of LEC field. */ + #define MCAN_PSR_LEC_Msk (0x7UL << MCAN_PSR_LEC_Pos) /*!< Bit mask of LEC field. */ + #define MCAN_PSR_LEC_Min (0x0UL) /*!< Min enumerator value of LEC field. */ + #define MCAN_PSR_LEC_Max (0x7UL) /*!< Max enumerator value of LEC field. */ + #define MCAN_PSR_LEC_NoError (0x0UL) /*!< No error occurred since LEC has been reset by successful reception or + transmission.*/ + #define MCAN_PSR_LEC_StuffError (0x1UL) /*!< More than 5 equal bits in a sequence have occurred in a part of a + received message where this is not allowed.*/ + #define MCAN_PSR_LEC_FormError (0x2UL) /*!< A fixed format part of a received frame has the wrong format. */ + #define MCAN_PSR_LEC_AckError (0x3UL) /*!< The message transmitted by the MCAN was not acknowledged by another + node.*/ + #define MCAN_PSR_LEC_Bit1Error (0x4UL) /*!< During the transmission of a message (with the exception of the + arbitration field), the device wanted to send a recessive level (bit + of logical value 1), but the monitored bus value was dominant.*/ + #define MCAN_PSR_LEC_Bit0Error (0x5UL) /*!< During the transmission of a message (or acknowledge bit, or active + error flag, or overload flag), the device wanted to send a dominant + level (data or identifier bit logical value '0'), but the monitored + bus value was recessive. During Bus_Off recovery this status is set + each time a sequence of 11 recessive bits has been monitored. This + enables the CPU to monitor the proceeding of the Bus_Off recovery + sequence (indicating the bus is not stuck at dominant or continuously + disturbed).*/ + #define MCAN_PSR_LEC_CRCError (0x6UL) /*!< The CRC check sum of a received message was incorrect. The CRC of an + incoming message does not match with the CRC calculated from the + received data.*/ + #define MCAN_PSR_LEC_NoChange (0x7UL) /*!< Any read access to the Protocol Status Register re-initializes the LEC + to '7'. When the LEC shows the value '7', no CAN bus event was + detected since the last CPU read access to the Protocol Status + Register.*/ + +/* ACT @Bits 3..4 : Activity */ + #define MCAN_PSR_ACT_Pos (3UL) /*!< Position of ACT field. */ + #define MCAN_PSR_ACT_Msk (0x3UL << MCAN_PSR_ACT_Pos) /*!< Bit mask of ACT field. */ + #define MCAN_PSR_ACT_Min (0x0UL) /*!< Min enumerator value of ACT field. */ + #define MCAN_PSR_ACT_Max (0x3UL) /*!< Max enumerator value of ACT field. */ + #define MCAN_PSR_ACT_Synchronizing (0x0UL) /*!< Node is synchronizing on CAN communication */ + #define MCAN_PSR_ACT_Idle (0x1UL) /*!< Node is neither receiver nor tr ansmitter */ + #define MCAN_PSR_ACT_Receiver (0x2UL) /*!< Node is operating as receiver */ + #define MCAN_PSR_ACT_Transmitter (0x3UL) /*!< Node is operating as transmitter */ + +/* EP @Bit 5 : Error Passive */ + #define MCAN_PSR_EP_Pos (5UL) /*!< Position of EP field. */ + #define MCAN_PSR_EP_Msk (0x1UL << MCAN_PSR_EP_Pos) /*!< Bit mask of EP field. */ + #define MCAN_PSR_EP_Min (0x0UL) /*!< Min enumerator value of EP field. */ + #define MCAN_PSR_EP_Max (0x1UL) /*!< Max enumerator value of EP field. */ + #define MCAN_PSR_EP_Active (0x0UL) /*!< The MCAN is in the Error_Active state. It normally takes part in bus + communication and sends an active error flag when an error has been + detected*/ + #define MCAN_PSR_EP_Passive (0x1UL) /*!< The MCAN is in the Error_Passive state */ + +/* EW @Bit 6 : Warning Status */ + #define MCAN_PSR_EW_Pos (6UL) /*!< Position of EW field. */ + #define MCAN_PSR_EW_Msk (0x1UL << MCAN_PSR_EW_Pos) /*!< Bit mask of EW field. */ + #define MCAN_PSR_EW_Min (0x0UL) /*!< Min enumerator value of EW field. */ + #define MCAN_PSR_EW_Max (0x1UL) /*!< Max enumerator value of EW field. */ + #define MCAN_PSR_EW_Below (0x0UL) /*!< Both error counters are below the Error_Warning limit of 96 */ + #define MCAN_PSR_EW_Reached (0x1UL) /*!< At least one of error counter has reached the Error_Warning limit of + 96*/ + +/* BO @Bit 7 : Bus_Off Status */ + #define MCAN_PSR_BO_Pos (7UL) /*!< Position of BO field. */ + #define MCAN_PSR_BO_Msk (0x1UL << MCAN_PSR_BO_Pos) /*!< Bit mask of BO field. */ + #define MCAN_PSR_BO_Min (0x0UL) /*!< Min enumerator value of BO field. */ + #define MCAN_PSR_BO_Max (0x1UL) /*!< Max enumerator value of BO field. */ + #define MCAN_PSR_BO_On (0x0UL) /*!< The MCAN is not Bus_Off */ + #define MCAN_PSR_BO_Off (0x1UL) /*!< The MCAN is in Bus_Off state */ + +/* DLEC @Bits 8..10 : Data Phase Last Error Code */ + #define MCAN_PSR_DLEC_Pos (8UL) /*!< Position of DLEC field. */ + #define MCAN_PSR_DLEC_Msk (0x7UL << MCAN_PSR_DLEC_Pos) /*!< Bit mask of DLEC field. */ + +/* RESI @Bit 11 : ESI flag of last received CAN FD Message */ + #define MCAN_PSR_RESI_Pos (11UL) /*!< Position of RESI field. */ + #define MCAN_PSR_RESI_Msk (0x1UL << MCAN_PSR_RESI_Pos) /*!< Bit mask of RESI field. */ + #define MCAN_PSR_RESI_Min (0x0UL) /*!< Min enumerator value of RESI field. */ + #define MCAN_PSR_RESI_Max (0x1UL) /*!< Max enumerator value of RESI field. */ + #define MCAN_PSR_RESI_NotReceived (0x0UL) /*!< Last received CAN FD message did not ha ve its ESI flag set */ + #define MCAN_PSR_RESI_Received (0x1UL) /*!< Last received CAN FD message had its ESI flag set */ + +/* RBRS @Bit 12 : BRS flag of last received CAN FD Message */ + #define MCAN_PSR_RBRS_Pos (12UL) /*!< Position of RBRS field. */ + #define MCAN_PSR_RBRS_Msk (0x1UL << MCAN_PSR_RBRS_Pos) /*!< Bit mask of RBRS field. */ + #define MCAN_PSR_RBRS_Min (0x0UL) /*!< Min enumerator value of RBRS field. */ + #define MCAN_PSR_RBRS_Max (0x1UL) /*!< Max enumerator value of RBRS field. */ + #define MCAN_PSR_RBRS_NotReceived (0x0UL) /*!< Last received CAN FD message did not ha ve its BRS flag set */ + #define MCAN_PSR_RBRS_Received (0x1UL) /*!< Last received CAN FD message had its BRS flag set */ + +/* RFDF @Bit 13 : Received a CAN FD Message */ + #define MCAN_PSR_RFDF_Pos (13UL) /*!< Position of RFDF field. */ + #define MCAN_PSR_RFDF_Msk (0x1UL << MCAN_PSR_RFDF_Pos) /*!< Bit mask of RFDF field. */ + #define MCAN_PSR_RFDF_Min (0x0UL) /*!< Min enumerator value of RFDF field. */ + #define MCAN_PSR_RFDF_Max (0x1UL) /*!< Max enumerator value of RFDF field. */ + #define MCAN_PSR_RFDF_NotReceived (0x0UL) /*!< Since this bit was reset by the CPU, no CAN FD message has been + received*/ + #define MCAN_PSR_RFDF_Received (0x1UL) /*!< Message in CAN FD format with FDF flag set has been received */ + +/* PXE @Bit 14 : Protocol Exception Event */ + #define MCAN_PSR_PXE_Pos (14UL) /*!< Position of PXE field. */ + #define MCAN_PSR_PXE_Msk (0x1UL << MCAN_PSR_PXE_Pos) /*!< Bit mask of PXE field. */ + #define MCAN_PSR_PXE_Min (0x0UL) /*!< Min enumerator value of PXE field. */ + #define MCAN_PSR_PXE_Max (0x1UL) /*!< Max enumerator value of PXE field. */ + #define MCAN_PSR_PXE_NotTriggered (0x0UL) /*!< No protocol exception event occurred since last read access */ + #define MCAN_PSR_PXE_Triggered (0x1UL) /*!< Protocol exception event occurred */ + +/* TDCV @Bits 16..22 : Transmitter Delay Compensation Value */ + #define MCAN_PSR_TDCV_Pos (16UL) /*!< Position of TDCV field. */ + #define MCAN_PSR_TDCV_Msk (0x7FUL << MCAN_PSR_TDCV_Pos) /*!< Bit mask of TDCV field. */ + + +/* MCAN_TDCR: Transmitter Delay Compensation Register */ + #define MCAN_TDCR_ResetValue (0x00000000UL) /*!< Reset value of TDCR register. */ + +/* TDCF @Bits 0..6 : Transmitter Delay Compensation Filter Window Length */ + #define MCAN_TDCR_TDCF_Pos (0UL) /*!< Position of TDCF field. */ + #define MCAN_TDCR_TDCF_Msk (0x7FUL << MCAN_TDCR_TDCF_Pos) /*!< Bit mask of TDCF field. */ + +/* TDCO @Bits 8..14 : Transmitter Delay Compensation SSP Offset */ + #define MCAN_TDCR_TDCO_Pos (8UL) /*!< Position of TDCO field. */ + #define MCAN_TDCR_TDCO_Msk (0x7FUL << MCAN_TDCR_TDCO_Pos) /*!< Bit mask of TDCO field. */ + + +/* MCAN_IR: Interrupt Register */ + #define MCAN_IR_ResetValue (0x00000000UL) /*!< Reset value of IR register. */ + +/* RF0N @Bit 0 : Rx FIFO 0 New Message */ + #define MCAN_IR_RF0N_Pos (0UL) /*!< Position of RF0N field. */ + #define MCAN_IR_RF0N_Msk (0x1UL << MCAN_IR_RF0N_Pos) /*!< Bit mask of RF0N field. */ + #define MCAN_IR_RF0N_Min (0x0UL) /*!< Min enumerator value of RF0N field. */ + #define MCAN_IR_RF0N_Max (0x1UL) /*!< Max enumerator value of RF0N field. */ + #define MCAN_IR_RF0N_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF0N_NotGenerated (0x0UL) /*!< No new message written to Rx FIFO 0 */ + #define MCAN_IR_RF0N_Generated (0x1UL) /*!< New message written to Rx FIFO 0 */ + +/* RF0W @Bit 1 : Rx FIFO 0 Watermark Reached */ + #define MCAN_IR_RF0W_Pos (1UL) /*!< Position of RF0W field. */ + #define MCAN_IR_RF0W_Msk (0x1UL << MCAN_IR_RF0W_Pos) /*!< Bit mask of RF0W field. */ + #define MCAN_IR_RF0W_Min (0x0UL) /*!< Min enumerator value of RF0W field. */ + #define MCAN_IR_RF0W_Max (0x1UL) /*!< Max enumerator value of RF0W field. */ + #define MCAN_IR_RF0W_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF0W_NotGenerated (0x0UL) /*!< Rx FIFO 0 fill level below watermark */ + #define MCAN_IR_RF0W_Generated (0x1UL) /*!< Rx FIFO 0 fill level reached watermark */ + +/* RF0F @Bit 2 : Rx FIFO 0 Full */ + #define MCAN_IR_RF0F_Pos (2UL) /*!< Position of RF0F field. */ + #define MCAN_IR_RF0F_Msk (0x1UL << MCAN_IR_RF0F_Pos) /*!< Bit mask of RF0F field. */ + #define MCAN_IR_RF0F_Min (0x0UL) /*!< Min enumerator value of RF0F field. */ + #define MCAN_IR_RF0F_Max (0x1UL) /*!< Max enumerator value of RF0F field. */ + #define MCAN_IR_RF0F_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF0F_NotGenerated (0x0UL) /*!< Rx FIFO 0 not full */ + #define MCAN_IR_RF0F_Generated (0x1UL) /*!< Rx FIFO 0 full */ + +/* RF0L @Bit 3 : Rx FIFO 0 Message Lost */ + #define MCAN_IR_RF0L_Pos (3UL) /*!< Position of RF0L field. */ + #define MCAN_IR_RF0L_Msk (0x1UL << MCAN_IR_RF0L_Pos) /*!< Bit mask of RF0L field. */ + #define MCAN_IR_RF0L_Min (0x0UL) /*!< Min enumerator value of RF0L field. */ + #define MCAN_IR_RF0L_Max (0x1UL) /*!< Max enumerator value of RF0L field. */ + #define MCAN_IR_RF0L_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF0L_NotGenerated (0x0UL) /*!< No Rx FIFO 0 message lost */ + #define MCAN_IR_RF0L_Generated (0x1UL) /*!< Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of + size zero*/ + +/* RF1N @Bit 4 : Rx FIFO 1 New Message */ + #define MCAN_IR_RF1N_Pos (4UL) /*!< Position of RF1N field. */ + #define MCAN_IR_RF1N_Msk (0x1UL << MCAN_IR_RF1N_Pos) /*!< Bit mask of RF1N field. */ + #define MCAN_IR_RF1N_Min (0x0UL) /*!< Min enumerator value of RF1N field. */ + #define MCAN_IR_RF1N_Max (0x1UL) /*!< Max enumerator value of RF1N field. */ + #define MCAN_IR_RF1N_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF1N_NotGenerated (0x0UL) /*!< No new message written to Rx FIFO 1 */ + #define MCAN_IR_RF1N_Generated (0x1UL) /*!< New message written to Rx FIFO 1 */ + +/* RF1W @Bit 5 : Rx FIFO 1 Watermark Reached */ + #define MCAN_IR_RF1W_Pos (5UL) /*!< Position of RF1W field. */ + #define MCAN_IR_RF1W_Msk (0x1UL << MCAN_IR_RF1W_Pos) /*!< Bit mask of RF1W field. */ + #define MCAN_IR_RF1W_Min (0x0UL) /*!< Min enumerator value of RF1W field. */ + #define MCAN_IR_RF1W_Max (0x1UL) /*!< Max enumerator value of RF1W field. */ + #define MCAN_IR_RF1W_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF1W_NotGenerated (0x0UL) /*!< Rx FIFO 1 fill level below watermark */ + #define MCAN_IR_RF1W_Generated (0x1UL) /*!< Rx FIFO 1 fill level reached watermark */ + +/* RF1F @Bit 6 : Rx FIFO 1 Full */ + #define MCAN_IR_RF1F_Pos (6UL) /*!< Position of RF1F field. */ + #define MCAN_IR_RF1F_Msk (0x1UL << MCAN_IR_RF1F_Pos) /*!< Bit mask of RF1F field. */ + #define MCAN_IR_RF1F_Min (0x0UL) /*!< Min enumerator value of RF1F field. */ + #define MCAN_IR_RF1F_Max (0x1UL) /*!< Max enumerator value of RF1F field. */ + #define MCAN_IR_RF1F_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF1F_NotGenerated (0x0UL) /*!< Rx FIFO 1 not full */ + #define MCAN_IR_RF1F_Generated (0x1UL) /*!< Rx FIFO 1 full */ + +/* RF1L @Bit 7 : Rx FIFO 1 Message Lost */ + #define MCAN_IR_RF1L_Pos (7UL) /*!< Position of RF1L field. */ + #define MCAN_IR_RF1L_Msk (0x1UL << MCAN_IR_RF1L_Pos) /*!< Bit mask of RF1L field. */ + #define MCAN_IR_RF1L_Min (0x0UL) /*!< Min enumerator value of RF1L field. */ + #define MCAN_IR_RF1L_Max (0x1UL) /*!< Max enumerator value of RF1L field. */ + #define MCAN_IR_RF1L_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_RF1L_NotGenerated (0x0UL) /*!< No Rx FIFO 1 message lost */ + #define MCAN_IR_RF1L_Generated (0x1UL) /*!< Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of + size zero*/ + +/* HPM @Bit 8 : High Priority Message */ + #define MCAN_IR_HPM_Pos (8UL) /*!< Position of HPM field. */ + #define MCAN_IR_HPM_Msk (0x1UL << MCAN_IR_HPM_Pos) /*!< Bit mask of HPM field. */ + #define MCAN_IR_HPM_Min (0x0UL) /*!< Min enumerator value of HPM field. */ + #define MCAN_IR_HPM_Max (0x1UL) /*!< Max enumerator value of HPM field. */ + #define MCAN_IR_HPM_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_HPM_NotGenerated (0x0UL) /*!< No high priority message received */ + #define MCAN_IR_HPM_Generated (0x1UL) /*!< High priority message received */ + +/* TC @Bit 9 : Transmission Completed */ + #define MCAN_IR_TC_Pos (9UL) /*!< Position of TC field. */ + #define MCAN_IR_TC_Msk (0x1UL << MCAN_IR_TC_Pos) /*!< Bit mask of TC field. */ + #define MCAN_IR_TC_Min (0x0UL) /*!< Min enumerator value of TC field. */ + #define MCAN_IR_TC_Max (0x1UL) /*!< Max enumerator value of TC field. */ + #define MCAN_IR_TC_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TC_NotGenerated (0x0UL) /*!< No transmission completed */ + #define MCAN_IR_TC_Generated (0x1UL) /*!< Transmission completed */ + +/* TCF @Bit 10 : Transmission Cancellation Finished */ + #define MCAN_IR_TCF_Pos (10UL) /*!< Position of TCF field. */ + #define MCAN_IR_TCF_Msk (0x1UL << MCAN_IR_TCF_Pos) /*!< Bit mask of TCF field. */ + #define MCAN_IR_TCF_Min (0x0UL) /*!< Min enumerator value of TCF field. */ + #define MCAN_IR_TCF_Max (0x1UL) /*!< Max enumerator value of TCF field. */ + #define MCAN_IR_TCF_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TCF_NotGenerated (0x0UL) /*!< No transmission cancellation finished */ + #define MCAN_IR_TCF_Generated (0x1UL) /*!< Transmission cancellation finished */ + +/* TFE @Bit 11 : Tx FIFO Empty */ + #define MCAN_IR_TFE_Pos (11UL) /*!< Position of TFE field. */ + #define MCAN_IR_TFE_Msk (0x1UL << MCAN_IR_TFE_Pos) /*!< Bit mask of TFE field. */ + #define MCAN_IR_TFE_Min (0x0UL) /*!< Min enumerator value of TFE field. */ + #define MCAN_IR_TFE_Max (0x1UL) /*!< Max enumerator value of TFE field. */ + #define MCAN_IR_TFE_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TFE_NotGenerated (0x0UL) /*!< Tx FIFO non-empty */ + #define MCAN_IR_TFE_Generated (0x1UL) /*!< Tx FIFO empty */ + +/* TEFN @Bit 12 : Tx Event FIFO New Entry */ + #define MCAN_IR_TEFN_Pos (12UL) /*!< Position of TEFN field. */ + #define MCAN_IR_TEFN_Msk (0x1UL << MCAN_IR_TEFN_Pos) /*!< Bit mask of TEFN field. */ + #define MCAN_IR_TEFN_Min (0x0UL) /*!< Min enumerator value of TEFN field. */ + #define MCAN_IR_TEFN_Max (0x1UL) /*!< Max enumerator value of TEFN field. */ + #define MCAN_IR_TEFN_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TEFN_NotGenerated (0x0UL) /*!< Tx Event FIFO unchanged */ + #define MCAN_IR_TEFN_Generated (0x1UL) /*!< Tx Handler wrote Tx Event FIFO element */ + +/* TEFW @Bit 13 : Tx Event FIFO Watermark Reached */ + #define MCAN_IR_TEFW_Pos (13UL) /*!< Position of TEFW field. */ + #define MCAN_IR_TEFW_Msk (0x1UL << MCAN_IR_TEFW_Pos) /*!< Bit mask of TEFW field. */ + #define MCAN_IR_TEFW_Min (0x0UL) /*!< Min enumerator value of TEFW field. */ + #define MCAN_IR_TEFW_Max (0x1UL) /*!< Max enumerator value of TEFW field. */ + #define MCAN_IR_TEFW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TEFW_NotGenerated (0x0UL) /*!< Tx Event FIFO fill level below watermark */ + #define MCAN_IR_TEFW_Generated (0x1UL) /*!< Tx Event FIFO fill level reached watermark */ + +/* TEFF @Bit 14 : Tx Event FIFO Full */ + #define MCAN_IR_TEFF_Pos (14UL) /*!< Position of TEFF field. */ + #define MCAN_IR_TEFF_Msk (0x1UL << MCAN_IR_TEFF_Pos) /*!< Bit mask of TEFF field. */ + #define MCAN_IR_TEFF_Min (0x0UL) /*!< Min enumerator value of TEFF field. */ + #define MCAN_IR_TEFF_Max (0x1UL) /*!< Max enumerator value of TEFF field. */ + #define MCAN_IR_TEFF_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TEFF_NotGenerated (0x0UL) /*!< Tx Event FIFO not full */ + #define MCAN_IR_TEFF_Generated (0x1UL) /*!< Tx Event FIFO full */ + +/* TEFL @Bit 15 : Tx Event FIFO Element Lost */ + #define MCAN_IR_TEFL_Pos (15UL) /*!< Position of TEFL field. */ + #define MCAN_IR_TEFL_Msk (0x1UL << MCAN_IR_TEFL_Pos) /*!< Bit mask of TEFL field. */ + #define MCAN_IR_TEFL_Min (0x0UL) /*!< Min enumerator value of TEFL field. */ + #define MCAN_IR_TEFL_Max (0x1UL) /*!< Max enumerator value of TEFL field. */ + #define MCAN_IR_TEFL_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TEFL_NotGenerated (0x0UL) /*!< No Tx Event FIFO element lost */ + #define MCAN_IR_TEFL_Generated (0x1UL) /*!< Tx Event FIFO element lost, also set after wr ite attempt to Tx Event + FIFO of siz e zero*/ + +/* TSW @Bit 16 : Timestamp Wraparound */ + #define MCAN_IR_TSW_Pos (16UL) /*!< Position of TSW field. */ + #define MCAN_IR_TSW_Msk (0x1UL << MCAN_IR_TSW_Pos) /*!< Bit mask of TSW field. */ + #define MCAN_IR_TSW_Min (0x0UL) /*!< Min enumerator value of TSW field. */ + #define MCAN_IR_TSW_Max (0x1UL) /*!< Max enumerator value of TSW field. */ + #define MCAN_IR_TSW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TSW_NotGenerated (0x0UL) /*!< No timestamp counter wrap-around */ + #define MCAN_IR_TSW_Generated (0x1UL) /*!< Timestamp counter wrapped around */ + +/* MRAF @Bit 17 : Message RAM Access Failure */ + #define MCAN_IR_MRAF_Pos (17UL) /*!< Position of MRAF field. */ + #define MCAN_IR_MRAF_Msk (0x1UL << MCAN_IR_MRAF_Pos) /*!< Bit mask of MRAF field. */ + #define MCAN_IR_MRAF_Min (0x0UL) /*!< Min enumerator value of MRAF field. */ + #define MCAN_IR_MRAF_Max (0x1UL) /*!< Max enumerator value of MRAF field. */ + #define MCAN_IR_MRAF_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_MRAF_NotGenerated (0x0UL) /*!< No Message RAM access failure occurred */ + #define MCAN_IR_MRAF_Generated (0x1UL) /*!< Message RAM access failure occurred */ + +/* TOO @Bit 18 : Timeout Occurred */ + #define MCAN_IR_TOO_Pos (18UL) /*!< Position of TOO field. */ + #define MCAN_IR_TOO_Msk (0x1UL << MCAN_IR_TOO_Pos) /*!< Bit mask of TOO field. */ + #define MCAN_IR_TOO_Min (0x0UL) /*!< Min enumerator value of TOO field. */ + #define MCAN_IR_TOO_Max (0x1UL) /*!< Max enumerator value of TOO field. */ + #define MCAN_IR_TOO_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_TOO_NotGenerated (0x0UL) /*!< No timeout */ + #define MCAN_IR_TOO_Generated (0x1UL) /*!< Timeout reached */ + +/* DRX @Bit 19 : Message stored to Dedicated Rx Buffer */ + #define MCAN_IR_DRX_Pos (19UL) /*!< Position of DRX field. */ + #define MCAN_IR_DRX_Msk (0x1UL << MCAN_IR_DRX_Pos) /*!< Bit mask of DRX field. */ + #define MCAN_IR_DRX_Min (0x0UL) /*!< Min enumerator value of DRX field. */ + #define MCAN_IR_DRX_Max (0x1UL) /*!< Max enumerator value of DRX field. */ + #define MCAN_IR_DRX_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_DRX_NotGenerated (0x0UL) /*!< No Rx Buffer updated */ + #define MCAN_IR_DRX_Generated (0x1UL) /*!< At least one received message stored into an Rx Buff er */ + +/* BEU @Bit 21 : Bus Error Uncorrected */ + #define MCAN_IR_BEU_Pos (21UL) /*!< Position of BEU field. */ + #define MCAN_IR_BEU_Msk (0x1UL << MCAN_IR_BEU_Pos) /*!< Bit mask of BEU field. */ + #define MCAN_IR_BEU_Min (0x0UL) /*!< Min enumerator value of BEU field. */ + #define MCAN_IR_BEU_Max (0x1UL) /*!< Max enumerator value of BEU field. */ + #define MCAN_IR_BEU_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_BEU_NotGenerated (0x0UL) /*!< No read slave error detected when reading from Message RAM */ + #define MCAN_IR_BEU_Generated (0x1UL) /*!< Read slave error detected */ + +/* ELO @Bit 22 : Error Logging Overflow */ + #define MCAN_IR_ELO_Pos (22UL) /*!< Position of ELO field. */ + #define MCAN_IR_ELO_Msk (0x1UL << MCAN_IR_ELO_Pos) /*!< Bit mask of ELO field. */ + #define MCAN_IR_ELO_Min (0x0UL) /*!< Min enumerator value of ELO field. */ + #define MCAN_IR_ELO_Max (0x1UL) /*!< Max enumerator value of ELO field. */ + #define MCAN_IR_ELO_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_ELO_NotGenerated (0x0UL) /*!< CAN Error Logging Counter did not overflow */ + #define MCAN_IR_ELO_Generated (0x1UL) /*!< Overflow of CAN Error Logging Counter occurred */ + +/* EP @Bit 23 : Error Passive */ + #define MCAN_IR_EP_Pos (23UL) /*!< Position of EP field. */ + #define MCAN_IR_EP_Msk (0x1UL << MCAN_IR_EP_Pos) /*!< Bit mask of EP field. */ + #define MCAN_IR_EP_Min (0x0UL) /*!< Min enumerator value of EP field. */ + #define MCAN_IR_EP_Max (0x1UL) /*!< Max enumerator value of EP field. */ + #define MCAN_IR_EP_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_EP_NotGenerated (0x0UL) /*!< Error_Passive status unchanged */ + #define MCAN_IR_EP_Generated (0x1UL) /*!< Error_Passive status changed */ + +/* EW @Bit 24 : Warning Status */ + #define MCAN_IR_EW_Pos (24UL) /*!< Position of EW field. */ + #define MCAN_IR_EW_Msk (0x1UL << MCAN_IR_EW_Pos) /*!< Bit mask of EW field. */ + #define MCAN_IR_EW_Min (0x0UL) /*!< Min enumerator value of EW field. */ + #define MCAN_IR_EW_Max (0x1UL) /*!< Max enumerator value of EW field. */ + #define MCAN_IR_EW_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_EW_NotGenerated (0x0UL) /*!< Error_Warning status unchanged */ + #define MCAN_IR_EW_Generated (0x1UL) /*!< Error_Warning status changed */ + +/* BO @Bit 25 : Bus_Off Status */ + #define MCAN_IR_BO_Pos (25UL) /*!< Position of BO field. */ + #define MCAN_IR_BO_Msk (0x1UL << MCAN_IR_BO_Pos) /*!< Bit mask of BO field. */ + #define MCAN_IR_BO_Min (0x0UL) /*!< Min enumerator value of BO field. */ + #define MCAN_IR_BO_Max (0x1UL) /*!< Max enumerator value of BO field. */ + #define MCAN_IR_BO_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_BO_NotGenerated (0x0UL) /*!< Bus_Off status unchanged */ + #define MCAN_IR_BO_Generated (0x1UL) /*!< Bus_Off status changed */ + +/* WDI @Bit 26 : Watchdog Interrupt */ + #define MCAN_IR_WDI_Pos (26UL) /*!< Position of WDI field. */ + #define MCAN_IR_WDI_Msk (0x1UL << MCAN_IR_WDI_Pos) /*!< Bit mask of WDI field. */ + #define MCAN_IR_WDI_Min (0x0UL) /*!< Min enumerator value of WDI field. */ + #define MCAN_IR_WDI_Max (0x1UL) /*!< Max enumerator value of WDI field. */ + #define MCAN_IR_WDI_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_WDI_NotGenerated (0x0UL) /*!< No Message RAM Watchdog event occurred */ + #define MCAN_IR_WDI_Generated (0x1UL) /*!< Message RAM Watchdog event due to missing READY */ + +/* PEA @Bit 27 : Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ + #define MCAN_IR_PEA_Pos (27UL) /*!< Position of PEA field. */ + #define MCAN_IR_PEA_Msk (0x1UL << MCAN_IR_PEA_Pos) /*!< Bit mask of PEA field. */ + #define MCAN_IR_PEA_Min (0x0UL) /*!< Min enumerator value of PEA field. */ + #define MCAN_IR_PEA_Max (0x1UL) /*!< Max enumerator value of PEA field. */ + #define MCAN_IR_PEA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_PEA_NotGenerated (0x0UL) /*!< No protocol error in arbitration phase */ + #define MCAN_IR_PEA_Generated (0x1UL) /*!< Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) */ + +/* PED @Bit 28 : Protocol Error in Data Phase (Data Bit Time is used) */ + #define MCAN_IR_PED_Pos (28UL) /*!< Position of PED field. */ + #define MCAN_IR_PED_Msk (0x1UL << MCAN_IR_PED_Pos) /*!< Bit mask of PED field. */ + #define MCAN_IR_PED_Min (0x0UL) /*!< Min enumerator value of PED field. */ + #define MCAN_IR_PED_Max (0x1UL) /*!< Max enumerator value of PED field. */ + #define MCAN_IR_PED_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_PED_NotGenerated (0x0UL) /*!< No protocol error in data phase */ + #define MCAN_IR_PED_Generated (0x1UL) /*!< Protocol error in data phase detected (PSR.DLEC ≠ 0,7) */ + +/* ARA @Bit 29 : Access to Reserved Address */ + #define MCAN_IR_ARA_Pos (29UL) /*!< Position of ARA field. */ + #define MCAN_IR_ARA_Msk (0x1UL << MCAN_IR_ARA_Pos) /*!< Bit mask of ARA field. */ + #define MCAN_IR_ARA_Min (0x0UL) /*!< Min enumerator value of ARA field. */ + #define MCAN_IR_ARA_Max (0x1UL) /*!< Max enumerator value of ARA field. */ + #define MCAN_IR_ARA_Clear (0x1UL) /*!< Write '1' to clear interrupt flag */ + #define MCAN_IR_ARA_NotGenerated (0x0UL) /*!< No access to reserved address occurred */ + #define MCAN_IR_ARA_Generated (0x1UL) /*!< Access to reserved address occurred */ + + +/* MCAN_IE: Interrupt Enable */ + #define MCAN_IE_ResetValue (0x00000000UL) /*!< Reset value of IE register. */ + +/* RF0NE @Bit 0 : Rx FIFO 0 New Message Interrupt Enable */ + #define MCAN_IE_RF0NE_Pos (0UL) /*!< Position of RF0NE field. */ + #define MCAN_IE_RF0NE_Msk (0x1UL << MCAN_IE_RF0NE_Pos) /*!< Bit mask of RF0NE field. */ + #define MCAN_IE_RF0NE_Min (0x0UL) /*!< Min enumerator value of RF0NE field. */ + #define MCAN_IE_RF0NE_Max (0x1UL) /*!< Max enumerator value of RF0NE field. */ + #define MCAN_IE_RF0NE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF0NE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF0WE @Bit 1 : Rx FIFO 0 Watermark Reached Interrupt Enable */ + #define MCAN_IE_RF0WE_Pos (1UL) /*!< Position of RF0WE field. */ + #define MCAN_IE_RF0WE_Msk (0x1UL << MCAN_IE_RF0WE_Pos) /*!< Bit mask of RF0WE field. */ + #define MCAN_IE_RF0WE_Min (0x0UL) /*!< Min enumerator value of RF0WE field. */ + #define MCAN_IE_RF0WE_Max (0x1UL) /*!< Max enumerator value of RF0WE field. */ + #define MCAN_IE_RF0WE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF0WE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF0FE @Bit 2 : Rx FIFO 0 Full Interrupt Enable */ + #define MCAN_IE_RF0FE_Pos (2UL) /*!< Position of RF0FE field. */ + #define MCAN_IE_RF0FE_Msk (0x1UL << MCAN_IE_RF0FE_Pos) /*!< Bit mask of RF0FE field. */ + #define MCAN_IE_RF0FE_Min (0x0UL) /*!< Min enumerator value of RF0FE field. */ + #define MCAN_IE_RF0FE_Max (0x1UL) /*!< Max enumerator value of RF0FE field. */ + #define MCAN_IE_RF0FE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF0FE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF0LE @Bit 3 : Rx FIFO 0 Message Lost Interrupt Enable */ + #define MCAN_IE_RF0LE_Pos (3UL) /*!< Position of RF0LE field. */ + #define MCAN_IE_RF0LE_Msk (0x1UL << MCAN_IE_RF0LE_Pos) /*!< Bit mask of RF0LE field. */ + #define MCAN_IE_RF0LE_Min (0x0UL) /*!< Min enumerator value of RF0LE field. */ + #define MCAN_IE_RF0LE_Max (0x1UL) /*!< Max enumerator value of RF0LE field. */ + #define MCAN_IE_RF0LE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF0LE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF1NE @Bit 4 : Rx FIFO 1 New Message Interrupt Enable */ + #define MCAN_IE_RF1NE_Pos (4UL) /*!< Position of RF1NE field. */ + #define MCAN_IE_RF1NE_Msk (0x1UL << MCAN_IE_RF1NE_Pos) /*!< Bit mask of RF1NE field. */ + #define MCAN_IE_RF1NE_Min (0x0UL) /*!< Min enumerator value of RF1NE field. */ + #define MCAN_IE_RF1NE_Max (0x1UL) /*!< Max enumerator value of RF1NE field. */ + #define MCAN_IE_RF1NE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF1NE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF1WE @Bit 5 : Rx FIFO 1 Watermark Reached Interrupt Enable */ + #define MCAN_IE_RF1WE_Pos (5UL) /*!< Position of RF1WE field. */ + #define MCAN_IE_RF1WE_Msk (0x1UL << MCAN_IE_RF1WE_Pos) /*!< Bit mask of RF1WE field. */ + #define MCAN_IE_RF1WE_Min (0x0UL) /*!< Min enumerator value of RF1WE field. */ + #define MCAN_IE_RF1WE_Max (0x1UL) /*!< Max enumerator value of RF1WE field. */ + #define MCAN_IE_RF1WE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF1WE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF1FE @Bit 6 : Rx FIFO 1 Full Interrupt Enable */ + #define MCAN_IE_RF1FE_Pos (6UL) /*!< Position of RF1FE field. */ + #define MCAN_IE_RF1FE_Msk (0x1UL << MCAN_IE_RF1FE_Pos) /*!< Bit mask of RF1FE field. */ + #define MCAN_IE_RF1FE_Min (0x0UL) /*!< Min enumerator value of RF1FE field. */ + #define MCAN_IE_RF1FE_Max (0x1UL) /*!< Max enumerator value of RF1FE field. */ + #define MCAN_IE_RF1FE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF1FE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* RF1LE @Bit 7 : Rx FIFO 1 Message Lost Interrupt Enable */ + #define MCAN_IE_RF1LE_Pos (7UL) /*!< Position of RF1LE field. */ + #define MCAN_IE_RF1LE_Msk (0x1UL << MCAN_IE_RF1LE_Pos) /*!< Bit mask of RF1LE field. */ + #define MCAN_IE_RF1LE_Min (0x0UL) /*!< Min enumerator value of RF1LE field. */ + #define MCAN_IE_RF1LE_Max (0x1UL) /*!< Max enumerator value of RF1LE field. */ + #define MCAN_IE_RF1LE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_RF1LE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* HPME @Bit 8 : High Priority Message Interrupt Enable */ + #define MCAN_IE_HPME_Pos (8UL) /*!< Position of HPME field. */ + #define MCAN_IE_HPME_Msk (0x1UL << MCAN_IE_HPME_Pos) /*!< Bit mask of HPME field. */ + #define MCAN_IE_HPME_Min (0x0UL) /*!< Min enumerator value of HPME field. */ + #define MCAN_IE_HPME_Max (0x1UL) /*!< Max enumerator value of HPME field. */ + #define MCAN_IE_HPME_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_HPME_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TCE @Bit 9 : Transmission Completed Interrupt Enable */ + #define MCAN_IE_TCE_Pos (9UL) /*!< Position of TCE field. */ + #define MCAN_IE_TCE_Msk (0x1UL << MCAN_IE_TCE_Pos) /*!< Bit mask of TCE field. */ + #define MCAN_IE_TCE_Min (0x0UL) /*!< Min enumerator value of TCE field. */ + #define MCAN_IE_TCE_Max (0x1UL) /*!< Max enumerator value of TCE field. */ + #define MCAN_IE_TCE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TCE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TCFE @Bit 10 : Transmission Cancellation Finished Interrupt Enable */ + #define MCAN_IE_TCFE_Pos (10UL) /*!< Position of TCFE field. */ + #define MCAN_IE_TCFE_Msk (0x1UL << MCAN_IE_TCFE_Pos) /*!< Bit mask of TCFE field. */ + #define MCAN_IE_TCFE_Min (0x0UL) /*!< Min enumerator value of TCFE field. */ + #define MCAN_IE_TCFE_Max (0x1UL) /*!< Max enumerator value of TCFE field. */ + #define MCAN_IE_TCFE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TCFE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TFEE @Bit 11 : Tx FIFO Empty Interrupt Enable */ + #define MCAN_IE_TFEE_Pos (11UL) /*!< Position of TFEE field. */ + #define MCAN_IE_TFEE_Msk (0x1UL << MCAN_IE_TFEE_Pos) /*!< Bit mask of TFEE field. */ + #define MCAN_IE_TFEE_Min (0x0UL) /*!< Min enumerator value of TFEE field. */ + #define MCAN_IE_TFEE_Max (0x1UL) /*!< Max enumerator value of TFEE field. */ + #define MCAN_IE_TFEE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TFEE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TEFNE @Bit 12 : Tx Event FIFO New Entry Interrupt Enable */ + #define MCAN_IE_TEFNE_Pos (12UL) /*!< Position of TEFNE field. */ + #define MCAN_IE_TEFNE_Msk (0x1UL << MCAN_IE_TEFNE_Pos) /*!< Bit mask of TEFNE field. */ + #define MCAN_IE_TEFNE_Min (0x0UL) /*!< Min enumerator value of TEFNE field. */ + #define MCAN_IE_TEFNE_Max (0x1UL) /*!< Max enumerator value of TEFNE field. */ + #define MCAN_IE_TEFNE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TEFNE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TEFWE @Bit 13 : Tx Event FIFO Watermark Reached Interrupt Enable */ + #define MCAN_IE_TEFWE_Pos (13UL) /*!< Position of TEFWE field. */ + #define MCAN_IE_TEFWE_Msk (0x1UL << MCAN_IE_TEFWE_Pos) /*!< Bit mask of TEFWE field. */ + #define MCAN_IE_TEFWE_Min (0x0UL) /*!< Min enumerator value of TEFWE field. */ + #define MCAN_IE_TEFWE_Max (0x1UL) /*!< Max enumerator value of TEFWE field. */ + #define MCAN_IE_TEFWE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TEFWE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TEFFE @Bit 14 : Tx Event FIFO Full Interrupt Enable */ + #define MCAN_IE_TEFFE_Pos (14UL) /*!< Position of TEFFE field. */ + #define MCAN_IE_TEFFE_Msk (0x1UL << MCAN_IE_TEFFE_Pos) /*!< Bit mask of TEFFE field. */ + #define MCAN_IE_TEFFE_Min (0x0UL) /*!< Min enumerator value of TEFFE field. */ + #define MCAN_IE_TEFFE_Max (0x1UL) /*!< Max enumerator value of TEFFE field. */ + #define MCAN_IE_TEFFE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TEFFE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TEFLE @Bit 15 : Tx Event FIFO Event Lost Interrupt Enable */ + #define MCAN_IE_TEFLE_Pos (15UL) /*!< Position of TEFLE field. */ + #define MCAN_IE_TEFLE_Msk (0x1UL << MCAN_IE_TEFLE_Pos) /*!< Bit mask of TEFLE field. */ + #define MCAN_IE_TEFLE_Min (0x0UL) /*!< Min enumerator value of TEFLE field. */ + #define MCAN_IE_TEFLE_Max (0x1UL) /*!< Max enumerator value of TEFLE field. */ + #define MCAN_IE_TEFLE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TEFLE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TSWE @Bit 16 : Timestamp Wraparound Interrupt Enable */ + #define MCAN_IE_TSWE_Pos (16UL) /*!< Position of TSWE field. */ + #define MCAN_IE_TSWE_Msk (0x1UL << MCAN_IE_TSWE_Pos) /*!< Bit mask of TSWE field. */ + #define MCAN_IE_TSWE_Min (0x0UL) /*!< Min enumerator value of TSWE field. */ + #define MCAN_IE_TSWE_Max (0x1UL) /*!< Max enumerator value of TSWE field. */ + #define MCAN_IE_TSWE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TSWE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* MRAFE @Bit 17 : Message RAM Access Failure Interrupt Enable */ + #define MCAN_IE_MRAFE_Pos (17UL) /*!< Position of MRAFE field. */ + #define MCAN_IE_MRAFE_Msk (0x1UL << MCAN_IE_MRAFE_Pos) /*!< Bit mask of MRAFE field. */ + #define MCAN_IE_MRAFE_Min (0x0UL) /*!< Min enumerator value of MRAFE field. */ + #define MCAN_IE_MRAFE_Max (0x1UL) /*!< Max enumerator value of MRAFE field. */ + #define MCAN_IE_MRAFE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_MRAFE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* TOOE @Bit 18 : Timeout Occurred Interrupt Enable */ + #define MCAN_IE_TOOE_Pos (18UL) /*!< Position of TOOE field. */ + #define MCAN_IE_TOOE_Msk (0x1UL << MCAN_IE_TOOE_Pos) /*!< Bit mask of TOOE field. */ + #define MCAN_IE_TOOE_Min (0x0UL) /*!< Min enumerator value of TOOE field. */ + #define MCAN_IE_TOOE_Max (0x1UL) /*!< Max enumerator value of TOOE field. */ + #define MCAN_IE_TOOE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_TOOE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* DRXE @Bit 19 : Message stored to Dedicated Rx Buffer Interrupt Enable */ + #define MCAN_IE_DRXE_Pos (19UL) /*!< Position of DRXE field. */ + #define MCAN_IE_DRXE_Msk (0x1UL << MCAN_IE_DRXE_Pos) /*!< Bit mask of DRXE field. */ + #define MCAN_IE_DRXE_Min (0x0UL) /*!< Min enumerator value of DRXE field. */ + #define MCAN_IE_DRXE_Max (0x1UL) /*!< Max enumerator value of DRXE field. */ + #define MCAN_IE_DRXE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_DRXE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* BEUE @Bit 21 : Bus Error Uncorrected Interrupt Enable */ + #define MCAN_IE_BEUE_Pos (21UL) /*!< Position of BEUE field. */ + #define MCAN_IE_BEUE_Msk (0x1UL << MCAN_IE_BEUE_Pos) /*!< Bit mask of BEUE field. */ + #define MCAN_IE_BEUE_Min (0x0UL) /*!< Min enumerator value of BEUE field. */ + #define MCAN_IE_BEUE_Max (0x1UL) /*!< Max enumerator value of BEUE field. */ + #define MCAN_IE_BEUE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_BEUE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* ELOE @Bit 22 : Error Logging Overflow Interrupt Enable */ + #define MCAN_IE_ELOE_Pos (22UL) /*!< Position of ELOE field. */ + #define MCAN_IE_ELOE_Msk (0x1UL << MCAN_IE_ELOE_Pos) /*!< Bit mask of ELOE field. */ + #define MCAN_IE_ELOE_Min (0x0UL) /*!< Min enumerator value of ELOE field. */ + #define MCAN_IE_ELOE_Max (0x1UL) /*!< Max enumerator value of ELOE field. */ + #define MCAN_IE_ELOE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_ELOE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* EPE @Bit 23 : Error Passive Interrupt Enable */ + #define MCAN_IE_EPE_Pos (23UL) /*!< Position of EPE field. */ + #define MCAN_IE_EPE_Msk (0x1UL << MCAN_IE_EPE_Pos) /*!< Bit mask of EPE field. */ + #define MCAN_IE_EPE_Min (0x0UL) /*!< Min enumerator value of EPE field. */ + #define MCAN_IE_EPE_Max (0x1UL) /*!< Max enumerator value of EPE field. */ + #define MCAN_IE_EPE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_EPE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* EWE @Bit 24 : Warning Status Interrupt Enable */ + #define MCAN_IE_EWE_Pos (24UL) /*!< Position of EWE field. */ + #define MCAN_IE_EWE_Msk (0x1UL << MCAN_IE_EWE_Pos) /*!< Bit mask of EWE field. */ + #define MCAN_IE_EWE_Min (0x0UL) /*!< Min enumerator value of EWE field. */ + #define MCAN_IE_EWE_Max (0x1UL) /*!< Max enumerator value of EWE field. */ + #define MCAN_IE_EWE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_EWE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* BOE @Bit 25 : Bus_Off Status Interrupt Enable */ + #define MCAN_IE_BOE_Pos (25UL) /*!< Position of BOE field. */ + #define MCAN_IE_BOE_Msk (0x1UL << MCAN_IE_BOE_Pos) /*!< Bit mask of BOE field. */ + #define MCAN_IE_BOE_Min (0x0UL) /*!< Min enumerator value of BOE field. */ + #define MCAN_IE_BOE_Max (0x1UL) /*!< Max enumerator value of BOE field. */ + #define MCAN_IE_BOE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_BOE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* WDIE @Bit 26 : Watchdog Interrupt Enable */ + #define MCAN_IE_WDIE_Pos (26UL) /*!< Position of WDIE field. */ + #define MCAN_IE_WDIE_Msk (0x1UL << MCAN_IE_WDIE_Pos) /*!< Bit mask of WDIE field. */ + #define MCAN_IE_WDIE_Min (0x0UL) /*!< Min enumerator value of WDIE field. */ + #define MCAN_IE_WDIE_Max (0x1UL) /*!< Max enumerator value of WDIE field. */ + #define MCAN_IE_WDIE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_WDIE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* PEAE @Bit 27 : Protocol Error in Arbitration Phase Enable */ + #define MCAN_IE_PEAE_Pos (27UL) /*!< Position of PEAE field. */ + #define MCAN_IE_PEAE_Msk (0x1UL << MCAN_IE_PEAE_Pos) /*!< Bit mask of PEAE field. */ + #define MCAN_IE_PEAE_Min (0x0UL) /*!< Min enumerator value of PEAE field. */ + #define MCAN_IE_PEAE_Max (0x1UL) /*!< Max enumerator value of PEAE field. */ + #define MCAN_IE_PEAE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_PEAE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* PEDE @Bit 28 : Protocol Error in Data Phase Enable */ + #define MCAN_IE_PEDE_Pos (28UL) /*!< Position of PEDE field. */ + #define MCAN_IE_PEDE_Msk (0x1UL << MCAN_IE_PEDE_Pos) /*!< Bit mask of PEDE field. */ + #define MCAN_IE_PEDE_Min (0x0UL) /*!< Min enumerator value of PEDE field. */ + #define MCAN_IE_PEDE_Max (0x1UL) /*!< Max enumerator value of PEDE field. */ + #define MCAN_IE_PEDE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_PEDE_Enable (0x1UL) /*!< Interrupt enabled. */ + +/* ARAE @Bit 29 : Access to Reserved Address Enable */ + #define MCAN_IE_ARAE_Pos (29UL) /*!< Position of ARAE field. */ + #define MCAN_IE_ARAE_Msk (0x1UL << MCAN_IE_ARAE_Pos) /*!< Bit mask of ARAE field. */ + #define MCAN_IE_ARAE_Min (0x0UL) /*!< Min enumerator value of ARAE field. */ + #define MCAN_IE_ARAE_Max (0x1UL) /*!< Max enumerator value of ARAE field. */ + #define MCAN_IE_ARAE_Disable (0x0UL) /*!< Interrupt disabled. */ + #define MCAN_IE_ARAE_Enable (0x1UL) /*!< Interrupt enabled. */ + + +/* MCAN_ILS: Interrupt Line Select */ + #define MCAN_ILS_ResetValue (0x00000000UL) /*!< Reset value of ILS register. */ + +/* RF0NL @Bit 0 : Rx FIFO 0 New Message Interrupt Line */ + #define MCAN_ILS_RF0NL_Pos (0UL) /*!< Position of RF0NL field. */ + #define MCAN_ILS_RF0NL_Msk (0x1UL << MCAN_ILS_RF0NL_Pos) /*!< Bit mask of RF0NL field. */ + #define MCAN_ILS_RF0NL_Min (0x0UL) /*!< Min enumerator value of RF0NL field. */ + #define MCAN_ILS_RF0NL_Max (0x1UL) /*!< Max enumerator value of RF0NL field. */ + #define MCAN_ILS_RF0NL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF0NL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF0WL @Bit 1 : Rx FIFO 0 Watermark Reached Interrupt Line */ + #define MCAN_ILS_RF0WL_Pos (1UL) /*!< Position of RF0WL field. */ + #define MCAN_ILS_RF0WL_Msk (0x1UL << MCAN_ILS_RF0WL_Pos) /*!< Bit mask of RF0WL field. */ + #define MCAN_ILS_RF0WL_Min (0x0UL) /*!< Min enumerator value of RF0WL field. */ + #define MCAN_ILS_RF0WL_Max (0x1UL) /*!< Max enumerator value of RF0WL field. */ + #define MCAN_ILS_RF0WL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF0WL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF0FL @Bit 2 : Rx FIFO 0 Full Interrupt Line */ + #define MCAN_ILS_RF0FL_Pos (2UL) /*!< Position of RF0FL field. */ + #define MCAN_ILS_RF0FL_Msk (0x1UL << MCAN_ILS_RF0FL_Pos) /*!< Bit mask of RF0FL field. */ + #define MCAN_ILS_RF0FL_Min (0x0UL) /*!< Min enumerator value of RF0FL field. */ + #define MCAN_ILS_RF0FL_Max (0x1UL) /*!< Max enumerator value of RF0FL field. */ + #define MCAN_ILS_RF0FL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF0FL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF0LL @Bit 3 : Rx FIFO 0 Message Lost Interrupt Line */ + #define MCAN_ILS_RF0LL_Pos (3UL) /*!< Position of RF0LL field. */ + #define MCAN_ILS_RF0LL_Msk (0x1UL << MCAN_ILS_RF0LL_Pos) /*!< Bit mask of RF0LL field. */ + #define MCAN_ILS_RF0LL_Min (0x0UL) /*!< Min enumerator value of RF0LL field. */ + #define MCAN_ILS_RF0LL_Max (0x1UL) /*!< Max enumerator value of RF0LL field. */ + #define MCAN_ILS_RF0LL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF0LL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF1NL @Bit 4 : Rx FIFO 1 New Message Interrupt Line */ + #define MCAN_ILS_RF1NL_Pos (4UL) /*!< Position of RF1NL field. */ + #define MCAN_ILS_RF1NL_Msk (0x1UL << MCAN_ILS_RF1NL_Pos) /*!< Bit mask of RF1NL field. */ + #define MCAN_ILS_RF1NL_Min (0x0UL) /*!< Min enumerator value of RF1NL field. */ + #define MCAN_ILS_RF1NL_Max (0x1UL) /*!< Max enumerator value of RF1NL field. */ + #define MCAN_ILS_RF1NL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF1NL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF1WL @Bit 5 : Rx FIFO 1 Watermark Reached Interrupt Line */ + #define MCAN_ILS_RF1WL_Pos (5UL) /*!< Position of RF1WL field. */ + #define MCAN_ILS_RF1WL_Msk (0x1UL << MCAN_ILS_RF1WL_Pos) /*!< Bit mask of RF1WL field. */ + #define MCAN_ILS_RF1WL_Min (0x0UL) /*!< Min enumerator value of RF1WL field. */ + #define MCAN_ILS_RF1WL_Max (0x1UL) /*!< Max enumerator value of RF1WL field. */ + #define MCAN_ILS_RF1WL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF1WL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF1FL @Bit 6 : Rx FIFO 1 Full Interrupt Line */ + #define MCAN_ILS_RF1FL_Pos (6UL) /*!< Position of RF1FL field. */ + #define MCAN_ILS_RF1FL_Msk (0x1UL << MCAN_ILS_RF1FL_Pos) /*!< Bit mask of RF1FL field. */ + #define MCAN_ILS_RF1FL_Min (0x0UL) /*!< Min enumerator value of RF1FL field. */ + #define MCAN_ILS_RF1FL_Max (0x1UL) /*!< Max enumerator value of RF1FL field. */ + #define MCAN_ILS_RF1FL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF1FL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* RF1LL @Bit 7 : Rx FIFO 1 Message Lost Interrupt Line */ + #define MCAN_ILS_RF1LL_Pos (7UL) /*!< Position of RF1LL field. */ + #define MCAN_ILS_RF1LL_Msk (0x1UL << MCAN_ILS_RF1LL_Pos) /*!< Bit mask of RF1LL field. */ + #define MCAN_ILS_RF1LL_Min (0x0UL) /*!< Min enumerator value of RF1LL field. */ + #define MCAN_ILS_RF1LL_Max (0x1UL) /*!< Max enumerator value of RF1LL field. */ + #define MCAN_ILS_RF1LL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_RF1LL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* HPML @Bit 8 : High Priority Message Interrupt Line */ + #define MCAN_ILS_HPML_Pos (8UL) /*!< Position of HPML field. */ + #define MCAN_ILS_HPML_Msk (0x1UL << MCAN_ILS_HPML_Pos) /*!< Bit mask of HPML field. */ + #define MCAN_ILS_HPML_Min (0x0UL) /*!< Min enumerator value of HPML field. */ + #define MCAN_ILS_HPML_Max (0x1UL) /*!< Max enumerator value of HPML field. */ + #define MCAN_ILS_HPML_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_HPML_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TCL @Bit 9 : Transmission Completed Interrupt Line */ + #define MCAN_ILS_TCL_Pos (9UL) /*!< Position of TCL field. */ + #define MCAN_ILS_TCL_Msk (0x1UL << MCAN_ILS_TCL_Pos) /*!< Bit mask of TCL field. */ + #define MCAN_ILS_TCL_Min (0x0UL) /*!< Min enumerator value of TCL field. */ + #define MCAN_ILS_TCL_Max (0x1UL) /*!< Max enumerator value of TCL field. */ + #define MCAN_ILS_TCL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TCL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TCFL @Bit 10 : Transmission Cancellation Finished Interrupt Line */ + #define MCAN_ILS_TCFL_Pos (10UL) /*!< Position of TCFL field. */ + #define MCAN_ILS_TCFL_Msk (0x1UL << MCAN_ILS_TCFL_Pos) /*!< Bit mask of TCFL field. */ + #define MCAN_ILS_TCFL_Min (0x0UL) /*!< Min enumerator value of TCFL field. */ + #define MCAN_ILS_TCFL_Max (0x1UL) /*!< Max enumerator value of TCFL field. */ + #define MCAN_ILS_TCFL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TCFL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TFEL @Bit 11 : Tx FIFO Empty Interrupt Line */ + #define MCAN_ILS_TFEL_Pos (11UL) /*!< Position of TFEL field. */ + #define MCAN_ILS_TFEL_Msk (0x1UL << MCAN_ILS_TFEL_Pos) /*!< Bit mask of TFEL field. */ + #define MCAN_ILS_TFEL_Min (0x0UL) /*!< Min enumerator value of TFEL field. */ + #define MCAN_ILS_TFEL_Max (0x1UL) /*!< Max enumerator value of TFEL field. */ + #define MCAN_ILS_TFEL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TFEL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TEFNL @Bit 12 : Tx Event FIFO New Entry Interrupt Line */ + #define MCAN_ILS_TEFNL_Pos (12UL) /*!< Position of TEFNL field. */ + #define MCAN_ILS_TEFNL_Msk (0x1UL << MCAN_ILS_TEFNL_Pos) /*!< Bit mask of TEFNL field. */ + #define MCAN_ILS_TEFNL_Min (0x0UL) /*!< Min enumerator value of TEFNL field. */ + #define MCAN_ILS_TEFNL_Max (0x1UL) /*!< Max enumerator value of TEFNL field. */ + #define MCAN_ILS_TEFNL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TEFNL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TEFWL @Bit 13 : Tx Event FIFO Watermark Reached Interrupt Line */ + #define MCAN_ILS_TEFWL_Pos (13UL) /*!< Position of TEFWL field. */ + #define MCAN_ILS_TEFWL_Msk (0x1UL << MCAN_ILS_TEFWL_Pos) /*!< Bit mask of TEFWL field. */ + #define MCAN_ILS_TEFWL_Min (0x0UL) /*!< Min enumerator value of TEFWL field. */ + #define MCAN_ILS_TEFWL_Max (0x1UL) /*!< Max enumerator value of TEFWL field. */ + #define MCAN_ILS_TEFWL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TEFWL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TEFFL @Bit 14 : Tx Event FIFO Full Interrupt Line */ + #define MCAN_ILS_TEFFL_Pos (14UL) /*!< Position of TEFFL field. */ + #define MCAN_ILS_TEFFL_Msk (0x1UL << MCAN_ILS_TEFFL_Pos) /*!< Bit mask of TEFFL field. */ + #define MCAN_ILS_TEFFL_Min (0x0UL) /*!< Min enumerator value of TEFFL field. */ + #define MCAN_ILS_TEFFL_Max (0x1UL) /*!< Max enumerator value of TEFFL field. */ + #define MCAN_ILS_TEFFL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TEFFL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TEFLL @Bit 15 : Tx Event FIFO Event Lost Interrupt Line */ + #define MCAN_ILS_TEFLL_Pos (15UL) /*!< Position of TEFLL field. */ + #define MCAN_ILS_TEFLL_Msk (0x1UL << MCAN_ILS_TEFLL_Pos) /*!< Bit mask of TEFLL field. */ + #define MCAN_ILS_TEFLL_Min (0x0UL) /*!< Min enumerator value of TEFLL field. */ + #define MCAN_ILS_TEFLL_Max (0x1UL) /*!< Max enumerator value of TEFLL field. */ + #define MCAN_ILS_TEFLL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TEFLL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TSWL @Bit 16 : Timestamp Wraparound Interrupt Line */ + #define MCAN_ILS_TSWL_Pos (16UL) /*!< Position of TSWL field. */ + #define MCAN_ILS_TSWL_Msk (0x1UL << MCAN_ILS_TSWL_Pos) /*!< Bit mask of TSWL field. */ + #define MCAN_ILS_TSWL_Min (0x0UL) /*!< Min enumerator value of TSWL field. */ + #define MCAN_ILS_TSWL_Max (0x1UL) /*!< Max enumerator value of TSWL field. */ + #define MCAN_ILS_TSWL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TSWL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* MRAFL @Bit 17 : Message RAM Access Failure Interrupt Line */ + #define MCAN_ILS_MRAFL_Pos (17UL) /*!< Position of MRAFL field. */ + #define MCAN_ILS_MRAFL_Msk (0x1UL << MCAN_ILS_MRAFL_Pos) /*!< Bit mask of MRAFL field. */ + #define MCAN_ILS_MRAFL_Min (0x0UL) /*!< Min enumerator value of MRAFL field. */ + #define MCAN_ILS_MRAFL_Max (0x1UL) /*!< Max enumerator value of MRAFL field. */ + #define MCAN_ILS_MRAFL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_MRAFL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* TOOL @Bit 18 : Timeout Occurred Interrupt Line */ + #define MCAN_ILS_TOOL_Pos (18UL) /*!< Position of TOOL field. */ + #define MCAN_ILS_TOOL_Msk (0x1UL << MCAN_ILS_TOOL_Pos) /*!< Bit mask of TOOL field. */ + #define MCAN_ILS_TOOL_Min (0x0UL) /*!< Min enumerator value of TOOL field. */ + #define MCAN_ILS_TOOL_Max (0x1UL) /*!< Max enumerator value of TOOL field. */ + #define MCAN_ILS_TOOL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_TOOL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* DRXL @Bit 19 : Message stored to Dedicated Rx Buffer Interrupt Line */ + #define MCAN_ILS_DRXL_Pos (19UL) /*!< Position of DRXL field. */ + #define MCAN_ILS_DRXL_Msk (0x1UL << MCAN_ILS_DRXL_Pos) /*!< Bit mask of DRXL field. */ + #define MCAN_ILS_DRXL_Min (0x0UL) /*!< Min enumerator value of DRXL field. */ + #define MCAN_ILS_DRXL_Max (0x1UL) /*!< Max enumerator value of DRXL field. */ + #define MCAN_ILS_DRXL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_DRXL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* BEUL @Bit 21 : Bus Error Uncorrected Interrupt Line */ + #define MCAN_ILS_BEUL_Pos (21UL) /*!< Position of BEUL field. */ + #define MCAN_ILS_BEUL_Msk (0x1UL << MCAN_ILS_BEUL_Pos) /*!< Bit mask of BEUL field. */ + #define MCAN_ILS_BEUL_Min (0x0UL) /*!< Min enumerator value of BEUL field. */ + #define MCAN_ILS_BEUL_Max (0x1UL) /*!< Max enumerator value of BEUL field. */ + #define MCAN_ILS_BEUL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_BEUL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* ELOL @Bit 22 : Error Logging Overflow Interrupt Line */ + #define MCAN_ILS_ELOL_Pos (22UL) /*!< Position of ELOL field. */ + #define MCAN_ILS_ELOL_Msk (0x1UL << MCAN_ILS_ELOL_Pos) /*!< Bit mask of ELOL field. */ + #define MCAN_ILS_ELOL_Min (0x0UL) /*!< Min enumerator value of ELOL field. */ + #define MCAN_ILS_ELOL_Max (0x1UL) /*!< Max enumerator value of ELOL field. */ + #define MCAN_ILS_ELOL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_ELOL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* EPL @Bit 23 : Error Passive Interrupt Line */ + #define MCAN_ILS_EPL_Pos (23UL) /*!< Position of EPL field. */ + #define MCAN_ILS_EPL_Msk (0x1UL << MCAN_ILS_EPL_Pos) /*!< Bit mask of EPL field. */ + #define MCAN_ILS_EPL_Min (0x0UL) /*!< Min enumerator value of EPL field. */ + #define MCAN_ILS_EPL_Max (0x1UL) /*!< Max enumerator value of EPL field. */ + #define MCAN_ILS_EPL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_EPL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* EWL @Bit 24 : Warning Status Interrupt Line */ + #define MCAN_ILS_EWL_Pos (24UL) /*!< Position of EWL field. */ + #define MCAN_ILS_EWL_Msk (0x1UL << MCAN_ILS_EWL_Pos) /*!< Bit mask of EWL field. */ + #define MCAN_ILS_EWL_Min (0x0UL) /*!< Min enumerator value of EWL field. */ + #define MCAN_ILS_EWL_Max (0x1UL) /*!< Max enumerator value of EWL field. */ + #define MCAN_ILS_EWL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_EWL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* BOL @Bit 25 : Bus_Off Status Interrupt Line */ + #define MCAN_ILS_BOL_Pos (25UL) /*!< Position of BOL field. */ + #define MCAN_ILS_BOL_Msk (0x1UL << MCAN_ILS_BOL_Pos) /*!< Bit mask of BOL field. */ + #define MCAN_ILS_BOL_Min (0x0UL) /*!< Min enumerator value of BOL field. */ + #define MCAN_ILS_BOL_Max (0x1UL) /*!< Max enumerator value of BOL field. */ + #define MCAN_ILS_BOL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_BOL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* WDIL @Bit 26 : Watchdog Interrupt Line */ + #define MCAN_ILS_WDIL_Pos (26UL) /*!< Position of WDIL field. */ + #define MCAN_ILS_WDIL_Msk (0x1UL << MCAN_ILS_WDIL_Pos) /*!< Bit mask of WDIL field. */ + #define MCAN_ILS_WDIL_Min (0x0UL) /*!< Min enumerator value of WDIL field. */ + #define MCAN_ILS_WDIL_Max (0x1UL) /*!< Max enumerator value of WDIL field. */ + #define MCAN_ILS_WDIL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_WDIL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* PEAL @Bit 27 : Protocol Error in Arbitration Phase Line */ + #define MCAN_ILS_PEAL_Pos (27UL) /*!< Position of PEAL field. */ + #define MCAN_ILS_PEAL_Msk (0x1UL << MCAN_ILS_PEAL_Pos) /*!< Bit mask of PEAL field. */ + #define MCAN_ILS_PEAL_Min (0x0UL) /*!< Min enumerator value of PEAL field. */ + #define MCAN_ILS_PEAL_Max (0x1UL) /*!< Max enumerator value of PEAL field. */ + #define MCAN_ILS_PEAL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_PEAL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* PEDL @Bit 28 : Protocol Error in Data Phase Line */ + #define MCAN_ILS_PEDL_Pos (28UL) /*!< Position of PEDL field. */ + #define MCAN_ILS_PEDL_Msk (0x1UL << MCAN_ILS_PEDL_Pos) /*!< Bit mask of PEDL field. */ + #define MCAN_ILS_PEDL_Min (0x0UL) /*!< Min enumerator value of PEDL field. */ + #define MCAN_ILS_PEDL_Max (0x1UL) /*!< Max enumerator value of PEDL field. */ + #define MCAN_ILS_PEDL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_PEDL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + +/* ARAL @Bit 29 : Access to Reserved Address Line */ + #define MCAN_ILS_ARAL_Pos (29UL) /*!< Position of ARAL field. */ + #define MCAN_ILS_ARAL_Msk (0x1UL << MCAN_ILS_ARAL_Pos) /*!< Bit mask of ARAL field. */ + #define MCAN_ILS_ARAL_Min (0x0UL) /*!< Min enumerator value of ARAL field. */ + #define MCAN_ILS_ARAL_Max (0x1UL) /*!< Max enumerator value of ARAL field. */ + #define MCAN_ILS_ARAL_Assigned0 (0x0UL) /*!< Interrupt assigned to interrupt line CORE0. */ + #define MCAN_ILS_ARAL_Assigned1 (0x1UL) /*!< Interrupt assigned to interrupt line CORE1. */ + + +/* MCAN_ILE: Interrupt Line Enable */ + #define MCAN_ILE_ResetValue (0x00000000UL) /*!< Reset value of ILE register. */ + +/* EINT0 @Bit 0 : Enable Interrupt Line 0 */ + #define MCAN_ILE_EINT0_Pos (0UL) /*!< Position of EINT0 field. */ + #define MCAN_ILE_EINT0_Msk (0x1UL << MCAN_ILE_EINT0_Pos) /*!< Bit mask of EINT0 field. */ + #define MCAN_ILE_EINT0_Min (0x0UL) /*!< Min enumerator value of EINT0 field. */ + #define MCAN_ILE_EINT0_Max (0x1UL) /*!< Max enumerator value of EINT0 field. */ + #define MCAN_ILE_EINT0_Disable (0x0UL) /*!< Interrupt line CORE0 disabled. */ + #define MCAN_ILE_EINT0_Enable (0x1UL) /*!< Interrupt line CORE0 enabled. */ + +/* EINT1 @Bit 1 : Enable Interrupt Line 1 */ + #define MCAN_ILE_EINT1_Pos (1UL) /*!< Position of EINT1 field. */ + #define MCAN_ILE_EINT1_Msk (0x1UL << MCAN_ILE_EINT1_Pos) /*!< Bit mask of EINT1 field. */ + #define MCAN_ILE_EINT1_Min (0x0UL) /*!< Min enumerator value of EINT1 field. */ + #define MCAN_ILE_EINT1_Max (0x1UL) /*!< Max enumerator value of EINT1 field. */ + #define MCAN_ILE_EINT1_Disable (0x0UL) /*!< Interrupt line CORE1 disabled. */ + #define MCAN_ILE_EINT1_Enable (0x1UL) /*!< Interrupt line CORE1 enabled. */ + + +/* MCAN_GFC: Global Filter Configuration */ + #define MCAN_GFC_ResetValue (0x00000000UL) /*!< Reset value of GFC register. */ + +/* RRFE @Bit 0 : Reject Remote Frames Extended */ + #define MCAN_GFC_RRFE_Pos (0UL) /*!< Position of RRFE field. */ + #define MCAN_GFC_RRFE_Msk (0x1UL << MCAN_GFC_RRFE_Pos) /*!< Bit mask of RRFE field. */ + #define MCAN_GFC_RRFE_Min (0x0UL) /*!< Min enumerator value of RRFE field. */ + #define MCAN_GFC_RRFE_Max (0x1UL) /*!< Max enumerator value of RRFE field. */ + #define MCAN_GFC_RRFE_Filter (0x0UL) /*!< Filter remote frames with 29-bit extended IDs. */ + #define MCAN_GFC_RRFE_Reject (0x1UL) /*!< Reject all remote frames with 29-bit extended IDs. */ + +/* RRFS @Bit 1 : Reject Remote Frames Standard */ + #define MCAN_GFC_RRFS_Pos (1UL) /*!< Position of RRFS field. */ + #define MCAN_GFC_RRFS_Msk (0x1UL << MCAN_GFC_RRFS_Pos) /*!< Bit mask of RRFS field. */ + #define MCAN_GFC_RRFS_Min (0x0UL) /*!< Min enumerator value of RRFS field. */ + #define MCAN_GFC_RRFS_Max (0x1UL) /*!< Max enumerator value of RRFS field. */ + #define MCAN_GFC_RRFS_Filter (0x0UL) /*!< Filter remote frames with 11-bit standard IDs. */ + #define MCAN_GFC_RRFS_Reject (0x1UL) /*!< Reject all remote frames with 11-bit standard IDs. */ + +/* ANFE @Bits 2..3 : Accept Non-matching Frames Extended */ + #define MCAN_GFC_ANFE_Pos (2UL) /*!< Position of ANFE field. */ + #define MCAN_GFC_ANFE_Msk (0x3UL << MCAN_GFC_ANFE_Pos) /*!< Bit mask of ANFE field. */ + #define MCAN_GFC_ANFE_Min (0x0UL) /*!< Min enumerator value of ANFE field. */ + #define MCAN_GFC_ANFE_Max (0x3UL) /*!< Max enumerator value of ANFE field. */ + #define MCAN_GFC_ANFE_Accept0 (0x0UL) /*!< Accept in Rx FIFO 0. */ + #define MCAN_GFC_ANFE_Accept1 (0x1UL) /*!< Accept in Rx FIFO 1. */ + #define MCAN_GFC_ANFE_Reject0 (0x2UL) /*!< Reject in both Rx FIFOs. */ + #define MCAN_GFC_ANFE_Reject1 (0x3UL) /*!< Reject in both Rx FIFOs. */ + +/* ANFS @Bits 4..5 : (unspecified) */ + #define MCAN_GFC_ANFS_Pos (4UL) /*!< Position of ANFS field. */ + #define MCAN_GFC_ANFS_Msk (0x3UL << MCAN_GFC_ANFS_Pos) /*!< Bit mask of ANFS field. */ + #define MCAN_GFC_ANFS_Min (0x0UL) /*!< Min enumerator value of ANFS field. */ + #define MCAN_GFC_ANFS_Max (0x3UL) /*!< Max enumerator value of ANFS field. */ + #define MCAN_GFC_ANFS_Accept0 (0x0UL) /*!< Accept in Rx FIFO 0. */ + #define MCAN_GFC_ANFS_Accept1 (0x1UL) /*!< Accept in Rx FIFO 1. */ + #define MCAN_GFC_ANFS_Reject0 (0x2UL) /*!< Reject in both Rx FIFOs. */ + #define MCAN_GFC_ANFS_Reject1 (0x3UL) /*!< Reject in both Rx FIFOs. */ + + +/* MCAN_SIDFC: Standard ID Filter Configuration */ + #define MCAN_SIDFC_ResetValue (0x00000000UL) /*!< Reset value of SIDFC register. */ + +/* FLSSA @Bits 2..15 : Filter List Standard Start Address */ + #define MCAN_SIDFC_FLSSA_Pos (2UL) /*!< Position of FLSSA field. */ + #define MCAN_SIDFC_FLSSA_Msk (0x3FFFUL << MCAN_SIDFC_FLSSA_Pos) /*!< Bit mask of FLSSA field. */ + +/* LSS @Bits 16..23 : List Size Standard */ + #define MCAN_SIDFC_LSS_Pos (16UL) /*!< Position of LSS field. */ + #define MCAN_SIDFC_LSS_Msk (0xFFUL << MCAN_SIDFC_LSS_Pos) /*!< Bit mask of LSS field. */ + + +/* MCAN_XIDFC: Extended ID Filter Configuration */ + #define MCAN_XIDFC_ResetValue (0x00000000UL) /*!< Reset value of XIDFC register. */ + +/* FLESA @Bits 2..15 : Filter List Extended Start Address */ + #define MCAN_XIDFC_FLESA_Pos (2UL) /*!< Position of FLESA field. */ + #define MCAN_XIDFC_FLESA_Msk (0x3FFFUL << MCAN_XIDFC_FLESA_Pos) /*!< Bit mask of FLESA field. */ + +/* LSE @Bits 16..22 : List Size Extended */ + #define MCAN_XIDFC_LSE_Pos (16UL) /*!< Position of LSE field. */ + #define MCAN_XIDFC_LSE_Msk (0x7FUL << MCAN_XIDFC_LSE_Pos) /*!< Bit mask of LSE field. */ + + +/* MCAN_XIDAM: Extended ID AND Mask */ + #define MCAN_XIDAM_ResetValue (0x00000000UL) /*!< Reset value of XIDAM register. */ + +/* EIDM @Bits 0..28 : Extended ID Mask */ + #define MCAN_XIDAM_EIDM_Pos (0UL) /*!< Position of EIDM field. */ + #define MCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << MCAN_XIDAM_EIDM_Pos) /*!< Bit mask of EIDM field. */ + + +/* MCAN_HPMS: High Priority Message Status */ + #define MCAN_HPMS_ResetValue (0x00000000UL) /*!< Reset value of HPMS register. */ + +/* BIDX @Bits 0..5 : Buffer Index */ + #define MCAN_HPMS_BIDX_Pos (0UL) /*!< Position of BIDX field. */ + #define MCAN_HPMS_BIDX_Msk (0x3FUL << MCAN_HPMS_BIDX_Pos) /*!< Bit mask of BIDX field. */ + +/* MSI @Bits 6..7 : Message Storage Indicator */ + #define MCAN_HPMS_MSI_Pos (6UL) /*!< Position of MSI field. */ + #define MCAN_HPMS_MSI_Msk (0x3UL << MCAN_HPMS_MSI_Pos) /*!< Bit mask of MSI field. */ + #define MCAN_HPMS_MSI_Min (0x0UL) /*!< Min enumerator value of MSI field. */ + #define MCAN_HPMS_MSI_Max (0x3UL) /*!< Max enumerator value of MSI field. */ + #define MCAN_HPMS_MSI_NotSelected (0x0UL) /*!< No FIFO selected. */ + #define MCAN_HPMS_MSI_Lost (0x1UL) /*!< FIFO message lost. */ + #define MCAN_HPMS_MSI_Stored0 (0x2UL) /*!< Message stored in FIFO 0. */ + #define MCAN_HPMS_MSI_Stored1 (0x3UL) /*!< Message stored in FIFO 1. */ + +/* FIDX @Bits 8..14 : Filter Index */ + #define MCAN_HPMS_FIDX_Pos (8UL) /*!< Position of FIDX field. */ + #define MCAN_HPMS_FIDX_Msk (0x7FUL << MCAN_HPMS_FIDX_Pos) /*!< Bit mask of FIDX field. */ + +/* FLST @Bit 15 : Filter List */ + #define MCAN_HPMS_FLST_Pos (15UL) /*!< Position of FLST field. */ + #define MCAN_HPMS_FLST_Msk (0x1UL << MCAN_HPMS_FLST_Pos) /*!< Bit mask of FLST field. */ + #define MCAN_HPMS_FLST_Min (0x0UL) /*!< Min enumerator value of FLST field. */ + #define MCAN_HPMS_FLST_Max (0x1UL) /*!< Max enumerator value of FLST field. */ + #define MCAN_HPMS_FLST_Standard (0x0UL) /*!< Standard Filter List. */ + #define MCAN_HPMS_FLST_Extended (0x1UL) /*!< Extended Filter List. */ + + +/* MCAN_NDAT1: New Data 1 */ + #define MCAN_NDAT1_ResetValue (0x00000000UL) /*!< Reset value of NDAT1 register. */ + +/* ND @Bits 0..31 : New Data */ + #define MCAN_NDAT1_ND_Pos (0UL) /*!< Position of ND field. */ + #define MCAN_NDAT1_ND_Msk (0xFFFFFFFFUL << MCAN_NDAT1_ND_Pos) /*!< Bit mask of ND field. */ + #define MCAN_NDAT1_ND_Min (0x0UL) /*!< Min enumerator value of ND field. */ + #define MCAN_NDAT1_ND_Max (0x1UL) /*!< Max enumerator value of ND field. */ + #define MCAN_NDAT1_ND_NotUpdated (0x00000000UL) /*!< Rx Buffer not updated. */ + #define MCAN_NDAT1_ND_Updated (0x00000001UL) /*!< Rx Buffer updated from new message. */ + + +/* MCAN_NDAT2: New Data 2 */ + #define MCAN_NDAT2_ResetValue (0x00000000UL) /*!< Reset value of NDAT2 register. */ + +/* ND @Bits 0..31 : New Data */ + #define MCAN_NDAT2_ND_Pos (0UL) /*!< Position of ND field. */ + #define MCAN_NDAT2_ND_Msk (0xFFFFFFFFUL << MCAN_NDAT2_ND_Pos) /*!< Bit mask of ND field. */ + #define MCAN_NDAT2_ND_Min (0x0UL) /*!< Min enumerator value of ND field. */ + #define MCAN_NDAT2_ND_Max (0x1UL) /*!< Max enumerator value of ND field. */ + #define MCAN_NDAT2_ND_NotUpdated (0x00000000UL) /*!< Rx Buffer not updated. */ + #define MCAN_NDAT2_ND_Updated (0x00000001UL) /*!< Rx Buffer updated from new message. */ + + +/* MCAN_RXF0C: Rx FIFO 0 Configuration */ + #define MCAN_RXF0C_ResetValue (0x00000000UL) /*!< Reset value of RXF0C register. */ + +/* F0SA @Bits 2..15 : Rx FIFO 0 Start Address */ + #define MCAN_RXF0C_F0SA_Pos (2UL) /*!< Position of F0SA field. */ + #define MCAN_RXF0C_F0SA_Msk (0x3FFFUL << MCAN_RXF0C_F0SA_Pos) /*!< Bit mask of F0SA field. */ + +/* F0S @Bits 16..22 : Rx FIFO 0 Size */ + #define MCAN_RXF0C_F0S_Pos (16UL) /*!< Position of F0S field. */ + #define MCAN_RXF0C_F0S_Msk (0x7FUL << MCAN_RXF0C_F0S_Pos) /*!< Bit mask of F0S field. */ + +/* F0WM @Bits 24..30 : Rx FIFO 0 Watermark */ + #define MCAN_RXF0C_F0WM_Pos (24UL) /*!< Position of F0WM field. */ + #define MCAN_RXF0C_F0WM_Msk (0x7FUL << MCAN_RXF0C_F0WM_Pos) /*!< Bit mask of F0WM field. */ + +/* F0OM @Bit 31 : FIFO 0 Operation Mode */ + #define MCAN_RXF0C_F0OM_Pos (31UL) /*!< Position of F0OM field. */ + #define MCAN_RXF0C_F0OM_Msk (0x1UL << MCAN_RXF0C_F0OM_Pos) /*!< Bit mask of F0OM field. */ + #define MCAN_RXF0C_F0OM_Min (0x0UL) /*!< Min enumerator value of F0OM field. */ + #define MCAN_RXF0C_F0OM_Max (0x1UL) /*!< Max enumerator value of F0OM field. */ + #define MCAN_RXF0C_F0OM_Blocking (0x0UL) /*!< FIFO 0 blocking mode. */ + #define MCAN_RXF0C_F0OM_Overwrite (0x1UL) /*!< FIFO 0 overwrite mode. */ + + +/* MCAN_RXF0S: Rx FIFO 0 Status */ + #define MCAN_RXF0S_ResetValue (0x00000000UL) /*!< Reset value of RXF0S register. */ + +/* F0FL @Bits 0..6 : Rx FIFO 0 Fill Leve */ + #define MCAN_RXF0S_F0FL_Pos (0UL) /*!< Position of F0FL field. */ + #define MCAN_RXF0S_F0FL_Msk (0x7FUL << MCAN_RXF0S_F0FL_Pos) /*!< Bit mask of F0FL field. */ + +/* F0GI @Bits 8..13 : Rx FIFO 0 Get Index */ + #define MCAN_RXF0S_F0GI_Pos (8UL) /*!< Position of F0GI field. */ + #define MCAN_RXF0S_F0GI_Msk (0x3FUL << MCAN_RXF0S_F0GI_Pos) /*!< Bit mask of F0GI field. */ + +/* F0PI @Bits 16..21 : Rx FIFO 0 Put Index */ + #define MCAN_RXF0S_F0PI_Pos (16UL) /*!< Position of F0PI field. */ + #define MCAN_RXF0S_F0PI_Msk (0x3FUL << MCAN_RXF0S_F0PI_Pos) /*!< Bit mask of F0PI field. */ + +/* F0F @Bit 24 : Rx FIFO 0 Full */ + #define MCAN_RXF0S_F0F_Pos (24UL) /*!< Position of F0F field. */ + #define MCAN_RXF0S_F0F_Msk (0x1UL << MCAN_RXF0S_F0F_Pos) /*!< Bit mask of F0F field. */ + #define MCAN_RXF0S_F0F_Min (0x0UL) /*!< Min enumerator value of F0F field. */ + #define MCAN_RXF0S_F0F_Max (0x1UL) /*!< Max enumerator value of F0F field. */ + #define MCAN_RXF0S_F0F_NotFull (0x0UL) /*!< Rx FIFO 0 not full. */ + #define MCAN_RXF0S_F0F_Full (0x1UL) /*!< Rx FIFO 0 full. */ + +/* RF0L @Bit 25 : Rx FIFO 0 Message Lost */ + #define MCAN_RXF0S_RF0L_Pos (25UL) /*!< Position of RF0L field. */ + #define MCAN_RXF0S_RF0L_Msk (0x1UL << MCAN_RXF0S_RF0L_Pos) /*!< Bit mask of RF0L field. */ + #define MCAN_RXF0S_RF0L_Min (0x0UL) /*!< Min enumerator value of RF0L field. */ + #define MCAN_RXF0S_RF0L_Max (0x1UL) /*!< Max enumerator value of RF0L field. */ + #define MCAN_RXF0S_RF0L_NotLost (0x0UL) /*!< No Rx FIFO 0 message lost. */ + #define MCAN_RXF0S_RF0L_Lost (0x1UL) /*!< Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of + size zero.*/ + + +/* MCAN_RXF0A: Rx FIFO 0 Acknowledge */ + #define MCAN_RXF0A_ResetValue (0x00000000UL) /*!< Reset value of RXF0A register. */ + +/* F0AI @Bits 0..5 : Rx FIFO 0 Acknowledge Index */ + #define MCAN_RXF0A_F0AI_Pos (0UL) /*!< Position of F0AI field. */ + #define MCAN_RXF0A_F0AI_Msk (0x3FUL << MCAN_RXF0A_F0AI_Pos) /*!< Bit mask of F0AI field. */ + + +/* MCAN_RXBC: Rx Buffer Configuration */ + #define MCAN_RXBC_ResetValue (0x00000000UL) /*!< Reset value of RXBC register. */ + +/* RBSA @Bits 2..15 : Rx Buffer Start Address */ + #define MCAN_RXBC_RBSA_Pos (2UL) /*!< Position of RBSA field. */ + #define MCAN_RXBC_RBSA_Msk (0x3FFFUL << MCAN_RXBC_RBSA_Pos) /*!< Bit mask of RBSA field. */ + + +/* MCAN_RXF1C: Rx FIFO 1 Configuration */ + #define MCAN_RXF1C_ResetValue (0x00000000UL) /*!< Reset value of RXF1C register. */ + +/* F1SA @Bits 2..15 : Rx FIFO 1 Start Address */ + #define MCAN_RXF1C_F1SA_Pos (2UL) /*!< Position of F1SA field. */ + #define MCAN_RXF1C_F1SA_Msk (0x3FFFUL << MCAN_RXF1C_F1SA_Pos) /*!< Bit mask of F1SA field. */ + +/* F1S @Bits 16..22 : Rx FIFO 1 Size */ + #define MCAN_RXF1C_F1S_Pos (16UL) /*!< Position of F1S field. */ + #define MCAN_RXF1C_F1S_Msk (0x7FUL << MCAN_RXF1C_F1S_Pos) /*!< Bit mask of F1S field. */ + +/* F1WM @Bits 24..30 : Rx FIFO 1 Watermark */ + #define MCAN_RXF1C_F1WM_Pos (24UL) /*!< Position of F1WM field. */ + #define MCAN_RXF1C_F1WM_Msk (0x7FUL << MCAN_RXF1C_F1WM_Pos) /*!< Bit mask of F1WM field. */ + +/* F1OM @Bit 31 : FIFO 1 Operation Mode */ + #define MCAN_RXF1C_F1OM_Pos (31UL) /*!< Position of F1OM field. */ + #define MCAN_RXF1C_F1OM_Msk (0x1UL << MCAN_RXF1C_F1OM_Pos) /*!< Bit mask of F1OM field. */ + #define MCAN_RXF1C_F1OM_Min (0x0UL) /*!< Min enumerator value of F1OM field. */ + #define MCAN_RXF1C_F1OM_Max (0x1UL) /*!< Max enumerator value of F1OM field. */ + #define MCAN_RXF1C_F1OM_BlockingMode (0x0UL) /*!< FIFO 1 blocking mode */ + #define MCAN_RXF1C_F1OM_OwerwriteMode (0x1UL) /*!< FIFO 1 overwrite mode */ + + +/* MCAN_RXF1S: Rx FIFO 1 Status */ + #define MCAN_RXF1S_ResetValue (0x00000000UL) /*!< Reset value of RXF1S register. */ + +/* F1FL @Bits 0..6 : Rx FIFO 1 Fill Level */ + #define MCAN_RXF1S_F1FL_Pos (0UL) /*!< Position of F1FL field. */ + #define MCAN_RXF1S_F1FL_Msk (0x7FUL << MCAN_RXF1S_F1FL_Pos) /*!< Bit mask of F1FL field. */ + +/* F1GI @Bits 8..13 : Rx FIFO 1 Get Index */ + #define MCAN_RXF1S_F1GI_Pos (8UL) /*!< Position of F1GI field. */ + #define MCAN_RXF1S_F1GI_Msk (0x3FUL << MCAN_RXF1S_F1GI_Pos) /*!< Bit mask of F1GI field. */ + +/* F1PI @Bits 16..21 : Rx FIFO 1 Put Index */ + #define MCAN_RXF1S_F1PI_Pos (16UL) /*!< Position of F1PI field. */ + #define MCAN_RXF1S_F1PI_Msk (0x3FUL << MCAN_RXF1S_F1PI_Pos) /*!< Bit mask of F1PI field. */ + +/* F1F @Bit 24 : Rx FIFO 1 Full */ + #define MCAN_RXF1S_F1F_Pos (24UL) /*!< Position of F1F field. */ + #define MCAN_RXF1S_F1F_Msk (0x1UL << MCAN_RXF1S_F1F_Pos) /*!< Bit mask of F1F field. */ + #define MCAN_RXF1S_F1F_Min (0x0UL) /*!< Min enumerator value of F1F field. */ + #define MCAN_RXF1S_F1F_Max (0x1UL) /*!< Max enumerator value of F1F field. */ + #define MCAN_RXF1S_F1F_NotFull (0x0UL) /*!< Rx FIFO 1 not full */ + #define MCAN_RXF1S_F1F_Full (0x1UL) /*!< Rx FIFO 1 full */ + +/* RF1L @Bit 25 : Rx FIFO 1 Message Lost */ + #define MCAN_RXF1S_RF1L_Pos (25UL) /*!< Position of RF1L field. */ + #define MCAN_RXF1S_RF1L_Msk (0x1UL << MCAN_RXF1S_RF1L_Pos) /*!< Bit mask of RF1L field. */ + #define MCAN_RXF1S_RF1L_Min (0x0UL) /*!< Min enumerator value of RF1L field. */ + #define MCAN_RXF1S_RF1L_Max (0x1UL) /*!< Max enumerator value of RF1L field. */ + #define MCAN_RXF1S_RF1L_NoMessageLost (0x0UL) /*!< No Rx FIFO 1 message lost */ + #define MCAN_RXF1S_RF1L_MessageLost (0x1UL) /*!< Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of + size zero*/ + +/* DMS @Bits 30..31 : Debug Message Status */ + #define MCAN_RXF1S_DMS_Pos (30UL) /*!< Position of DMS field. */ + #define MCAN_RXF1S_DMS_Msk (0x3UL << MCAN_RXF1S_DMS_Pos) /*!< Bit mask of DMS field. */ + #define MCAN_RXF1S_DMS_Min (0x0UL) /*!< Min enumerator value of DMS field. */ + #define MCAN_RXF1S_DMS_Max (0x3UL) /*!< Max enumerator value of DMS field. */ + #define MCAN_RXF1S_DMS_Idle (0x0UL) /*!< Idle state, wait for reception of debug messages, DMA request is + cleared*/ + #define MCAN_RXF1S_DMS_ReceivedMesA (0x1UL) /*!< Debug message A received */ + #define MCAN_RXF1S_DMS_ReceivedMesAB (0x2UL) /*!< Debug messages A, B received */ + #define MCAN_RXF1S_DMS_ReceivedMesABC (0x3UL) /*!< Debug messages A, B, C received, DMA request is set */ + + +/* MCAN_RXF1A: Rx FIFO 1 Acknowledge */ + #define MCAN_RXF1A_ResetValue (0x00000000UL) /*!< Reset value of RXF1A register. */ + +/* F1AI @Bits 0..5 : Rx FIFO 1 Acknowledge Index */ + #define MCAN_RXF1A_F1AI_Pos (0UL) /*!< Position of F1AI field. */ + #define MCAN_RXF1A_F1AI_Msk (0x3FUL << MCAN_RXF1A_F1AI_Pos) /*!< Bit mask of F1AI field. */ + + +/* MCAN_RXESC: Rx Buffer / FIFO Element Size Configuration */ + #define MCAN_RXESC_ResetValue (0x00000000UL) /*!< Reset value of RXESC register. */ + +/* F0DS @Bits 0..2 : Rx FIFO 0 Data Field Size */ + #define MCAN_RXESC_F0DS_Pos (0UL) /*!< Position of F0DS field. */ + #define MCAN_RXESC_F0DS_Msk (0x7UL << MCAN_RXESC_F0DS_Pos) /*!< Bit mask of F0DS field. */ + #define MCAN_RXESC_F0DS_Min (0x0UL) /*!< Min enumerator value of F0DS field. */ + #define MCAN_RXESC_F0DS_Max (0x7UL) /*!< Max enumerator value of F0DS field. */ + #define MCAN_RXESC_F0DS_DataField8B (0x0UL) /*!< 8 byte data field */ + #define MCAN_RXESC_F0DS_DataField12B (0x1UL) /*!< 12 byte data field */ + #define MCAN_RXESC_F0DS_DataField16B (0x2UL) /*!< 16 byte data field */ + #define MCAN_RXESC_F0DS_DataField20B (0x3UL) /*!< 20 byte data field */ + #define MCAN_RXESC_F0DS_DataField24B (0x4UL) /*!< 24 byte data field */ + #define MCAN_RXESC_F0DS_DataField32B (0x5UL) /*!< 32 byte data field */ + #define MCAN_RXESC_F0DS_DataField48B (0x6UL) /*!< 48 byte data field */ + #define MCAN_RXESC_F0DS_DataField64B (0x7UL) /*!< 64 byte data field */ + +/* F1DS @Bits 4..6 : Rx FIFO 1 Data Field Size */ + #define MCAN_RXESC_F1DS_Pos (4UL) /*!< Position of F1DS field. */ + #define MCAN_RXESC_F1DS_Msk (0x7UL << MCAN_RXESC_F1DS_Pos) /*!< Bit mask of F1DS field. */ + #define MCAN_RXESC_F1DS_Min (0x0UL) /*!< Min enumerator value of F1DS field. */ + #define MCAN_RXESC_F1DS_Max (0x7UL) /*!< Max enumerator value of F1DS field. */ + #define MCAN_RXESC_F1DS_DataField8B (0x0UL) /*!< 8 byte data field */ + #define MCAN_RXESC_F1DS_DataField12B (0x1UL) /*!< 12 byte data field */ + #define MCAN_RXESC_F1DS_DataField16B (0x2UL) /*!< 16 byte data field */ + #define MCAN_RXESC_F1DS_DataField20B (0x3UL) /*!< 20 byte data field */ + #define MCAN_RXESC_F1DS_DataField24B (0x4UL) /*!< 24 byte data field */ + #define MCAN_RXESC_F1DS_DataField32B (0x5UL) /*!< 32 byte data field */ + #define MCAN_RXESC_F1DS_DataField48B (0x6UL) /*!< 48 byte data field */ + #define MCAN_RXESC_F1DS_DataField64B (0x7UL) /*!< 64 byte data field */ + +/* RBDS @Bits 8..10 : Rx Buffer Data Field Size */ + #define MCAN_RXESC_RBDS_Pos (8UL) /*!< Position of RBDS field. */ + #define MCAN_RXESC_RBDS_Msk (0x7UL << MCAN_RXESC_RBDS_Pos) /*!< Bit mask of RBDS field. */ + #define MCAN_RXESC_RBDS_Min (0x0UL) /*!< Min enumerator value of RBDS field. */ + #define MCAN_RXESC_RBDS_Max (0x7UL) /*!< Max enumerator value of RBDS field. */ + #define MCAN_RXESC_RBDS_DataField8B (0x0UL) /*!< 8 byte data field */ + #define MCAN_RXESC_RBDS_DataField12B (0x1UL) /*!< 12 byte data field */ + #define MCAN_RXESC_RBDS_DataField16B (0x2UL) /*!< 16 byte data field */ + #define MCAN_RXESC_RBDS_DataField20B (0x3UL) /*!< 20 byte data field */ + #define MCAN_RXESC_RBDS_DataField24B (0x4UL) /*!< 24 byte data field */ + #define MCAN_RXESC_RBDS_DataField32B (0x5UL) /*!< 32 byte data field */ + #define MCAN_RXESC_RBDS_DataField48B (0x6UL) /*!< 48 byte data field */ + #define MCAN_RXESC_RBDS_DataField64B (0x7UL) /*!< 64 byte data field */ + + +/* MCAN_TXBC: Tx Buffer Configuration */ + #define MCAN_TXBC_ResetValue (0x00000000UL) /*!< Reset value of TXBC register. */ + +/* TBSA @Bits 2..15 : Tx Buffers Start Address */ + #define MCAN_TXBC_TBSA_Pos (2UL) /*!< Position of TBSA field. */ + #define MCAN_TXBC_TBSA_Msk (0x3FFFUL << MCAN_TXBC_TBSA_Pos) /*!< Bit mask of TBSA field. */ + +/* NDTB @Bits 16..21 : Number of Dedicated Transmit Buffers */ + #define MCAN_TXBC_NDTB_Pos (16UL) /*!< Position of NDTB field. */ + #define MCAN_TXBC_NDTB_Msk (0x3FUL << MCAN_TXBC_NDTB_Pos) /*!< Bit mask of NDTB field. */ + +/* TFQS @Bits 24..29 : Transmit FIFO/Queue Size */ + #define MCAN_TXBC_TFQS_Pos (24UL) /*!< Position of TFQS field. */ + #define MCAN_TXBC_TFQS_Msk (0x3FUL << MCAN_TXBC_TFQS_Pos) /*!< Bit mask of TFQS field. */ + +/* TFQM @Bit 30 : Tx FIFO/Queue Mode */ + #define MCAN_TXBC_TFQM_Pos (30UL) /*!< Position of TFQM field. */ + #define MCAN_TXBC_TFQM_Msk (0x1UL << MCAN_TXBC_TFQM_Pos) /*!< Bit mask of TFQM field. */ + #define MCAN_TXBC_TFQM_Min (0x0UL) /*!< Min enumerator value of TFQM field. */ + #define MCAN_TXBC_TFQM_Max (0x1UL) /*!< Max enumerator value of TFQM field. */ + #define MCAN_TXBC_TFQM_TxFIFO (0x0UL) /*!< Tx FIFO operation */ + #define MCAN_TXBC_TFQM_TxQueue (0x1UL) /*!< Tx Queue operation */ + + +/* MCAN_TXFQS: Tx FIFO/Queue Status */ + #define MCAN_TXFQS_ResetValue (0x00000000UL) /*!< Reset value of TXFQS register. */ + +/* TFFL @Bits 0..5 : Tx FIFO Free Level */ + #define MCAN_TXFQS_TFFL_Pos (0UL) /*!< Position of TFFL field. */ + #define MCAN_TXFQS_TFFL_Msk (0x3FUL << MCAN_TXFQS_TFFL_Pos) /*!< Bit mask of TFFL field. */ + +/* TFGI @Bits 8..12 : Tx FIFO Get Index */ + #define MCAN_TXFQS_TFGI_Pos (8UL) /*!< Position of TFGI field. */ + #define MCAN_TXFQS_TFGI_Msk (0x1FUL << MCAN_TXFQS_TFGI_Pos) /*!< Bit mask of TFGI field. */ + +/* TFQPI @Bits 16..20 : Tx FIFO/Queue Put Index */ + #define MCAN_TXFQS_TFQPI_Pos (16UL) /*!< Position of TFQPI field. */ + #define MCAN_TXFQS_TFQPI_Msk (0x1FUL << MCAN_TXFQS_TFQPI_Pos) /*!< Bit mask of TFQPI field. */ + +/* TFQF @Bit 21 : Tx FIFO/Queue Full */ + #define MCAN_TXFQS_TFQF_Pos (21UL) /*!< Position of TFQF field. */ + #define MCAN_TXFQS_TFQF_Msk (0x1UL << MCAN_TXFQS_TFQF_Pos) /*!< Bit mask of TFQF field. */ + #define MCAN_TXFQS_TFQF_Min (0x0UL) /*!< Min enumerator value of TFQF field. */ + #define MCAN_TXFQS_TFQF_Max (0x1UL) /*!< Max enumerator value of TFQF field. */ + #define MCAN_TXFQS_TFQF_NotFull (0x0UL) /*!< Tx FIFO/Queue not full */ + #define MCAN_TXFQS_TFQF_Full (0x1UL) /*!< Tx FIFO/Queue full */ + + +/* MCAN_TXESC: Tx Buffer Element Size Configuration */ + #define MCAN_TXESC_ResetValue (0x00000000UL) /*!< Reset value of TXESC register. */ + +/* TBDS @Bits 0..2 : Tx Buffer Data Field Size */ + #define MCAN_TXESC_TBDS_Pos (0UL) /*!< Position of TBDS field. */ + #define MCAN_TXESC_TBDS_Msk (0x7UL << MCAN_TXESC_TBDS_Pos) /*!< Bit mask of TBDS field. */ + #define MCAN_TXESC_TBDS_Min (0x0UL) /*!< Min enumerator value of TBDS field. */ + #define MCAN_TXESC_TBDS_Max (0x7UL) /*!< Max enumerator value of TBDS field. */ + #define MCAN_TXESC_TBDS_DataField8B (0x0UL) /*!< 8 byte data field */ + #define MCAN_TXESC_TBDS_DataField12B (0x1UL) /*!< 12 byte data field */ + #define MCAN_TXESC_TBDS_DataField16B (0x2UL) /*!< 16 byte data field */ + #define MCAN_TXESC_TBDS_DataField20B (0x3UL) /*!< 20 byte data field */ + #define MCAN_TXESC_TBDS_DataField24B (0x4UL) /*!< 24 byte data field */ + #define MCAN_TXESC_TBDS_DataField32B (0x5UL) /*!< 32 byte data field */ + #define MCAN_TXESC_TBDS_DataField48B (0x6UL) /*!< 48 byte data field */ + #define MCAN_TXESC_TBDS_DataField64B (0x7UL) /*!< 64 byte data field */ + + +/* MCAN_TXBRP: Tx Buffer Request Pending */ + #define MCAN_TXBRP_ResetValue (0x00000000UL) /*!< Reset value of TXBRP register. */ + +/* TRP @Bits 0..31 : Transmission Request Pending */ + #define MCAN_TXBRP_TRP_Pos (0UL) /*!< Position of TRP field. */ + #define MCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << MCAN_TXBRP_TRP_Pos) /*!< Bit mask of TRP field. */ + #define MCAN_TXBRP_TRP_Min (0x0UL) /*!< Min enumerator value of TRP field. */ + #define MCAN_TXBRP_TRP_Max (0x1UL) /*!< Max enumerator value of TRP field. */ + #define MCAN_TXBRP_TRP_NoRequest (0x00000000UL) /*!< No transmission request pending */ + #define MCAN_TXBRP_TRP_Request (0x00000001UL) /*!< Transmission request pending */ + + +/* MCAN_TXBAR: Tx Buffer Add Request */ + #define MCAN_TXBAR_ResetValue (0x00000000UL) /*!< Reset value of TXBAR register. */ + +/* AR @Bits 0..31 : Add Request */ + #define MCAN_TXBAR_AR_Pos (0UL) /*!< Position of AR field. */ + #define MCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << MCAN_TXBAR_AR_Pos) /*!< Bit mask of AR field. */ + #define MCAN_TXBAR_AR_Min (0x0UL) /*!< Min enumerator value of AR field. */ + #define MCAN_TXBAR_AR_Max (0x1UL) /*!< Max enumerator value of AR field. */ + #define MCAN_TXBAR_AR_NoRequest (0x00000000UL) /*!< No transmission request added */ + #define MCAN_TXBAR_AR_Request (0x00000001UL) /*!< Transmission requested added */ + + +/* MCAN_TXBCR: Tx Buffer Cancellation Request */ + #define MCAN_TXBCR_ResetValue (0x00000000UL) /*!< Reset value of TXBCR register. */ + +/* CR @Bits 0..31 : Cancellation Request */ + #define MCAN_TXBCR_CR_Pos (0UL) /*!< Position of CR field. */ + #define MCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << MCAN_TXBCR_CR_Pos) /*!< Bit mask of CR field. */ + #define MCAN_TXBCR_CR_Min (0x0UL) /*!< Min enumerator value of CR field. */ + #define MCAN_TXBCR_CR_Max (0x1UL) /*!< Max enumerator value of CR field. */ + #define MCAN_TXBCR_CR_NoCancellation (0x00000000UL) /*!< No cancellation pending */ + #define MCAN_TXBCR_CR_Cancellation (0x00000001UL) /*!< Cancellation pending */ + + +/* MCAN_TXBTO: Tx Buffer Transmission Occurred */ + #define MCAN_TXBTO_ResetValue (0x00000000UL) /*!< Reset value of TXBTO register. */ + +/* TO @Bits 0..31 : Transmission Occurred */ + #define MCAN_TXBTO_TO_Pos (0UL) /*!< Position of TO field. */ + #define MCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << MCAN_TXBTO_TO_Pos) /*!< Bit mask of TO field. */ + #define MCAN_TXBTO_TO_Min (0x0UL) /*!< Min enumerator value of TO field. */ + #define MCAN_TXBTO_TO_Max (0x1UL) /*!< Max enumerator value of TO field. */ + #define MCAN_TXBTO_TO_NoTransmittion (0x00000000UL) /*!< No transmission occurred */ + #define MCAN_TXBTO_TO_Transmittion (0x00000001UL) /*!< Transmission occurred */ + + +/* MCAN_TXBCF: Tx Buffer Cancellation Finished */ + #define MCAN_TXBCF_ResetValue (0x00000000UL) /*!< Reset value of TXBCF register. */ + +/* CF @Bits 0..31 : Cancellation Finished */ + #define MCAN_TXBCF_CF_Pos (0UL) /*!< Position of CF field. */ + #define MCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << MCAN_TXBCF_CF_Pos) /*!< Bit mask of CF field. */ + #define MCAN_TXBCF_CF_Min (0x0UL) /*!< Min enumerator value of CF field. */ + #define MCAN_TXBCF_CF_Max (0x1UL) /*!< Max enumerator value of CF field. */ + #define MCAN_TXBCF_CF_NoCancellation (0x00000000UL) /*!< No transmit buffer cancellation */ + #define MCAN_TXBCF_CF_CancellationFinished (0x00000001UL) /*!< Transmit buffer cancellation finished */ + + +/* MCAN_TXBTIE: Tx Buffer Transmission Interrupt Enable */ + #define MCAN_TXBTIE_ResetValue (0x00000000UL) /*!< Reset value of TXBTIE register. */ + +/* TIE @Bits 0..31 : Transmission Interrupt Enable */ + #define MCAN_TXBTIE_TIE_Pos (0UL) /*!< Position of TIE field. */ + #define MCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << MCAN_TXBTIE_TIE_Pos) /*!< Bit mask of TIE field. */ + #define MCAN_TXBTIE_TIE_Min (0x0UL) /*!< Min enumerator value of TIE field. */ + #define MCAN_TXBTIE_TIE_Max (0x1UL) /*!< Max enumerator value of TIE field. */ + #define MCAN_TXBTIE_TIE_Disable (0x00000000UL) /*!< Transmission interrupt disabled */ + #define MCAN_TXBTIE_TIE_Enable (0x00000001UL) /*!< Transmission interrupt enable */ + + +/* MCAN_TXBCIE: Tx Buffer Cancellation Finished Interrupt Enable */ + #define MCAN_TXBCIE_ResetValue (0x00000000UL) /*!< Reset value of TXBCIE register. */ + +/* CFIE @Bits 0..31 : Cancellation Finished Interrupt Enable */ + #define MCAN_TXBCIE_CFIE_Pos (0UL) /*!< Position of CFIE field. */ + #define MCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << MCAN_TXBCIE_CFIE_Pos) /*!< Bit mask of CFIE field. */ + #define MCAN_TXBCIE_CFIE_Min (0x0UL) /*!< Min enumerator value of CFIE field. */ + #define MCAN_TXBCIE_CFIE_Max (0x1UL) /*!< Max enumerator value of CFIE field. */ + #define MCAN_TXBCIE_CFIE_Disable (0x00000000UL) /*!< Cancellation finished interrupt disabled */ + #define MCAN_TXBCIE_CFIE_Enable (0x00000001UL) /*!< Cancellation finished interrupt enabled */ + + +/* MCAN_TXEFC: Tx Event FIFO Configuration */ + #define MCAN_TXEFC_ResetValue (0x00000000UL) /*!< Reset value of TXEFC register. */ + +/* EFSA @Bits 2..15 : Event FIFO Start Address */ + #define MCAN_TXEFC_EFSA_Pos (2UL) /*!< Position of EFSA field. */ + #define MCAN_TXEFC_EFSA_Msk (0x3FFFUL << MCAN_TXEFC_EFSA_Pos) /*!< Bit mask of EFSA field. */ + +/* EFS @Bits 16..21 : Event FIFO Size */ + #define MCAN_TXEFC_EFS_Pos (16UL) /*!< Position of EFS field. */ + #define MCAN_TXEFC_EFS_Msk (0x3FUL << MCAN_TXEFC_EFS_Pos) /*!< Bit mask of EFS field. */ + +/* EFWM @Bits 24..29 : Event FIFO Watermark */ + #define MCAN_TXEFC_EFWM_Pos (24UL) /*!< Position of EFWM field. */ + #define MCAN_TXEFC_EFWM_Msk (0x3FUL << MCAN_TXEFC_EFWM_Pos) /*!< Bit mask of EFWM field. */ + + +/* MCAN_TXEFS: Tx Event FIFO Status */ + #define MCAN_TXEFS_ResetValue (0x00000000UL) /*!< Reset value of TXEFS register. */ + +/* EFFL @Bits 0..5 : Event FIFO Fill Level */ + #define MCAN_TXEFS_EFFL_Pos (0UL) /*!< Position of EFFL field. */ + #define MCAN_TXEFS_EFFL_Msk (0x3FUL << MCAN_TXEFS_EFFL_Pos) /*!< Bit mask of EFFL field. */ + +/* EFGI @Bits 8..12 : Event FIFO Get Index */ + #define MCAN_TXEFS_EFGI_Pos (8UL) /*!< Position of EFGI field. */ + #define MCAN_TXEFS_EFGI_Msk (0x1FUL << MCAN_TXEFS_EFGI_Pos) /*!< Bit mask of EFGI field. */ + +/* EFPI @Bits 16..20 : Event FIFO Put Index */ + #define MCAN_TXEFS_EFPI_Pos (16UL) /*!< Position of EFPI field. */ + #define MCAN_TXEFS_EFPI_Msk (0x1FUL << MCAN_TXEFS_EFPI_Pos) /*!< Bit mask of EFPI field. */ + +/* EFF @Bit 24 : Event FIFO Full */ + #define MCAN_TXEFS_EFF_Pos (24UL) /*!< Position of EFF field. */ + #define MCAN_TXEFS_EFF_Msk (0x1UL << MCAN_TXEFS_EFF_Pos) /*!< Bit mask of EFF field. */ + #define MCAN_TXEFS_EFF_Min (0x0UL) /*!< Min enumerator value of EFF field. */ + #define MCAN_TXEFS_EFF_Max (0x1UL) /*!< Max enumerator value of EFF field. */ + #define MCAN_TXEFS_EFF_NotFull (0x0UL) /*!< Tx Event FIFO not full */ + #define MCAN_TXEFS_EFF_Full (0x1UL) /*!< Tx Event FIFO full */ + +/* TEFL @Bit 25 : Tx Event FIFO Element Lost */ + #define MCAN_TXEFS_TEFL_Pos (25UL) /*!< Position of TEFL field. */ + #define MCAN_TXEFS_TEFL_Msk (0x1UL << MCAN_TXEFS_TEFL_Pos) /*!< Bit mask of TEFL field. */ + #define MCAN_TXEFS_TEFL_Min (0x0UL) /*!< Min enumerator value of TEFL field. */ + #define MCAN_TXEFS_TEFL_Max (0x1UL) /*!< Max enumerator value of TEFL field. */ + #define MCAN_TXEFS_TEFL_NotLost (0x0UL) /*!< No Tx Event FIFO element lost */ + #define MCAN_TXEFS_TEFL_Lost (0x1UL) /*!< Tx Event FIFO element lost, also set after wr ite attempt to Tx Event + FIFO of siz e zero.*/ + + +/* MCAN_TXEFA: Tx Event FIFO Acknowledge */ + #define MCAN_TXEFA_ResetValue (0x00000000UL) /*!< Reset value of TXEFA register. */ + +/* EFAI @Bits 0..4 : Event FIFO Acknowledge Index */ + #define MCAN_TXEFA_EFAI_Pos (0UL) /*!< Position of EFAI field. */ + #define MCAN_TXEFA_EFAI_Msk (0x1FUL << MCAN_TXEFA_EFAI_Pos) /*!< Bit mask of EFAI field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MEMCONF ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct MEMCONF_POWER =================================================== */ +/** + * @brief POWER [MEMCONF_POWER] (unspecified) + */ +typedef struct { + __IOM uint32_t CONTROL; /*!< (@ 0x00000000) Control memory block power. */ + __IM uint32_t RESERVED; + __IOM uint32_t RET; /*!< (@ 0x00000008) RAM retention for RAM [n]. */ + __IOM uint32_t RET2; /*!< (@ 0x0000000C) RAM retention for the second bank in the RAM block */ +} NRF_MEMCONF_POWER_Type; /*!< Size = 16 (0x010) */ + #define MEMCONF_POWER_MaxCount (2UL) /*!< Size of POWER[2] array. */ + #define MEMCONF_POWER_MaxIndex (1UL) /*!< Max index of POWER[2] array. */ + #define MEMCONF_POWER_MinIndex (0UL) /*!< Min index of POWER[2] array. */ + +/* MEMCONF_POWER_CONTROL: Control memory block power. */ + #define MEMCONF_POWER_CONTROL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONTROL register. */ + +/* MEM0 @Bit 0 : Keep the memory block MEM[0] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM0_Pos (0UL) /*!< Position of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM0_Pos) /*!< Bit mask of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Min (0x0UL) /*!< Min enumerator value of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Max (0x1UL) /*!< Max enumerator value of MEM0 field. */ + #define MEMCONF_POWER_CONTROL_MEM0_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM0_On (0x1UL) /*!< Power up */ + +/* MEM1 @Bit 1 : Keep the memory block MEM[1] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM1_Pos (1UL) /*!< Position of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM1_Pos) /*!< Bit mask of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Min (0x0UL) /*!< Min enumerator value of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Max (0x1UL) /*!< Max enumerator value of MEM1 field. */ + #define MEMCONF_POWER_CONTROL_MEM1_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM1_On (0x1UL) /*!< Power up */ + +/* MEM2 @Bit 2 : Keep the memory block MEM[2] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM2_Pos (2UL) /*!< Position of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM2_Pos) /*!< Bit mask of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Min (0x0UL) /*!< Min enumerator value of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Max (0x1UL) /*!< Max enumerator value of MEM2 field. */ + #define MEMCONF_POWER_CONTROL_MEM2_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM2_On (0x1UL) /*!< Power up */ + +/* MEM3 @Bit 3 : Keep the memory block MEM[3] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM3_Pos (3UL) /*!< Position of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM3_Pos) /*!< Bit mask of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Min (0x0UL) /*!< Min enumerator value of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Max (0x1UL) /*!< Max enumerator value of MEM3 field. */ + #define MEMCONF_POWER_CONTROL_MEM3_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM3_On (0x1UL) /*!< Power up */ + +/* MEM4 @Bit 4 : Keep the memory block MEM[4] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM4_Pos (4UL) /*!< Position of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM4_Pos) /*!< Bit mask of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Min (0x0UL) /*!< Min enumerator value of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Max (0x1UL) /*!< Max enumerator value of MEM4 field. */ + #define MEMCONF_POWER_CONTROL_MEM4_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM4_On (0x1UL) /*!< Power up */ + +/* MEM5 @Bit 5 : Keep the memory block MEM[5] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM5_Pos (5UL) /*!< Position of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM5_Pos) /*!< Bit mask of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Min (0x0UL) /*!< Min enumerator value of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Max (0x1UL) /*!< Max enumerator value of MEM5 field. */ + #define MEMCONF_POWER_CONTROL_MEM5_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM5_On (0x1UL) /*!< Power up */ + +/* MEM6 @Bit 6 : Keep the memory block MEM[6] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM6_Pos (6UL) /*!< Position of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM6_Pos) /*!< Bit mask of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Min (0x0UL) /*!< Min enumerator value of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Max (0x1UL) /*!< Max enumerator value of MEM6 field. */ + #define MEMCONF_POWER_CONTROL_MEM6_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM6_On (0x1UL) /*!< Power up */ + +/* MEM7 @Bit 7 : Keep the memory block MEM[7] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM7_Pos (7UL) /*!< Position of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM7_Pos) /*!< Bit mask of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Min (0x0UL) /*!< Min enumerator value of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Max (0x1UL) /*!< Max enumerator value of MEM7 field. */ + #define MEMCONF_POWER_CONTROL_MEM7_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM7_On (0x1UL) /*!< Power up */ + +/* MEM8 @Bit 8 : Keep the memory block MEM[8] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM8_Pos (8UL) /*!< Position of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM8_Pos) /*!< Bit mask of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Min (0x0UL) /*!< Min enumerator value of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Max (0x1UL) /*!< Max enumerator value of MEM8 field. */ + #define MEMCONF_POWER_CONTROL_MEM8_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM8_On (0x1UL) /*!< Power up */ + +/* MEM9 @Bit 9 : Keep the memory block MEM[9] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM9_Pos (9UL) /*!< Position of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM9_Pos) /*!< Bit mask of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Min (0x0UL) /*!< Min enumerator value of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Max (0x1UL) /*!< Max enumerator value of MEM9 field. */ + #define MEMCONF_POWER_CONTROL_MEM9_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM9_On (0x1UL) /*!< Power up */ + +/* MEM10 @Bit 10 : Keep the memory block MEM[10] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM10_Pos (10UL) /*!< Position of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM10_Pos) /*!< Bit mask of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Min (0x0UL) /*!< Min enumerator value of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Max (0x1UL) /*!< Max enumerator value of MEM10 field. */ + #define MEMCONF_POWER_CONTROL_MEM10_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM10_On (0x1UL) /*!< Power up */ + +/* MEM11 @Bit 11 : Keep the memory block MEM[11] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM11_Pos (11UL) /*!< Position of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM11_Pos) /*!< Bit mask of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Min (0x0UL) /*!< Min enumerator value of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Max (0x1UL) /*!< Max enumerator value of MEM11 field. */ + #define MEMCONF_POWER_CONTROL_MEM11_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM11_On (0x1UL) /*!< Power up */ + +/* MEM12 @Bit 12 : Keep the memory block MEM[12] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM12_Pos (12UL) /*!< Position of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM12_Pos) /*!< Bit mask of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Min (0x0UL) /*!< Min enumerator value of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Max (0x1UL) /*!< Max enumerator value of MEM12 field. */ + #define MEMCONF_POWER_CONTROL_MEM12_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM12_On (0x1UL) /*!< Power up */ + +/* MEM13 @Bit 13 : Keep the memory block MEM[13] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM13_Pos (13UL) /*!< Position of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM13_Pos) /*!< Bit mask of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Min (0x0UL) /*!< Min enumerator value of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Max (0x1UL) /*!< Max enumerator value of MEM13 field. */ + #define MEMCONF_POWER_CONTROL_MEM13_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM13_On (0x1UL) /*!< Power up */ + +/* MEM14 @Bit 14 : Keep the memory block MEM[14] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM14_Pos (14UL) /*!< Position of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM14_Pos) /*!< Bit mask of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Min (0x0UL) /*!< Min enumerator value of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Max (0x1UL) /*!< Max enumerator value of MEM14 field. */ + #define MEMCONF_POWER_CONTROL_MEM14_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM14_On (0x1UL) /*!< Power up */ + +/* MEM15 @Bit 15 : Keep the memory block MEM[15] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM15_Pos (15UL) /*!< Position of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM15_Pos) /*!< Bit mask of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Min (0x0UL) /*!< Min enumerator value of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Max (0x1UL) /*!< Max enumerator value of MEM15 field. */ + #define MEMCONF_POWER_CONTROL_MEM15_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM15_On (0x1UL) /*!< Power up */ + +/* MEM16 @Bit 16 : Keep the memory block MEM[16] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM16_Pos (16UL) /*!< Position of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM16_Pos) /*!< Bit mask of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Min (0x0UL) /*!< Min enumerator value of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Max (0x1UL) /*!< Max enumerator value of MEM16 field. */ + #define MEMCONF_POWER_CONTROL_MEM16_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM16_On (0x1UL) /*!< Power up */ + +/* MEM17 @Bit 17 : Keep the memory block MEM[17] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM17_Pos (17UL) /*!< Position of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM17_Pos) /*!< Bit mask of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Min (0x0UL) /*!< Min enumerator value of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Max (0x1UL) /*!< Max enumerator value of MEM17 field. */ + #define MEMCONF_POWER_CONTROL_MEM17_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM17_On (0x1UL) /*!< Power up */ + +/* MEM18 @Bit 18 : Keep the memory block MEM[18] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM18_Pos (18UL) /*!< Position of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM18_Pos) /*!< Bit mask of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Min (0x0UL) /*!< Min enumerator value of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Max (0x1UL) /*!< Max enumerator value of MEM18 field. */ + #define MEMCONF_POWER_CONTROL_MEM18_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM18_On (0x1UL) /*!< Power up */ + +/* MEM19 @Bit 19 : Keep the memory block MEM[19] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM19_Pos (19UL) /*!< Position of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM19_Pos) /*!< Bit mask of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Min (0x0UL) /*!< Min enumerator value of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Max (0x1UL) /*!< Max enumerator value of MEM19 field. */ + #define MEMCONF_POWER_CONTROL_MEM19_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM19_On (0x1UL) /*!< Power up */ + +/* MEM20 @Bit 20 : Keep the memory block MEM[20] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM20_Pos (20UL) /*!< Position of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM20_Pos) /*!< Bit mask of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Min (0x0UL) /*!< Min enumerator value of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Max (0x1UL) /*!< Max enumerator value of MEM20 field. */ + #define MEMCONF_POWER_CONTROL_MEM20_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM20_On (0x1UL) /*!< Power up */ + +/* MEM21 @Bit 21 : Keep the memory block MEM[21] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM21_Pos (21UL) /*!< Position of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM21_Pos) /*!< Bit mask of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Min (0x0UL) /*!< Min enumerator value of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Max (0x1UL) /*!< Max enumerator value of MEM21 field. */ + #define MEMCONF_POWER_CONTROL_MEM21_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM21_On (0x1UL) /*!< Power up */ + +/* MEM22 @Bit 22 : Keep the memory block MEM[22] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM22_Pos (22UL) /*!< Position of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM22_Pos) /*!< Bit mask of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Min (0x0UL) /*!< Min enumerator value of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Max (0x1UL) /*!< Max enumerator value of MEM22 field. */ + #define MEMCONF_POWER_CONTROL_MEM22_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM22_On (0x1UL) /*!< Power up */ + +/* MEM23 @Bit 23 : Keep the memory block MEM[23] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM23_Pos (23UL) /*!< Position of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM23_Pos) /*!< Bit mask of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Min (0x0UL) /*!< Min enumerator value of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Max (0x1UL) /*!< Max enumerator value of MEM23 field. */ + #define MEMCONF_POWER_CONTROL_MEM23_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM23_On (0x1UL) /*!< Power up */ + +/* MEM24 @Bit 24 : Keep the memory block MEM[24] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM24_Pos (24UL) /*!< Position of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM24_Pos) /*!< Bit mask of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Min (0x0UL) /*!< Min enumerator value of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Max (0x1UL) /*!< Max enumerator value of MEM24 field. */ + #define MEMCONF_POWER_CONTROL_MEM24_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM24_On (0x1UL) /*!< Power up */ + +/* MEM25 @Bit 25 : Keep the memory block MEM[25] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM25_Pos (25UL) /*!< Position of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM25_Pos) /*!< Bit mask of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Min (0x0UL) /*!< Min enumerator value of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Max (0x1UL) /*!< Max enumerator value of MEM25 field. */ + #define MEMCONF_POWER_CONTROL_MEM25_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM25_On (0x1UL) /*!< Power up */ + +/* MEM26 @Bit 26 : Keep the memory block MEM[26] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM26_Pos (26UL) /*!< Position of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM26_Pos) /*!< Bit mask of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Min (0x0UL) /*!< Min enumerator value of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Max (0x1UL) /*!< Max enumerator value of MEM26 field. */ + #define MEMCONF_POWER_CONTROL_MEM26_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM26_On (0x1UL) /*!< Power up */ + +/* MEM27 @Bit 27 : Keep the memory block MEM[27] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM27_Pos (27UL) /*!< Position of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM27_Pos) /*!< Bit mask of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Min (0x0UL) /*!< Min enumerator value of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Max (0x1UL) /*!< Max enumerator value of MEM27 field. */ + #define MEMCONF_POWER_CONTROL_MEM27_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM27_On (0x1UL) /*!< Power up */ + +/* MEM28 @Bit 28 : Keep the memory block MEM[28] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM28_Pos (28UL) /*!< Position of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM28_Pos) /*!< Bit mask of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Min (0x0UL) /*!< Min enumerator value of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Max (0x1UL) /*!< Max enumerator value of MEM28 field. */ + #define MEMCONF_POWER_CONTROL_MEM28_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM28_On (0x1UL) /*!< Power up */ + +/* MEM29 @Bit 29 : Keep the memory block MEM[29] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM29_Pos (29UL) /*!< Position of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM29_Pos) /*!< Bit mask of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Min (0x0UL) /*!< Min enumerator value of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Max (0x1UL) /*!< Max enumerator value of MEM29 field. */ + #define MEMCONF_POWER_CONTROL_MEM29_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM29_On (0x1UL) /*!< Power up */ + +/* MEM30 @Bit 30 : Keep the memory block MEM[30] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM30_Pos (30UL) /*!< Position of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM30_Pos) /*!< Bit mask of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Min (0x0UL) /*!< Min enumerator value of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Max (0x1UL) /*!< Max enumerator value of MEM30 field. */ + #define MEMCONF_POWER_CONTROL_MEM30_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM30_On (0x1UL) /*!< Power up */ + +/* MEM31 @Bit 31 : Keep the memory block MEM[31] on or off when in System ON mode. */ + #define MEMCONF_POWER_CONTROL_MEM31_Pos (31UL) /*!< Position of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM31_Pos) /*!< Bit mask of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Min (0x0UL) /*!< Min enumerator value of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Max (0x1UL) /*!< Max enumerator value of MEM31 field. */ + #define MEMCONF_POWER_CONTROL_MEM31_Off (0x0UL) /*!< Power down */ + #define MEMCONF_POWER_CONTROL_MEM31_On (0x1UL) /*!< Power up */ + + +/* MEMCONF_POWER_RET: RAM retention for RAM [n]. */ + #define MEMCONF_POWER_RET_ResetValue (0x00000000UL) /*!< Reset value of RET register. */ + +/* MEM0 @Bit 0 : Keep the RAM block MEM[0] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM0_Pos (0UL) /*!< Position of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Msk (0x1UL << MEMCONF_POWER_RET_MEM0_Pos) /*!< Bit mask of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Min (0x0UL) /*!< Min enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Max (0x1UL) /*!< Max enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET_MEM0_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM0_On (0x1UL) /*!< Retention on */ + +/* MEM1 @Bit 1 : Keep the RAM block MEM[1] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM1_Pos (1UL) /*!< Position of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Msk (0x1UL << MEMCONF_POWER_RET_MEM1_Pos) /*!< Bit mask of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Min (0x0UL) /*!< Min enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Max (0x1UL) /*!< Max enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET_MEM1_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM1_On (0x1UL) /*!< Retention on */ + +/* MEM2 @Bit 2 : Keep the RAM block MEM[2] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM2_Pos (2UL) /*!< Position of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Msk (0x1UL << MEMCONF_POWER_RET_MEM2_Pos) /*!< Bit mask of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Min (0x0UL) /*!< Min enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Max (0x1UL) /*!< Max enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET_MEM2_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM2_On (0x1UL) /*!< Retention on */ + +/* MEM3 @Bit 3 : Keep the RAM block MEM[3] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM3_Pos (3UL) /*!< Position of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Msk (0x1UL << MEMCONF_POWER_RET_MEM3_Pos) /*!< Bit mask of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Min (0x0UL) /*!< Min enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Max (0x1UL) /*!< Max enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET_MEM3_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM3_On (0x1UL) /*!< Retention on */ + +/* MEM4 @Bit 4 : Keep the RAM block MEM[4] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM4_Pos (4UL) /*!< Position of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Msk (0x1UL << MEMCONF_POWER_RET_MEM4_Pos) /*!< Bit mask of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Min (0x0UL) /*!< Min enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Max (0x1UL) /*!< Max enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET_MEM4_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM4_On (0x1UL) /*!< Retention on */ + +/* MEM5 @Bit 5 : Keep the RAM block MEM[5] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM5_Pos (5UL) /*!< Position of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Msk (0x1UL << MEMCONF_POWER_RET_MEM5_Pos) /*!< Bit mask of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Min (0x0UL) /*!< Min enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Max (0x1UL) /*!< Max enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET_MEM5_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM5_On (0x1UL) /*!< Retention on */ + +/* MEM6 @Bit 6 : Keep the RAM block MEM[6] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM6_Pos (6UL) /*!< Position of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Msk (0x1UL << MEMCONF_POWER_RET_MEM6_Pos) /*!< Bit mask of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Min (0x0UL) /*!< Min enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Max (0x1UL) /*!< Max enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET_MEM6_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM6_On (0x1UL) /*!< Retention on */ + +/* MEM7 @Bit 7 : Keep the RAM block MEM[7] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM7_Pos (7UL) /*!< Position of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Msk (0x1UL << MEMCONF_POWER_RET_MEM7_Pos) /*!< Bit mask of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Min (0x0UL) /*!< Min enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Max (0x1UL) /*!< Max enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET_MEM7_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM7_On (0x1UL) /*!< Retention on */ + +/* MEM8 @Bit 8 : Keep the RAM block MEM[8] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM8_Pos (8UL) /*!< Position of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Msk (0x1UL << MEMCONF_POWER_RET_MEM8_Pos) /*!< Bit mask of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Min (0x0UL) /*!< Min enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Max (0x1UL) /*!< Max enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET_MEM8_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM8_On (0x1UL) /*!< Retention on */ + +/* MEM9 @Bit 9 : Keep the RAM block MEM[9] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM9_Pos (9UL) /*!< Position of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Msk (0x1UL << MEMCONF_POWER_RET_MEM9_Pos) /*!< Bit mask of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Min (0x0UL) /*!< Min enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Max (0x1UL) /*!< Max enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET_MEM9_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM9_On (0x1UL) /*!< Retention on */ + +/* MEM10 @Bit 10 : Keep the RAM block MEM[10] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM10_Pos (10UL) /*!< Position of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Msk (0x1UL << MEMCONF_POWER_RET_MEM10_Pos) /*!< Bit mask of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Min (0x0UL) /*!< Min enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Max (0x1UL) /*!< Max enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET_MEM10_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM10_On (0x1UL) /*!< Retention on */ + +/* MEM11 @Bit 11 : Keep the RAM block MEM[11] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM11_Pos (11UL) /*!< Position of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Msk (0x1UL << MEMCONF_POWER_RET_MEM11_Pos) /*!< Bit mask of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Min (0x0UL) /*!< Min enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Max (0x1UL) /*!< Max enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET_MEM11_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM11_On (0x1UL) /*!< Retention on */ + +/* MEM12 @Bit 12 : Keep the RAM block MEM[12] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM12_Pos (12UL) /*!< Position of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Msk (0x1UL << MEMCONF_POWER_RET_MEM12_Pos) /*!< Bit mask of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Min (0x0UL) /*!< Min enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Max (0x1UL) /*!< Max enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET_MEM12_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM12_On (0x1UL) /*!< Retention on */ + +/* MEM13 @Bit 13 : Keep the RAM block MEM[13] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM13_Pos (13UL) /*!< Position of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Msk (0x1UL << MEMCONF_POWER_RET_MEM13_Pos) /*!< Bit mask of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Min (0x0UL) /*!< Min enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Max (0x1UL) /*!< Max enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET_MEM13_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM13_On (0x1UL) /*!< Retention on */ + +/* MEM14 @Bit 14 : Keep the RAM block MEM[14] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM14_Pos (14UL) /*!< Position of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Msk (0x1UL << MEMCONF_POWER_RET_MEM14_Pos) /*!< Bit mask of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Min (0x0UL) /*!< Min enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Max (0x1UL) /*!< Max enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET_MEM14_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM14_On (0x1UL) /*!< Retention on */ + +/* MEM15 @Bit 15 : Keep the RAM block MEM[15] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM15_Pos (15UL) /*!< Position of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Msk (0x1UL << MEMCONF_POWER_RET_MEM15_Pos) /*!< Bit mask of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Min (0x0UL) /*!< Min enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Max (0x1UL) /*!< Max enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET_MEM15_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM15_On (0x1UL) /*!< Retention on */ + +/* MEM16 @Bit 16 : Keep the RAM block MEM[16] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM16_Pos (16UL) /*!< Position of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Msk (0x1UL << MEMCONF_POWER_RET_MEM16_Pos) /*!< Bit mask of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Min (0x0UL) /*!< Min enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Max (0x1UL) /*!< Max enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET_MEM16_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM16_On (0x1UL) /*!< Retention on */ + +/* MEM17 @Bit 17 : Keep the RAM block MEM[17] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM17_Pos (17UL) /*!< Position of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Msk (0x1UL << MEMCONF_POWER_RET_MEM17_Pos) /*!< Bit mask of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Min (0x0UL) /*!< Min enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Max (0x1UL) /*!< Max enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET_MEM17_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM17_On (0x1UL) /*!< Retention on */ + +/* MEM18 @Bit 18 : Keep the RAM block MEM[18] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM18_Pos (18UL) /*!< Position of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Msk (0x1UL << MEMCONF_POWER_RET_MEM18_Pos) /*!< Bit mask of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Min (0x0UL) /*!< Min enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Max (0x1UL) /*!< Max enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET_MEM18_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM18_On (0x1UL) /*!< Retention on */ + +/* MEM19 @Bit 19 : Keep the RAM block MEM[19] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM19_Pos (19UL) /*!< Position of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Msk (0x1UL << MEMCONF_POWER_RET_MEM19_Pos) /*!< Bit mask of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Min (0x0UL) /*!< Min enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Max (0x1UL) /*!< Max enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET_MEM19_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM19_On (0x1UL) /*!< Retention on */ + +/* MEM20 @Bit 20 : Keep the RAM block MEM[20] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM20_Pos (20UL) /*!< Position of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Msk (0x1UL << MEMCONF_POWER_RET_MEM20_Pos) /*!< Bit mask of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Min (0x0UL) /*!< Min enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Max (0x1UL) /*!< Max enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET_MEM20_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM20_On (0x1UL) /*!< Retention on */ + +/* MEM21 @Bit 21 : Keep the RAM block MEM[21] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM21_Pos (21UL) /*!< Position of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Msk (0x1UL << MEMCONF_POWER_RET_MEM21_Pos) /*!< Bit mask of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Min (0x0UL) /*!< Min enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Max (0x1UL) /*!< Max enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET_MEM21_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM21_On (0x1UL) /*!< Retention on */ + +/* MEM22 @Bit 22 : Keep the RAM block MEM[22] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM22_Pos (22UL) /*!< Position of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Msk (0x1UL << MEMCONF_POWER_RET_MEM22_Pos) /*!< Bit mask of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Min (0x0UL) /*!< Min enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Max (0x1UL) /*!< Max enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET_MEM22_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM22_On (0x1UL) /*!< Retention on */ + +/* MEM23 @Bit 23 : Keep the RAM block MEM[23] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM23_Pos (23UL) /*!< Position of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Msk (0x1UL << MEMCONF_POWER_RET_MEM23_Pos) /*!< Bit mask of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Min (0x0UL) /*!< Min enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Max (0x1UL) /*!< Max enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET_MEM23_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM23_On (0x1UL) /*!< Retention on */ + +/* MEM24 @Bit 24 : Keep the RAM block MEM[24] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM24_Pos (24UL) /*!< Position of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Msk (0x1UL << MEMCONF_POWER_RET_MEM24_Pos) /*!< Bit mask of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Min (0x0UL) /*!< Min enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Max (0x1UL) /*!< Max enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET_MEM24_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM24_On (0x1UL) /*!< Retention on */ + +/* MEM25 @Bit 25 : Keep the RAM block MEM[25] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM25_Pos (25UL) /*!< Position of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Msk (0x1UL << MEMCONF_POWER_RET_MEM25_Pos) /*!< Bit mask of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Min (0x0UL) /*!< Min enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Max (0x1UL) /*!< Max enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET_MEM25_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM25_On (0x1UL) /*!< Retention on */ + +/* MEM26 @Bit 26 : Keep the RAM block MEM[26] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM26_Pos (26UL) /*!< Position of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Msk (0x1UL << MEMCONF_POWER_RET_MEM26_Pos) /*!< Bit mask of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Min (0x0UL) /*!< Min enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Max (0x1UL) /*!< Max enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET_MEM26_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM26_On (0x1UL) /*!< Retention on */ + +/* MEM27 @Bit 27 : Keep the RAM block MEM[27] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM27_Pos (27UL) /*!< Position of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Msk (0x1UL << MEMCONF_POWER_RET_MEM27_Pos) /*!< Bit mask of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Min (0x0UL) /*!< Min enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Max (0x1UL) /*!< Max enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET_MEM27_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM27_On (0x1UL) /*!< Retention on */ + +/* MEM28 @Bit 28 : Keep the RAM block MEM[28] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM28_Pos (28UL) /*!< Position of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Msk (0x1UL << MEMCONF_POWER_RET_MEM28_Pos) /*!< Bit mask of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Min (0x0UL) /*!< Min enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Max (0x1UL) /*!< Max enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET_MEM28_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM28_On (0x1UL) /*!< Retention on */ + +/* MEM29 @Bit 29 : Keep the RAM block MEM[29] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM29_Pos (29UL) /*!< Position of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Msk (0x1UL << MEMCONF_POWER_RET_MEM29_Pos) /*!< Bit mask of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Min (0x0UL) /*!< Min enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Max (0x1UL) /*!< Max enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET_MEM29_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM29_On (0x1UL) /*!< Retention on */ + +/* MEM30 @Bit 30 : Keep the RAM block MEM[30] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM30_Pos (30UL) /*!< Position of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Msk (0x1UL << MEMCONF_POWER_RET_MEM30_Pos) /*!< Bit mask of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Min (0x0UL) /*!< Min enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Max (0x1UL) /*!< Max enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET_MEM30_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM30_On (0x1UL) /*!< Retention on */ + +/* MEM31 @Bit 31 : Keep the RAM block MEM[31] retained when the parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET_MEM31_Pos (31UL) /*!< Position of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Msk (0x1UL << MEMCONF_POWER_RET_MEM31_Pos) /*!< Bit mask of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Min (0x0UL) /*!< Min enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Max (0x1UL) /*!< Max enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET_MEM31_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET_MEM31_On (0x1UL) /*!< Retention on */ + + +/* MEMCONF_POWER_RET2: RAM retention for the second bank in the RAM block */ + #define MEMCONF_POWER_RET2_ResetValue (0x00000000UL) /*!< Reset value of RET2 register. */ + +/* MEM0 @Bit 0 : Keep the second bank in RAM block MEM[0] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM0_Pos (0UL) /*!< Position of MEM0 field. */ + #define MEMCONF_POWER_RET2_MEM0_Msk (0x1UL << MEMCONF_POWER_RET2_MEM0_Pos) /*!< Bit mask of MEM0 field. */ + #define MEMCONF_POWER_RET2_MEM0_Min (0x0UL) /*!< Min enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET2_MEM0_Max (0x1UL) /*!< Max enumerator value of MEM0 field. */ + #define MEMCONF_POWER_RET2_MEM0_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM0_On (0x1UL) /*!< Retention on */ + +/* MEM1 @Bit 1 : Keep the second bank in RAM block MEM[1] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM1_Pos (1UL) /*!< Position of MEM1 field. */ + #define MEMCONF_POWER_RET2_MEM1_Msk (0x1UL << MEMCONF_POWER_RET2_MEM1_Pos) /*!< Bit mask of MEM1 field. */ + #define MEMCONF_POWER_RET2_MEM1_Min (0x0UL) /*!< Min enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET2_MEM1_Max (0x1UL) /*!< Max enumerator value of MEM1 field. */ + #define MEMCONF_POWER_RET2_MEM1_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM1_On (0x1UL) /*!< Retention on */ + +/* MEM2 @Bit 2 : Keep the second bank in RAM block MEM[2] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM2_Pos (2UL) /*!< Position of MEM2 field. */ + #define MEMCONF_POWER_RET2_MEM2_Msk (0x1UL << MEMCONF_POWER_RET2_MEM2_Pos) /*!< Bit mask of MEM2 field. */ + #define MEMCONF_POWER_RET2_MEM2_Min (0x0UL) /*!< Min enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET2_MEM2_Max (0x1UL) /*!< Max enumerator value of MEM2 field. */ + #define MEMCONF_POWER_RET2_MEM2_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM2_On (0x1UL) /*!< Retention on */ + +/* MEM3 @Bit 3 : Keep the second bank in RAM block MEM[3] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM3_Pos (3UL) /*!< Position of MEM3 field. */ + #define MEMCONF_POWER_RET2_MEM3_Msk (0x1UL << MEMCONF_POWER_RET2_MEM3_Pos) /*!< Bit mask of MEM3 field. */ + #define MEMCONF_POWER_RET2_MEM3_Min (0x0UL) /*!< Min enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET2_MEM3_Max (0x1UL) /*!< Max enumerator value of MEM3 field. */ + #define MEMCONF_POWER_RET2_MEM3_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM3_On (0x1UL) /*!< Retention on */ + +/* MEM4 @Bit 4 : Keep the second bank in RAM block MEM[4] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM4_Pos (4UL) /*!< Position of MEM4 field. */ + #define MEMCONF_POWER_RET2_MEM4_Msk (0x1UL << MEMCONF_POWER_RET2_MEM4_Pos) /*!< Bit mask of MEM4 field. */ + #define MEMCONF_POWER_RET2_MEM4_Min (0x0UL) /*!< Min enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET2_MEM4_Max (0x1UL) /*!< Max enumerator value of MEM4 field. */ + #define MEMCONF_POWER_RET2_MEM4_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM4_On (0x1UL) /*!< Retention on */ + +/* MEM5 @Bit 5 : Keep the second bank in RAM block MEM[5] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM5_Pos (5UL) /*!< Position of MEM5 field. */ + #define MEMCONF_POWER_RET2_MEM5_Msk (0x1UL << MEMCONF_POWER_RET2_MEM5_Pos) /*!< Bit mask of MEM5 field. */ + #define MEMCONF_POWER_RET2_MEM5_Min (0x0UL) /*!< Min enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET2_MEM5_Max (0x1UL) /*!< Max enumerator value of MEM5 field. */ + #define MEMCONF_POWER_RET2_MEM5_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM5_On (0x1UL) /*!< Retention on */ + +/* MEM6 @Bit 6 : Keep the second bank in RAM block MEM[6] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM6_Pos (6UL) /*!< Position of MEM6 field. */ + #define MEMCONF_POWER_RET2_MEM6_Msk (0x1UL << MEMCONF_POWER_RET2_MEM6_Pos) /*!< Bit mask of MEM6 field. */ + #define MEMCONF_POWER_RET2_MEM6_Min (0x0UL) /*!< Min enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET2_MEM6_Max (0x1UL) /*!< Max enumerator value of MEM6 field. */ + #define MEMCONF_POWER_RET2_MEM6_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM6_On (0x1UL) /*!< Retention on */ + +/* MEM7 @Bit 7 : Keep the second bank in RAM block MEM[7] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM7_Pos (7UL) /*!< Position of MEM7 field. */ + #define MEMCONF_POWER_RET2_MEM7_Msk (0x1UL << MEMCONF_POWER_RET2_MEM7_Pos) /*!< Bit mask of MEM7 field. */ + #define MEMCONF_POWER_RET2_MEM7_Min (0x0UL) /*!< Min enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET2_MEM7_Max (0x1UL) /*!< Max enumerator value of MEM7 field. */ + #define MEMCONF_POWER_RET2_MEM7_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM7_On (0x1UL) /*!< Retention on */ + +/* MEM8 @Bit 8 : Keep the second bank in RAM block MEM[8] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM8_Pos (8UL) /*!< Position of MEM8 field. */ + #define MEMCONF_POWER_RET2_MEM8_Msk (0x1UL << MEMCONF_POWER_RET2_MEM8_Pos) /*!< Bit mask of MEM8 field. */ + #define MEMCONF_POWER_RET2_MEM8_Min (0x0UL) /*!< Min enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET2_MEM8_Max (0x1UL) /*!< Max enumerator value of MEM8 field. */ + #define MEMCONF_POWER_RET2_MEM8_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM8_On (0x1UL) /*!< Retention on */ + +/* MEM9 @Bit 9 : Keep the second bank in RAM block MEM[9] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM9_Pos (9UL) /*!< Position of MEM9 field. */ + #define MEMCONF_POWER_RET2_MEM9_Msk (0x1UL << MEMCONF_POWER_RET2_MEM9_Pos) /*!< Bit mask of MEM9 field. */ + #define MEMCONF_POWER_RET2_MEM9_Min (0x0UL) /*!< Min enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET2_MEM9_Max (0x1UL) /*!< Max enumerator value of MEM9 field. */ + #define MEMCONF_POWER_RET2_MEM9_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM9_On (0x1UL) /*!< Retention on */ + +/* MEM10 @Bit 10 : Keep the second bank in RAM block MEM[10] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM10_Pos (10UL) /*!< Position of MEM10 field. */ + #define MEMCONF_POWER_RET2_MEM10_Msk (0x1UL << MEMCONF_POWER_RET2_MEM10_Pos) /*!< Bit mask of MEM10 field. */ + #define MEMCONF_POWER_RET2_MEM10_Min (0x0UL) /*!< Min enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET2_MEM10_Max (0x1UL) /*!< Max enumerator value of MEM10 field. */ + #define MEMCONF_POWER_RET2_MEM10_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM10_On (0x1UL) /*!< Retention on */ + +/* MEM11 @Bit 11 : Keep the second bank in RAM block MEM[11] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM11_Pos (11UL) /*!< Position of MEM11 field. */ + #define MEMCONF_POWER_RET2_MEM11_Msk (0x1UL << MEMCONF_POWER_RET2_MEM11_Pos) /*!< Bit mask of MEM11 field. */ + #define MEMCONF_POWER_RET2_MEM11_Min (0x0UL) /*!< Min enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET2_MEM11_Max (0x1UL) /*!< Max enumerator value of MEM11 field. */ + #define MEMCONF_POWER_RET2_MEM11_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM11_On (0x1UL) /*!< Retention on */ + +/* MEM12 @Bit 12 : Keep the second bank in RAM block MEM[12] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM12_Pos (12UL) /*!< Position of MEM12 field. */ + #define MEMCONF_POWER_RET2_MEM12_Msk (0x1UL << MEMCONF_POWER_RET2_MEM12_Pos) /*!< Bit mask of MEM12 field. */ + #define MEMCONF_POWER_RET2_MEM12_Min (0x0UL) /*!< Min enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET2_MEM12_Max (0x1UL) /*!< Max enumerator value of MEM12 field. */ + #define MEMCONF_POWER_RET2_MEM12_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM12_On (0x1UL) /*!< Retention on */ + +/* MEM13 @Bit 13 : Keep the second bank in RAM block MEM[13] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM13_Pos (13UL) /*!< Position of MEM13 field. */ + #define MEMCONF_POWER_RET2_MEM13_Msk (0x1UL << MEMCONF_POWER_RET2_MEM13_Pos) /*!< Bit mask of MEM13 field. */ + #define MEMCONF_POWER_RET2_MEM13_Min (0x0UL) /*!< Min enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET2_MEM13_Max (0x1UL) /*!< Max enumerator value of MEM13 field. */ + #define MEMCONF_POWER_RET2_MEM13_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM13_On (0x1UL) /*!< Retention on */ + +/* MEM14 @Bit 14 : Keep the second bank in RAM block MEM[14] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM14_Pos (14UL) /*!< Position of MEM14 field. */ + #define MEMCONF_POWER_RET2_MEM14_Msk (0x1UL << MEMCONF_POWER_RET2_MEM14_Pos) /*!< Bit mask of MEM14 field. */ + #define MEMCONF_POWER_RET2_MEM14_Min (0x0UL) /*!< Min enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET2_MEM14_Max (0x1UL) /*!< Max enumerator value of MEM14 field. */ + #define MEMCONF_POWER_RET2_MEM14_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM14_On (0x1UL) /*!< Retention on */ + +/* MEM15 @Bit 15 : Keep the second bank in RAM block MEM[15] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM15_Pos (15UL) /*!< Position of MEM15 field. */ + #define MEMCONF_POWER_RET2_MEM15_Msk (0x1UL << MEMCONF_POWER_RET2_MEM15_Pos) /*!< Bit mask of MEM15 field. */ + #define MEMCONF_POWER_RET2_MEM15_Min (0x0UL) /*!< Min enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET2_MEM15_Max (0x1UL) /*!< Max enumerator value of MEM15 field. */ + #define MEMCONF_POWER_RET2_MEM15_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM15_On (0x1UL) /*!< Retention on */ + +/* MEM16 @Bit 16 : Keep the second bank in RAM block MEM[16] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM16_Pos (16UL) /*!< Position of MEM16 field. */ + #define MEMCONF_POWER_RET2_MEM16_Msk (0x1UL << MEMCONF_POWER_RET2_MEM16_Pos) /*!< Bit mask of MEM16 field. */ + #define MEMCONF_POWER_RET2_MEM16_Min (0x0UL) /*!< Min enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET2_MEM16_Max (0x1UL) /*!< Max enumerator value of MEM16 field. */ + #define MEMCONF_POWER_RET2_MEM16_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM16_On (0x1UL) /*!< Retention on */ + +/* MEM17 @Bit 17 : Keep the second bank in RAM block MEM[17] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM17_Pos (17UL) /*!< Position of MEM17 field. */ + #define MEMCONF_POWER_RET2_MEM17_Msk (0x1UL << MEMCONF_POWER_RET2_MEM17_Pos) /*!< Bit mask of MEM17 field. */ + #define MEMCONF_POWER_RET2_MEM17_Min (0x0UL) /*!< Min enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET2_MEM17_Max (0x1UL) /*!< Max enumerator value of MEM17 field. */ + #define MEMCONF_POWER_RET2_MEM17_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM17_On (0x1UL) /*!< Retention on */ + +/* MEM18 @Bit 18 : Keep the second bank in RAM block MEM[18] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM18_Pos (18UL) /*!< Position of MEM18 field. */ + #define MEMCONF_POWER_RET2_MEM18_Msk (0x1UL << MEMCONF_POWER_RET2_MEM18_Pos) /*!< Bit mask of MEM18 field. */ + #define MEMCONF_POWER_RET2_MEM18_Min (0x0UL) /*!< Min enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET2_MEM18_Max (0x1UL) /*!< Max enumerator value of MEM18 field. */ + #define MEMCONF_POWER_RET2_MEM18_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM18_On (0x1UL) /*!< Retention on */ + +/* MEM19 @Bit 19 : Keep the second bank in RAM block MEM[19] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM19_Pos (19UL) /*!< Position of MEM19 field. */ + #define MEMCONF_POWER_RET2_MEM19_Msk (0x1UL << MEMCONF_POWER_RET2_MEM19_Pos) /*!< Bit mask of MEM19 field. */ + #define MEMCONF_POWER_RET2_MEM19_Min (0x0UL) /*!< Min enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET2_MEM19_Max (0x1UL) /*!< Max enumerator value of MEM19 field. */ + #define MEMCONF_POWER_RET2_MEM19_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM19_On (0x1UL) /*!< Retention on */ + +/* MEM20 @Bit 20 : Keep the second bank in RAM block MEM[20] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM20_Pos (20UL) /*!< Position of MEM20 field. */ + #define MEMCONF_POWER_RET2_MEM20_Msk (0x1UL << MEMCONF_POWER_RET2_MEM20_Pos) /*!< Bit mask of MEM20 field. */ + #define MEMCONF_POWER_RET2_MEM20_Min (0x0UL) /*!< Min enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET2_MEM20_Max (0x1UL) /*!< Max enumerator value of MEM20 field. */ + #define MEMCONF_POWER_RET2_MEM20_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM20_On (0x1UL) /*!< Retention on */ + +/* MEM21 @Bit 21 : Keep the second bank in RAM block MEM[21] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM21_Pos (21UL) /*!< Position of MEM21 field. */ + #define MEMCONF_POWER_RET2_MEM21_Msk (0x1UL << MEMCONF_POWER_RET2_MEM21_Pos) /*!< Bit mask of MEM21 field. */ + #define MEMCONF_POWER_RET2_MEM21_Min (0x0UL) /*!< Min enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET2_MEM21_Max (0x1UL) /*!< Max enumerator value of MEM21 field. */ + #define MEMCONF_POWER_RET2_MEM21_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM21_On (0x1UL) /*!< Retention on */ + +/* MEM22 @Bit 22 : Keep the second bank in RAM block MEM[22] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM22_Pos (22UL) /*!< Position of MEM22 field. */ + #define MEMCONF_POWER_RET2_MEM22_Msk (0x1UL << MEMCONF_POWER_RET2_MEM22_Pos) /*!< Bit mask of MEM22 field. */ + #define MEMCONF_POWER_RET2_MEM22_Min (0x0UL) /*!< Min enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET2_MEM22_Max (0x1UL) /*!< Max enumerator value of MEM22 field. */ + #define MEMCONF_POWER_RET2_MEM22_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM22_On (0x1UL) /*!< Retention on */ + +/* MEM23 @Bit 23 : Keep the second bank in RAM block MEM[23] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM23_Pos (23UL) /*!< Position of MEM23 field. */ + #define MEMCONF_POWER_RET2_MEM23_Msk (0x1UL << MEMCONF_POWER_RET2_MEM23_Pos) /*!< Bit mask of MEM23 field. */ + #define MEMCONF_POWER_RET2_MEM23_Min (0x0UL) /*!< Min enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET2_MEM23_Max (0x1UL) /*!< Max enumerator value of MEM23 field. */ + #define MEMCONF_POWER_RET2_MEM23_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM23_On (0x1UL) /*!< Retention on */ + +/* MEM24 @Bit 24 : Keep the second bank in RAM block MEM[24] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM24_Pos (24UL) /*!< Position of MEM24 field. */ + #define MEMCONF_POWER_RET2_MEM24_Msk (0x1UL << MEMCONF_POWER_RET2_MEM24_Pos) /*!< Bit mask of MEM24 field. */ + #define MEMCONF_POWER_RET2_MEM24_Min (0x0UL) /*!< Min enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET2_MEM24_Max (0x1UL) /*!< Max enumerator value of MEM24 field. */ + #define MEMCONF_POWER_RET2_MEM24_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM24_On (0x1UL) /*!< Retention on */ + +/* MEM25 @Bit 25 : Keep the second bank in RAM block MEM[25] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM25_Pos (25UL) /*!< Position of MEM25 field. */ + #define MEMCONF_POWER_RET2_MEM25_Msk (0x1UL << MEMCONF_POWER_RET2_MEM25_Pos) /*!< Bit mask of MEM25 field. */ + #define MEMCONF_POWER_RET2_MEM25_Min (0x0UL) /*!< Min enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET2_MEM25_Max (0x1UL) /*!< Max enumerator value of MEM25 field. */ + #define MEMCONF_POWER_RET2_MEM25_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM25_On (0x1UL) /*!< Retention on */ + +/* MEM26 @Bit 26 : Keep the second bank in RAM block MEM[26] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM26_Pos (26UL) /*!< Position of MEM26 field. */ + #define MEMCONF_POWER_RET2_MEM26_Msk (0x1UL << MEMCONF_POWER_RET2_MEM26_Pos) /*!< Bit mask of MEM26 field. */ + #define MEMCONF_POWER_RET2_MEM26_Min (0x0UL) /*!< Min enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET2_MEM26_Max (0x1UL) /*!< Max enumerator value of MEM26 field. */ + #define MEMCONF_POWER_RET2_MEM26_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM26_On (0x1UL) /*!< Retention on */ + +/* MEM27 @Bit 27 : Keep the second bank in RAM block MEM[27] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM27_Pos (27UL) /*!< Position of MEM27 field. */ + #define MEMCONF_POWER_RET2_MEM27_Msk (0x1UL << MEMCONF_POWER_RET2_MEM27_Pos) /*!< Bit mask of MEM27 field. */ + #define MEMCONF_POWER_RET2_MEM27_Min (0x0UL) /*!< Min enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET2_MEM27_Max (0x1UL) /*!< Max enumerator value of MEM27 field. */ + #define MEMCONF_POWER_RET2_MEM27_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM27_On (0x1UL) /*!< Retention on */ + +/* MEM28 @Bit 28 : Keep the second bank in RAM block MEM[28] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM28_Pos (28UL) /*!< Position of MEM28 field. */ + #define MEMCONF_POWER_RET2_MEM28_Msk (0x1UL << MEMCONF_POWER_RET2_MEM28_Pos) /*!< Bit mask of MEM28 field. */ + #define MEMCONF_POWER_RET2_MEM28_Min (0x0UL) /*!< Min enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET2_MEM28_Max (0x1UL) /*!< Max enumerator value of MEM28 field. */ + #define MEMCONF_POWER_RET2_MEM28_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM28_On (0x1UL) /*!< Retention on */ + +/* MEM29 @Bit 29 : Keep the second bank in RAM block MEM[29] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM29_Pos (29UL) /*!< Position of MEM29 field. */ + #define MEMCONF_POWER_RET2_MEM29_Msk (0x1UL << MEMCONF_POWER_RET2_MEM29_Pos) /*!< Bit mask of MEM29 field. */ + #define MEMCONF_POWER_RET2_MEM29_Min (0x0UL) /*!< Min enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET2_MEM29_Max (0x1UL) /*!< Max enumerator value of MEM29 field. */ + #define MEMCONF_POWER_RET2_MEM29_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM29_On (0x1UL) /*!< Retention on */ + +/* MEM30 @Bit 30 : Keep the second bank in RAM block MEM[30] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM30_Pos (30UL) /*!< Position of MEM30 field. */ + #define MEMCONF_POWER_RET2_MEM30_Msk (0x1UL << MEMCONF_POWER_RET2_MEM30_Pos) /*!< Bit mask of MEM30 field. */ + #define MEMCONF_POWER_RET2_MEM30_Min (0x0UL) /*!< Min enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET2_MEM30_Max (0x1UL) /*!< Max enumerator value of MEM30 field. */ + #define MEMCONF_POWER_RET2_MEM30_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM30_On (0x1UL) /*!< Retention on */ + +/* MEM31 @Bit 31 : Keep the second bank in RAM block MEM[31] retained when parent power domain of the RAM is off. */ + #define MEMCONF_POWER_RET2_MEM31_Pos (31UL) /*!< Position of MEM31 field. */ + #define MEMCONF_POWER_RET2_MEM31_Msk (0x1UL << MEMCONF_POWER_RET2_MEM31_Pos) /*!< Bit mask of MEM31 field. */ + #define MEMCONF_POWER_RET2_MEM31_Min (0x0UL) /*!< Min enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET2_MEM31_Max (0x1UL) /*!< Max enumerator value of MEM31 field. */ + #define MEMCONF_POWER_RET2_MEM31_Off (0x0UL) /*!< Retention off */ + #define MEMCONF_POWER_RET2_MEM31_On (0x1UL) /*!< Retention on */ + + + +/* ================================================== Struct MEMCONF_REPAIR ================================================== */ +/** + * @brief REPAIR [MEMCONF_REPAIR] (unspecified) + */ +typedef struct { + __IOM uint32_t BITLINE; /*!< (@ 0x00000000) Repair configuration for RAM blocks. */ +} NRF_MEMCONF_REPAIR_Type; /*!< Size = 4 (0x004) */ + #define MEMCONF_REPAIR_MaxCount (192UL) /*!< Size of REPAIR[192] array. */ + #define MEMCONF_REPAIR_MaxIndex (191UL) /*!< Max index of REPAIR[192] array. */ + #define MEMCONF_REPAIR_MinIndex (0UL) /*!< Min index of REPAIR[192] array. */ + +/* MEMCONF_REPAIR_BITLINE: Repair configuration for RAM blocks. */ + #define MEMCONF_REPAIR_BITLINE_ResetValue (0x00000000UL) /*!< Reset value of BITLINE register. */ + +/* ADDR @Bits 0..6 : Repair address of the bitline */ + #define MEMCONF_REPAIR_BITLINE_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define MEMCONF_REPAIR_BITLINE_ADDR_Msk (0x7FUL << MEMCONF_REPAIR_BITLINE_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* EN @Bit 31 : Enable bitline repair */ + #define MEMCONF_REPAIR_BITLINE_EN_Pos (31UL) /*!< Position of EN field. */ + #define MEMCONF_REPAIR_BITLINE_EN_Msk (0x1UL << MEMCONF_REPAIR_BITLINE_EN_Pos) /*!< Bit mask of EN field. */ + #define MEMCONF_REPAIR_BITLINE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MEMCONF_REPAIR_BITLINE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MEMCONF_REPAIR_BITLINE_EN_Disabled (0x0UL) /*!< Repair disabled. */ + #define MEMCONF_REPAIR_BITLINE_EN_Enabled (0x1UL) /*!< Repair enabled. */ + + + +/* ================================================ Struct MEMCONF_BLOCKTYPE ================================================= */ +/** + * @brief BLOCKTYPE [MEMCONF_BLOCKTYPE] (unspecified) + */ +typedef struct { + __IOM uint32_t TRIM; /*!< (@ 0x00000000) Trim configuration for the memory block types. */ +} NRF_MEMCONF_BLOCKTYPE_Type; /*!< Size = 4 (0x004) */ + #define MEMCONF_BLOCKTYPE_MaxCount (64UL) /*!< Size of BLOCKTYPE[64] array. */ + #define MEMCONF_BLOCKTYPE_MaxIndex (63UL) /*!< Max index of BLOCKTYPE[64] array. */ + #define MEMCONF_BLOCKTYPE_MinIndex (0UL) /*!< Min index of BLOCKTYPE[64] array. */ + +/* MEMCONF_BLOCKTYPE_TRIM: Trim configuration for the memory block types. */ + #define MEMCONF_BLOCKTYPE_TRIM_ResetValue (0x00000000UL) /*!< Reset value of TRIM register. */ + +/* MEMTRIM0 @Bit 0 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos (0UL) /*!< Position of MEMTRIM0 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos) /*!< Bit mask of MEMTRIM0 field. */ + +/* MEMTRIM1 @Bit 1 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Pos (1UL) /*!< Position of MEMTRIM1 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Pos) /*!< Bit mask of MEMTRIM1 field. */ + +/* MEMTRIM2 @Bit 2 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Pos (2UL) /*!< Position of MEMTRIM2 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Pos) /*!< Bit mask of MEMTRIM2 field. */ + +/* MEMTRIM3 @Bit 3 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Pos (3UL) /*!< Position of MEMTRIM3 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Pos) /*!< Bit mask of MEMTRIM3 field. */ + +/* MEMTRIM4 @Bit 4 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Pos (4UL) /*!< Position of MEMTRIM4 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Pos) /*!< Bit mask of MEMTRIM4 field. */ + +/* MEMTRIM5 @Bit 5 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Pos (5UL) /*!< Position of MEMTRIM5 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Pos) /*!< Bit mask of MEMTRIM5 field. */ + +/* MEMTRIM6 @Bit 6 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Pos (6UL) /*!< Position of MEMTRIM6 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Pos) /*!< Bit mask of MEMTRIM6 field. */ + +/* MEMTRIM7 @Bit 7 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Pos (7UL) /*!< Position of MEMTRIM7 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Pos) /*!< Bit mask of MEMTRIM7 field. */ + +/* MEMTRIM8 @Bit 8 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Pos (8UL) /*!< Position of MEMTRIM8 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Pos) /*!< Bit mask of MEMTRIM8 field. */ + +/* MEMTRIM9 @Bit 9 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Pos (9UL) /*!< Position of MEMTRIM9 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Pos) /*!< Bit mask of MEMTRIM9 field. */ + +/* MEMTRIM10 @Bit 10 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Pos (10UL) /*!< Position of MEMTRIM10 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Pos) /*!< Bit mask of MEMTRIM10 + field.*/ + +/* MEMTRIM11 @Bit 11 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Pos (11UL) /*!< Position of MEMTRIM11 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Pos) /*!< Bit mask of MEMTRIM11 + field.*/ + +/* MEMTRIM12 @Bit 12 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Pos (12UL) /*!< Position of MEMTRIM12 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Pos) /*!< Bit mask of MEMTRIM12 + field.*/ + +/* MEMTRIM13 @Bit 13 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Pos (13UL) /*!< Position of MEMTRIM13 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Pos) /*!< Bit mask of MEMTRIM13 + field.*/ + +/* MEMTRIM14 @Bit 14 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Pos (14UL) /*!< Position of MEMTRIM14 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Pos) /*!< Bit mask of MEMTRIM14 + field.*/ + +/* MEMTRIM15 @Bit 15 : Read/write margin trim. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Pos (15UL) /*!< Position of MEMTRIM15 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Pos) /*!< Bit mask of MEMTRIM15 + field.*/ + +/* MEMRETTRIM0 @Bit 16 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos (16UL) /*!< Position of MEMRETTRIM0 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos) /*!< Bit mask of MEMRETTRIM0 + field.*/ + +/* MEMRETTRIM1 @Bit 17 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Pos (17UL) /*!< Position of MEMRETTRIM1 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Pos) /*!< Bit mask of MEMRETTRIM1 + field.*/ + +/* MEMRETTRIM2 @Bit 18 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Pos (18UL) /*!< Position of MEMRETTRIM2 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Pos) /*!< Bit mask of MEMRETTRIM2 + field.*/ + +/* MEMRETTRIM3 @Bit 19 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Pos (19UL) /*!< Position of MEMRETTRIM3 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Pos) /*!< Bit mask of MEMRETTRIM3 + field.*/ + +/* MEMRETTRIM4 @Bit 20 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Pos (20UL) /*!< Position of MEMRETTRIM4 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Pos) /*!< Bit mask of MEMRETTRIM4 + field.*/ + +/* MEMRETTRIM5 @Bit 21 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Pos (21UL) /*!< Position of MEMRETTRIM5 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Pos) /*!< Bit mask of MEMRETTRIM5 + field.*/ + +/* MEMRETTRIM6 @Bit 22 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Pos (22UL) /*!< Position of MEMRETTRIM6 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Pos) /*!< Bit mask of MEMRETTRIM6 + field.*/ + +/* MEMRETTRIM7 @Bit 23 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Pos (23UL) /*!< Position of MEMRETTRIM7 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Pos) /*!< Bit mask of MEMRETTRIM7 + field.*/ + +/* MEMRETTRIM8 @Bit 24 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Pos (24UL) /*!< Position of MEMRETTRIM8 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Pos) /*!< Bit mask of MEMRETTRIM8 + field.*/ + +/* MEMRETTRIM9 @Bit 25 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Pos (25UL) /*!< Position of MEMRETTRIM9 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Pos) /*!< Bit mask of MEMRETTRIM9 + field.*/ + +/* MEMRETTRIM10 @Bit 26 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Pos (26UL) /*!< Position of MEMRETTRIM10 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Pos) /*!< Bit mask of + MEMRETTRIM10 field.*/ + +/* MEMRETTRIM11 @Bit 27 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Pos (27UL) /*!< Position of MEMRETTRIM11 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Pos) /*!< Bit mask of + MEMRETTRIM11 field.*/ + +/* MEMRETTRIM12 @Bit 28 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Pos (28UL) /*!< Position of MEMRETTRIM12 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Pos) /*!< Bit mask of + MEMRETTRIM12 field.*/ + +/* MEMRETTRIM13 @Bit 29 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Pos (29UL) /*!< Position of MEMRETTRIM13 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Pos) /*!< Bit mask of + MEMRETTRIM13 field.*/ + +/* MEMRETTRIM14 @Bit 30 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Pos (30UL) /*!< Position of MEMRETTRIM14 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Pos) /*!< Bit mask of + MEMRETTRIM14 field.*/ + +/* MEMRETTRIM15 @Bit 31 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Pos (31UL) /*!< Position of MEMRETTRIM15 field. */ + #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Pos) /*!< Bit mask of + MEMRETTRIM15 field.*/ + + +/* ===================================================== Struct MEMCONF ====================================================== */ +/** + * @brief Memory configuration + */ + typedef struct { /*!< MEMCONF Structure */ + __IM uint32_t RESERVED[320]; + __IOM NRF_MEMCONF_POWER_Type POWER[2]; /*!< (@ 0x00000500) (unspecified) */ + __IM uint32_t RESERVED1[56]; + __IOM NRF_MEMCONF_REPAIR_Type REPAIR[192]; /*!< (@ 0x00000600) (unspecified) */ + __IOM NRF_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[64]; /*!< (@ 0x00000900) (unspecified) */ + } NRF_MEMCONF_Type; /*!< Size = 2560 (0xA00) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MPC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct MPC_MEMACCERR =================================================== */ +/** + * @brief MEMACCERR [MPC_MEMACCERR] Memory Access Error status registers + */ +typedef struct { + __IM uint32_t ADDRESS; /*!< (@ 0x00000000) Target Address of Memory Access Error. Register content + won't be changed as long as MEMACCERR event is active.*/ + __IM uint32_t INFO; /*!< (@ 0x00000004) Access information for the transaction that triggered a + memory access error. Register content won't be changed + as long as MEMACCERR event is active.*/ +} NRF_MPC_MEMACCERR_Type; /*!< Size = 8 (0x008) */ + +/* MPC_MEMACCERR_ADDRESS: Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is + active. */ + + #define MPC_MEMACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..31 : Target address for erroneous access */ + #define MPC_MEMACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MPC_MEMACCERR_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MPC_MEMACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/ + + +/* MPC_MEMACCERR_INFO: Access information for the transaction that triggered a memory access error. Register content won't be + changed as long as MEMACCERR event is active. */ + + #define MPC_MEMACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* OWNERID @Bits 0..3 : Owner identifier of the erroneous access */ + #define MPC_MEMACCERR_INFO_OWNERID_Pos (0UL) /*!< Position of OWNERID field. */ + #define MPC_MEMACCERR_INFO_OWNERID_Msk (0xFUL << MPC_MEMACCERR_INFO_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define MPC_MEMACCERR_INFO_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define MPC_MEMACCERR_INFO_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + +/* MASTERPORT @Bits 4..8 : Master port where erroneous access is detected */ + #define MPC_MEMACCERR_INFO_MASTERPORT_Pos (4UL) /*!< Position of MASTERPORT field. */ + #define MPC_MEMACCERR_INFO_MASTERPORT_Msk (0x1FUL << MPC_MEMACCERR_INFO_MASTERPORT_Pos) /*!< Bit mask of MASTERPORT field. */ + #define MPC_MEMACCERR_INFO_MASTERPORT_Min (0x00UL) /*!< Min value of MASTERPORT field. */ + #define MPC_MEMACCERR_INFO_MASTERPORT_Max (0x1FUL) /*!< Max size of MASTERPORT field. */ + +/* READ @Bit 12 : Read bit of bus access */ + #define MPC_MEMACCERR_INFO_READ_Pos (12UL) /*!< Position of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Msk (0x1UL << MPC_MEMACCERR_INFO_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_MEMACCERR_INFO_READ_Set (0x1UL) /*!< Read access bit was set */ + #define MPC_MEMACCERR_INFO_READ_NotSet (0x0UL) /*!< Read access bit was not set */ + +/* WRITE @Bit 13 : Write bit of bus access */ + #define MPC_MEMACCERR_INFO_WRITE_Pos (13UL) /*!< Position of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Msk (0x1UL << MPC_MEMACCERR_INFO_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_MEMACCERR_INFO_WRITE_Set (0x1UL) /*!< Write access bit was set */ + #define MPC_MEMACCERR_INFO_WRITE_NotSet (0x0UL) /*!< Write access bit was not set */ + +/* EXECUTE @Bit 14 : Execute bit of bus access */ + #define MPC_MEMACCERR_INFO_EXECUTE_Pos (14UL) /*!< Position of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Msk (0x1UL << MPC_MEMACCERR_INFO_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_MEMACCERR_INFO_EXECUTE_Set (0x1UL) /*!< Execute access bit was set */ + #define MPC_MEMACCERR_INFO_EXECUTE_NotSet (0x0UL) /*!< Execute access bit was not set */ + +/* SECURE @Bit 15 : Secure bit of bus access */ + #define MPC_MEMACCERR_INFO_SECURE_Pos (15UL) /*!< Position of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Msk (0x1UL << MPC_MEMACCERR_INFO_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define MPC_MEMACCERR_INFO_SECURE_Set (0x1UL) /*!< Secure access bit was set */ + #define MPC_MEMACCERR_INFO_SECURE_NotSet (0x0UL) /*!< Secure access bit was not set */ + +/* ERRORSOURCE @Bit 16 : Source of memory access error */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Pos (16UL) /*!< Position of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Msk (0x1UL << MPC_MEMACCERR_INFO_ERRORSOURCE_Pos) /*!< Bit mask of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Min (0x0UL) /*!< Min enumerator value of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Max (0x1UL) /*!< Max enumerator value of ERRORSOURCE field. */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_MPC (0x1UL) /*!< Error was triggered by MPC module */ + #define MPC_MEMACCERR_INFO_ERRORSOURCE_Slave (0x0UL) /*!< Error was triggered by an AXI slave */ + + + +/* ================================================= Struct MPC_GLOBALSLAVE ================================================== */ +/** + * @brief GLOBALSLAVE [MPC_GLOBALSLAVE] Global slave master port connection information + */ +typedef struct { + __IOM uint32_t MASTERPORT; /*!< (@ 0x00000000) Global slave connection information for master port */ + __IOM uint32_t LOCK; /*!< (@ 0x00000004) Lock global slave registers */ +} NRF_MPC_GLOBALSLAVE_Type; /*!< Size = 8 (0x008) */ + +/* MPC_GLOBALSLAVE_MASTERPORT: Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register. */ + +/* CONNECTION0 @Bit 0 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Pos (0UL) /*!< Position of CONNECTION0 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Pos) /*!< Bit mask of + CONNECTION0 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Min (0x0UL) /*!< Min enumerator value of CONNECTION0 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Max (0x1UL) /*!< Max enumerator value of CONNECTION0 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Disabled (0x0UL) /*!< Master port 0 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Enabled (0x1UL) /*!< Master port 0 connection to global slave is enabled */ + +/* CONNECTION1 @Bit 1 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Pos (1UL) /*!< Position of CONNECTION1 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Pos) /*!< Bit mask of + CONNECTION1 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Min (0x0UL) /*!< Min enumerator value of CONNECTION1 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Max (0x1UL) /*!< Max enumerator value of CONNECTION1 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Disabled (0x0UL) /*!< Master port 1 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Enabled (0x1UL) /*!< Master port 1 connection to global slave is enabled */ + +/* CONNECTION2 @Bit 2 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Pos (2UL) /*!< Position of CONNECTION2 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Pos) /*!< Bit mask of + CONNECTION2 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Min (0x0UL) /*!< Min enumerator value of CONNECTION2 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Max (0x1UL) /*!< Max enumerator value of CONNECTION2 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Disabled (0x0UL) /*!< Master port 2 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Enabled (0x1UL) /*!< Master port 2 connection to global slave is enabled */ + +/* CONNECTION3 @Bit 3 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Pos (3UL) /*!< Position of CONNECTION3 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Pos) /*!< Bit mask of + CONNECTION3 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Min (0x0UL) /*!< Min enumerator value of CONNECTION3 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Max (0x1UL) /*!< Max enumerator value of CONNECTION3 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Disabled (0x0UL) /*!< Master port 3 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Enabled (0x1UL) /*!< Master port 3 connection to global slave is enabled */ + +/* CONNECTION4 @Bit 4 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Pos (4UL) /*!< Position of CONNECTION4 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Pos) /*!< Bit mask of + CONNECTION4 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Min (0x0UL) /*!< Min enumerator value of CONNECTION4 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Max (0x1UL) /*!< Max enumerator value of CONNECTION4 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Disabled (0x0UL) /*!< Master port 4 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Enabled (0x1UL) /*!< Master port 4 connection to global slave is enabled */ + +/* CONNECTION5 @Bit 5 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Pos (5UL) /*!< Position of CONNECTION5 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Pos) /*!< Bit mask of + CONNECTION5 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Min (0x0UL) /*!< Min enumerator value of CONNECTION5 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Max (0x1UL) /*!< Max enumerator value of CONNECTION5 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Disabled (0x0UL) /*!< Master port 5 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Enabled (0x1UL) /*!< Master port 5 connection to global slave is enabled */ + +/* CONNECTION6 @Bit 6 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Pos (6UL) /*!< Position of CONNECTION6 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Pos) /*!< Bit mask of + CONNECTION6 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Min (0x0UL) /*!< Min enumerator value of CONNECTION6 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Max (0x1UL) /*!< Max enumerator value of CONNECTION6 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Disabled (0x0UL) /*!< Master port 6 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Enabled (0x1UL) /*!< Master port 6 connection to global slave is enabled */ + +/* CONNECTION7 @Bit 7 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Pos (7UL) /*!< Position of CONNECTION7 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Pos) /*!< Bit mask of + CONNECTION7 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Min (0x0UL) /*!< Min enumerator value of CONNECTION7 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Max (0x1UL) /*!< Max enumerator value of CONNECTION7 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Disabled (0x0UL) /*!< Master port 7 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Enabled (0x1UL) /*!< Master port 7 connection to global slave is enabled */ + +/* CONNECTION8 @Bit 8 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Pos (8UL) /*!< Position of CONNECTION8 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Pos) /*!< Bit mask of + CONNECTION8 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Min (0x0UL) /*!< Min enumerator value of CONNECTION8 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Max (0x1UL) /*!< Max enumerator value of CONNECTION8 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Disabled (0x0UL) /*!< Master port 8 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Enabled (0x1UL) /*!< Master port 8 connection to global slave is enabled */ + +/* CONNECTION9 @Bit 9 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Pos (9UL) /*!< Position of CONNECTION9 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Pos) /*!< Bit mask of + CONNECTION9 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Min (0x0UL) /*!< Min enumerator value of CONNECTION9 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Max (0x1UL) /*!< Max enumerator value of CONNECTION9 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Disabled (0x0UL) /*!< Master port 9 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Enabled (0x1UL) /*!< Master port 9 connection to global slave is enabled */ + +/* CONNECTION10 @Bit 10 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Pos (10UL) /*!< Position of CONNECTION10 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Pos) /*!< Bit mask of + CONNECTION10 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Min (0x0UL) /*!< Min enumerator value of CONNECTION10 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Max (0x1UL) /*!< Max enumerator value of CONNECTION10 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Disabled (0x0UL) /*!< Master port 10 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Enabled (0x1UL) /*!< Master port 10 connection to global slave is enabled */ + +/* CONNECTION11 @Bit 11 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Pos (11UL) /*!< Position of CONNECTION11 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Pos) /*!< Bit mask of + CONNECTION11 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Min (0x0UL) /*!< Min enumerator value of CONNECTION11 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Max (0x1UL) /*!< Max enumerator value of CONNECTION11 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Disabled (0x0UL) /*!< Master port 11 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Enabled (0x1UL) /*!< Master port 11 connection to global slave is enabled */ + +/* CONNECTION12 @Bit 12 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Pos (12UL) /*!< Position of CONNECTION12 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Pos) /*!< Bit mask of + CONNECTION12 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Min (0x0UL) /*!< Min enumerator value of CONNECTION12 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Max (0x1UL) /*!< Max enumerator value of CONNECTION12 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Disabled (0x0UL) /*!< Master port 12 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Enabled (0x1UL) /*!< Master port 12 connection to global slave is enabled */ + +/* CONNECTION13 @Bit 13 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Pos (13UL) /*!< Position of CONNECTION13 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Pos) /*!< Bit mask of + CONNECTION13 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Min (0x0UL) /*!< Min enumerator value of CONNECTION13 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Max (0x1UL) /*!< Max enumerator value of CONNECTION13 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Disabled (0x0UL) /*!< Master port 13 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Enabled (0x1UL) /*!< Master port 13 connection to global slave is enabled */ + +/* CONNECTION14 @Bit 14 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Pos (14UL) /*!< Position of CONNECTION14 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Pos) /*!< Bit mask of + CONNECTION14 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Min (0x0UL) /*!< Min enumerator value of CONNECTION14 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Max (0x1UL) /*!< Max enumerator value of CONNECTION14 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Disabled (0x0UL) /*!< Master port 14 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Enabled (0x1UL) /*!< Master port 14 connection to global slave is enabled */ + +/* CONNECTION15 @Bit 15 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Pos (15UL) /*!< Position of CONNECTION15 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Pos) /*!< Bit mask of + CONNECTION15 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Min (0x0UL) /*!< Min enumerator value of CONNECTION15 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Max (0x1UL) /*!< Max enumerator value of CONNECTION15 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Disabled (0x0UL) /*!< Master port 15 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Enabled (0x1UL) /*!< Master port 15 connection to global slave is enabled */ + +/* CONNECTION16 @Bit 16 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Pos (16UL) /*!< Position of CONNECTION16 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Pos) /*!< Bit mask of + CONNECTION16 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Min (0x0UL) /*!< Min enumerator value of CONNECTION16 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Max (0x1UL) /*!< Max enumerator value of CONNECTION16 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Disabled (0x0UL) /*!< Master port 16 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Enabled (0x1UL) /*!< Master port 16 connection to global slave is enabled */ + +/* CONNECTION17 @Bit 17 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Pos (17UL) /*!< Position of CONNECTION17 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Pos) /*!< Bit mask of + CONNECTION17 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Min (0x0UL) /*!< Min enumerator value of CONNECTION17 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Max (0x1UL) /*!< Max enumerator value of CONNECTION17 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Disabled (0x0UL) /*!< Master port 17 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Enabled (0x1UL) /*!< Master port 17 connection to global slave is enabled */ + +/* CONNECTION18 @Bit 18 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Pos (18UL) /*!< Position of CONNECTION18 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Pos) /*!< Bit mask of + CONNECTION18 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Min (0x0UL) /*!< Min enumerator value of CONNECTION18 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Max (0x1UL) /*!< Max enumerator value of CONNECTION18 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Disabled (0x0UL) /*!< Master port 18 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Enabled (0x1UL) /*!< Master port 18 connection to global slave is enabled */ + +/* CONNECTION19 @Bit 19 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Pos (19UL) /*!< Position of CONNECTION19 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Pos) /*!< Bit mask of + CONNECTION19 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Min (0x0UL) /*!< Min enumerator value of CONNECTION19 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Max (0x1UL) /*!< Max enumerator value of CONNECTION19 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Disabled (0x0UL) /*!< Master port 19 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Enabled (0x1UL) /*!< Master port 19 connection to global slave is enabled */ + +/* CONNECTION20 @Bit 20 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Pos (20UL) /*!< Position of CONNECTION20 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Pos) /*!< Bit mask of + CONNECTION20 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Min (0x0UL) /*!< Min enumerator value of CONNECTION20 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Max (0x1UL) /*!< Max enumerator value of CONNECTION20 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Disabled (0x0UL) /*!< Master port 20 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Enabled (0x1UL) /*!< Master port 20 connection to global slave is enabled */ + +/* CONNECTION21 @Bit 21 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Pos (21UL) /*!< Position of CONNECTION21 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Pos) /*!< Bit mask of + CONNECTION21 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Min (0x0UL) /*!< Min enumerator value of CONNECTION21 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Max (0x1UL) /*!< Max enumerator value of CONNECTION21 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Disabled (0x0UL) /*!< Master port 21 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Enabled (0x1UL) /*!< Master port 21 connection to global slave is enabled */ + +/* CONNECTION22 @Bit 22 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Pos (22UL) /*!< Position of CONNECTION22 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Pos) /*!< Bit mask of + CONNECTION22 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Min (0x0UL) /*!< Min enumerator value of CONNECTION22 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Max (0x1UL) /*!< Max enumerator value of CONNECTION22 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Disabled (0x0UL) /*!< Master port 22 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Enabled (0x1UL) /*!< Master port 22 connection to global slave is enabled */ + +/* CONNECTION23 @Bit 23 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Pos (23UL) /*!< Position of CONNECTION23 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Pos) /*!< Bit mask of + CONNECTION23 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Min (0x0UL) /*!< Min enumerator value of CONNECTION23 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Max (0x1UL) /*!< Max enumerator value of CONNECTION23 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Disabled (0x0UL) /*!< Master port 23 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Enabled (0x1UL) /*!< Master port 23 connection to global slave is enabled */ + +/* CONNECTION24 @Bit 24 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Pos (24UL) /*!< Position of CONNECTION24 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Pos) /*!< Bit mask of + CONNECTION24 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Min (0x0UL) /*!< Min enumerator value of CONNECTION24 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Max (0x1UL) /*!< Max enumerator value of CONNECTION24 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Disabled (0x0UL) /*!< Master port 24 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Enabled (0x1UL) /*!< Master port 24 connection to global slave is enabled */ + +/* CONNECTION25 @Bit 25 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Pos (25UL) /*!< Position of CONNECTION25 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Pos) /*!< Bit mask of + CONNECTION25 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Min (0x0UL) /*!< Min enumerator value of CONNECTION25 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Max (0x1UL) /*!< Max enumerator value of CONNECTION25 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Disabled (0x0UL) /*!< Master port 25 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Enabled (0x1UL) /*!< Master port 25 connection to global slave is enabled */ + +/* CONNECTION26 @Bit 26 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Pos (26UL) /*!< Position of CONNECTION26 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Pos) /*!< Bit mask of + CONNECTION26 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Min (0x0UL) /*!< Min enumerator value of CONNECTION26 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Max (0x1UL) /*!< Max enumerator value of CONNECTION26 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Disabled (0x0UL) /*!< Master port 26 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Enabled (0x1UL) /*!< Master port 26 connection to global slave is enabled */ + +/* CONNECTION27 @Bit 27 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Pos (27UL) /*!< Position of CONNECTION27 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Pos) /*!< Bit mask of + CONNECTION27 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Min (0x0UL) /*!< Min enumerator value of CONNECTION27 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Max (0x1UL) /*!< Max enumerator value of CONNECTION27 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Disabled (0x0UL) /*!< Master port 27 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Enabled (0x1UL) /*!< Master port 27 connection to global slave is enabled */ + +/* CONNECTION28 @Bit 28 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Pos (28UL) /*!< Position of CONNECTION28 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Pos) /*!< Bit mask of + CONNECTION28 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Min (0x0UL) /*!< Min enumerator value of CONNECTION28 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Max (0x1UL) /*!< Max enumerator value of CONNECTION28 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Disabled (0x0UL) /*!< Master port 28 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Enabled (0x1UL) /*!< Master port 28 connection to global slave is enabled */ + +/* CONNECTION29 @Bit 29 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Pos (29UL) /*!< Position of CONNECTION29 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Pos) /*!< Bit mask of + CONNECTION29 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Min (0x0UL) /*!< Min enumerator value of CONNECTION29 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Max (0x1UL) /*!< Max enumerator value of CONNECTION29 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Disabled (0x0UL) /*!< Master port 29 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Enabled (0x1UL) /*!< Master port 29 connection to global slave is enabled */ + +/* CONNECTION30 @Bit 30 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Pos (30UL) /*!< Position of CONNECTION30 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Pos) /*!< Bit mask of + CONNECTION30 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Min (0x0UL) /*!< Min enumerator value of CONNECTION30 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Max (0x1UL) /*!< Max enumerator value of CONNECTION30 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Disabled (0x0UL) /*!< Master port 30 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Enabled (0x1UL) /*!< Master port 30 connection to global slave is enabled */ + +/* CONNECTION31 @Bit 31 : Global slave connection information for master port */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Pos (31UL) /*!< Position of CONNECTION31 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Pos) /*!< Bit mask of + CONNECTION31 field.*/ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Min (0x0UL) /*!< Min enumerator value of CONNECTION31 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Max (0x1UL) /*!< Max enumerator value of CONNECTION31 field. */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Disabled (0x0UL) /*!< Master port 31 connection to global slave is disabled */ + #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Enabled (0x1UL) /*!< Master port 31 connection to global slave is enabled */ + + +/* MPC_GLOBALSLAVE_LOCK: Lock global slave registers */ + #define MPC_GLOBALSLAVE_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register. */ + +/* LOCK @Bit 0 : Enable lock */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Msk (0x1UL << MPC_GLOBALSLAVE_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Disabled (0x0UL) /*!< Lock disabled. */ + #define MPC_GLOBALSLAVE_LOCK_LOCK_Enabled (0x1UL) /*!< Lock enabled. */ + + + +/* =================================================== Struct MPC_RTCHOKE ==================================================== */ +/** + * @brief RTCHOKE [MPC_RTCHOKE] Real time choke configuration for AXI master port + */ +typedef struct { + __IOM uint32_t WRITEACCESS; /*!< (@ 0x00000000) Enable AXI Write Address Channel Real Time Choke for + master port*/ + __IOM uint32_t READACCESS; /*!< (@ 0x00000004) Enable AXI Read Address Channel Real Time Choke for + master port*/ + __IM uint32_t RESERVED[22]; + __IOM uint32_t DELAY[32]; /*!< (@ 0x00000060) Real Time Choke delay value for slave number n */ +} NRF_MPC_RTCHOKE_Type; /*!< Size = 224 (0x0E0) */ + +/* MPC_RTCHOKE_WRITEACCESS: Enable AXI Write Address Channel Real Time Choke for master port */ + #define MPC_RTCHOKE_WRITEACCESS_ResetValue (0x00000000UL) /*!< Reset value of WRITEACCESS register. */ + +/* ENABLE0 @Bit 0 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 0 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 0 Write Address + Channel*/ + +/* ENABLE1 @Bit 1 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 1 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 1 Write Address + Channel*/ + +/* ENABLE2 @Bit 2 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 2 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 2 Write Address + Channel*/ + +/* ENABLE3 @Bit 3 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 3 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 3 Write Address + Channel*/ + +/* ENABLE4 @Bit 4 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Pos (4UL) /*!< Position of ENABLE4 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 4 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 4 Write Address + Channel*/ + +/* ENABLE5 @Bit 5 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Pos (5UL) /*!< Position of ENABLE5 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 5 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 5 Write Address + Channel*/ + +/* ENABLE6 @Bit 6 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Pos (6UL) /*!< Position of ENABLE6 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 6 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 6 Write Address + Channel*/ + +/* ENABLE7 @Bit 7 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Pos (7UL) /*!< Position of ENABLE7 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 7 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 7 Write Address + Channel*/ + +/* ENABLE8 @Bit 8 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Pos (8UL) /*!< Position of ENABLE8 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 8 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 8 Write Address + Channel*/ + +/* ENABLE9 @Bit 9 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Pos (9UL) /*!< Position of ENABLE9 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 9 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 9 Write Address + Channel*/ + +/* ENABLE10 @Bit 10 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 10 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 10 Write Address + Channel*/ + +/* ENABLE11 @Bit 11 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 11 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 11 Write Address + Channel*/ + +/* ENABLE12 @Bit 12 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 12 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 12 Write Address + Channel*/ + +/* ENABLE13 @Bit 13 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 13 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 13 Write Address + Channel*/ + +/* ENABLE14 @Bit 14 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 14 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 14 Write Address + Channel*/ + +/* ENABLE15 @Bit 15 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 15 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 15 Write Address + Channel*/ + +/* ENABLE16 @Bit 16 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 16 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 16 Write Address + Channel*/ + +/* ENABLE17 @Bit 17 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 17 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 17 Write Address + Channel*/ + +/* ENABLE18 @Bit 18 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 18 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 18 Write Address + Channel*/ + +/* ENABLE19 @Bit 19 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 19 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 19 Write Address + Channel*/ + +/* ENABLE20 @Bit 20 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 20 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 20 Write Address + Channel*/ + +/* ENABLE21 @Bit 21 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 21 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 21 Write Address + Channel*/ + +/* ENABLE22 @Bit 22 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 22 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 22 Write Address + Channel*/ + +/* ENABLE23 @Bit 23 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 23 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 23 Write Address + Channel*/ + +/* ENABLE24 @Bit 24 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 24 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 24 Write Address + Channel*/ + +/* ENABLE25 @Bit 25 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 25 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 25 Write Address + Channel*/ + +/* ENABLE26 @Bit 26 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 26 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 26 Write Address + Channel*/ + +/* ENABLE27 @Bit 27 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 27 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 27 Write Address + Channel*/ + +/* ENABLE28 @Bit 28 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 28 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 28 Write Address + Channel*/ + +/* ENABLE29 @Bit 29 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 29 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 29 Write Address + Channel*/ + +/* ENABLE30 @Bit 30 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 30 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 30 Write Address + Channel*/ + +/* ENABLE31 @Bit 31 : Enable Real Time Choke for Write Address Channel */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field. */ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 31 Write Address + Channel*/ + #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 31 Write Address + Channel*/ + + +/* MPC_RTCHOKE_READACCESS: Enable AXI Read Address Channel Real Time Choke for master port */ + #define MPC_RTCHOKE_READACCESS_ResetValue (0x00000000UL) /*!< Reset value of READACCESS register. */ + +/* ENABLE0 @Bit 0 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 0 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE0_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 0 Read Address Channel */ + +/* ENABLE1 @Bit 1 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 1 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE1_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 1 Read Address Channel */ + +/* ENABLE2 @Bit 2 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 2 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE2_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 2 Read Address Channel */ + +/* ENABLE3 @Bit 3 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 3 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE3_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 3 Read Address Channel */ + +/* ENABLE4 @Bit 4 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Pos (4UL) /*!< Position of ENABLE4 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 4 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE4_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 4 Read Address Channel */ + +/* ENABLE5 @Bit 5 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Pos (5UL) /*!< Position of ENABLE5 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 5 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE5_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 5 Read Address Channel */ + +/* ENABLE6 @Bit 6 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Pos (6UL) /*!< Position of ENABLE6 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 6 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE6_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 6 Read Address Channel */ + +/* ENABLE7 @Bit 7 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Pos (7UL) /*!< Position of ENABLE7 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 7 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE7_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 7 Read Address Channel */ + +/* ENABLE8 @Bit 8 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Pos (8UL) /*!< Position of ENABLE8 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 8 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE8_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 8 Read Address Channel */ + +/* ENABLE9 @Bit 9 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Pos (9UL) /*!< Position of ENABLE9 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 9 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE9_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 9 Read Address Channel */ + +/* ENABLE10 @Bit 10 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 10 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE10_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 10 Read Address + Channel*/ + +/* ENABLE11 @Bit 11 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 11 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE11_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 11 Read Address + Channel*/ + +/* ENABLE12 @Bit 12 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 12 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE12_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 12 Read Address + Channel*/ + +/* ENABLE13 @Bit 13 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 13 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE13_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 13 Read Address + Channel*/ + +/* ENABLE14 @Bit 14 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 14 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE14_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 14 Read Address + Channel*/ + +/* ENABLE15 @Bit 15 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 15 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE15_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 15 Read Address + Channel*/ + +/* ENABLE16 @Bit 16 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 16 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE16_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 16 Read Address + Channel*/ + +/* ENABLE17 @Bit 17 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 17 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE17_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 17 Read Address + Channel*/ + +/* ENABLE18 @Bit 18 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 18 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE18_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 18 Read Address + Channel*/ + +/* ENABLE19 @Bit 19 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 19 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE19_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 19 Read Address + Channel*/ + +/* ENABLE20 @Bit 20 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 20 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE20_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 20 Read Address + Channel*/ + +/* ENABLE21 @Bit 21 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 21 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE21_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 21 Read Address + Channel*/ + +/* ENABLE22 @Bit 22 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 22 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE22_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 22 Read Address + Channel*/ + +/* ENABLE23 @Bit 23 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 23 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE23_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 23 Read Address + Channel*/ + +/* ENABLE24 @Bit 24 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 24 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE24_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 24 Read Address + Channel*/ + +/* ENABLE25 @Bit 25 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 25 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE25_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 25 Read Address + Channel*/ + +/* ENABLE26 @Bit 26 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 26 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE26_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 26 Read Address + Channel*/ + +/* ENABLE27 @Bit 27 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 27 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE27_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 27 Read Address + Channel*/ + +/* ENABLE28 @Bit 28 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 28 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE28_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 28 Read Address + Channel*/ + +/* ENABLE29 @Bit 29 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 29 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE29_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 29 Read Address + Channel*/ + +/* ENABLE30 @Bit 30 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 30 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE30_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 30 Read Address + Channel*/ + +/* ENABLE31 @Bit 31 : Enable Real Time Choke for Read Address Channel */ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field. */ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 31 Read Address + Channel*/ + #define MPC_RTCHOKE_READACCESS_ENABLE31_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 31 Read Address + Channel*/ + + +/* MPC_RTCHOKE_DELAY: Real Time Choke delay value for slave number n */ + #define MPC_RTCHOKE_DELAY_MaxCount (32UL) /*!< Max size of DELAY[32] array. */ + #define MPC_RTCHOKE_DELAY_MaxIndex (31UL) /*!< Max index of DELAY[32] array. */ + #define MPC_RTCHOKE_DELAY_MinIndex (0UL) /*!< Min index of DELAY[32] array. */ + #define MPC_RTCHOKE_DELAY_ResetValue (0x00000000UL) /*!< Reset value of DELAY[32] register. */ + +/* DELAY @Bits 0..7 : Real Time Choke delay in bus clock cycles. */ + #define MPC_RTCHOKE_DELAY_DELAY_Pos (0UL) /*!< Position of DELAY field. */ + #define MPC_RTCHOKE_DELAY_DELAY_Msk (0xFFUL << MPC_RTCHOKE_DELAY_DELAY_Pos) /*!< Bit mask of DELAY field. */ + #define MPC_RTCHOKE_DELAY_DELAY_Min (0x00UL) /*!< Min value of DELAY field. */ + #define MPC_RTCHOKE_DELAY_DELAY_Max (0xFFUL) /*!< Max size of DELAY field. */ + + + +/* ==================================================== Struct MPC_REGION ==================================================== */ +/** + * @brief REGION [MPC_REGION] Memory region to slave decoding table + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Slave region n Configuration register */ + __IOM uint32_t STARTADDR; /*!< (@ 0x00000004) Region n start address */ + __IOM uint32_t ADDRMASK; /*!< (@ 0x00000008) Select which bits of the incoming address are compared + against the STARTADDR*/ + __IOM uint32_t MASTERPORT; /*!< (@ 0x0000000C) Region n local master enable */ +} NRF_MPC_REGION_Type; /*!< Size = 16 (0x010) */ + #define MPC_REGION_MaxCount (32UL) /*!< Size of REGION[32] array. */ + #define MPC_REGION_MaxIndex (31UL) /*!< Max index of REGION[32] array. */ + #define MPC_REGION_MinIndex (0UL) /*!< Min index of REGION[32] array. */ + +/* MPC_REGION_CONFIG: Slave region n Configuration register */ + #define MPC_REGION_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* SLAVENUMBER @Bits 0..4 : Target slave number for region n accesses. Slave number 0 is reserved for default slave */ + #define MPC_REGION_CONFIG_SLAVENUMBER_Pos (0UL) /*!< Position of SLAVENUMBER field. */ + #define MPC_REGION_CONFIG_SLAVENUMBER_Msk (0x1FUL << MPC_REGION_CONFIG_SLAVENUMBER_Pos) /*!< Bit mask of SLAVENUMBER field. */ + #define MPC_REGION_CONFIG_SLAVENUMBER_Min (0x00UL) /*!< Min value of SLAVENUMBER field. */ + #define MPC_REGION_CONFIG_SLAVENUMBER_Max (0x1FUL) /*!< Max size of SLAVENUMBER field. */ + +/* LOCK @Bit 8 : Locks the region n setting */ + #define MPC_REGION_CONFIG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define MPC_REGION_CONFIG_LOCK_Msk (0x1UL << MPC_REGION_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define MPC_REGION_CONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define MPC_REGION_CONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define MPC_REGION_CONFIG_LOCK_Unlocked (0x0UL) /*!< Region n settings can be updated */ + #define MPC_REGION_CONFIG_LOCK_Locked (0x1UL) /*!< Region n settings can't be updated until next reset */ + +/* ENABLE @Bit 9 : Region n enable */ + #define MPC_REGION_CONFIG_ENABLE_Pos (9UL) /*!< Position of ENABLE field. */ + #define MPC_REGION_CONFIG_ENABLE_Msk (0x1UL << MPC_REGION_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define MPC_REGION_CONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define MPC_REGION_CONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define MPC_REGION_CONFIG_ENABLE_Disabled (0x0UL) /*!< Region n is not used */ + #define MPC_REGION_CONFIG_ENABLE_Enabled (0x1UL) /*!< Region n is used */ + +/* READ @Bit 12 : Read access */ + #define MPC_REGION_CONFIG_READ_Pos (12UL) /*!< Position of READ field. */ + #define MPC_REGION_CONFIG_READ_Msk (0x1UL << MPC_REGION_CONFIG_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_REGION_CONFIG_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_REGION_CONFIG_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_REGION_CONFIG_READ_NotAllowed (0x0UL) /*!< Read access to region n is not allowed */ + #define MPC_REGION_CONFIG_READ_Allowed (0x1UL) /*!< Read access to region n is allowed */ + +/* WRITE @Bit 13 : Write access */ + #define MPC_REGION_CONFIG_WRITE_Pos (13UL) /*!< Position of WRITE field. */ + #define MPC_REGION_CONFIG_WRITE_Msk (0x1UL << MPC_REGION_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_REGION_CONFIG_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_REGION_CONFIG_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_REGION_CONFIG_WRITE_NotAllowed (0x0UL) /*!< Write access to region n is not allowed */ + #define MPC_REGION_CONFIG_WRITE_Allowed (0x1UL) /*!< Write access to region n is allowed */ + +/* EXECUTE @Bit 14 : Software execute */ + #define MPC_REGION_CONFIG_EXECUTE_Pos (14UL) /*!< Position of EXECUTE field. */ + #define MPC_REGION_CONFIG_EXECUTE_Msk (0x1UL << MPC_REGION_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_REGION_CONFIG_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_REGION_CONFIG_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_REGION_CONFIG_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from region n is not allowed */ + #define MPC_REGION_CONFIG_EXECUTE_Allowed (0x1UL) /*!< Software execution from region n is allowed */ + +/* SECATTR @Bit 15 : Memory security mapping */ + #define MPC_REGION_CONFIG_SECATTR_Pos (15UL) /*!< Position of SECATTR field. */ + #define MPC_REGION_CONFIG_SECATTR_Msk (0x1UL << MPC_REGION_CONFIG_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define MPC_REGION_CONFIG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define MPC_REGION_CONFIG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define MPC_REGION_CONFIG_SECATTR_Secure (0x1UL) /*!< Memory is mapped in secure memory address space */ + #define MPC_REGION_CONFIG_SECATTR_NonSecure (0x0UL) /*!< Memory is mapped in non-secure memory address space */ + +/* OWNERID @Bits 16..19 : Region owner identifier. */ + #define MPC_REGION_CONFIG_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define MPC_REGION_CONFIG_OWNERID_Msk (0xFUL << MPC_REGION_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + + +/* MPC_REGION_STARTADDR: Region n start address */ + #define MPC_REGION_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register. */ + +/* STARTADDR @Bits 0..31 : Start address for memory region n */ + #define MPC_REGION_STARTADDR_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field. */ + #define MPC_REGION_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_REGION_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR + field.*/ + + +/* MPC_REGION_ADDRMASK: Select which bits of the incoming address are compared against the STARTADDR */ + #define MPC_REGION_ADDRMASK_ResetValue (0x00000000UL) /*!< Reset value of ADDRMASK register. */ + +/* ADDRMASK @Bits 0..31 : Address mask for memory region n */ + #define MPC_REGION_ADDRMASK_ADDRMASK_Pos (0UL) /*!< Position of ADDRMASK field. */ + #define MPC_REGION_ADDRMASK_ADDRMASK_Msk (0xFFFFFFFFUL << MPC_REGION_ADDRMASK_ADDRMASK_Pos) /*!< Bit mask of ADDRMASK field. */ + + +/* MPC_REGION_MASTERPORT: Region n local master enable */ + #define MPC_REGION_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register. */ + +/* ENABLE0 @Bit 0 : Enable region n for master port 0 */ + #define MPC_REGION_MASTERPORT_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define MPC_REGION_MASTERPORT_ENABLE0_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define MPC_REGION_MASTERPORT_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define MPC_REGION_MASTERPORT_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define MPC_REGION_MASTERPORT_ENABLE0_Disable (0x0UL) /*!< Region n is disabled for master port 0 */ + #define MPC_REGION_MASTERPORT_ENABLE0_Enable (0x1UL) /*!< Region n is enabled for master port 0 */ + +/* ENABLE1 @Bit 1 : Enable region n for master port 1 */ + #define MPC_REGION_MASTERPORT_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define MPC_REGION_MASTERPORT_ENABLE1_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define MPC_REGION_MASTERPORT_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define MPC_REGION_MASTERPORT_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define MPC_REGION_MASTERPORT_ENABLE1_Disable (0x0UL) /*!< Region n is disabled for master port 1 */ + #define MPC_REGION_MASTERPORT_ENABLE1_Enable (0x1UL) /*!< Region n is enabled for master port 1 */ + +/* ENABLE2 @Bit 2 : Enable region n for master port 2 */ + #define MPC_REGION_MASTERPORT_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define MPC_REGION_MASTERPORT_ENABLE2_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define MPC_REGION_MASTERPORT_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define MPC_REGION_MASTERPORT_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define MPC_REGION_MASTERPORT_ENABLE2_Disable (0x0UL) /*!< Region n is disabled for master port 2 */ + #define MPC_REGION_MASTERPORT_ENABLE2_Enable (0x1UL) /*!< Region n is enabled for master port 2 */ + +/* ENABLE3 @Bit 3 : Enable region n for master port 3 */ + #define MPC_REGION_MASTERPORT_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define MPC_REGION_MASTERPORT_ENABLE3_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define MPC_REGION_MASTERPORT_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define MPC_REGION_MASTERPORT_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define MPC_REGION_MASTERPORT_ENABLE3_Disable (0x0UL) /*!< Region n is disabled for master port 3 */ + #define MPC_REGION_MASTERPORT_ENABLE3_Enable (0x1UL) /*!< Region n is enabled for master port 3 */ + +/* ENABLE4 @Bit 4 : Enable region n for master port 4 */ + #define MPC_REGION_MASTERPORT_ENABLE4_Pos (4UL) /*!< Position of ENABLE4 field. */ + #define MPC_REGION_MASTERPORT_ENABLE4_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field. */ + #define MPC_REGION_MASTERPORT_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field. */ + #define MPC_REGION_MASTERPORT_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field. */ + #define MPC_REGION_MASTERPORT_ENABLE4_Disable (0x0UL) /*!< Region n is disabled for master port 4 */ + #define MPC_REGION_MASTERPORT_ENABLE4_Enable (0x1UL) /*!< Region n is enabled for master port 4 */ + +/* ENABLE5 @Bit 5 : Enable region n for master port 5 */ + #define MPC_REGION_MASTERPORT_ENABLE5_Pos (5UL) /*!< Position of ENABLE5 field. */ + #define MPC_REGION_MASTERPORT_ENABLE5_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field. */ + #define MPC_REGION_MASTERPORT_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field. */ + #define MPC_REGION_MASTERPORT_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field. */ + #define MPC_REGION_MASTERPORT_ENABLE5_Disable (0x0UL) /*!< Region n is disabled for master port 5 */ + #define MPC_REGION_MASTERPORT_ENABLE5_Enable (0x1UL) /*!< Region n is enabled for master port 5 */ + +/* ENABLE6 @Bit 6 : Enable region n for master port 6 */ + #define MPC_REGION_MASTERPORT_ENABLE6_Pos (6UL) /*!< Position of ENABLE6 field. */ + #define MPC_REGION_MASTERPORT_ENABLE6_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field. */ + #define MPC_REGION_MASTERPORT_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field. */ + #define MPC_REGION_MASTERPORT_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field. */ + #define MPC_REGION_MASTERPORT_ENABLE6_Disable (0x0UL) /*!< Region n is disabled for master port 6 */ + #define MPC_REGION_MASTERPORT_ENABLE6_Enable (0x1UL) /*!< Region n is enabled for master port 6 */ + +/* ENABLE7 @Bit 7 : Enable region n for master port 7 */ + #define MPC_REGION_MASTERPORT_ENABLE7_Pos (7UL) /*!< Position of ENABLE7 field. */ + #define MPC_REGION_MASTERPORT_ENABLE7_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field. */ + #define MPC_REGION_MASTERPORT_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field. */ + #define MPC_REGION_MASTERPORT_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field. */ + #define MPC_REGION_MASTERPORT_ENABLE7_Disable (0x0UL) /*!< Region n is disabled for master port 7 */ + #define MPC_REGION_MASTERPORT_ENABLE7_Enable (0x1UL) /*!< Region n is enabled for master port 7 */ + +/* ENABLE8 @Bit 8 : Enable region n for master port 8 */ + #define MPC_REGION_MASTERPORT_ENABLE8_Pos (8UL) /*!< Position of ENABLE8 field. */ + #define MPC_REGION_MASTERPORT_ENABLE8_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field. */ + #define MPC_REGION_MASTERPORT_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field. */ + #define MPC_REGION_MASTERPORT_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field. */ + #define MPC_REGION_MASTERPORT_ENABLE8_Disable (0x0UL) /*!< Region n is disabled for master port 8 */ + #define MPC_REGION_MASTERPORT_ENABLE8_Enable (0x1UL) /*!< Region n is enabled for master port 8 */ + +/* ENABLE9 @Bit 9 : Enable region n for master port 9 */ + #define MPC_REGION_MASTERPORT_ENABLE9_Pos (9UL) /*!< Position of ENABLE9 field. */ + #define MPC_REGION_MASTERPORT_ENABLE9_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field. */ + #define MPC_REGION_MASTERPORT_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field. */ + #define MPC_REGION_MASTERPORT_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field. */ + #define MPC_REGION_MASTERPORT_ENABLE9_Disable (0x0UL) /*!< Region n is disabled for master port 9 */ + #define MPC_REGION_MASTERPORT_ENABLE9_Enable (0x1UL) /*!< Region n is enabled for master port 9 */ + +/* ENABLE10 @Bit 10 : Enable region n for master port 10 */ + #define MPC_REGION_MASTERPORT_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field. */ + #define MPC_REGION_MASTERPORT_ENABLE10_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field. */ + #define MPC_REGION_MASTERPORT_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field. */ + #define MPC_REGION_MASTERPORT_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field. */ + #define MPC_REGION_MASTERPORT_ENABLE10_Disable (0x0UL) /*!< Region n is disabled for master port 10 */ + #define MPC_REGION_MASTERPORT_ENABLE10_Enable (0x1UL) /*!< Region n is enabled for master port 10 */ + +/* ENABLE11 @Bit 11 : Enable region n for master port 11 */ + #define MPC_REGION_MASTERPORT_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field. */ + #define MPC_REGION_MASTERPORT_ENABLE11_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field. */ + #define MPC_REGION_MASTERPORT_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field. */ + #define MPC_REGION_MASTERPORT_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field. */ + #define MPC_REGION_MASTERPORT_ENABLE11_Disable (0x0UL) /*!< Region n is disabled for master port 11 */ + #define MPC_REGION_MASTERPORT_ENABLE11_Enable (0x1UL) /*!< Region n is enabled for master port 11 */ + +/* ENABLE12 @Bit 12 : Enable region n for master port 12 */ + #define MPC_REGION_MASTERPORT_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field. */ + #define MPC_REGION_MASTERPORT_ENABLE12_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field. */ + #define MPC_REGION_MASTERPORT_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field. */ + #define MPC_REGION_MASTERPORT_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field. */ + #define MPC_REGION_MASTERPORT_ENABLE12_Disable (0x0UL) /*!< Region n is disabled for master port 12 */ + #define MPC_REGION_MASTERPORT_ENABLE12_Enable (0x1UL) /*!< Region n is enabled for master port 12 */ + +/* ENABLE13 @Bit 13 : Enable region n for master port 13 */ + #define MPC_REGION_MASTERPORT_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field. */ + #define MPC_REGION_MASTERPORT_ENABLE13_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field. */ + #define MPC_REGION_MASTERPORT_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field. */ + #define MPC_REGION_MASTERPORT_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field. */ + #define MPC_REGION_MASTERPORT_ENABLE13_Disable (0x0UL) /*!< Region n is disabled for master port 13 */ + #define MPC_REGION_MASTERPORT_ENABLE13_Enable (0x1UL) /*!< Region n is enabled for master port 13 */ + +/* ENABLE14 @Bit 14 : Enable region n for master port 14 */ + #define MPC_REGION_MASTERPORT_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field. */ + #define MPC_REGION_MASTERPORT_ENABLE14_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field. */ + #define MPC_REGION_MASTERPORT_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field. */ + #define MPC_REGION_MASTERPORT_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field. */ + #define MPC_REGION_MASTERPORT_ENABLE14_Disable (0x0UL) /*!< Region n is disabled for master port 14 */ + #define MPC_REGION_MASTERPORT_ENABLE14_Enable (0x1UL) /*!< Region n is enabled for master port 14 */ + +/* ENABLE15 @Bit 15 : Enable region n for master port 15 */ + #define MPC_REGION_MASTERPORT_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field. */ + #define MPC_REGION_MASTERPORT_ENABLE15_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field. */ + #define MPC_REGION_MASTERPORT_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field. */ + #define MPC_REGION_MASTERPORT_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field. */ + #define MPC_REGION_MASTERPORT_ENABLE15_Disable (0x0UL) /*!< Region n is disabled for master port 15 */ + #define MPC_REGION_MASTERPORT_ENABLE15_Enable (0x1UL) /*!< Region n is enabled for master port 15 */ + +/* ENABLE16 @Bit 16 : Enable region n for master port 16 */ + #define MPC_REGION_MASTERPORT_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field. */ + #define MPC_REGION_MASTERPORT_ENABLE16_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field. */ + #define MPC_REGION_MASTERPORT_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field. */ + #define MPC_REGION_MASTERPORT_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field. */ + #define MPC_REGION_MASTERPORT_ENABLE16_Disable (0x0UL) /*!< Region n is disabled for master port 16 */ + #define MPC_REGION_MASTERPORT_ENABLE16_Enable (0x1UL) /*!< Region n is enabled for master port 16 */ + +/* ENABLE17 @Bit 17 : Enable region n for master port 17 */ + #define MPC_REGION_MASTERPORT_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field. */ + #define MPC_REGION_MASTERPORT_ENABLE17_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field. */ + #define MPC_REGION_MASTERPORT_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field. */ + #define MPC_REGION_MASTERPORT_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field. */ + #define MPC_REGION_MASTERPORT_ENABLE17_Disable (0x0UL) /*!< Region n is disabled for master port 17 */ + #define MPC_REGION_MASTERPORT_ENABLE17_Enable (0x1UL) /*!< Region n is enabled for master port 17 */ + +/* ENABLE18 @Bit 18 : Enable region n for master port 18 */ + #define MPC_REGION_MASTERPORT_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field. */ + #define MPC_REGION_MASTERPORT_ENABLE18_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field. */ + #define MPC_REGION_MASTERPORT_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field. */ + #define MPC_REGION_MASTERPORT_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field. */ + #define MPC_REGION_MASTERPORT_ENABLE18_Disable (0x0UL) /*!< Region n is disabled for master port 18 */ + #define MPC_REGION_MASTERPORT_ENABLE18_Enable (0x1UL) /*!< Region n is enabled for master port 18 */ + +/* ENABLE19 @Bit 19 : Enable region n for master port 19 */ + #define MPC_REGION_MASTERPORT_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field. */ + #define MPC_REGION_MASTERPORT_ENABLE19_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field. */ + #define MPC_REGION_MASTERPORT_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field. */ + #define MPC_REGION_MASTERPORT_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field. */ + #define MPC_REGION_MASTERPORT_ENABLE19_Disable (0x0UL) /*!< Region n is disabled for master port 19 */ + #define MPC_REGION_MASTERPORT_ENABLE19_Enable (0x1UL) /*!< Region n is enabled for master port 19 */ + +/* ENABLE20 @Bit 20 : Enable region n for master port 20 */ + #define MPC_REGION_MASTERPORT_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field. */ + #define MPC_REGION_MASTERPORT_ENABLE20_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field. */ + #define MPC_REGION_MASTERPORT_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field. */ + #define MPC_REGION_MASTERPORT_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field. */ + #define MPC_REGION_MASTERPORT_ENABLE20_Disable (0x0UL) /*!< Region n is disabled for master port 20 */ + #define MPC_REGION_MASTERPORT_ENABLE20_Enable (0x1UL) /*!< Region n is enabled for master port 20 */ + +/* ENABLE21 @Bit 21 : Enable region n for master port 21 */ + #define MPC_REGION_MASTERPORT_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field. */ + #define MPC_REGION_MASTERPORT_ENABLE21_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field. */ + #define MPC_REGION_MASTERPORT_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field. */ + #define MPC_REGION_MASTERPORT_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field. */ + #define MPC_REGION_MASTERPORT_ENABLE21_Disable (0x0UL) /*!< Region n is disabled for master port 21 */ + #define MPC_REGION_MASTERPORT_ENABLE21_Enable (0x1UL) /*!< Region n is enabled for master port 21 */ + +/* ENABLE22 @Bit 22 : Enable region n for master port 22 */ + #define MPC_REGION_MASTERPORT_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field. */ + #define MPC_REGION_MASTERPORT_ENABLE22_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field. */ + #define MPC_REGION_MASTERPORT_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field. */ + #define MPC_REGION_MASTERPORT_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field. */ + #define MPC_REGION_MASTERPORT_ENABLE22_Disable (0x0UL) /*!< Region n is disabled for master port 22 */ + #define MPC_REGION_MASTERPORT_ENABLE22_Enable (0x1UL) /*!< Region n is enabled for master port 22 */ + +/* ENABLE23 @Bit 23 : Enable region n for master port 23 */ + #define MPC_REGION_MASTERPORT_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field. */ + #define MPC_REGION_MASTERPORT_ENABLE23_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field. */ + #define MPC_REGION_MASTERPORT_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field. */ + #define MPC_REGION_MASTERPORT_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field. */ + #define MPC_REGION_MASTERPORT_ENABLE23_Disable (0x0UL) /*!< Region n is disabled for master port 23 */ + #define MPC_REGION_MASTERPORT_ENABLE23_Enable (0x1UL) /*!< Region n is enabled for master port 23 */ + +/* ENABLE24 @Bit 24 : Enable region n for master port 24 */ + #define MPC_REGION_MASTERPORT_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field. */ + #define MPC_REGION_MASTERPORT_ENABLE24_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field. */ + #define MPC_REGION_MASTERPORT_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field. */ + #define MPC_REGION_MASTERPORT_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field. */ + #define MPC_REGION_MASTERPORT_ENABLE24_Disable (0x0UL) /*!< Region n is disabled for master port 24 */ + #define MPC_REGION_MASTERPORT_ENABLE24_Enable (0x1UL) /*!< Region n is enabled for master port 24 */ + +/* ENABLE25 @Bit 25 : Enable region n for master port 25 */ + #define MPC_REGION_MASTERPORT_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field. */ + #define MPC_REGION_MASTERPORT_ENABLE25_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field. */ + #define MPC_REGION_MASTERPORT_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field. */ + #define MPC_REGION_MASTERPORT_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field. */ + #define MPC_REGION_MASTERPORT_ENABLE25_Disable (0x0UL) /*!< Region n is disabled for master port 25 */ + #define MPC_REGION_MASTERPORT_ENABLE25_Enable (0x1UL) /*!< Region n is enabled for master port 25 */ + +/* ENABLE26 @Bit 26 : Enable region n for master port 26 */ + #define MPC_REGION_MASTERPORT_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field. */ + #define MPC_REGION_MASTERPORT_ENABLE26_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field. */ + #define MPC_REGION_MASTERPORT_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field. */ + #define MPC_REGION_MASTERPORT_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field. */ + #define MPC_REGION_MASTERPORT_ENABLE26_Disable (0x0UL) /*!< Region n is disabled for master port 26 */ + #define MPC_REGION_MASTERPORT_ENABLE26_Enable (0x1UL) /*!< Region n is enabled for master port 26 */ + +/* ENABLE27 @Bit 27 : Enable region n for master port 27 */ + #define MPC_REGION_MASTERPORT_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field. */ + #define MPC_REGION_MASTERPORT_ENABLE27_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field. */ + #define MPC_REGION_MASTERPORT_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field. */ + #define MPC_REGION_MASTERPORT_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field. */ + #define MPC_REGION_MASTERPORT_ENABLE27_Disable (0x0UL) /*!< Region n is disabled for master port 27 */ + #define MPC_REGION_MASTERPORT_ENABLE27_Enable (0x1UL) /*!< Region n is enabled for master port 27 */ + +/* ENABLE28 @Bit 28 : Enable region n for master port 28 */ + #define MPC_REGION_MASTERPORT_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field. */ + #define MPC_REGION_MASTERPORT_ENABLE28_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field. */ + #define MPC_REGION_MASTERPORT_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field. */ + #define MPC_REGION_MASTERPORT_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field. */ + #define MPC_REGION_MASTERPORT_ENABLE28_Disable (0x0UL) /*!< Region n is disabled for master port 28 */ + #define MPC_REGION_MASTERPORT_ENABLE28_Enable (0x1UL) /*!< Region n is enabled for master port 28 */ + +/* ENABLE29 @Bit 29 : Enable region n for master port 29 */ + #define MPC_REGION_MASTERPORT_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field. */ + #define MPC_REGION_MASTERPORT_ENABLE29_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field. */ + #define MPC_REGION_MASTERPORT_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field. */ + #define MPC_REGION_MASTERPORT_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field. */ + #define MPC_REGION_MASTERPORT_ENABLE29_Disable (0x0UL) /*!< Region n is disabled for master port 29 */ + #define MPC_REGION_MASTERPORT_ENABLE29_Enable (0x1UL) /*!< Region n is enabled for master port 29 */ + +/* ENABLE30 @Bit 30 : Enable region n for master port 30 */ + #define MPC_REGION_MASTERPORT_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field. */ + #define MPC_REGION_MASTERPORT_ENABLE30_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field. */ + #define MPC_REGION_MASTERPORT_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field. */ + #define MPC_REGION_MASTERPORT_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field. */ + #define MPC_REGION_MASTERPORT_ENABLE30_Disable (0x0UL) /*!< Region n is disabled for master port 30 */ + #define MPC_REGION_MASTERPORT_ENABLE30_Enable (0x1UL) /*!< Region n is enabled for master port 30 */ + +/* ENABLE31 @Bit 31 : Enable region n for master port 31 */ + #define MPC_REGION_MASTERPORT_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field. */ + #define MPC_REGION_MASTERPORT_ENABLE31_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field. */ + #define MPC_REGION_MASTERPORT_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field. */ + #define MPC_REGION_MASTERPORT_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field. */ + #define MPC_REGION_MASTERPORT_ENABLE31_Disable (0x0UL) /*!< Region n is disabled for master port 31 */ + #define MPC_REGION_MASTERPORT_ENABLE31_Enable (0x1UL) /*!< Region n is enabled for master port 31 */ + + + +/* =================================================== Struct MPC_OVERRIDE =================================================== */ +/** + * @brief OVERRIDE [MPC_OVERRIDE] Special privilege tables + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Override region n Configuration register */ + __IOM uint32_t STARTADDR; /*!< (@ 0x00000004) Override region n Start Address */ + __IOM uint32_t ENDADDR; /*!< (@ 0x00000008) Override region n End Address */ + __IOM int32_t OFFSET; /*!< (@ 0x0000000C) Address offset value divided by 2 for override region n + address re-map*/ + __IOM uint32_t PERM; /*!< (@ 0x00000010) Permission settings for override region n */ + __IOM uint32_t PERMMASK; /*!< (@ 0x00000014) Masks permission setting fields from register + OVERRIDE.PERM*/ + __IOM uint32_t OWNER; /*!< (@ 0x00000018) Owner for override region */ + __IOM uint32_t MASTERPORT; /*!< (@ 0x0000001C) Override region n local master enable */ +} NRF_MPC_OVERRIDE_Type; /*!< Size = 32 (0x020) */ + #define MPC_OVERRIDE_MaxCount (40UL) /*!< Size of OVERRIDE[40] array. */ + #define MPC_OVERRIDE_MaxIndex (39UL) /*!< Max index of OVERRIDE[40] array. */ + #define MPC_OVERRIDE_MinIndex (0UL) /*!< Min index of OVERRIDE[40] array. */ + +/* MPC_OVERRIDE_CONFIG: Override region n Configuration register */ + #define MPC_OVERRIDE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* SLAVENUMBER @Bits 0..4 : Target slave number for override region n accesses. Slave number 0 is reserved for default slave */ + #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos (0UL) /*!< Position of SLAVENUMBER field. */ + #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Msk (0x1FUL << MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos) /*!< Bit mask of SLAVENUMBER + field.*/ + #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Min (0x00UL) /*!< Min value of SLAVENUMBER field. */ + #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Max (0x1FUL) /*!< Max size of SLAVENUMBER field. */ + +/* LOCK @Bit 8 : Lock Override region n */ + #define MPC_OVERRIDE_CONFIG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define MPC_OVERRIDE_CONFIG_LOCK_Unlocked (0x0UL) /*!< Override region n settings can be updated */ + #define MPC_OVERRIDE_CONFIG_LOCK_Locked (0x1UL) /*!< Override region n settings can't be updated until next reset */ + +/* ENABLE @Bit 9 : Enable Override region n */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Pos (9UL) /*!< Position of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Disabled (0x0UL) /*!< Override region n is not used */ + #define MPC_OVERRIDE_CONFIG_ENABLE_Enabled (0x1UL) /*!< Override region n is used */ + +/* SECDOMENABLE @Bit 10 : Secure domain access enable for Override region n */ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos (10UL) /*!< Position of SECDOMENABLE field. */ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos) /*!< Bit mask of SECDOMENABLE + field.*/ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Min (0x0UL) /*!< Min enumerator value of SECDOMENABLE field. */ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Max (0x1UL) /*!< Max enumerator value of SECDOMENABLE field. */ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Disabled (0x0UL) /*!< Overriding of secure domain permissions is disabled for + override region n*/ + #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Enabled (0x1UL) /*!< Overriding of secure domain permissions is enabled for override + region n*/ + +/* SECUREMASK @Bit 12 : Secure mask enable for Override region n */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Pos (12UL) /*!< Position of SECUREMASK field. */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_SECUREMASK_Pos) /*!< Bit mask of SECUREMASK field. */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Min (0x0UL) /*!< Min enumerator value of SECUREMASK field. */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Max (0x1UL) /*!< Max enumerator value of SECUREMASK field. */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Disabled (0x0UL) /*!< Mask is disabled for override region n */ + #define MPC_OVERRIDE_CONFIG_SECUREMASK_Enabled (0x1UL) /*!< Mask is enabled for override region n */ + + +/* MPC_OVERRIDE_STARTADDR: Override region n Start Address */ + #define MPC_OVERRIDE_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register. */ + +/* STARTADDR @Bits 0..31 : Start address for override region n */ + #define MPC_OVERRIDE_STARTADDR_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field. */ + #define MPC_OVERRIDE_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR + field.*/ + + +/* MPC_OVERRIDE_ENDADDR: Override region n End Address */ + #define MPC_OVERRIDE_ENDADDR_ResetValue (0x00000000UL) /*!< Reset value of ENDADDR register. */ + +/* ENDADDR @Bits 0..31 : End address for override region n */ + #define MPC_OVERRIDE_ENDADDR_ENDADDR_Pos (0UL) /*!< Position of ENDADDR field. */ + #define MPC_OVERRIDE_ENDADDR_ENDADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_ENDADDR_ENDADDR_Pos) /*!< Bit mask of ENDADDR field. */ + + +/* MPC_OVERRIDE_OFFSET: Address offset value divided by 2 for override region n address re-map */ + #define MPC_OVERRIDE_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register. */ + +/* OFFSET @Bits 0..31 : Offset value */ + #define MPC_OVERRIDE_OFFSET_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define MPC_OVERRIDE_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + + +/* MPC_OVERRIDE_PERM: Permission settings for override region n */ + #define MPC_OVERRIDE_PERM_ResetValue (0x00000000UL) /*!< Reset value of PERM register. */ + +/* READ @Bit 0 : Read access */ + #define MPC_OVERRIDE_PERM_READ_Pos (0UL) /*!< Position of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Msk (0x1UL << MPC_OVERRIDE_PERM_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_OVERRIDE_PERM_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_OVERRIDE_PERM_READ_NotAllowed (0x0UL) /*!< Read access to override region n is not allowed */ + #define MPC_OVERRIDE_PERM_READ_Allowed (0x1UL) /*!< Read access to override region n is allowed */ + +/* WRITE @Bit 1 : Write access */ + #define MPC_OVERRIDE_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERM_WRITE_NotAllowed (0x0UL) /*!< Write access to override region n is not allowed */ + #define MPC_OVERRIDE_PERM_WRITE_Allowed (0x1UL) /*!< Write access to override region n is allowed */ + +/* EXECUTE @Bit 2 : Software execute */ + #define MPC_OVERRIDE_PERM_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERM_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from override region n is not allowed */ + #define MPC_OVERRIDE_PERM_EXECUTE_Allowed (0x1UL) /*!< Software execution from override region n is allowed */ + +/* SECATTR @Bit 3 : Security mapping */ + #define MPC_OVERRIDE_PERM_SECATTR_Pos (3UL) /*!< Position of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERM_SECATTR_Secure (0x1UL) /*!< Override region n is mapped in secure memory address space */ + #define MPC_OVERRIDE_PERM_SECATTR_NonSecure (0x0UL) /*!< Override region n is mapped in non-secure memory address space */ + + +/* MPC_OVERRIDE_PERMMASK: Masks permission setting fields from register OVERRIDE.PERM */ + #define MPC_OVERRIDE_PERMMASK_ResetValue (0x00000000UL) /*!< Reset value of PERMMASK register. */ + +/* READ @Bit 0 : Read mask */ + #define MPC_OVERRIDE_PERMMASK_READ_Pos (0UL) /*!< Position of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_READ_Pos) /*!< Bit mask of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define MPC_OVERRIDE_PERMMASK_READ_Masked (0x0UL) /*!< Permission setting READ in OVERRIDE register will not be applied */ + #define MPC_OVERRIDE_PERMMASK_READ_UnMasked (0x1UL) /*!< Permission setting READ in OVERRIDE register will be applied */ + +/* WRITE @Bit 1 : Write mask */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define MPC_OVERRIDE_PERMMASK_WRITE_Masked (0x0UL) /*!< Permission setting WRITE in OVERRIDE register will not be applied */ + #define MPC_OVERRIDE_PERMMASK_WRITE_UnMasked (0x1UL) /*!< Permission setting WRITE in OVERRIDE register will be applied */ + +/* EXECUTE @Bit 2 : Execute mask */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_Masked (0x0UL) /*!< Permission setting EXECUTE in OVERRIDE register will not be applied*/ + #define MPC_OVERRIDE_PERMMASK_EXECUTE_UnMasked (0x1UL) /*!< Permission setting EXECUTE in OVERRIDE register will be applied */ + +/* SECATTR @Bit 3 : Security mapping mask */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Pos (3UL) /*!< Position of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define MPC_OVERRIDE_PERMMASK_SECATTR_Masked (0x0UL) /*!< Permission setting SECATTR in OVERRIDE register will not be applied*/ + #define MPC_OVERRIDE_PERMMASK_SECATTR_UnMasked (0x1UL) /*!< Permission setting SECATTR in OVERRIDE register will be applied */ + + +/* MPC_OVERRIDE_OWNER: Owner for override region */ + #define MPC_OVERRIDE_OWNER_ResetValue (0x00000000UL) /*!< Reset value of OWNER register. */ + +/* OWNERID @Bits 0..3 : owner identifier for override region n */ + #define MPC_OVERRIDE_OWNER_OWNERID_Pos (0UL) /*!< Position of OWNERID field. */ + #define MPC_OVERRIDE_OWNER_OWNERID_Msk (0xFUL << MPC_OVERRIDE_OWNER_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define MPC_OVERRIDE_OWNER_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define MPC_OVERRIDE_OWNER_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* MPC_OVERRIDE_MASTERPORT: Override region n local master enable */ + #define MPC_OVERRIDE_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register. */ + +/* ENABLE0 @Bit 0 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Disable (0x0UL) /*!< Override region n is disabled for master port 0 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Enable (0x1UL) /*!< Override region n is enabled for master port 0 */ + +/* ENABLE1 @Bit 1 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Disable (0x0UL) /*!< Override region n is disabled for master port 1 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Enable (0x1UL) /*!< Override region n is enabled for master port 1 */ + +/* ENABLE2 @Bit 2 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Disable (0x0UL) /*!< Override region n is disabled for master port 2 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Enable (0x1UL) /*!< Override region n is enabled for master port 2 */ + +/* ENABLE3 @Bit 3 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Disable (0x0UL) /*!< Override region n is disabled for master port 3 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Enable (0x1UL) /*!< Override region n is enabled for master port 3 */ + +/* ENABLE4 @Bit 4 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Pos (4UL) /*!< Position of ENABLE4 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Disable (0x0UL) /*!< Override region n is disabled for master port 4 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Enable (0x1UL) /*!< Override region n is enabled for master port 4 */ + +/* ENABLE5 @Bit 5 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Pos (5UL) /*!< Position of ENABLE5 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Disable (0x0UL) /*!< Override region n is disabled for master port 5 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Enable (0x1UL) /*!< Override region n is enabled for master port 5 */ + +/* ENABLE6 @Bit 6 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Pos (6UL) /*!< Position of ENABLE6 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Disable (0x0UL) /*!< Override region n is disabled for master port 6 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Enable (0x1UL) /*!< Override region n is enabled for master port 6 */ + +/* ENABLE7 @Bit 7 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Pos (7UL) /*!< Position of ENABLE7 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Disable (0x0UL) /*!< Override region n is disabled for master port 7 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Enable (0x1UL) /*!< Override region n is enabled for master port 7 */ + +/* ENABLE8 @Bit 8 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Pos (8UL) /*!< Position of ENABLE8 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Disable (0x0UL) /*!< Override region n is disabled for master port 8 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Enable (0x1UL) /*!< Override region n is enabled for master port 8 */ + +/* ENABLE9 @Bit 9 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Pos (9UL) /*!< Position of ENABLE9 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Disable (0x0UL) /*!< Override region n is disabled for master port 9 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Enable (0x1UL) /*!< Override region n is enabled for master port 9 */ + +/* ENABLE10 @Bit 10 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Disable (0x0UL) /*!< Override region n is disabled for master port 10 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Enable (0x1UL) /*!< Override region n is enabled for master port 10 */ + +/* ENABLE11 @Bit 11 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Disable (0x0UL) /*!< Override region n is disabled for master port 11 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Enable (0x1UL) /*!< Override region n is enabled for master port 11 */ + +/* ENABLE12 @Bit 12 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Disable (0x0UL) /*!< Override region n is disabled for master port 12 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Enable (0x1UL) /*!< Override region n is enabled for master port 12 */ + +/* ENABLE13 @Bit 13 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Disable (0x0UL) /*!< Override region n is disabled for master port 13 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Enable (0x1UL) /*!< Override region n is enabled for master port 13 */ + +/* ENABLE14 @Bit 14 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Disable (0x0UL) /*!< Override region n is disabled for master port 14 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Enable (0x1UL) /*!< Override region n is enabled for master port 14 */ + +/* ENABLE15 @Bit 15 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Disable (0x0UL) /*!< Override region n is disabled for master port 15 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Enable (0x1UL) /*!< Override region n is enabled for master port 15 */ + +/* ENABLE16 @Bit 16 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Disable (0x0UL) /*!< Override region n is disabled for master port 16 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Enable (0x1UL) /*!< Override region n is enabled for master port 16 */ + +/* ENABLE17 @Bit 17 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Disable (0x0UL) /*!< Override region n is disabled for master port 17 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Enable (0x1UL) /*!< Override region n is enabled for master port 17 */ + +/* ENABLE18 @Bit 18 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Disable (0x0UL) /*!< Override region n is disabled for master port 18 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Enable (0x1UL) /*!< Override region n is enabled for master port 18 */ + +/* ENABLE19 @Bit 19 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Disable (0x0UL) /*!< Override region n is disabled for master port 19 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Enable (0x1UL) /*!< Override region n is enabled for master port 19 */ + +/* ENABLE20 @Bit 20 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Disable (0x0UL) /*!< Override region n is disabled for master port 20 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Enable (0x1UL) /*!< Override region n is enabled for master port 20 */ + +/* ENABLE21 @Bit 21 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Disable (0x0UL) /*!< Override region n is disabled for master port 21 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Enable (0x1UL) /*!< Override region n is enabled for master port 21 */ + +/* ENABLE22 @Bit 22 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Disable (0x0UL) /*!< Override region n is disabled for master port 22 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Enable (0x1UL) /*!< Override region n is enabled for master port 22 */ + +/* ENABLE23 @Bit 23 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Disable (0x0UL) /*!< Override region n is disabled for master port 23 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Enable (0x1UL) /*!< Override region n is enabled for master port 23 */ + +/* ENABLE24 @Bit 24 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Disable (0x0UL) /*!< Override region n is disabled for master port 24 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Enable (0x1UL) /*!< Override region n is enabled for master port 24 */ + +/* ENABLE25 @Bit 25 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Disable (0x0UL) /*!< Override region n is disabled for master port 25 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Enable (0x1UL) /*!< Override region n is enabled for master port 25 */ + +/* ENABLE26 @Bit 26 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Disable (0x0UL) /*!< Override region n is disabled for master port 26 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Enable (0x1UL) /*!< Override region n is enabled for master port 26 */ + +/* ENABLE27 @Bit 27 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Disable (0x0UL) /*!< Override region n is disabled for master port 27 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Enable (0x1UL) /*!< Override region n is enabled for master port 27 */ + +/* ENABLE28 @Bit 28 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Disable (0x0UL) /*!< Override region n is disabled for master port 28 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Enable (0x1UL) /*!< Override region n is enabled for master port 28 */ + +/* ENABLE29 @Bit 29 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Disable (0x0UL) /*!< Override region n is disabled for master port 29 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Enable (0x1UL) /*!< Override region n is enabled for master port 29 */ + +/* ENABLE30 @Bit 30 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Disable (0x0UL) /*!< Override region n is disabled for master port 30 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Enable (0x1UL) /*!< Override region n is enabled for master port 30 */ + +/* ENABLE31 @Bit 31 : Enable override */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.*/ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field. */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Disable (0x0UL) /*!< Override region n is disabled for master port 31 */ + #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Enable (0x1UL) /*!< Override region n is enabled for master port 31 */ + + +/* ======================================================= Struct MPC ======================================================== */ +/** + * @brief Memory Privilege Controller + */ + typedef struct { /*!< MPC Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_MEMACCERR; /*!< (@ 0x00000100) Memory Access Error event */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IOM NRF_MPC_MEMACCERR_Type MEMACCERR; /*!< (@ 0x00000400) Memory Access Error status registers */ + __IM uint32_t RESERVED3[2]; + __IOM NRF_MPC_GLOBALSLAVE_Type GLOBALSLAVE; /*!< (@ 0x00000410) Global slave master port connection information */ + __IOM uint32_t EXTENDCLKREQ; /*!< (@ 0x00000418) Extend clock request configuration */ + __IM uint32_t RESERVED4; + __IOM NRF_MPC_RTCHOKE_Type RTCHOKE; /*!< (@ 0x00000420) Real time choke configuration for AXI master port */ + __IM uint32_t RESERVED5[64]; + __IOM NRF_MPC_REGION_Type REGION[32]; /*!< (@ 0x00000600) Memory region to slave decoding table */ + __IOM NRF_MPC_OVERRIDE_Type OVERRIDE[40]; /*!< (@ 0x00000800) Special privilege tables */ + } NRF_MPC_Type; /*!< Size = 3328 (0xD00) */ + +/* MPC_EVENTS_MEMACCERR: Memory Access Error event */ + #define MPC_EVENTS_MEMACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MEMACCERR register. */ + +/* EVENTS_MEMACCERR @Bit 0 : Memory Access Error event */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos (0UL) /*!< Position of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Msk (0x1UL << MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos) /*!< Bit mask of + EVENTS_MEMACCERR field.*/ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_MEMACCERR field. */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_NotGenerated (0x0UL) /*!< Event not generated */ + #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Generated (0x1UL) /*!< Event generated */ + + +/* MPC_INTEN: Enable or disable interrupt */ + #define MPC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* MEMACCERR @Bit 0 : Enable or disable interrupt for event MEMACCERR */ + #define MPC_INTEN_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Msk (0x1UL << MPC_INTEN_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTEN_MEMACCERR_Disabled (0x0UL) /*!< Disable */ + #define MPC_INTEN_MEMACCERR_Enabled (0x1UL) /*!< Enable */ + + +/* MPC_INTENSET: Enable interrupt */ + #define MPC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* MEMACCERR @Bit 0 : Write '1' to enable interrupt for event MEMACCERR */ + #define MPC_INTENSET_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Msk (0x1UL << MPC_INTENSET_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTENSET_MEMACCERR_Set (0x1UL) /*!< Enable */ + #define MPC_INTENSET_MEMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MPC_INTENSET_MEMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* MPC_INTENCLR: Disable interrupt */ + #define MPC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* MEMACCERR @Bit 0 : Write '1' to disable interrupt for event MEMACCERR */ + #define MPC_INTENCLR_MEMACCERR_Pos (0UL) /*!< Position of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Msk (0x1UL << MPC_INTENCLR_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of MEMACCERR field. */ + #define MPC_INTENCLR_MEMACCERR_Clear (0x1UL) /*!< Disable */ + #define MPC_INTENCLR_MEMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MPC_INTENCLR_MEMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* MPC_EXTENDCLKREQ: Extend clock request configuration */ + #define MPC_EXTENDCLKREQ_ResetValue (0x00000003UL) /*!< Reset value of EXTENDCLKREQ register. */ + +/* INIT @Bits 0..15 : Initial value of the down counter used for extending the clock request. */ + #define MPC_EXTENDCLKREQ_INIT_Pos (0UL) /*!< Position of INIT field. */ + #define MPC_EXTENDCLKREQ_INIT_Msk (0xFFFFUL << MPC_EXTENDCLKREQ_INIT_Pos) /*!< Bit mask of INIT field. */ + +/* ENABLE @Bit 31 : Enable the extend clock request feature */ + #define MPC_EXTENDCLKREQ_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ + #define MPC_EXTENDCLKREQ_ENABLE_Msk (0x1UL << MPC_EXTENDCLKREQ_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define MPC_EXTENDCLKREQ_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define MPC_EXTENDCLKREQ_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define MPC_EXTENDCLKREQ_ENABLE_Disable (0x0UL) /*!< Disable */ + #define MPC_EXTENDCLKREQ_ENABLE_Enable (0x1UL) /*!< Enable */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MUTEX ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct MUTEX ======================================================= */ +/** + * @brief MUTEX + */ + typedef struct { /*!< MUTEX Structure */ + __IM uint32_t RESERVED[256]; + __IOM uint32_t MUTEX[32]; /*!< (@ 0x00000400) Mutex register */ + } NRF_MUTEX_Type; /*!< Size = 1152 (0x480) */ + +/* MUTEX_MUTEX: Mutex register */ + #define MUTEX_MUTEX_MaxCount (32UL) /*!< Max size of MUTEX[32] array. */ + #define MUTEX_MUTEX_MaxIndex (31UL) /*!< Max index of MUTEX[32] array. */ + #define MUTEX_MUTEX_MinIndex (0UL) /*!< Min index of MUTEX[32] array. */ + #define MUTEX_MUTEX_ResetValue (0x00000000UL) /*!< Reset value of MUTEX[32] register. */ + +/* MUTEX @Bit 0 : Mutex register n */ + #define MUTEX_MUTEX_MUTEX_Pos (0UL) /*!< Position of MUTEX field. */ + #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos) /*!< Bit mask of MUTEX field. */ + #define MUTEX_MUTEX_MUTEX_Min (0x0UL) /*!< Min enumerator value of MUTEX field. */ + #define MUTEX_MUTEX_MUTEX_Max (0x1UL) /*!< Max enumerator value of MUTEX field. */ + #define MUTEX_MUTEX_MUTEX_Unlocked (0x0UL) /*!< Mutex n is in unlocked state */ + #define MUTEX_MUTEX_MUTEX_Locked (0x1UL) /*!< Mutex n is in locked state */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ MVDMA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =============================================== Struct MVDMA_EVENTS_SOURCE ================================================ */ +/** + * @brief EVENTS_SOURCE [MVDMA_EVENTS_SOURCE] Peripheral events. + */ +typedef struct { + __IOM uint32_t BUSERROR; /*!< (@ 0x00000000) Event indicating that a bus error has been received on + the Source channel.*/ + __IOM uint32_t SELECTJOBDONE; /*!< (@ 0x00000004) Event indicating that a job on the Source channel with + EVENT_ENABLE active has been processed.*/ +} NRF_MVDMA_EVENTS_SOURCE_Type; /*!< Size = 8 (0x008) */ + +/* MVDMA_EVENTS_SOURCE_BUSERROR: Event indicating that a bus error has been received on the Source channel. */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : Event indicating that a bus error has been received on the Source channel. */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Msk (0x1UL << MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Pos) /*!< Bit mask of + BUSERROR field.*/ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_SOURCE_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_SOURCE_SELECTJOBDONE: Event indicating that a job on the Source channel with EVENT_ENABLE active has been + processed. */ + + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of SELECTJOBDONE register. */ + +/* SELECTJOBDONE @Bit 0 : Event indicating that a job on the Source channel with EVENT_ENABLE active has been processed. */ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Pos (0UL) /*!< Position of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Msk (0x1UL << MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Pos) + /*!< Bit mask of SELECTJOBDONE field.*/ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_SOURCE_SELECTJOBDONE_SELECTJOBDONE_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct MVDMA_EVENTS_SINK ================================================= */ +/** + * @brief EVENTS_SINK [MVDMA_EVENTS_SINK] Peripheral events. + */ +typedef struct { + __IOM uint32_t BUSERROR; /*!< (@ 0x00000000) Event indicating that a bus error has been received on + the Sink channel.*/ + __IOM uint32_t SELECTJOBDONE; /*!< (@ 0x00000004) Event indicating that a job on the Sink channel with + EVENT_ENABLE active has been processed.*/ +} NRF_MVDMA_EVENTS_SINK_Type; /*!< Size = 8 (0x008) */ + +/* MVDMA_EVENTS_SINK_BUSERROR: Event indicating that a bus error has been received on the Sink channel. */ + #define MVDMA_EVENTS_SINK_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : Event indicating that a bus error has been received on the Sink channel. */ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Msk (0x1UL << MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_SINK_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_SINK_SELECTJOBDONE: Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. + */ + + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of SELECTJOBDONE register. */ + +/* SELECTJOBDONE @Bit 0 : Event indicating that a job on the Sink channel with EVENT_ENABLE active has been processed. */ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Pos (0UL) /*!< Position of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Msk (0x1UL << MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Pos) /*!< + Bit mask of SELECTJOBDONE field.*/ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SELECTJOBDONE field. */ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_SINK_SELECTJOBDONE_SELECTJOBDONE_Generated (0x1UL) /*!< Event generated */ + + + +/* =============================================== Struct MVDMA_PUBLISH_SOURCE =============================================== */ +/** + * @brief PUBLISH_SOURCE [MVDMA_PUBLISH_SOURCE] Publish configuration for events + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t SELECTJOBDONE; /*!< (@ 0x00000004) Publish configuration for event SOURCE.SELECTJOBDONE */ +} NRF_MVDMA_PUBLISH_SOURCE_Type; /*!< Size = 8 (0x008) */ + +/* MVDMA_PUBLISH_SOURCE_SELECTJOBDONE: Publish configuration for event SOURCE.SELECTJOBDONE */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of SELECTJOBDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SOURCE.SELECTJOBDONE will publish to */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Msk (0x1UL << MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Pos) /*!< Bit mask of EN + field.*/ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define MVDMA_PUBLISH_SOURCE_SELECTJOBDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================ Struct MVDMA_PUBLISH_SINK ================================================ */ +/** + * @brief PUBLISH_SINK [MVDMA_PUBLISH_SINK] Publish configuration for events + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t SELECTJOBDONE; /*!< (@ 0x00000004) Publish configuration for event SINK.SELECTJOBDONE */ +} NRF_MVDMA_PUBLISH_SINK_Type; /*!< Size = 8 (0x008) */ + +/* MVDMA_PUBLISH_SINK_SELECTJOBDONE: Publish configuration for event SINK.SELECTJOBDONE */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of SELECTJOBDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SINK.SELECTJOBDONE will publish to */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SINK_SELECTJOBDONE_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Msk (0x1UL << MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Pos) /*!< Bit mask of EN field.*/ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define MVDMA_PUBLISH_SINK_SELECTJOBDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =================================================== Struct MVDMA_STATUS =================================================== */ +/** + * @brief STATUS [MVDMA_STATUS] MVDMA status registers. + */ +typedef struct { + __IM uint32_t CRCRESULT; /*!< (@ 0x00000000) CRC checksum calculation result */ + __IM uint32_t FIFO; /*!< (@ 0x00000004) Status of intermediate fifo: empty, not empty and full + information available.*/ + __IM uint32_t ACTIVE; /*!< (@ 0x00000008) Status of DMA transfer. */ +} NRF_MVDMA_STATUS_Type; /*!< Size = 12 (0x00C) */ + +/* MVDMA_STATUS_CRCRESULT: CRC checksum calculation result */ + #define MVDMA_STATUS_CRCRESULT_ResetValue (0x00000000UL) /*!< Reset value of CRCRESULT register. */ + +/* CRC @Bits 0..31 : Result */ + #define MVDMA_STATUS_CRCRESULT_CRC_Pos (0UL) /*!< Position of CRC field. */ + #define MVDMA_STATUS_CRCRESULT_CRC_Msk (0xFFFFFFFFUL << MVDMA_STATUS_CRCRESULT_CRC_Pos) /*!< Bit mask of CRC field. */ + + +/* MVDMA_STATUS_FIFO: Status of intermediate fifo: empty, not empty and full information available. */ + #define MVDMA_STATUS_FIFO_ResetValue (0x00000000UL) /*!< Reset value of FIFO register. */ + +/* FIFOSTATUS @Bits 0..1 : Result */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Pos (0UL) /*!< Position of FIFOSTATUS field. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Msk (0x3UL << MVDMA_STATUS_FIFO_FIFOSTATUS_Pos) /*!< Bit mask of FIFOSTATUS field. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Min (0x0UL) /*!< Min enumerator value of FIFOSTATUS field. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Max (0x2UL) /*!< Max enumerator value of FIFOSTATUS field. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Empty (0x0UL) /*!< Fifo is empty. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_NotEmpty (0x1UL) /*!< Fifo contains data. */ + #define MVDMA_STATUS_FIFO_FIFOSTATUS_Full (0x2UL) /*!< Fifo is full. */ + + +/* MVDMA_STATUS_ACTIVE: Status of DMA transfer. */ + #define MVDMA_STATUS_ACTIVE_ResetValue (0x00000000UL) /*!< Reset value of ACTIVE register. */ + +/* ACTIVE @Bit 0 : DMA activity */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Msk (0x1UL << MVDMA_STATUS_ACTIVE_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Idle (0x0UL) /*!< DMA is in IDLE state. */ + #define MVDMA_STATUS_ACTIVE_ACTIVE_Active (0x1UL) /*!< Data being transferred. */ + + + +/* =================================================== Struct MVDMA_CONFIG =================================================== */ +/** + * @brief CONFIG [MVDMA_CONFIG] MVDMA configuration registers. + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) Configure MVDMA mode of operation. */ + __IM uint32_t RESERVED; +} NRF_MVDMA_CONFIG_Type; /*!< Size = 8 (0x008) */ + +/* MVDMA_CONFIG_MODE: Configure MVDMA mode of operation. */ + #define MVDMA_CONFIG_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bit 0 : (unspecified) */ + #define MVDMA_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define MVDMA_CONFIG_MODE_MODE_Msk (0x1UL << MVDMA_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define MVDMA_CONFIG_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define MVDMA_CONFIG_MODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define MVDMA_CONFIG_MODE_MODE_SingleMode (0x0UL) /*!< Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a + single job list.*/ + #define MVDMA_CONFIG_MODE_MODE_MultiMode (0x1UL) /*!< Registers SOURCE.LISTPTR and SINK.LISTPTR contain start address of a + list of job list pointers in memory.*/ + + + +/* =================================================== Struct MVDMA_SOURCE =================================================== */ +/** + * @brief SOURCE [MVDMA_SOURCE] Source channel configuration and status. + */ +typedef struct { + __IOM uint32_t LISTPTR; /*!< (@ 0x00000000) Start address of Source job list or list of job list + pointers, depending on value of CONFIG.MODE.*/ + __IM uint32_t BUSERROR; /*!< (@ 0x00000004) Source bus error status. */ + __IM uint32_t ADDRESS; /*!< (@ 0x00000008) Latest address being accessed on the Source channel.If + a bus error occurs, these registers will contain the + address that cause the error.*/ + __IM uint32_t JOBCOUNT; /*!< (@ 0x0000000C) Number of completed jobs in the current Source + descriptor list. This resets to 0 when a new joblist is + started.*/ +} NRF_MVDMA_SOURCE_Type; /*!< Size = 16 (0x010) */ + +/* MVDMA_SOURCE_LISTPTR: Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE. */ + #define MVDMA_SOURCE_LISTPTR_ResetValue (0x00000000UL) /*!< Reset value of LISTPTR register. */ + +/* ADDRESS @Bits 0..31 : Source job descriptor list address. */ + #define MVDMA_SOURCE_LISTPTR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MVDMA_SOURCE_LISTPTR_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_SOURCE_LISTPTR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* MVDMA_SOURCE_BUSERROR: Source bus error status. */ + #define MVDMA_SOURCE_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bits 0..1 : Bus error type */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_Msk (0x3UL << MVDMA_SOURCE_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR field. */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_Max (0x2UL) /*!< Max enumerator value of BUSERROR field. */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_NoError (0x0UL) /*!< There are no errors. */ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_ReadError (0x1UL) /*!< Error related to memory when reading joblist, or error related + to memory/register when reading data.*/ + #define MVDMA_SOURCE_BUSERROR_BUSERROR_ReadDecodeError (0x2UL) /*!< Error related to the joblist address when reading joblist, + or error related to address when reading memory/register.*/ + + +/* MVDMA_SOURCE_ADDRESS: Latest address being accessed on the Source channel.If a bus error occurs, these registers will contain + the address that cause the error. */ + + #define MVDMA_SOURCE_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..31 : Source address */ + #define MVDMA_SOURCE_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MVDMA_SOURCE_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_SOURCE_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* MVDMA_SOURCE_JOBCOUNT: Number of completed jobs in the current Source descriptor list. This resets to 0 when a new joblist is + started. */ + + #define MVDMA_SOURCE_JOBCOUNT_ResetValue (0x00000000UL) /*!< Reset value of JOBCOUNT register. */ + +/* COUNT @Bits 0..31 : Source job count */ + #define MVDMA_SOURCE_JOBCOUNT_COUNT_Pos (0UL) /*!< Position of COUNT field. */ + #define MVDMA_SOURCE_JOBCOUNT_COUNT_Msk (0xFFFFFFFFUL << MVDMA_SOURCE_JOBCOUNT_COUNT_Pos) /*!< Bit mask of COUNT field. */ + + + +/* ==================================================== Struct MVDMA_SINK ==================================================== */ +/** + * @brief SINK [MVDMA_SINK] Sink channel configuration and status. + */ +typedef struct { + __IOM uint32_t LISTPTR; /*!< (@ 0x00000000) Start address of Sink job list or list of job list + pointers, depending on value of CONFIG.MODE.*/ + __IM uint32_t BUSERROR; /*!< (@ 0x00000004) Sink bus error status. */ + __IM uint32_t ADDRESS; /*!< (@ 0x00000008) Latest address being accessed on the Sink channel. If a + bus error occurs, these registers will contain the + address that cause the error.*/ + __IM uint32_t JOBCOUNT; /*!< (@ 0x0000000C) Number of completed jobs in the current Sink descriptor + list. This resets to 0 when a new joblist is started.*/ +} NRF_MVDMA_SINK_Type; /*!< Size = 16 (0x010) */ + +/* MVDMA_SINK_LISTPTR: Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. */ + #define MVDMA_SINK_LISTPTR_ResetValue (0x00000000UL) /*!< Reset value of LISTPTR register. */ + +/* ADDRESS @Bits 0..31 : Sink descriptor list address. */ + #define MVDMA_SINK_LISTPTR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MVDMA_SINK_LISTPTR_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_SINK_LISTPTR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* MVDMA_SINK_BUSERROR: Sink bus error status. */ + #define MVDMA_SINK_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bits 0..2 : Bus error type */ + #define MVDMA_SINK_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_Msk (0x7UL << MVDMA_SINK_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR field. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_Max (0x4UL) /*!< Max enumerator value of BUSERROR field. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_NoError (0x0UL) /*!< There are no errors. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_ReadError (0x1UL) /*!< Error related to memory when reading joblist. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_ReadDecodeError (0x2UL) /*!< Error related to the joblist address when reading joblist. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_WriteError (0x3UL) /*!< Error related to memory/register when writing data. */ + #define MVDMA_SINK_BUSERROR_BUSERROR_WriteDecodeError (0x4UL) /*!< Error related to the memory/register address when writing + data.*/ + + +/* MVDMA_SINK_ADDRESS: Latest address being accessed on the Sink channel. If a bus error occurs, these registers will contain + the address that cause the error. */ + + #define MVDMA_SINK_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..31 : Sink address */ + #define MVDMA_SINK_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define MVDMA_SINK_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_SINK_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* MVDMA_SINK_JOBCOUNT: Number of completed jobs in the current Sink descriptor list. This resets to 0 when a new joblist is + started. */ + + #define MVDMA_SINK_JOBCOUNT_ResetValue (0x00000000UL) /*!< Reset value of JOBCOUNT register. */ + +/* COUNT @Bits 0..31 : Sink job count */ + #define MVDMA_SINK_JOBCOUNT_COUNT_Pos (0UL) /*!< Position of COUNT field. */ + #define MVDMA_SINK_JOBCOUNT_COUNT_Msk (0xFFFFFFFFUL << MVDMA_SINK_JOBCOUNT_COUNT_Pos) /*!< Bit mask of COUNT field. */ + + +/* ====================================================== Struct MVDMA ======================================================= */ +/** + * @brief MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each + transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and + they contain data buffer information, address pointers, buffer sizes and data type attributes. + + */ + typedef struct { /*!< MVDMA Structure */ + __OM uint32_t TASKS_PAUSE; /*!< (@ 0x00000000) Pause operation. */ + __OM uint32_t TASKS_RESET; /*!< (@ 0x00000004) Reset operation. */ + __OM uint32_t TASKS_START[8]; /*!< (@ 0x00000008) Start operation of job list n. Base address for + successive TASKS_STARTs.*/ + __IM uint32_t RESERVED[24]; + __IOM uint32_t SUBSCRIBE_START[8]; /*!< (@ 0x00000088) Subscribe configuration for task START[n] */ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Event indicating that Sink data descriptor list has + been completed.*/ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Event indicating that the source list processing has + started.*/ + __IOM uint32_t EVENTS_PAUSED; /*!< (@ 0x00000108) Event indicating that the data transfer has been + paused.*/ + __IOM uint32_t EVENTS_RESET; /*!< (@ 0x0000010C) Event indicating that the peripheral has been reset. */ + __IOM NRF_MVDMA_EVENTS_SOURCE_Type EVENTS_SOURCE; /*!< (@ 0x00000110) Peripheral events. */ + __IOM NRF_MVDMA_EVENTS_SINK_Type EVENTS_SINK; /*!< (@ 0x00000118) Peripheral events. */ + __IOM uint32_t EVENTS_COMPLETED[8]; /*!< (@ 0x00000120) Event indicating that the operation started by the task + START[n] has been completed. Base address for + successive EVENTS_COMPLETED.*/ + __IM uint32_t RESERVED2[16]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ + __IM uint32_t RESERVED3[3]; + __IOM NRF_MVDMA_PUBLISH_SOURCE_Type PUBLISH_SOURCE; /*!< (@ 0x00000190) Publish configuration for events */ + __IOM NRF_MVDMA_PUBLISH_SINK_Type PUBLISH_SINK; /*!< (@ 0x00000198) Publish configuration for events */ + __IOM uint32_t PUBLISH_COMPLETED[8]; /*!< (@ 0x000001A0) Publish configuration for event COMPLETED[n] */ + __IM uint32_t RESERVED4[80]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED5[60]; + __IOM NRF_MVDMA_STATUS_Type STATUS; /*!< (@ 0x00000400) MVDMA status registers. */ + __IM uint32_t RESERVED6[61]; + __IOM NRF_MVDMA_CONFIG_Type CONFIG; /*!< (@ 0x00000500) MVDMA configuration registers. */ + __IM uint32_t RESERVED7[62]; + __IOM NRF_MVDMA_SOURCE_Type SOURCE; /*!< (@ 0x00000600) Source channel configuration and status. */ + __IM uint32_t RESERVED8[4]; + __IOM NRF_MVDMA_SINK_Type SINK; /*!< (@ 0x00000620) Sink channel configuration and status. */ + } NRF_MVDMA_Type; /*!< Size = 1584 (0x630) */ + +/* MVDMA_TASKS_PAUSE: Pause operation. */ + #define MVDMA_TASKS_PAUSE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PAUSE register. */ + +/* TASKS_PAUSE @Bit 0 : Pause operation. */ + #define MVDMA_TASKS_PAUSE_TASKS_PAUSE_Pos (0UL) /*!< Position of TASKS_PAUSE field. */ + #define MVDMA_TASKS_PAUSE_TASKS_PAUSE_Msk (0x1UL << MVDMA_TASKS_PAUSE_TASKS_PAUSE_Pos) /*!< Bit mask of TASKS_PAUSE field. */ + #define MVDMA_TASKS_PAUSE_TASKS_PAUSE_Min (0x1UL) /*!< Min enumerator value of TASKS_PAUSE field. */ + #define MVDMA_TASKS_PAUSE_TASKS_PAUSE_Max (0x1UL) /*!< Max enumerator value of TASKS_PAUSE field. */ + #define MVDMA_TASKS_PAUSE_TASKS_PAUSE_Trigger (0x1UL) /*!< Trigger task */ + + +/* MVDMA_TASKS_RESET: Reset operation. */ + #define MVDMA_TASKS_RESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESET register. */ + +/* TASKS_RESET @Bit 0 : Reset operation. */ + #define MVDMA_TASKS_RESET_TASKS_RESET_Pos (0UL) /*!< Position of TASKS_RESET field. */ + #define MVDMA_TASKS_RESET_TASKS_RESET_Msk (0x1UL << MVDMA_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET field. */ + #define MVDMA_TASKS_RESET_TASKS_RESET_Min (0x1UL) /*!< Min enumerator value of TASKS_RESET field. */ + #define MVDMA_TASKS_RESET_TASKS_RESET_Max (0x1UL) /*!< Max enumerator value of TASKS_RESET field. */ + #define MVDMA_TASKS_RESET_TASKS_RESET_Trigger (0x1UL) /*!< Trigger task */ + + +/* MVDMA_TASKS_START: Start operation of job list n. Base address for successive TASKS_STARTs. */ + #define MVDMA_TASKS_START_MaxCount (8UL) /*!< Max size of TASKS_START[8] array. */ + #define MVDMA_TASKS_START_MaxIndex (7UL) /*!< Max index of TASKS_START[8] array. */ + #define MVDMA_TASKS_START_MinIndex (0UL) /*!< Min index of TASKS_START[8] array. */ + #define MVDMA_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START[8] register. */ + +/* TASKS_START @Bit 0 : Start operation of job list n. Base address for successive TASKS_STARTs. */ + #define MVDMA_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define MVDMA_TASKS_START_TASKS_START_Msk (0x1UL << MVDMA_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define MVDMA_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define MVDMA_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define MVDMA_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* MVDMA_SUBSCRIBE_START: Subscribe configuration for task START[n] */ + #define MVDMA_SUBSCRIBE_START_MaxCount (8UL) /*!< Max size of SUBSCRIBE_START[8] array. */ + #define MVDMA_SUBSCRIBE_START_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_START[8] array. */ + #define MVDMA_SUBSCRIBE_START_MinIndex (0UL) /*!< Min index of SUBSCRIBE_START[8] array. */ + #define MVDMA_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START[n] will subscribe to */ + #define MVDMA_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define MVDMA_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << MVDMA_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define MVDMA_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define MVDMA_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define MVDMA_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define MVDMA_SUBSCRIBE_START_EN_Msk (0x1UL << MVDMA_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define MVDMA_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MVDMA_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MVDMA_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define MVDMA_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* MVDMA_EVENTS_END: Event indicating that Sink data descriptor list has been completed. */ + #define MVDMA_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Event indicating that Sink data descriptor list has been completed. */ + #define MVDMA_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define MVDMA_EVENTS_END_EVENTS_END_Msk (0x1UL << MVDMA_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define MVDMA_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define MVDMA_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define MVDMA_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_STARTED: Event indicating that the source list processing has started. */ + #define MVDMA_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : Event indicating that the source list processing has started. */ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << MVDMA_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_PAUSED: Event indicating that the data transfer has been paused. */ + #define MVDMA_EVENTS_PAUSED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PAUSED register. */ + +/* EVENTS_PAUSED @Bit 0 : Event indicating that the data transfer has been paused. */ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Pos (0UL) /*!< Position of EVENTS_PAUSED field. */ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Msk (0x1UL << MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Pos) /*!< Bit mask of EVENTS_PAUSED + field.*/ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PAUSED field. */ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PAUSED field. */ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_PAUSED_EVENTS_PAUSED_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_RESET: Event indicating that the peripheral has been reset. */ + #define MVDMA_EVENTS_RESET_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESET register. */ + +/* EVENTS_RESET @Bit 0 : Event indicating that the peripheral has been reset. */ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_Pos (0UL) /*!< Position of EVENTS_RESET field. */ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_Msk (0x1UL << MVDMA_EVENTS_RESET_EVENTS_RESET_Pos) /*!< Bit mask of EVENTS_RESET + field.*/ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESET field. */ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESET field. */ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_RESET_EVENTS_RESET_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_EVENTS_COMPLETED: Event indicating that the operation started by the task START[n] has been completed. Base address for + successive EVENTS_COMPLETED. */ + + #define MVDMA_EVENTS_COMPLETED_MaxCount (8UL) /*!< Max size of EVENTS_COMPLETED[8] array. */ + #define MVDMA_EVENTS_COMPLETED_MaxIndex (7UL) /*!< Max index of EVENTS_COMPLETED[8] array. */ + #define MVDMA_EVENTS_COMPLETED_MinIndex (0UL) /*!< Min index of EVENTS_COMPLETED[8] array. */ + #define MVDMA_EVENTS_COMPLETED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPLETED[8] register. */ + +/* EVENTS_COMPLETED @Bit 0 : Event indicating that the operation started by the task START[n] has been completed. Base address + for successive EVENTS_COMPLETED. */ + + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Pos (0UL) /*!< Position of EVENTS_COMPLETED field. */ + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Msk (0x1UL << MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Pos) /*!< Bit mask of + EVENTS_COMPLETED field.*/ + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPLETED field. */ + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPLETED field. */ + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_NotGenerated (0x0UL) /*!< Event not generated */ + #define MVDMA_EVENTS_COMPLETED_EVENTS_COMPLETED_Generated (0x1UL) /*!< Event generated */ + + +/* MVDMA_PUBLISH_END: Publish configuration for event END */ + #define MVDMA_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define MVDMA_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define MVDMA_PUBLISH_END_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define MVDMA_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define MVDMA_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define MVDMA_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define MVDMA_PUBLISH_END_EN_Msk (0x1UL << MVDMA_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define MVDMA_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MVDMA_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MVDMA_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define MVDMA_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* MVDMA_PUBLISH_COMPLETED: Publish configuration for event COMPLETED[n] */ + #define MVDMA_PUBLISH_COMPLETED_MaxCount (8UL) /*!< Max size of PUBLISH_COMPLETED[8] array. */ + #define MVDMA_PUBLISH_COMPLETED_MaxIndex (7UL) /*!< Max index of PUBLISH_COMPLETED[8] array. */ + #define MVDMA_PUBLISH_COMPLETED_MinIndex (0UL) /*!< Min index of PUBLISH_COMPLETED[8] array. */ + #define MVDMA_PUBLISH_COMPLETED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPLETED[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPLETED[n] will publish to */ + #define MVDMA_PUBLISH_COMPLETED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define MVDMA_PUBLISH_COMPLETED_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_COMPLETED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define MVDMA_PUBLISH_COMPLETED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define MVDMA_PUBLISH_COMPLETED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define MVDMA_PUBLISH_COMPLETED_EN_Pos (31UL) /*!< Position of EN field. */ + #define MVDMA_PUBLISH_COMPLETED_EN_Msk (0x1UL << MVDMA_PUBLISH_COMPLETED_EN_Pos) /*!< Bit mask of EN field. */ + #define MVDMA_PUBLISH_COMPLETED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define MVDMA_PUBLISH_COMPLETED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define MVDMA_PUBLISH_COMPLETED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define MVDMA_PUBLISH_COMPLETED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* MVDMA_INTEN: Enable or disable interrupt */ + #define MVDMA_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* END @Bit 0 : Enable or disable interrupt for event END */ + #define MVDMA_INTEN_END_Pos (0UL) /*!< Position of END field. */ + #define MVDMA_INTEN_END_Msk (0x1UL << MVDMA_INTEN_END_Pos) /*!< Bit mask of END field. */ + #define MVDMA_INTEN_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define MVDMA_INTEN_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define MVDMA_INTEN_END_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_END_Enabled (0x1UL) /*!< Enable */ + +/* STARTED @Bit 1 : Enable or disable interrupt for event STARTED */ + #define MVDMA_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define MVDMA_INTEN_STARTED_Msk (0x1UL << MVDMA_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define MVDMA_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define MVDMA_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define MVDMA_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* PAUSED @Bit 2 : Enable or disable interrupt for event PAUSED */ + #define MVDMA_INTEN_PAUSED_Pos (2UL) /*!< Position of PAUSED field. */ + #define MVDMA_INTEN_PAUSED_Msk (0x1UL << MVDMA_INTEN_PAUSED_Pos) /*!< Bit mask of PAUSED field. */ + #define MVDMA_INTEN_PAUSED_Min (0x0UL) /*!< Min enumerator value of PAUSED field. */ + #define MVDMA_INTEN_PAUSED_Max (0x1UL) /*!< Max enumerator value of PAUSED field. */ + #define MVDMA_INTEN_PAUSED_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_PAUSED_Enabled (0x1UL) /*!< Enable */ + +/* RESET @Bit 3 : Enable or disable interrupt for event RESET */ + #define MVDMA_INTEN_RESET_Pos (3UL) /*!< Position of RESET field. */ + #define MVDMA_INTEN_RESET_Msk (0x1UL << MVDMA_INTEN_RESET_Pos) /*!< Bit mask of RESET field. */ + #define MVDMA_INTEN_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define MVDMA_INTEN_RESET_Max (0x1UL) /*!< Max enumerator value of RESET field. */ + #define MVDMA_INTEN_RESET_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_RESET_Enabled (0x1UL) /*!< Enable */ + +/* SOURCEBUSERROR @Bit 4 : Enable or disable interrupt for event SOURCEBUSERROR */ + #define MVDMA_INTEN_SOURCEBUSERROR_Pos (4UL) /*!< Position of SOURCEBUSERROR field. */ + #define MVDMA_INTEN_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTEN_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field. */ + #define MVDMA_INTEN_SOURCEBUSERROR_Min (0x0UL) /*!< Min enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTEN_SOURCEBUSERROR_Max (0x1UL) /*!< Max enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTEN_SOURCEBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_SOURCEBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* SOURCESELECTJOBDONE @Bit 5 : Enable or disable interrupt for event SOURCESELECTJOBDONE */ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Pos (5UL) /*!< Position of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTEN_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of + SOURCESELECTJOBDONE field.*/ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Enable */ + +/* SINKBUSERROR @Bit 6 : Enable or disable interrupt for event SINKBUSERROR */ + #define MVDMA_INTEN_SINKBUSERROR_Pos (6UL) /*!< Position of SINKBUSERROR field. */ + #define MVDMA_INTEN_SINKBUSERROR_Msk (0x1UL << MVDMA_INTEN_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field. */ + #define MVDMA_INTEN_SINKBUSERROR_Min (0x0UL) /*!< Min enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTEN_SINKBUSERROR_Max (0x1UL) /*!< Max enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTEN_SINKBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_SINKBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* SINKSELECTJOBDONE @Bit 7 : Enable or disable interrupt for event SINKSELECTJOBDONE */ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field. */ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTEN_SINKSELECTJOBDONE_Pos) /*!< Bit mask of SINKSELECTJOBDONE + field.*/ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED0 @Bit 8 : Enable or disable interrupt for event COMPLETED[0] */ + #define MVDMA_INTEN_COMPLETED0_Pos (8UL) /*!< Position of COMPLETED0 field. */ + #define MVDMA_INTEN_COMPLETED0_Msk (0x1UL << MVDMA_INTEN_COMPLETED0_Pos) /*!< Bit mask of COMPLETED0 field. */ + #define MVDMA_INTEN_COMPLETED0_Min (0x0UL) /*!< Min enumerator value of COMPLETED0 field. */ + #define MVDMA_INTEN_COMPLETED0_Max (0x1UL) /*!< Max enumerator value of COMPLETED0 field. */ + #define MVDMA_INTEN_COMPLETED0_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED0_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED1 @Bit 9 : Enable or disable interrupt for event COMPLETED[1] */ + #define MVDMA_INTEN_COMPLETED1_Pos (9UL) /*!< Position of COMPLETED1 field. */ + #define MVDMA_INTEN_COMPLETED1_Msk (0x1UL << MVDMA_INTEN_COMPLETED1_Pos) /*!< Bit mask of COMPLETED1 field. */ + #define MVDMA_INTEN_COMPLETED1_Min (0x0UL) /*!< Min enumerator value of COMPLETED1 field. */ + #define MVDMA_INTEN_COMPLETED1_Max (0x1UL) /*!< Max enumerator value of COMPLETED1 field. */ + #define MVDMA_INTEN_COMPLETED1_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED1_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED2 @Bit 10 : Enable or disable interrupt for event COMPLETED[2] */ + #define MVDMA_INTEN_COMPLETED2_Pos (10UL) /*!< Position of COMPLETED2 field. */ + #define MVDMA_INTEN_COMPLETED2_Msk (0x1UL << MVDMA_INTEN_COMPLETED2_Pos) /*!< Bit mask of COMPLETED2 field. */ + #define MVDMA_INTEN_COMPLETED2_Min (0x0UL) /*!< Min enumerator value of COMPLETED2 field. */ + #define MVDMA_INTEN_COMPLETED2_Max (0x1UL) /*!< Max enumerator value of COMPLETED2 field. */ + #define MVDMA_INTEN_COMPLETED2_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED2_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED3 @Bit 11 : Enable or disable interrupt for event COMPLETED[3] */ + #define MVDMA_INTEN_COMPLETED3_Pos (11UL) /*!< Position of COMPLETED3 field. */ + #define MVDMA_INTEN_COMPLETED3_Msk (0x1UL << MVDMA_INTEN_COMPLETED3_Pos) /*!< Bit mask of COMPLETED3 field. */ + #define MVDMA_INTEN_COMPLETED3_Min (0x0UL) /*!< Min enumerator value of COMPLETED3 field. */ + #define MVDMA_INTEN_COMPLETED3_Max (0x1UL) /*!< Max enumerator value of COMPLETED3 field. */ + #define MVDMA_INTEN_COMPLETED3_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED3_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED4 @Bit 12 : Enable or disable interrupt for event COMPLETED[4] */ + #define MVDMA_INTEN_COMPLETED4_Pos (12UL) /*!< Position of COMPLETED4 field. */ + #define MVDMA_INTEN_COMPLETED4_Msk (0x1UL << MVDMA_INTEN_COMPLETED4_Pos) /*!< Bit mask of COMPLETED4 field. */ + #define MVDMA_INTEN_COMPLETED4_Min (0x0UL) /*!< Min enumerator value of COMPLETED4 field. */ + #define MVDMA_INTEN_COMPLETED4_Max (0x1UL) /*!< Max enumerator value of COMPLETED4 field. */ + #define MVDMA_INTEN_COMPLETED4_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED4_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED5 @Bit 13 : Enable or disable interrupt for event COMPLETED[5] */ + #define MVDMA_INTEN_COMPLETED5_Pos (13UL) /*!< Position of COMPLETED5 field. */ + #define MVDMA_INTEN_COMPLETED5_Msk (0x1UL << MVDMA_INTEN_COMPLETED5_Pos) /*!< Bit mask of COMPLETED5 field. */ + #define MVDMA_INTEN_COMPLETED5_Min (0x0UL) /*!< Min enumerator value of COMPLETED5 field. */ + #define MVDMA_INTEN_COMPLETED5_Max (0x1UL) /*!< Max enumerator value of COMPLETED5 field. */ + #define MVDMA_INTEN_COMPLETED5_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED5_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED6 @Bit 14 : Enable or disable interrupt for event COMPLETED[6] */ + #define MVDMA_INTEN_COMPLETED6_Pos (14UL) /*!< Position of COMPLETED6 field. */ + #define MVDMA_INTEN_COMPLETED6_Msk (0x1UL << MVDMA_INTEN_COMPLETED6_Pos) /*!< Bit mask of COMPLETED6 field. */ + #define MVDMA_INTEN_COMPLETED6_Min (0x0UL) /*!< Min enumerator value of COMPLETED6 field. */ + #define MVDMA_INTEN_COMPLETED6_Max (0x1UL) /*!< Max enumerator value of COMPLETED6 field. */ + #define MVDMA_INTEN_COMPLETED6_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED6_Enabled (0x1UL) /*!< Enable */ + +/* COMPLETED7 @Bit 15 : Enable or disable interrupt for event COMPLETED[7] */ + #define MVDMA_INTEN_COMPLETED7_Pos (15UL) /*!< Position of COMPLETED7 field. */ + #define MVDMA_INTEN_COMPLETED7_Msk (0x1UL << MVDMA_INTEN_COMPLETED7_Pos) /*!< Bit mask of COMPLETED7 field. */ + #define MVDMA_INTEN_COMPLETED7_Min (0x0UL) /*!< Min enumerator value of COMPLETED7 field. */ + #define MVDMA_INTEN_COMPLETED7_Max (0x1UL) /*!< Max enumerator value of COMPLETED7 field. */ + #define MVDMA_INTEN_COMPLETED7_Disabled (0x0UL) /*!< Disable */ + #define MVDMA_INTEN_COMPLETED7_Enabled (0x1UL) /*!< Enable */ + + +/* MVDMA_INTENSET: Enable interrupt */ + #define MVDMA_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 0 : Write '1' to enable interrupt for event END */ + #define MVDMA_INTENSET_END_Pos (0UL) /*!< Position of END field. */ + #define MVDMA_INTENSET_END_Msk (0x1UL << MVDMA_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define MVDMA_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define MVDMA_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define MVDMA_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 1 : Write '1' to enable interrupt for event STARTED */ + #define MVDMA_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define MVDMA_INTENSET_STARTED_Msk (0x1UL << MVDMA_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define MVDMA_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define MVDMA_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define MVDMA_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAUSED @Bit 2 : Write '1' to enable interrupt for event PAUSED */ + #define MVDMA_INTENSET_PAUSED_Pos (2UL) /*!< Position of PAUSED field. */ + #define MVDMA_INTENSET_PAUSED_Msk (0x1UL << MVDMA_INTENSET_PAUSED_Pos) /*!< Bit mask of PAUSED field. */ + #define MVDMA_INTENSET_PAUSED_Min (0x0UL) /*!< Min enumerator value of PAUSED field. */ + #define MVDMA_INTENSET_PAUSED_Max (0x1UL) /*!< Max enumerator value of PAUSED field. */ + #define MVDMA_INTENSET_PAUSED_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_PAUSED_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_PAUSED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESET @Bit 3 : Write '1' to enable interrupt for event RESET */ + #define MVDMA_INTENSET_RESET_Pos (3UL) /*!< Position of RESET field. */ + #define MVDMA_INTENSET_RESET_Msk (0x1UL << MVDMA_INTENSET_RESET_Pos) /*!< Bit mask of RESET field. */ + #define MVDMA_INTENSET_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define MVDMA_INTENSET_RESET_Max (0x1UL) /*!< Max enumerator value of RESET field. */ + #define MVDMA_INTENSET_RESET_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_RESET_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_RESET_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SOURCEBUSERROR @Bit 4 : Write '1' to enable interrupt for event SOURCEBUSERROR */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Pos (4UL) /*!< Position of SOURCEBUSERROR field. */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTENSET_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.*/ + #define MVDMA_INTENSET_SOURCEBUSERROR_Min (0x0UL) /*!< Min enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Max (0x1UL) /*!< Max enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_SOURCEBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SOURCESELECTJOBDONE @Bit 5 : Write '1' to enable interrupt for event SOURCESELECTJOBDONE */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Pos (5UL) /*!< Position of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTENSET_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of + SOURCESELECTJOBDONE field.*/ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SINKBUSERROR @Bit 6 : Write '1' to enable interrupt for event SINKBUSERROR */ + #define MVDMA_INTENSET_SINKBUSERROR_Pos (6UL) /*!< Position of SINKBUSERROR field. */ + #define MVDMA_INTENSET_SINKBUSERROR_Msk (0x1UL << MVDMA_INTENSET_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field. */ + #define MVDMA_INTENSET_SINKBUSERROR_Min (0x0UL) /*!< Min enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTENSET_SINKBUSERROR_Max (0x1UL) /*!< Max enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTENSET_SINKBUSERROR_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_SINKBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_SINKBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SINKSELECTJOBDONE @Bit 7 : Write '1' to enable interrupt for event SINKSELECTJOBDONE */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTENSET_SINKSELECTJOBDONE_Pos) /*!< Bit mask of + SINKSELECTJOBDONE field.*/ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED0 @Bit 8 : Write '1' to enable interrupt for event COMPLETED[0] */ + #define MVDMA_INTENSET_COMPLETED0_Pos (8UL) /*!< Position of COMPLETED0 field. */ + #define MVDMA_INTENSET_COMPLETED0_Msk (0x1UL << MVDMA_INTENSET_COMPLETED0_Pos) /*!< Bit mask of COMPLETED0 field. */ + #define MVDMA_INTENSET_COMPLETED0_Min (0x0UL) /*!< Min enumerator value of COMPLETED0 field. */ + #define MVDMA_INTENSET_COMPLETED0_Max (0x1UL) /*!< Max enumerator value of COMPLETED0 field. */ + #define MVDMA_INTENSET_COMPLETED0_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED1 @Bit 9 : Write '1' to enable interrupt for event COMPLETED[1] */ + #define MVDMA_INTENSET_COMPLETED1_Pos (9UL) /*!< Position of COMPLETED1 field. */ + #define MVDMA_INTENSET_COMPLETED1_Msk (0x1UL << MVDMA_INTENSET_COMPLETED1_Pos) /*!< Bit mask of COMPLETED1 field. */ + #define MVDMA_INTENSET_COMPLETED1_Min (0x0UL) /*!< Min enumerator value of COMPLETED1 field. */ + #define MVDMA_INTENSET_COMPLETED1_Max (0x1UL) /*!< Max enumerator value of COMPLETED1 field. */ + #define MVDMA_INTENSET_COMPLETED1_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED2 @Bit 10 : Write '1' to enable interrupt for event COMPLETED[2] */ + #define MVDMA_INTENSET_COMPLETED2_Pos (10UL) /*!< Position of COMPLETED2 field. */ + #define MVDMA_INTENSET_COMPLETED2_Msk (0x1UL << MVDMA_INTENSET_COMPLETED2_Pos) /*!< Bit mask of COMPLETED2 field. */ + #define MVDMA_INTENSET_COMPLETED2_Min (0x0UL) /*!< Min enumerator value of COMPLETED2 field. */ + #define MVDMA_INTENSET_COMPLETED2_Max (0x1UL) /*!< Max enumerator value of COMPLETED2 field. */ + #define MVDMA_INTENSET_COMPLETED2_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED3 @Bit 11 : Write '1' to enable interrupt for event COMPLETED[3] */ + #define MVDMA_INTENSET_COMPLETED3_Pos (11UL) /*!< Position of COMPLETED3 field. */ + #define MVDMA_INTENSET_COMPLETED3_Msk (0x1UL << MVDMA_INTENSET_COMPLETED3_Pos) /*!< Bit mask of COMPLETED3 field. */ + #define MVDMA_INTENSET_COMPLETED3_Min (0x0UL) /*!< Min enumerator value of COMPLETED3 field. */ + #define MVDMA_INTENSET_COMPLETED3_Max (0x1UL) /*!< Max enumerator value of COMPLETED3 field. */ + #define MVDMA_INTENSET_COMPLETED3_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED4 @Bit 12 : Write '1' to enable interrupt for event COMPLETED[4] */ + #define MVDMA_INTENSET_COMPLETED4_Pos (12UL) /*!< Position of COMPLETED4 field. */ + #define MVDMA_INTENSET_COMPLETED4_Msk (0x1UL << MVDMA_INTENSET_COMPLETED4_Pos) /*!< Bit mask of COMPLETED4 field. */ + #define MVDMA_INTENSET_COMPLETED4_Min (0x0UL) /*!< Min enumerator value of COMPLETED4 field. */ + #define MVDMA_INTENSET_COMPLETED4_Max (0x1UL) /*!< Max enumerator value of COMPLETED4 field. */ + #define MVDMA_INTENSET_COMPLETED4_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED5 @Bit 13 : Write '1' to enable interrupt for event COMPLETED[5] */ + #define MVDMA_INTENSET_COMPLETED5_Pos (13UL) /*!< Position of COMPLETED5 field. */ + #define MVDMA_INTENSET_COMPLETED5_Msk (0x1UL << MVDMA_INTENSET_COMPLETED5_Pos) /*!< Bit mask of COMPLETED5 field. */ + #define MVDMA_INTENSET_COMPLETED5_Min (0x0UL) /*!< Min enumerator value of COMPLETED5 field. */ + #define MVDMA_INTENSET_COMPLETED5_Max (0x1UL) /*!< Max enumerator value of COMPLETED5 field. */ + #define MVDMA_INTENSET_COMPLETED5_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED6 @Bit 14 : Write '1' to enable interrupt for event COMPLETED[6] */ + #define MVDMA_INTENSET_COMPLETED6_Pos (14UL) /*!< Position of COMPLETED6 field. */ + #define MVDMA_INTENSET_COMPLETED6_Msk (0x1UL << MVDMA_INTENSET_COMPLETED6_Pos) /*!< Bit mask of COMPLETED6 field. */ + #define MVDMA_INTENSET_COMPLETED6_Min (0x0UL) /*!< Min enumerator value of COMPLETED6 field. */ + #define MVDMA_INTENSET_COMPLETED6_Max (0x1UL) /*!< Max enumerator value of COMPLETED6 field. */ + #define MVDMA_INTENSET_COMPLETED6_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED7 @Bit 15 : Write '1' to enable interrupt for event COMPLETED[7] */ + #define MVDMA_INTENSET_COMPLETED7_Pos (15UL) /*!< Position of COMPLETED7 field. */ + #define MVDMA_INTENSET_COMPLETED7_Msk (0x1UL << MVDMA_INTENSET_COMPLETED7_Pos) /*!< Bit mask of COMPLETED7 field. */ + #define MVDMA_INTENSET_COMPLETED7_Min (0x0UL) /*!< Min enumerator value of COMPLETED7 field. */ + #define MVDMA_INTENSET_COMPLETED7_Max (0x1UL) /*!< Max enumerator value of COMPLETED7 field. */ + #define MVDMA_INTENSET_COMPLETED7_Set (0x1UL) /*!< Enable */ + #define MVDMA_INTENSET_COMPLETED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENSET_COMPLETED7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* MVDMA_INTENCLR: Disable interrupt */ + #define MVDMA_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 0 : Write '1' to disable interrupt for event END */ + #define MVDMA_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ + #define MVDMA_INTENCLR_END_Msk (0x1UL << MVDMA_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define MVDMA_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define MVDMA_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define MVDMA_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STARTED @Bit 1 : Write '1' to disable interrupt for event STARTED */ + #define MVDMA_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define MVDMA_INTENCLR_STARTED_Msk (0x1UL << MVDMA_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define MVDMA_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define MVDMA_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define MVDMA_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAUSED @Bit 2 : Write '1' to disable interrupt for event PAUSED */ + #define MVDMA_INTENCLR_PAUSED_Pos (2UL) /*!< Position of PAUSED field. */ + #define MVDMA_INTENCLR_PAUSED_Msk (0x1UL << MVDMA_INTENCLR_PAUSED_Pos) /*!< Bit mask of PAUSED field. */ + #define MVDMA_INTENCLR_PAUSED_Min (0x0UL) /*!< Min enumerator value of PAUSED field. */ + #define MVDMA_INTENCLR_PAUSED_Max (0x1UL) /*!< Max enumerator value of PAUSED field. */ + #define MVDMA_INTENCLR_PAUSED_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_PAUSED_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_PAUSED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESET @Bit 3 : Write '1' to disable interrupt for event RESET */ + #define MVDMA_INTENCLR_RESET_Pos (3UL) /*!< Position of RESET field. */ + #define MVDMA_INTENCLR_RESET_Msk (0x1UL << MVDMA_INTENCLR_RESET_Pos) /*!< Bit mask of RESET field. */ + #define MVDMA_INTENCLR_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define MVDMA_INTENCLR_RESET_Max (0x1UL) /*!< Max enumerator value of RESET field. */ + #define MVDMA_INTENCLR_RESET_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_RESET_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_RESET_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SOURCEBUSERROR @Bit 4 : Write '1' to disable interrupt for event SOURCEBUSERROR */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Pos (4UL) /*!< Position of SOURCEBUSERROR field. */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTENCLR_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.*/ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Min (0x0UL) /*!< Min enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Max (0x1UL) /*!< Max enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_SOURCEBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SOURCESELECTJOBDONE @Bit 5 : Write '1' to disable interrupt for event SOURCESELECTJOBDONE */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Pos (5UL) /*!< Position of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTENCLR_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of + SOURCESELECTJOBDONE field.*/ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SINKBUSERROR @Bit 6 : Write '1' to disable interrupt for event SINKBUSERROR */ + #define MVDMA_INTENCLR_SINKBUSERROR_Pos (6UL) /*!< Position of SINKBUSERROR field. */ + #define MVDMA_INTENCLR_SINKBUSERROR_Msk (0x1UL << MVDMA_INTENCLR_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field. */ + #define MVDMA_INTENCLR_SINKBUSERROR_Min (0x0UL) /*!< Min enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTENCLR_SINKBUSERROR_Max (0x1UL) /*!< Max enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTENCLR_SINKBUSERROR_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_SINKBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_SINKBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SINKSELECTJOBDONE @Bit 7 : Write '1' to disable interrupt for event SINKSELECTJOBDONE */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTENCLR_SINKSELECTJOBDONE_Pos) /*!< Bit mask of + SINKSELECTJOBDONE field.*/ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED0 @Bit 8 : Write '1' to disable interrupt for event COMPLETED[0] */ + #define MVDMA_INTENCLR_COMPLETED0_Pos (8UL) /*!< Position of COMPLETED0 field. */ + #define MVDMA_INTENCLR_COMPLETED0_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED0_Pos) /*!< Bit mask of COMPLETED0 field. */ + #define MVDMA_INTENCLR_COMPLETED0_Min (0x0UL) /*!< Min enumerator value of COMPLETED0 field. */ + #define MVDMA_INTENCLR_COMPLETED0_Max (0x1UL) /*!< Max enumerator value of COMPLETED0 field. */ + #define MVDMA_INTENCLR_COMPLETED0_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED1 @Bit 9 : Write '1' to disable interrupt for event COMPLETED[1] */ + #define MVDMA_INTENCLR_COMPLETED1_Pos (9UL) /*!< Position of COMPLETED1 field. */ + #define MVDMA_INTENCLR_COMPLETED1_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED1_Pos) /*!< Bit mask of COMPLETED1 field. */ + #define MVDMA_INTENCLR_COMPLETED1_Min (0x0UL) /*!< Min enumerator value of COMPLETED1 field. */ + #define MVDMA_INTENCLR_COMPLETED1_Max (0x1UL) /*!< Max enumerator value of COMPLETED1 field. */ + #define MVDMA_INTENCLR_COMPLETED1_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED2 @Bit 10 : Write '1' to disable interrupt for event COMPLETED[2] */ + #define MVDMA_INTENCLR_COMPLETED2_Pos (10UL) /*!< Position of COMPLETED2 field. */ + #define MVDMA_INTENCLR_COMPLETED2_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED2_Pos) /*!< Bit mask of COMPLETED2 field. */ + #define MVDMA_INTENCLR_COMPLETED2_Min (0x0UL) /*!< Min enumerator value of COMPLETED2 field. */ + #define MVDMA_INTENCLR_COMPLETED2_Max (0x1UL) /*!< Max enumerator value of COMPLETED2 field. */ + #define MVDMA_INTENCLR_COMPLETED2_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED3 @Bit 11 : Write '1' to disable interrupt for event COMPLETED[3] */ + #define MVDMA_INTENCLR_COMPLETED3_Pos (11UL) /*!< Position of COMPLETED3 field. */ + #define MVDMA_INTENCLR_COMPLETED3_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED3_Pos) /*!< Bit mask of COMPLETED3 field. */ + #define MVDMA_INTENCLR_COMPLETED3_Min (0x0UL) /*!< Min enumerator value of COMPLETED3 field. */ + #define MVDMA_INTENCLR_COMPLETED3_Max (0x1UL) /*!< Max enumerator value of COMPLETED3 field. */ + #define MVDMA_INTENCLR_COMPLETED3_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED4 @Bit 12 : Write '1' to disable interrupt for event COMPLETED[4] */ + #define MVDMA_INTENCLR_COMPLETED4_Pos (12UL) /*!< Position of COMPLETED4 field. */ + #define MVDMA_INTENCLR_COMPLETED4_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED4_Pos) /*!< Bit mask of COMPLETED4 field. */ + #define MVDMA_INTENCLR_COMPLETED4_Min (0x0UL) /*!< Min enumerator value of COMPLETED4 field. */ + #define MVDMA_INTENCLR_COMPLETED4_Max (0x1UL) /*!< Max enumerator value of COMPLETED4 field. */ + #define MVDMA_INTENCLR_COMPLETED4_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED5 @Bit 13 : Write '1' to disable interrupt for event COMPLETED[5] */ + #define MVDMA_INTENCLR_COMPLETED5_Pos (13UL) /*!< Position of COMPLETED5 field. */ + #define MVDMA_INTENCLR_COMPLETED5_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED5_Pos) /*!< Bit mask of COMPLETED5 field. */ + #define MVDMA_INTENCLR_COMPLETED5_Min (0x0UL) /*!< Min enumerator value of COMPLETED5 field. */ + #define MVDMA_INTENCLR_COMPLETED5_Max (0x1UL) /*!< Max enumerator value of COMPLETED5 field. */ + #define MVDMA_INTENCLR_COMPLETED5_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED6 @Bit 14 : Write '1' to disable interrupt for event COMPLETED[6] */ + #define MVDMA_INTENCLR_COMPLETED6_Pos (14UL) /*!< Position of COMPLETED6 field. */ + #define MVDMA_INTENCLR_COMPLETED6_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED6_Pos) /*!< Bit mask of COMPLETED6 field. */ + #define MVDMA_INTENCLR_COMPLETED6_Min (0x0UL) /*!< Min enumerator value of COMPLETED6 field. */ + #define MVDMA_INTENCLR_COMPLETED6_Max (0x1UL) /*!< Max enumerator value of COMPLETED6 field. */ + #define MVDMA_INTENCLR_COMPLETED6_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPLETED7 @Bit 15 : Write '1' to disable interrupt for event COMPLETED[7] */ + #define MVDMA_INTENCLR_COMPLETED7_Pos (15UL) /*!< Position of COMPLETED7 field. */ + #define MVDMA_INTENCLR_COMPLETED7_Msk (0x1UL << MVDMA_INTENCLR_COMPLETED7_Pos) /*!< Bit mask of COMPLETED7 field. */ + #define MVDMA_INTENCLR_COMPLETED7_Min (0x0UL) /*!< Min enumerator value of COMPLETED7 field. */ + #define MVDMA_INTENCLR_COMPLETED7_Max (0x1UL) /*!< Max enumerator value of COMPLETED7 field. */ + #define MVDMA_INTENCLR_COMPLETED7_Clear (0x1UL) /*!< Disable */ + #define MVDMA_INTENCLR_COMPLETED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define MVDMA_INTENCLR_COMPLETED7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* MVDMA_INTPEND: Pending interrupts */ + #define MVDMA_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* END @Bit 0 : Read pending status of interrupt for event END */ + #define MVDMA_INTPEND_END_Pos (0UL) /*!< Position of END field. */ + #define MVDMA_INTPEND_END_Msk (0x1UL << MVDMA_INTPEND_END_Pos) /*!< Bit mask of END field. */ + #define MVDMA_INTPEND_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define MVDMA_INTPEND_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define MVDMA_INTPEND_END_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_END_Pending (0x1UL) /*!< Read: Pending */ + +/* STARTED @Bit 1 : Read pending status of interrupt for event STARTED */ + #define MVDMA_INTPEND_STARTED_Pos (1UL) /*!< Position of STARTED field. */ + #define MVDMA_INTPEND_STARTED_Msk (0x1UL << MVDMA_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define MVDMA_INTPEND_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define MVDMA_INTPEND_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define MVDMA_INTPEND_STARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_STARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* PAUSED @Bit 2 : Read pending status of interrupt for event PAUSED */ + #define MVDMA_INTPEND_PAUSED_Pos (2UL) /*!< Position of PAUSED field. */ + #define MVDMA_INTPEND_PAUSED_Msk (0x1UL << MVDMA_INTPEND_PAUSED_Pos) /*!< Bit mask of PAUSED field. */ + #define MVDMA_INTPEND_PAUSED_Min (0x0UL) /*!< Min enumerator value of PAUSED field. */ + #define MVDMA_INTPEND_PAUSED_Max (0x1UL) /*!< Max enumerator value of PAUSED field. */ + #define MVDMA_INTPEND_PAUSED_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_PAUSED_Pending (0x1UL) /*!< Read: Pending */ + +/* RESET @Bit 3 : Read pending status of interrupt for event RESET */ + #define MVDMA_INTPEND_RESET_Pos (3UL) /*!< Position of RESET field. */ + #define MVDMA_INTPEND_RESET_Msk (0x1UL << MVDMA_INTPEND_RESET_Pos) /*!< Bit mask of RESET field. */ + #define MVDMA_INTPEND_RESET_Min (0x0UL) /*!< Min enumerator value of RESET field. */ + #define MVDMA_INTPEND_RESET_Max (0x1UL) /*!< Max enumerator value of RESET field. */ + #define MVDMA_INTPEND_RESET_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_RESET_Pending (0x1UL) /*!< Read: Pending */ + +/* SOURCEBUSERROR @Bit 4 : Read pending status of interrupt for event SOURCEBUSERROR */ + #define MVDMA_INTPEND_SOURCEBUSERROR_Pos (4UL) /*!< Position of SOURCEBUSERROR field. */ + #define MVDMA_INTPEND_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTPEND_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field. */ + #define MVDMA_INTPEND_SOURCEBUSERROR_Min (0x0UL) /*!< Min enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTPEND_SOURCEBUSERROR_Max (0x1UL) /*!< Max enumerator value of SOURCEBUSERROR field. */ + #define MVDMA_INTPEND_SOURCEBUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_SOURCEBUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* SOURCESELECTJOBDONE @Bit 5 : Read pending status of interrupt for event SOURCESELECTJOBDONE */ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Pos (5UL) /*!< Position of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTPEND_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of + SOURCESELECTJOBDONE field.*/ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field. */ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Pending (0x1UL) /*!< Read: Pending */ + +/* SINKBUSERROR @Bit 6 : Read pending status of interrupt for event SINKBUSERROR */ + #define MVDMA_INTPEND_SINKBUSERROR_Pos (6UL) /*!< Position of SINKBUSERROR field. */ + #define MVDMA_INTPEND_SINKBUSERROR_Msk (0x1UL << MVDMA_INTPEND_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field. */ + #define MVDMA_INTPEND_SINKBUSERROR_Min (0x0UL) /*!< Min enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTPEND_SINKBUSERROR_Max (0x1UL) /*!< Max enumerator value of SINKBUSERROR field. */ + #define MVDMA_INTPEND_SINKBUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_SINKBUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* SINKSELECTJOBDONE @Bit 7 : Read pending status of interrupt for event SINKSELECTJOBDONE */ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field. */ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTPEND_SINKSELECTJOBDONE_Pos) /*!< Bit mask of SINKSELECTJOBDONE + field.*/ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field. */ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_SINKSELECTJOBDONE_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED0 @Bit 8 : Read pending status of interrupt for event COMPLETED[0] */ + #define MVDMA_INTPEND_COMPLETED0_Pos (8UL) /*!< Position of COMPLETED0 field. */ + #define MVDMA_INTPEND_COMPLETED0_Msk (0x1UL << MVDMA_INTPEND_COMPLETED0_Pos) /*!< Bit mask of COMPLETED0 field. */ + #define MVDMA_INTPEND_COMPLETED0_Min (0x0UL) /*!< Min enumerator value of COMPLETED0 field. */ + #define MVDMA_INTPEND_COMPLETED0_Max (0x1UL) /*!< Max enumerator value of COMPLETED0 field. */ + #define MVDMA_INTPEND_COMPLETED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED1 @Bit 9 : Read pending status of interrupt for event COMPLETED[1] */ + #define MVDMA_INTPEND_COMPLETED1_Pos (9UL) /*!< Position of COMPLETED1 field. */ + #define MVDMA_INTPEND_COMPLETED1_Msk (0x1UL << MVDMA_INTPEND_COMPLETED1_Pos) /*!< Bit mask of COMPLETED1 field. */ + #define MVDMA_INTPEND_COMPLETED1_Min (0x0UL) /*!< Min enumerator value of COMPLETED1 field. */ + #define MVDMA_INTPEND_COMPLETED1_Max (0x1UL) /*!< Max enumerator value of COMPLETED1 field. */ + #define MVDMA_INTPEND_COMPLETED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED2 @Bit 10 : Read pending status of interrupt for event COMPLETED[2] */ + #define MVDMA_INTPEND_COMPLETED2_Pos (10UL) /*!< Position of COMPLETED2 field. */ + #define MVDMA_INTPEND_COMPLETED2_Msk (0x1UL << MVDMA_INTPEND_COMPLETED2_Pos) /*!< Bit mask of COMPLETED2 field. */ + #define MVDMA_INTPEND_COMPLETED2_Min (0x0UL) /*!< Min enumerator value of COMPLETED2 field. */ + #define MVDMA_INTPEND_COMPLETED2_Max (0x1UL) /*!< Max enumerator value of COMPLETED2 field. */ + #define MVDMA_INTPEND_COMPLETED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED3 @Bit 11 : Read pending status of interrupt for event COMPLETED[3] */ + #define MVDMA_INTPEND_COMPLETED3_Pos (11UL) /*!< Position of COMPLETED3 field. */ + #define MVDMA_INTPEND_COMPLETED3_Msk (0x1UL << MVDMA_INTPEND_COMPLETED3_Pos) /*!< Bit mask of COMPLETED3 field. */ + #define MVDMA_INTPEND_COMPLETED3_Min (0x0UL) /*!< Min enumerator value of COMPLETED3 field. */ + #define MVDMA_INTPEND_COMPLETED3_Max (0x1UL) /*!< Max enumerator value of COMPLETED3 field. */ + #define MVDMA_INTPEND_COMPLETED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED3_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED4 @Bit 12 : Read pending status of interrupt for event COMPLETED[4] */ + #define MVDMA_INTPEND_COMPLETED4_Pos (12UL) /*!< Position of COMPLETED4 field. */ + #define MVDMA_INTPEND_COMPLETED4_Msk (0x1UL << MVDMA_INTPEND_COMPLETED4_Pos) /*!< Bit mask of COMPLETED4 field. */ + #define MVDMA_INTPEND_COMPLETED4_Min (0x0UL) /*!< Min enumerator value of COMPLETED4 field. */ + #define MVDMA_INTPEND_COMPLETED4_Max (0x1UL) /*!< Max enumerator value of COMPLETED4 field. */ + #define MVDMA_INTPEND_COMPLETED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED4_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED5 @Bit 13 : Read pending status of interrupt for event COMPLETED[5] */ + #define MVDMA_INTPEND_COMPLETED5_Pos (13UL) /*!< Position of COMPLETED5 field. */ + #define MVDMA_INTPEND_COMPLETED5_Msk (0x1UL << MVDMA_INTPEND_COMPLETED5_Pos) /*!< Bit mask of COMPLETED5 field. */ + #define MVDMA_INTPEND_COMPLETED5_Min (0x0UL) /*!< Min enumerator value of COMPLETED5 field. */ + #define MVDMA_INTPEND_COMPLETED5_Max (0x1UL) /*!< Max enumerator value of COMPLETED5 field. */ + #define MVDMA_INTPEND_COMPLETED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED5_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED6 @Bit 14 : Read pending status of interrupt for event COMPLETED[6] */ + #define MVDMA_INTPEND_COMPLETED6_Pos (14UL) /*!< Position of COMPLETED6 field. */ + #define MVDMA_INTPEND_COMPLETED6_Msk (0x1UL << MVDMA_INTPEND_COMPLETED6_Pos) /*!< Bit mask of COMPLETED6 field. */ + #define MVDMA_INTPEND_COMPLETED6_Min (0x0UL) /*!< Min enumerator value of COMPLETED6 field. */ + #define MVDMA_INTPEND_COMPLETED6_Max (0x1UL) /*!< Max enumerator value of COMPLETED6 field. */ + #define MVDMA_INTPEND_COMPLETED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED6_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPLETED7 @Bit 15 : Read pending status of interrupt for event COMPLETED[7] */ + #define MVDMA_INTPEND_COMPLETED7_Pos (15UL) /*!< Position of COMPLETED7 field. */ + #define MVDMA_INTPEND_COMPLETED7_Msk (0x1UL << MVDMA_INTPEND_COMPLETED7_Pos) /*!< Bit mask of COMPLETED7 field. */ + #define MVDMA_INTPEND_COMPLETED7_Min (0x0UL) /*!< Min enumerator value of COMPLETED7 field. */ + #define MVDMA_INTPEND_COMPLETED7_Max (0x1UL) /*!< Max enumerator value of COMPLETED7 field. */ + #define MVDMA_INTPEND_COMPLETED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define MVDMA_INTPEND_COMPLETED7_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct PDM_PSEL ===================================================== */ +/** + * @brief PSEL [PDM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} NRF_PDM_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* PDM_PSEL_CLK: Pin number configuration for PDM CLK signal */ + #define PDM_PSEL_CLK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CLK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PDM_PSEL_CLK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PDM_PSEL_CLK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PDM_PSEL_CLK_PORT_Msk (0xFUL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PDM_PSEL_CLK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PDM_PSEL_CLK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* PDM_PSEL_DIN: Pin number configuration for PDM DIN signal */ + #define PDM_PSEL_DIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PDM_PSEL_DIN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PDM_PSEL_DIN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PDM_PSEL_DIN_PORT_Msk (0xFUL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PDM_PSEL_DIN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PDM_PSEL_DIN_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ==================================================== Struct PDM_SAMPLE ==================================================== */ +/** + * @brief SAMPLE [PDM_SAMPLE] (unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode*/ + __IM uint32_t RESERVED; +} NRF_PDM_SAMPLE_Type; /*!< Size = 12 (0x00C) */ + +/* PDM_SAMPLE_PTR: RAM address pointer to write samples to with EasyDMA */ + #define PDM_SAMPLE_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* SAMPLEPTR @Bits 0..31 : Address to write PDM samples to over DMA */ + #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ + #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + + +/* PDM_SAMPLE_MAXCNT: Number of samples to allocate memory for in EasyDMA mode */ + #define PDM_SAMPLE_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* BUFFSIZE @Bits 0..14 : Length of DMA RAM allocation in number of samples */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Min (0x0000UL) /*!< Min value of BUFFSIZE field. */ + #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Max (0x7FFFUL) /*!< Max size of BUFFSIZE field. */ + + + +/* ===================================================== Struct PDM_DMA ====================================================== */ +/** + * @brief DMA [PDM_DMA] (unspecified) + */ +typedef struct { + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is + detected.*/ + __IOM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_PDM_DMA_Type; /*!< Size = 8 (0x008) */ + +/* PDM_DMA_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define PDM_DMA_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE + field.*/ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_DMA_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define PDM_DMA_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* ======================================================= Struct PDM ======================================================== */ +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface + */ + typedef struct { /*!< PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified by + SAMPLE.MAXCNT (or the last sample after a STOP task has + been received) to Data RAM*/ + __IM uint32_t RESERVED2[29]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ + __IM uint32_t RESERVED3[93]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED4[124]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals*/ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the decimation ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly.*/ + __IM uint32_t RESERVED6[7]; + __IOM NRF_PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) (unspecified) */ + __IM uint32_t RESERVED7; + __IOM uint32_t MCLKCONFIG; /*!< (@ 0x0000054C) Master clock generator configuration */ + __IM uint32_t RESERVED8[4]; + __IOM NRF_PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) (unspecified) */ + __IM uint32_t RESERVED9[101]; + __IOM NRF_PDM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_PDM_Type; /*!< Size = 1800 (0x708) */ + +/* PDM_TASKS_START: Starts continuous PDM transfer */ + #define PDM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Starts continuous PDM transfer */ + #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* PDM_TASKS_STOP: Stops PDM transfer */ + #define PDM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops PDM transfer */ + #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PDM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define PDM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PDM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define PDM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PDM_EVENTS_STARTED: PDM transfer has started */ + #define PDM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : PDM transfer has started */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED + field.*/ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_EVENTS_STOPPED: PDM transfer has finished */ + #define PDM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : PDM transfer has finished */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_EVENTS_END: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been + received) to Data RAM */ + + #define PDM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has + been received) to Data RAM */ + + #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* PDM_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define PDM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define PDM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_PUBLISH_END: Publish configuration for event END */ + #define PDM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PDM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define PDM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PDM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PDM_INTEN: Enable or disable interrupt */ + #define PDM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */ + #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* END @Bit 2 : Enable or disable interrupt for event END */ + #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTEN_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTEN_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */ + #define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_INTENSET: Enable interrupt */ + #define PDM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to enable interrupt for event END */ + #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PDM_INTENCLR: Disable interrupt */ + #define PDM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to disable interrupt for event END */ + #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PDM_INTPEND: Pending interrupts */ + #define PDM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* STARTED @Bit 0 : Read pending status of interrupt for event STARTED */ + #define PDM_INTPEND_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define PDM_INTPEND_STARTED_Msk (0x1UL << PDM_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define PDM_INTPEND_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define PDM_INTPEND_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define PDM_INTPEND_STARTED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_STARTED_Pending (0x1UL) /*!< Read: Pending */ + +/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */ + #define PDM_INTPEND_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Msk (0x1UL << PDM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PDM_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PDM_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* END @Bit 2 : Read pending status of interrupt for event END */ + #define PDM_INTPEND_END_Pos (2UL) /*!< Position of END field. */ + #define PDM_INTPEND_END_Msk (0x1UL << PDM_INTPEND_END_Pos) /*!< Bit mask of END field. */ + #define PDM_INTPEND_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PDM_INTPEND_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PDM_INTPEND_END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PDM_INTPEND_END_Pending (0x1UL) /*!< Read: Pending */ + + +/* PDM_ENABLE: PDM module enable register */ + #define PDM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable PDM module */ + #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PDM_PDMCLKCTRL: PDM clock generator control */ + #define PDM_PDMCLKCTRL_ResetValue (0x08400000UL) /*!< Reset value of PDMCLKCTRL register. */ + +/* FREQ @Bits 0..31 : PDM_CLK frequency configuration. Enumerations are deprecated, use PDMCLKCTRL equation to find the register + value. The 12 least significant bits of the register are ignored and shall be set to zero. */ + + #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ + #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ + #define PDM_PDMCLKCTRL_FREQ_Min (0x8000000UL) /*!< Min enumerator value of FREQ field. */ + #define PDM_PDMCLKCTRL_FREQ_Max (0xA800000UL) /*!< Max enumerator value of FREQ field. */ + #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ + #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ + #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ + #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ + #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ + + +/* PDM_MODE: Defines the routing of the connected PDM microphones' signals */ + #define PDM_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* OPERATION @Bit 0 : Mono or stereo operation */ + #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ + #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ + #define PDM_MODE_OPERATION_Min (0x0UL) /*!< Min enumerator value of OPERATION field. */ + #define PDM_MODE_OPERATION_Max (0x1UL) /*!< Max enumerator value of OPERATION field. */ + #define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM + word R=[31:16]; L=[15:0]*/ + #define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM + word L1=[31:16]; L0=[15:0]*/ + +/* EDGE @Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled. */ + #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ + #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ + #define PDM_MODE_EDGE_Min (0x0UL) /*!< Min enumerator value of EDGE field. */ + #define PDM_MODE_EDGE_Max (0x1UL) /*!< Max enumerator value of EDGE field. */ + #define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ + #define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + + +/* PDM_GAINL: Left output gain adjustment */ + #define PDM_GAINL_ResetValue (0x00000028UL) /*!< Reset value of GAINL register. */ + +/* GAINL @Bits 0..6 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust + 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ + + #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ + #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ + #define PDM_GAINL_GAINL_Min (0x0UL) /*!< Min enumerator value of GAINL field. */ + #define PDM_GAINL_GAINL_Max (0x50UL) /*!< Max enumerator value of GAINL field. */ + #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ + #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ + #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + + +/* PDM_GAINR: Right output gain adjustment */ + #define PDM_GAINR_ResetValue (0x00000028UL) /*!< Reset value of GAINR register. */ + +/* GAINR @Bits 0..6 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + */ + + #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ + #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ + #define PDM_GAINR_GAINR_Min (0x0UL) /*!< Min enumerator value of GAINR field. */ + #define PDM_GAINR_GAINR_Max (0x50UL) /*!< Max enumerator value of GAINR field. */ + #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ + #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ + #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ + + +/* PDM_RATIO: Selects the decimation ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ + #define PDM_RATIO_ResetValue (0x00000000UL) /*!< Reset value of RATIO register. */ + +/* RATIO @Bits 0..2 : Selects the decimation ratio between PDM_CLK and output sample rate */ + #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ + #define PDM_RATIO_RATIO_Msk (0x7UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ + #define PDM_RATIO_RATIO_Min (0x0UL) /*!< Min enumerator value of RATIO field. */ + #define PDM_RATIO_RATIO_Max (0x1UL) /*!< Max enumerator value of RATIO field. */ + #define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */ + #define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */ + + +/* PDM_MCLKCONFIG: Master clock generator configuration */ + #define PDM_MCLKCONFIG_ResetValue (0x00000000UL) /*!< Reset value of MCLKCONFIG register. */ + +/* SRC @Bit 0 : Master clock source selection */ + #define PDM_MCLKCONFIG_SRC_Pos (0UL) /*!< Position of SRC field. */ + #define PDM_MCLKCONFIG_SRC_Msk (0x1UL << PDM_MCLKCONFIG_SRC_Pos) /*!< Bit mask of SRC field. */ + #define PDM_MCLKCONFIG_SRC_Min (0x0UL) /*!< Min enumerator value of SRC field. */ + #define PDM_MCLKCONFIG_SRC_Max (0x1UL) /*!< Max enumerator value of SRC field. */ + #define PDM_MCLKCONFIG_SRC_PCLK32M (0x0UL) /*!< 32 MHz peripheral clock */ + #define PDM_MCLKCONFIG_SRC_ACLK (0x1UL) /*!< Audio PLL clock */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PPIB ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct PPIB_OVERFLOW =================================================== */ +/** + * @brief OVERFLOW [PPIB_OVERFLOW] (unspecified) + */ +typedef struct { + __IOM uint32_t SEND; /*!< (@ 0x00000000) The task overflow for SEND tasks using SUBSCRIBE_SEND. + Write 0 to clear.*/ +} NRF_PPIB_OVERFLOW_Type; /*!< Size = 4 (0x004) */ + +/* PPIB_OVERFLOW_SEND: The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. */ + #define PPIB_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register. */ + +/* SEND0 @Bit 0 : The status for tasks overflow at SUBSCRIBE_SEND[0]. */ + #define PPIB_OVERFLOW_SEND_SEND0_Pos (0UL) /*!< Position of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Min (0x0UL) /*!< Min enumerator value of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Max (0x1UL) /*!< Max enumerator value of SEND0 field. */ + #define PPIB_OVERFLOW_SEND_SEND0_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND1 @Bit 1 : The status for tasks overflow at SUBSCRIBE_SEND[1]. */ + #define PPIB_OVERFLOW_SEND_SEND1_Pos (1UL) /*!< Position of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Min (0x0UL) /*!< Min enumerator value of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Max (0x1UL) /*!< Max enumerator value of SEND1 field. */ + #define PPIB_OVERFLOW_SEND_SEND1_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND2 @Bit 2 : The status for tasks overflow at SUBSCRIBE_SEND[2]. */ + #define PPIB_OVERFLOW_SEND_SEND2_Pos (2UL) /*!< Position of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Min (0x0UL) /*!< Min enumerator value of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Max (0x1UL) /*!< Max enumerator value of SEND2 field. */ + #define PPIB_OVERFLOW_SEND_SEND2_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND3 @Bit 3 : The status for tasks overflow at SUBSCRIBE_SEND[3]. */ + #define PPIB_OVERFLOW_SEND_SEND3_Pos (3UL) /*!< Position of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Min (0x0UL) /*!< Min enumerator value of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Max (0x1UL) /*!< Max enumerator value of SEND3 field. */ + #define PPIB_OVERFLOW_SEND_SEND3_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND4 @Bit 4 : The status for tasks overflow at SUBSCRIBE_SEND[4]. */ + #define PPIB_OVERFLOW_SEND_SEND4_Pos (4UL) /*!< Position of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Min (0x0UL) /*!< Min enumerator value of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Max (0x1UL) /*!< Max enumerator value of SEND4 field. */ + #define PPIB_OVERFLOW_SEND_SEND4_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND5 @Bit 5 : The status for tasks overflow at SUBSCRIBE_SEND[5]. */ + #define PPIB_OVERFLOW_SEND_SEND5_Pos (5UL) /*!< Position of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Min (0x0UL) /*!< Min enumerator value of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Max (0x1UL) /*!< Max enumerator value of SEND5 field. */ + #define PPIB_OVERFLOW_SEND_SEND5_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND6 @Bit 6 : The status for tasks overflow at SUBSCRIBE_SEND[6]. */ + #define PPIB_OVERFLOW_SEND_SEND6_Pos (6UL) /*!< Position of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Min (0x0UL) /*!< Min enumerator value of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Max (0x1UL) /*!< Max enumerator value of SEND6 field. */ + #define PPIB_OVERFLOW_SEND_SEND6_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND7 @Bit 7 : The status for tasks overflow at SUBSCRIBE_SEND[7]. */ + #define PPIB_OVERFLOW_SEND_SEND7_Pos (7UL) /*!< Position of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Min (0x0UL) /*!< Min enumerator value of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Max (0x1UL) /*!< Max enumerator value of SEND7 field. */ + #define PPIB_OVERFLOW_SEND_SEND7_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND8 @Bit 8 : The status for tasks overflow at SUBSCRIBE_SEND[8]. */ + #define PPIB_OVERFLOW_SEND_SEND8_Pos (8UL) /*!< Position of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Min (0x0UL) /*!< Min enumerator value of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Max (0x1UL) /*!< Max enumerator value of SEND8 field. */ + #define PPIB_OVERFLOW_SEND_SEND8_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND9 @Bit 9 : The status for tasks overflow at SUBSCRIBE_SEND[9]. */ + #define PPIB_OVERFLOW_SEND_SEND9_Pos (9UL) /*!< Position of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Min (0x0UL) /*!< Min enumerator value of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Max (0x1UL) /*!< Max enumerator value of SEND9 field. */ + #define PPIB_OVERFLOW_SEND_SEND9_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND10 @Bit 10 : The status for tasks overflow at SUBSCRIBE_SEND[10]. */ + #define PPIB_OVERFLOW_SEND_SEND10_Pos (10UL) /*!< Position of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Min (0x0UL) /*!< Min enumerator value of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Max (0x1UL) /*!< Max enumerator value of SEND10 field. */ + #define PPIB_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND11 @Bit 11 : The status for tasks overflow at SUBSCRIBE_SEND[11]. */ + #define PPIB_OVERFLOW_SEND_SEND11_Pos (11UL) /*!< Position of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Min (0x0UL) /*!< Min enumerator value of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Max (0x1UL) /*!< Max enumerator value of SEND11 field. */ + #define PPIB_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND12 @Bit 12 : The status for tasks overflow at SUBSCRIBE_SEND[12]. */ + #define PPIB_OVERFLOW_SEND_SEND12_Pos (12UL) /*!< Position of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Min (0x0UL) /*!< Min enumerator value of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Max (0x1UL) /*!< Max enumerator value of SEND12 field. */ + #define PPIB_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND13 @Bit 13 : The status for tasks overflow at SUBSCRIBE_SEND[13]. */ + #define PPIB_OVERFLOW_SEND_SEND13_Pos (13UL) /*!< Position of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Min (0x0UL) /*!< Min enumerator value of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Max (0x1UL) /*!< Max enumerator value of SEND13 field. */ + #define PPIB_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND14 @Bit 14 : The status for tasks overflow at SUBSCRIBE_SEND[14]. */ + #define PPIB_OVERFLOW_SEND_SEND14_Pos (14UL) /*!< Position of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Min (0x0UL) /*!< Min enumerator value of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Max (0x1UL) /*!< Max enumerator value of SEND14 field. */ + #define PPIB_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND15 @Bit 15 : The status for tasks overflow at SUBSCRIBE_SEND[15]. */ + #define PPIB_OVERFLOW_SEND_SEND15_Pos (15UL) /*!< Position of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Min (0x0UL) /*!< Min enumerator value of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Max (0x1UL) /*!< Max enumerator value of SEND15 field. */ + #define PPIB_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND16 @Bit 16 : The status for tasks overflow at SUBSCRIBE_SEND[16]. */ + #define PPIB_OVERFLOW_SEND_SEND16_Pos (16UL) /*!< Position of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND16_Pos) /*!< Bit mask of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Min (0x0UL) /*!< Min enumerator value of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Max (0x1UL) /*!< Max enumerator value of SEND16 field. */ + #define PPIB_OVERFLOW_SEND_SEND16_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND16_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND17 @Bit 17 : The status for tasks overflow at SUBSCRIBE_SEND[17]. */ + #define PPIB_OVERFLOW_SEND_SEND17_Pos (17UL) /*!< Position of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND17_Pos) /*!< Bit mask of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Min (0x0UL) /*!< Min enumerator value of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Max (0x1UL) /*!< Max enumerator value of SEND17 field. */ + #define PPIB_OVERFLOW_SEND_SEND17_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND17_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND18 @Bit 18 : The status for tasks overflow at SUBSCRIBE_SEND[18]. */ + #define PPIB_OVERFLOW_SEND_SEND18_Pos (18UL) /*!< Position of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND18_Pos) /*!< Bit mask of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Min (0x0UL) /*!< Min enumerator value of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Max (0x1UL) /*!< Max enumerator value of SEND18 field. */ + #define PPIB_OVERFLOW_SEND_SEND18_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND18_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND19 @Bit 19 : The status for tasks overflow at SUBSCRIBE_SEND[19]. */ + #define PPIB_OVERFLOW_SEND_SEND19_Pos (19UL) /*!< Position of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND19_Pos) /*!< Bit mask of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Min (0x0UL) /*!< Min enumerator value of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Max (0x1UL) /*!< Max enumerator value of SEND19 field. */ + #define PPIB_OVERFLOW_SEND_SEND19_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND19_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND20 @Bit 20 : The status for tasks overflow at SUBSCRIBE_SEND[20]. */ + #define PPIB_OVERFLOW_SEND_SEND20_Pos (20UL) /*!< Position of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND20_Pos) /*!< Bit mask of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Min (0x0UL) /*!< Min enumerator value of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Max (0x1UL) /*!< Max enumerator value of SEND20 field. */ + #define PPIB_OVERFLOW_SEND_SEND20_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND20_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND21 @Bit 21 : The status for tasks overflow at SUBSCRIBE_SEND[21]. */ + #define PPIB_OVERFLOW_SEND_SEND21_Pos (21UL) /*!< Position of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND21_Pos) /*!< Bit mask of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Min (0x0UL) /*!< Min enumerator value of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Max (0x1UL) /*!< Max enumerator value of SEND21 field. */ + #define PPIB_OVERFLOW_SEND_SEND21_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND21_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND22 @Bit 22 : The status for tasks overflow at SUBSCRIBE_SEND[22]. */ + #define PPIB_OVERFLOW_SEND_SEND22_Pos (22UL) /*!< Position of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND22_Pos) /*!< Bit mask of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Min (0x0UL) /*!< Min enumerator value of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Max (0x1UL) /*!< Max enumerator value of SEND22 field. */ + #define PPIB_OVERFLOW_SEND_SEND22_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND22_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND23 @Bit 23 : The status for tasks overflow at SUBSCRIBE_SEND[23]. */ + #define PPIB_OVERFLOW_SEND_SEND23_Pos (23UL) /*!< Position of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND23_Pos) /*!< Bit mask of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Min (0x0UL) /*!< Min enumerator value of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Max (0x1UL) /*!< Max enumerator value of SEND23 field. */ + #define PPIB_OVERFLOW_SEND_SEND23_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND23_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND24 @Bit 24 : The status for tasks overflow at SUBSCRIBE_SEND[24]. */ + #define PPIB_OVERFLOW_SEND_SEND24_Pos (24UL) /*!< Position of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND24_Pos) /*!< Bit mask of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Min (0x0UL) /*!< Min enumerator value of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Max (0x1UL) /*!< Max enumerator value of SEND24 field. */ + #define PPIB_OVERFLOW_SEND_SEND24_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND24_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND25 @Bit 25 : The status for tasks overflow at SUBSCRIBE_SEND[25]. */ + #define PPIB_OVERFLOW_SEND_SEND25_Pos (25UL) /*!< Position of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND25_Pos) /*!< Bit mask of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Min (0x0UL) /*!< Min enumerator value of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Max (0x1UL) /*!< Max enumerator value of SEND25 field. */ + #define PPIB_OVERFLOW_SEND_SEND25_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND25_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND26 @Bit 26 : The status for tasks overflow at SUBSCRIBE_SEND[26]. */ + #define PPIB_OVERFLOW_SEND_SEND26_Pos (26UL) /*!< Position of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND26_Pos) /*!< Bit mask of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Min (0x0UL) /*!< Min enumerator value of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Max (0x1UL) /*!< Max enumerator value of SEND26 field. */ + #define PPIB_OVERFLOW_SEND_SEND26_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND26_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND27 @Bit 27 : The status for tasks overflow at SUBSCRIBE_SEND[27]. */ + #define PPIB_OVERFLOW_SEND_SEND27_Pos (27UL) /*!< Position of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND27_Pos) /*!< Bit mask of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Min (0x0UL) /*!< Min enumerator value of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Max (0x1UL) /*!< Max enumerator value of SEND27 field. */ + #define PPIB_OVERFLOW_SEND_SEND27_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND27_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND28 @Bit 28 : The status for tasks overflow at SUBSCRIBE_SEND[28]. */ + #define PPIB_OVERFLOW_SEND_SEND28_Pos (28UL) /*!< Position of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND28_Pos) /*!< Bit mask of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Min (0x0UL) /*!< Min enumerator value of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Max (0x1UL) /*!< Max enumerator value of SEND28 field. */ + #define PPIB_OVERFLOW_SEND_SEND28_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND28_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND29 @Bit 29 : The status for tasks overflow at SUBSCRIBE_SEND[29]. */ + #define PPIB_OVERFLOW_SEND_SEND29_Pos (29UL) /*!< Position of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND29_Pos) /*!< Bit mask of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Min (0x0UL) /*!< Min enumerator value of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Max (0x1UL) /*!< Max enumerator value of SEND29 field. */ + #define PPIB_OVERFLOW_SEND_SEND29_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND29_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND30 @Bit 30 : The status for tasks overflow at SUBSCRIBE_SEND[30]. */ + #define PPIB_OVERFLOW_SEND_SEND30_Pos (30UL) /*!< Position of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND30_Pos) /*!< Bit mask of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Min (0x0UL) /*!< Min enumerator value of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Max (0x1UL) /*!< Max enumerator value of SEND30 field. */ + #define PPIB_OVERFLOW_SEND_SEND30_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND30_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + +/* SEND31 @Bit 31 : The status for tasks overflow at SUBSCRIBE_SEND[31]. */ + #define PPIB_OVERFLOW_SEND_SEND31_Pos (31UL) /*!< Position of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND31_Pos) /*!< Bit mask of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Min (0x0UL) /*!< Min enumerator value of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Max (0x1UL) /*!< Max enumerator value of SEND31 field. */ + #define PPIB_OVERFLOW_SEND_SEND31_Overflow (0x1UL) /*!< Task overflow is happened. */ + #define PPIB_OVERFLOW_SEND_SEND31_NoOverflow (0x0UL) /*!< Task overflow is not happened. */ + + +/* ======================================================= Struct PPIB ======================================================= */ +/** + * @brief PPIB APB registers + */ + typedef struct { /*!< PPIB Structure */ + __OM uint32_t TASKS_SEND[32]; /*!< (@ 0x00000000) This task is unused, but the PPIB provides the + SUBSCRIBE task to connect SEND [n] task.*/ + __IOM uint32_t SUBSCRIBE_SEND[32]; /*!< (@ 0x00000080) Subscribe configuration for task SEND[n] */ + __IOM uint32_t EVENTS_RECEIVE[32]; /*!< (@ 0x00000100) This event is unused, but the PPIB provides the PUBLISH + event to connect RECEIVE [n] event.*/ + __IOM uint32_t PUBLISH_RECEIVE[32]; /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n] */ + __IM uint32_t RESERVED[128]; + __IOM NRF_PPIB_OVERFLOW_Type OVERFLOW; /*!< (@ 0x00000400) (unspecified) */ + } NRF_PPIB_Type; /*!< Size = 1028 (0x404) */ + +/* PPIB_TASKS_SEND: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */ + #define PPIB_TASKS_SEND_MaxCount (32UL) /*!< Max size of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_MaxIndex (31UL) /*!< Max index of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_MinIndex (0UL) /*!< Min index of TASKS_SEND[32] array. */ + #define PPIB_TASKS_SEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SEND[32] register. */ + +/* TASKS_SEND @Bit 0 : This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Msk (0x1UL << PPIB_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SEND field. */ + #define PPIB_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* PPIB_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */ + #define PPIB_SUBSCRIBE_SEND_MaxCount (32UL) /*!< Max size of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_MaxIndex (31UL) /*!< Max index of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_MinIndex (0UL) /*!< Min index of SUBSCRIBE_SEND[32] array. */ + #define PPIB_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[32] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << PPIB_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PPIB_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PPIB_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Msk (0x1UL << PPIB_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PPIB_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PPIB_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PPIB_EVENTS_RECEIVE: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */ + #define PPIB_EVENTS_RECEIVE_MaxCount (32UL) /*!< Max size of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_MaxIndex (31UL) /*!< Max index of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_MinIndex (0UL) /*!< Min index of EVENTS_RECEIVE[32] array. */ + #define PPIB_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[32] register. */ + +/* EVENTS_RECEIVE @Bit 0 : This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of + EVENTS_RECEIVE field.*/ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field. */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */ + #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */ + + +/* PPIB_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */ + #define PPIB_PUBLISH_RECEIVE_MaxCount (32UL) /*!< Max size of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_MaxIndex (31UL) /*!< Max index of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_MinIndex (0UL) /*!< Min index of PUBLISH_RECEIVE[32] array. */ + #define PPIB_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[32] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << PPIB_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PPIB_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PPIB_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Msk (0x1UL << PPIB_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PPIB_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PPIB_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct PWM_TASKS_DMA_SEQ ================================================= */ +/** + * @brief SEQ [PWM_TASKS_DMA_SEQ] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_PWM_TASKS_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ + #define PWM_TASKS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_TASKS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_TASKS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_TASKS_DMA_SEQ_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define PWM_TASKS_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define PWM_TASKS_DMA_SEQ_START_START_Pos (0UL) /*!< Position of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Msk (0x1UL << PWM_TASKS_DMA_SEQ_START_START_Pos) /*!< Bit mask of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define PWM_TASKS_DMA_SEQ_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_TASKS_DMA_SEQ_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Msk (0x1UL << PWM_TASKS_DMA_SEQ_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define PWM_TASKS_DMA_SEQ_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct PWM_TASKS_DMA =================================================== */ +/** + * @brief TASKS_DMA [PWM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_PWM_TASKS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral tasks. */ +} NRF_PWM_TASKS_DMA_Type; /*!< Size = 16 (0x010) */ + + +/* ============================================== Struct PWM_SUBSCRIBE_DMA_SEQ =============================================== */ +/** + * @brief SEQ [PWM_SUBSCRIBE_DMA_SEQ] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type; /*!< Size = 8 (0x008) */ + #define PWM_SUBSCRIBE_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_SUBSCRIBE_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_SUBSCRIBE_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_SUBSCRIBE_DMA_SEQ_START: Subscribe configuration for task START */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_SUBSCRIBE_DMA_SEQ_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct PWM_SUBSCRIBE_DMA ================================================= */ +/** + * @brief SUBSCRIBE_DMA [PWM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_PWM_SUBSCRIBE_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Subscribe configuration for tasks */ +} NRF_PWM_SUBSCRIBE_DMA_Type; /*!< Size = 16 (0x010) */ + + +/* ================================================ Struct PWM_EVENTS_DMA_SEQ ================================================ */ +/** + * @brief SEQ [PWM_EVENTS_DMA_SEQ] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_PWM_EVENTS_DMA_SEQ_Type; /*!< Size = 12 (0x00C) */ + #define PWM_EVENTS_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_EVENTS_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_EVENTS_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_EVENTS_DMA_SEQ_END: Generated after all MAXCNT bytes have been transferred */ + #define PWM_EVENTS_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define PWM_EVENTS_DMA_SEQ_END_END_Pos (0UL) /*!< Position of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_END_END_Pos) /*!< Bit mask of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define PWM_EVENTS_DMA_SEQ_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_DMA_SEQ_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define PWM_EVENTS_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define PWM_EVENTS_DMA_SEQ_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_DMA_SEQ_BUSERROR: An error occured during the bus transfer. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================== Struct PWM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [PWM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_PWM_EVENTS_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Peripheral events. */ +} NRF_PWM_EVENTS_DMA_Type; /*!< Size = 24 (0x018) */ + + +/* =============================================== Struct PWM_PUBLISH_DMA_SEQ ================================================ */ +/** + * @brief SEQ [PWM_PUBLISH_DMA_SEQ] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_PWM_PUBLISH_DMA_SEQ_Type; /*!< Size = 12 (0x00C) */ + #define PWM_PUBLISH_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_PUBLISH_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_PUBLISH_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_PUBLISH_DMA_SEQ_END: Publish configuration for event END */ + #define PWM_PUBLISH_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_END_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_DMA_SEQ_READY: Publish configuration for event READY */ + #define PWM_PUBLISH_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_DMA_SEQ_BUSERROR: Publish configuration for event BUSERROR */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct PWM_PUBLISH_DMA ================================================== */ +/** + * @brief PUBLISH_DMA [PWM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_PWM_PUBLISH_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) Publish configuration for events */ +} NRF_PWM_PUBLISH_DMA_Type; /*!< Size = 24 (0x018) */ + + +/* ===================================================== Struct PWM_SEQ ====================================================== */ +/** + * @brief SEQ [PWM_SEQ] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Number of additional PWM periods between samples loaded + into compare register*/ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Time added after the sequence */ + __IM uint32_t RESERVED1[4]; +} NRF_PWM_SEQ_Type; /*!< Size = 32 (0x020) */ + #define PWM_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_SEQ_REFRESH: Number of additional PWM periods between samples loaded into compare register */ + #define PWM_SEQ_REFRESH_ResetValue (0x00000001UL) /*!< Reset value of REFRESH register. */ + +/* CNT @Bits 0..23 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM + periods) */ + + #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Min (0x0UL) /*!< Min enumerator value of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Max (0x0UL) /*!< Max enumerator value of CNT field. */ + #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */ + + +/* PWM_SEQ_ENDDELAY: Time added after the sequence */ + #define PWM_SEQ_ENDDELAY_ResetValue (0x00000000UL) /*!< Reset value of ENDDELAY register. */ + +/* CNT @Bits 0..23 : Time added after the sequence in PWM periods */ + #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + + + +/* ===================================================== Struct PWM_PSEL ===================================================== */ +/** + * @brief PSEL [PWM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Output pin select for PWM channel n */ +} NRF_PWM_PSEL_Type; /*!< Size = 16 (0x010) */ + +/* PWM_PSEL_OUT: Output pin select for PWM channel n */ + #define PWM_PSEL_OUT_MaxCount (4UL) /*!< Max size of OUT[4] array. */ + #define PWM_PSEL_OUT_MaxIndex (3UL) /*!< Max index of OUT[4] array. */ + #define PWM_PSEL_OUT_MinIndex (0UL) /*!< Min index of OUT[4] array. */ + #define PWM_PSEL_OUT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OUT[4] register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + #define PWM_PSEL_OUT_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define PWM_PSEL_OUT_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define PWM_PSEL_OUT_PORT_Msk (0xFUL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ + #define PWM_PSEL_OUT_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define PWM_PSEL_OUT_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* =================================================== Struct PWM_DMA_SEQ ==================================================== */ +/** + * @brief SEQ [PWM_DMA_SEQ] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_PWM_DMA_SEQ_Type; /*!< Size = 36 (0x024) */ + #define PWM_DMA_SEQ_MaxCount (2UL) /*!< Size of SEQ[2] array. */ + #define PWM_DMA_SEQ_MaxIndex (1UL) /*!< Max index of SEQ[2] array. */ + #define PWM_DMA_SEQ_MinIndex (0UL) /*!< Min index of SEQ[2] array. */ + +/* PWM_DMA_SEQ_PTR: RAM buffer start address */ + #define PWM_DMA_SEQ_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define PWM_DMA_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define PWM_DMA_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* PWM_DMA_SEQ_MAXCNT: Maximum number of bytes in channel buffer */ + #define PWM_DMA_SEQ_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk (0x7FFFUL << PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */ + #define PWM_DMA_SEQ_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* PWM_DMA_SEQ_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* PWM_DMA_SEQ_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_DMA_SEQ_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct PWM_DMA ====================================================== */ +/** + * @brief DMA [PWM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_PWM_DMA_SEQ_Type SEQ[2]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_PWM_DMA_Type; /*!< Size = 72 (0x048) */ + +/* ======================================================= Struct PWM ======================================================== */ +/** + * @brief Pulse width modulation unit + */ + typedef struct { /*!< PWM Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end + of current PWM period, and stops sequence playback*/ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000008) Steps by one value in the current sequence on all + enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running.*/ + __IM uint32_t RESERVED1; + __OM NRF_PWM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000010) Peripheral tasks. */ + __IM uint32_t RESERVED2[25]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000088) Subscribe configuration for task NEXTSTEP */ + __IM uint32_t RESERVED3; + __IOM NRF_PWM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x00000090) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[25]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no + longer generated*/ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) First PWM period started on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Emitted at end of every sequence n, when last value + from RAM has been applied to wave counter*/ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of + times defined in LOOP.CNT*/ + __IOM uint32_t EVENTS_RAMUNDERFLOW; /*!< (@ 0x00000120) Emitted when retrieving from RAM does not complete in + time for the PWM module*/ + __IOM NRF_PWM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x00000124) Peripheral events. */ + __IOM uint32_t EVENTS_COMPAREMATCH[4]; /*!< (@ 0x0000013C) This event is generated when the compare matches for + the compare channel [n].*/ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Publish configuration for event SEQSTARTED[n] */ + __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Publish configuration for event SEQEND[n] */ + __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ + __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ + __IOM uint32_t PUBLISH_RAMUNDERFLOW; /*!< (@ 0x000001A0) Publish configuration for event RAMUNDERFLOW */ + __IOM NRF_PWM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001A4) Publish configuration for events */ + __IOM uint32_t PUBLISH_COMPAREMATCH[4]; /*!< (@ 0x000001BC) Publish configuration for event COMPAREMATCH[n] */ + __IM uint32_t RESERVED6[13]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED8[124]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IOM uint32_t IDLEOUT; /*!< (@ 0x00000518) Configure the output value on the PWM channel during + idle*/ + __IM uint32_t RESERVED9; + __IOM NRF_PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) (unspecified) */ + __IOM NRF_PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) (unspecified) */ + __IM uint32_t RESERVED10[100]; + __IOM NRF_PWM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_PWM_Type; /*!< Size = 1864 (0x748) */ + +/* PWM_TASKS_STOP: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + #define PWM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + */ + + #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_TASKS_NEXTSTEP: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running. */ + + #define PWM_TASKS_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEXTSTEP register. */ + +/* TASKS_NEXTSTEP @Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not + cause PWM generation to start if not running. */ + + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP + field.*/ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Min (0x1UL) /*!< Min enumerator value of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Max (0x1UL) /*!< Max enumerator value of TASKS_NEXTSTEP field. */ + #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */ + + +/* PWM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define PWM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_SUBSCRIBE_NEXTSTEP: Subscribe configuration for task NEXTSTEP */ + #define PWM_SUBSCRIBE_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_NEXTSTEP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task NEXTSTEP will subscribe to */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* PWM_EVENTS_STOPPED: Response to STOP task, emitted when PWM pulses are no longer generated */ + #define PWM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_SEQSTARTED: First PWM period started on sequence n */ + #define PWM_EVENTS_SEQSTARTED_MaxCount (2UL) /*!< Max size of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_MaxIndex (1UL) /*!< Max index of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_MinIndex (0UL) /*!< Min index of EVENTS_SEQSTARTED[2] array. */ + #define PWM_EVENTS_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQSTARTED[2] register. */ + +/* EVENTS_SEQSTARTED @Bit 0 : First PWM period started on sequence n */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of + EVENTS_SEQSTARTED field.*/ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQSTARTED field. */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_SEQEND: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + #define PWM_EVENTS_SEQEND_MaxCount (2UL) /*!< Max size of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_MaxIndex (1UL) /*!< Max index of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_MinIndex (0UL) /*!< Min index of EVENTS_SEQEND[2] array. */ + #define PWM_EVENTS_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQEND[2] register. */ + +/* EVENTS_SEQEND @Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND + field.*/ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQEND field. */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_PWMPERIODEND: Emitted at the end of each PWM period */ + #define PWM_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register. */ + +/* EVENTS_PWMPERIODEND @Bit 0 : Emitted at the end of each PWM period */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit + mask of EVENTS_PWMPERIODEND field.*/ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field. */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_LOOPSDONE: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + #define PWM_EVENTS_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LOOPSDONE register. */ + +/* EVENTS_LOOPSDONE @Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of + EVENTS_LOOPSDONE field.*/ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_LOOPSDONE field. */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_RAMUNDERFLOW: Emitted when retrieving from RAM does not complete in time for the PWM module */ + #define PWM_EVENTS_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RAMUNDERFLOW register. */ + +/* EVENTS_RAMUNDERFLOW @Bit 0 : Emitted when retrieving from RAM does not complete in time for the PWM module */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos (0UL) /*!< Position of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Msk (0x1UL << PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos) /*!< Bit + mask of EVENTS_RAMUNDERFLOW field.*/ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of EVENTS_RAMUNDERFLOW field. */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_EVENTS_COMPAREMATCH: This event is generated when the compare matches for the compare channel [n]. */ + #define PWM_EVENTS_COMPAREMATCH_MaxCount (4UL) /*!< Max size of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_MaxIndex (3UL) /*!< Max index of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_MinIndex (0UL) /*!< Min index of EVENTS_COMPAREMATCH[4] array. */ + #define PWM_EVENTS_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPAREMATCH[4] register. */ + +/* EVENTS_COMPAREMATCH @Bit 0 : This event is generated when the compare matches for the compare channel [n]. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos (0UL) /*!< Position of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Msk (0x1UL << PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos) /*!< Bit + mask of EVENTS_COMPAREMATCH field.*/ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPAREMATCH field. */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* PWM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define PWM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_SEQSTARTED: Publish configuration for event SEQSTARTED[n] */ + #define PWM_PUBLISH_SEQSTARTED_MaxCount (2UL) /*!< Max size of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_MaxIndex (1UL) /*!< Max index of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_MinIndex (0UL) /*!< Min index of PUBLISH_SEQSTARTED[2] array. */ + #define PWM_PUBLISH_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQSTARTED[2] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SEQSTARTED[n] will publish to */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_SEQSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_SEQEND: Publish configuration for event SEQEND[n] */ + #define PWM_PUBLISH_SEQEND_MaxCount (2UL) /*!< Max size of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_MaxIndex (1UL) /*!< Max index of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_MinIndex (0UL) /*!< Min index of PUBLISH_SEQEND[2] array. */ + #define PWM_PUBLISH_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQEND[2] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SEQEND[n] will publish to */ + #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_SEQEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_PWMPERIODEND: Publish configuration for event PWMPERIODEND */ + #define PWM_PUBLISH_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMPERIODEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PWMPERIODEND will publish to */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_LOOPSDONE: Publish configuration for event LOOPSDONE */ + #define PWM_PUBLISH_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LOOPSDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LOOPSDONE will publish to */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_LOOPSDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_RAMUNDERFLOW: Publish configuration for event RAMUNDERFLOW */ + #define PWM_PUBLISH_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RAMUNDERFLOW register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RAMUNDERFLOW will publish to */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Msk (0xFFUL << PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Msk (0x1UL << PWM_PUBLISH_RAMUNDERFLOW_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_RAMUNDERFLOW_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_PUBLISH_COMPAREMATCH: Publish configuration for event COMPAREMATCH[n] */ + #define PWM_PUBLISH_COMPAREMATCH_MaxCount (4UL) /*!< Max size of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_MaxIndex (3UL) /*!< Max index of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_MinIndex (0UL) /*!< Min index of PUBLISH_COMPAREMATCH[4] array. */ + #define PWM_PUBLISH_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPAREMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPAREMATCH[n] will publish to */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Msk (0xFFUL << PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Msk (0x1UL << PWM_PUBLISH_COMPAREMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define PWM_PUBLISH_COMPAREMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* PWM_SHORTS: Shortcuts between local events and tasks */ + #define PWM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* SEQEND0_STOP @Bit 0 : Shortcut between event SEQEND[n] and task STOP */ + #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Min (0x0UL) /*!< Min enumerator value of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Max (0x1UL) /*!< Max enumerator value of SEQEND0_STOP field. */ + #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SEQEND1_STOP @Bit 1 : Shortcut between event SEQEND[n] and task STOP */ + #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Min (0x0UL) /*!< Min enumerator value of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Max (0x1UL) /*!< Max enumerator value of SEQEND1_STOP field. */ + #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ0_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of + LOOPSDONE_DMA_SEQ1_START field.*/ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field. */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */ + #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_STOP field. */ + #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RAMUNDERFLOW_STOP @Bit 5 : Shortcut between event RAMUNDERFLOW and task STOP */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Pos (5UL) /*!< Position of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Msk (0x1UL << PWM_SHORTS_RAMUNDERFLOW_STOP_Pos) /*!< Bit mask of RAMUNDERFLOW_STOP + field.*/ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW_STOP field. */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_RAMUNDERFLOW_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_SEQ0_BUSERROR_STOP @Bit 6 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos (6UL) /*!< Position of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos) /*!< Bit mask of + DMA_SEQ0_BUSERROR_STOP field.*/ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ0_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_SEQ1_BUSERROR_STOP @Bit 7 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos (7UL) /*!< Position of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos) /*!< Bit mask of + DMA_SEQ1_BUSERROR_STOP field.*/ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ1_BUSERROR_STOP field. */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* PWM_INTEN: Enable or disable interrupt */ + #define PWM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* SEQSTARTED0 @Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ + #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */ + +/* SEQSTARTED1 @Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ + #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */ + +/* SEQEND0 @Bit 4 : Enable or disable interrupt for event SEQEND[0] */ + #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */ + +/* SEQEND1 @Bit 5 : Enable or disable interrupt for event SEQEND[1] */ + #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */ + +/* PWMPERIODEND @Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ + #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ + +/* LOOPSDONE @Bit 7 : Enable or disable interrupt for event LOOPSDONE */ + #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */ + +/* RAMUNDERFLOW @Bit 8 : Enable or disable interrupt for event RAMUNDERFLOW */ + #define PWM_INTEN_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Msk (0x1UL << PWM_INTEN_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTEN_RAMUNDERFLOW_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_RAMUNDERFLOW_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0END @Bit 9 : Enable or disable interrupt for event DMASEQ0END */ + #define PWM_INTEN_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Msk (0x1UL << PWM_INTEN_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTEN_DMASEQ0END_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0END_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0READY @Bit 10 : Enable or disable interrupt for event DMASEQ0READY */ + #define PWM_INTEN_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Msk (0x1UL << PWM_INTEN_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTEN_DMASEQ0READY_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0READY_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ0BUSERROR @Bit 11 : Enable or disable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTEN_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTEN_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1END @Bit 12 : Enable or disable interrupt for event DMASEQ1END */ + #define PWM_INTEN_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Msk (0x1UL << PWM_INTEN_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTEN_DMASEQ1END_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1END_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1READY @Bit 13 : Enable or disable interrupt for event DMASEQ1READY */ + #define PWM_INTEN_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Msk (0x1UL << PWM_INTEN_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTEN_DMASEQ1READY_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1READY_Enabled (0x1UL) /*!< Enable */ + +/* DMASEQ1BUSERROR @Bit 14 : Enable or disable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTEN_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTEN_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH0 @Bit 15 : Enable or disable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTEN_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Msk (0x1UL << PWM_INTEN_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTEN_COMPAREMATCH0_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH1 @Bit 16 : Enable or disable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTEN_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Msk (0x1UL << PWM_INTEN_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTEN_COMPAREMATCH1_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH2 @Bit 17 : Enable or disable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTEN_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Msk (0x1UL << PWM_INTEN_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTEN_COMPAREMATCH2_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* COMPAREMATCH3 @Bit 18 : Enable or disable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTEN_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Msk (0x1UL << PWM_INTEN_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTEN_COMPAREMATCH3_Disabled (0x0UL) /*!< Disable */ + #define PWM_INTEN_COMPAREMATCH3_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_INTENSET: Enable interrupt */ + #define PWM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED0 @Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ + #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED1 @Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ + #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND0 @Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ + #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND1 @Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ + #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ + #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOOPSDONE @Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ + #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RAMUNDERFLOW @Bit 8 : Write '1' to enable interrupt for event RAMUNDERFLOW */ + #define PWM_INTENSET_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENSET_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENSET_RAMUNDERFLOW_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_RAMUNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0END @Bit 9 : Write '1' to enable interrupt for event DMASEQ0END */ + #define PWM_INTENSET_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Msk (0x1UL << PWM_INTENSET_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTENSET_DMASEQ0END_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0READY @Bit 10 : Write '1' to enable interrupt for event DMASEQ0READY */ + #define PWM_INTENSET_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Msk (0x1UL << PWM_INTENSET_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTENSET_DMASEQ0READY_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0BUSERROR @Bit 11 : Write '1' to enable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1END @Bit 12 : Write '1' to enable interrupt for event DMASEQ1END */ + #define PWM_INTENSET_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Msk (0x1UL << PWM_INTENSET_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTENSET_DMASEQ1END_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1READY @Bit 13 : Write '1' to enable interrupt for event DMASEQ1READY */ + #define PWM_INTENSET_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Msk (0x1UL << PWM_INTENSET_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTENSET_DMASEQ1READY_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1BUSERROR @Bit 14 : Write '1' to enable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH0 @Bit 15 : Write '1' to enable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTENSET_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENSET_COMPAREMATCH0_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH1 @Bit 16 : Write '1' to enable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTENSET_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENSET_COMPAREMATCH1_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH2 @Bit 17 : Write '1' to enable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTENSET_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENSET_COMPAREMATCH2_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH3 @Bit 18 : Write '1' to enable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTENSET_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENSET_COMPAREMATCH3_Set (0x1UL) /*!< Enable */ + #define PWM_INTENSET_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENSET_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PWM_INTENCLR: Disable interrupt */ + #define PWM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED0 @Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ + #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQSTARTED1 @Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ + #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND0 @Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ + #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SEQEND1 @Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ + #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PWMPERIODEND @Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ + #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LOOPSDONE @Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ + #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RAMUNDERFLOW @Bit 8 : Write '1' to disable interrupt for event RAMUNDERFLOW */ + #define PWM_INTENCLR_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENCLR_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTENCLR_RAMUNDERFLOW_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_RAMUNDERFLOW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0END @Bit 9 : Write '1' to disable interrupt for event DMASEQ0END */ + #define PWM_INTENCLR_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Msk (0x1UL << PWM_INTENCLR_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTENCLR_DMASEQ0END_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0READY @Bit 10 : Write '1' to disable interrupt for event DMASEQ0READY */ + #define PWM_INTENCLR_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTENCLR_DMASEQ0READY_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ0BUSERROR @Bit 11 : Write '1' to disable interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1END @Bit 12 : Write '1' to disable interrupt for event DMASEQ1END */ + #define PWM_INTENCLR_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Msk (0x1UL << PWM_INTENCLR_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTENCLR_DMASEQ1END_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1END_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1READY @Bit 13 : Write '1' to disable interrupt for event DMASEQ1READY */ + #define PWM_INTENCLR_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTENCLR_DMASEQ1READY_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMASEQ1BUSERROR @Bit 14 : Write '1' to disable interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH0 @Bit 15 : Write '1' to disable interrupt for event COMPAREMATCH[0] */ + #define PWM_INTENCLR_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTENCLR_COMPAREMATCH0_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH1 @Bit 16 : Write '1' to disable interrupt for event COMPAREMATCH[1] */ + #define PWM_INTENCLR_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTENCLR_COMPAREMATCH1_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH2 @Bit 17 : Write '1' to disable interrupt for event COMPAREMATCH[2] */ + #define PWM_INTENCLR_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTENCLR_COMPAREMATCH2_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPAREMATCH3 @Bit 18 : Write '1' to disable interrupt for event COMPAREMATCH[3] */ + #define PWM_INTENCLR_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTENCLR_COMPAREMATCH3_Clear (0x1UL) /*!< Disable */ + #define PWM_INTENCLR_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define PWM_INTENCLR_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* PWM_INTPEND: Pending interrupts */ + #define PWM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */ + #define PWM_INTPEND_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Msk (0x1UL << PWM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define PWM_INTPEND_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define PWM_INTPEND_STOPPED_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_STOPPED_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQSTARTED0 @Bit 2 : Read pending status of interrupt for event SEQSTARTED[0] */ + #define PWM_INTPEND_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Msk (0x1UL << PWM_INTPEND_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED0 field. */ + #define PWM_INTPEND_SEQSTARTED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQSTARTED0_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQSTARTED1 @Bit 3 : Read pending status of interrupt for event SEQSTARTED[1] */ + #define PWM_INTPEND_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Msk (0x1UL << PWM_INTPEND_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Min (0x0UL) /*!< Min enumerator value of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_Max (0x1UL) /*!< Max enumerator value of SEQSTARTED1 field. */ + #define PWM_INTPEND_SEQSTARTED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQSTARTED1_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQEND0 @Bit 4 : Read pending status of interrupt for event SEQEND[0] */ + #define PWM_INTPEND_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Msk (0x1UL << PWM_INTPEND_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Min (0x0UL) /*!< Min enumerator value of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_Max (0x1UL) /*!< Max enumerator value of SEQEND0 field. */ + #define PWM_INTPEND_SEQEND0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQEND0_Pending (0x1UL) /*!< Read: Pending */ + +/* SEQEND1 @Bit 5 : Read pending status of interrupt for event SEQEND[1] */ + #define PWM_INTPEND_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Msk (0x1UL << PWM_INTPEND_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Min (0x0UL) /*!< Min enumerator value of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_Max (0x1UL) /*!< Max enumerator value of SEQEND1 field. */ + #define PWM_INTPEND_SEQEND1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_SEQEND1_Pending (0x1UL) /*!< Read: Pending */ + +/* PWMPERIODEND @Bit 6 : Read pending status of interrupt for event PWMPERIODEND */ + #define PWM_INTPEND_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Msk (0x1UL << PWM_INTPEND_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of PWMPERIODEND field. */ + #define PWM_INTPEND_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending */ + +/* LOOPSDONE @Bit 7 : Read pending status of interrupt for event LOOPSDONE */ + #define PWM_INTPEND_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Msk (0x1UL << PWM_INTPEND_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE field. */ + #define PWM_INTPEND_LOOPSDONE_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_LOOPSDONE_Pending (0x1UL) /*!< Read: Pending */ + +/* RAMUNDERFLOW @Bit 8 : Read pending status of interrupt for event RAMUNDERFLOW */ + #define PWM_INTPEND_RAMUNDERFLOW_Pos (8UL) /*!< Position of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Msk (0x1UL << PWM_INTPEND_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of RAMUNDERFLOW field. */ + #define PWM_INTPEND_RAMUNDERFLOW_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_RAMUNDERFLOW_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0END @Bit 9 : Read pending status of interrupt for event DMASEQ0END */ + #define PWM_INTPEND_DMASEQ0END_Pos (9UL) /*!< Position of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Msk (0x1UL << PWM_INTPEND_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Min (0x0UL) /*!< Min enumerator value of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_Max (0x1UL) /*!< Max enumerator value of DMASEQ0END field. */ + #define PWM_INTPEND_DMASEQ0END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0END_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0READY @Bit 10 : Read pending status of interrupt for event DMASEQ0READY */ + #define PWM_INTPEND_DMASEQ0READY_Pos (10UL) /*!< Position of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Msk (0x1UL << PWM_INTPEND_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ0READY field. */ + #define PWM_INTPEND_DMASEQ0READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ0BUSERROR @Bit 11 : Read pending status of interrupt for event DMASEQ0BUSERROR */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Pos (11UL) /*!< Position of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ0BUSERROR field. */ + #define PWM_INTPEND_DMASEQ0BUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ0BUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1END @Bit 12 : Read pending status of interrupt for event DMASEQ1END */ + #define PWM_INTPEND_DMASEQ1END_Pos (12UL) /*!< Position of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Msk (0x1UL << PWM_INTPEND_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Min (0x0UL) /*!< Min enumerator value of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_Max (0x1UL) /*!< Max enumerator value of DMASEQ1END field. */ + #define PWM_INTPEND_DMASEQ1END_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1END_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1READY @Bit 13 : Read pending status of interrupt for event DMASEQ1READY */ + #define PWM_INTPEND_DMASEQ1READY_Pos (13UL) /*!< Position of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Msk (0x1UL << PWM_INTPEND_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Min (0x0UL) /*!< Min enumerator value of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_Max (0x1UL) /*!< Max enumerator value of DMASEQ1READY field. */ + #define PWM_INTPEND_DMASEQ1READY_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1READY_Pending (0x1UL) /*!< Read: Pending */ + +/* DMASEQ1BUSERROR @Bit 14 : Read pending status of interrupt for event DMASEQ1BUSERROR */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Pos (14UL) /*!< Position of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Min (0x0UL) /*!< Min enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Max (0x1UL) /*!< Max enumerator value of DMASEQ1BUSERROR field. */ + #define PWM_INTPEND_DMASEQ1BUSERROR_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_DMASEQ1BUSERROR_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH0 @Bit 15 : Read pending status of interrupt for event COMPAREMATCH[0] */ + #define PWM_INTPEND_COMPAREMATCH0_Pos (15UL) /*!< Position of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH0 field. */ + #define PWM_INTPEND_COMPAREMATCH0_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH0_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH1 @Bit 16 : Read pending status of interrupt for event COMPAREMATCH[1] */ + #define PWM_INTPEND_COMPAREMATCH1_Pos (16UL) /*!< Position of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH1 field. */ + #define PWM_INTPEND_COMPAREMATCH1_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH1_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH2 @Bit 17 : Read pending status of interrupt for event COMPAREMATCH[2] */ + #define PWM_INTPEND_COMPAREMATCH2_Pos (17UL) /*!< Position of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH2 field. */ + #define PWM_INTPEND_COMPAREMATCH2_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH2_Pending (0x1UL) /*!< Read: Pending */ + +/* COMPAREMATCH3 @Bit 18 : Read pending status of interrupt for event COMPAREMATCH[3] */ + #define PWM_INTPEND_COMPAREMATCH3_Pos (18UL) /*!< Position of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Min (0x0UL) /*!< Min enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_Max (0x1UL) /*!< Max enumerator value of COMPAREMATCH3 field. */ + #define PWM_INTPEND_COMPAREMATCH3_NotPending (0x0UL) /*!< Read: Not pending */ + #define PWM_INTPEND_COMPAREMATCH3_Pending (0x1UL) /*!< Read: Pending */ + + +/* PWM_ENABLE: PWM module enable register */ + #define PWM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable PWM module */ + #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */ + #define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* PWM_MODE: Selects operating mode of the wave counter */ + #define PWM_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* UPDOWN @Bit 0 : Selects up mode or up-and-down mode for the counter */ + #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Min (0x0UL) /*!< Min enumerator value of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Max (0x1UL) /*!< Max enumerator value of UPDOWN field. */ + #define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */ + #define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + + +/* PWM_COUNTERTOP: Value up to which the pulse generator counter counts */ + #define PWM_COUNTERTOP_ResetValue (0x000003FFUL) /*!< Reset value of COUNTERTOP register. */ + +/* COUNTERTOP @Bits 0..14 : Value up to which the pulse generator counter counts. This register is ignored when + DECODER.MODE=WaveForm and only values from RAM are used. */ + + #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Min (0x0003UL) /*!< Min value of COUNTERTOP field. */ + #define PWM_COUNTERTOP_COUNTERTOP_Max (0x7FFFUL) /*!< Max size of COUNTERTOP field. */ + + +/* PWM_PRESCALER: Configuration for PWM_CLK */ + #define PWM_PRESCALER_ResetValue (0x00000000UL) /*!< Reset value of PRESCALER register. */ + +/* PRESCALER @Bits 0..2 : Prescaler of PWM_CLK */ + #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Min (0x0UL) /*!< Min enumerator value of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_Max (0x7UL) /*!< Max enumerator value of PRESCALER field. */ + #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */ + #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */ + + +/* PWM_DECODER: Configuration of the decoder */ + #define PWM_DECODER_ResetValue (0x00000000UL) /*!< Reset value of DECODER register. */ + +/* LOAD @Bits 0..1 : How a sequence is read from RAM and spread to the compare register */ + #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ + #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ + #define PWM_DECODER_LOAD_Min (0x0UL) /*!< Min enumerator value of LOAD field. */ + #define PWM_DECODER_LOAD_Max (0x3UL) /*!< Max enumerator value of LOAD field. */ + #define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ + #define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3*/ + #define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ + #define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* MODE @Bit 8 : Selects source for advancing the active sequence */ + #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ + #define PWM_DECODER_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define PWM_DECODER_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare + registers*/ + #define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare + registers*/ + + +/* PWM_LOOP: Number of playbacks of a loop */ + #define PWM_LOOP_ResetValue (0x00000000UL) /*!< Reset value of LOOP register. */ + +/* CNT @Bits 0..15 : Number of playbacks of pattern cycles */ + #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ + #define PWM_LOOP_CNT_Min (0x0UL) /*!< Min enumerator value of CNT field. */ + #define PWM_LOOP_CNT_Max (0x0UL) /*!< Max enumerator value of CNT field. */ + #define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */ + + +/* PWM_IDLEOUT: Configure the output value on the PWM channel during idle */ + #define PWM_IDLEOUT_ResetValue (0x00000000UL) /*!< Reset value of IDLEOUT register. */ + +/* VAL0 @Bit 0 : Idle output value for PWM channel [0] */ + #define PWM_IDLEOUT_VAL0_Pos (0UL) /*!< Position of VAL0 field. */ + #define PWM_IDLEOUT_VAL0_Msk (0x1UL << PWM_IDLEOUT_VAL0_Pos) /*!< Bit mask of VAL0 field. */ + +/* VAL1 @Bit 1 : Idle output value for PWM channel [1] */ + #define PWM_IDLEOUT_VAL1_Pos (1UL) /*!< Position of VAL1 field. */ + #define PWM_IDLEOUT_VAL1_Msk (0x1UL << PWM_IDLEOUT_VAL1_Pos) /*!< Bit mask of VAL1 field. */ + +/* VAL2 @Bit 2 : Idle output value for PWM channel [2] */ + #define PWM_IDLEOUT_VAL2_Pos (2UL) /*!< Position of VAL2 field. */ + #define PWM_IDLEOUT_VAL2_Msk (0x1UL << PWM_IDLEOUT_VAL2_Pos) /*!< Bit mask of VAL2 field. */ + +/* VAL3 @Bit 3 : Idle output value for PWM channel [3] */ + #define PWM_IDLEOUT_VAL3_Pos (3UL) /*!< Position of VAL3 field. */ + #define PWM_IDLEOUT_VAL3_Msk (0x1UL << PWM_IDLEOUT_VAL3_Pos) /*!< Bit mask of VAL3 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct QDEC_PSEL ===================================================== */ +/** + * @brief PSEL [QDEC_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} NRF_QDEC_PSEL_Type; /*!< Size = 12 (0x00C) */ + +/* QDEC_PSEL_LED: Pin select for LED signal */ + #define QDEC_PSEL_LED_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LED register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_LED_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_LED_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_LED_PORT_Msk (0xFUL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_LED_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_LED_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_LED_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* QDEC_PSEL_A: Pin select for A signal */ + #define QDEC_PSEL_A_ResetValue (0xFFFFFFFFUL) /*!< Reset value of A register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_A_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_A_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_A_PORT_Msk (0xFUL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_A_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_A_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_A_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* QDEC_PSEL_B: Pin select for B signal */ + #define QDEC_PSEL_B_ResetValue (0xFFFFFFFFUL) /*!< Reset value of B register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + #define QDEC_PSEL_B_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define QDEC_PSEL_B_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define QDEC_PSEL_B_PORT_Msk (0xFUL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ + #define QDEC_PSEL_B_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define QDEC_PSEL_B_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define QDEC_PSEL_B_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* ======================================================= Struct QDEC ======================================================= */ +/** + * @brief Quadrature Decoder + */ + typedef struct { /*!< QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[27]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_READCLRACC; /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC */ + __IOM uint32_t SUBSCRIBE_RDCLRACC; /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC */ + __IOM uint32_t SUBSCRIBE_RDCLRDBL; /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL */ + __IM uint32_t RESERVED1[27]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register*/ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED2[27]; + __IOM uint32_t PUBLISH_SAMPLERDY; /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY */ + __IOM uint32_t PUBLISH_REPORTRDY; /*!< (@ 0x00000184) Publish configuration for event REPORTRDY */ + __IOM uint32_t PUBLISH_ACCOF; /*!< (@ 0x00000188) Publish configuration for event ACCOF */ + __IOM uint32_t PUBLISH_DBLRDY; /*!< (@ 0x0000018C) Publish configuration for event DBLRDY */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000190) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY and + DBLRDY events can be generated*/ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the READCLRACC + or RDCLRACC task*/ + __IOM NRF_QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) (unspecified) */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected double + transitions*/ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC or + RDCLRDBL task*/ + } NRF_QDEC_Type; /*!< Size = 1356 (0x54C) */ + +/* QDEC_TASKS_START: Task starting the quadrature decoder */ + #define QDEC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Task starting the quadrature decoder */ + #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_STOP: Task stopping the quadrature decoder */ + #define QDEC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Task stopping the quadrature decoder */ + #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_READCLRACC: Read and clear ACC and ACCDBL */ + #define QDEC_TASKS_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READCLRACC register. */ + +/* TASKS_READCLRACC @Bit 0 : Read and clear ACC and ACCDBL */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of + TASKS_READCLRACC field.*/ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_READCLRACC field. */ + #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_RDCLRACC: Read and clear ACC */ + #define QDEC_TASKS_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRACC register. */ + +/* TASKS_RDCLRACC @Bit 0 : Read and clear ACC */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of + TASKS_RDCLRACC field.*/ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRACC field. */ + #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_TASKS_RDCLRDBL: Read and clear ACCDBL */ + #define QDEC_TASKS_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRDBL register. */ + +/* TASKS_RDCLRDBL @Bit 0 : Read and clear ACCDBL */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of + TASKS_RDCLRDBL field.*/ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRDBL field. */ + #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task */ + + +/* QDEC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define QDEC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define QDEC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_READCLRACC: Subscribe configuration for task READCLRACC */ + #define QDEC_SUBSCRIBE_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_READCLRACC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task READCLRACC will subscribe to */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_RDCLRACC: Subscribe configuration for task RDCLRACC */ + #define QDEC_SUBSCRIBE_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRACC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRACC will subscribe to */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_SUBSCRIBE_RDCLRDBL: Subscribe configuration for task RDCLRDBL */ + #define QDEC_SUBSCRIBE_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRDBL register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRDBL will subscribe to */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* QDEC_EVENTS_SAMPLERDY: Event being generated for every new sample value written to the SAMPLE register */ + #define QDEC_EVENTS_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SAMPLERDY register. */ + +/* EVENTS_SAMPLERDY @Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of + EVENTS_SAMPLERDY field.*/ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_SAMPLERDY field. */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_REPORTRDY: Non-null report ready */ + #define QDEC_EVENTS_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REPORTRDY register. */ + +/* EVENTS_REPORTRDY @Bit 0 : Non-null report ready */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of + EVENTS_REPORTRDY field.*/ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_REPORTRDY field. */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_ACCOF: ACC or ACCDBL register overflow */ + #define QDEC_EVENTS_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCOF register. */ + +/* EVENTS_ACCOF @Bit 0 : ACC or ACCDBL register overflow */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field.*/ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCOF field. */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_DBLRDY: Double displacement(s) detected */ + #define QDEC_EVENTS_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DBLRDY register. */ + +/* EVENTS_DBLRDY @Bit 0 : Double displacement(s) detected */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY + field.*/ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DBLRDY field. */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_EVENTS_STOPPED: QDEC has been stopped */ + #define QDEC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : QDEC has been stopped */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* QDEC_PUBLISH_SAMPLERDY: Publish configuration for event SAMPLERDY */ + #define QDEC_PUBLISH_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SAMPLERDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SAMPLERDY will publish to */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_REPORTRDY: Publish configuration for event REPORTRDY */ + #define QDEC_PUBLISH_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_REPORTRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event REPORTRDY will publish to */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_REPORTRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_ACCOF: Publish configuration for event ACCOF */ + #define QDEC_PUBLISH_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACCOF register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ACCOF will publish to */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_ACCOF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_ACCOF_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_ACCOF_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_DBLRDY: Publish configuration for event DBLRDY */ + #define QDEC_PUBLISH_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DBLRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DBLRDY will publish to */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_DBLRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_DBLRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define QDEC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define QDEC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define QDEC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define QDEC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* QDEC_SHORTS: Shortcuts between local events and tasks */ + #define QDEC_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* REPORTRDY_READCLRACC @Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of + REPORTRDY_READCLRACC field.*/ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_READCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SAMPLERDY_STOP @Bit 1 : Shortcut between event SAMPLERDY and task STOP */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_STOP field. */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* REPORTRDY_RDCLRACC @Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC + field.*/ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_RDCLRACC field. */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + +/* REPORTRDY_STOP @Bit 3 : Shortcut between event REPORTRDY and task STOP */ + #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_STOP field. */ + #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DBLRDY_RDCLRDBL @Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Min (0x0UL) /*!< Min enumerator value of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of DBLRDY_RDCLRDBL field. */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DBLRDY_STOP @Bit 5 : Shortcut between event DBLRDY and task STOP */ + #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Min (0x0UL) /*!< Min enumerator value of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Max (0x1UL) /*!< Max enumerator value of DBLRDY_STOP field. */ + #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* SAMPLERDY_READCLRACC @Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of + SAMPLERDY_READCLRACC field.*/ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_READCLRACC field. */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut */ + #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* QDEC_INTENSET: Enable interrupt */ + #define QDEC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* SAMPLERDY @Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ + #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY field. */ + #define QDEC_INTENSET_SAMPLERDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* REPORTRDY @Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ + #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of REPORTRDY field. */ + #define QDEC_INTENSET_REPORTRDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCOF @Bit 2 : Write '1' to enable interrupt for event ACCOF */ + #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Min (0x0UL) /*!< Min enumerator value of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Max (0x1UL) /*!< Max enumerator value of ACCOF field. */ + #define QDEC_INTENSET_ACCOF_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DBLRDY @Bit 3 : Write '1' to enable interrupt for event DBLRDY */ + #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Min (0x0UL) /*!< Min enumerator value of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Max (0x1UL) /*!< Max enumerator value of DBLRDY field. */ + #define QDEC_INTENSET_DBLRDY_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 4 : Write '1' to enable interrupt for event STOPPED */ + #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define QDEC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define QDEC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* QDEC_INTENCLR: Disable interrupt */ + #define QDEC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* SAMPLERDY @Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ + #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY field. */ + #define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* REPORTRDY @Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ + #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of REPORTRDY field. */ + #define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACCOF @Bit 2 : Write '1' to disable interrupt for event ACCOF */ + #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Min (0x0UL) /*!< Min enumerator value of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Max (0x1UL) /*!< Max enumerator value of ACCOF field. */ + #define QDEC_INTENCLR_ACCOF_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_ACCOF_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_ACCOF_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DBLRDY @Bit 3 : Write '1' to disable interrupt for event DBLRDY */ + #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Min (0x0UL) /*!< Min enumerator value of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Max (0x1UL) /*!< Max enumerator value of DBLRDY field. */ + #define QDEC_INTENCLR_DBLRDY_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 4 : Write '1' to disable interrupt for event STOPPED */ + #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define QDEC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define QDEC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define QDEC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* QDEC_ENABLE: Enable the quadrature decoder */ + #define QDEC_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable the quadrature decoder */ + #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define QDEC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define QDEC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* QDEC_LEDPOL: LED output pin polarity */ + #define QDEC_LEDPOL_ResetValue (0x00000000UL) /*!< Reset value of LEDPOL register. */ + +/* LEDPOL @Bit 0 : LED output pin polarity */ + #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Min (0x0UL) /*!< Min enumerator value of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_Max (0x1UL) /*!< Max enumerator value of LEDPOL field. */ + #define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL) /*!< Led active on output pin low */ + #define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL) /*!< Led active on output pin high */ + + +/* QDEC_SAMPLEPER: Sample period */ + #define QDEC_SAMPLEPER_ResetValue (0x00000000UL) /*!< Reset value of SAMPLEPER register. */ + +/* SAMPLEPER @Bits 0..3 : Sample period. The SAMPLE register will be updated for every new sample */ + #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Min (0x0UL) /*!< Min enumerator value of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_Max (0xAUL) /*!< Max enumerator value of SAMPLEPER field. */ + #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL) /*!< 128 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL) /*!< 256 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL) /*!< 512 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL) /*!< 1024 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL) /*!< 2048 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL) /*!< 4096 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL) /*!< 8192 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL) /*!< 16384 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL) /*!< 32768 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL) /*!< 65536 us */ + #define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL) /*!< 131072 us */ + + +/* QDEC_SAMPLE: Motion sample value */ + #define QDEC_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLE register. */ + +/* SAMPLE @Bits 0..31 : Last motion sample */ + #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Min (0xFFFFFFFFUL) /*!< Min value of SAMPLE field. */ + #define QDEC_SAMPLE_SAMPLE_Max (0x00000002UL) /*!< Max size of SAMPLE field. */ + + +/* QDEC_REPORTPER: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + #define QDEC_REPORTPER_ResetValue (0x00000000UL) /*!< Reset value of REPORTPER register. */ + +/* REPORTPER @Bits 0..3 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY + events can be generated. */ + + #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Min (0x0UL) /*!< Min enumerator value of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_Max (0x8UL) /*!< Max enumerator value of REPORTPER field. */ + #define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL) /*!< 10 samples/report */ + #define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL) /*!< 40 samples/report */ + #define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL) /*!< 80 samples/report */ + #define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL) /*!< 120 samples/report */ + #define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL) /*!< 160 samples/report */ + #define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL) /*!< 200 samples/report */ + #define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL) /*!< 240 samples/report */ + #define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL) /*!< 280 samples/report */ + #define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL) /*!< 1 sample/report */ + + +/* QDEC_ACC: Register accumulating the valid transitions */ + #define QDEC_ACC_ResetValue (0x00000000UL) /*!< Reset value of ACC register. */ + +/* ACC @Bits 0..31 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ + #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ + #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + #define QDEC_ACC_ACC_Min (0xFFFFFC00UL) /*!< Min value of ACC field. */ + #define QDEC_ACC_ACC_Max (0x000003FFUL) /*!< Max size of ACC field. */ + + +/* QDEC_ACCREAD: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + #define QDEC_ACCREAD_ResetValue (0x00000000UL) /*!< Reset value of ACCREAD register. */ + +/* ACCREAD @Bits 0..31 : Snapshot of the ACC register. */ + #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Min (0xFFFFFC00UL) /*!< Min value of ACCREAD field. */ + #define QDEC_ACCREAD_ACCREAD_Max (0x000003FFUL) /*!< Max size of ACCREAD field. */ + + +/* QDEC_DBFEN: Enable input debounce filters */ + #define QDEC_DBFEN_ResetValue (0x00000000UL) /*!< Reset value of DBFEN register. */ + +/* DBFEN @Bit 0 : Enable input debounce filters */ + #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Min (0x0UL) /*!< Min enumerator value of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Max (0x1UL) /*!< Max enumerator value of DBFEN field. */ + #define QDEC_DBFEN_DBFEN_Disabled (0x0UL) /*!< Debounce input filters disabled */ + #define QDEC_DBFEN_DBFEN_Enabled (0x1UL) /*!< Debounce input filters enabled */ + + +/* QDEC_LEDPRE: Time period the LED is switched ON prior to sampling */ + #define QDEC_LEDPRE_ResetValue (0x00000010UL) /*!< Reset value of LEDPRE register. */ + +/* LEDPRE @Bits 0..8 : Period in us the LED is switched on prior to sampling */ + #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Min (0x001UL) /*!< Min value of LEDPRE field. */ + #define QDEC_LEDPRE_LEDPRE_Max (0x1FFUL) /*!< Max size of LEDPRE field. */ + + +/* QDEC_ACCDBL: Register accumulating the number of detected double transitions */ + #define QDEC_ACCDBL_ResetValue (0x00000000UL) /*!< Reset value of ACCDBL register. */ + +/* ACCDBL @Bits 0..3 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ + #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Min (0x0UL) /*!< Min value of ACCDBL field. */ + #define QDEC_ACCDBL_ACCDBL_Max (0xFUL) /*!< Max size of ACCDBL field. */ + + +/* QDEC_ACCDBLREAD: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + #define QDEC_ACCDBLREAD_ResetValue (0x00000000UL) /*!< Reset value of ACCDBLREAD register. */ + +/* ACCDBLREAD @Bits 0..3 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is + triggered. */ + + #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Min (0x0UL) /*!< Min value of ACCDBLREAD field. */ + #define QDEC_ACCDBLREAD_ACCDBLREAD_Max (0xFUL) /*!< Max size of ACCDBLREAD field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ==================================================== Struct RADIO_PSEL ==================================================== */ +/** + * @brief PSEL [RADIO_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Pin select for DFE pin n */ +} NRF_RADIO_PSEL_Type; /*!< Size = 32 (0x020) */ + +/* RADIO_PSEL_DFEGPIO: Pin select for DFE pin n */ + #define RADIO_PSEL_DFEGPIO_MaxCount (8UL) /*!< Max size of DFEGPIO[8] array. */ + #define RADIO_PSEL_DFEGPIO_MaxIndex (7UL) /*!< Max index of DFEGPIO[8] array. */ + #define RADIO_PSEL_DFEGPIO_MinIndex (0UL) /*!< Min index of DFEGPIO[8] array. */ + #define RADIO_PSEL_DFEGPIO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DFEGPIO[8] register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define RADIO_PSEL_DFEGPIO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Msk (0xFUL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define RADIO_PSEL_DFEGPIO_PORT_Max (0x1UL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================= Struct RADIO_DFEPACKET ================================================== */ +/** + * @brief DFEPACKET [RADIO_DFEPACKET] DFE packet EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the current transaction*/ + __IM uint32_t RESERVED[2]; +} NRF_RADIO_DFEPACKET_Type; /*!< Size = 24 (0x018) */ + +/* RADIO_DFEPACKET_PTR: Data pointer */ + #define RADIO_DFEPACKET_PTR_ResetValue (0x01000000UL) /*!< Reset value of PTR register. */ + +/* OFFSET @Bits 0..15 : Data pointer */ + #define RADIO_DFEPACKET_PTR_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define RADIO_DFEPACKET_PTR_OFFSET_Msk (0xFFFFUL << RADIO_DFEPACKET_PTR_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + +/* BASE @Bit 29 : (unspecified) */ + #define RADIO_DFEPACKET_PTR_BASE_Pos (29UL) /*!< Position of BASE field. */ + #define RADIO_DFEPACKET_PTR_BASE_Msk (0x1UL << RADIO_DFEPACKET_PTR_BASE_Pos) /*!< Bit mask of BASE field. */ + + +/* RADIO_DFEPACKET_MAXCNT: Maximum number of bytes to transfer */ + #define RADIO_DFEPACKET_MAXCNT_ResetValue (0x00004000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..15 : Maximum number of bytes to transfer */ + #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0xFFFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* RADIO_DFEPACKET_AMOUNT: Number of bytes transferred in the last transaction */ + #define RADIO_DFEPACKET_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction */ + #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* RADIO_DFEPACKET_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..15 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of + AMOUNT field.*/ + + +/* ====================================================== Struct RADIO ======================================================= */ +/** + * @brief 2.4 GHz radio + */ + typedef struct { /*!< RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of the + receive signal strength*/ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x00000018) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x0000001C) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000020) Start the energy detect measurement used in IEEE + 802.15.4 mode*/ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000024) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x00000028) Start the clear channel assessment used in IEEE + 802.15.4 mode*/ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x0000002C) Stop the clear channel assessment */ + __IM uint32_t RESERVED[52]; + __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000100) Subscribe configuration for task TXEN */ + __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000104) Subscribe configuration for task RXEN */ + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000108) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000010C) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000110) Subscribe configuration for task DISABLE */ + __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000114) Subscribe configuration for task RSSISTART */ + __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x00000118) Subscribe configuration for task BCSTART */ + __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x0000011C) Subscribe configuration for task BCSTOP */ + __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x00000120) Subscribe configuration for task EDSTART */ + __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x00000124) Subscribe configuration for task EDSTOP */ + __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x00000128) Subscribe configuration for task CCASTART */ + __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x0000012C) Subscribe configuration for task CCASTOP */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000200) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000204) RADIO has ramped up and is ready to be started TX path*/ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000208) RADIO has ramped up and is ready to be started RX path*/ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x0000020C) Address sent or received */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000210) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000214) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000218) Packet sent or received */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000021C) The last bit is sent on air or last bit is received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000220) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000224) A device address match occurred on the last received + packet*/ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000228) No device address match occurred on the last received + packet*/ + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x0000022C) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000230) Packet received with CRC error */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000238) Bit counter reached bit count value */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000023C) Sampling of energy detection complete (a new ED sample + is ready for readout from the RADIO.EDSAMPLE register)*/ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000240) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000244) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000248) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000024C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000250) Ble_LR CI field received, receive mode is changed from + Ble_LR125Kbit to Ble_LR500Kbit*/ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x00000254) MAC header match found */ + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000258) Initial sync detected */ + __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x0000025C) CTEInfo byte is received */ + __IM uint32_t RESERVED3[40]; + __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000300) Publish configuration for event READY */ + __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x00000304) Publish configuration for event TXREADY */ + __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x00000308) Publish configuration for event RXREADY */ + __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x0000030C) Publish configuration for event ADDRESS */ + __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x00000310) Publish configuration for event FRAMESTART */ + __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000314) Publish configuration for event PAYLOAD */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000318) Publish configuration for event END */ + __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x0000031C) Publish configuration for event PHYEND */ + __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000320) Publish configuration for event DISABLED */ + __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000324) Publish configuration for event DEVMATCH */ + __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000328) Publish configuration for event DEVMISS */ + __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x0000032C) Publish configuration for event CRCOK */ + __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x00000330) Publish configuration for event CRCERROR */ + __IM uint32_t RESERVED4; + __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x00000338) Publish configuration for event BCMATCH */ + __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x0000033C) Publish configuration for event EDEND */ + __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x00000340) Publish configuration for event EDSTOPPED */ + __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x00000344) Publish configuration for event CCAIDLE */ + __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x00000348) Publish configuration for event CCABUSY */ + __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x0000034C) Publish configuration for event CCASTOPPED */ + __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x00000350) Publish configuration for event RATEBOOST */ + __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x00000354) Publish configuration for event MHRMATCH */ + __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x00000358) Publish configuration for event SYNC */ + __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x0000035C) Publish configuration for event CTEPRESENT */ + __IM uint32_t RESERVED5[40]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000400) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[33]; + __IOM uint32_t INTENSET00; /*!< (@ 0x00000488) Enable interrupt */ + __IM uint32_t RESERVED7; + __IOM uint32_t INTENCLR00; /*!< (@ 0x00000490) Disable interrupt */ + __IM uint32_t RESERVED8[5]; + __IOM uint32_t INTENSET10; /*!< (@ 0x000004A8) Enable interrupt */ + __IM uint32_t RESERVED9; + __IOM uint32_t INTENCLR10; /*!< (@ 0x000004B0) Disable interrupt */ + __IM uint32_t RESERVED10[19]; + __IOM uint32_t MODE; /*!< (@ 0x00000500) Data rate and modulation */ + __IM uint32_t RESERVED11[7]; + __IM uint32_t STATE; /*!< (@ 0x00000520) Current radio state */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t EDCTRL; /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control */ + __IM uint32_t EDSAMPLE; /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED13; + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000540) Data whitening initial value */ + __IM uint32_t RESERVED14[112]; + __IOM uint32_t TIMING; /*!< (@ 0x00000704) Timing */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000708) Frequency */ + __IM uint32_t RESERVED15; + __IOM uint32_t TXPOWER; /*!< (@ 0x00000710) Output power */ + __IOM uint32_t TIFS; /*!< (@ 0x00000714) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000718) RSSI sample */ + __IM uint32_t RESERVED16[377]; + __IOM uint32_t DFEMODE; /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or + Angle-of-Departure (AOD)*/ + __IM uint32_t DFESTATUS; /*!< (@ 0x00000D04) DFE status information */ + __IM uint32_t RESERVED17[2]; + __IOM uint32_t DFECTRL1; /*!< (@ 0x00000D10) Various configuration for Direction finding */ + __IOM uint32_t DFECTRL2; /*!< (@ 0x00000D14) Start offset for Direction finding */ + __IM uint32_t RESERVED18[4]; + __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna */ + __OM uint32_t CLEARPATTERN; /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control */ + __IOM NRF_RADIO_PSEL_Type PSEL; /*!< (@ 0x00000D30) (unspecified) */ + __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000D50) DFE packet EasyDMA channel */ + __IM uint32_t RESERVED19[41]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000E0C) CRC status */ + __IM uint32_t RXMATCH; /*!< (@ 0x00000E10) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x00000E14) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000E18) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000E1C) Payload status */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000E20) Packet configuration register 0 */ + __IM uint32_t RESERVED20; + __IOM uint32_t PCNF1; /*!< (@ 0x00000E28) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x00000E2C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000E30) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000E34) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000E38) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x00000E3C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000E40) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000E44) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000E48) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x00000E4C) CRC initial value */ + __IOM uint32_t DAB[8]; /*!< (@ 0x00000E50) Device address base segment n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000E70) Device address prefix n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000E90) Device address match configuration */ + __IOM uint32_t BCC; /*!< (@ 0x00000E94) Bit counter compare */ + __IM uint32_t RESERVED21[3]; + __IM uint32_t CTESTATUS; /*!< (@ 0x00000EA4) CTEInfo parsed from received packet */ + __IM uint32_t RESERVED22[3]; + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000EB4) Search pattern configuration */ + __IOM uint32_t MHRMATCHMASK; /*!< (@ 0x00000EB8) Pattern mask */ + __IOM uint32_t SFD; /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000EC0) Configuration for CTE inline mode */ + __IM uint32_t RESERVED23[3]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000ED0) (unspecified) */ + __IM uint32_t RESERVED24[74]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ + } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + +/* RADIO_TASKS_TXEN: Enable RADIO in TX mode */ + #define RADIO_TASKS_TXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TXEN register. */ + +/* TASKS_TXEN @Bit 0 : Enable RADIO in TX mode */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Min (0x1UL) /*!< Min enumerator value of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Max (0x1UL) /*!< Max enumerator value of TASKS_TXEN field. */ + #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_RXEN: Enable RADIO in RX mode */ + #define RADIO_TASKS_RXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RXEN register. */ + +/* TASKS_RXEN @Bit 0 : Enable RADIO in RX mode */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Min (0x1UL) /*!< Min enumerator value of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Max (0x1UL) /*!< Max enumerator value of TASKS_RXEN field. */ + #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_START: Start RADIO */ + #define RADIO_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start RADIO */ + #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define RADIO_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_STOP: Stop RADIO */ + #define RADIO_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop RADIO */ + #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_DISABLE: Disable RADIO */ + #define RADIO_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register. */ + +/* TASKS_DISABLE @Bit 0 : Disable RADIO */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE + field.*/ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field. */ + #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_RSSISTART: Start the RSSI and take one single sample of the receive signal strength */ + #define RADIO_TASKS_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RSSISTART register. */ + +/* TASKS_RSSISTART @Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of + TASKS_RSSISTART field.*/ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Min (0x1UL) /*!< Min enumerator value of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of TASKS_RSSISTART field. */ + #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_BCSTART: Start the bit counter */ + #define RADIO_TASKS_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTART register. */ + +/* TASKS_BCSTART @Bit 0 : Start the bit counter */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART + field.*/ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTART field. */ + #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_BCSTOP: Stop the bit counter */ + #define RADIO_TASKS_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTOP register. */ + +/* TASKS_BCSTOP @Bit 0 : Stop the bit counter */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP + field.*/ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTOP field. */ + #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_EDSTART: Start the energy detect measurement used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTART register. */ + +/* TASKS_EDSTART @Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART + field.*/ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTART field. */ + #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_EDSTOP: Stop the energy detect measurement */ + #define RADIO_TASKS_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTOP register. */ + +/* TASKS_EDSTOP @Bit 0 : Stop the energy detect measurement */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP + field.*/ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTOP field. */ + #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CCASTART: Start the clear channel assessment used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTART register. */ + +/* TASKS_CCASTART @Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of + TASKS_CCASTART field.*/ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTART field. */ + #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_TASKS_CCASTOP: Stop the clear channel assessment */ + #define RADIO_TASKS_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTOP register. */ + +/* TASKS_CCASTOP @Bit 0 : Stop the clear channel assessment */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP + field.*/ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTOP field. */ + #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RADIO_SUBSCRIBE_TXEN: Subscribe configuration for task TXEN */ + #define RADIO_SUBSCRIBE_TXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TXEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task TXEN will subscribe to */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_TXEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_RXEN: Subscribe configuration for task RXEN */ + #define RADIO_SUBSCRIBE_RXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RXEN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RXEN will subscribe to */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_RXEN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_START: Subscribe configuration for task START */ + #define RADIO_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define RADIO_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */ + #define RADIO_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_RSSISTART: Subscribe configuration for task RSSISTART */ + #define RADIO_SUBSCRIBE_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RSSISTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RSSISTART will subscribe to */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_BCSTART: Subscribe configuration for task BCSTART */ + #define RADIO_SUBSCRIBE_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task BCSTART will subscribe to */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_BCSTOP: Subscribe configuration for task BCSTOP */ + #define RADIO_SUBSCRIBE_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task BCSTOP will subscribe to */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_EDSTART: Subscribe configuration for task EDSTART */ + #define RADIO_SUBSCRIBE_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task EDSTART will subscribe to */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_EDSTOP: Subscribe configuration for task EDSTOP */ + #define RADIO_SUBSCRIBE_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task EDSTOP will subscribe to */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CCASTART: Subscribe configuration for task CCASTART */ + #define RADIO_SUBSCRIBE_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CCASTART will subscribe to */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_SUBSCRIBE_CCASTOP: Subscribe configuration for task CCASTOP */ + #define RADIO_SUBSCRIBE_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CCASTOP will subscribe to */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RADIO_EVENTS_READY: RADIO has ramped up and is ready to be started */ + #define RADIO_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register. */ + +/* EVENTS_READY @Bit 0 : RADIO has ramped up and is ready to be started */ + #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY + field.*/ + #define RADIO_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field. */ + #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_TXREADY: RADIO has ramped up and is ready to be started TX path */ + #define RADIO_EVENTS_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXREADY register. */ + +/* EVENTS_TXREADY @Bit 0 : RADIO has ramped up and is ready to be started TX path */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of + EVENTS_TXREADY field.*/ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXREADY field. */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RXREADY: RADIO has ramped up and is ready to be started RX path */ + #define RADIO_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register. */ + +/* EVENTS_RXREADY @Bit 0 : RADIO has ramped up and is ready to be started RX path */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of + EVENTS_RXREADY field.*/ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field. */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_ADDRESS: Address sent or received */ + #define RADIO_EVENTS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ADDRESS register. */ + +/* EVENTS_ADDRESS @Bit 0 : Address sent or received */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of + EVENTS_ADDRESS field.*/ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_ADDRESS field. */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_FRAMESTART: IEEE 802.15.4 length field received */ + #define RADIO_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register. */ + +/* EVENTS_FRAMESTART @Bit 0 : IEEE 802.15.4 length field received */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask + of EVENTS_FRAMESTART field.*/ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field. */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_PAYLOAD: Packet payload sent or received */ + #define RADIO_EVENTS_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PAYLOAD register. */ + +/* EVENTS_PAYLOAD @Bit 0 : Packet payload sent or received */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of + EVENTS_PAYLOAD field.*/ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_PAYLOAD field. */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_END: Packet sent or received */ + #define RADIO_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Packet sent or received */ + #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_PHYEND: The last bit is sent on air or last bit is received */ + #define RADIO_EVENTS_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PHYEND register. */ + +/* EVENTS_PHYEND @Bit 0 : The last bit is sent on air or last bit is received */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND + field.*/ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PHYEND field. */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DISABLED: RADIO has been disabled */ + #define RADIO_EVENTS_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DISABLED register. */ + +/* EVENTS_DISABLED @Bit 0 : RADIO has been disabled */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of + EVENTS_DISABLED field.*/ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Min (0x0UL) /*!< Min enumerator value of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Max (0x1UL) /*!< Max enumerator value of EVENTS_DISABLED field. */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DEVMATCH: A device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMATCH register. */ + +/* EVENTS_DEVMATCH @Bit 0 : A device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of + EVENTS_DEVMATCH field.*/ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMATCH field. */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_DEVMISS: No device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMISS register. */ + +/* EVENTS_DEVMISS @Bit 0 : No device address match occurred on the last received packet */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of + EVENTS_DEVMISS field.*/ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMISS field. */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CRCOK: Packet received with CRC ok */ + #define RADIO_EVENTS_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCOK register. */ + +/* EVENTS_CRCOK @Bit 0 : Packet received with CRC ok */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK + field.*/ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCOK field. */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CRCERROR: Packet received with CRC error */ + #define RADIO_EVENTS_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCERROR register. */ + +/* EVENTS_CRCERROR @Bit 0 : Packet received with CRC error */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of + EVENTS_CRCERROR field.*/ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCERROR field. */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_BCMATCH: Bit counter reached bit count value */ + #define RADIO_EVENTS_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_BCMATCH register. */ + +/* EVENTS_BCMATCH @Bit 0 : Bit counter reached bit count value */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of + EVENTS_BCMATCH field.*/ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_BCMATCH field. */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_EDEND: Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE + register) */ + + #define RADIO_EVENTS_EDEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDEND register. */ + +/* EVENTS_EDEND @Bit 0 : Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE + register) */ + + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND + field.*/ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDEND field. */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_EDSTOPPED: The sampling of energy detection has stopped */ + #define RADIO_EVENTS_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDSTOPPED register. */ + +/* EVENTS_EDSTOPPED @Bit 0 : The sampling of energy detection has stopped */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of + EVENTS_EDSTOPPED field.*/ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDSTOPPED field. */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCAIDLE: Wireless medium in idle - clear to send */ + #define RADIO_EVENTS_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCAIDLE register. */ + +/* EVENTS_CCAIDLE @Bit 0 : Wireless medium in idle - clear to send */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of + EVENTS_CCAIDLE field.*/ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCAIDLE field. */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCABUSY: Wireless medium busy - do not send */ + #define RADIO_EVENTS_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCABUSY register. */ + +/* EVENTS_CCABUSY @Bit 0 : Wireless medium busy - do not send */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of + EVENTS_CCABUSY field.*/ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCABUSY field. */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CCASTOPPED: The CCA has stopped */ + #define RADIO_EVENTS_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCASTOPPED register. */ + +/* EVENTS_CCASTOPPED @Bit 0 : The CCA has stopped */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask + of EVENTS_CCASTOPPED field.*/ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCASTOPPED field. */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_RATEBOOST: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */ + #define RADIO_EVENTS_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RATEBOOST register. */ + +/* EVENTS_RATEBOOST @Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of + EVENTS_RATEBOOST field.*/ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_RATEBOOST field. */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_MHRMATCH: MAC header match found */ + #define RADIO_EVENTS_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MHRMATCH register. */ + +/* EVENTS_MHRMATCH @Bit 0 : MAC header match found */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of + EVENTS_MHRMATCH field.*/ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_MHRMATCH field. */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_SYNC: Initial sync detected */ + #define RADIO_EVENTS_SYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYNC register. */ + +/* EVENTS_SYNC @Bit 0 : Initial sync detected */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Min (0x0UL) /*!< Min enumerator value of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Max (0x1UL) /*!< Max enumerator value of EVENTS_SYNC field. */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_EVENTS_CTEPRESENT: CTEInfo byte is received */ + #define RADIO_EVENTS_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTEPRESENT register. */ + +/* EVENTS_CTEPRESENT @Bit 0 : CTEInfo byte is received */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask + of EVENTS_CTEPRESENT field.*/ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTEPRESENT field. */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0x0UL) /*!< Event not generated */ + #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (0x1UL) /*!< Event generated */ + + +/* RADIO_PUBLISH_READY: Publish configuration for event READY */ + #define RADIO_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_TXREADY: Publish configuration for event TXREADY */ + #define RADIO_PUBLISH_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXREADY will publish to */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_TXREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_TXREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_TXREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RXREADY: Publish configuration for event RXREADY */ + #define RADIO_PUBLISH_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXREADY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXREADY will publish to */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RXREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RXREADY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RXREADY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_ADDRESS: Publish configuration for event ADDRESS */ + #define RADIO_PUBLISH_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ADDRESS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ADDRESS will publish to */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_ADDRESS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_ADDRESS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */ + #define RADIO_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_PAYLOAD: Publish configuration for event PAYLOAD */ + #define RADIO_PUBLISH_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PAYLOAD register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PAYLOAD will publish to */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PAYLOAD_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_END: Publish configuration for event END */ + #define RADIO_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_PHYEND: Publish configuration for event PHYEND */ + #define RADIO_PUBLISH_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PHYEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event PHYEND will publish to */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_PHYEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_PHYEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_PHYEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DISABLED: Publish configuration for event DISABLED */ + #define RADIO_PUBLISH_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DISABLED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DISABLED will publish to */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DISABLED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DISABLED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DISABLED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DEVMATCH: Publish configuration for event DEVMATCH */ + #define RADIO_PUBLISH_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DEVMATCH will publish to */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DEVMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_DEVMISS: Publish configuration for event DEVMISS */ + #define RADIO_PUBLISH_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMISS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DEVMISS will publish to */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_DEVMISS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_DEVMISS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CRCOK: Publish configuration for event CRCOK */ + #define RADIO_PUBLISH_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCOK register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CRCOK will publish to */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CRCOK_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCOK_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CRCOK_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CRCERROR: Publish configuration for event CRCERROR */ + #define RADIO_PUBLISH_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CRCERROR will publish to */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CRCERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CRCERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_BCMATCH: Publish configuration for event BCMATCH */ + #define RADIO_PUBLISH_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_BCMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BCMATCH will publish to */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_BCMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_BCMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_EDEND: Publish configuration for event EDEND */ + #define RADIO_PUBLISH_EDEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event EDEND will publish to */ + #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_EDEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_EDEND_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_EDEND_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_EDSTOPPED: Publish configuration for event EDSTOPPED */ + #define RADIO_PUBLISH_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDSTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event EDSTOPPED will publish to */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCAIDLE: Publish configuration for event CCAIDLE */ + #define RADIO_PUBLISH_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCAIDLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCAIDLE will publish to */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCAIDLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCABUSY: Publish configuration for event CCABUSY */ + #define RADIO_PUBLISH_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCABUSY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCABUSY will publish to */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCABUSY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCABUSY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CCASTOPPED: Publish configuration for event CCASTOPPED */ + #define RADIO_PUBLISH_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCASTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CCASTOPPED will publish to */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_RATEBOOST: Publish configuration for event RATEBOOST */ + #define RADIO_PUBLISH_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RATEBOOST register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RATEBOOST will publish to */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_RATEBOOST_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_MHRMATCH: Publish configuration for event MHRMATCH */ + #define RADIO_PUBLISH_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_MHRMATCH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MHRMATCH will publish to */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_MHRMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_SYNC: Publish configuration for event SYNC */ + #define RADIO_PUBLISH_SYNC_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SYNC register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SYNC will publish to */ + #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_SYNC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_SYNC_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_SYNC_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_PUBLISH_CTEPRESENT: Publish configuration for event CTEPRESENT */ + #define RADIO_PUBLISH_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTEPRESENT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CTEPRESENT will publish to */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RADIO_SHORTS: Shortcuts between local events and tasks */ + #define RADIO_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* READY_START @Bit 0 : Shortcut between event READY and task START */ + #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ + #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ + #define RADIO_SHORTS_READY_START_Min (0x0UL) /*!< Min enumerator value of READY_START field. */ + #define RADIO_SHORTS_READY_START_Max (0x1UL) /*!< Max enumerator value of READY_START field. */ + #define RADIO_SHORTS_READY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_READY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* END_DISABLE @Bit 1 : Shortcut between event END and task DISABLE */ + #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ + #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ + #define RADIO_SHORTS_END_DISABLE_Min (0x0UL) /*!< Min enumerator value of END_DISABLE field. */ + #define RADIO_SHORTS_END_DISABLE_Max (0x1UL) /*!< Max enumerator value of END_DISABLE field. */ + #define RADIO_SHORTS_END_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_END_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DISABLED_TXEN @Bit 2 : Shortcut between event DISABLED and task TXEN */ + #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Min (0x0UL) /*!< Min enumerator value of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Max (0x1UL) /*!< Max enumerator value of DISABLED_TXEN field. */ + #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_DISABLED_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DISABLED_RXEN @Bit 3 : Shortcut between event DISABLED and task RXEN */ + #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Min (0x0UL) /*!< Min enumerator value of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Max (0x1UL) /*!< Max enumerator value of DISABLED_RXEN field. */ + #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_DISABLED_RXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* ADDRESS_RSSISTART @Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART + field.*/ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_RSSISTART field. */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* END_START @Bit 5 : Shortcut between event END and task START */ + #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ + #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ + #define RADIO_SHORTS_END_START_Min (0x0UL) /*!< Min enumerator value of END_START field. */ + #define RADIO_SHORTS_END_START_Max (0x1UL) /*!< Max enumerator value of END_START field. */ + #define RADIO_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* ADDRESS_BCSTART @Bit 6 : Shortcut between event ADDRESS and task BCSTART */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_BCSTART field. */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */ + #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL) /*!< Position of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART + field.*/ + #define RADIO_SHORTS_RXREADY_CCASTART_Min (0x0UL) /*!< Min enumerator value of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Max (0x1UL) /*!< Max enumerator value of RXREADY_CCASTART field. */ + #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCAIDLE_TXEN @Bit 11 : Shortcut between event CCAIDLE and task TXEN */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (11UL) /*!< Position of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Min (0x0UL) /*!< Min enumerator value of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Max (0x1UL) /*!< Max enumerator value of CCAIDLE_TXEN field. */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCABUSY_DISABLE @Bit 12 : Shortcut between event CCABUSY and task DISABLE */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (12UL) /*!< Position of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Min (0x0UL) /*!< Min enumerator value of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Max (0x1UL) /*!< Max enumerator value of CCABUSY_DISABLE field. */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* FRAMESTART_BCSTART @Bit 13 : Shortcut between event FRAMESTART and task BCSTART */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (13UL) /*!< Position of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART + field.*/ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART_BCSTART field. */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READY_EDSTART @Bit 14 : Shortcut between event READY and task EDSTART */ + #define RADIO_SHORTS_READY_EDSTART_Pos (14UL) /*!< Position of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Min (0x0UL) /*!< Min enumerator value of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Max (0x1UL) /*!< Max enumerator value of READY_EDSTART field. */ + #define RADIO_SHORTS_READY_EDSTART_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_READY_EDSTART_Enabled (0x1UL) /*!< Enable shortcut */ + +/* EDEND_DISABLE @Bit 15 : Shortcut between event EDEND and task DISABLE */ + #define RADIO_SHORTS_EDEND_DISABLE_Pos (15UL) /*!< Position of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Min (0x0UL) /*!< Min enumerator value of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Max (0x1UL) /*!< Max enumerator value of EDEND_DISABLE field. */ + #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_EDEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* CCAIDLE_STOP @Bit 16 : Shortcut between event CCAIDLE and task STOP */ + #define RADIO_SHORTS_CCAIDLE_STOP_Pos (16UL) /*!< Position of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Min (0x0UL) /*!< Min enumerator value of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Max (0x1UL) /*!< Max enumerator value of CCAIDLE_STOP field. */ + #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* TXREADY_START @Bit 17 : Shortcut between event TXREADY and task START */ + #define RADIO_SHORTS_TXREADY_START_Pos (17UL) /*!< Position of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Min (0x0UL) /*!< Min enumerator value of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Max (0x1UL) /*!< Max enumerator value of TXREADY_START field. */ + #define RADIO_SHORTS_TXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_TXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* RXREADY_START @Bit 18 : Shortcut between event RXREADY and task START */ + #define RADIO_SHORTS_RXREADY_START_Pos (18UL) /*!< Position of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Min (0x0UL) /*!< Min enumerator value of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Max (0x1UL) /*!< Max enumerator value of RXREADY_START field. */ + #define RADIO_SHORTS_RXREADY_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_RXREADY_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PHYEND_DISABLE @Bit 19 : Shortcut between event PHYEND and task DISABLE */ + #define RADIO_SHORTS_PHYEND_DISABLE_Pos (19UL) /*!< Position of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Min (0x0UL) /*!< Min enumerator value of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Max (0x1UL) /*!< Max enumerator value of PHYEND_DISABLE field. */ + #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* PHYEND_START @Bit 20 : Shortcut between event PHYEND and task START */ + #define RADIO_SHORTS_PHYEND_START_Pos (20UL) /*!< Position of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Min (0x0UL) /*!< Min enumerator value of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Max (0x1UL) /*!< Max enumerator value of PHYEND_START field. */ + #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* RADIO_INTENSET00: Enable interrupt */ + #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define RADIO_INTENSET00_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENSET00_READY_Msk (0x1UL << RADIO_INTENSET00_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENSET00_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENSET00_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENSET00_READY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */ + #define RADIO_INTENSET00_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Msk (0x1UL << RADIO_INTENSET00_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENSET00_TXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */ + #define RADIO_INTENSET00_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Msk (0x1UL << RADIO_INTENSET00_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENSET00_RXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */ + #define RADIO_INTENSET00_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Msk (0x1UL << RADIO_INTENSET00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENSET00_ADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */ + #define RADIO_INTENSET00_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Msk (0x1UL << RADIO_INTENSET00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET00_FRAMESTART_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */ + #define RADIO_INTENSET00_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Msk (0x1UL << RADIO_INTENSET00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET00_PAYLOAD_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to enable interrupt for event END */ + #define RADIO_INTENSET00_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENSET00_END_Msk (0x1UL << RADIO_INTENSET00_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENSET00_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENSET00_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENSET00_END_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */ + #define RADIO_INTENSET00_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Msk (0x1UL << RADIO_INTENSET00_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENSET00_PHYEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */ + #define RADIO_INTENSET00_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Msk (0x1UL << RADIO_INTENSET00_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENSET00_DISABLED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */ + #define RADIO_INTENSET00_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Msk (0x1UL << RADIO_INTENSET00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET00_DEVMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */ + #define RADIO_INTENSET00_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Msk (0x1UL << RADIO_INTENSET00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENSET00_DEVMISS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */ + #define RADIO_INTENSET00_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Msk (0x1UL << RADIO_INTENSET00_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENSET00_CRCOK_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */ + #define RADIO_INTENSET00_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Msk (0x1UL << RADIO_INTENSET00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENSET00_CRCERROR_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */ + #define RADIO_INTENSET00_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Msk (0x1UL << RADIO_INTENSET00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENSET00_BCMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */ + #define RADIO_INTENSET00_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Msk (0x1UL << RADIO_INTENSET00_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENSET00_EDEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ + #define RADIO_INTENSET00_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET00_EDSTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ + #define RADIO_INTENSET00_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Msk (0x1UL << RADIO_INTENSET00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET00_CCAIDLE_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */ + #define RADIO_INTENSET00_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Msk (0x1UL << RADIO_INTENSET00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENSET00_CCABUSY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ + #define RADIO_INTENSET00_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET00_CCASTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ + #define RADIO_INTENSET00_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Msk (0x1UL << RADIO_INTENSET00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET00_RATEBOOST_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */ + #define RADIO_INTENSET00_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Msk (0x1UL << RADIO_INTENSET00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET00_MHRMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */ + #define RADIO_INTENSET00_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Msk (0x1UL << RADIO_INTENSET00_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENSET00_SYNC_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */ + #define RADIO_INTENSET00_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET00_CTEPRESENT_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR00: Disable interrupt */ + #define RADIO_INTENCLR00_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR00 register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define RADIO_INTENCLR00_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENCLR00_READY_Msk (0x1UL << RADIO_INTENCLR00_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENCLR00_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENCLR00_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENCLR00_READY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */ + #define RADIO_INTENCLR00_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Msk (0x1UL << RADIO_INTENCLR00_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENCLR00_TXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */ + #define RADIO_INTENCLR00_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Msk (0x1UL << RADIO_INTENCLR00_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENCLR00_RXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */ + #define RADIO_INTENCLR00_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Msk (0x1UL << RADIO_INTENCLR00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR00_ADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */ + #define RADIO_INTENCLR00_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR00_FRAMESTART_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */ + #define RADIO_INTENCLR00_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR00_PAYLOAD_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to disable interrupt for event END */ + #define RADIO_INTENCLR00_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENCLR00_END_Msk (0x1UL << RADIO_INTENCLR00_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENCLR00_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENCLR00_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENCLR00_END_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */ + #define RADIO_INTENCLR00_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Msk (0x1UL << RADIO_INTENCLR00_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENCLR00_PHYEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */ + #define RADIO_INTENCLR00_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Msk (0x1UL << RADIO_INTENCLR00_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENCLR00_DISABLED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */ + #define RADIO_INTENCLR00_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR00_DEVMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */ + #define RADIO_INTENCLR00_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Msk (0x1UL << RADIO_INTENCLR00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR00_DEVMISS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */ + #define RADIO_INTENCLR00_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Msk (0x1UL << RADIO_INTENCLR00_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENCLR00_CRCOK_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */ + #define RADIO_INTENCLR00_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Msk (0x1UL << RADIO_INTENCLR00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR00_CRCERROR_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */ + #define RADIO_INTENCLR00_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Msk (0x1UL << RADIO_INTENCLR00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR00_BCMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */ + #define RADIO_INTENCLR00_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Msk (0x1UL << RADIO_INTENCLR00_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENCLR00_EDEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ + #define RADIO_INTENCLR00_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR00_EDSTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ + #define RADIO_INTENCLR00_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR00_CCAIDLE_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */ + #define RADIO_INTENCLR00_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Msk (0x1UL << RADIO_INTENCLR00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR00_CCABUSY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ + #define RADIO_INTENCLR00_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR00_CCASTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ + #define RADIO_INTENCLR00_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR00_RATEBOOST_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */ + #define RADIO_INTENCLR00_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR00_MHRMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */ + #define RADIO_INTENCLR00_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Msk (0x1UL << RADIO_INTENCLR00_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENCLR00_SYNC_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */ + #define RADIO_INTENCLR00_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR00_CTEPRESENT_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENSET10: Enable interrupt */ + #define RADIO_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register. */ + +/* READY @Bit 0 : Write '1' to enable interrupt for event READY */ + #define RADIO_INTENSET10_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENSET10_READY_Msk (0x1UL << RADIO_INTENSET10_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENSET10_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENSET10_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENSET10_READY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */ + #define RADIO_INTENSET10_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Msk (0x1UL << RADIO_INTENSET10_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENSET10_TXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */ + #define RADIO_INTENSET10_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Msk (0x1UL << RADIO_INTENSET10_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENSET10_RXREADY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */ + #define RADIO_INTENSET10_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Msk (0x1UL << RADIO_INTENSET10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENSET10_ADDRESS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */ + #define RADIO_INTENSET10_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Msk (0x1UL << RADIO_INTENSET10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENSET10_FRAMESTART_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */ + #define RADIO_INTENSET10_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Msk (0x1UL << RADIO_INTENSET10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENSET10_PAYLOAD_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to enable interrupt for event END */ + #define RADIO_INTENSET10_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENSET10_END_Msk (0x1UL << RADIO_INTENSET10_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENSET10_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENSET10_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENSET10_END_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */ + #define RADIO_INTENSET10_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Msk (0x1UL << RADIO_INTENSET10_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENSET10_PHYEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */ + #define RADIO_INTENSET10_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Msk (0x1UL << RADIO_INTENSET10_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENSET10_DISABLED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */ + #define RADIO_INTENSET10_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Msk (0x1UL << RADIO_INTENSET10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENSET10_DEVMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */ + #define RADIO_INTENSET10_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Msk (0x1UL << RADIO_INTENSET10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENSET10_DEVMISS_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */ + #define RADIO_INTENSET10_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Msk (0x1UL << RADIO_INTENSET10_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENSET10_CRCOK_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */ + #define RADIO_INTENSET10_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Msk (0x1UL << RADIO_INTENSET10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENSET10_CRCERROR_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */ + #define RADIO_INTENSET10_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Msk (0x1UL << RADIO_INTENSET10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENSET10_BCMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */ + #define RADIO_INTENSET10_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Msk (0x1UL << RADIO_INTENSET10_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENSET10_EDEND_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ + #define RADIO_INTENSET10_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENSET10_EDSTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ + #define RADIO_INTENSET10_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Msk (0x1UL << RADIO_INTENSET10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENSET10_CCAIDLE_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */ + #define RADIO_INTENSET10_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Msk (0x1UL << RADIO_INTENSET10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENSET10_CCABUSY_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ + #define RADIO_INTENSET10_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENSET10_CCASTOPPED_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ + #define RADIO_INTENSET10_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Msk (0x1UL << RADIO_INTENSET10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENSET10_RATEBOOST_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */ + #define RADIO_INTENSET10_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Msk (0x1UL << RADIO_INTENSET10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENSET10_MHRMATCH_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */ + #define RADIO_INTENSET10_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Msk (0x1UL << RADIO_INTENSET10_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENSET10_SYNC_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */ + #define RADIO_INTENSET10_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENSET10_CTEPRESENT_Set (0x1UL) /*!< Enable */ + #define RADIO_INTENSET10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENSET10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_INTENCLR10: Disable interrupt */ + #define RADIO_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register. */ + +/* READY @Bit 0 : Write '1' to disable interrupt for event READY */ + #define RADIO_INTENCLR10_READY_Pos (0UL) /*!< Position of READY field. */ + #define RADIO_INTENCLR10_READY_Msk (0x1UL << RADIO_INTENCLR10_READY_Pos) /*!< Bit mask of READY field. */ + #define RADIO_INTENCLR10_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define RADIO_INTENCLR10_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define RADIO_INTENCLR10_READY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_READY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_READY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */ + #define RADIO_INTENCLR10_TXREADY_Pos (1UL) /*!< Position of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Msk (0x1UL << RADIO_INTENCLR10_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Min (0x0UL) /*!< Min enumerator value of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Max (0x1UL) /*!< Max enumerator value of TXREADY field. */ + #define RADIO_INTENCLR10_TXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_TXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_TXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */ + #define RADIO_INTENCLR10_RXREADY_Pos (2UL) /*!< Position of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Msk (0x1UL << RADIO_INTENCLR10_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Min (0x0UL) /*!< Min enumerator value of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Max (0x1UL) /*!< Max enumerator value of RXREADY field. */ + #define RADIO_INTENCLR10_RXREADY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_RXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_RXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */ + #define RADIO_INTENCLR10_ADDRESS_Pos (3UL) /*!< Position of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Msk (0x1UL << RADIO_INTENCLR10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Min (0x0UL) /*!< Min enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Max (0x1UL) /*!< Max enumerator value of ADDRESS field. */ + #define RADIO_INTENCLR10_ADDRESS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_ADDRESS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_ADDRESS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */ + #define RADIO_INTENCLR10_FRAMESTART_Pos (4UL) /*!< Position of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART field. */ + #define RADIO_INTENCLR10_FRAMESTART_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */ + #define RADIO_INTENCLR10_PAYLOAD_Pos (5UL) /*!< Position of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of PAYLOAD field. */ + #define RADIO_INTENCLR10_PAYLOAD_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_PAYLOAD_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_PAYLOAD_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 6 : Write '1' to disable interrupt for event END */ + #define RADIO_INTENCLR10_END_Pos (6UL) /*!< Position of END field. */ + #define RADIO_INTENCLR10_END_Msk (0x1UL << RADIO_INTENCLR10_END_Pos) /*!< Bit mask of END field. */ + #define RADIO_INTENCLR10_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define RADIO_INTENCLR10_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define RADIO_INTENCLR10_END_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */ + #define RADIO_INTENCLR10_PHYEND_Pos (7UL) /*!< Position of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Msk (0x1UL << RADIO_INTENCLR10_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Min (0x0UL) /*!< Min enumerator value of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Max (0x1UL) /*!< Max enumerator value of PHYEND field. */ + #define RADIO_INTENCLR10_PHYEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_PHYEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_PHYEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */ + #define RADIO_INTENCLR10_DISABLED_Pos (8UL) /*!< Position of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Msk (0x1UL << RADIO_INTENCLR10_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Min (0x0UL) /*!< Min enumerator value of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Max (0x1UL) /*!< Max enumerator value of DISABLED field. */ + #define RADIO_INTENCLR10_DISABLED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DISABLED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */ + #define RADIO_INTENCLR10_DEVMATCH_Pos (9UL) /*!< Position of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of DEVMATCH field. */ + #define RADIO_INTENCLR10_DEVMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DEVMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */ + #define RADIO_INTENCLR10_DEVMISS_Pos (10UL) /*!< Position of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Msk (0x1UL << RADIO_INTENCLR10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Min (0x0UL) /*!< Min enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Max (0x1UL) /*!< Max enumerator value of DEVMISS field. */ + #define RADIO_INTENCLR10_DEVMISS_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_DEVMISS_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_DEVMISS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */ + #define RADIO_INTENCLR10_CRCOK_Pos (11UL) /*!< Position of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Msk (0x1UL << RADIO_INTENCLR10_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Min (0x0UL) /*!< Min enumerator value of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Max (0x1UL) /*!< Max enumerator value of CRCOK field. */ + #define RADIO_INTENCLR10_CRCOK_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CRCOK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CRCOK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */ + #define RADIO_INTENCLR10_CRCERROR_Pos (12UL) /*!< Position of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Msk (0x1UL << RADIO_INTENCLR10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Min (0x0UL) /*!< Min enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Max (0x1UL) /*!< Max enumerator value of CRCERROR field. */ + #define RADIO_INTENCLR10_CRCERROR_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CRCERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */ + #define RADIO_INTENCLR10_BCMATCH_Pos (14UL) /*!< Position of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Msk (0x1UL << RADIO_INTENCLR10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Min (0x0UL) /*!< Min enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Max (0x1UL) /*!< Max enumerator value of BCMATCH field. */ + #define RADIO_INTENCLR10_BCMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_BCMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_BCMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */ + #define RADIO_INTENCLR10_EDEND_Pos (15UL) /*!< Position of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Msk (0x1UL << RADIO_INTENCLR10_EDEND_Pos) /*!< Bit mask of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Min (0x0UL) /*!< Min enumerator value of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Max (0x1UL) /*!< Max enumerator value of EDEND field. */ + #define RADIO_INTENCLR10_EDEND_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_EDEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_EDEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ + #define RADIO_INTENCLR10_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EDSTOPPED field. */ + #define RADIO_INTENCLR10_EDSTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ + #define RADIO_INTENCLR10_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of CCAIDLE field. */ + #define RADIO_INTENCLR10_CCAIDLE_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCAIDLE_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCAIDLE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */ + #define RADIO_INTENCLR10_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Msk (0x1UL << RADIO_INTENCLR10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Min (0x0UL) /*!< Min enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Max (0x1UL) /*!< Max enumerator value of CCABUSY field. */ + #define RADIO_INTENCLR10_CCABUSY_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCABUSY_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCABUSY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ + #define RADIO_INTENCLR10_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of CCASTOPPED field. */ + #define RADIO_INTENCLR10_CCASTOPPED_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ + #define RADIO_INTENCLR10_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of RATEBOOST field. */ + #define RADIO_INTENCLR10_RATEBOOST_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled */ + +/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */ + #define RADIO_INTENCLR10_MHRMATCH_Pos (21UL) /*!< Position of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of MHRMATCH field. */ + #define RADIO_INTENCLR10_MHRMATCH_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_MHRMATCH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */ + #define RADIO_INTENCLR10_SYNC_Pos (22UL) /*!< Position of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Msk (0x1UL << RADIO_INTENCLR10_SYNC_Pos) /*!< Bit mask of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Min (0x0UL) /*!< Min enumerator value of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Max (0x1UL) /*!< Max enumerator value of SYNC field. */ + #define RADIO_INTENCLR10_SYNC_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_SYNC_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_SYNC_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */ + #define RADIO_INTENCLR10_CTEPRESENT_Pos (23UL) /*!< Position of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of CTEPRESENT field. */ + #define RADIO_INTENCLR10_CTEPRESENT_Clear (0x1UL) /*!< Disable */ + #define RADIO_INTENCLR10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled */ + #define RADIO_INTENCLR10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RADIO_MODE: Data rate and modulation */ + #define RADIO_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..3 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ + #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define RADIO_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define RADIO_MODE_MODE_Max (0xFUL) /*!< Max enumerator value of MODE field. */ + #define RADIO_MODE_MODE_Nrf_1Mbit (0x0UL) /*!< 1 Mbps Nordic proprietary radio mode */ + #define RADIO_MODE_MODE_Nrf_2Mbit (0x1UL) /*!< 2 Mbps Nordic proprietary radio mode */ + #define RADIO_MODE_MODE_Ble_1Mbit (0x3UL) /*!< 1 Mbps BLE */ + #define RADIO_MODE_MODE_Ble_2Mbit (0x4UL) /*!< 2 Mbps BLE */ + #define RADIO_MODE_MODE_Ble_LR125Kbit (0x5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */ + #define RADIO_MODE_MODE_Ble_LR500Kbit (0x6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */ + #define RADIO_MODE_MODE_Nrf_4Mbit0_5 (0x9UL) /*!< 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.5) */ + #define RADIO_MODE_MODE_Nrf_4Mbit0_25 (0xAUL) /*!< 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.25) */ + #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbps */ + + +/* RADIO_STATE: Current radio state */ + #define RADIO_STATE_ResetValue (0x00000000UL) /*!< Reset value of STATE register. */ + +/* STATE @Bits 0..3 : Current radio state */ + #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ + #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ + #define RADIO_STATE_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define RADIO_STATE_STATE_Max (0xCUL) /*!< Max enumerator value of STATE field. */ + #define RADIO_STATE_STATE_Disabled (0x0UL) /*!< RADIO is in the Disabled state */ + #define RADIO_STATE_STATE_RxRu (0x1UL) /*!< RADIO is in the RXRU state */ + #define RADIO_STATE_STATE_RxIdle (0x2UL) /*!< RADIO is in the RXIDLE state */ + #define RADIO_STATE_STATE_Rx (0x3UL) /*!< RADIO is in the RX state */ + #define RADIO_STATE_STATE_RxDisable (0x4UL) /*!< RADIO is in the RXDISABLED state */ + #define RADIO_STATE_STATE_TxRu (0x9UL) /*!< RADIO is in the TXRU state */ + #define RADIO_STATE_STATE_TxIdle (0xAUL) /*!< RADIO is in the TXIDLE state */ + #define RADIO_STATE_STATE_Tx (0xBUL) /*!< RADIO is in the TX state */ + #define RADIO_STATE_STATE_TxDisable (0xCUL) /*!< RADIO is in the TXDISABLED state */ + + +/* RADIO_EDCTRL: IEEE 802.15.4 energy detect control */ + #define RADIO_EDCTRL_ResetValue (0x20000000UL) /*!< Reset value of EDCTRL register. */ + +/* EDCNT @Bits 0..20 : IEEE 802.15.4 energy detect loop count */ + #define RADIO_EDCTRL_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ + #define RADIO_EDCTRL_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCTRL_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* EDPERIOD @Bits 24..29 : IEEE 802.15.4 energy detect/cca period, 4us resolution */ + #define RADIO_EDCTRL_EDPERIOD_Pos (24UL) /*!< Position of EDPERIOD field. */ + #define RADIO_EDCTRL_EDPERIOD_Msk (0x3FUL << RADIO_EDCTRL_EDPERIOD_Pos) /*!< Bit mask of EDPERIOD field. */ + + +/* RADIO_EDSAMPLE: IEEE 802.15.4 energy detect level */ + #define RADIO_EDSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of EDSAMPLE register. */ + +/* EDLVL @Bits 0..7 : IEEE 802.15.4 energy detect level */ + #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Min (0x00UL) /*!< Min value of EDLVL field. */ + #define RADIO_EDSAMPLE_EDLVL_Max (0x7FUL) /*!< Max size of EDLVL field. */ + + +/* RADIO_CCACTRL: IEEE 802.15.4 clear channel assessment control */ + #define RADIO_CCACTRL_ResetValue (0x052D0000UL) /*!< Reset value of CCACTRL register. */ + +/* CCAMODE @Bits 0..2 : CCA mode of operation */ + #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Min (0x0UL) /*!< Min enumerator value of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_Max (0x4UL) /*!< Max enumerator value of CCAMODE field. */ + #define RADIO_CCACTRL_CCAMODE_EdMode (0x0UL) /*!< Energy above threshold */ + #define RADIO_CCACTRL_CCAMODE_CarrierMode (0x1UL) /*!< Carrier seen */ + #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (0x2UL) /*!< Energy above threshold AND carrier seen */ + #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (0x3UL) /*!< Energy above threshold OR carrier seen */ + #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (0x4UL) /*!< Energy above threshold test mode that will abort when first ED + measurement over threshold is seen. No averaging.*/ + +/* CCAEDTHRES @Bits 8..15 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ + #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ + #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* CCACORRTHRES @Bits 16..23 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and + CarrierOrEdMode. */ + + #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ + #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* CCACORRCNT @Bits 24..31 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect + is enabled. */ + + #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ + #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + + +/* RADIO_DATAWHITEIV: Data whitening initial value */ + #define RADIO_DATAWHITEIV_ResetValue (0x00000040UL) /*!< Reset value of DATAWHITEIV register. */ + +/* DATAWHITEIV @Bits 0..5 : (unspecified) */ + #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ + #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + + +/* RADIO_TIMING: Timing */ + #define RADIO_TIMING_ResetValue (0x00000000UL) /*!< Reset value of TIMING register. */ + +/* RU @Bit 0 : 0: Default ramp-up time, compatible with 180nm radio. 1: Fast ramp-up. */ + #define RADIO_TIMING_RU_Pos (0UL) /*!< Position of RU field. */ + #define RADIO_TIMING_RU_Msk (0x1UL << RADIO_TIMING_RU_Pos) /*!< Bit mask of RU field. */ + + +/* RADIO_FREQUENCY: Frequency */ + #define RADIO_FREQUENCY_ResetValue (0x00000002UL) /*!< Reset value of FREQUENCY register. */ + +/* FREQUENCY @Bits 0..6 : Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). */ + #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ + #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* MAP @Bit 8 : Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1: + Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). */ + + #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ + #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ + + +/* RADIO_TXPOWER: Output power */ + #define RADIO_TXPOWER_ResetValue (0x00000000UL) /*!< Reset value of TXPOWER register. */ + +/* TXPOWER @Bits 0..7 : RADIO output power */ + #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Min (0x0UL) /*!< Min enumerator value of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Max (0xFFUL) /*!< Max enumerator value of TXPOWER field. */ + #define RADIO_TXPOWER_TXPOWER_Pos10dBm (0x0AUL) /*!< +10 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x09UL) /*!< +9 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x08UL) /*!< +8 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x07UL) /*!< +7 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x06UL) /*!< +6 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x05UL) /*!< +5 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x02UL) /*!< +2 dBm */ + #define RADIO_TXPOWER_TXPOWER_Pos1dBm (0x01UL) /*!< +1 dBm */ + #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL) /*!< -1 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL) /*!< -2 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< -30 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ + #define RADIO_TXPOWER_TXPOWER_Neg70dBm (0xBAUL) /*!< -70 dBm */ + + +/* RADIO_TIFS: Interframe spacing in us */ + #define RADIO_TIFS_ResetValue (0x00000000UL) /*!< Reset value of TIFS register. */ + +/* TIFS @Bits 0..9 : Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is + defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of + the first bit of the subsequent packet. */ + + #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ + #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + + +/* RADIO_RSSISAMPLE: RSSI sample */ + #define RADIO_RSSISAMPLE_ResetValue (0x0000007FUL) /*!< Reset value of RSSISAMPLE register. */ + +/* RSSISAMPLE @Bits 0..6 : RSSI sample result. The value of this register is read as a positive value while the actual received + signal strength is a negative value. Actual received signal strength is therefore as follows: + received signal strength = -A dBm. */ + + #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ + #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + + +/* RADIO_DFEMODE: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ + #define RADIO_DFEMODE_ResetValue (0x00000000UL) /*!< Reset value of DFEMODE register. */ + +/* DFEOPMODE @Bits 0..1 : Direction finding operation mode */ + #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Min (0x0UL) /*!< Min enumerator value of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Max (0x3UL) /*!< Max enumerator value of DFEOPMODE field. */ + #define RADIO_DFEMODE_DFEOPMODE_Disabled (0x0UL) /*!< Direction finding mode disabled */ + #define RADIO_DFEMODE_DFEOPMODE_AoD (0x2UL) /*!< Direction finding mode set to AoD */ + #define RADIO_DFEMODE_DFEOPMODE_AoA (0x3UL) /*!< Direction finding mode set to AoA */ + + +/* RADIO_DFESTATUS: DFE status information */ + #define RADIO_DFESTATUS_ResetValue (0x00000000UL) /*!< Reset value of DFESTATUS register. */ + +/* SWITCHINGSTATE @Bits 0..2 : Internal state of switching state machine */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE + field.*/ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Min (0x0UL) /*!< Min enumerator value of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Max (0x5UL) /*!< Max enumerator value of SWITCHINGSTATE field. */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0x0UL) /*!< Switching state Idle */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (0x1UL) /*!< Switching state Offset */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (0x2UL) /*!< Switching state Guard */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (0x3UL) /*!< Switching state Ref */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (0x4UL) /*!< Switching state Switching */ + #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (0x5UL) /*!< Switching state Ending */ + +/* SAMPLINGSTATE @Bit 4 : Internal state of sampling state machine */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Min (0x0UL) /*!< Min enumerator value of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Max (0x1UL) /*!< Max enumerator value of SAMPLINGSTATE field. */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0x0UL) /*!< Sampling state Idle */ + #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (0x1UL) /*!< Sampling state Sampling */ + + +/* RADIO_DFECTRL1: Various configuration for Direction finding */ + #define RADIO_DFECTRL1_ResetValue (0x00023282UL) /*!< Reset value of DFECTRL1 register. */ + +/* NUMBEROF8US @Bits 0..5 : Length of the AoA/AoD procedure in number of 8 us units */ + #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ + #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ + +/* DFEINEXTENSION @Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field.*/ + #define RADIO_DFECTRL1_DFEINEXTENSION_Min (0x0UL) /*!< Min enumerator value of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Max (0x1UL) /*!< Max enumerator value of DFEINEXTENSION field. */ + #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (0x1UL) /*!< AoA/AoD procedure triggered at end of CRC */ + #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0x0UL) /*!< Antenna switching/sampling is done in the packet payload */ + +/* TSWITCHSPACING @Bits 8..10 : Interval between every time the antenna is changed in the SWITCHING state */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field.*/ + #define RADIO_DFECTRL1_TSWITCHSPACING_Min (0x1UL) /*!< Min enumerator value of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_Max (0x3UL) /*!< Max enumerator value of TSWITCHSPACING field. */ + #define RADIO_DFECTRL1_TSWITCHSPACING_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSWITCHSPACING_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSWITCHSPACING_1us (0x3UL) /*!< 1us */ + +/* TSAMPLESPACINGREF @Bits 12..14 : Interval between samples in the REFERENCE period */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of + TSAMPLESPACINGREF field.*/ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACINGREF field. */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (0x3UL) /*!< 1us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (0x6UL) /*!< 0.125us */ + +/* SAMPLETYPE @Bit 15 : Whether to sample I/Q or magnitude/phase */ + #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Min (0x0UL) /*!< Min enumerator value of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_Max (0x1UL) /*!< Max enumerator value of SAMPLETYPE field. */ + #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0x0UL) /*!< Complex samples in I and Q */ + #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (0x1UL) /*!< Complex samples as magnitude and phase */ + +/* TSAMPLESPACING @Bits 16..18 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field.*/ + #define RADIO_DFECTRL1_TSAMPLESPACING_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACING field. */ + #define RADIO_DFECTRL1_TSAMPLESPACING_4us (0x1UL) /*!< 4us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_2us (0x2UL) /*!< 2us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_1us (0x3UL) /*!< 1us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (0x6UL) /*!< 0.125us */ + +/* REPEATPATTERN @Bits 20..23 : Repeat every antenna pattern N times. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Min (0x0UL) /*!< Min enumerator value of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_Max (0x0UL) /*!< Max enumerator value of REPEATPATTERN field. */ + #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0x0UL) /*!< Do not repeat (1 time in total) */ + +/* AGCBACKOFFGAIN @Bits 24..27 : Gain will be lowered by the specified number of gain steps at the start of CTE */ + #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ + #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field.*/ + + +/* RADIO_DFECTRL2: Start offset for Direction finding */ + #define RADIO_DFECTRL2_ResetValue (0x00000000UL) /*!< Reset value of DFECTRL2 register. */ + +/* TSWITCHOFFSET @Bits 0..12 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ + #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ + #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field.*/ + +/* TSAMPLEOFFSET @Bits 16..27 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning + of the REFERENCE state - 12 us after switching start */ + + #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ + #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ + + +/* RADIO_SWITCHPATTERN: GPIO patterns to be used for each antenna */ + #define RADIO_SWITCHPATTERN_ResetValue (0x00000000UL) /*!< Reset value of SWITCHPATTERN register. */ + +/* SWITCHPATTERN @Bits 0..7 : Fill array of GPIO patterns for antenna control */ + #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ + #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN + field.*/ + + +/* RADIO_CLEARPATTERN: Clear the GPIO pattern array for antenna control */ + #define RADIO_CLEARPATTERN_ResetValue (0x00000000UL) /*!< Reset value of CLEARPATTERN register. */ + +/* CLEARPATTERN @Bit 0 : Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor + IRQ */ + + #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ + #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN + field.*/ + + +/* RADIO_CRCSTATUS: CRC status */ + #define RADIO_CRCSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CRCSTATUS register. */ + +/* CRCSTATUS @Bit 0 : CRC status of packet received */ + #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Min (0x0UL) /*!< Min enumerator value of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_Max (0x1UL) /*!< Max enumerator value of CRCSTATUS field. */ + #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0x0UL) /*!< Packet received with CRC error */ + #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (0x1UL) /*!< Packet received with CRC ok */ + + +/* RADIO_RXMATCH: Received address */ + #define RADIO_RXMATCH_ResetValue (0x00000000UL) /*!< Reset value of RXMATCH register. */ + +/* RXMATCH @Bits 0..2 : Received address */ + #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ + #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + + +/* RADIO_RXCRC: CRC field of previously received packet */ + #define RADIO_RXCRC_ResetValue (0x00000000UL) /*!< Reset value of RXCRC register. */ + +/* RXCRC @Bits 0..23 : CRC field of previously received packet */ + #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ + #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + + +/* RADIO_DAI: Device address match index */ + #define RADIO_DAI_ResetValue (0x00000000UL) /*!< Reset value of DAI register. */ + +/* DAI @Bits 0..2 : Device address match index */ + #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ + #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + + +/* RADIO_PDUSTAT: Payload status */ + #define RADIO_PDUSTAT_ResetValue (0x00000000UL) /*!< Reset value of PDUSTAT register. */ + +/* PDUSTAT @Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ + #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Min (0x0UL) /*!< Min enumerator value of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_Max (0x1UL) /*!< Max enumerator value of PDUSTAT field. */ + #define RADIO_PDUSTAT_PDUSTAT_LessThan (0x0UL) /*!< Payload less than PCNF1.MAXLEN */ + #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (0x1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* CISTAT @Bits 1..2 : Status on what rate packet is received with in Long Range */ + #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Min (0x0UL) /*!< Min enumerator value of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_Max (0x1UL) /*!< Max enumerator value of CISTAT field. */ + #define RADIO_PDUSTAT_CISTAT_LR125kbit (0x0UL) /*!< Frame is received at 125 kbps */ + #define RADIO_PDUSTAT_CISTAT_LR500kbit (0x1UL) /*!< Frame is received at 500 kbps */ + + +/* RADIO_PCNF0: Packet configuration register 0 */ + #define RADIO_PCNF0_ResetValue (0x00000000UL) /*!< Reset value of PCNF0 register. */ + +/* LFLEN @Bits 0..3 : Length on air of LENGTH field in number of bits. */ + #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ + #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* S0LEN @Bit 8 : Length on air of S0 field in number of bytes. */ + #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ + #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* S1LEN @Bits 16..19 : Length on air of S1 field in number of bits. */ + #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ + #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* S1INCL @Bits 20..21 : Include or exclude S1 field in RAM */ + #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Msk (0x3UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Min (0x0UL) /*!< Min enumerator value of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Max (0x1UL) /*!< Max enumerator value of S1INCL field. */ + #define RADIO_PCNF0_S1INCL_Automatic (0x0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ + #define RADIO_PCNF0_S1INCL_Include (0x1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* CILEN @Bits 22..23 : Length of code indicator - long range */ + #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ + #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* PLEN @Bits 24..25 : Length of preamble on air. Decision point: TASKS_START task */ + #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ + #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ + #define RADIO_PCNF0_PLEN_Min (0x0UL) /*!< Min enumerator value of PLEN field. */ + #define RADIO_PCNF0_PLEN_Max (0x3UL) /*!< Max enumerator value of PLEN field. */ + #define RADIO_PCNF0_PLEN_8bit (0x0UL) /*!< 8-bit preamble */ + #define RADIO_PCNF0_PLEN_16bit (0x1UL) /*!< 16-bit preamble */ + #define RADIO_PCNF0_PLEN_32bitZero (0x2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ + #define RADIO_PCNF0_PLEN_LongRange (0x3UL) /*!< Preamble - used for BLE long range */ + +/* CRCINC @Bit 26 : Indicates if LENGTH field contains CRC or not */ + #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Min (0x0UL) /*!< Min enumerator value of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Max (0x1UL) /*!< Max enumerator value of CRCINC field. */ + #define RADIO_PCNF0_CRCINC_Exclude (0x0UL) /*!< LENGTH does not contain CRC */ + #define RADIO_PCNF0_CRCINC_Include (0x1UL) /*!< LENGTH includes CRC */ + +/* TERMLEN @Bits 29..30 : Length of TERM field in Long Range operation */ + #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ + #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + + +/* RADIO_PCNF1: Packet configuration register 1 */ + #define RADIO_PCNF1_ResetValue (0x00000000UL) /*!< Reset value of PCNF1 register. */ + +/* MAXLEN @Bits 0..7 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate + the payload to MAXLEN. */ + + #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Min (0x00UL) /*!< Min value of MAXLEN field. */ + #define RADIO_PCNF1_MAXLEN_Max (0xFFUL) /*!< Max size of MAXLEN field. */ + +/* STATLEN @Bits 8..15 : Static length in number of bytes */ + #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Min (0x00UL) /*!< Min value of STATLEN field. */ + #define RADIO_PCNF1_STATLEN_Max (0xFFUL) /*!< Max size of STATLEN field. */ + +/* BALEN @Bits 16..18 : Base address length in number of bytes */ + #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ + #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + #define RADIO_PCNF1_BALEN_Min (0x1UL) /*!< Min value of BALEN field. */ + #define RADIO_PCNF1_BALEN_Max (0x1UL) /*!< Max size of BALEN field. */ + +/* ENDIAN @Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ + #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Min (0x0UL) /*!< Min enumerator value of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Max (0x1UL) /*!< Max enumerator value of ENDIAN field. */ + #define RADIO_PCNF1_ENDIAN_Little (0x0UL) /*!< Least significant bit on air first */ + #define RADIO_PCNF1_ENDIAN_Big (0x1UL) /*!< Most significant bit on air first */ + +/* WHITEEN @Bit 25 : Enable or disable packet whitening */ + #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Min (0x0UL) /*!< Min enumerator value of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Max (0x1UL) /*!< Max enumerator value of WHITEEN field. */ + #define RADIO_PCNF1_WHITEEN_Disabled (0x0UL) /*!< Disable */ + #define RADIO_PCNF1_WHITEEN_Enabled (0x1UL) /*!< Enable */ + + +/* RADIO_BASE0: Base address 0 */ + #define RADIO_BASE0_ResetValue (0x00000000UL) /*!< Reset value of BASE0 register. */ + +/* BASE0 @Bits 0..31 : Base address 0 */ + #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ + #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + + +/* RADIO_BASE1: Base address 1 */ + #define RADIO_BASE1_ResetValue (0x00000000UL) /*!< Reset value of BASE1 register. */ + +/* BASE1 @Bits 0..31 : Base address 1 */ + #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ + #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + + +/* RADIO_PREFIX0: Prefixes bytes for logical addresses 0-3 */ + #define RADIO_PREFIX0_ResetValue (0x00000000UL) /*!< Reset value of PREFIX0 register. */ + +/* AP0 @Bits 0..7 : Address prefix 0 */ + #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ + #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* AP1 @Bits 8..15 : Address prefix 1 */ + #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ + #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* AP2 @Bits 16..23 : Address prefix 2 */ + #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ + #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* AP3 @Bits 24..31 : Address prefix 3 */ + #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ + #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + + +/* RADIO_PREFIX1: Prefixes bytes for logical addresses 4-7 */ + #define RADIO_PREFIX1_ResetValue (0x00000000UL) /*!< Reset value of PREFIX1 register. */ + +/* AP4 @Bits 0..7 : Address prefix 4 */ + #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ + #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* AP5 @Bits 8..15 : Address prefix 5 */ + #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ + #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* AP6 @Bits 16..23 : Address prefix 6 */ + #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ + #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* AP7 @Bits 24..31 : Address prefix 7 */ + #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ + #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + + +/* RADIO_TXADDRESS: Transmit address select */ + #define RADIO_TXADDRESS_ResetValue (0x00000000UL) /*!< Reset value of TXADDRESS register. */ + +/* TXADDRESS @Bits 0..2 : Transmit address select */ + #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ + #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + + +/* RADIO_RXADDRESSES: Receive address select */ + #define RADIO_RXADDRESSES_ResetValue (0x00000000UL) /*!< Reset value of RXADDRESSES register. */ + +/* ADDR0 @Bit 0 : Enable or disable reception on logical address 0 */ + #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Min (0x0UL) /*!< Min enumerator value of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Max (0x1UL) /*!< Max enumerator value of ADDR0 field. */ + #define RADIO_RXADDRESSES_ADDR0_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR0_Enabled (0x1UL) /*!< Enable */ + +/* ADDR1 @Bit 1 : Enable or disable reception on logical address 1 */ + #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Min (0x0UL) /*!< Min enumerator value of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Max (0x1UL) /*!< Max enumerator value of ADDR1 field. */ + #define RADIO_RXADDRESSES_ADDR1_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR1_Enabled (0x1UL) /*!< Enable */ + +/* ADDR2 @Bit 2 : Enable or disable reception on logical address 2 */ + #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Min (0x0UL) /*!< Min enumerator value of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Max (0x1UL) /*!< Max enumerator value of ADDR2 field. */ + #define RADIO_RXADDRESSES_ADDR2_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR2_Enabled (0x1UL) /*!< Enable */ + +/* ADDR3 @Bit 3 : Enable or disable reception on logical address 3 */ + #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Min (0x0UL) /*!< Min enumerator value of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Max (0x1UL) /*!< Max enumerator value of ADDR3 field. */ + #define RADIO_RXADDRESSES_ADDR3_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR3_Enabled (0x1UL) /*!< Enable */ + +/* ADDR4 @Bit 4 : Enable or disable reception on logical address 4 */ + #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Min (0x0UL) /*!< Min enumerator value of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Max (0x1UL) /*!< Max enumerator value of ADDR4 field. */ + #define RADIO_RXADDRESSES_ADDR4_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR4_Enabled (0x1UL) /*!< Enable */ + +/* ADDR5 @Bit 5 : Enable or disable reception on logical address 5 */ + #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Min (0x0UL) /*!< Min enumerator value of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Max (0x1UL) /*!< Max enumerator value of ADDR5 field. */ + #define RADIO_RXADDRESSES_ADDR5_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR5_Enabled (0x1UL) /*!< Enable */ + +/* ADDR6 @Bit 6 : Enable or disable reception on logical address 6 */ + #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Min (0x0UL) /*!< Min enumerator value of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Max (0x1UL) /*!< Max enumerator value of ADDR6 field. */ + #define RADIO_RXADDRESSES_ADDR6_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR6_Enabled (0x1UL) /*!< Enable */ + +/* ADDR7 @Bit 7 : Enable or disable reception on logical address 7 */ + #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Min (0x0UL) /*!< Min enumerator value of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Max (0x1UL) /*!< Max enumerator value of ADDR7 field. */ + #define RADIO_RXADDRESSES_ADDR7_Disabled (0x0UL) /*!< Disable */ + #define RADIO_RXADDRESSES_ADDR7_Enabled (0x1UL) /*!< Enable */ + + +/* RADIO_CRCCNF: CRC configuration */ + #define RADIO_CRCCNF_ResetValue (0x00000000UL) /*!< Reset value of CRCCNF register. */ + +/* LEN @Bits 0..1 : CRC length in number of bytes. */ + #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ + #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ + #define RADIO_CRCCNF_LEN_Min (0x1UL) /*!< Min value of LEN field. */ + #define RADIO_CRCCNF_LEN_Max (0x3UL) /*!< Max size of LEN field. */ + #define RADIO_CRCCNF_LEN_Disabled (0x0UL) /*!< CRC length is zero and CRC calculation is disabled */ + #define RADIO_CRCCNF_LEN_One (0x1UL) /*!< CRC length is one byte and CRC calculation is enabled */ + #define RADIO_CRCCNF_LEN_Two (0x2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ + #define RADIO_CRCCNF_LEN_Three (0x3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* SKIPADDR @Bits 8..9 : Include or exclude packet address field out of CRC calculation. */ + #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Min (0x0UL) /*!< Min enumerator value of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Max (0x2UL) /*!< Max enumerator value of SKIPADDR field. */ + #define RADIO_CRCCNF_SKIPADDR_Include (0x0UL) /*!< CRC calculation includes address field */ + #define RADIO_CRCCNF_SKIPADDR_Skip (0x1UL) /*!< CRC calculation does not include address field. The CRC calculation + will start at the first byte after the address.*/ + #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (0x2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after + length field.*/ + + +/* RADIO_CRCPOLY: CRC polynomial */ + #define RADIO_CRCPOLY_ResetValue (0x00000000UL) /*!< Reset value of CRCPOLY register. */ + +/* CRCPOLY @Bits 0..23 : CRC polynomial */ + #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ + #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + + +/* RADIO_CRCINIT: CRC initial value */ + #define RADIO_CRCINIT_ResetValue (0x00000000UL) /*!< Reset value of CRCINIT register. */ + +/* CRCINIT @Bits 0..23 : CRC initial value */ + #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ + #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + + +/* RADIO_DAB: Device address base segment n */ + #define RADIO_DAB_MaxCount (8UL) /*!< Max size of DAB[8] array. */ + #define RADIO_DAB_MaxIndex (7UL) /*!< Max index of DAB[8] array. */ + #define RADIO_DAB_MinIndex (0UL) /*!< Min index of DAB[8] array. */ + #define RADIO_DAB_ResetValue (0x00000000UL) /*!< Reset value of DAB[8] register. */ + +/* DAB @Bits 0..31 : Device address base segment n */ + #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ + #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + + +/* RADIO_DAP: Device address prefix n */ + #define RADIO_DAP_MaxCount (8UL) /*!< Max size of DAP[8] array. */ + #define RADIO_DAP_MaxIndex (7UL) /*!< Max index of DAP[8] array. */ + #define RADIO_DAP_MinIndex (0UL) /*!< Min index of DAP[8] array. */ + #define RADIO_DAP_ResetValue (0x00000000UL) /*!< Reset value of DAP[8] register. */ + +/* DAP @Bits 0..15 : Device address prefix n */ + #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ + #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + + +/* RADIO_DACNF: Device address match configuration */ + #define RADIO_DACNF_ResetValue (0x00000000UL) /*!< Reset value of DACNF register. */ + +/* ENA0 @Bit 0 : Enable or disable device address matching using device address 0 */ + #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ + #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ + #define RADIO_DACNF_ENA0_Min (0x0UL) /*!< Min enumerator value of ENA0 field. */ + #define RADIO_DACNF_ENA0_Max (0x1UL) /*!< Max enumerator value of ENA0 field. */ + #define RADIO_DACNF_ENA0_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA0_Enabled (0x1UL) /*!< Enabled */ + +/* ENA1 @Bit 1 : Enable or disable device address matching using device address 1 */ + #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ + #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ + #define RADIO_DACNF_ENA1_Min (0x0UL) /*!< Min enumerator value of ENA1 field. */ + #define RADIO_DACNF_ENA1_Max (0x1UL) /*!< Max enumerator value of ENA1 field. */ + #define RADIO_DACNF_ENA1_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA1_Enabled (0x1UL) /*!< Enabled */ + +/* ENA2 @Bit 2 : Enable or disable device address matching using device address 2 */ + #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ + #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ + #define RADIO_DACNF_ENA2_Min (0x0UL) /*!< Min enumerator value of ENA2 field. */ + #define RADIO_DACNF_ENA2_Max (0x1UL) /*!< Max enumerator value of ENA2 field. */ + #define RADIO_DACNF_ENA2_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA2_Enabled (0x1UL) /*!< Enabled */ + +/* ENA3 @Bit 3 : Enable or disable device address matching using device address 3 */ + #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ + #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ + #define RADIO_DACNF_ENA3_Min (0x0UL) /*!< Min enumerator value of ENA3 field. */ + #define RADIO_DACNF_ENA3_Max (0x1UL) /*!< Max enumerator value of ENA3 field. */ + #define RADIO_DACNF_ENA3_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA3_Enabled (0x1UL) /*!< Enabled */ + +/* ENA4 @Bit 4 : Enable or disable device address matching using device address 4 */ + #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ + #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ + #define RADIO_DACNF_ENA4_Min (0x0UL) /*!< Min enumerator value of ENA4 field. */ + #define RADIO_DACNF_ENA4_Max (0x1UL) /*!< Max enumerator value of ENA4 field. */ + #define RADIO_DACNF_ENA4_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA4_Enabled (0x1UL) /*!< Enabled */ + +/* ENA5 @Bit 5 : Enable or disable device address matching using device address 5 */ + #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ + #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ + #define RADIO_DACNF_ENA5_Min (0x0UL) /*!< Min enumerator value of ENA5 field. */ + #define RADIO_DACNF_ENA5_Max (0x1UL) /*!< Max enumerator value of ENA5 field. */ + #define RADIO_DACNF_ENA5_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA5_Enabled (0x1UL) /*!< Enabled */ + +/* ENA6 @Bit 6 : Enable or disable device address matching using device address 6 */ + #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ + #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ + #define RADIO_DACNF_ENA6_Min (0x0UL) /*!< Min enumerator value of ENA6 field. */ + #define RADIO_DACNF_ENA6_Max (0x1UL) /*!< Max enumerator value of ENA6 field. */ + #define RADIO_DACNF_ENA6_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA6_Enabled (0x1UL) /*!< Enabled */ + +/* ENA7 @Bit 7 : Enable or disable device address matching using device address 7 */ + #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ + #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ + #define RADIO_DACNF_ENA7_Min (0x0UL) /*!< Min enumerator value of ENA7 field. */ + #define RADIO_DACNF_ENA7_Max (0x1UL) /*!< Max enumerator value of ENA7 field. */ + #define RADIO_DACNF_ENA7_Disabled (0x0UL) /*!< Disabled */ + #define RADIO_DACNF_ENA7_Enabled (0x1UL) /*!< Enabled */ + +/* TXADD0 @Bit 8 : TxAdd for device address 0 */ + #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ + #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* TXADD1 @Bit 9 : TxAdd for device address 1 */ + #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ + #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* TXADD2 @Bit 10 : TxAdd for device address 2 */ + #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ + #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* TXADD3 @Bit 11 : TxAdd for device address 3 */ + #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ + #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* TXADD4 @Bit 12 : TxAdd for device address 4 */ + #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ + #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* TXADD5 @Bit 13 : TxAdd for device address 5 */ + #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ + #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* TXADD6 @Bit 14 : TxAdd for device address 6 */ + #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ + #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* TXADD7 @Bit 15 : TxAdd for device address 7 */ + #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ + #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + + +/* RADIO_BCC: Bit counter compare */ + #define RADIO_BCC_ResetValue (0x00000000UL) /*!< Reset value of BCC register. */ + +/* BCC @Bits 0..31 : Bit counter compare */ + #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ + #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + + +/* RADIO_CTESTATUS: CTEInfo parsed from received packet */ + #define RADIO_CTESTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTESTATUS register. */ + +/* CTETIME @Bits 0..4 : CTETime parsed from packet */ + #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ + #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ + +/* RFU @Bit 5 : RFU parsed from packet */ + #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ + #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ + +/* CTETYPE @Bits 6..7 : CTEType parsed from packet */ + #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ + #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ + + +/* RADIO_MHRMATCHCONF: Search pattern configuration */ + #define RADIO_MHRMATCHCONF_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHCONF register. */ + +/* MHRMATCHCONF @Bits 0..31 : Search pattern configuration */ + #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ + #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of + MHRMATCHCONF field.*/ + + +/* RADIO_MHRMATCHMASK: Pattern mask */ + #define RADIO_MHRMATCHMASK_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHMASK register. */ + +/* MHRMATCHMASK @Bits 0..31 : Pattern mask */ + #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos (0UL) /*!< Position of MHRMATCHMASK field. */ + #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos) /*!< Bit mask of + MHRMATCHMASK field.*/ + + +/* RADIO_SFD: IEEE 802.15.4 start of frame delimiter */ + #define RADIO_SFD_ResetValue (0x000000A7UL) /*!< Reset value of SFD register. */ + +/* SFD @Bits 0..7 : IEEE 802.15.4 start of frame delimiter */ + #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ + #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + + +/* RADIO_CTEINLINECONF: Configuration for CTE inline mode */ + #define RADIO_CTEINLINECONF_ResetValue (0x00002800UL) /*!< Reset value of CTEINLINECONF register. */ + +/* CTEINLINECTRLEN @Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of + CTEINLINECTRLEN field.*/ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Min (0x0UL) /*!< Min enumerator value of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Max (0x1UL) /*!< Max enumerator value of CTEINLINECTRLEN field. */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (0x1UL) /*!< Parsing of CTEInfo is enabled */ + #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0x0UL) /*!< Parsing of CTEInfo is disabled */ + +/* CTEINFOINS1 @Bit 3 : CTEInfo is S1 byte or not */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 + field.*/ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Min (0x0UL) /*!< Min enumerator value of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_Max (0x1UL) /*!< Max enumerator value of CTEINFOINS1 field. */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (0x1UL) /*!< CTEInfo is in S1 byte (data PDU) */ + #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0x0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ + +/* CTEERRORHANDLING @Bit 4 : Sampling/switching if CRC is not OK */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of + CTEERRORHANDLING field.*/ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Min (0x0UL) /*!< Min enumerator value of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Max (0x1UL) /*!< Max enumerator value of CTEERRORHANDLING field. */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (0x1UL) /*!< Sampling and antenna switching also when CRC is not OK */ + #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0x0UL) /*!< No sampling and antenna switching when CRC is not OK */ + +/* CTETIMEVALIDRANGE @Bits 6..7 : Max range of CTETime */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of + CTETIMEVALIDRANGE field.*/ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Min (0x0UL) /*!< Min enumerator value of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Max (0x2UL) /*!< Max enumerator value of CTETIMEVALIDRANGE field. */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0x0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger + han 20*/ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (0x1UL) /*!< 31 in 8us unit */ + #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (0x2UL) /*!< 63 in 8us unit */ + +/* CTEINLINERXMODE1US @Bits 10..12 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of + CTEINLINERXMODE1US field.*/ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE1US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (0x1UL) /*!< 4us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (0x2UL) /*!< 2us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (0x3UL) /*!< 1us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (0x6UL) /*!< 0.125us */ + +/* CTEINLINERXMODE2US @Bits 13..15 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of + CTEINLINERXMODE2US field.*/ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE2US field. */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (0x1UL) /*!< 4us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (0x2UL) /*!< 2us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (0x3UL) /*!< 1us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (0x4UL) /*!< 0.5us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (0x5UL) /*!< 0.25us */ + #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (0x6UL) /*!< 0.125us */ + +/* S0CONF @Bits 16..23 : S0 bit pattern to match */ + #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ + #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ + +/* S0MASK @Bits 24..31 : S0 bit mask to set which bit to match */ + #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ + #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ + + +/* RADIO_PACKETPTR: (unspecified) */ + #define RADIO_PACKETPTR_ResetValue (0x00000000UL) /*!< Reset value of PACKETPTR register. */ + +/* OFFSET @Bits 0..15 : (unspecified) */ + #define RADIO_PACKETPTR_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define RADIO_PACKETPTR_OFFSET_Msk (0xFFFFUL << RADIO_PACKETPTR_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + +/* BASE @Bit 29 : (unspecified) */ + #define RADIO_PACKETPTR_BASE_Pos (29UL) /*!< Position of BASE field. */ + #define RADIO_PACKETPTR_BASE_Msk (0x1UL << RADIO_PACKETPTR_BASE_Pos) /*!< Bit mask of BASE field. */ + + +/* RADIO_POWER: Peripheral power control */ + #define RADIO_POWER_ResetValue (0x00000001UL) /*!< Reset value of POWER register. */ + +/* POWER @Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the + peripheral off and then back on again. */ + + #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ + #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ + #define RADIO_POWER_POWER_Min (0x0UL) /*!< Min enumerator value of POWER field. */ + #define RADIO_POWER_POWER_Max (0x1UL) /*!< Max enumerator value of POWER field. */ + #define RADIO_POWER_POWER_Disabled (0x0UL) /*!< Peripheral is powered off */ + #define RADIO_POWER_POWER_Enabled (0x1UL) /*!< Peripheral is powered on */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RAMC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct RAMC ======================================================= */ +/** + * @brief RAM Controller + */ + typedef struct { /*!< RAMC Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_ERRORFIX; /*!< (@ 0x00000100) ECC detected fixable (one bit) error in read data from + RAM.*/ + __IOM uint32_t EVENTS_ERRORNONFIX; /*!< (@ 0x00000104) ECC detected non-fixable (multiple bits) error in read + data from RAM.*/ + __IM uint32_t RESERVED1[254]; + __IOM uint32_t WAITSTATES; /*!< (@ 0x00000500) Waitstates for read operations. */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t SECBASE; /*!< (@ 0x00000600) Base address for secure access area. */ + __IOM uint32_t SECENABLE; /*!< (@ 0x00000604) Enable secure access restrictions. */ + } NRF_RAMC_Type; /*!< Size = 1544 (0x608) */ + +/* RAMC_EVENTS_ERRORFIX: ECC detected fixable (one bit) error in read data from RAM. */ + #define RAMC_EVENTS_ERRORFIX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERRORFIX register. */ + +/* EVENTS_ERRORFIX @Bit 0 : ECC detected fixable (one bit) error in read data from RAM. */ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Pos (0UL) /*!< Position of EVENTS_ERRORFIX field. */ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Msk (0x1UL << RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Pos) /*!< Bit mask of + EVENTS_ERRORFIX field.*/ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERRORFIX field. */ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERRORFIX field. */ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_NotGenerated (0x0UL) /*!< Event not generated */ + #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Generated (0x1UL) /*!< Event generated */ + + +/* RAMC_EVENTS_ERRORNONFIX: ECC detected non-fixable (multiple bits) error in read data from RAM. */ + #define RAMC_EVENTS_ERRORNONFIX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERRORNONFIX register. */ + +/* EVENTS_ERRORNONFIX @Bit 0 : ECC detected non-fixable (multiple bits) error in read data from RAM. */ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Pos (0UL) /*!< Position of EVENTS_ERRORNONFIX field. */ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Msk (0x1UL << RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Pos) /*!< Bit mask + of EVENTS_ERRORNONFIX field.*/ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERRORNONFIX field. */ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERRORNONFIX field. */ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_NotGenerated (0x0UL) /*!< Event not generated */ + #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Generated (0x1UL) /*!< Event generated */ + + +/* RAMC_WAITSTATES: Waitstates for read operations. */ + #define RAMC_WAITSTATES_ResetValue (0x00000000UL) /*!< Reset value of WAITSTATES register. */ + +/* WAITSTATES @Bit 0 : Number of waitstates for a read from the RAM. */ + #define RAMC_WAITSTATES_WAITSTATES_Pos (0UL) /*!< Position of WAITSTATES field. */ + #define RAMC_WAITSTATES_WAITSTATES_Msk (0x1UL << RAMC_WAITSTATES_WAITSTATES_Pos) /*!< Bit mask of WAITSTATES field. */ + #define RAMC_WAITSTATES_WAITSTATES_Min (0x0UL) /*!< Min value of WAITSTATES field. */ + #define RAMC_WAITSTATES_WAITSTATES_Max (0x1UL) /*!< Max size of WAITSTATES field. */ + + +/* RAMC_SECBASE: Base address for secure access area. */ + #define RAMC_SECBASE_ResetValue (0x00000000UL) /*!< Reset value of SECBASE register. */ + +/* ADDR @Bits 0..31 : Base address */ + #define RAMC_SECBASE_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define RAMC_SECBASE_ADDR_Msk (0xFFFFFFFFUL << RAMC_SECBASE_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* RAMC_SECENABLE: Enable secure access restrictions. */ + #define RAMC_SECENABLE_ResetValue (0x00000000UL) /*!< Reset value of SECENABLE register. */ + +/* ENABLE @Bit 0 : Enable secure access restrictions */ + #define RAMC_SECENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define RAMC_SECENABLE_ENABLE_Msk (0x1UL << RAMC_SECENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define RAMC_SECENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define RAMC_SECENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define RAMC_SECENABLE_ENABLE_Disable (0x0UL) /*!< Secure access restrictions disabled */ + #define RAMC_SECENABLE_ENABLE_Enable (0x1UL) /*!< Secure access restrictions enabled */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RESETINFO ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =============================================== Struct RESETINFO_RESETREAS ================================================ */ +/** + * @brief RESETREAS [RESETINFO_RESETREAS] (unspecified) + */ +typedef struct { + __IOM uint32_t GLOBAL; /*!< (@ 0x00000000) Global reset reason. */ + __IOM uint32_t LOCAL; /*!< (@ 0x00000004) Local reset reason. */ +} NRF_RESETINFO_RESETREAS_Type; /*!< Size = 8 (0x008) */ + +/* RESETINFO_RESETREAS_GLOBAL: Global reset reason. */ + #define RESETINFO_RESETREAS_GLOBAL_ResetValue (0x00000000UL) /*!< Reset value of GLOBAL register. */ + +/* RESETPORONLY @Bit 0 : Reset from power on reset (reset reason POR or BOR). */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Pos (0UL) /*!< Position of RESETPORONLY field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Pos) /*!< Bit mask of + RESETPORONLY field.*/ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Min (0x0UL) /*!< Min enumerator value of RESETPORONLY field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Max (0x1UL) /*!< Max enumerator value of RESETPORONLY field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPORONLY_Detected (0x1UL) /*!< Detected */ + +/* RESETPIN @Bit 1 : Reset from pin reset detected. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Pos (1UL) /*!< Position of RESETPIN field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_RESETPIN_Pos) /*!< Bit mask of RESETPIN + field.*/ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Min (0x0UL) /*!< Min enumerator value of RESETPIN field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Max (0x1UL) /*!< Max enumerator value of RESETPIN field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Detected (0x1UL) /*!< Detected */ + +/* DOG @Bit 2 : Reset from the SysCtrl watchdog timer detected. */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_Pos (2UL) /*!< Position of DOG field. */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_DOG_Pos) /*!< Bit mask of DOG field. */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_Min (0x0UL) /*!< Min enumerator value of DOG field. */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_Max (0x1UL) /*!< Max enumerator value of DOG field. */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_DOG_Detected (0x1UL) /*!< Detected */ + +/* CTRLAP @Bit 3 : Reset from CTRL-AP detected. */ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Pos (3UL) /*!< Position of CTRLAP field. */ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_CTRLAP_Pos) /*!< Bit mask of CTRLAP field.*/ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Min (0x0UL) /*!< Min enumerator value of CTRLAP field. */ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Max (0x1UL) /*!< Max enumerator value of CTRLAP field. */ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Detected (0x1UL) /*!< Detected */ + +/* SECSREQ @Bit 4 : Reset due to secure domain system reset request. */ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Pos (4UL) /*!< Position of SECSREQ field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECSREQ_Pos) /*!< Bit mask of SECSREQ + field.*/ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Min (0x0UL) /*!< Min enumerator value of SECSREQ field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Max (0x1UL) /*!< Max enumerator value of SECSREQ field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Detected (0x1UL) /*!< Detected */ + +/* SECWDT0 @Bit 5 : Reset due to the first instance of watchdog timer in secure domain detected. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_Pos (5UL) /*!< Position of SECWDT0 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECWDT0_Pos) /*!< Bit mask of SECWDT0 + field.*/ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_Min (0x0UL) /*!< Min enumerator value of SECWDT0 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_Max (0x1UL) /*!< Max enumerator value of SECWDT0 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT0_Detected (0x1UL) /*!< Detected */ + +/* SECWDT1 @Bit 6 : Reset due to the second instance of watchdog timer in secure domain detected. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_Pos (6UL) /*!< Position of SECWDT1 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECWDT1_Pos) /*!< Bit mask of SECWDT1 + field.*/ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_Min (0x0UL) /*!< Min enumerator value of SECWDT1 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_Max (0x1UL) /*!< Max enumerator value of SECWDT1 field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECWDT1_Detected (0x1UL) /*!< Detected */ + +/* SECLOCKUP @Bit 7 : Reset due to secure domain lockup. */ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Pos (7UL) /*!< Position of SECLOCKUP field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Pos) /*!< Bit mask of + SECLOCKUP field.*/ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Min (0x0UL) /*!< Min enumerator value of SECLOCKUP field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Max (0x1UL) /*!< Max enumerator value of SECLOCKUP field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Detected (0x1UL) /*!< Detected */ + +/* SECTAMPER @Bit 8 : Reset due to secure domain tamper detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Pos (8UL) /*!< Position of SECTAMPER field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Pos) /*!< Bit mask of + SECTAMPER field.*/ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Min (0x0UL) /*!< Min enumerator value of SECTAMPER field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Max (0x1UL) /*!< Max enumerator value of SECTAMPER field. */ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Detected (0x1UL) /*!< Detected */ + +/* RESETPOR @Bit 9 : Reset from power on reset (reset reason other than POR or BOR). */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Pos (9UL) /*!< Position of RESETPOR field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_RESETPOR_Pos) /*!< Bit mask of RESETPOR + field.*/ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Min (0x0UL) /*!< Min enumerator value of RESETPOR field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Max (0x1UL) /*!< Max enumerator value of RESETPOR field. */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Detected (0x1UL) /*!< Detected */ + +/* OFF @Bit 16 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO. */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_Pos (16UL) /*!< Position of OFF field. */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_OFF_Pos) /*!< Bit mask of OFF field. */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_Min (0x0UL) /*!< Min enumerator value of OFF field. */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_Max (0x1UL) /*!< Max enumerator value of OFF field. */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_OFF_Detected (0x1UL) /*!< Detected */ + +/* LPCOMP @Bit 17 : Reset due to wakeup from System OFF mode when wakeup is triggered by LPCOMP (Low Power Comparator). */ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_LPCOMP_Pos) /*!< Bit mask of LPCOMP field.*/ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Min (0x0UL) /*!< Min enumerator value of LPCOMP field. */ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Max (0x1UL) /*!< Max enumerator value of LPCOMP field. */ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Detected (0x1UL) /*!< Detected */ + +/* DIF @Bit 18 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode. */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_Pos (18UL) /*!< Position of DIF field. */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_DIF_Pos) /*!< Bit mask of DIF field. */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_Min (0x0UL) /*!< Min enumerator value of DIF field. */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_Max (0x1UL) /*!< Max enumerator value of DIF field. */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_DIF_Detected (0x1UL) /*!< Detected */ + +/* GRTC @Bit 19 : Reset due to wakeup from System OFF mode when wakeup is triggered by GRTC interrupt. */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_Pos (19UL) /*!< Position of GRTC field. */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_GRTC_Pos) /*!< Bit mask of GRTC field. */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_Min (0x0UL) /*!< Min enumerator value of GRTC field. */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_Max (0x1UL) /*!< Max enumerator value of GRTC field. */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_GRTC_Detected (0x1UL) /*!< Detected */ + +/* NFC @Bit 20 : Reset due to wakeup from System OFF mode when wakeup is triggered by NFC field detection in sense mode. */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_Pos (20UL) /*!< Position of NFC field. */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_NFC_Pos) /*!< Bit mask of NFC field. */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_Min (0x0UL) /*!< Min enumerator value of NFC field. */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_Max (0x1UL) /*!< Max enumerator value of NFC field. */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_NFC_Detected (0x1UL) /*!< Detected */ + +/* VUSB @Bit 21 : Reset after wakeup from System OFF mode due to VBUS rising into valid range. */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_Pos (21UL) /*!< Position of VUSB field. */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_VUSB_Pos) /*!< Bit mask of VUSB field. */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_Min (0x0UL) /*!< Min enumerator value of VUSB field. */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_Max (0x1UL) /*!< Max enumerator value of VUSB field. */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_GLOBAL_VUSB_Detected (0x1UL) /*!< Detected */ + + +/* RESETINFO_RESETREAS_LOCAL: Local reset reason. */ + #define RESETINFO_RESETREAS_LOCAL_ResetValue (0x00000000UL) /*!< Reset value of LOCAL register. */ + +/* DOG @Bit 0 : Reset from the local watchdog timer detected */ + #define RESETINFO_RESETREAS_LOCAL_DOG_Pos (0UL) /*!< Position of DOG field. */ + #define RESETINFO_RESETREAS_LOCAL_DOG_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_DOG_Pos) /*!< Bit mask of DOG field. */ + #define RESETINFO_RESETREAS_LOCAL_DOG_Min (0x0UL) /*!< Min enumerator value of DOG field. */ + #define RESETINFO_RESETREAS_LOCAL_DOG_Max (0x1UL) /*!< Max enumerator value of DOG field. */ + #define RESETINFO_RESETREAS_LOCAL_DOG_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_LOCAL_DOG_Detected (0x1UL) /*!< Detected */ + +/* DOGNS @Bit 1 : Reset from the local non-secure watchdog timer detected */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_Pos (1UL) /*!< Position of DOGNS field. */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_DOGNS_Pos) /*!< Bit mask of DOGNS field. */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_Min (0x0UL) /*!< Min enumerator value of DOGNS field. */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_Max (0x1UL) /*!< Max enumerator value of DOGNS field. */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_LOCAL_DOGNS_Detected (0x1UL) /*!< Detected */ + +/* SREQ @Bit 2 : Reset from the local soft reset request detected. */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_Pos (2UL) /*!< Position of SREQ field. */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_SREQ_Pos) /*!< Bit mask of SREQ field. */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_Min (0x0UL) /*!< Min enumerator value of SREQ field. */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_Max (0x1UL) /*!< Max enumerator value of SREQ field. */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_LOCAL_SREQ_Detected (0x1UL) /*!< Detected */ + +/* LOCKUP @Bit 3 : Reset from local CPU lockup detected */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Min (0x0UL) /*!< Min enumerator value of LOCKUP field. */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Max (0x1UL) /*!< Max enumerator value of LOCKUP field. */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Detected (0x1UL) /*!< Detected */ + +/* CROSSDOMAIN @Bit 4 : Reset due to cross domain reset source. */ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos (4UL) /*!< Position of CROSSDOMAIN field. */ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos) /*!< Bit mask of + CROSSDOMAIN field.*/ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Min (0x0UL) /*!< Min enumerator value of CROSSDOMAIN field. */ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Max (0x1UL) /*!< Max enumerator value of CROSSDOMAIN field. */ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_NotDetected (0x0UL) /*!< Not detected */ + #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Detected (0x1UL) /*!< Detected */ + +/* UNRETAINEDWAKE @Bit 5 : Reset due to wake from unretained state. */ + #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos (5UL) /*!< Position of UNRETAINEDWAKE field. */ + #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos) /*!< Bit mask of + UNRETAINEDWAKE field.*/ + + + +/* ================================================= Struct RESETINFO_ERROR ================================================== */ +/** + * @brief ERROR [RESETINFO_ERROR] (unspecified) + */ +typedef struct { + __IOM uint32_t STATUS; /*!< (@ 0x00000000) Reset error status. */ + __IOM uint32_t ADDRESS; /*!< (@ 0x00000004) Reset error address. */ +} NRF_RESETINFO_ERROR_Type; /*!< Size = 8 (0x008) */ + +/* RESETINFO_ERROR_STATUS: Reset error status. */ + #define RESETINFO_ERROR_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* ERRORSTATUS @Bits 0..3 : Error status */ + #define RESETINFO_ERROR_STATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field. */ + #define RESETINFO_ERROR_STATUS_ERRORSTATUS_Msk (0xFUL << RESETINFO_ERROR_STATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS + field.*/ + + +/* RESETINFO_ERROR_ADDRESS: Reset error address. */ + #define RESETINFO_ERROR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ERRORADDRESS @Bits 0..31 : Error address */ + #define RESETINFO_ERROR_ADDRESS_ERRORADDRESS_Pos (0UL) /*!< Position of ERRORADDRESS field. */ + #define RESETINFO_ERROR_ADDRESS_ERRORADDRESS_Msk (0xFFFFFFFFUL << RESETINFO_ERROR_ADDRESS_ERRORADDRESS_Pos) /*!< Bit mask of + ERRORADDRESS field.*/ + + +/* ==================================================== Struct RESETINFO ===================================================== */ +/** + * @brief RESETINFO + */ + typedef struct { /*!< RESETINFO Structure */ + __IM uint32_t RESERVED[296]; + __IOM NRF_RESETINFO_RESETREAS_Type RESETREAS; /*!< (@ 0x000004A0) (unspecified) */ + __IOM NRF_RESETINFO_ERROR_Type ERROR; /*!< (@ 0x000004A8) (unspecified) */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t RESTOREVALID; /*!< (@ 0x000004C0) Valid restore image is present in RAM. */ + } NRF_RESETINFO_Type; /*!< Size = 1220 (0x4C4) */ + +/* RESETINFO_RESTOREVALID: Valid restore image is present in RAM. */ + #define RESETINFO_RESTOREVALID_ResetValue (0x00000000UL) /*!< Reset value of RESTOREVALID register. */ + +/* RESTOREVALID @Bit 0 : Valid restore image is present in RAM. */ + #define RESETINFO_RESTOREVALID_RESTOREVALID_Pos (0UL) /*!< Position of RESTOREVALID field. */ + #define RESETINFO_RESTOREVALID_RESTOREVALID_Msk (0x1UL << RESETINFO_RESTOREVALID_RESTOREVALID_Pos) /*!< Bit mask of + RESTOREVALID field.*/ + #define RESETINFO_RESTOREVALID_RESTOREVALID_Min (0x0UL) /*!< Min enumerator value of RESTOREVALID field. */ + #define RESETINFO_RESTOREVALID_RESTOREVALID_Max (0x1UL) /*!< Max enumerator value of RESTOREVALID field. */ + #define RESETINFO_RESTOREVALID_RESTOREVALID_NotPreset (0x0UL) /*!< Not present */ + #define RESETINFO_RESTOREVALID_RESTOREVALID_Present (0x1UL) /*!< Present */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct RTC ======================================================== */ +/** + * @brief Real-time counter + */ + typedef struct { /*!< RTC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ + __IM uint32_t RESERVED[12]; + __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Capture RTC counter to CC[n] register */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ + __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ + __IM uint32_t RESERVED2[12]; + __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n] */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Compare event on CC[n] match */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ + __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ + __IM uint32_t RESERVED6[14]; + __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n] */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED10[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 / + (PRESCALER + 1)). Must be written when RTC is stopped.*/ + __IM uint32_t RESERVED11[13]; + __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Compare register n */ + } NRF_RTC_Type; /*!< Size = 1376 (0x560) */ + +/* RTC_TASKS_START: Start RTC counter */ + #define RTC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start RTC counter */ + #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define RTC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define RTC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* RTC_TASKS_STOP: Stop RTC counter */ + #define RTC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop RTC counter */ + #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define RTC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define RTC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* RTC_TASKS_CLEAR: Clear RTC counter */ + #define RTC_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register. */ + +/* TASKS_CLEAR @Bit 0 : Clear RTC counter */ + #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ + #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + #define RTC_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEAR field. */ + #define RTC_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEAR field. */ + #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ + + +/* RTC_TASKS_TRIGOVRFLW: Set counter to 0xFFFFF0 */ + #define RTC_TASKS_TRIGOVRFLW_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGOVRFLW register. */ + +/* TASKS_TRIGOVRFLW @Bit 0 : Set counter to 0xFFFFF0 */ + #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ + #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of + TASKS_TRIGOVRFLW field.*/ + #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGOVRFLW field. */ + #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGOVRFLW field. */ + #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */ + + +/* RTC_TASKS_CAPTURE: Capture RTC counter to CC[n] register */ + #define RTC_TASKS_CAPTURE_MaxCount (8UL) /*!< Max size of TASKS_CAPTURE[8] array. */ + #define RTC_TASKS_CAPTURE_MaxIndex (7UL) /*!< Max index of TASKS_CAPTURE[8] array. */ + #define RTC_TASKS_CAPTURE_MinIndex (0UL) /*!< Min index of TASKS_CAPTURE[8] array. */ + #define RTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register. */ + +/* TASKS_CAPTURE @Bit 0 : Capture RTC counter to CC[n] register */ + #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ + #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE + field.*/ + #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field. */ + #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field. */ + #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ + + +/* RTC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define RTC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RTC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define RTC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RTC_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */ + #define RTC_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */ + #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_SUBSCRIBE_CLEAR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_SUBSCRIBE_CLEAR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_SUBSCRIBE_CLEAR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RTC_SUBSCRIBE_TRIGOVRFLW: Subscribe configuration for task TRIGOVRFLW */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGOVRFLW register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task TRIGOVRFLW will subscribe to */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */ + #define RTC_SUBSCRIBE_CAPTURE_MaxCount (8UL) /*!< Max size of SUBSCRIBE_CAPTURE[8] array. */ + #define RTC_SUBSCRIBE_CAPTURE_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_CAPTURE[8] array. */ + #define RTC_SUBSCRIBE_CAPTURE_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CAPTURE[8] array. */ + #define RTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */ + #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* RTC_EVENTS_TICK: Event on counter increment */ + #define RTC_EVENTS_TICK_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TICK register. */ + +/* EVENTS_TICK @Bit 0 : Event on counter increment */ + #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ + #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ + #define RTC_EVENTS_TICK_EVENTS_TICK_Min (0x0UL) /*!< Min enumerator value of EVENTS_TICK field. */ + #define RTC_EVENTS_TICK_EVENTS_TICK_Max (0x1UL) /*!< Max enumerator value of EVENTS_TICK field. */ + #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */ + #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */ + + +/* RTC_EVENTS_OVRFLW: Event on counter overflow */ + #define RTC_EVENTS_OVRFLW_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_OVRFLW register. */ + +/* EVENTS_OVRFLW @Bit 0 : Event on counter overflow */ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW + field.*/ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Min (0x0UL) /*!< Min enumerator value of EVENTS_OVRFLW field. */ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Max (0x1UL) /*!< Max enumerator value of EVENTS_OVRFLW field. */ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */ + #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */ + + +/* RTC_EVENTS_COMPARE: Compare event on CC[n] match */ + #define RTC_EVENTS_COMPARE_MaxCount (8UL) /*!< Max size of EVENTS_COMPARE[8] array. */ + #define RTC_EVENTS_COMPARE_MaxIndex (7UL) /*!< Max index of EVENTS_COMPARE[8] array. */ + #define RTC_EVENTS_COMPARE_MinIndex (0UL) /*!< Min index of EVENTS_COMPARE[8] array. */ + #define RTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register. */ + +/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE + field.*/ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field. */ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field. */ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ + #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ + + +/* RTC_PUBLISH_TICK: Publish configuration for event TICK */ + #define RTC_PUBLISH_TICK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TICK register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TICK will publish to */ + #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_PUBLISH_TICK_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_PUBLISH_TICK_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_PUBLISH_TICK_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_PUBLISH_TICK_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_PUBLISH_TICK_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RTC_PUBLISH_TICK_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RTC_PUBLISH_OVRFLW: Publish configuration for event OVRFLW */ + #define RTC_PUBLISH_OVRFLW_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_OVRFLW register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event OVRFLW will publish to */ + #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_PUBLISH_OVRFLW_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_PUBLISH_OVRFLW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_PUBLISH_OVRFLW_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_PUBLISH_OVRFLW_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */ + #define RTC_PUBLISH_COMPARE_MaxCount (8UL) /*!< Max size of PUBLISH_COMPARE[8] array. */ + #define RTC_PUBLISH_COMPARE_MaxIndex (7UL) /*!< Max index of PUBLISH_COMPARE[8] array. */ + #define RTC_PUBLISH_COMPARE_MinIndex (0UL) /*!< Min index of PUBLISH_COMPARE[8] array. */ + #define RTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */ + #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define RTC_PUBLISH_COMPARE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define RTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ + #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ + #define RTC_PUBLISH_COMPARE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define RTC_PUBLISH_COMPARE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* RTC_SHORTS: Shortcuts between local events and tasks */ + #define RTC_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ + #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ + #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ + #define RTC_SHORTS_COMPARE0_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE0_CLEAR field. */ + #define RTC_SHORTS_COMPARE0_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE0_CLEAR field. */ + #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ + #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ + #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ + #define RTC_SHORTS_COMPARE1_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE1_CLEAR field. */ + #define RTC_SHORTS_COMPARE1_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE1_CLEAR field. */ + #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ + #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ + #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ + #define RTC_SHORTS_COMPARE2_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE2_CLEAR field. */ + #define RTC_SHORTS_COMPARE2_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE2_CLEAR field. */ + #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ + #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ + #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ + #define RTC_SHORTS_COMPARE3_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE3_CLEAR field. */ + #define RTC_SHORTS_COMPARE3_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE3_CLEAR field. */ + #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ + #define RTC_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ + #define RTC_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ + #define RTC_SHORTS_COMPARE4_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE4_CLEAR field. */ + #define RTC_SHORTS_COMPARE4_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE4_CLEAR field. */ + #define RTC_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ + #define RTC_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ + #define RTC_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ + #define RTC_SHORTS_COMPARE5_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE5_CLEAR field. */ + #define RTC_SHORTS_COMPARE5_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE5_CLEAR field. */ + #define RTC_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */ + #define RTC_SHORTS_COMPARE6_CLEAR_Pos (6UL) /*!< Position of COMPARE6_CLEAR field. */ + #define RTC_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field. */ + #define RTC_SHORTS_COMPARE6_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE6_CLEAR field. */ + #define RTC_SHORTS_COMPARE6_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE6_CLEAR field. */ + #define RTC_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */ + #define RTC_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */ + #define RTC_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */ + #define RTC_SHORTS_COMPARE7_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE7_CLEAR field. */ + #define RTC_SHORTS_COMPARE7_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE7_CLEAR field. */ + #define RTC_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define RTC_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* RTC_INTENSET: Enable interrupt */ + #define RTC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TICK @Bit 0 : Write '1' to enable interrupt for event TICK */ + #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ + #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ + #define RTC_INTENSET_TICK_Min (0x0UL) /*!< Min enumerator value of TICK field. */ + #define RTC_INTENSET_TICK_Max (0x1UL) /*!< Max enumerator value of TICK field. */ + #define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* OVRFLW @Bit 1 : Write '1' to enable interrupt for event OVRFLW */ + #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ + #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ + #define RTC_INTENSET_OVRFLW_Min (0x0UL) /*!< Min enumerator value of OVRFLW field. */ + #define RTC_INTENSET_OVRFLW_Max (0x1UL) /*!< Max enumerator value of OVRFLW field. */ + #define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ + #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define RTC_INTENSET_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define RTC_INTENSET_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ + #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define RTC_INTENSET_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define RTC_INTENSET_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ + #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define RTC_INTENSET_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define RTC_INTENSET_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ + #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define RTC_INTENSET_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define RTC_INTENSET_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ + #define RTC_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define RTC_INTENSET_COMPARE4_Msk (0x1UL << RTC_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define RTC_INTENSET_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define RTC_INTENSET_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define RTC_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ + #define RTC_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define RTC_INTENSET_COMPARE5_Msk (0x1UL << RTC_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define RTC_INTENSET_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define RTC_INTENSET_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define RTC_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */ + #define RTC_INTENSET_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define RTC_INTENSET_COMPARE6_Msk (0x1UL << RTC_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define RTC_INTENSET_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define RTC_INTENSET_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define RTC_INTENSET_COMPARE6_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */ + #define RTC_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define RTC_INTENSET_COMPARE7_Msk (0x1UL << RTC_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define RTC_INTENSET_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define RTC_INTENSET_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define RTC_INTENSET_COMPARE7_Set (0x1UL) /*!< Enable */ + #define RTC_INTENSET_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENSET_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RTC_INTENCLR: Disable interrupt */ + #define RTC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TICK @Bit 0 : Write '1' to disable interrupt for event TICK */ + #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ + #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ + #define RTC_INTENCLR_TICK_Min (0x0UL) /*!< Min enumerator value of TICK field. */ + #define RTC_INTENCLR_TICK_Max (0x1UL) /*!< Max enumerator value of TICK field. */ + #define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ + +/* OVRFLW @Bit 1 : Write '1' to disable interrupt for event OVRFLW */ + #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ + #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ + #define RTC_INTENCLR_OVRFLW_Min (0x0UL) /*!< Min enumerator value of OVRFLW field. */ + #define RTC_INTENCLR_OVRFLW_Max (0x1UL) /*!< Max enumerator value of OVRFLW field. */ + #define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ + #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define RTC_INTENCLR_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define RTC_INTENCLR_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ + #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define RTC_INTENCLR_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define RTC_INTENCLR_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ + #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define RTC_INTENCLR_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define RTC_INTENCLR_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ + #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define RTC_INTENCLR_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define RTC_INTENCLR_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ + #define RTC_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define RTC_INTENCLR_COMPARE4_Msk (0x1UL << RTC_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define RTC_INTENCLR_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define RTC_INTENCLR_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define RTC_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ + #define RTC_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define RTC_INTENCLR_COMPARE5_Msk (0x1UL << RTC_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define RTC_INTENCLR_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define RTC_INTENCLR_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define RTC_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */ + #define RTC_INTENCLR_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define RTC_INTENCLR_COMPARE6_Msk (0x1UL << RTC_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define RTC_INTENCLR_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define RTC_INTENCLR_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define RTC_INTENCLR_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */ + #define RTC_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define RTC_INTENCLR_COMPARE7_Msk (0x1UL << RTC_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define RTC_INTENCLR_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define RTC_INTENCLR_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define RTC_INTENCLR_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define RTC_INTENCLR_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_INTENCLR_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* RTC_EVTEN: Enable or disable event routing */ + #define RTC_EVTEN_ResetValue (0x00000000UL) /*!< Reset value of EVTEN register. */ + +/* TICK @Bit 0 : Enable or disable event routing for event TICK */ + #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ + #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ + #define RTC_EVTEN_TICK_Min (0x0UL) /*!< Min enumerator value of TICK field. */ + #define RTC_EVTEN_TICK_Max (0x1UL) /*!< Max enumerator value of TICK field. */ + #define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */ + +/* OVRFLW @Bit 1 : Enable or disable event routing for event OVRFLW */ + #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ + #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ + #define RTC_EVTEN_OVRFLW_Min (0x0UL) /*!< Min enumerator value of OVRFLW field. */ + #define RTC_EVTEN_OVRFLW_Max (0x1UL) /*!< Max enumerator value of OVRFLW field. */ + #define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE0 @Bit 16 : Enable or disable event routing for event COMPARE[0] */ + #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define RTC_EVTEN_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define RTC_EVTEN_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 17 : Enable or disable event routing for event COMPARE[1] */ + #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define RTC_EVTEN_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define RTC_EVTEN_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 18 : Enable or disable event routing for event COMPARE[2] */ + #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define RTC_EVTEN_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define RTC_EVTEN_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 19 : Enable or disable event routing for event COMPARE[3] */ + #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define RTC_EVTEN_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define RTC_EVTEN_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 20 : Enable or disable event routing for event COMPARE[4] */ + #define RTC_EVTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define RTC_EVTEN_COMPARE4_Msk (0x1UL << RTC_EVTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define RTC_EVTEN_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define RTC_EVTEN_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define RTC_EVTEN_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 21 : Enable or disable event routing for event COMPARE[5] */ + #define RTC_EVTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define RTC_EVTEN_COMPARE5_Msk (0x1UL << RTC_EVTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define RTC_EVTEN_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define RTC_EVTEN_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define RTC_EVTEN_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 22 : Enable or disable event routing for event COMPARE[6] */ + #define RTC_EVTEN_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define RTC_EVTEN_COMPARE6_Msk (0x1UL << RTC_EVTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define RTC_EVTEN_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define RTC_EVTEN_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define RTC_EVTEN_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 23 : Enable or disable event routing for event COMPARE[7] */ + #define RTC_EVTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define RTC_EVTEN_COMPARE7_Msk (0x1UL << RTC_EVTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define RTC_EVTEN_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define RTC_EVTEN_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define RTC_EVTEN_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define RTC_EVTEN_COMPARE7_Enabled (0x1UL) /*!< Enable */ + + +/* RTC_EVTENSET: Enable event routing */ + #define RTC_EVTENSET_ResetValue (0x00000000UL) /*!< Reset value of EVTENSET register. */ + +/* TICK @Bit 0 : Write '1' to enable event routing for event TICK */ + #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ + #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ + #define RTC_EVTENSET_TICK_Min (0x0UL) /*!< Min enumerator value of TICK field. */ + #define RTC_EVTENSET_TICK_Max (0x1UL) /*!< Max enumerator value of TICK field. */ + #define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */ + +/* OVRFLW @Bit 1 : Write '1' to enable event routing for event OVRFLW */ + #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ + #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ + #define RTC_EVTENSET_OVRFLW_Min (0x0UL) /*!< Min enumerator value of OVRFLW field. */ + #define RTC_EVTENSET_OVRFLW_Max (0x1UL) /*!< Max enumerator value of OVRFLW field. */ + #define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ + +/* COMPARE0 @Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ + #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define RTC_EVTENSET_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define RTC_EVTENSET_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ + #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define RTC_EVTENSET_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define RTC_EVTENSET_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ + #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define RTC_EVTENSET_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define RTC_EVTENSET_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ + #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define RTC_EVTENSET_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define RTC_EVTENSET_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 20 : Write '1' to enable event routing for event COMPARE[4] */ + #define RTC_EVTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define RTC_EVTENSET_COMPARE4_Msk (0x1UL << RTC_EVTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define RTC_EVTENSET_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define RTC_EVTENSET_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define RTC_EVTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 21 : Write '1' to enable event routing for event COMPARE[5] */ + #define RTC_EVTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define RTC_EVTENSET_COMPARE5_Msk (0x1UL << RTC_EVTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define RTC_EVTENSET_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define RTC_EVTENSET_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define RTC_EVTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 22 : Write '1' to enable event routing for event COMPARE[6] */ + #define RTC_EVTENSET_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define RTC_EVTENSET_COMPARE6_Msk (0x1UL << RTC_EVTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define RTC_EVTENSET_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define RTC_EVTENSET_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define RTC_EVTENSET_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE6_Set (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 23 : Write '1' to enable event routing for event COMPARE[7] */ + #define RTC_EVTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define RTC_EVTENSET_COMPARE7_Msk (0x1UL << RTC_EVTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define RTC_EVTENSET_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define RTC_EVTENSET_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define RTC_EVTENSET_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENSET_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENSET_COMPARE7_Set (0x1UL) /*!< Enable */ + + +/* RTC_EVTENCLR: Disable event routing */ + #define RTC_EVTENCLR_ResetValue (0x00000000UL) /*!< Reset value of EVTENCLR register. */ + +/* TICK @Bit 0 : Write '1' to disable event routing for event TICK */ + #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ + #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ + #define RTC_EVTENCLR_TICK_Min (0x0UL) /*!< Min enumerator value of TICK field. */ + #define RTC_EVTENCLR_TICK_Max (0x1UL) /*!< Max enumerator value of TICK field. */ + #define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */ + +/* OVRFLW @Bit 1 : Write '1' to disable event routing for event OVRFLW */ + #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ + #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ + #define RTC_EVTENCLR_OVRFLW_Min (0x0UL) /*!< Min enumerator value of OVRFLW field. */ + #define RTC_EVTENCLR_OVRFLW_Max (0x1UL) /*!< Max enumerator value of OVRFLW field. */ + #define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ + +/* COMPARE0 @Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ + #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define RTC_EVTENCLR_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define RTC_EVTENCLR_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ + +/* COMPARE1 @Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ + #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define RTC_EVTENCLR_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define RTC_EVTENCLR_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ + +/* COMPARE2 @Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ + #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define RTC_EVTENCLR_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define RTC_EVTENCLR_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ + +/* COMPARE3 @Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ + #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define RTC_EVTENCLR_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define RTC_EVTENCLR_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ + +/* COMPARE4 @Bit 20 : Write '1' to disable event routing for event COMPARE[4] */ + #define RTC_EVTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define RTC_EVTENCLR_COMPARE4_Msk (0x1UL << RTC_EVTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define RTC_EVTENCLR_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define RTC_EVTENCLR_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define RTC_EVTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ + +/* COMPARE5 @Bit 21 : Write '1' to disable event routing for event COMPARE[5] */ + #define RTC_EVTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define RTC_EVTENCLR_COMPARE5_Msk (0x1UL << RTC_EVTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define RTC_EVTENCLR_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define RTC_EVTENCLR_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define RTC_EVTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ + +/* COMPARE6 @Bit 22 : Write '1' to disable event routing for event COMPARE[6] */ + #define RTC_EVTENCLR_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define RTC_EVTENCLR_COMPARE6_Msk (0x1UL << RTC_EVTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define RTC_EVTENCLR_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define RTC_EVTENCLR_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define RTC_EVTENCLR_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE6_Clear (0x1UL) /*!< Disable */ + +/* COMPARE7 @Bit 23 : Write '1' to disable event routing for event COMPARE[7] */ + #define RTC_EVTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define RTC_EVTENCLR_COMPARE7_Msk (0x1UL << RTC_EVTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define RTC_EVTENCLR_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define RTC_EVTENCLR_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define RTC_EVTENCLR_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define RTC_EVTENCLR_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + #define RTC_EVTENCLR_COMPARE7_Clear (0x1UL) /*!< Disable */ + + +/* RTC_COUNTER: Current counter value */ + #define RTC_COUNTER_ResetValue (0x00000000UL) /*!< Reset value of COUNTER register. */ + +/* COUNTER @Bits 0..23 : Counter value */ + #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ + #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + + +/* RTC_PRESCALER: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */ + #define RTC_PRESCALER_ResetValue (0x00000000UL) /*!< Reset value of PRESCALER register. */ + +/* PRESCALER @Bits 0..11 : Prescaler value */ + #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ + #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + + +/* RTC_CC: Compare register n */ + #define RTC_CC_MaxCount (8UL) /*!< Max size of CC[8] array. */ + #define RTC_CC_MaxIndex (7UL) /*!< Max index of CC[8] array. */ + #define RTC_CC_MinIndex (0UL) /*!< Min index of CC[8] array. */ + #define RTC_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[8] register. */ + +/* COMPARE @Bits 0..31 : Compare value */ + #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ + #define RTC_CC_COMPARE_Msk (0xFFFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct SAADC_EVENTS_CH ================================================== */ +/** + * @brief EVENTS_CH [SAADC_EVENTS_CH] Peripheral events. + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Last results is equal or above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Last results is equal or below CH[n].LIMIT.LOW */ +} NRF_SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x008) */ + #define SAADC_EVENTS_CH_MaxCount (8UL) /*!< Size of EVENTS_CH[8] array. */ + #define SAADC_EVENTS_CH_MaxIndex (7UL) /*!< Max index of EVENTS_CH[8] array. */ + #define SAADC_EVENTS_CH_MinIndex (0UL) /*!< Min index of EVENTS_CH[8] array. */ + +/* SAADC_EVENTS_CH_LIMITH: Last results is equal or above CH[n].LIMIT.HIGH */ + #define SAADC_EVENTS_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ + +/* LIMITH @Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Min (0x0UL) /*!< Min enumerator value of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Max (0x1UL) /*!< Max enumerator value of LIMITH field. */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_CH_LIMITL: Last results is equal or below CH[n].LIMIT.LOW */ + #define SAADC_EVENTS_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register. */ + +/* LIMITL @Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Min (0x0UL) /*!< Min enumerator value of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Max (0x1UL) /*!< Max enumerator value of LIMITL field. */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SAADC_PUBLISH_CH ================================================= */ +/** + * @brief PUBLISH_CH [SAADC_PUBLISH_CH] Publish configuration for events + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Publish configuration for event CH[n].LIMITH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Publish configuration for event CH[n].LIMITL */ +} NRF_SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x008) */ + #define SAADC_PUBLISH_CH_MaxCount (8UL) /*!< Size of PUBLISH_CH[8] array. */ + #define SAADC_PUBLISH_CH_MaxIndex (7UL) /*!< Max index of PUBLISH_CH[8] array. */ + #define SAADC_PUBLISH_CH_MinIndex (0UL) /*!< Min index of PUBLISH_CH[8] array. */ + +/* SAADC_PUBLISH_CH_LIMITH: Publish configuration for event CH[n].LIMITH */ + #define SAADC_PUBLISH_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITH will publish to */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_CH_LIMITL: Publish configuration for event CH[n].LIMITL */ + #define SAADC_PUBLISH_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITL will publish to */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ==================================================== Struct SAADC_TRIM ==================================================== */ +/** + * @brief TRIM [SAADC_TRIM] (unspecified) + */ +typedef struct { + __IOM uint32_t LINCALCOEFF[6]; /*!< (@ 0x00000000) Linearity calibration coefficient */ +} NRF_SAADC_TRIM_Type; /*!< Size = 24 (0x018) */ + +/* SAADC_TRIM_LINCALCOEFF: Linearity calibration coefficient */ + #define SAADC_TRIM_LINCALCOEFF_MaxCount (6UL) /*!< Max size of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_MaxIndex (5UL) /*!< Max index of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_MinIndex (0UL) /*!< Min index of LINCALCOEFF[6] array. */ + #define SAADC_TRIM_LINCALCOEFF_ResetValue (0x00000000UL) /*!< Reset value of LINCALCOEFF[6] register. */ + +/* VAL @Bits 0..15 : value */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Msk (0xFFFFUL << SAADC_TRIM_LINCALCOEFF_VAL_Pos) /*!< Bit mask of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Min (0x0000UL) /*!< Min value of VAL field. */ + #define SAADC_TRIM_LINCALCOEFF_VAL_Max (0xFFFFUL) /*!< Max size of VAL field. */ + + + +/* ===================================================== Struct SAADC_CH ===================================================== */ +/** + * @brief CH [SAADC_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Input positive pin selection for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Input negative pin selection for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Input configuration for CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) High/low limits for event monitoring a channel */ +} NRF_SAADC_CH_Type; /*!< Size = 16 (0x010) */ + #define SAADC_CH_MaxCount (8UL) /*!< Size of CH[8] array. */ + #define SAADC_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ + #define SAADC_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ + +/* SAADC_CH_PSELP: Input positive pin selection for CH[n] */ + #define SAADC_CH_PSELP_ResetValue (0x00000000UL) /*!< Reset value of PSELP register. */ + +/* PIN @Bits 0..4 : Analog positive input pin select */ + #define SAADC_CH_PSELP_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define SAADC_CH_PSELP_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* CONNECT @Bits 30..31 : Connection */ + #define SAADC_CH_PSELP_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Msk (0x3UL << SAADC_CH_PSELP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELP_CONNECT_NC (0x0UL) /*!< Not connected */ + #define SAADC_CH_PSELP_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + + +/* SAADC_CH_PSELN: Input negative pin selection for CH[n] */ + #define SAADC_CH_PSELN_ResetValue (0x00000000UL) /*!< Reset value of PSELN register. */ + +/* PIN @Bits 0..4 : Analog negative input pin select */ + #define SAADC_CH_PSELN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* PORT @Bits 8..11 : GPIO Port selection */ + #define SAADC_CH_PSELN_PORT_Pos (8UL) /*!< Position of PORT field. */ + #define SAADC_CH_PSELN_PORT_Msk (0xFUL << SAADC_CH_PSELN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* CONNECT @Bits 30..31 : Connection */ + #define SAADC_CH_PSELN_CONNECT_Pos (30UL) /*!< Position of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SAADC_CH_PSELN_CONNECT_NC (0x0UL) /*!< Not connected */ + #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input */ + + +/* SAADC_CH_CONFIG: Input configuration for CH[n] */ + #define SAADC_CH_CONFIG_ResetValue (0x00020000UL) /*!< Reset value of CONFIG register. */ + +/* RESP @Bits 0..1 : Positive channel resistor control */ + #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ + #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ + #define SAADC_CH_CONFIG_RESP_Min (0x0UL) /*!< Min enumerator value of RESP field. */ + #define SAADC_CH_CONFIG_RESP_Max (0x3UL) /*!< Max enumerator value of RESP field. */ + #define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */ + #define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */ + #define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD_AO_1V8 */ + #define SAADC_CH_CONFIG_RESP_VDDAO1V8div2 (0x3UL) /*!< Set input at VDD_AO_1V8/2 */ + +/* RESN @Bits 4..5 : Negative channel resistor control */ + #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ + #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ + #define SAADC_CH_CONFIG_RESN_Min (0x0UL) /*!< Min enumerator value of RESN field. */ + #define SAADC_CH_CONFIG_RESN_Max (0x3UL) /*!< Max enumerator value of RESN field. */ + #define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */ + #define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */ + #define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD_AO_1V8 */ + #define SAADC_CH_CONFIG_RESN_VDDAO1V8div2 (0x3UL) /*!< Set input at VDD_AO_1V8/2 */ + +/* GAIN @Bits 8..9 : Gain control */ + #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Msk (0x3UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Min (0x0UL) /*!< Min enumerator value of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Max (0x3UL) /*!< Max enumerator value of GAIN field. */ + #define SAADC_CH_CONFIG_GAIN_Gain2_3 (0x0UL) /*!< 2/3 */ + #define SAADC_CH_CONFIG_GAIN_Gain1 (0x1UL) /*!< 1 */ + #define SAADC_CH_CONFIG_GAIN_Gain2 (0x2UL) /*!< 2 */ + #define SAADC_CH_CONFIG_GAIN_Gain4 (0x3UL) /*!< 4 */ + +/* BURST @Bit 11 : Enable burst mode */ + #define SAADC_CH_CONFIG_BURST_Pos (11UL) /*!< Position of BURST field. */ + #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ + #define SAADC_CH_CONFIG_BURST_Min (0x0UL) /*!< Min enumerator value of BURST field. */ + #define SAADC_CH_CONFIG_BURST_Max (0x1UL) /*!< Max enumerator value of BURST field. */ + #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */ + #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as + fast as it can, and sends the average to Data RAM.*/ + +/* REFSEL @Bit 12 : Reference control */ + #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Min (0x0UL) /*!< Min enumerator value of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Max (0x1UL) /*!< Max enumerator value of REFSEL field. */ + #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (1.024 V) */ + #define SAADC_CH_CONFIG_REFSEL_External (0x1UL) /*!< External reference given at PADC_EXT_REF_1V2 */ + +/* MODE @Bit 15 : Enable differential mode */ + #define SAADC_CH_CONFIG_MODE_Pos (15UL) /*!< Position of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define SAADC_CH_CONFIG_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to + GND*/ + #define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */ + +/* TACQ @Bits 16..24 : Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is + ((TACQ+1) x 125 ns) */ + + #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Msk (0x1FFUL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Min (0x000UL) /*!< Min value of TACQ field. */ + #define SAADC_CH_CONFIG_TACQ_Max (0x13FUL) /*!< Max size of TACQ field. */ + +/* TCONV @Bits 28..30 : Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) */ + #define SAADC_CH_CONFIG_TCONV_Pos (28UL) /*!< Position of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Msk (0x7UL << SAADC_CH_CONFIG_TCONV_Pos) /*!< Bit mask of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Min (0x0UL) /*!< Min value of TCONV field. */ + #define SAADC_CH_CONFIG_TCONV_Max (0x7UL) /*!< Max size of TCONV field. */ + + +/* SAADC_CH_LIMIT: High/low limits for event monitoring a channel */ + #define SAADC_CH_LIMIT_ResetValue (0x7FFF8000UL) /*!< Reset value of LIMIT register. */ + +/* LOW @Bits 0..15 : Low level limit */ + #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ + #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* HIGH @Bits 16..31 : High level limit */ + #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ + #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + + + +/* =================================================== Struct SAADC_RESULT =================================================== */ +/** + * @brief RESULT [SAADC_RESULT] RESULT EasyDMA channel + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer bytes transferred since last START */ + __IM uint32_t RESERVED; +} NRF_SAADC_RESULT_Type; /*!< Size = 16 (0x010) */ + +/* SAADC_RESULT_PTR: Data pointer */ + #define SAADC_RESULT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Data pointer */ + #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SAADC_RESULT_MAXCNT: Maximum number of buffer bytes to transfer */ + #define SAADC_RESULT_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of buffer bytes to transfer */ + #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + + +/* SAADC_RESULT_AMOUNT: Number of buffer bytes transferred since last START */ + #define SAADC_RESULT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED + event. */ + + #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* ====================================================== Struct SAADC ======================================================= */ +/** + * @brief Analog to Digital Converter + */ + typedef struct { /*!< SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled*/ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[28]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ + __IM uint32_t RESERVED1[28]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending on the + mode, multiple conversions might be needed for a result + to be transferred to RAM.*/ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ + __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ + __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ + __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ + __IM uint32_t RESERVED3[74]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED5[15]; + __IOM NRF_SAADC_TRIM_Type TRIM; /*!< (@ 0x00000440) (unspecified) */ + __IM uint32_t RESERVED6[42]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED7[3]; + __IOM NRF_SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) (unspecified) */ + __IM uint32_t RESERVED8[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should not be + combined with SCAN. The RESOLUTION is applied before + averaging, thus for high OVERSAMPLE a higher RESOLUTION + should be used.*/ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED9[12]; + __IOM NRF_SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ + } NRF_SAADC_Type; /*!< Size = 1596 (0x63C) */ + +/* SAADC_TASKS_START: Start the ADC and prepare the result buffer in RAM */ + #define SAADC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the ADC and prepare the result buffer in RAM */ + #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled */ + #define SAADC_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register. */ + +/* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE + field.*/ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field. */ + #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_STOP: Stop the ADC and terminate any on-going conversion */ + #define SAADC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop the ADC and terminate any on-going conversion */ + #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_TASKS_CALIBRATEOFFSET: Starts offset auto-calibration */ + #define SAADC_TASKS_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CALIBRATEOFFSET register. */ + +/* TASKS_CALIBRATEOFFSET @Bit 0 : Starts offset auto-calibration */ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) + /*!< Bit mask of TASKS_CALIBRATEOFFSET field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Min (0x1UL) /*!< Min enumerator value of TASKS_CALIBRATEOFFSET + field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Max (0x1UL) /*!< Max enumerator value of TASKS_CALIBRATEOFFSET + field.*/ + #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */ + + +/* SAADC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SAADC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */ + #define SAADC_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define SAADC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_SUBSCRIBE_CALIBRATEOFFSET: Subscribe configuration for task CALIBRATEOFFSET */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CALIBRATEOFFSET register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SAADC_EVENTS_STARTED: The ADC has started */ + #define SAADC_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : The ADC has started */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_END: The ADC has filled up the Result buffer */ + #define SAADC_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : The ADC has filled up the Result buffer */ + #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_DONE: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a + result to be transferred to RAM. */ + + #define SAADC_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register. */ + +/* EVENTS_DONE @Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a + result to be transferred to RAM. */ + + #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_DONE field. */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_RESULTDONE: A result is ready to get transferred to RAM. */ + #define SAADC_EVENTS_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESULTDONE register. */ + +/* EVENTS_RESULTDONE @Bit 0 : A result is ready to get transferred to RAM. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask + of EVENTS_RESULTDONE field.*/ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESULTDONE field. */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_CALIBRATEDONE: Calibration is complete */ + #define SAADC_EVENTS_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CALIBRATEDONE register. */ + +/* EVENTS_CALIBRATEDONE @Bit 0 : Calibration is complete */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) + /*!< Bit mask of EVENTS_CALIBRATEDONE field.*/ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CALIBRATEDONE field. */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_EVENTS_STOPPED: The ADC has stopped */ + #define SAADC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : The ADC has stopped */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* SAADC_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define SAADC_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_END: Publish configuration for event END */ + #define SAADC_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_DONE: Publish configuration for event DONE */ + #define SAADC_PUBLISH_DONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DONE will publish to */ + #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_DONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_RESULTDONE: Publish configuration for event RESULTDONE */ + #define SAADC_PUBLISH_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESULTDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RESULTDONE will publish to */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_RESULTDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_CALIBRATEDONE: Publish configuration for event CALIBRATEDONE */ + #define SAADC_PUBLISH_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CALIBRATEDONE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CALIBRATEDONE will publish to */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define SAADC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SAADC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SAADC_INTEN: Enable or disable interrupt */ + #define SAADC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */ + #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTEN_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTEN_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ + +/* END @Bit 1 : Enable or disable interrupt for event END */ + #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTEN_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTEN_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */ + +/* DONE @Bit 2 : Enable or disable interrupt for event DONE */ + #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTEN_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTEN_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ + +/* RESULTDONE @Bit 3 : Enable or disable interrupt for event RESULTDONE */ + #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */ + +/* CALIBRATEDONE @Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ + #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */ + +/* STOPPED @Bit 5 : Enable or disable interrupt for event STOPPED */ + #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* CH0LIMITH @Bit 6 : Enable or disable interrupt for event CH0LIMITH */ + #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH0LIMITL @Bit 7 : Enable or disable interrupt for event CH0LIMITL */ + #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH1LIMITH @Bit 8 : Enable or disable interrupt for event CH1LIMITH */ + #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH1LIMITL @Bit 9 : Enable or disable interrupt for event CH1LIMITL */ + #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH2LIMITH @Bit 10 : Enable or disable interrupt for event CH2LIMITH */ + #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH2LIMITL @Bit 11 : Enable or disable interrupt for event CH2LIMITL */ + #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH3LIMITH @Bit 12 : Enable or disable interrupt for event CH3LIMITH */ + #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH3LIMITL @Bit 13 : Enable or disable interrupt for event CH3LIMITL */ + #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH4LIMITH @Bit 14 : Enable or disable interrupt for event CH4LIMITH */ + #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH4LIMITL @Bit 15 : Enable or disable interrupt for event CH4LIMITL */ + #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH5LIMITH @Bit 16 : Enable or disable interrupt for event CH5LIMITH */ + #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH5LIMITL @Bit 17 : Enable or disable interrupt for event CH5LIMITL */ + #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH6LIMITH @Bit 18 : Enable or disable interrupt for event CH6LIMITH */ + #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH6LIMITL @Bit 19 : Enable or disable interrupt for event CH6LIMITL */ + #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */ + +/* CH7LIMITH @Bit 20 : Enable or disable interrupt for event CH7LIMITH */ + #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */ + +/* CH7LIMITL @Bit 21 : Enable or disable interrupt for event CH7LIMITL */ + #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */ + #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */ + + +/* SAADC_INTENSET: Enable interrupt */ + #define SAADC_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 2 : Write '1' to enable interrupt for event DONE */ + #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTENSET_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTENSET_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESULTDONE @Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ + #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CALIBRATEDONE @Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ + #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 5 : Write '1' to enable interrupt for event STOPPED */ + #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITH @Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ + #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITL @Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ + #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITH @Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ + #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITL @Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ + #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITH @Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ + #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITL @Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ + #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITH @Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ + #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITL @Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ + #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITH @Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ + #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITL @Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ + #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITH @Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ + #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITL @Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ + #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITH @Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ + #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITL @Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ + #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITH @Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ + #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITL @Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ + #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */ + #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SAADC_INTENCLR: Disable interrupt */ + #define SAADC_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SAADC_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SAADC_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DONE @Bit 2 : Write '1' to disable interrupt for event DONE */ + #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ + #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ + #define SAADC_INTENCLR_DONE_Min (0x0UL) /*!< Min enumerator value of DONE field. */ + #define SAADC_INTENCLR_DONE_Max (0x1UL) /*!< Max enumerator value of DONE field. */ + #define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RESULTDONE @Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ + #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of RESULTDONE field. */ + #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CALIBRATEDONE @Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ + #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of CALIBRATEDONE field. */ + #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 5 : Write '1' to disable interrupt for event STOPPED */ + #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITH @Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ + #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Min (0x0UL) /*!< Min enumerator value of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Max (0x1UL) /*!< Max enumerator value of CH0LIMITH field. */ + #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH0LIMITL @Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ + #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Min (0x0UL) /*!< Min enumerator value of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Max (0x1UL) /*!< Max enumerator value of CH0LIMITL field. */ + #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITH @Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ + #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Min (0x0UL) /*!< Min enumerator value of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Max (0x1UL) /*!< Max enumerator value of CH1LIMITH field. */ + #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH1LIMITL @Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ + #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Min (0x0UL) /*!< Min enumerator value of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Max (0x1UL) /*!< Max enumerator value of CH1LIMITL field. */ + #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITH @Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ + #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Min (0x0UL) /*!< Min enumerator value of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Max (0x1UL) /*!< Max enumerator value of CH2LIMITH field. */ + #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH2LIMITL @Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ + #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Min (0x0UL) /*!< Min enumerator value of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Max (0x1UL) /*!< Max enumerator value of CH2LIMITL field. */ + #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITH @Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ + #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Min (0x0UL) /*!< Min enumerator value of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Max (0x1UL) /*!< Max enumerator value of CH3LIMITH field. */ + #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH3LIMITL @Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ + #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Min (0x0UL) /*!< Min enumerator value of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Max (0x1UL) /*!< Max enumerator value of CH3LIMITL field. */ + #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITH @Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ + #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Min (0x0UL) /*!< Min enumerator value of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Max (0x1UL) /*!< Max enumerator value of CH4LIMITH field. */ + #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH4LIMITL @Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ + #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Min (0x0UL) /*!< Min enumerator value of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Max (0x1UL) /*!< Max enumerator value of CH4LIMITL field. */ + #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITH @Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ + #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Min (0x0UL) /*!< Min enumerator value of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Max (0x1UL) /*!< Max enumerator value of CH5LIMITH field. */ + #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH5LIMITL @Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ + #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Min (0x0UL) /*!< Min enumerator value of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Max (0x1UL) /*!< Max enumerator value of CH5LIMITL field. */ + #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITH @Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ + #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Min (0x0UL) /*!< Min enumerator value of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Max (0x1UL) /*!< Max enumerator value of CH6LIMITH field. */ + #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH6LIMITL @Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ + #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Min (0x0UL) /*!< Min enumerator value of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Max (0x1UL) /*!< Max enumerator value of CH6LIMITL field. */ + #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITH @Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ + #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Min (0x0UL) /*!< Min enumerator value of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Max (0x1UL) /*!< Max enumerator value of CH7LIMITH field. */ + #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ + +/* CH7LIMITL @Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ + #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Min (0x0UL) /*!< Min enumerator value of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Max (0x1UL) /*!< Max enumerator value of CH7LIMITL field. */ + #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */ + #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ + #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SAADC_STATUS: Status */ + #define SAADC_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* STATUS @Bit 0 : Status */ + #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ + #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + #define SAADC_STATUS_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field. */ + #define SAADC_STATUS_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field. */ + #define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No on-going conversion. */ + #define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Single conversion in progress. */ + + +/* SAADC_ENABLE: Enable or disable ADC */ + #define SAADC_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable ADC */ + #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */ + #define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */ + + +/* SAADC_RESOLUTION: Resolution configuration */ + #define SAADC_RESOLUTION_ResetValue (0x00000001UL) /*!< Reset value of RESOLUTION register. */ + +/* VAL @Bits 0..2 : Set the resolution */ + #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ + #define SAADC_RESOLUTION_VAL_Min (0x0UL) /*!< Min enumerator value of VAL field. */ + #define SAADC_RESOLUTION_VAL_Max (0x3UL) /*!< Max enumerator value of VAL field. */ + #define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */ + #define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */ + #define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */ + #define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */ + + +/* SAADC_OVERSAMPLE: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before + averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + + #define SAADC_OVERSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of OVERSAMPLE register. */ + +/* OVERSAMPLE @Bits 0..3 : Oversample control */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Min (0x0UL) /*!< Min enumerator value of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Max (0x8UL) /*!< Max enumerator value of OVERSAMPLE field. */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */ + #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */ + + +/* SAADC_SAMPLERATE: Controls normal or continuous sample rate */ + #define SAADC_SAMPLERATE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLERATE register. */ + +/* CC @Bits 0..10 : Capture and compare value. Sample rate is 16 MHz/CC */ + #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ + #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + #define SAADC_SAMPLERATE_CC_Min (0x004UL) /*!< Min value of CC field. */ + #define SAADC_SAMPLERATE_CC_Max (0x7FFUL) /*!< Max size of CC field. */ + +/* MODE @Bit 12 : Select mode for sample rate control */ + #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field. */ + #define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */ + #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPIM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct SPIM_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [SPIM_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_SPIM_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct SPIM_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [SPIM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __OM NRF_SPIM_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000008) Peripheral tasks. */ +} NRF_SPIM_TASKS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ============================================== Struct SPIM_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [SPIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_SPIM_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct SPIM_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [SPIM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM NRF_SPIM_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000008) Subscribe configuration for tasks */ +} NRF_SPIM_SUBSCRIBE_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================ Struct SPIM_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [SPIM_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_SPIM_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct SPIM_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [SPIM_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_SPIM_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIM_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIM_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SPIM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [SPIM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_SPIM_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_SPIM_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_SPIM_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct SPIM_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [SPIM_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_SPIM_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIM_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define SPIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define SPIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct SPIM_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [SPIM_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_SPIM_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIM_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define SPIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define SPIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct SPIM_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [SPIM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_SPIM_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_SPIM_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_SPIM_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================== Struct SPIM_IFTIMING =================================================== */ +/** + * @brief IFTIMING [SPIM_IFTIMING] (unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge of SCK. + When SHORTS.END_START is used, this is also the minimum + duration CSN must stay high between transactions.*/ +} NRF_SPIM_IFTIMING_Type; /*!< Size = 8 (0x008) */ + +/* SPIM_IFTIMING_RXDELAY: Sample delay for input serial data on MISO */ + #define SPIM_IFTIMING_RXDELAY_ResetValue (0x00000002UL) /*!< Reset value of RXDELAY register. */ + +/* RXDELAY @Bits 0..2 : Sample delay for input serial data on MISO. The value specifies the number of SPIM core clock cycles + delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA + = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the + input serial data is sampled on the rising edge of SCK. */ + + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Min (0x0UL) /*!< Min value of RXDELAY field. */ + #define SPIM_IFTIMING_RXDELAY_RXDELAY_Max (0x7UL) /*!< Max size of RXDELAY field. */ + + +/* SPIM_IFTIMING_CSNDUR: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the + minimum duration CSN must stay high between transactions. */ + + #define SPIM_IFTIMING_CSNDUR_ResetValue (0x00000002UL) /*!< Reset value of CSNDUR register. */ + +/* CSNDUR @Bits 0..7 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum + duration CSN must stay high between transactions. The value is specified in number of SPIM core clock + cycles. */ + + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Min (0x00UL) /*!< Min value of CSNDUR field. */ + #define SPIM_IFTIMING_CSNDUR_CSNDUR_Max (0xFFUL) /*!< Max size of CSNDUR field. */ + + + +/* ==================================================== Struct SPIM_PSEL ===================================================== */ +/** + * @brief PSEL [SPIM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ + __IOM uint32_t DCX; /*!< (@ 0x0000000C) Pin select for DCX signal */ + __IOM uint32_t CSN[1]; /*!< (@ 0x00000010) Pin select for CSN */ +} NRF_SPIM_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* SPIM_PSEL_SCK: Pin select for SCK */ + #define SPIM_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Msk (0xFUL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_SCK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_MOSI: Pin select for MOSI signal */ + #define SPIM_PSEL_MOSI_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MOSI register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_MOSI_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Msk (0xFUL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_MOSI_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_MISO: Pin select for MISO signal */ + #define SPIM_PSEL_MISO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MISO register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_MISO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Msk (0xFUL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_MISO_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_DCX: Pin select for DCX signal */ + #define SPIM_PSEL_DCX_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DCX register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_DCX_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Msk (0x1FUL << SPIM_PSEL_DCX_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_DCX_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIM_PSEL_DCX_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Msk (0xFUL << SPIM_PSEL_DCX_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_DCX_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_DCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Msk (0x1UL << SPIM_PSEL_DCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_DCX_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_DCX_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIM_PSEL_CSN: Pin select for CSN */ + #define SPIM_PSEL_CSN_MaxCount (1UL) /*!< Max size of CSN[1] array. */ + #define SPIM_PSEL_CSN_MaxIndex (0UL) /*!< Max index of CSN[1] array. */ + #define SPIM_PSEL_CSN_MinIndex (0UL) /*!< Min index of CSN[1] array. */ + #define SPIM_PSEL_CSN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CSN[1] register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIM_PSEL_CSN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Msk (0xFUL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIM_PSEL_CSN_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct SPIM_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [SPIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_SPIM_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* SPIM_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define SPIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* SPIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct SPIM_DMA_RX ==================================================== */ +/** + * @brief RX [SPIM_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_SPIM_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_SPIM_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* SPIM_DMA_RX_PTR: RAM buffer start address */ + #define SPIM_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIM_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIM_DMA_RX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_RX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_RX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define SPIM_DMA_RX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define SPIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define SPIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_RX_LIST: EasyDMA list type */ + #define SPIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct SPIM_DMA_TX ==================================================== */ +/** + * @brief TX [SPIM_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_SPIM_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* SPIM_DMA_TX_PTR: RAM buffer start address */ + #define SPIM_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIM_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIM_DMA_TX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_TX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_TX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define SPIM_DMA_TX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define SPIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define SPIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIM_DMA_TX_LIST: EasyDMA list type */ + #define SPIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct SPIM_DMA ===================================================== */ +/** + * @brief DMA [SPIM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_SPIM_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_SPIM_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_SPIM_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct SPIM ======================================================= */ +/** + * @brief Serial Peripheral Interface Master with EasyDMA + */ + typedef struct { /*!< SPIM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop SPI transaction */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume SPI transaction */ + __IM uint32_t RESERVED1[5]; + __OM NRF_SPIM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[12]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED3; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED4[5]; + __IOM NRF_SPIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED5[12]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) SPI transaction has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED6[16]; + __IOM NRF_SPIM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ + __IM uint32_t RESERVED8[16]; + __IOM NRF_SPIM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED10[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED11[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED12[10]; + __IOM uint32_t PRESCALER; /*!< (@ 0x0000052C) The prescaler is used to set the SPI frequency. */ + __IM uint32_t RESERVED13[9]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[21]; + __IOM NRF_SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x000005AC) (unspecified) */ + __IOM uint32_t DCXCNT; /*!< (@ 0x000005B4) DCX configuration */ + __IOM uint32_t CSNPOL; /*!< (@ 0x000005B8) Polarity of CSN output */ + __IOM uint32_t CSNCONTROL; /*!< (@ 0x000005BC) Selects which CSN is used, only one CSN can be active + at one time. This register can be safely written during + an ongoing SPI transaction.*/ + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have been + transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT*/ + __IM uint32_t RESERVED15[15]; + __IOM NRF_SPIM_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED16[59]; + __IOM NRF_SPIM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_SPIM_Type; /*!< Size = 1884 (0x75C) */ + +/* SPIM_TASKS_START: Start SPI transaction */ + #define SPIM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start SPI transaction */ + #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_STOP: Stop SPI transaction */ + #define SPIM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop SPI transaction */ + #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_SUSPEND: Suspend SPI transaction */ + #define SPIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend SPI transaction */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_TASKS_RESUME: Resume SPI transaction */ + #define SPIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume SPI transaction */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIM_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SPIM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define SPIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define SPIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define SPIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIM_EVENTS_STARTED: SPI transaction has started */ + #define SPIM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register. */ + +/* EVENTS_STARTED @Bit 0 : SPI transaction has started */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of + EVENTS_STARTED field.*/ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field. */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_STOPPED: SPI transaction has stopped */ + #define SPIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : SPI transaction has stopped */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_EVENTS_END: End of RXD buffer and TXD buffer reached */ + #define SPIM_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : End of RXD buffer and TXD buffer reached */ + #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIM_PUBLISH_STARTED: Publish configuration for event STARTED */ + #define SPIM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */ + #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_STARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define SPIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_PUBLISH_END: Publish configuration for event END */ + #define SPIM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIM_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIM_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIM_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIM_SHORTS: Shortcuts between local events and tasks */ + #define SPIM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* END_START @Bit 17 : Shortcut between event END and task START */ + #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ + #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ + #define SPIM_SHORTS_END_START_Min (0x0UL) /*!< Min enumerator value of END_START field. */ + #define SPIM_SHORTS_END_START_Max (0x1UL) /*!< Max enumerator value of END_START field. */ + #define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* SPIM_INTENSET: Enable interrupt */ + #define SPIM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */ + #define SPIM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SPIM_INTENSET_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SPIM_INTENSET_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to enable interrupt for event END */ + #define SPIM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ + #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define SPIM_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Msk (0x1UL << SPIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIM_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define SPIM_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Msk (0x1UL << SPIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIM_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define SPIM_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define SPIM_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define SPIM_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define SPIM_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define SPIM_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define SPIM_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Msk (0x1UL << SPIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIM_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define SPIM_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Msk (0x1UL << SPIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIM_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define SPIM_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIM_INTENCLR: Disable interrupt */ + #define SPIM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */ + #define SPIM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Min (0x0UL) /*!< Min enumerator value of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Max (0x1UL) /*!< Max enumerator value of STARTED field. */ + #define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* END @Bit 2 : Write '1' to disable interrupt for event END */ + #define SPIM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ + #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SPIM_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIM_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define SPIM_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Msk (0x1UL << SPIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIM_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define SPIM_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Msk (0x1UL << SPIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIM_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define SPIM_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define SPIM_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIM_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define SPIM_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIM_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define SPIM_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIM_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define SPIM_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIM_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define SPIM_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Msk (0x1UL << SPIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIM_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define SPIM_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Msk (0x1UL << SPIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIM_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define SPIM_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIM_ENABLE: Enable SPIM */ + #define SPIM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable SPIM */ + #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Max (0x7UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */ + #define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */ + + +/* SPIM_PRESCALER: The prescaler is used to set the SPI frequency. */ + #define SPIM_PRESCALER_ResetValue (0x00000040UL) /*!< Reset value of PRESCALER register. */ + +/* DIVISOR @Bits 0..6 : Core clock to SCK divisor */ + #define SPIM_PRESCALER_DIVISOR_Pos (0UL) /*!< Position of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Msk (0x7FUL << SPIM_PRESCALER_DIVISOR_Pos) /*!< Bit mask of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Min (0x02UL) /*!< Min value of DIVISOR field. */ + #define SPIM_PRESCALER_DIVISOR_Max (0x7EUL) /*!< Max size of DIVISOR field. */ + + +/* SPIM_CONFIG: Configuration register */ + #define SPIM_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ORDER @Bit 0 : Bit order */ + #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ + #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ + #define SPIM_CONFIG_ORDER_Min (0x0UL) /*!< Min enumerator value of ORDER field. */ + #define SPIM_CONFIG_ORDER_Max (0x1UL) /*!< Max enumerator value of ORDER field. */ + #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ + #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ + +/* CPHA @Bit 1 : Serial clock (SCK) phase */ + #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ + #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ + #define SPIM_CONFIG_CPHA_Min (0x0UL) /*!< Min enumerator value of CPHA field. */ + #define SPIM_CONFIG_CPHA_Max (0x1UL) /*!< Max enumerator value of CPHA field. */ + #define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ + #define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* CPOL @Bit 2 : Serial clock (SCK) polarity */ + #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ + #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ + #define SPIM_CONFIG_CPOL_Min (0x0UL) /*!< Min enumerator value of CPOL field. */ + #define SPIM_CONFIG_CPOL_Max (0x1UL) /*!< Max enumerator value of CPOL field. */ + #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ + #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ + + +/* SPIM_DCXCNT: DCX configuration */ + #define SPIM_DCXCNT_ResetValue (0x00000000UL) /*!< Reset value of DCXCNT register. */ + +/* DCXCNT @Bits 0..3 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be + low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates + that all bytes are command bytes. */ + + #define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Min (0x0UL) /*!< Min value of DCXCNT field. */ + #define SPIM_DCXCNT_DCXCNT_Max (0xFUL) /*!< Max size of DCXCNT field. */ + + +/* SPIM_CSNPOL: Polarity of CSN output */ + #define SPIM_CSNPOL_ResetValue (0x00000000UL) /*!< Reset value of CSNPOL register. */ + +/* CSNPOL0 @Bit 0 : Polarity of CSN output */ + #define SPIM_CSNPOL_CSNPOL0_Pos (0UL) /*!< Position of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Msk (0x1UL << SPIM_CSNPOL_CSNPOL0_Pos) /*!< Bit mask of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Min (0x0UL) /*!< Min enumerator value of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_Max (0x1UL) /*!< Max enumerator value of CSNPOL0 field. */ + #define SPIM_CSNPOL_CSNPOL0_LOW (0x0UL) /*!< Active low (idle state high) */ + #define SPIM_CSNPOL_CSNPOL0_HIGH (0x1UL) /*!< Active high (idle state low) */ + + +/* SPIM_CSNCONTROL: Selects which CSN is used, only one CSN can be active at one time. This register can be safely written + during an ongoing SPI transaction. */ + + #define SPIM_CSNCONTROL_ResetValue (0x00000000UL) /*!< Reset value of CSNCONTROL register. */ + +/* CSN @Bit 0 : CSN Number. */ + #define SPIM_CSNCONTROL_CSN_Pos (0UL) /*!< Position of CSN field. */ + #define SPIM_CSNCONTROL_CSN_Msk (0x1UL << SPIM_CSNCONTROL_CSN_Pos) /*!< Bit mask of CSN field. */ + + +/* SPIM_ORC: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT */ + + #define SPIM_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than + TXD.MAXCNT. */ + + #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPIS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct SPIS_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [SPIS_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_SPIS_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct SPIS_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [SPIS_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __OM NRF_SPIS_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000008) Peripheral tasks. */ +} NRF_SPIS_TASKS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ============================================== Struct SPIS_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [SPIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_SPIS_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct SPIS_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [SPIS_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IM uint32_t RESERVED[2]; + __IOM NRF_SPIS_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000008) Subscribe configuration for tasks */ +} NRF_SPIS_SUBSCRIBE_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ================================================ Struct SPIS_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [SPIS_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_SPIS_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct SPIS_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [SPIS_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_SPIS_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define SPIS_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define SPIS_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define SPIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct SPIS_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [SPIS_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_SPIS_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_SPIS_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_SPIS_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct SPIS_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [SPIS_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_SPIS_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* SPIS_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define SPIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define SPIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct SPIS_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [SPIS_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_SPIS_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* SPIS_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define SPIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define SPIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct SPIS_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [SPIS_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_SPIS_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_SPIS_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_SPIS_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct SPIS_PSEL ===================================================== */ +/** + * @brief PSEL [SPIS_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IM uint32_t RESERVED; + __IOM uint32_t CSN; /*!< (@ 0x00000010) Pin select for CSN signal */ +} NRF_SPIS_PSEL_Type; /*!< Size = 20 (0x014) */ + +/* SPIS_PSEL_SCK: Pin select for SCK */ + #define SPIS_PSEL_SCK_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCK register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_SCK_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Msk (0xFUL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_SCK_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_MISO: Pin select for MISO signal */ + #define SPIS_PSEL_MISO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MISO register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_MISO_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Msk (0xFUL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_MISO_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_MOSI: Pin select for MOSI signal */ + #define SPIS_PSEL_MOSI_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MOSI register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_MOSI_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Msk (0xFUL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_MOSI_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* SPIS_PSEL_CSN: Pin select for CSN signal */ + #define SPIS_PSEL_CSN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CSN register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define SPIS_PSEL_CSN_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Msk (0xFUL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define SPIS_PSEL_CSN_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct SPIS_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [SPIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_SPIS_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* SPIS_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define SPIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* SPIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct SPIS_DMA_RX ==================================================== */ +/** + * @brief RX [SPIS_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_SPIS_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_SPIS_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* SPIS_DMA_RX_PTR: RAM buffer start address */ + #define SPIS_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIS_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIS_DMA_RX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_RX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define SPIS_DMA_RX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define SPIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define SPIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_RX_LIST: EasyDMA list type */ + #define SPIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct SPIS_DMA_TX ==================================================== */ +/** + * @brief TX [SPIS_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_SPIS_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* SPIS_DMA_TX_PTR: RAM buffer start address */ + #define SPIS_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define SPIS_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define SPIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* SPIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define SPIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define SPIS_DMA_TX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* SPIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define SPIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_TX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define SPIS_DMA_TX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define SPIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define SPIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define SPIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define SPIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* SPIS_DMA_TX_LIST: EasyDMA list type */ + #define SPIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define SPIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define SPIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define SPIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* SPIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct SPIS_DMA ===================================================== */ +/** + * @brief DMA [SPIS_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_SPIS_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_SPIS_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_SPIS_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct SPIS ======================================================= */ +/** + * @brief SPI Slave + */ + typedef struct { /*!< SPIS Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000014) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000018) Release SPI semaphore, enabling the SPI slave to + acquire it*/ + __IM uint32_t RESERVED1[3]; + __OM NRF_SPIS_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[17]; + __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x00000094) Subscribe configuration for task ACQUIRE */ + __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x00000098) Subscribe configuration for task RELEASE */ + __IM uint32_t RESERVED3[3]; + __IOM NRF_SPIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[13]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000118) Semaphore acquired */ + __IM uint32_t RESERVED6[12]; + __IOM NRF_SPIS_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED7[4]; + __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ + __IM uint32_t RESERVED8[4]; + __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x00000198) Publish configuration for event ACQUIRED */ + __IM uint32_t RESERVED9[12]; + __IOM NRF_SPIS_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED10[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED11[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED12[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED13[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED14[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED15[20]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED16; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case of an + ignored transaction.*/ + __IM uint32_t RESERVED17[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ + __IM uint32_t RESERVED18[15]; + __IOM NRF_SPIS_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED19[59]; + __IOM NRF_SPIS_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_SPIS_Type; /*!< Size = 1884 (0x75C) */ + +/* SPIS_TASKS_ACQUIRE: Acquire SPI semaphore */ + #define SPIS_TASKS_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACQUIRE register. */ + +/* TASKS_ACQUIRE @Bit 0 : Acquire SPI semaphore */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE + field.*/ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACQUIRE field. */ + #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_TASKS_RELEASE: Release SPI semaphore, enabling the SPI slave to acquire it */ + #define SPIS_TASKS_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RELEASE register. */ + +/* TASKS_RELEASE @Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE + field.*/ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Min (0x1UL) /*!< Min enumerator value of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Max (0x1UL) /*!< Max enumerator value of TASKS_RELEASE field. */ + #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */ + + +/* SPIS_SUBSCRIBE_ACQUIRE: Subscribe configuration for task ACQUIRE */ + #define SPIS_SUBSCRIBE_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACQUIRE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ACQUIRE will subscribe to */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_SUBSCRIBE_RELEASE: Subscribe configuration for task RELEASE */ + #define SPIS_SUBSCRIBE_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RELEASE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RELEASE will subscribe to */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* SPIS_EVENTS_END: Granted transaction completed */ + #define SPIS_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register. */ + +/* EVENTS_END @Bit 0 : Granted transaction completed */ + #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Min (0x0UL) /*!< Min enumerator value of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_Max (0x1UL) /*!< Max enumerator value of EVENTS_END field. */ + #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_EVENTS_ACQUIRED: Semaphore acquired */ + #define SPIS_EVENTS_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACQUIRED register. */ + +/* EVENTS_ACQUIRED @Bit 0 : Semaphore acquired */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of + EVENTS_ACQUIRED field.*/ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACQUIRED field. */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */ + + +/* SPIS_PUBLISH_END: Publish configuration for event END */ + #define SPIS_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_PUBLISH_ACQUIRED: Publish configuration for event ACQUIRED */ + #define SPIS_PUBLISH_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACQUIRED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ACQUIRED will publish to */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SPIS_PUBLISH_ACQUIRED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* SPIS_SHORTS: Shortcuts between local events and tasks */ + #define SPIS_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* END_ACQUIRE @Bit 2 : Shortcut between event END and task ACQUIRE */ + #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Min (0x0UL) /*!< Min enumerator value of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of END_ACQUIRE field. */ + #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* SPIS_INTENSET: Enable interrupt */ + #define SPIS_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* END @Bit 1 : Write '1' to enable interrupt for event END */ + #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ + #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_INTENSET_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_INTENSET_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACQUIRED @Bit 6 : Write '1' to enable interrupt for event ACQUIRED */ + #define SPIS_INTENSET_ACQUIRED_Pos (6UL) /*!< Position of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of ACQUIRED field. */ + #define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define SPIS_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Msk (0x1UL << SPIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIS_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define SPIS_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Msk (0x1UL << SPIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIS_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define SPIS_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define SPIS_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define SPIS_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define SPIS_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define SPIS_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define SPIS_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Msk (0x1UL << SPIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIS_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define SPIS_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Msk (0x1UL << SPIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIS_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define SPIS_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define SPIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIS_INTENCLR: Disable interrupt */ + #define SPIS_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* END @Bit 1 : Write '1' to disable interrupt for event END */ + #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ + #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ + #define SPIS_INTENCLR_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define SPIS_INTENCLR_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ACQUIRED @Bit 6 : Write '1' to disable interrupt for event ACQUIRED */ + #define SPIS_INTENCLR_ACQUIRED_Pos (6UL) /*!< Position of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of ACQUIRED field. */ + #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define SPIS_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Msk (0x1UL << SPIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define SPIS_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define SPIS_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Msk (0x1UL << SPIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define SPIS_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define SPIS_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define SPIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define SPIS_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define SPIS_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define SPIS_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define SPIS_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define SPIS_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define SPIS_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define SPIS_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define SPIS_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define SPIS_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Msk (0x1UL << SPIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define SPIS_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define SPIS_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Msk (0x1UL << SPIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define SPIS_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define SPIS_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define SPIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define SPIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPIS_SEMSTAT: Semaphore status register */ + #define SPIS_SEMSTAT_ResetValue (0x00000001UL) /*!< Reset value of SEMSTAT register. */ + +/* SEMSTAT @Bits 0..1 : Semaphore status */ + #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Min (0x0UL) /*!< Min enumerator value of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Max (0x3UL) /*!< Max enumerator value of SEMSTAT field. */ + #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */ + #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */ + #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */ + #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + + +/* SPIS_STATUS: Status from last transaction */ + #define SPIS_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* OVERREAD @Bit 0 : TX buffer over-read detected, and prevented */ + #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Min (0x0UL) /*!< Min enumerator value of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_Max (0x1UL) /*!< Max enumerator value of OVERREAD field. */ + #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */ + #define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */ + #define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */ + +/* OVERFLOW @Bit 1 : RX buffer overflow detected, and prevented */ + #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */ + #define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */ + #define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */ + + +/* SPIS_ENABLE: Enable SPI slave */ + #define SPIS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable SPI slave */ + #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Max (0x2UL) /*!< Max enumerator value of ENABLE field. */ + #define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */ + #define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */ + + +/* SPIS_CONFIG: Configuration register */ + #define SPIS_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ORDER @Bit 0 : Bit order */ + #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ + #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ + #define SPIS_CONFIG_ORDER_Min (0x0UL) /*!< Min enumerator value of ORDER field. */ + #define SPIS_CONFIG_ORDER_Max (0x1UL) /*!< Max enumerator value of ORDER field. */ + #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ + #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ + +/* CPHA @Bit 1 : Serial clock (SCK) phase */ + #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ + #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ + #define SPIS_CONFIG_CPHA_Min (0x0UL) /*!< Min enumerator value of CPHA field. */ + #define SPIS_CONFIG_CPHA_Max (0x1UL) /*!< Max enumerator value of CPHA field. */ + #define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ + #define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* CPOL @Bit 2 : Serial clock (SCK) polarity */ + #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ + #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ + #define SPIS_CONFIG_CPOL_Min (0x0UL) /*!< Min enumerator value of CPOL field. */ + #define SPIS_CONFIG_CPOL_Max (0x1UL) /*!< Max enumerator value of CPOL field. */ + #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ + #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ + + +/* SPIS_DEF: Default character. Character clocked out in case of an ignored transaction. */ + #define SPIS_DEF_ResetValue (0x00000000UL) /*!< Reset value of DEF register. */ + +/* DEF @Bits 0..7 : Default character. Character clocked out in case of an ignored transaction. */ + #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ + #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + + +/* SPIS_ORC: Over-read character */ + #define SPIS_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ + #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SPU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================= Struct SPU_PERIPHACCERR ================================================= */ +/** + * @brief PERIPHACCERR [SPU_PERIPHACCERR] (unspecified) + */ +typedef struct { + __IM uint32_t ADDRESS; /*!< (@ 0x00000000) Address of the transaction that caused first error. */ + __IM uint32_t INFO; /*!< (@ 0x00000004) Information about the transaction that caused first + error.*/ +} NRF_SPU_PERIPHACCERR_Type; /*!< Size = 8 (0x008) */ + +/* SPU_PERIPHACCERR_ADDRESS: Address of the transaction that caused first error. */ + #define SPU_PERIPHACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..15 : Address */ + #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk (0xFFFFUL << SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* SPU_PERIPHACCERR_INFO: Information about the transaction that caused first error. */ + #define SPU_PERIPHACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register. */ + +/* OWNERID @Bits 0..3 : OWNERID */ + #define SPU_PERIPHACCERR_INFO_OWNERID_Pos (0UL) /*!< Position of OWNERID field. */ + #define SPU_PERIPHACCERR_INFO_OWNERID_Msk (0xFUL << SPU_PERIPHACCERR_INFO_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + + + +/* ==================================================== Struct SPU_PERIPH ==================================================== */ +/** + * @brief PERIPH [SPU_PERIPH] (unspecified) + */ +typedef struct { + __IOM uint32_t PERM; /*!< (@ 0x00000000) Get and set the applicable access permissions for the + peripheral slave index n*/ +} NRF_SPU_PERIPH_Type; /*!< Size = 4 (0x004) */ + #define SPU_PERIPH_MaxCount (32UL) /*!< Size of PERIPH[32] array. */ + #define SPU_PERIPH_MaxIndex (31UL) /*!< Max index of PERIPH[32] array. */ + #define SPU_PERIPH_MinIndex (0UL) /*!< Min index of PERIPH[32] array. */ + +/* SPU_PERIPH_PERM: Get and set the applicable access permissions for the peripheral slave index n */ + #define SPU_PERIPH_PERM_ResetValue (0x8000000AUL) /*!< Reset value of PERM register. */ + +/* SECUREMAPPING @Bits 0..1 : Read capabilities for TrustZone Cortex-M secure attribute */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPH_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Min (0x0UL) /*!< Min enumerator value of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Max (0x3UL) /*!< Max enumerator value of SECUREMAPPING field. */ + #define SPU_PERIPH_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ + #define SPU_PERIPH_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */ + #define SPU_PERIPH_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is + defined by the PERIPH[n].PERM register*/ + #define SPU_PERIPH_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. */ + +/* DMA @Bits 2..3 : Read the peripheral DMA capabilities */ + #define SPU_PERIPH_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Msk (0x3UL << SPU_PERIPH_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Min (0x0UL) /*!< Min enumerator value of DMA field. */ + #define SPU_PERIPH_PERM_DMA_Max (0x2UL) /*!< Max enumerator value of DMA field. */ + #define SPU_PERIPH_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */ + #define SPU_PERIPH_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same + security attribute as assigned to the peripheral*/ + #define SPU_PERIPH_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security + attribute than the one assigned to the peripheral*/ + +/* SECATTR @Bit 4 : Peripheral security mapping */ + #define SPU_PERIPH_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Msk (0x1UL << SPU_PERIPH_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_PERIPH_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */ + #define SPU_PERIPH_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure + peripheral address space. If SECUREMAPPING == Split: Peripheral is + mapped in non-secure and secure peripheral address space.*/ + +/* DMASEC @Bit 5 : Security attribution for the DMA transfer */ + #define SPU_PERIPH_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Msk (0x1UL << SPU_PERIPH_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Min (0x0UL) /*!< Min enumerator value of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Max (0x1UL) /*!< Max enumerator value of DMASEC field. */ + #define SPU_PERIPH_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute + set*/ + #define SPU_PERIPH_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure + attribute set*/ + +/* LOCK @Bit 8 : Register lock */ + #define SPU_PERIPH_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Msk (0x1UL << SPU_PERIPH_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_PERIPH_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ + #define SPU_PERIPH_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Peripheral owner ID */ + #define SPU_PERIPH_PERM_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_PERIPH_PERM_OWNERID_Msk (0xFUL << SPU_PERIPH_PERM_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_PERIPH_PERM_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_PERIPH_PERM_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + +/* OWNERPROG @Bit 30 : Indicates if OWNERID is programmable or not */ + #define SPU_PERIPH_PERM_OWNERPROG_Pos (30UL) /*!< Position of OWNERPROG field. */ + #define SPU_PERIPH_PERM_OWNERPROG_Msk (0x1UL << SPU_PERIPH_PERM_OWNERPROG_Pos) /*!< Bit mask of OWNERPROG field. */ + #define SPU_PERIPH_PERM_OWNERPROG_Min (0x0UL) /*!< Min enumerator value of OWNERPROG field. */ + #define SPU_PERIPH_PERM_OWNERPROG_Max (0x1UL) /*!< Max enumerator value of OWNERPROG field. */ + #define SPU_PERIPH_PERM_OWNERPROG_NotProgrammable (0x0UL) /*!< OWNERID is not programmable */ + #define SPU_PERIPH_PERM_OWNERPROG_Programmable (0x1UL) /*!< OWNERID is programmable */ + +/* PRESENT @Bit 31 : Indicates if a peripheral is present with peripheral slave index n */ + #define SPU_PERIPH_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Msk (0x1UL << SPU_PERIPH_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define SPU_PERIPH_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */ + #define SPU_PERIPH_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */ + + + +/* ================================================= Struct SPU_FEATURE_IPCT ================================================= */ +/** + * @brief IPCT [SPU_FEATURE_IPCT] (unspecified) + */ +typedef struct { + __IOM uint32_t CH[24]; /*!< (@ 0x00000000) Configuration of features for channel n of IPCT */ + __IOM uint32_t INTERRUPT[8]; /*!< (@ 0x00000060) Configuration of features for interrupt n of IPCT */ +} NRF_SPU_FEATURE_IPCT_Type; /*!< Size = 128 (0x080) */ + +/* SPU_FEATURE_IPCT_CH: Configuration of features for channel n of IPCT */ + #define SPU_FEATURE_IPCT_CH_MaxCount (24UL) /*!< Max size of CH[24] array. */ + #define SPU_FEATURE_IPCT_CH_MaxIndex (23UL) /*!< Max index of CH[24] array. */ + #define SPU_FEATURE_IPCT_CH_MinIndex (0UL) /*!< Min index of CH[24] array. */ + #define SPU_FEATURE_IPCT_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_IPCT_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_IPCT_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_IPCT_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_IPCT_CH_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_IPCT_CH_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_IPCT_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_IPCT_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_IPCT_CH_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_IPCT_CH_LOCK_Msk (0x1UL << SPU_FEATURE_IPCT_CH_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_IPCT_CH_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_IPCT_CH_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_IPCT_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_IPCT_CH_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_IPCT_CH_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_IPCT_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_IPCT_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_IPCT_CH_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_IPCT_CH_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_IPCT_INTERRUPT: Configuration of features for interrupt n of IPCT */ + #define SPU_FEATURE_IPCT_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array. */ + #define SPU_FEATURE_IPCT_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array. */ + #define SPU_FEATURE_IPCT_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array. */ + #define SPU_FEATURE_IPCT_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================ Struct SPU_FEATURE_DPPIC ================================================= */ +/** + * @brief DPPIC [SPU_FEATURE_DPPIC] (unspecified) + */ +typedef struct { + __IOM uint32_t CH[24]; /*!< (@ 0x00000000) Configuration of features for channel n of DPPIC */ + __IOM uint32_t CHG[8]; /*!< (@ 0x00000060) Configuration of features for channel group n of DPPIC*/ +} NRF_SPU_FEATURE_DPPIC_Type; /*!< Size = 128 (0x080) */ + +/* SPU_FEATURE_DPPIC_CH: Configuration of features for channel n of DPPIC */ + #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL) /*!< Max size of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL) /*!< Max index of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL) /*!< Min index of CH[24] array. */ + #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_DPPIC_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_DPPIC_CH_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_DPPIC_CH_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_DPPIC_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CH_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CH_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_DPPIC_CHG: Configuration of features for channel group n of DPPIC */ + #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL) /*!< Max size of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL) /*!< Max index of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL) /*!< Min index of CHG[8] array. */ + #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_DPPIC_CHG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_DPPIC_CHG_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_DPPIC_CHG_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CHG_OWNERID_Msk (0xFUL << SPU_FEATURE_DPPIC_CHG_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CHG_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_DPPIC_CHG_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================ Struct SPU_FEATURE_GPIOTE ================================================ */ +/** + * @brief GPIOTE [SPU_FEATURE_GPIOTE] (unspecified) + */ +typedef struct { + __IOM uint32_t CH[8]; /*!< (@ 0x00000000) Configuration of features for channel o of GPIOTE[n] */ + __IOM uint32_t INTERRUPT[8]; /*!< (@ 0x00000020) Configuration of features for interrupt o of GPIOTE[n]*/ +} NRF_SPU_FEATURE_GPIOTE_Type; /*!< Size = 64 (0x040) */ + #define SPU_FEATURE_GPIOTE_MaxCount (2UL) /*!< Size of GPIOTE[2] array. */ + #define SPU_FEATURE_GPIOTE_MaxIndex (1UL) /*!< Max index of GPIOTE[2] array. */ + #define SPU_FEATURE_GPIOTE_MinIndex (0UL) /*!< Min index of GPIOTE[2] array. */ + +/* SPU_FEATURE_GPIOTE_CH: Configuration of features for channel o of GPIOTE[n] */ + #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL) /*!< Max size of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL) /*!< Max index of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL) /*!< Min index of CH[8] array. */ + #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIOTE_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIOTE_CH_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GPIOTE_CH_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GPIOTE_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIOTE_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_GPIOTE_CH_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GPIOTE_CH_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_GPIOTE_INTERRUPT: Configuration of features for interrupt o of GPIOTE[n] */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================= Struct SPU_FEATURE_GPIO ================================================= */ +/** + * @brief GPIO [SPU_FEATURE_GPIO] (unspecified) + */ +typedef struct { + __IOM uint32_t PIN[32]; /*!< (@ 0x00000000) Configuration of features for GPIO[n] PIN[o] */ +} NRF_SPU_FEATURE_GPIO_Type; /*!< Size = 128 (0x080) */ + #define SPU_FEATURE_GPIO_MaxCount (14UL) /*!< Size of GPIO[14] array. */ + #define SPU_FEATURE_GPIO_MaxIndex (13UL) /*!< Max index of GPIO[14] array. */ + #define SPU_FEATURE_GPIO_MinIndex (0UL) /*!< Min index of GPIO[14] array. */ + +/* SPU_FEATURE_GPIO_PIN: Configuration of features for GPIO[n] PIN[o] */ + #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL) /*!< Max size of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL) /*!< Max index of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL) /*!< Min index of PIN[32] array. */ + #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00000000UL) /*!< Reset value of PIN[32] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GPIO_PIN_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GPIO_PIN_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GPIO_PIN_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GPIO_PIN_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIO_PIN_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_GPIO_PIN_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GPIO_PIN_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================= Struct SPU_FEATURE_GRTC ================================================= */ +/** + * @brief GRTC [SPU_FEATURE_GRTC] (unspecified) + */ +typedef struct { + __IOM uint32_t CC[16]; /*!< (@ 0x00000000) Configuration of features for CC n of GRTC */ + __IM uint32_t RESERVED[13]; + __IOM uint32_t PWMCONFIG; /*!< (@ 0x00000074) Configuration of feature for PWMCONFIG of GRTC */ + __IOM uint32_t CLK; /*!< (@ 0x00000078) Configuration of features for CLKOUT/CLKCFG of GRTC */ + __IOM uint32_t SYSCOUNTER; /*!< (@ 0x0000007C) Configuration of features for SYSCOUNTERL/SYSCOUNTERH + of GRTC*/ + __IOM uint32_t INTERRUPT[13]; /*!< (@ 0x00000080) Configuration of features for interrupt n of GRTC */ +} NRF_SPU_FEATURE_GRTC_Type; /*!< Size = 180 (0x0B4) */ + +/* SPU_FEATURE_GRTC_CC: Configuration of features for CC n of GRTC */ + #define SPU_FEATURE_GRTC_CC_MaxCount (16UL) /*!< Max size of CC[16] array. */ + #define SPU_FEATURE_GRTC_CC_MaxIndex (15UL) /*!< Max index of CC[16] array. */ + #define SPU_FEATURE_GRTC_CC_MinIndex (0UL) /*!< Min index of CC[16] array. */ + #define SPU_FEATURE_GRTC_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[16] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CC_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CC_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_CC_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_CC_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CC_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CC_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_CC_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GRTC_CC_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GRTC_CC_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_CC_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_GRTC_CC_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GRTC_CC_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_GRTC_PWMCONFIG: Configuration of feature for PWMCONFIG of GRTC */ + #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00000000UL) /*!< Reset value of PWMCONFIG register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GRTC_PWMCONFIG_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_PWMCONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_GRTC_PWMCONFIG_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GRTC_PWMCONFIG_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_GRTC_CLK: Configuration of features for CLKOUT/CLKCFG of GRTC */ + #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00000000UL) /*!< Reset value of CLK register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_CLK_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_CLK_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GRTC_CLK_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GRTC_CLK_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_CLK_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_GRTC_CLK_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GRTC_CLK_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_GRTC_SYSCOUNTER: Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTER register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_GRTC_INTERRUPT: Configuration of features for interrupt n of GRTC */ + #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (13UL) /*!< Max size of INTERRUPT[13] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (12UL) /*!< Max index of INTERRUPT[13] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[13] array. */ + #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[13] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================ Struct SPU_FEATURE_MRAMC ================================================= */ +/** + * @brief MRAMC [SPU_FEATURE_MRAMC] (unspecified) + */ +typedef struct { + __IOM uint32_t WAITSTATES; /*!< (@ 0x00000000) Configuration of features for WAITSTATES of MRAMC [n] */ + __IOM uint32_t AUTODPOWERDOWN; /*!< (@ 0x00000004) Configuration of features for POWER.AUTODPOWERDOWN of + MRAMC [n]*/ + __IOM uint32_t READY; /*!< (@ 0x00000008) Configuration of features for READY and READYNEXT of + MRAMC [n]*/ +} NRF_SPU_FEATURE_MRAMC_Type; /*!< Size = 12 (0x00C) */ + #define SPU_FEATURE_MRAMC_MaxCount (2UL) /*!< Size of MRAMC[2] array. */ + #define SPU_FEATURE_MRAMC_MaxIndex (1UL) /*!< Max index of MRAMC[2] array. */ + #define SPU_FEATURE_MRAMC_MinIndex (0UL) /*!< Min index of MRAMC[2] array. */ + +/* SPU_FEATURE_MRAMC_WAITSTATES: Configuration of features for WAITSTATES of MRAMC [n] */ + #define SPU_FEATURE_MRAMC_WAITSTATES_ResetValue (0x00000000UL) /*!< Reset value of WAITSTATES register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Msk (0x1UL << SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Pos) /*!< Bit mask of SECATTR + field.*/ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_MRAMC_WAITSTATES_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Msk (0x1UL << SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_MRAMC_WAITSTATES_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Msk (0xFUL << SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Pos) /*!< Bit mask of OWNERID + field.*/ + #define SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_MRAMC_WAITSTATES_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_MRAMC_AUTODPOWERDOWN: Configuration of features for POWER.AUTODPOWERDOWN of MRAMC [n] */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_ResetValue (0x00000000UL) /*!< Reset value of AUTODPOWERDOWN register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Msk (0x1UL << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Pos) /*!< Bit mask of + SECATTR field.*/ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Msk (0x1UL << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset*/ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Msk (0xFUL << SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Pos) /*!< Bit mask of + OWNERID field.*/ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_MRAMC_AUTODPOWERDOWN_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_MRAMC_READY: Configuration of features for READY and READYNEXT of MRAMC [n] */ + #define SPU_FEATURE_MRAMC_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_Msk (0x1UL << SPU_FEATURE_MRAMC_READY_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_MRAMC_READY_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Msk (0x1UL << SPU_FEATURE_MRAMC_READY_LOCK_Pos) /*!< Bit mask of LOCK field. */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_MRAMC_READY_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset */ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_MRAMC_READY_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_MRAMC_READY_OWNERID_Msk (0xFUL << SPU_FEATURE_MRAMC_READY_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define SPU_FEATURE_MRAMC_READY_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_MRAMC_READY_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* =========================================== Struct SPU_FEATURE_BELLS_PROCESSOR ============================================ */ +/** + * @brief PROCESSOR [SPU_FEATURE_BELLS_PROCESSOR] (unspecified) + */ +typedef struct { + __IOM uint32_t TASKS[16]; /*!< (@ 0x00000000) Configuration of features for tasks pair [(o * 2) + 1:o + * 2] of Processor ID n*/ + __IOM uint32_t EVENTS[16]; /*!< (@ 0x00000040) Configuration of features for events pair [(o * 2) + + 1:o * 2] of Processor ID n*/ + __IOM uint32_t INTERRUPT[16]; /*!< (@ 0x00000080) Configuration of features for interrupt register pair + [(o * 2) + 1:o * 2] of Processor ID n*/ +} NRF_SPU_FEATURE_BELLS_PROCESSOR_Type; /*!< Size = 192 (0x0C0) */ + #define SPU_FEATURE_BELLS_PROCESSOR_MaxCount (8UL) /*!< Size of PROCESSOR[8] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_MaxIndex (7UL) /*!< Max index of PROCESSOR[8] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_MinIndex (0UL) /*!< Min index of PROCESSOR[8] array. */ + +/* SPU_FEATURE_BELLS_PROCESSOR_TASKS: Configuration of features for tasks pair [(o * 2) + 1:o * 2] of Processor ID n */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_MaxCount (16UL) /*!< Max size of TASKS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_MaxIndex (15UL) /*!< Max index of TASKS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_MinIndex (0UL) /*!< Min index of TASKS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_ResetValue (0x00000000UL) /*!< Reset value of TASKS[16] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Pos) /*!< Bit mask + of SECATTR field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Pos) /*!< Bit mask of LOCK + field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next + reset*/ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Msk (0xFUL << SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Pos) /*!< Bit mask + of OWNERID field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_TASKS_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_BELLS_PROCESSOR_EVENTS: Configuration of features for events pair [(o * 2) + 1:o * 2] of Processor ID n */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_MaxCount (16UL) /*!< Max size of EVENTS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_MaxIndex (15UL) /*!< Max index of EVENTS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_MinIndex (0UL) /*!< Min index of EVENTS[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS[16] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Pos) /*!< Bit mask + of SECATTR field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Pos) /*!< Bit mask of + LOCK field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next + reset*/ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Msk (0xFUL << SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Pos) /*!< Bit mask + of OWNERID field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_EVENTS_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + +/* SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT: Configuration of features for interrupt register pair [(o * 2) + 1:o * 2] of Processor + ID n */ + + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_MaxCount (16UL) /*!< Max size of INTERRUPT[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_MaxIndex (15UL) /*!< Max index of INTERRUPT[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[16] array. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[16] register. */ + +/* SECATTR @Bit 4 : SECATTR feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos) /*!< + Bit mask of SECATTR field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage */ + +/* LOCK @Bit 8 : LOCK feature */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos) /*!< Bit mask + of LOCK field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next + reset*/ + +/* OWNERID @Bits 16..19 : Feature owner ID */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos) /*!< + Bit mask of OWNERID field.*/ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + + + +/* ================================================ Struct SPU_FEATURE_BELLS ================================================= */ +/** + * @brief BELLS [SPU_FEATURE_BELLS] (unspecified) + */ +typedef struct { + __IOM NRF_SPU_FEATURE_BELLS_PROCESSOR_Type PROCESSOR[8]; /*!< (@ 0x00000000) (unspecified) */ +} NRF_SPU_FEATURE_BELLS_Type; /*!< Size = 1536 (0x600) */ + + +/* =================================================== Struct SPU_FEATURE ==================================================== */ +/** + * @brief FEATURE [SPU_FEATURE] (unspecified) + */ +typedef union { + struct { + __IOM NRF_SPU_FEATURE_IPCT_Type IPCT; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC; /*!< (@ 0x00000080) (unspecified) */ + __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2]; /*!< (@ 0x00000100) (unspecified) */ + __IM uint32_t RESERVED[32]; + #if defined(_GNUC_) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpedantic" + #endif + union { + __IOM NRF_SPU_FEATURE_GPIO_Type GPIO[14]; /*!< (@ 0x00000200) (unspecified) */ + struct { + __IOM NRF_SPU_FEATURE_GRTC_Type GRTC; /*!< (@ 0x00000200) (unspecified) */ + }; + struct { + __IM uint32_t RESERVED1[256]; + __IOM NRF_SPU_FEATURE_MRAMC_Type MRAMC[2]; /*!< (@ 0x00000600) (unspecified) */ + }; + __IM uint32_t RESERVED2[448]; + }; + #if defined(_GNUC_) + #pragma GCC diagnostic pop + #endif + }; + __IOM NRF_SPU_FEATURE_BELLS_Type BELLS; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED3[576]; +} NRF_SPU_FEATURE_Type; /*!< Size = 2304 (0x900) */ + +/* ======================================================= Struct SPU ======================================================== */ +/** + * @brief System protection unit + */ + typedef struct { /*!< SPU Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000100) A security violation has been detected on one or + several peripherals*/ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[61]; + __IOM NRF_SPU_PERIPHACCERR_Type PERIPHACCERR; /*!< (@ 0x00000404) (unspecified) */ + __IM uint32_t RESERVED3[61]; + __IOM NRF_SPU_PERIPH_Type PERIPH[32]; /*!< (@ 0x00000500) (unspecified) */ + __IM uint32_t RESERVED4[32]; + __IOM NRF_SPU_FEATURE_Type FEATURE; /*!< (@ 0x00000600) (unspecified) */ + } NRF_SPU_Type; /*!< Size = 3840 (0xF00) */ + +/* SPU_EVENTS_PERIPHACCERR: A security violation has been detected on one or several peripherals */ + #define SPU_EVENTS_PERIPHACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PERIPHACCERR register. */ + +/* EVENTS_PERIPHACCERR @Bit 0 : A security violation has been detected on one or several peripherals */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit + mask of EVENTS_PERIPHACCERR field.*/ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_PERIPHACCERR field. */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ + #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */ + + +/* SPU_INTEN: Enable or disable interrupt */ + #define SPU_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* PERIPHACCERR @Bit 0 : Enable or disable interrupt for event PERIPHACCERR */ + #define SPU_INTEN_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */ + #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */ + + +/* SPU_INTENSET: Enable interrupt */ + #define SPU_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* PERIPHACCERR @Bit 0 : Write '1' to enable interrupt for event PERIPHACCERR */ + #define SPU_INTENSET_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */ + #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPU_INTENCLR: Disable interrupt */ + #define SPU_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* PERIPHACCERR @Bit 0 : Write '1' to disable interrupt for event PERIPHACCERR */ + #define SPU_INTENCLR_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */ + #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ + #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* SPU_INTPEND: Pending interrupts */ + #define SPU_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* PERIPHACCERR @Bit 0 : Read pending status of interrupt for event PERIPHACCERR */ + #define SPU_INTPEND_PERIPHACCERR_Pos (0UL) /*!< Position of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Msk (0x1UL << SPU_INTPEND_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of PERIPHACCERR field. */ + #define SPU_INTPEND_PERIPHACCERR_NotPending (0x0UL) /*!< Read: Not pending */ + #define SPU_INTPEND_PERIPHACCERR_Pending (0x1UL) /*!< Read: Pending */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ STM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct STM ======================================================== */ +/** + * @brief System Trace Macrocell + */ + typedef struct { /*!< STM Structure */ + __IM uint32_t RESERVED[772]; + __IOM uint32_t DMACTLR; /*!< (@ 0x00000C10) Controls the DMA transfer request mechanism. */ + __IM uint32_t RESERVED1[120]; + __IM uint32_t HEMASTR; /*!< (@ 0x00000DF4) Indicates the STPv2 master number of hardware event + trace. This number is the master number presented in + STPv2.*/ + __IM uint32_t HEFEAT1R; /*!< (@ 0x00000DF8) Indicates the features of the STM. */ + __IM uint32_t HEIDR; /*!< (@ 0x00000DFC) Indicates the features of hardware event tracing in the + STM.*/ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t TCSR; /*!< (@ 0x00000E80) Controls the STM settings. */ + __IM uint32_t RESERVED3[4]; + __IOM uint32_t AUXCR; /*!< (@ 0x00000E94) Used for implementation defined STM controls. */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SPFEAT1R; /*!< (@ 0x00000EA0) Indicates the features of the STM. */ + __IOM uint32_t SPFEAT2R; /*!< (@ 0x00000EA4) Indicates the features of the STM. */ + __IOM uint32_t SPFEAT3R; /*!< (@ 0x00000EA8) Indicates the features of the STM. */ + __IM uint32_t RESERVED5[15]; + __OM uint32_t ITTRIGGER; /*!< (@ 0x00000EE8) Integration Test for Cross-Trigger Outputs Register. */ + __OM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) Controls the value of the ATDATAM output in integration + mode.*/ + __OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Controls the value of the ATDATAM output in integration + mode.*/ + __OM uint32_t ITATBID; /*!< (@ 0x00000EF4) Controls the value of the ATIDM output in integration + mode.*/ + __OM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) Controls the value of the ATVALIDM, AFREADYM, and + ATBYTESM outputs in integration mode.*/ + __IM uint32_t RESERVED6; + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Used to enable topology detection. This register + enables the component to switch from a functional mode, + the default behavior, to integration mode where the + inputs and outputs of the component can be directly + controlled for integration testing and topology + solving.*/ + __IM uint32_t RESERVED7[43]; + __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device + registers.*/ + __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control + mechanism. This lock prevents accidental writes by code + under debug. Accesses to the extended stimulus port + registers are not affected by the lock mechanism. This + register must always be present although there might + not be any lock access control mechanism. The lock + mechanism, where present and locked, must block write + accesses to any control register, except the Lock + Access Register. For most components this covers all + registers except for the Lock Access Register.*/ + __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t RESERVED8[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the STM. */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Controls the single-shot comparator. */ + __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t PIDR0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ + __IOM uint32_t CIDR0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + __IOM uint32_t CIDR1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ + __IOM uint32_t CIDR2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ + __IOM uint32_t CIDR3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ + } NRF_STM_Type; /*!< Size = 4096 (0x1000) */ + +/* STM_DMACTLR: Controls the DMA transfer request mechanism. */ + #define STM_DMACTLR_ResetValue (0x00000000UL) /*!< Reset value of DMACTLR register. */ + +/* SENS @Bits 2..3 : Determines the sensitivity of the DMA request to the current buffer level in the STM */ + #define STM_DMACTLR_SENS_Pos (2UL) /*!< Position of SENS field. */ + #define STM_DMACTLR_SENS_Msk (0x3UL << STM_DMACTLR_SENS_Pos) /*!< Bit mask of SENS field. */ + #define STM_DMACTLR_SENS_Min (0x0UL) /*!< Min enumerator value of SENS field. */ + #define STM_DMACTLR_SENS_Max (0x3UL) /*!< Max enumerator value of SENS field. */ + #define STM_DMACTLR_SENS_LT25 (0x0UL) /*!< Buffer is <25 percent full. */ + #define STM_DMACTLR_SENS_LT50 (0x1UL) /*!< Buffer is <50 percent full. */ + #define STM_DMACTLR_SENS_LT75 (0x2UL) /*!< Buffer is <75 percent full. */ + #define STM_DMACTLR_SENS_LT100 (0x3UL) /*!< Buffer is <100 percent full. */ + + +/* STM_HEMASTR: Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2. + */ + + #define STM_HEMASTR_ResetValue (0x00000000UL) /*!< Reset value of HEMASTR register. */ + +/* MASTER @Bits 0..16 : The STPv2 master number that hardware event traces should be associated with. */ + #define STM_HEMASTR_MASTER_Pos (0UL) /*!< Position of MASTER field. */ + #define STM_HEMASTR_MASTER_Msk (0x1FFFFUL << STM_HEMASTR_MASTER_Pos) /*!< Bit mask of MASTER field. */ + #define STM_HEMASTR_MASTER_Min (0x00000UL) /*!< Min value of MASTER field. */ + #define STM_HEMASTR_MASTER_Max (0x0FFFFUL) /*!< Max size of MASTER field. */ + + +/* STM_HEFEAT1R: Indicates the features of the STM. */ + #define STM_HEFEAT1R_ResetValue (0x00000000UL) /*!< Reset value of HEFEAT1R register. */ + +/* HETER @Bit 0 : STMHETER support */ + #define STM_HEFEAT1R_HETER_Pos (0UL) /*!< Position of HETER field. */ + #define STM_HEFEAT1R_HETER_Msk (0x1UL << STM_HEFEAT1R_HETER_Pos) /*!< Bit mask of HETER field. */ + #define STM_HEFEAT1R_HETER_Min (0x0UL) /*!< Min enumerator value of HETER field. */ + #define STM_HEFEAT1R_HETER_Max (0x1UL) /*!< Max enumerator value of HETER field. */ + #define STM_HEFEAT1R_HETER_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_HEFEAT1R_HETER_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* HEERR @Bit 2 : Hardware event error detection support */ + #define STM_HEFEAT1R_HEERR_Pos (2UL) /*!< Position of HEERR field. */ + #define STM_HEFEAT1R_HEERR_Msk (0x1UL << STM_HEFEAT1R_HEERR_Pos) /*!< Bit mask of HEERR field. */ + #define STM_HEFEAT1R_HEERR_Min (0x0UL) /*!< Min enumerator value of HEERR field. */ + #define STM_HEFEAT1R_HEERR_Max (0x1UL) /*!< Max enumerator value of HEERR field. */ + #define STM_HEFEAT1R_HEERR_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_HEFEAT1R_HEERR_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* HEMASTR @Bit 3 : STMHEMASTR support */ + #define STM_HEFEAT1R_HEMASTR_Pos (3UL) /*!< Position of HEMASTR field. */ + #define STM_HEFEAT1R_HEMASTR_Msk (0x1UL << STM_HEFEAT1R_HEMASTR_Pos) /*!< Bit mask of HEMASTR field. */ + #define STM_HEFEAT1R_HEMASTR_Min (0x0UL) /*!< Min enumerator value of HEMASTR field. */ + #define STM_HEFEAT1R_HEMASTR_Max (0x1UL) /*!< Max enumerator value of HEMASTR field. */ + #define STM_HEFEAT1R_HEMASTR_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_HEFEAT1R_HEMASTR_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NUMHE @Bits 15..23 : The number of hardware events supported by the STM */ + #define STM_HEFEAT1R_NUMHE_Pos (15UL) /*!< Position of NUMHE field. */ + #define STM_HEFEAT1R_NUMHE_Msk (0x1FFUL << STM_HEFEAT1R_NUMHE_Pos) /*!< Bit mask of NUMHE field. */ + #define STM_HEFEAT1R_NUMHE_Min (0x000UL) /*!< Min value of NUMHE field. */ + #define STM_HEFEAT1R_NUMHE_Max (0x0FFUL) /*!< Max size of NUMHE field. */ + + +/* STM_HEIDR: Indicates the features of hardware event tracing in the STM. */ + #define STM_HEIDR_ResetValue (0x00000000UL) /*!< Reset value of HEIDR register. */ + +/* CLASS @Bits 0..3 : The CLASS field identifies the programmers model */ + #define STM_HEIDR_CLASS_Pos (0UL) /*!< Position of CLASS field. */ + #define STM_HEIDR_CLASS_Msk (0xFUL << STM_HEIDR_CLASS_Pos) /*!< Bit mask of CLASS field. */ + #define STM_HEIDR_CLASS_Min (0x1UL) /*!< Min enumerator value of CLASS field. */ + #define STM_HEIDR_CLASS_Max (0x1UL) /*!< Max enumerator value of CLASS field. */ + #define STM_HEIDR_CLASS_HardwareEventControl (0x1UL) /*!< Hardware Event Control programmers model */ + +/* CLASSREV @Bits 4..7 : The CLASSREV field identifies the revision of the programmers model */ + #define STM_HEIDR_CLASSREV_Pos (4UL) /*!< Position of CLASSREV field. */ + #define STM_HEIDR_CLASSREV_Msk (0xFUL << STM_HEIDR_CLASSREV_Pos) /*!< Bit mask of CLASSREV field. */ + +/* VENDSPEC @Bits 8..11 : The VENDSPEC field identifies any vendor specific modifications or mappings */ + #define STM_HEIDR_VENDSPEC_Pos (8UL) /*!< Position of VENDSPEC field. */ + #define STM_HEIDR_VENDSPEC_Msk (0xFUL << STM_HEIDR_VENDSPEC_Pos) /*!< Bit mask of VENDSPEC field. */ + + +/* STM_TCSR: Controls the STM settings. */ + #define STM_TCSR_ResetValue (0x00000000UL) /*!< Reset value of TCSR register. */ + +/* EN @Bit 0 : Global STM enable */ + #define STM_TCSR_EN_Pos (0UL) /*!< Position of EN field. */ + #define STM_TCSR_EN_Msk (0x1UL << STM_TCSR_EN_Pos) /*!< Bit mask of EN field. */ + #define STM_TCSR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define STM_TCSR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define STM_TCSR_EN_Disabled (0x0UL) /*!< The STM is disabled. */ + #define STM_TCSR_EN_Enabled (0x1UL) /*!< The STM is enabled. */ + +/* TSEN @Bit 1 : Enable or disable timestamp bundling. */ + #define STM_TCSR_TSEN_Pos (1UL) /*!< Position of TSEN field. */ + #define STM_TCSR_TSEN_Msk (0x1UL << STM_TCSR_TSEN_Pos) /*!< Bit mask of TSEN field. */ + #define STM_TCSR_TSEN_Min (0x0UL) /*!< Min enumerator value of TSEN field. */ + #define STM_TCSR_TSEN_Max (0x1UL) /*!< Max enumerator value of TSEN field. */ + #define STM_TCSR_TSEN_Disabled (0x0UL) /*!< Time stamps are disabled. Requests for timestamp generation are + ignored, and stimulus port writes selecting timestamping are treated + as if it were not selected.*/ + #define STM_TCSR_TSEN_Enabled (0x1UL) /*!< Time stamps are enabled. If stimulus writes select timestamping, a + timestamp is output according to STPv2.*/ + +/* SYNCEN @Bit 2 : STMSYNCR is implemented so this value is Read As One. */ + #define STM_TCSR_SYNCEN_Pos (2UL) /*!< Position of SYNCEN field. */ + #define STM_TCSR_SYNCEN_Msk (0x1UL << STM_TCSR_SYNCEN_Pos) /*!< Bit mask of SYNCEN field. */ + #define STM_TCSR_SYNCEN_Min (0x0UL) /*!< Min enumerator value of SYNCEN field. */ + #define STM_TCSR_SYNCEN_Max (0x1UL) /*!< Max enumerator value of SYNCEN field. */ + #define STM_TCSR_SYNCEN_Disabled (0x0UL) /*!< The STM Sync feature is disabled. */ + #define STM_TCSR_SYNCEN_Enabled (0x1UL) /*!< The STM Sync feature is enabled. */ + +/* COMPEN @Bit 5 : Compression Enable for Stimulus Ports. */ + #define STM_TCSR_COMPEN_Pos (5UL) /*!< Position of COMPEN field. */ + #define STM_TCSR_COMPEN_Msk (0x1UL << STM_TCSR_COMPEN_Pos) /*!< Bit mask of COMPEN field. */ + #define STM_TCSR_COMPEN_Min (0x0UL) /*!< Min enumerator value of COMPEN field. */ + #define STM_TCSR_COMPEN_Max (0x1UL) /*!< Max enumerator value of COMPEN field. */ + #define STM_TCSR_COMPEN_Disabled (0x0UL) /*!< Compression disabled, data transfers are transmitted at the size of + the transaction.*/ + #define STM_TCSR_COMPEN_Enabled (0x1UL) /*!< Compression enabled, data transfers are compressed to save bandwidth.*/ + +/* TRACEID @Bits 16..22 : ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. */ + #define STM_TCSR_TRACEID_Pos (16UL) /*!< Position of TRACEID field. */ + #define STM_TCSR_TRACEID_Msk (0x7FUL << STM_TCSR_TRACEID_Pos) /*!< Bit mask of TRACEID field. */ + #define STM_TCSR_TRACEID_Min (0x7FUL) /*!< Min value of TRACEID field. */ + #define STM_TCSR_TRACEID_Max (0x7FUL) /*!< Max size of TRACEID field. */ + +/* BUSY @Bit 23 : STM is busy, for example the STM trace FIFO is not empty. */ + #define STM_TCSR_BUSY_Pos (23UL) /*!< Position of BUSY field. */ + #define STM_TCSR_BUSY_Msk (0x1UL << STM_TCSR_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define STM_TCSR_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define STM_TCSR_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define STM_TCSR_BUSY_Ready (0x0UL) /*!< STM is not busy. */ + #define STM_TCSR_BUSY_Busy (0x1UL) /*!< STM is busy. */ + + +/* STM_AUXCR: Used for implementation defined STM controls. */ + #define STM_AUXCR_ResetValue (0x00000000UL) /*!< Reset value of AUXCR register. */ + +/* FIFOAF @Bit 0 : FIFO Auto-flush. */ + #define STM_AUXCR_FIFOAF_Pos (0UL) /*!< Position of FIFOAF field. */ + #define STM_AUXCR_FIFOAF_Msk (0x1UL << STM_AUXCR_FIFOAF_Pos) /*!< Bit mask of FIFOAF field. */ + #define STM_AUXCR_FIFOAF_Min (0x0UL) /*!< Min enumerator value of FIFOAF field. */ + #define STM_AUXCR_FIFOAF_Max (0x1UL) /*!< Max enumerator value of FIFOAF field. */ + #define STM_AUXCR_FIFOAF_Disabled (0x0UL) /*!< Auto-flush is disabled. */ + #define STM_AUXCR_FIFOAF_Enabled (0x1UL) /*!< Auto-flush is enabled. The STM automatically drains all data it has + even if the ATB interface is not fully utilized.*/ + +/* ASYNCPE @Bit 1 : Is ASYNC priority higher than trace? */ + #define STM_AUXCR_ASYNCPE_Pos (1UL) /*!< Position of ASYNCPE field. */ + #define STM_AUXCR_ASYNCPE_Msk (0x1UL << STM_AUXCR_ASYNCPE_Pos) /*!< Bit mask of ASYNCPE field. */ + #define STM_AUXCR_ASYNCPE_Min (0x0UL) /*!< Min enumerator value of ASYNCPE field. */ + #define STM_AUXCR_ASYNCPE_Max (0x1UL) /*!< Max enumerator value of ASYNCPE field. */ + #define STM_AUXCR_ASYNCPE_Lower (0x0UL) /*!< ASYNC priority is always lower than trace. */ + #define STM_AUXCR_ASYNCPE_Escalate (0x1UL) /*!< ASYNC priority escalates on second synchronization request. */ + +/* PRIORINVDIS @Bit 2 : Controls arbitration between AXI and HW during flush. */ + #define STM_AUXCR_PRIORINVDIS_Pos (2UL) /*!< Position of PRIORINVDIS field. */ + #define STM_AUXCR_PRIORINVDIS_Msk (0x1UL << STM_AUXCR_PRIORINVDIS_Pos) /*!< Bit mask of PRIORINVDIS field. */ + #define STM_AUXCR_PRIORINVDIS_Min (0x0UL) /*!< Min enumerator value of PRIORINVDIS field. */ + #define STM_AUXCR_PRIORINVDIS_Max (0x1UL) /*!< Max enumerator value of PRIORINVDIS field. */ + #define STM_AUXCR_PRIORINVDIS_Enabled (0x0UL) /*!< Priority inversion, when AXI flush is finished, HW gets priority until + HW flush is done.*/ + #define STM_AUXCR_PRIORINVDIS_Disabled (0x1UL) /*!< Priority inversion disabled, AXI always has priority over HW. */ + +/* CLKON @Bit 3 : Provides override control for architectural clock gate enable. */ + #define STM_AUXCR_CLKON_Pos (3UL) /*!< Position of CLKON field. */ + #define STM_AUXCR_CLKON_Msk (0x1UL << STM_AUXCR_CLKON_Pos) /*!< Bit mask of CLKON field. */ + #define STM_AUXCR_CLKON_Min (0x0UL) /*!< Min enumerator value of CLKON field. */ + #define STM_AUXCR_CLKON_Max (0x1UL) /*!< Max enumerator value of CLKON field. */ + #define STM_AUXCR_CLKON_Disabled (0x0UL) /*!< No override, clock gate is controlled by the state of STM. */ + #define STM_AUXCR_CLKON_Enabled (0x1UL) /*!< Override, clock is enabled. */ + +/* AFREADYHIGH @Bit 4 : Provides override control for the AFREADY output */ + #define STM_AUXCR_AFREADYHIGH_Pos (4UL) /*!< Position of AFREADYHIGH field. */ + #define STM_AUXCR_AFREADYHIGH_Msk (0x1UL << STM_AUXCR_AFREADYHIGH_Pos) /*!< Bit mask of AFREADYHIGH field. */ + #define STM_AUXCR_AFREADYHIGH_Min (0x0UL) /*!< Min enumerator value of AFREADYHIGH field. */ + #define STM_AUXCR_AFREADYHIGH_Max (0x1UL) /*!< Max enumerator value of AFREADYHIGH field. */ + #define STM_AUXCR_AFREADYHIGH_Disabled (0x0UL) /*!< No override, AFREADY is controlled by the state of STM. */ + #define STM_AUXCR_AFREADYHIGH_Enabled (0x1UL) /*!< Override, AFREADY is driven HIGH. */ + + +/* STM_SPFEAT1R: Indicates the features of the STM. */ + #define STM_SPFEAT1R_ResetValue (0x00000000UL) /*!< Reset value of SPFEAT1R register. */ + +/* PROT @Bits 0..3 : Indicates the implemented STM protocol. */ + #define STM_SPFEAT1R_PROT_Pos (0UL) /*!< Position of PROT field. */ + #define STM_SPFEAT1R_PROT_Msk (0xFUL << STM_SPFEAT1R_PROT_Pos) /*!< Bit mask of PROT field. */ + #define STM_SPFEAT1R_PROT_Min (0x1UL) /*!< Min enumerator value of PROT field. */ + #define STM_SPFEAT1R_PROT_Max (0x1UL) /*!< Max enumerator value of PROT field. */ + #define STM_SPFEAT1R_PROT_STPV2 (0x1UL) /*!< STM implements the STPV2 protocol. */ + +/* TS @Bits 4..5 : Timestamp support. */ + #define STM_SPFEAT1R_TS_Pos (4UL) /*!< Position of TS field. */ + #define STM_SPFEAT1R_TS_Msk (0x3UL << STM_SPFEAT1R_TS_Pos) /*!< Bit mask of TS field. */ + #define STM_SPFEAT1R_TS_Min (0x1UL) /*!< Min enumerator value of TS field. */ + #define STM_SPFEAT1R_TS_Max (0x1UL) /*!< Max enumerator value of TS field. */ + #define STM_SPFEAT1R_TS_Absolute (0x1UL) /*!< Absolute timestamps implemented. */ + +/* TSFREQ @Bit 6 : Timestamp frequency indication configuration. */ + #define STM_SPFEAT1R_TSFREQ_Pos (6UL) /*!< Position of TSFREQ field. */ + #define STM_SPFEAT1R_TSFREQ_Msk (0x1UL << STM_SPFEAT1R_TSFREQ_Pos) /*!< Bit mask of TSFREQ field. */ + #define STM_SPFEAT1R_TSFREQ_Min (0x0UL) /*!< Min enumerator value of TSFREQ field. */ + #define STM_SPFEAT1R_TSFREQ_Max (0x1UL) /*!< Max enumerator value of TSFREQ field. */ + #define STM_SPFEAT1R_TSFREQ_NotImplemented (0x0UL) /*!< STMTSFREQR is read-only. */ + #define STM_SPFEAT1R_TSFREQ_Implemented (0x1UL) /*!< STMTSFREQR is read-write. */ + +/* FORCETS @Bit 7 : Timestamp force configuration. */ + #define STM_SPFEAT1R_FORCETS_Pos (7UL) /*!< Position of FORCETS field. */ + #define STM_SPFEAT1R_FORCETS_Msk (0x1UL << STM_SPFEAT1R_FORCETS_Pos) /*!< Bit mask of FORCETS field. */ + #define STM_SPFEAT1R_FORCETS_Min (0x0UL) /*!< Min enumerator value of FORCETS field. */ + #define STM_SPFEAT1R_FORCETS_Max (0x1UL) /*!< Max enumerator value of FORCETS field. */ + #define STM_SPFEAT1R_FORCETS_NotImplemented (0x0UL) /*!< STMTSSTIMR bit 0 is read-only. */ + #define STM_SPFEAT1R_FORCETS_Implemented (0x1UL) /*!< STMTSSTIMR bit 0 is read-write. */ + +/* TRACEBUS @Bits 10..13 : Trace bus support. */ + #define STM_SPFEAT1R_TRACEBUS_Pos (10UL) /*!< Position of TRACEBUS field. */ + #define STM_SPFEAT1R_TRACEBUS_Msk (0xFUL << STM_SPFEAT1R_TRACEBUS_Pos) /*!< Bit mask of TRACEBUS field. */ + +/* TRIGCTL @Bits 14..15 : Trigger control support. */ + #define STM_SPFEAT1R_TRIGCTL_Pos (14UL) /*!< Position of TRIGCTL field. */ + #define STM_SPFEAT1R_TRIGCTL_Msk (0x3UL << STM_SPFEAT1R_TRIGCTL_Pos) /*!< Bit mask of TRIGCTL field. */ + +/* TSPRESCALE @Bits 16..17 : Timestamp prescale support */ + #define STM_SPFEAT1R_TSPRESCALE_Pos (16UL) /*!< Position of TSPRESCALE field. */ + #define STM_SPFEAT1R_TSPRESCALE_Msk (0x3UL << STM_SPFEAT1R_TSPRESCALE_Pos) /*!< Bit mask of TSPRESCALE field. */ + #define STM_SPFEAT1R_TSPRESCALE_Min (0x0UL) /*!< Min enumerator value of TSPRESCALE field. */ + #define STM_SPFEAT1R_TSPRESCALE_Max (0x1UL) /*!< Max enumerator value of TSPRESCALE field. */ + #define STM_SPFEAT1R_TSPRESCALE_NotImplemented (0x0UL) /*!< Timestamp prescale is not implemented. */ + #define STM_SPFEAT1R_TSPRESCALE_Implemented (0x1UL) /*!< Timestamp prescale is implemented. */ + +/* HWTEN @Bits 18..19 : STMTCSR.HWTEN support */ + #define STM_SPFEAT1R_HWTEN_Pos (18UL) /*!< Position of HWTEN field. */ + #define STM_SPFEAT1R_HWTEN_Msk (0x3UL << STM_SPFEAT1R_HWTEN_Pos) /*!< Bit mask of HWTEN field. */ + #define STM_SPFEAT1R_HWTEN_Min (0x1UL) /*!< Min enumerator value of HWTEN field. */ + #define STM_SPFEAT1R_HWTEN_Max (0x1UL) /*!< Max enumerator value of HWTEN field. */ + #define STM_SPFEAT1R_HWTEN_NotImplemented (0x1UL) /*!< STMTCSR.HWTEN is not implemented */ + +/* SYNCEN @Bits 20..21 : STMTCSR.SYNCEN support */ + #define STM_SPFEAT1R_SYNCEN_Pos (20UL) /*!< Position of SYNCEN field. */ + #define STM_SPFEAT1R_SYNCEN_Msk (0x3UL << STM_SPFEAT1R_SYNCEN_Pos) /*!< Bit mask of SYNCEN field. */ + #define STM_SPFEAT1R_SYNCEN_Min (0x2UL) /*!< Min enumerator value of SYNCEN field. */ + #define STM_SPFEAT1R_SYNCEN_Max (0x2UL) /*!< Max enumerator value of SYNCEN field. */ + #define STM_SPFEAT1R_SYNCEN_ReadAsOne (0x2UL) /*!< STMTCSR.SYNCEN implemented but always reads as b1 */ + +/* SWOEN @Bits 22..23 : STMTCSR.SWOEN support */ + #define STM_SPFEAT1R_SWOEN_Pos (22UL) /*!< Position of SWOEN field. */ + #define STM_SPFEAT1R_SWOEN_Msk (0x3UL << STM_SPFEAT1R_SWOEN_Pos) /*!< Bit mask of SWOEN field. */ + #define STM_SPFEAT1R_SWOEN_Min (0x1UL) /*!< Min enumerator value of SWOEN field. */ + #define STM_SPFEAT1R_SWOEN_Max (0x1UL) /*!< Max enumerator value of SWOEN field. */ + #define STM_SPFEAT1R_SWOEN_NotImplemented (0x1UL) /*!< STMTCSR.SWOEN not implemented */ + + +/* STM_SPFEAT2R: Indicates the features of the STM. */ + #define STM_SPFEAT2R_ResetValue (0x00000000UL) /*!< Reset value of SPFEAT2R register. */ + +/* SPTER @Bits 0..1 : STMSPTER support. */ + #define STM_SPFEAT2R_SPTER_Pos (0UL) /*!< Position of SPTER field. */ + #define STM_SPFEAT2R_SPTER_Msk (0x3UL << STM_SPFEAT2R_SPTER_Pos) /*!< Bit mask of SPTER field. */ + #define STM_SPFEAT2R_SPTER_Min (0x2UL) /*!< Min enumerator value of SPTER field. */ + #define STM_SPFEAT2R_SPTER_Max (0x2UL) /*!< Max enumerator value of SPTER field. */ + #define STM_SPFEAT2R_SPTER_Implemented (0x2UL) /*!< STMSPTER is implemented. */ + +/* SPER @Bit 2 : STMSPER presence. */ + #define STM_SPFEAT2R_SPER_Pos (2UL) /*!< Position of SPER field. */ + #define STM_SPFEAT2R_SPER_Msk (0x1UL << STM_SPFEAT2R_SPER_Pos) /*!< Bit mask of SPER field. */ + #define STM_SPFEAT2R_SPER_Min (0x0UL) /*!< Min enumerator value of SPER field. */ + #define STM_SPFEAT2R_SPER_Max (0x1UL) /*!< Max enumerator value of SPER field. */ + #define STM_SPFEAT2R_SPER_Implemented (0x0UL) /*!< STMSPER is implemented. */ + #define STM_SPFEAT2R_SPER_NotImplemented (0x1UL) /*!< STMSPER is not implemented. */ + +/* SPCOMP @Bits 4..5 : Data compression on stimulus ports support. */ + #define STM_SPFEAT2R_SPCOMP_Pos (4UL) /*!< Position of SPCOMP field. */ + #define STM_SPFEAT2R_SPCOMP_Msk (0x3UL << STM_SPFEAT2R_SPCOMP_Pos) /*!< Bit mask of SPCOMP field. */ + #define STM_SPFEAT2R_SPCOMP_Min (0x3UL) /*!< Min enumerator value of SPCOMP field. */ + #define STM_SPFEAT2R_SPCOMP_Max (0x3UL) /*!< Max enumerator value of SPCOMP field. */ + #define STM_SPFEAT2R_SPCOMP_Programmable (0x3UL) /*!< Data compression support is programmable. STMTCSR.COMPEN is + implemented.*/ + +/* SPOVERRIDE @Bit 6 : Timestamp force configuration. */ + #define STM_SPFEAT2R_SPOVERRIDE_Pos (6UL) /*!< Position of SPOVERRIDE field. */ + #define STM_SPFEAT2R_SPOVERRIDE_Msk (0x1UL << STM_SPFEAT2R_SPOVERRIDE_Pos) /*!< Bit mask of SPOVERRIDE field. */ + #define STM_SPFEAT2R_SPOVERRIDE_Min (0x0UL) /*!< Min enumerator value of SPOVERRIDE field. */ + #define STM_SPFEAT2R_SPOVERRIDE_Max (0x1UL) /*!< Max enumerator value of SPOVERRIDE field. */ + #define STM_SPFEAT2R_SPOVERRIDE_NotImplemented (0x0UL) /*!< STMSPOVERRIDER and STMSPMOVERRIDER is not implemented. */ + #define STM_SPFEAT2R_SPOVERRIDE_Implemented (0x1UL) /*!< STMSPOVERRIDER and STMSPMOVERRIDER is implemented. */ + +/* PRIVMASK @Bits 7..8 : STMPRIVMASKR support. */ + #define STM_SPFEAT2R_PRIVMASK_Pos (7UL) /*!< Position of PRIVMASK field. */ + #define STM_SPFEAT2R_PRIVMASK_Msk (0x3UL << STM_SPFEAT2R_PRIVMASK_Pos) /*!< Bit mask of PRIVMASK field. */ + #define STM_SPFEAT2R_PRIVMASK_Min (0x1UL) /*!< Min enumerator value of PRIVMASK field. */ + #define STM_SPFEAT2R_PRIVMASK_Max (0x1UL) /*!< Max enumerator value of PRIVMASK field. */ + #define STM_SPFEAT2R_PRIVMASK_NotImplemented (0x1UL) /*!< STMPRIVMASKR is not implemented. */ + +/* SPTRTYPE @Bits 9..10 : Stimulus port transaction type support. */ + #define STM_SPFEAT2R_SPTRTYPE_Pos (9UL) /*!< Position of SPTRTYPE field. */ + #define STM_SPFEAT2R_SPTRTYPE_Msk (0x3UL << STM_SPFEAT2R_SPTRTYPE_Pos) /*!< Bit mask of SPTRTYPE field. */ + #define STM_SPFEAT2R_SPTRTYPE_Min (0x2UL) /*!< Min enumerator value of SPTRTYPE field. */ + #define STM_SPFEAT2R_SPTRTYPE_Max (0x2UL) /*!< Max enumerator value of SPTRTYPE field. */ + #define STM_SPFEAT2R_SPTRTYPE_InvariantAndGuaranteed (0x2UL) /*!< Both invariant timing and guaranteed transactions are + supported.*/ + +/* DSIZE @Bits 12..15 : Fundamental data size. */ + #define STM_SPFEAT2R_DSIZE_Pos (12UL) /*!< Position of DSIZE field. */ + #define STM_SPFEAT2R_DSIZE_Msk (0xFUL << STM_SPFEAT2R_DSIZE_Pos) /*!< Bit mask of DSIZE field. */ + #define STM_SPFEAT2R_DSIZE_Min (0x0UL) /*!< Min enumerator value of DSIZE field. */ + #define STM_SPFEAT2R_DSIZE_Max (0x0UL) /*!< Max enumerator value of DSIZE field. */ + #define STM_SPFEAT2R_DSIZE_Bits32 (0x0UL) /*!< 32-bit data. */ + +/* SPTYPE @Bits 18..19 : Stimulus port type support */ + #define STM_SPFEAT2R_SPTYPE_Pos (18UL) /*!< Position of SPTYPE field. */ + #define STM_SPFEAT2R_SPTYPE_Msk (0x3UL << STM_SPFEAT2R_SPTYPE_Pos) /*!< Bit mask of SPTYPE field. */ + #define STM_SPFEAT2R_SPTYPE_Min (0x1UL) /*!< Min enumerator value of SPTYPE field. */ + #define STM_SPFEAT2R_SPTYPE_Max (0x1UL) /*!< Max enumerator value of SPTYPE field. */ + #define STM_SPFEAT2R_SPTYPE_OnlyExtended (0x1UL) /*!< Only extended stimulus ports are implemented. */ + + +/* STM_SPFEAT3R: Indicates the features of the STM. */ + #define STM_SPFEAT3R_ResetValue (0x00000000UL) /*!< Reset value of SPFEAT3R register. */ + +/* NUMMAST @Bits 0..6 : The number of stimulus ports masters implemented, minus 1. */ + #define STM_SPFEAT3R_NUMMAST_Pos (0UL) /*!< Position of NUMMAST field. */ + #define STM_SPFEAT3R_NUMMAST_Msk (0x7FUL << STM_SPFEAT3R_NUMMAST_Pos) /*!< Bit mask of NUMMAST field. */ + #define STM_SPFEAT3R_NUMMAST_Min (0x3FUL) /*!< Min enumerator value of NUMMAST field. */ + #define STM_SPFEAT3R_NUMMAST_Max (0x3FUL) /*!< Max enumerator value of NUMMAST field. */ + #define STM_SPFEAT3R_NUMMAST_Masters128 (0x3FUL) /*!< Example: 128 masters implemented. */ + + +/* STM_ITTRIGGER: Integration Test for Cross-Trigger Outputs Register. */ + #define STM_ITTRIGGER_ResetValue (0x00000000UL) /*!< Reset value of ITTRIGGER register. */ + +/* TRIGOUTSPTE_W @Bit 0 : Sets the value of the TRIGOUTSPTE output in integration mode. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_Pos (0UL) /*!< Position of TRIGOUTSPTE_W field. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTSPTE_W_Pos) /*!< Bit mask of TRIGOUTSPTE_W field. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSPTE_W field. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSPTE_W field. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITTRIGGER_TRIGOUTSPTE_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* TRIGOUTSW_W @Bit 1 : Sets the value of the TRIGOUTSW output in integration mode. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_Pos (1UL) /*!< Position of TRIGOUTSW_W field. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTSW_W_Pos) /*!< Bit mask of TRIGOUTSW_W field. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSW_W field. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSW_W field. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITTRIGGER_TRIGOUTSW_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* TRIGOUTHETE_W @Bit 2 : Sets the value of the TRIGOUTHETE output in integration mode. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_Pos (2UL) /*!< Position of TRIGOUTHETE_W field. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTHETE_W_Pos) /*!< Bit mask of TRIGOUTHETE_W field. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_Min (0x0UL) /*!< Min enumerator value of TRIGOUTHETE_W field. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_Max (0x1UL) /*!< Max enumerator value of TRIGOUTHETE_W field. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITTRIGGER_TRIGOUTHETE_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* ASYNCOUT_W @Bit 3 : Sets the value of the ASYNCOUT output in integration mode. */ + #define STM_ITTRIGGER_ASYNCOUT_W_Pos (3UL) /*!< Position of ASYNCOUT_W field. */ + #define STM_ITTRIGGER_ASYNCOUT_W_Msk (0x1UL << STM_ITTRIGGER_ASYNCOUT_W_Pos) /*!< Bit mask of ASYNCOUT_W field. */ + #define STM_ITTRIGGER_ASYNCOUT_W_Min (0x0UL) /*!< Min enumerator value of ASYNCOUT_W field. */ + #define STM_ITTRIGGER_ASYNCOUT_W_Max (0x1UL) /*!< Max enumerator value of ASYNCOUT_W field. */ + #define STM_ITTRIGGER_ASYNCOUT_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITTRIGGER_ASYNCOUT_W_High (0x1UL) /*!< Drive logic 1 on output. */ + + +/* STM_ITATBDATA0: Controls the value of the ATDATAM output in integration mode. */ + #define STM_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register. */ + +/* ATDATAM0_W @Bit 0 : Sets the value of the ATDATAM[0]. */ + #define STM_ITATBDATA0_ATDATAM0_W_Pos (0UL) /*!< Position of ATDATAM0_W field. */ + #define STM_ITATBDATA0_ATDATAM0_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM0_W_Pos) /*!< Bit mask of ATDATAM0_W field. */ + #define STM_ITATBDATA0_ATDATAM0_W_Min (0x0UL) /*!< Min enumerator value of ATDATAM0_W field. */ + #define STM_ITATBDATA0_ATDATAM0_W_Max (0x1UL) /*!< Max enumerator value of ATDATAM0_W field. */ + #define STM_ITATBDATA0_ATDATAM0_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITATBDATA0_ATDATAM0_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* ATDATAM7_W @Bit 1 : Sets the value of the ATDATAM[7] output. */ + #define STM_ITATBDATA0_ATDATAM7_W_Pos (1UL) /*!< Position of ATDATAM7_W field. */ + #define STM_ITATBDATA0_ATDATAM7_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM7_W_Pos) /*!< Bit mask of ATDATAM7_W field. */ + #define STM_ITATBDATA0_ATDATAM7_W_Min (0x0UL) /*!< Min enumerator value of ATDATAM7_W field. */ + #define STM_ITATBDATA0_ATDATAM7_W_Max (0x1UL) /*!< Max enumerator value of ATDATAM7_W field. */ + #define STM_ITATBDATA0_ATDATAM7_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITATBDATA0_ATDATAM7_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* ATDATAM15_W @Bit 2 : Sets the value of the ATDATAM[15]. */ + #define STM_ITATBDATA0_ATDATAM15_W_Pos (2UL) /*!< Position of ATDATAM15_W field. */ + #define STM_ITATBDATA0_ATDATAM15_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM15_W_Pos) /*!< Bit mask of ATDATAM15_W field. */ + #define STM_ITATBDATA0_ATDATAM15_W_Min (0x0UL) /*!< Min enumerator value of ATDATAM15_W field. */ + #define STM_ITATBDATA0_ATDATAM15_W_Max (0x1UL) /*!< Max enumerator value of ATDATAM15_W field. */ + #define STM_ITATBDATA0_ATDATAM15_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITATBDATA0_ATDATAM15_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* ATDATAM23_W @Bit 3 : Sets the value of the ATDATAM[23]. */ + #define STM_ITATBDATA0_ATDATAM23_W_Pos (3UL) /*!< Position of ATDATAM23_W field. */ + #define STM_ITATBDATA0_ATDATAM23_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM23_W_Pos) /*!< Bit mask of ATDATAM23_W field. */ + #define STM_ITATBDATA0_ATDATAM23_W_Min (0x0UL) /*!< Min enumerator value of ATDATAM23_W field. */ + #define STM_ITATBDATA0_ATDATAM23_W_Max (0x1UL) /*!< Max enumerator value of ATDATAM23_W field. */ + #define STM_ITATBDATA0_ATDATAM23_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITATBDATA0_ATDATAM23_W_High (0x1UL) /*!< Drive logic 1 on output. */ + +/* ATDATAM31_W @Bit 4 : Sets the value of the ATDATAM[31]. */ + #define STM_ITATBDATA0_ATDATAM31_W_Pos (4UL) /*!< Position of ATDATAM31_W field. */ + #define STM_ITATBDATA0_ATDATAM31_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM31_W_Pos) /*!< Bit mask of ATDATAM31_W field. */ + #define STM_ITATBDATA0_ATDATAM31_W_Min (0x0UL) /*!< Min enumerator value of ATDATAM31_W field. */ + #define STM_ITATBDATA0_ATDATAM31_W_Max (0x1UL) /*!< Max enumerator value of ATDATAM31_W field. */ + #define STM_ITATBDATA0_ATDATAM31_W_Low (0x0UL) /*!< Drive logic 0 on output. */ + #define STM_ITATBDATA0_ATDATAM31_W_High (0x1UL) /*!< Drive logic 1 on output. */ + + +/* STM_ITATBCTR2: Controls the value of the ATDATAM output in integration mode. */ + #define STM_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register. */ + +/* ATREADYM_R @Bit 0 : Reads the value of the ATREADYM input. */ + #define STM_ITATBCTR2_ATREADYM_R_Pos (0UL) /*!< Position of ATREADYM_R field. */ + #define STM_ITATBCTR2_ATREADYM_R_Msk (0x1UL << STM_ITATBCTR2_ATREADYM_R_Pos) /*!< Bit mask of ATREADYM_R field. */ + #define STM_ITATBCTR2_ATREADYM_R_Min (0x0UL) /*!< Min enumerator value of ATREADYM_R field. */ + #define STM_ITATBCTR2_ATREADYM_R_Max (0x1UL) /*!< Max enumerator value of ATREADYM_R field. */ + #define STM_ITATBCTR2_ATREADYM_R_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR2_ATREADYM_R_High (0x1UL) /*!< Pin is at logic 1. */ + +/* AFVALIDM_R @Bit 1 : Reads the value of the AFVALIDM input. */ + #define STM_ITATBCTR2_AFVALIDM_R_Pos (1UL) /*!< Position of AFVALIDM_R field. */ + #define STM_ITATBCTR2_AFVALIDM_R_Msk (0x1UL << STM_ITATBCTR2_AFVALIDM_R_Pos) /*!< Bit mask of AFVALIDM_R field. */ + #define STM_ITATBCTR2_AFVALIDM_R_Min (0x0UL) /*!< Min enumerator value of AFVALIDM_R field. */ + #define STM_ITATBCTR2_AFVALIDM_R_Max (0x1UL) /*!< Max enumerator value of AFVALIDM_R field. */ + #define STM_ITATBCTR2_AFVALIDM_R_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR2_AFVALIDM_R_High (0x1UL) /*!< Pin is at logic 1. */ + + +/* STM_ITATBID: Controls the value of the ATIDM output in integration mode. */ + #define STM_ITATBID_ResetValue (0x00000000UL) /*!< Reset value of ITATBID register. */ + +/* ATIDM_W0 @Bit 0 : Sets the value of pin 0 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W0_Pos (0UL) /*!< Position of ATIDM_W0 field. */ + #define STM_ITATBID_ATIDM_W0_Msk (0x1UL << STM_ITATBID_ATIDM_W0_Pos) /*!< Bit mask of ATIDM_W0 field. */ + #define STM_ITATBID_ATIDM_W0_Min (0x0UL) /*!< Min enumerator value of ATIDM_W0 field. */ + #define STM_ITATBID_ATIDM_W0_Max (0x1UL) /*!< Max enumerator value of ATIDM_W0 field. */ + #define STM_ITATBID_ATIDM_W0_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W0_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W1 @Bit 1 : Sets the value of pin 1 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W1_Pos (1UL) /*!< Position of ATIDM_W1 field. */ + #define STM_ITATBID_ATIDM_W1_Msk (0x1UL << STM_ITATBID_ATIDM_W1_Pos) /*!< Bit mask of ATIDM_W1 field. */ + #define STM_ITATBID_ATIDM_W1_Min (0x0UL) /*!< Min enumerator value of ATIDM_W1 field. */ + #define STM_ITATBID_ATIDM_W1_Max (0x1UL) /*!< Max enumerator value of ATIDM_W1 field. */ + #define STM_ITATBID_ATIDM_W1_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W1_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W2 @Bit 2 : Sets the value of pin 2 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W2_Pos (2UL) /*!< Position of ATIDM_W2 field. */ + #define STM_ITATBID_ATIDM_W2_Msk (0x1UL << STM_ITATBID_ATIDM_W2_Pos) /*!< Bit mask of ATIDM_W2 field. */ + #define STM_ITATBID_ATIDM_W2_Min (0x0UL) /*!< Min enumerator value of ATIDM_W2 field. */ + #define STM_ITATBID_ATIDM_W2_Max (0x1UL) /*!< Max enumerator value of ATIDM_W2 field. */ + #define STM_ITATBID_ATIDM_W2_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W2_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W3 @Bit 3 : Sets the value of pin 3 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W3_Pos (3UL) /*!< Position of ATIDM_W3 field. */ + #define STM_ITATBID_ATIDM_W3_Msk (0x1UL << STM_ITATBID_ATIDM_W3_Pos) /*!< Bit mask of ATIDM_W3 field. */ + #define STM_ITATBID_ATIDM_W3_Min (0x0UL) /*!< Min enumerator value of ATIDM_W3 field. */ + #define STM_ITATBID_ATIDM_W3_Max (0x1UL) /*!< Max enumerator value of ATIDM_W3 field. */ + #define STM_ITATBID_ATIDM_W3_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W3_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W4 @Bit 4 : Sets the value of pin 4 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W4_Pos (4UL) /*!< Position of ATIDM_W4 field. */ + #define STM_ITATBID_ATIDM_W4_Msk (0x1UL << STM_ITATBID_ATIDM_W4_Pos) /*!< Bit mask of ATIDM_W4 field. */ + #define STM_ITATBID_ATIDM_W4_Min (0x0UL) /*!< Min enumerator value of ATIDM_W4 field. */ + #define STM_ITATBID_ATIDM_W4_Max (0x1UL) /*!< Max enumerator value of ATIDM_W4 field. */ + #define STM_ITATBID_ATIDM_W4_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W4_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W5 @Bit 5 : Sets the value of pin 5 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W5_Pos (5UL) /*!< Position of ATIDM_W5 field. */ + #define STM_ITATBID_ATIDM_W5_Msk (0x1UL << STM_ITATBID_ATIDM_W5_Pos) /*!< Bit mask of ATIDM_W5 field. */ + #define STM_ITATBID_ATIDM_W5_Min (0x0UL) /*!< Min enumerator value of ATIDM_W5 field. */ + #define STM_ITATBID_ATIDM_W5_Max (0x1UL) /*!< Max enumerator value of ATIDM_W5 field. */ + #define STM_ITATBID_ATIDM_W5_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W5_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATIDM_W6 @Bit 6 : Sets the value of pin 6 of the ATIDM output. */ + #define STM_ITATBID_ATIDM_W6_Pos (6UL) /*!< Position of ATIDM_W6 field. */ + #define STM_ITATBID_ATIDM_W6_Msk (0x1UL << STM_ITATBID_ATIDM_W6_Pos) /*!< Bit mask of ATIDM_W6 field. */ + #define STM_ITATBID_ATIDM_W6_Min (0x0UL) /*!< Min enumerator value of ATIDM_W6 field. */ + #define STM_ITATBID_ATIDM_W6_Max (0x1UL) /*!< Max enumerator value of ATIDM_W6 field. */ + #define STM_ITATBID_ATIDM_W6_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBID_ATIDM_W6_High (0x1UL) /*!< Pin is at logic 1. */ + + +/* STM_ITATBCTR0: Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. */ + #define STM_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALIDM_W @Bit 0 : Sets the value of the ATVALIDM output. */ + #define STM_ITATBCTR0_ATVALIDM_W_Pos (0UL) /*!< Position of ATVALIDM_W field. */ + #define STM_ITATBCTR0_ATVALIDM_W_Msk (0x1UL << STM_ITATBCTR0_ATVALIDM_W_Pos) /*!< Bit mask of ATVALIDM_W field. */ + #define STM_ITATBCTR0_ATVALIDM_W_Min (0x0UL) /*!< Min enumerator value of ATVALIDM_W field. */ + #define STM_ITATBCTR0_ATVALIDM_W_Max (0x1UL) /*!< Max enumerator value of ATVALIDM_W field. */ + #define STM_ITATBCTR0_ATVALIDM_W_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR0_ATVALIDM_W_High (0x1UL) /*!< Pin is at logic 1. */ + +/* AFREADYM_W @Bit 1 : Sets the value of the AFREADYM_W output. */ + #define STM_ITATBCTR0_AFREADYM_W_Pos (1UL) /*!< Position of AFREADYM_W field. */ + #define STM_ITATBCTR0_AFREADYM_W_Msk (0x1UL << STM_ITATBCTR0_AFREADYM_W_Pos) /*!< Bit mask of AFREADYM_W field. */ + #define STM_ITATBCTR0_AFREADYM_W_Min (0x0UL) /*!< Min enumerator value of AFREADYM_W field. */ + #define STM_ITATBCTR0_AFREADYM_W_Max (0x1UL) /*!< Max enumerator value of AFREADYM_W field. */ + #define STM_ITATBCTR0_AFREADYM_W_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR0_AFREADYM_W_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATBYTESM_W0 @Bit 8 : Sets the value of pin 0 of the ATBYTESM output. */ + #define STM_ITATBCTR0_ATBYTESM_W0_Pos (8UL) /*!< Position of ATBYTESM_W0 field. */ + #define STM_ITATBCTR0_ATBYTESM_W0_Msk (0x1UL << STM_ITATBCTR0_ATBYTESM_W0_Pos) /*!< Bit mask of ATBYTESM_W0 field. */ + #define STM_ITATBCTR0_ATBYTESM_W0_Min (0x0UL) /*!< Min enumerator value of ATBYTESM_W0 field. */ + #define STM_ITATBCTR0_ATBYTESM_W0_Max (0x1UL) /*!< Max enumerator value of ATBYTESM_W0 field. */ + #define STM_ITATBCTR0_ATBYTESM_W0_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR0_ATBYTESM_W0_High (0x1UL) /*!< Pin is at logic 1. */ + +/* ATBYTESM_W1 @Bit 9 : Sets the value of pin 1 of the ATBYTESM output. */ + #define STM_ITATBCTR0_ATBYTESM_W1_Pos (9UL) /*!< Position of ATBYTESM_W1 field. */ + #define STM_ITATBCTR0_ATBYTESM_W1_Msk (0x1UL << STM_ITATBCTR0_ATBYTESM_W1_Pos) /*!< Bit mask of ATBYTESM_W1 field. */ + #define STM_ITATBCTR0_ATBYTESM_W1_Min (0x0UL) /*!< Min enumerator value of ATBYTESM_W1 field. */ + #define STM_ITATBCTR0_ATBYTESM_W1_Max (0x1UL) /*!< Max enumerator value of ATBYTESM_W1 field. */ + #define STM_ITATBCTR0_ATBYTESM_W1_Low (0x0UL) /*!< Pin is at logic 0. */ + #define STM_ITATBCTR0_ATBYTESM_W1_High (0x1UL) /*!< Pin is at logic 1. */ + + +/* STM_ITCTRL: Used to enable topology detection. This register enables the component to switch from a functional mode, the + default behavior, to integration mode where the inputs and outputs of the component can be directly controlled + for integration testing and topology solving. */ + + #define STM_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* INTEGRATIONMODE @Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration + functionality is implemented, this register must read as zero. */ + + #define STM_ITCTRL_INTEGRATIONMODE_Pos (0UL) /*!< Position of INTEGRATIONMODE field. */ + #define STM_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << STM_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field. */ + #define STM_ITCTRL_INTEGRATIONMODE_Min (0x0UL) /*!< Min enumerator value of INTEGRATIONMODE field. */ + #define STM_ITCTRL_INTEGRATIONMODE_Max (0x1UL) /*!< Max enumerator value of INTEGRATIONMODE field. */ + #define STM_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled. */ + #define STM_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled. */ + + +/* STM_LAR: This is used to enable write access to device registers. */ + #define STM_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + */ + + #define STM_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ + #define STM_LAR_ACCESS_Msk (0xFFFFFFFFUL << STM_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ + #define STM_LAR_ACCESS_Min (0xC5ACCE55UL) /*!< Min enumerator value of ACCESS field. */ + #define STM_LAR_ACCESS_Max (0xC5ACCE55UL) /*!< Max enumerator value of ACCESS field. */ + #define STM_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ + + +/* STM_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always + be present although there might not be any lock access control mechanism. The lock mechanism, where present and + locked, must block write accesses to any control register, except the Lock Access Register. For most components + this covers all registers except for the Lock Access Register. */ + + #define STM_LSR_ResetValue (0x00000000UL) /*!< Reset value of LSR register. */ + +/* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */ + #define STM_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ + #define STM_LSR_PRESENT_Msk (0x1UL << STM_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define STM_LSR_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define STM_LSR_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define STM_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register + are ignored.*/ + #define STM_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ + +/* LOCKED @Bit 1 : Returns the current status of the Lock. */ + #define STM_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ + #define STM_LSR_LOCKED_Msk (0x1UL << STM_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define STM_LSR_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define STM_LSR_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define STM_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ + #define STM_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control + registers are ignored. Reads are permitted.*/ + +/* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ + #define STM_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ + #define STM_LSR_TYPE_Msk (0x1UL << STM_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define STM_LSR_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define STM_LSR_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define STM_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ + #define STM_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ + + +/* STM_AUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define STM_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define STM_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define STM_AUTHSTATUS_NSID_Msk (0x3UL << STM_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define STM_AUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define STM_AUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define STM_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define STM_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define STM_AUTHSTATUS_NSNID_Msk (0x3UL << STM_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define STM_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define STM_AUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define STM_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define STM_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define STM_AUTHSTATUS_SID_Msk (0x3UL << STM_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define STM_AUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define STM_AUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define STM_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define STM_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define STM_AUTHSTATUS_SNID_Msk (0x3UL << STM_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define STM_AUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define STM_AUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define STM_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define STM_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* STM_DEVID: Indicates the capabilities of the STM. */ + #define STM_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register. */ + +/* NUMSP @Bits 0..16 : This value indicates the number of stimulus ports implemented. */ + #define STM_DEVID_NUMSP_Pos (0UL) /*!< Position of NUMSP field. */ + #define STM_DEVID_NUMSP_Msk (0x1FFFFUL << STM_DEVID_NUMSP_Pos) /*!< Bit mask of NUMSP field. */ + #define STM_DEVID_NUMSP_Max (0x10000UL) /*!< Maximum 65,536 stimulus ports can be implemented. */ + + +/* STM_DEVTYPE: Controls the single-shot comparator. */ + #define STM_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define STM_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define STM_DEVTYPE_MAJOR_Msk (0xFUL << STM_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define STM_DEVTYPE_MAJOR_Min (0x3UL) /*!< Min enumerator value of MAJOR field. */ + #define STM_DEVTYPE_MAJOR_Max (0x3UL) /*!< Max enumerator value of MAJOR field. */ + #define STM_DEVTYPE_MAJOR_TraceSource (0x3UL) /*!< Peripheral is a trace source. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define STM_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define STM_DEVTYPE_SUB_Msk (0xFUL << STM_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define STM_DEVTYPE_SUB_Min (0x6UL) /*!< Min enumerator value of SUB field. */ + #define STM_DEVTYPE_SUB_Max (0x6UL) /*!< Max enumerator value of SUB field. */ + #define STM_DEVTYPE_SUB_StimulusTrace (0x6UL) /*!< Peripheral is a stimulus trace source. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ STMDATA ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct STMDATA_DOMAIN ================================================== */ +/** + * @brief DOMAIN [STMDATA_DOMAIN] (unspecified) + */ +typedef struct { + __IOM uint8_t DATA[16777216]; /*!< (@ 0x00000000) STM extended stimulus port data buffer area for domain + n. NonSecure writes to this region generates trace + packets with id n+96. Secure writes to this region + generates trace packets with id n+32.*/ +} NRF_STMDATA_DOMAIN_Type; /*!< Size = 16777216 (0x1000000) */ + #define STMDATA_DOMAIN_MaxCount (16UL) /*!< Size of DOMAIN[16] array. */ + #define STMDATA_DOMAIN_MaxIndex (15UL) /*!< Max index of DOMAIN[16] array. */ + #define STMDATA_DOMAIN_MinIndex (0UL) /*!< Min index of DOMAIN[16] array. */ + +/* ===================================================== Struct STMDATA ====================================================== */ +/** + * @brief System Trace Macrocell data buffer + */ + typedef struct { /*!< STMDATA Structure */ + __IOM NRF_STMDATA_DOMAIN_Type DOMAIN[16]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_STMDATA_Type; /*!< Size = 268435456 (0x10000000) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ SWI ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct SWI ======================================================== */ +/** + * @brief Software interrupt + */ + typedef struct { /*!< SWI Structure */ + __IM uint32_t RESERVED; + } NRF_SWI_Type; /*!< Size = 4 (0x004) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TBM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TBM ======================================================== */ +/** + * @brief Trace buffer monitor + */ + typedef struct { /*!< TBM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start counter */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop counter, clear counter value */ + __OM uint32_t TASKS_FLUSH; /*!< (@ 0x00000008) Save current counter value to COUNTSNAPSHOT */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_HALFFULL; /*!< (@ 0x00000100) Counter value equals half-full */ + __IOM uint32_t EVENTS_FULL; /*!< (@ 0x00000104) Counter value equals full */ + __IOM uint32_t EVENTS_FLUSH; /*!< (@ 0x00000108) Counter value saved to COUNTSNAPSHOT due to flush */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t BUFFERSIZE; /*!< (@ 0x00000400) System RAM trace buffer total size in bytes */ + __IOM uint32_t COUNT; /*!< (@ 0x00000404) Counter current value */ + __IM uint32_t COUNTSNAPSHOT; /*!< (@ 0x00000408) Copy of the current COUNT value */ + } NRF_TBM_Type; /*!< Size = 1036 (0x40C) */ + +/* TBM_TASKS_START: Start counter */ + #define TBM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start counter */ + #define TBM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TBM_TASKS_START_TASKS_START_Msk (0x1UL << TBM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TBM_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TBM_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TBM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TBM_TASKS_STOP: Stop counter, clear counter value */ + #define TBM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop counter, clear counter value */ + #define TBM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TBM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TBM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TBM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TBM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TBM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TBM_TASKS_FLUSH: Save current counter value to COUNTSNAPSHOT */ + #define TBM_TASKS_FLUSH_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSH register. */ + +/* TASKS_FLUSH @Bit 0 : Save current counter value to COUNTSNAPSHOT */ + #define TBM_TASKS_FLUSH_TASKS_FLUSH_Pos (0UL) /*!< Position of TASKS_FLUSH field. */ + #define TBM_TASKS_FLUSH_TASKS_FLUSH_Msk (0x1UL << TBM_TASKS_FLUSH_TASKS_FLUSH_Pos) /*!< Bit mask of TASKS_FLUSH field. */ + #define TBM_TASKS_FLUSH_TASKS_FLUSH_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSH field. */ + #define TBM_TASKS_FLUSH_TASKS_FLUSH_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSH field. */ + #define TBM_TASKS_FLUSH_TASKS_FLUSH_Trigger (0x1UL) /*!< Trigger task */ + + +/* TBM_EVENTS_HALFFULL: Counter value equals half-full */ + #define TBM_EVENTS_HALFFULL_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_HALFFULL register. */ + +/* EVENTS_HALFFULL @Bit 0 : Counter value equals half-full */ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Pos (0UL) /*!< Position of EVENTS_HALFFULL field. */ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Msk (0x1UL << TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Pos) /*!< Bit mask of + EVENTS_HALFFULL field.*/ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Min (0x0UL) /*!< Min enumerator value of EVENTS_HALFFULL field. */ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Max (0x1UL) /*!< Max enumerator value of EVENTS_HALFFULL field. */ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_NotGenerated (0x0UL) /*!< Event not generated */ + #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Generated (0x1UL) /*!< Event generated */ + + +/* TBM_EVENTS_FULL: Counter value equals full */ + #define TBM_EVENTS_FULL_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FULL register. */ + +/* EVENTS_FULL @Bit 0 : Counter value equals full */ + #define TBM_EVENTS_FULL_EVENTS_FULL_Pos (0UL) /*!< Position of EVENTS_FULL field. */ + #define TBM_EVENTS_FULL_EVENTS_FULL_Msk (0x1UL << TBM_EVENTS_FULL_EVENTS_FULL_Pos) /*!< Bit mask of EVENTS_FULL field. */ + #define TBM_EVENTS_FULL_EVENTS_FULL_Min (0x0UL) /*!< Min enumerator value of EVENTS_FULL field. */ + #define TBM_EVENTS_FULL_EVENTS_FULL_Max (0x1UL) /*!< Max enumerator value of EVENTS_FULL field. */ + #define TBM_EVENTS_FULL_EVENTS_FULL_NotGenerated (0x0UL) /*!< Event not generated */ + #define TBM_EVENTS_FULL_EVENTS_FULL_Generated (0x1UL) /*!< Event generated */ + + +/* TBM_EVENTS_FLUSH: Counter value saved to COUNTSNAPSHOT due to flush */ + #define TBM_EVENTS_FLUSH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FLUSH register. */ + +/* EVENTS_FLUSH @Bit 0 : Counter value saved to COUNTSNAPSHOT due to flush */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Pos (0UL) /*!< Position of EVENTS_FLUSH field. */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Msk (0x1UL << TBM_EVENTS_FLUSH_EVENTS_FLUSH_Pos) /*!< Bit mask of EVENTS_FLUSH field. */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Min (0x0UL) /*!< Min enumerator value of EVENTS_FLUSH field. */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Max (0x1UL) /*!< Max enumerator value of EVENTS_FLUSH field. */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_NotGenerated (0x0UL) /*!< Event not generated */ + #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Generated (0x1UL) /*!< Event generated */ + + +/* TBM_INTEN: Enable or disable interrupt */ + #define TBM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* HALFFULL @Bit 0 : Enable or disable interrupt for event HALFFULL */ + #define TBM_INTEN_HALFFULL_Pos (0UL) /*!< Position of HALFFULL field. */ + #define TBM_INTEN_HALFFULL_Msk (0x1UL << TBM_INTEN_HALFFULL_Pos) /*!< Bit mask of HALFFULL field. */ + #define TBM_INTEN_HALFFULL_Min (0x0UL) /*!< Min enumerator value of HALFFULL field. */ + #define TBM_INTEN_HALFFULL_Max (0x1UL) /*!< Max enumerator value of HALFFULL field. */ + #define TBM_INTEN_HALFFULL_Disabled (0x0UL) /*!< Disable */ + #define TBM_INTEN_HALFFULL_Enabled (0x1UL) /*!< Enable */ + +/* FULL @Bit 1 : Enable or disable interrupt for event FULL */ + #define TBM_INTEN_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define TBM_INTEN_FULL_Msk (0x1UL << TBM_INTEN_FULL_Pos) /*!< Bit mask of FULL field. */ + #define TBM_INTEN_FULL_Min (0x0UL) /*!< Min enumerator value of FULL field. */ + #define TBM_INTEN_FULL_Max (0x1UL) /*!< Max enumerator value of FULL field. */ + #define TBM_INTEN_FULL_Disabled (0x0UL) /*!< Disable */ + #define TBM_INTEN_FULL_Enabled (0x1UL) /*!< Enable */ + +/* FLUSH @Bit 2 : Enable or disable interrupt for event FLUSH */ + #define TBM_INTEN_FLUSH_Pos (2UL) /*!< Position of FLUSH field. */ + #define TBM_INTEN_FLUSH_Msk (0x1UL << TBM_INTEN_FLUSH_Pos) /*!< Bit mask of FLUSH field. */ + #define TBM_INTEN_FLUSH_Min (0x0UL) /*!< Min enumerator value of FLUSH field. */ + #define TBM_INTEN_FLUSH_Max (0x1UL) /*!< Max enumerator value of FLUSH field. */ + #define TBM_INTEN_FLUSH_Disabled (0x0UL) /*!< Disable */ + #define TBM_INTEN_FLUSH_Enabled (0x1UL) /*!< Enable */ + + +/* TBM_INTENSET: Enable interrupt */ + #define TBM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* HALFFULL @Bit 0 : Write '1' to enable interrupt for event HALFFULL */ + #define TBM_INTENSET_HALFFULL_Pos (0UL) /*!< Position of HALFFULL field. */ + #define TBM_INTENSET_HALFFULL_Msk (0x1UL << TBM_INTENSET_HALFFULL_Pos) /*!< Bit mask of HALFFULL field. */ + #define TBM_INTENSET_HALFFULL_Min (0x0UL) /*!< Min enumerator value of HALFFULL field. */ + #define TBM_INTENSET_HALFFULL_Max (0x1UL) /*!< Max enumerator value of HALFFULL field. */ + #define TBM_INTENSET_HALFFULL_Set (0x1UL) /*!< Enable */ + #define TBM_INTENSET_HALFFULL_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENSET_HALFFULL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FULL @Bit 1 : Write '1' to enable interrupt for event FULL */ + #define TBM_INTENSET_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define TBM_INTENSET_FULL_Msk (0x1UL << TBM_INTENSET_FULL_Pos) /*!< Bit mask of FULL field. */ + #define TBM_INTENSET_FULL_Min (0x0UL) /*!< Min enumerator value of FULL field. */ + #define TBM_INTENSET_FULL_Max (0x1UL) /*!< Max enumerator value of FULL field. */ + #define TBM_INTENSET_FULL_Set (0x1UL) /*!< Enable */ + #define TBM_INTENSET_FULL_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENSET_FULL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FLUSH @Bit 2 : Write '1' to enable interrupt for event FLUSH */ + #define TBM_INTENSET_FLUSH_Pos (2UL) /*!< Position of FLUSH field. */ + #define TBM_INTENSET_FLUSH_Msk (0x1UL << TBM_INTENSET_FLUSH_Pos) /*!< Bit mask of FLUSH field. */ + #define TBM_INTENSET_FLUSH_Min (0x0UL) /*!< Min enumerator value of FLUSH field. */ + #define TBM_INTENSET_FLUSH_Max (0x1UL) /*!< Max enumerator value of FLUSH field. */ + #define TBM_INTENSET_FLUSH_Set (0x1UL) /*!< Enable */ + #define TBM_INTENSET_FLUSH_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENSET_FLUSH_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TBM_INTENCLR: Disable interrupt */ + #define TBM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* HALFFULL @Bit 0 : Write '1' to disable interrupt for event HALFFULL */ + #define TBM_INTENCLR_HALFFULL_Pos (0UL) /*!< Position of HALFFULL field. */ + #define TBM_INTENCLR_HALFFULL_Msk (0x1UL << TBM_INTENCLR_HALFFULL_Pos) /*!< Bit mask of HALFFULL field. */ + #define TBM_INTENCLR_HALFFULL_Min (0x0UL) /*!< Min enumerator value of HALFFULL field. */ + #define TBM_INTENCLR_HALFFULL_Max (0x1UL) /*!< Max enumerator value of HALFFULL field. */ + #define TBM_INTENCLR_HALFFULL_Clear (0x1UL) /*!< Disable */ + #define TBM_INTENCLR_HALFFULL_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENCLR_HALFFULL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FULL @Bit 1 : Write '1' to disable interrupt for event FULL */ + #define TBM_INTENCLR_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define TBM_INTENCLR_FULL_Msk (0x1UL << TBM_INTENCLR_FULL_Pos) /*!< Bit mask of FULL field. */ + #define TBM_INTENCLR_FULL_Min (0x0UL) /*!< Min enumerator value of FULL field. */ + #define TBM_INTENCLR_FULL_Max (0x1UL) /*!< Max enumerator value of FULL field. */ + #define TBM_INTENCLR_FULL_Clear (0x1UL) /*!< Disable */ + #define TBM_INTENCLR_FULL_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENCLR_FULL_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FLUSH @Bit 2 : Write '1' to disable interrupt for event FLUSH */ + #define TBM_INTENCLR_FLUSH_Pos (2UL) /*!< Position of FLUSH field. */ + #define TBM_INTENCLR_FLUSH_Msk (0x1UL << TBM_INTENCLR_FLUSH_Pos) /*!< Bit mask of FLUSH field. */ + #define TBM_INTENCLR_FLUSH_Min (0x0UL) /*!< Min enumerator value of FLUSH field. */ + #define TBM_INTENCLR_FLUSH_Max (0x1UL) /*!< Max enumerator value of FLUSH field. */ + #define TBM_INTENCLR_FLUSH_Clear (0x1UL) /*!< Disable */ + #define TBM_INTENCLR_FLUSH_Disabled (0x0UL) /*!< Read: Disabled */ + #define TBM_INTENCLR_FLUSH_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TBM_INTPEND: Pending interrupts */ + #define TBM_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* HALFFULL @Bit 0 : Read pending status of interrupt for event HALFFULL */ + #define TBM_INTPEND_HALFFULL_Pos (0UL) /*!< Position of HALFFULL field. */ + #define TBM_INTPEND_HALFFULL_Msk (0x1UL << TBM_INTPEND_HALFFULL_Pos) /*!< Bit mask of HALFFULL field. */ + #define TBM_INTPEND_HALFFULL_Min (0x0UL) /*!< Min enumerator value of HALFFULL field. */ + #define TBM_INTPEND_HALFFULL_Max (0x1UL) /*!< Max enumerator value of HALFFULL field. */ + #define TBM_INTPEND_HALFFULL_NotPending (0x0UL) /*!< Read: Not pending */ + #define TBM_INTPEND_HALFFULL_Pending (0x1UL) /*!< Read: Pending */ + +/* FULL @Bit 1 : Read pending status of interrupt for event FULL */ + #define TBM_INTPEND_FULL_Pos (1UL) /*!< Position of FULL field. */ + #define TBM_INTPEND_FULL_Msk (0x1UL << TBM_INTPEND_FULL_Pos) /*!< Bit mask of FULL field. */ + #define TBM_INTPEND_FULL_Min (0x0UL) /*!< Min enumerator value of FULL field. */ + #define TBM_INTPEND_FULL_Max (0x1UL) /*!< Max enumerator value of FULL field. */ + #define TBM_INTPEND_FULL_NotPending (0x0UL) /*!< Read: Not pending */ + #define TBM_INTPEND_FULL_Pending (0x1UL) /*!< Read: Pending */ + +/* FLUSH @Bit 2 : Read pending status of interrupt for event FLUSH */ + #define TBM_INTPEND_FLUSH_Pos (2UL) /*!< Position of FLUSH field. */ + #define TBM_INTPEND_FLUSH_Msk (0x1UL << TBM_INTPEND_FLUSH_Pos) /*!< Bit mask of FLUSH field. */ + #define TBM_INTPEND_FLUSH_Min (0x0UL) /*!< Min enumerator value of FLUSH field. */ + #define TBM_INTPEND_FLUSH_Max (0x1UL) /*!< Max enumerator value of FLUSH field. */ + #define TBM_INTPEND_FLUSH_NotPending (0x0UL) /*!< Read: Not pending */ + #define TBM_INTPEND_FLUSH_Pending (0x1UL) /*!< Read: Pending */ + + +/* TBM_BUFFERSIZE: System RAM trace buffer total size in bytes */ + #define TBM_BUFFERSIZE_ResetValue (0x00000400UL) /*!< Reset value of BUFFERSIZE register. */ + +/* BUFFERSIZE @Bits 0..12 : Must only be configured in STOP mode. Must be programmed to multiple of 16 bytes to make half-buffer + size always 64 bit word aligned. Typical minimum BUFFERSIZE value 0x010 i.e. 16 bytes, typical + maximum value 0x1000 i.e. 4096 bytes. */ + + #define TBM_BUFFERSIZE_BUFFERSIZE_Pos (0UL) /*!< Position of BUFFERSIZE field. */ + #define TBM_BUFFERSIZE_BUFFERSIZE_Msk (0x1FFFUL << TBM_BUFFERSIZE_BUFFERSIZE_Pos) /*!< Bit mask of BUFFERSIZE field. */ + #define TBM_BUFFERSIZE_BUFFERSIZE_Zero (0x0000UL) /*!< 0 bytes */ + #define TBM_BUFFERSIZE_BUFFERSIZE_Min (0x0010UL) /*!< 16 bytes */ + #define TBM_BUFFERSIZE_BUFFERSIZE_Max (0x1000UL) /*!< 4096 bytes */ + + +/* TBM_COUNT: Counter current value */ + #define TBM_COUNT_ResetValue (0x00000000UL) /*!< Reset value of COUNT register. */ + +/* COUNT @Bits 0..12 : Counter current value. Only writable when counter is in stopped state. Writing when not in stopped state + will generate a bus fault. */ + + #define TBM_COUNT_COUNT_Pos (0UL) /*!< Position of COUNT field. */ + #define TBM_COUNT_COUNT_Msk (0x1FFFUL << TBM_COUNT_COUNT_Pos) /*!< Bit mask of COUNT field. */ + + +/* TBM_COUNTSNAPSHOT: Copy of the current COUNT value */ + #define TBM_COUNTSNAPSHOT_ResetValue (0x00000000UL) /*!< Reset value of COUNTSNAPSHOT register. */ + +/* COUNTSNAPSHOT @Bits 0..12 : TASKS_FLUSH will copy the current COUNT value to this register. */ + #define TBM_COUNTSNAPSHOT_COUNTSNAPSHOT_Pos (0UL) /*!< Position of COUNTSNAPSHOT field. */ + #define TBM_COUNTSNAPSHOT_COUNTSNAPSHOT_Msk (0x1FFFUL << TBM_COUNTSNAPSHOT_COUNTSNAPSHOT_Pos) /*!< Bit mask of COUNTSNAPSHOT + field.*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TDDCONF ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ===================================================== Struct TDDCONF ====================================================== */ +/** + * @brief TDDCONF + */ + typedef struct { /*!< TDDCONF Structure */ + __IM uint32_t RESERVED[256]; + __IOM uint32_t SYSPWRUPREQ; /*!< (@ 0x00000400) System power-up request */ + __IOM uint32_t DBGPWRUPREQ; /*!< (@ 0x00000404) Debug power-up request */ + __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000408) Trace port trace clock speed */ + __IM uint32_t DEBUGPOWERREQSTATUS; /*!< (@ 0x0000040C) Combined effective system status of both SWJ-DP and + TDDCONF registers originated power requests*/ + } NRF_TDDCONF_Type; /*!< Size = 1040 (0x410) */ + +/* TDDCONF_SYSPWRUPREQ: System power-up request */ + #define TDDCONF_SYSPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of SYSPWRUPREQ register. */ + +/* ACTIVE @Bit 0 : Activate power-up request */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_Msk (0x1UL << TDDCONF_SYSPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active */ + #define TDDCONF_SYSPWRUPREQ_ACTIVE_Active (0x1UL) /*!< Power-up request active */ + + +/* TDDCONF_DBGPWRUPREQ: Debug power-up request */ + #define TDDCONF_DBGPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of DBGPWRUPREQ register. */ + +/* ACTIVE @Bit 0 : Activate power-up request */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_Pos (0UL) /*!< Position of ACTIVE field. */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_Msk (0x1UL << TDDCONF_DBGPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field. */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_Min (0x0UL) /*!< Min enumerator value of ACTIVE field. */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_Max (0x1UL) /*!< Max enumerator value of ACTIVE field. */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active */ + #define TDDCONF_DBGPWRUPREQ_ACTIVE_Active (0x1UL) /*!< Power-up request active */ + + +/* TDDCONF_TRACEPORTSPEED: Trace port trace clock speed */ + #define TDDCONF_TRACEPORTSPEED_ResetValue (0x00000000UL) /*!< Reset value of TRACEPORTSPEED register. */ + +/* SPEED @Bits 0..1 : Trace clock speed */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Pos (0UL) /*!< Position of SPEED field. */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Msk (0x3UL << TDDCONF_TRACEPORTSPEED_SPEED_Pos) /*!< Bit mask of SPEED field. */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Min (0x0UL) /*!< Min enumerator value of SPEED field. */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Max (0x3UL) /*!< Max enumerator value of SPEED field. */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Speed100MHz (0x0UL) /*!< Speed 100MHz */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Speed50MHz (0x1UL) /*!< Speed 50MHz */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Speed25MHz (0x2UL) /*!< Speed 25MHz */ + #define TDDCONF_TRACEPORTSPEED_SPEED_Speed12500KHz (0x3UL) /*!< Speed 12.5MHz */ + + +/* TDDCONF_DEBUGPOWERREQSTATUS: Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests + */ + + #define TDDCONF_DEBUGPOWERREQSTATUS_ResetValue (0x00000000UL) /*!< Reset value of DEBUGPOWERREQSTATUS register. */ + +/* SYSPWRUPREQUESTED @Bit 0 : System powerup request status */ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Pos (0UL) /*!< Position of SYSPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Msk (0x1UL << TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Pos) /*!< + Bit mask of SYSPWRUPREQUESTED field.*/ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Min (0x0UL) /*!< Min enumerator value of SYSPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Max (0x1UL) /*!< Max enumerator value of SYSPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_NoPowerReq (0x0UL) /*!< Power not requested */ + #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_PowerReq (0x1UL) /*!< Power requested */ + +/* DBGPWRUPREQUESTED @Bit 1 : Debug domain powerup request status */ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Pos (1UL) /*!< Position of DBGPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Msk (0x1UL << TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Pos) /*!< + Bit mask of DBGPWRUPREQUESTED field.*/ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Min (0x0UL) /*!< Min enumerator value of DBGPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Max (0x1UL) /*!< Max enumerator value of DBGPWRUPREQUESTED field. */ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_NoPowerReq (0x0UL) /*!< Power not requested */ + #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_PowerReq (0x1UL) /*!< Power requested */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TEMP ======================================================= */ +/** + * @brief Temperature Sensor + */ + typedef struct { /*!< TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED2[31]; + __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ + __IM uint32_t RESERVED3[96]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED5[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A6; /*!< (@ 0x00000538) Slope of 7th piece wise linear function */ + __IM uint32_t RESERVED6; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B6; /*!< (@ 0x00000558) y-intercept of 7th piece wise linear function */ + __IM uint32_t RESERVED7; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T5; /*!< (@ 0x00000574) End point of 6th piece wise linear function */ + } NRF_TEMP_Type; /*!< Size = 1400 (0x578) */ + +/* TEMP_TASKS_START: Start temperature measurement */ + #define TEMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start temperature measurement */ + #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TEMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TEMP_TASKS_STOP: Stop temperature measurement */ + #define TEMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop temperature measurement */ + #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TEMP_SUBSCRIBE_START: Subscribe configuration for task START */ + #define TEMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TEMP_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TEMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TEMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TEMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TEMP_EVENTS_DATARDY: Temperature measurement complete, data ready */ + #define TEMP_EVENTS_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DATARDY register. */ + +/* EVENTS_DATARDY @Bit 0 : Temperature measurement complete, data ready */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of + EVENTS_DATARDY field.*/ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DATARDY field. */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (0x1UL) /*!< Event generated */ + + +/* TEMP_PUBLISH_DATARDY: Publish configuration for event DATARDY */ + #define TEMP_PUBLISH_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DATARDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event DATARDY will publish to */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TEMP_PUBLISH_DATARDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TEMP_PUBLISH_DATARDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TEMP_PUBLISH_DATARDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TEMP_INTENSET: Enable interrupt */ + #define TEMP_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* DATARDY @Bit 0 : Write '1' to enable interrupt for event DATARDY */ + #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Min (0x0UL) /*!< Min enumerator value of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Max (0x1UL) /*!< Max enumerator value of DATARDY field. */ + #define TEMP_INTENSET_DATARDY_Set (0x1UL) /*!< Enable */ + #define TEMP_INTENSET_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TEMP_INTENSET_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TEMP_INTENCLR: Disable interrupt */ + #define TEMP_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* DATARDY @Bit 0 : Write '1' to disable interrupt for event DATARDY */ + #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Min (0x0UL) /*!< Min enumerator value of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Max (0x1UL) /*!< Max enumerator value of DATARDY field. */ + #define TEMP_INTENCLR_DATARDY_Clear (0x1UL) /*!< Disable */ + #define TEMP_INTENCLR_DATARDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TEMP_INTENCLR_DATARDY_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TEMP_TEMP: Temperature in degC (0.25deg steps) */ + #define TEMP_TEMP_ResetValue (0x00000000UL) /*!< Reset value of TEMP register. */ + +/* TEMP @Bits 0..31 : Temperature in degC (0.25deg steps) */ + #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ + #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + + +/* TEMP_A0: Slope of 1st piece wise linear function */ + #define TEMP_A0_ResetValue (0x00000276UL) /*!< Reset value of A0 register. */ + +/* A0 @Bits 0..11 : Slope of 1st piece wise linear function */ + #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ + #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + + +/* TEMP_A1: Slope of 2nd piece wise linear function */ + #define TEMP_A1_ResetValue (0x00000324UL) /*!< Reset value of A1 register. */ + +/* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */ + #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ + #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + + +/* TEMP_A2: Slope of 3rd piece wise linear function */ + #define TEMP_A2_ResetValue (0x000003ABUL) /*!< Reset value of A2 register. */ + +/* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */ + #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ + #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + + +/* TEMP_A3: Slope of 4th piece wise linear function */ + #define TEMP_A3_ResetValue (0x00000453UL) /*!< Reset value of A3 register. */ + +/* A3 @Bits 0..11 : Slope of 4th piece wise linear function */ + #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ + #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + + +/* TEMP_A4: Slope of 5th piece wise linear function */ + #define TEMP_A4_ResetValue (0x0000049BUL) /*!< Reset value of A4 register. */ + +/* A4 @Bits 0..11 : Slope of 5th piece wise linear function */ + #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ + #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + + +/* TEMP_A5: Slope of 6th piece wise linear function */ + #define TEMP_A5_ResetValue (0x00000550UL) /*!< Reset value of A5 register. */ + +/* A5 @Bits 0..11 : Slope of 6th piece wise linear function */ + #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ + #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + + +/* TEMP_A6: Slope of 7th piece wise linear function */ + #define TEMP_A6_ResetValue (0x0000067EUL) /*!< Reset value of A6 register. */ + +/* A6 @Bits 0..11 : Slope of 7th piece wise linear function */ + #define TEMP_A6_A6_Pos (0UL) /*!< Position of A6 field. */ + #define TEMP_A6_A6_Msk (0xFFFUL << TEMP_A6_A6_Pos) /*!< Bit mask of A6 field. */ + + +/* TEMP_B0: y-intercept of 1st piece wise linear function */ + #define TEMP_B0_ResetValue (0x00000FA6UL) /*!< Reset value of B0 register. */ + +/* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */ + #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ + #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + + +/* TEMP_B1: y-intercept of 2nd piece wise linear function */ + #define TEMP_B1_ResetValue (0x00000F35UL) /*!< Reset value of B1 register. */ + +/* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */ + #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ + #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + + +/* TEMP_B2: y-intercept of 3rd piece wise linear function */ + #define TEMP_B2_ResetValue (0x00000FAAUL) /*!< Reset value of B2 register. */ + +/* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */ + #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ + #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + + +/* TEMP_B3: y-intercept of 4th piece wise linear function */ + #define TEMP_B3_ResetValue (0x0000007EUL) /*!< Reset value of B3 register. */ + +/* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */ + #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ + #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + + +/* TEMP_B4: y-intercept of 5th piece wise linear function */ + #define TEMP_B4_ResetValue (0x000000EAUL) /*!< Reset value of B4 register. */ + +/* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */ + #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ + #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + + +/* TEMP_B5: y-intercept of 6th piece wise linear function */ + #define TEMP_B5_ResetValue (0x000001EDUL) /*!< Reset value of B5 register. */ + +/* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */ + #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ + #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + + +/* TEMP_B6: y-intercept of 7th piece wise linear function */ + #define TEMP_B6_ResetValue (0x00000378UL) /*!< Reset value of B6 register. */ + +/* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */ + #define TEMP_B6_B6_Pos (0UL) /*!< Position of B6 field. */ + #define TEMP_B6_B6_Msk (0xFFFUL << TEMP_B6_B6_Pos) /*!< Bit mask of B6 field. */ + + +/* TEMP_T0: End point of 1st piece wise linear function */ + #define TEMP_T0_ResetValue (0x000000EDUL) /*!< Reset value of T0 register. */ + +/* T0 @Bits 0..7 : End point of 1st piece wise linear function */ + #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ + #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + + +/* TEMP_T1: End point of 2nd piece wise linear function */ + #define TEMP_T1_ResetValue (0x00000013UL) /*!< Reset value of T1 register. */ + +/* T1 @Bits 0..7 : End point of 2nd piece wise linear function */ + #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ + #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + + +/* TEMP_T2: End point of 3rd piece wise linear function */ + #define TEMP_T2_ResetValue (0x00000029UL) /*!< Reset value of T2 register. */ + +/* T2 @Bits 0..7 : End point of 3rd piece wise linear function */ + #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ + #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + + +/* TEMP_T3: End point of 4th piece wise linear function */ + #define TEMP_T3_ResetValue (0x0000003CUL) /*!< Reset value of T3 register. */ + +/* T3 @Bits 0..7 : End point of 4th piece wise linear function */ + #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ + #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + + +/* TEMP_T4: End point of 5th piece wise linear function */ + #define TEMP_T4_ResetValue (0x00000044UL) /*!< Reset value of T4 register. */ + +/* T4 @Bits 0..7 : End point of 5th piece wise linear function */ + #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ + #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* TEMP_T5: End point of 6th piece wise linear function */ + #define TEMP_T5_ResetValue (0x00000053UL) /*!< Reset value of T5 register. */ + +/* T5 @Bits 0..7 : End point of 6th piece wise linear function */ + #define TEMP_T5_T5_Pos (0UL) /*!< Position of T5 field. */ + #define TEMP_T5_T5_Msk (0xFFUL << TEMP_T5_T5_Pos) /*!< Bit mask of T5 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct TIMER ======================================================= */ +/** + * @brief Timer/Counter + */ + typedef struct { /*!< TIMER Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Capture Timer value to CC[n] register */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ + __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ + __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Subscribe configuration for task SHUTDOWN */ + __IM uint32_t RESERVED2[11]; + __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n] */ + __IM uint32_t RESERVED3[24]; + __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Compare event on CC[n] match */ + __IM uint32_t RESERVED4[24]; + __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n] */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED8; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Capture/Compare register n */ + __IM uint32_t RESERVED10[8]; + __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Enable one-shot operation for Capture/Compare channel + n*/ + } NRF_TIMER_Type; /*!< Size = 1440 (0x5A0) */ + +/* TIMER_TASKS_START: Start Timer */ + #define TIMER_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start Timer */ + #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_STOP: Stop Timer */ + #define TIMER_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop Timer */ + #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_COUNT: Increment Timer (Counter mode only) */ + #define TIMER_TASKS_COUNT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COUNT register. */ + +/* TASKS_COUNT @Bit 0 : Increment Timer (Counter mode only) */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Min (0x1UL) /*!< Min enumerator value of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Max (0x1UL) /*!< Max enumerator value of TASKS_COUNT field. */ + #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_CLEAR: Clear time */ + #define TIMER_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register. */ + +/* TASKS_CLEAR @Bit 0 : Clear time */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEAR field. */ + #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_SHUTDOWN: Shut down timer */ + #define TIMER_TASKS_SHUTDOWN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SHUTDOWN register. */ + +/* TASKS_SHUTDOWN @Bit 0 : Shut down timer */ + #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ + #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of + TASKS_SHUTDOWN field.*/ + #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Min (0x1UL) /*!< Min enumerator value of TASKS_SHUTDOWN field. */ + #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Max (0x1UL) /*!< Max enumerator value of TASKS_SHUTDOWN field. */ + #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_TASKS_CAPTURE: Capture Timer value to CC[n] register */ + #define TIMER_TASKS_CAPTURE_MaxCount (8UL) /*!< Max size of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_MaxIndex (7UL) /*!< Max index of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_MinIndex (0UL) /*!< Min index of TASKS_CAPTURE[8] array. */ + #define TIMER_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register. */ + +/* TASKS_CAPTURE @Bit 0 : Capture Timer value to CC[n] register */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE + field.*/ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field. */ + #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ + + +/* TIMER_SUBSCRIBE_START: Subscribe configuration for task START */ + #define TIMER_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TIMER_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_COUNT: Subscribe configuration for task COUNT */ + #define TIMER_SUBSCRIBE_COUNT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COUNT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task COUNT will subscribe to */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_COUNT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */ + #define TIMER_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_SHUTDOWN: Subscribe configuration for task SHUTDOWN */ + #define TIMER_SUBSCRIBE_SHUTDOWN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SHUTDOWN register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SHUTDOWN will subscribe to */ + #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */ + #define TIMER_SUBSCRIBE_CAPTURE_MaxCount (8UL) /*!< Max size of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_MaxIndex (7UL) /*!< Max index of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_MinIndex (0UL) /*!< Min index of SUBSCRIBE_CAPTURE[8] array. */ + #define TIMER_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TIMER_EVENTS_COMPARE: Compare event on CC[n] match */ + #define TIMER_EVENTS_COMPARE_MaxCount (8UL) /*!< Max size of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_MaxIndex (7UL) /*!< Max index of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_MinIndex (0UL) /*!< Min index of EVENTS_COMPARE[8] array. */ + #define TIMER_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register. */ + +/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of + EVENTS_COMPARE field.*/ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field. */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ + #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ + + +/* TIMER_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */ + #define TIMER_PUBLISH_COMPARE_MaxCount (8UL) /*!< Max size of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_MaxIndex (7UL) /*!< Max index of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_MinIndex (0UL) /*!< Min index of PUBLISH_COMPARE[8] array. */ + #define TIMER_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TIMER_PUBLISH_COMPARE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TIMER_SHORTS: Shortcuts between local events and tasks */ + #define TIMER_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE0_CLEAR field. */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE1_CLEAR field. */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE2_CLEAR field. */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE3_CLEAR field. */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE4_CLEAR field. */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE5_CLEAR field. */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL) /*!< Position of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE6_CLEAR field. */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Min (0x0UL) /*!< Min enumerator value of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Max (0x1UL) /*!< Max enumerator value of COMPARE7_CLEAR field. */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE0_STOP @Bit 16 : Shortcut between event COMPARE[0] and task STOP */ + #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE0_STOP field. */ + #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE1_STOP @Bit 17 : Shortcut between event COMPARE[1] and task STOP */ + #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL) /*!< Position of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE1_STOP field. */ + #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE2_STOP @Bit 18 : Shortcut between event COMPARE[2] and task STOP */ + #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL) /*!< Position of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE2_STOP field. */ + #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE3_STOP @Bit 19 : Shortcut between event COMPARE[3] and task STOP */ + #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL) /*!< Position of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE3_STOP field. */ + #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE4_STOP @Bit 20 : Shortcut between event COMPARE[4] and task STOP */ + #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL) /*!< Position of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE4_STOP field. */ + #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE5_STOP @Bit 21 : Shortcut between event COMPARE[5] and task STOP */ + #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL) /*!< Position of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE5_STOP field. */ + #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE6_STOP @Bit 22 : Shortcut between event COMPARE[6] and task STOP */ + #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL) /*!< Position of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos) /*!< Bit mask of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE6_STOP field. */ + #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE6_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* COMPARE7_STOP @Bit 23 : Shortcut between event COMPARE[7] and task STOP */ + #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Min (0x0UL) /*!< Min enumerator value of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Max (0x1UL) /*!< Max enumerator value of COMPARE7_STOP field. */ + #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TIMER_SHORTS_COMPARE7_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TIMER_INTEN: Enable or disable interrupt */ + #define TIMER_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* COMPARE0 @Bit 16 : Enable or disable interrupt for event COMPARE[0] */ + #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE1 @Bit 17 : Enable or disable interrupt for event COMPARE[1] */ + #define TIMER_INTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE2 @Bit 18 : Enable or disable interrupt for event COMPARE[2] */ + #define TIMER_INTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE3 @Bit 19 : Enable or disable interrupt for event COMPARE[3] */ + #define TIMER_INTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE4 @Bit 20 : Enable or disable interrupt for event COMPARE[4] */ + #define TIMER_INTEN_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTEN_COMPARE4_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE4_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE5 @Bit 21 : Enable or disable interrupt for event COMPARE[5] */ + #define TIMER_INTEN_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTEN_COMPARE5_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE5_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE6 @Bit 22 : Enable or disable interrupt for event COMPARE[6] */ + #define TIMER_INTEN_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTEN_COMPARE6_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE6_Enabled (0x1UL) /*!< Enable */ + +/* COMPARE7 @Bit 23 : Enable or disable interrupt for event COMPARE[7] */ + #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTEN_COMPARE7_Disabled (0x0UL) /*!< Disable */ + #define TIMER_INTEN_COMPARE7_Enabled (0x1UL) /*!< Enable */ + + +/* TIMER_INTENSET: Enable interrupt */ + #define TIMER_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ + #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ + #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ + #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ + #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ + #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ + #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */ + #define TIMER_INTENSET_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTENSET_COMPARE6_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */ + #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTENSET_COMPARE7_Set (0x1UL) /*!< Enable */ + #define TIMER_INTENSET_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENSET_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TIMER_INTENCLR: Disable interrupt */ + #define TIMER_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ + #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Min (0x0UL) /*!< Min enumerator value of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Max (0x1UL) /*!< Max enumerator value of COMPARE0 field. */ + #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ + #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Min (0x0UL) /*!< Min enumerator value of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Max (0x1UL) /*!< Max enumerator value of COMPARE1 field. */ + #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ + #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Min (0x0UL) /*!< Min enumerator value of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Max (0x1UL) /*!< Max enumerator value of COMPARE2 field. */ + #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ + #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Min (0x0UL) /*!< Min enumerator value of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Max (0x1UL) /*!< Max enumerator value of COMPARE3 field. */ + #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ + #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Min (0x0UL) /*!< Min enumerator value of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Max (0x1UL) /*!< Max enumerator value of COMPARE4 field. */ + #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ + #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Min (0x0UL) /*!< Min enumerator value of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Max (0x1UL) /*!< Max enumerator value of COMPARE5 field. */ + #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */ + #define TIMER_INTENCLR_COMPARE6_Pos (22UL) /*!< Position of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Min (0x0UL) /*!< Min enumerator value of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Max (0x1UL) /*!< Max enumerator value of COMPARE6 field. */ + #define TIMER_INTENCLR_COMPARE6_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE6_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */ + #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Min (0x0UL) /*!< Min enumerator value of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Max (0x1UL) /*!< Max enumerator value of COMPARE7 field. */ + #define TIMER_INTENCLR_COMPARE7_Clear (0x1UL) /*!< Disable */ + #define TIMER_INTENCLR_COMPARE7_Disabled (0x0UL) /*!< Read: Disabled */ + #define TIMER_INTENCLR_COMPARE7_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TIMER_MODE: Timer mode selection */ + #define TIMER_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : Timer mode */ + #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define TIMER_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define TIMER_MODE_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */ + #define TIMER_MODE_MODE_Counter (0x1UL) /*!< Select Counter mode */ + #define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */ + + +/* TIMER_BITMODE: Configure the number of bits used by the TIMER */ + #define TIMER_BITMODE_ResetValue (0x00000000UL) /*!< Reset value of BITMODE register. */ + +/* BITMODE @Bits 0..1 : Timer bit width */ + #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Min (0x0UL) /*!< Min enumerator value of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_Max (0x3UL) /*!< Max enumerator value of BITMODE field. */ + #define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */ + #define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */ + + +/* TIMER_PRESCALER: Timer prescaler register */ + #define TIMER_PRESCALER_ResetValue (0x00000004UL) /*!< Reset value of PRESCALER register. */ + +/* PRESCALER @Bits 0..3 : Prescaler value */ + #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Min (0x0UL) /*!< Min value of PRESCALER field. */ + #define TIMER_PRESCALER_PRESCALER_Max (0x9UL) /*!< Max size of PRESCALER field. */ + + +/* TIMER_CC: Capture/Compare register n */ + #define TIMER_CC_MaxCount (8UL) /*!< Max size of CC[8] array. */ + #define TIMER_CC_MaxIndex (7UL) /*!< Max index of CC[8] array. */ + #define TIMER_CC_MinIndex (0UL) /*!< Min index of CC[8] array. */ + #define TIMER_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[8] register. */ + +/* CC @Bits 0..31 : Capture/Compare value */ + #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ + #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* TIMER_ONESHOTEN: Enable one-shot operation for Capture/Compare channel n */ + #define TIMER_ONESHOTEN_MaxCount (8UL) /*!< Max size of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_MaxIndex (7UL) /*!< Max index of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_MinIndex (0UL) /*!< Min index of ONESHOTEN[8] array. */ + #define TIMER_ONESHOTEN_ResetValue (0x00000000UL) /*!< Reset value of ONESHOTEN[8] register. */ + +/* ONESHOTEN @Bit 0 : Enable one-shot operation */ + #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Min (0x0UL) /*!< Min enumerator value of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Max (0x1UL) /*!< Max enumerator value of ONESHOTEN field. */ + #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */ + #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TPIU ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct TPIU ======================================================= */ +/** + * @brief Trace Port Interface Unit + */ + typedef struct { /*!< TPIU Structure */ + __IOM uint32_t SUPPORTEDPORTSIZES; /*!< (@ 0x00000000) Each bit location is a single port size that is + supported on the device.*/ + __IOM uint32_t CURRENTPORTSIZE; /*!< (@ 0x00000004) Each bit location is a single port size. One bit can be + set, and indicates the current port size.*/ + __IM uint32_t RESERVED[62]; + __IOM uint32_t SUPPORTEDTRIGGERMODES; /*!< (@ 0x00000100) The Supported_trigger_modes register indicates the + implemented trigger counter multipliers and other + supported features of the trigger system.*/ + __IOM uint32_t TRIGGERCOUNTERVALUE; /*!< (@ 0x00000104) The Trigger_counter_value register enables delaying the + indication of triggers to any external connected trace + capture or storage devices.*/ + __IOM uint32_t TRIGGERMULTIPLIER; /*!< (@ 0x00000108) The Trigger_multiplier register contains the selectors + for the trigger counter multiplier.*/ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SUPPPORTEDTESTPATTERNMODES; /*!< (@ 0x00000200) The Supported_test_pattern_modes register provides a + set of known bit sequences or patterns that can be + output over the trace port and can be detected by the + TPA or other associated trace capture device.*/ + __IOM uint32_t CURRENTTESTPATTERNMODES; /*!< (@ 0x00000204) Current_test_pattern_mode indicates the current test + pattern or mode selected.*/ + __IOM uint32_t TPRCR; /*!< (@ 0x00000208) The TPRCR register is an 8-bit counter start value that + is decremented. A write sets the initial counter value + and a read returns the programmed value.*/ + __IM uint32_t RESERVED2[61]; + __IOM uint32_t FFSR; /*!< (@ 0x00000300) The FFSR register indicates the current status of the + formatter and flush features available in the TPIU.*/ + __IOM uint32_t FFCR; /*!< (@ 0x00000304) The FFCR register controls the generation of stop, + trigger, and flush events.*/ + __IOM uint32_t FSCR; /*!< (@ 0x00000308) The FSCR register enables the frequency of + synchronization information to be optimized to suit the + Trace Port Analyzer (TPA) capture buffer size.*/ + __IM uint32_t RESERVED3[61]; + __IOM uint32_t EXTCTLINPORT; /*!< (@ 0x00000400) Two ports can be used as a control and feedback + mechanism for any serializers, pin sharing + multiplexers, or other solutions that might be added to + the trace output pins either for pin control or a + high-speed trace port solution.*/ + __IOM uint32_t EXTCTLOUTPORT; /*!< (@ 0x00000404) Two ports can be used as a control and feedback + mechanism for any serializers, pin sharing + multiplexers, or other solutions that might be added to + the trace output pins either for pin control or a high + speed trace port solution. These ports are raw register + banks that sample or export the corresponding external + pins.*/ + __IM uint32_t RESERVED4[695]; + __IOM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) The ITTRFLINACK register enables control of the + triginack and flushinack outputs from the TPIU.*/ + __IOM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) The ITTRFLIN register contains the values of the + flushin and trigin inputs to the TPIU.*/ + __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register contains the value of the + atdatas inputs to the TPIU. The values are valid only + when atvalids is HIGH.*/ + __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Enables control of the atreadys and afvalids outputs of + the TPIU.*/ + __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register contains the value of the atids + input to the TPIU. This is only valid when atvalids is + HIGH.*/ + __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register captures the values of the + atvalids, afreadys, and atbytess inputs to the TPIU. To + ensure the integration registers work correctly in a + system, the value of atbytess is only valid when + atvalids, bit[0], is HIGH.*/ + __IM uint32_t RESERVED5; + __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Used to enable topology detection. This register + enables the component to switch from a functional mode, + the default behavior, to integration mode where the + inputs and outputs of the component can be directly + controlled for integration testing and topology + solving.*/ + __IM uint32_t RESERVED6[39]; + __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMSET register sets + bits in the claim tag, and determines the number of + claim bits implemented.*/ + __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate + application and debugger access to trace unit + functionality. The claim tags have no effect on the + operation of the component. The CLAIMCLR register sets + the bits in the claim tag to 0 and determines the + current value of the claim tag.*/ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device + registers.*/ + __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control + mechanism. This lock prevents accidental writes by code + under debug. Accesses to the extended stimulus port + registers are not affected by the lock mechanism. This + register must always be present although there might + not be any lock access control mechanism. The lock + mechanism, where present and locked, must block write + accesses to any control register, except the Lock + Access Register. For most components this covers all + registers except for the Lock Access Register.*/ + __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the + system*/ + __IM uint32_t RESERVED8[3]; + __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ + __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with + information about the component when the Part Number + field is not recognized. The debugger can then report + this information.*/ + __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t PIDR0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ + __IOM uint32_t PIDR3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ + __IOM uint32_t CIDR0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ + __IOM uint32_t CIDR1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ + __IOM uint32_t CIDR2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ + __IOM uint32_t CIDR3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ + } NRF_TPIU_Type; /*!< Size = 4096 (0x1000) */ + +/* TPIU_SUPPORTEDPORTSIZES: Each bit location is a single port size that is supported on the device. */ + #define TPIU_SUPPORTEDPORTSIZES_ResetValue (0x00000000UL) /*!< Reset value of SUPPORTEDPORTSIZES register. */ + +/* PORT_SIZE_1 @Bit 0 : Indicates whether the TPIU supports port size of 1-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos) /*!< Bit mask of + PORT_SIZE_1 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_1 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_1 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_NotSupported (0x0UL) /*!< Port size 1 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Supported (0x1UL) /*!< Port size 1 is supported. */ + +/* PORT_SIZE_2 @Bit 1 : Indicates whether the TPIU supports port size of 2-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos) /*!< Bit mask of + PORT_SIZE_2 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_2 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_2 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_NotSupported (0x0UL) /*!< Port size 2 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Supported (0x1UL) /*!< Port size 2 is supported. */ + +/* PORT_SIZE_3 @Bit 2 : Indicates whether the TPIU supports port size of 3-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos) /*!< Bit mask of + PORT_SIZE_3 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_3 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_3 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_NotSupported (0x0UL) /*!< Port size 3 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Supported (0x1UL) /*!< Port size 3 is supported. */ + +/* PORT_SIZE_4 @Bit 3 : Indicates whether the TPIU supports port size of 4-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos) /*!< Bit mask of + PORT_SIZE_4 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_4 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_4 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_NotSupported (0x0UL) /*!< Port size 4 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Supported (0x1UL) /*!< Port size 4 is supported. */ + +/* PORT_SIZE_5 @Bit 4 : Indicates whether the TPIU supports port size of 5-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos) /*!< Bit mask of + PORT_SIZE_5 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_5 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_5 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_NotSupported (0x0UL) /*!< Port size 5 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Supported (0x1UL) /*!< Port size 5 is supported. */ + +/* PORT_SIZE_6 @Bit 5 : Indicates whether the TPIU supports port size of 6-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos) /*!< Bit mask of + PORT_SIZE_6 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_6 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_6 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_NotSupported (0x0UL) /*!< Port size 6 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Supported (0x1UL) /*!< Port size 6 is supported. */ + +/* PORT_SIZE_7 @Bit 6 : Indicates whether the TPIU supports port size of 7-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos) /*!< Bit mask of + PORT_SIZE_7 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_7 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_7 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_NotSupported (0x0UL) /*!< Port size 7 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Supported (0x1UL) /*!< Port size 7 is supported. */ + +/* PORT_SIZE_8 @Bit 7 : Indicates whether the TPIU supports port size of 8-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos) /*!< Bit mask of + PORT_SIZE_8 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_8 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_8 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_NotSupported (0x0UL) /*!< Port size 8 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Supported (0x1UL) /*!< Port size 8 is supported. */ + +/* PORT_SIZE_9 @Bit 8 : Indicates whether the TPIU supports port size of 9-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos) /*!< Bit mask of + PORT_SIZE_9 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_9 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_9 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_NotSupported (0x0UL) /*!< Port size 9 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Supported (0x1UL) /*!< Port size 9 is supported. */ + +/* PORT_SIZE_10 @Bit 9 : Indicates whether the TPIU supports port size of 10-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos) /*!< Bit mask of + PORT_SIZE_10 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_10 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_10 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_NotSupported (0x0UL) /*!< Port size 10 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Supported (0x1UL) /*!< Port size 10 is supported. */ + +/* PORT_SIZE_11 @Bit 10 : Indicates whether the TPIU supports port size of 11-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos) /*!< Bit mask of + PORT_SIZE_11 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_11 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_11 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_NotSupported (0x0UL) /*!< Port size 11 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Supported (0x1UL) /*!< Port size 11 is supported. */ + +/* PORT_SIZE_12 @Bit 11 : Indicates whether the TPIU supports port size of 12-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos) /*!< Bit mask of + PORT_SIZE_12 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_12 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_12 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_NotSupported (0x0UL) /*!< Port size 12 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Supported (0x1UL) /*!< Port size 12 is supported. */ + +/* PORT_SIZE_13 @Bit 12 : Indicates whether the TPIU supports port size of 13-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos) /*!< Bit mask of + PORT_SIZE_13 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_13 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_13 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_NotSupported (0x0UL) /*!< Port size 13 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Supported (0x1UL) /*!< Port size 13 is supported. */ + +/* PORT_SIZE_14 @Bit 13 : Indicates whether the TPIU supports port size of 14-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos) /*!< Bit mask of + PORT_SIZE_14 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_14 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_14 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_NotSupported (0x0UL) /*!< Port size 14 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Supported (0x1UL) /*!< Port size 14 is supported. */ + +/* PORT_SIZE_15 @Bit 14 : Indicates whether the TPIU supports port size of 15-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos) /*!< Bit mask of + PORT_SIZE_15 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_15 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_15 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_NotSupported (0x0UL) /*!< Port size 15 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Supported (0x1UL) /*!< Port size 15 is supported. */ + +/* PORT_SIZE_16 @Bit 15 : Indicates whether the TPIU supports port size of 16-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos) /*!< Bit mask of + PORT_SIZE_16 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_16 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_16 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_NotSupported (0x0UL) /*!< Port size 16 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Supported (0x1UL) /*!< Port size 16 is supported. */ + +/* PORT_SIZE_17 @Bit 16 : Indicates whether the TPIU supports port size of 17-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos) /*!< Bit mask of + PORT_SIZE_17 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_17 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_17 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_NotSupported (0x0UL) /*!< Port size 17 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Supported (0x1UL) /*!< Port size 17 is supported. */ + +/* PORT_SIZE_18 @Bit 17 : Indicates whether the TPIU supports port size of 18-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos) /*!< Bit mask of + PORT_SIZE_18 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_18 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_18 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_NotSupported (0x0UL) /*!< Port size 18 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Supported (0x1UL) /*!< Port size 18 is supported. */ + +/* PORT_SIZE_19 @Bit 18 : Indicates whether the TPIU supports port size of 19-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos) /*!< Bit mask of + PORT_SIZE_19 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_19 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_19 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_NotSupported (0x0UL) /*!< Port size 19 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Supported (0x1UL) /*!< Port size 19 is supported. */ + +/* PORT_SIZE_20 @Bit 19 : Indicates whether the TPIU supports port size of 20-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos) /*!< Bit mask of + PORT_SIZE_20 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_20 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_20 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_NotSupported (0x0UL) /*!< Port size 20 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Supported (0x1UL) /*!< Port size 20 is supported. */ + +/* PORT_SIZE_21 @Bit 20 : Indicates whether the TPIU supports port size of 21-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos) /*!< Bit mask of + PORT_SIZE_21 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_21 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_21 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_NotSupported (0x0UL) /*!< Port size 21 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Supported (0x1UL) /*!< Port size 21 is supported. */ + +/* PORT_SIZE_22 @Bit 21 : Indicates whether the TPIU supports port size of 22-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos) /*!< Bit mask of + PORT_SIZE_22 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_22 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_22 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_NotSupported (0x0UL) /*!< Port size 22 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Supported (0x1UL) /*!< Port size 22 is supported. */ + +/* PORT_SIZE_23 @Bit 22 : Indicates whether the TPIU supports port size of 23-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos) /*!< Bit mask of + PORT_SIZE_23 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_23 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_23 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_NotSupported (0x0UL) /*!< Port size 23 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Supported (0x1UL) /*!< Port size 23 is supported. */ + +/* PORT_SIZE_24 @Bit 23 : Indicates whether the TPIU supports port size of 24-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos) /*!< Bit mask of + PORT_SIZE_24 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_24 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_24 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_NotSupported (0x0UL) /*!< Port size 24 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Supported (0x1UL) /*!< Port size 24 is supported. */ + +/* PORT_SIZE_25 @Bit 24 : Indicates whether the TPIU supports port size of 25-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos) /*!< Bit mask of + PORT_SIZE_25 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_25 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_25 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_NotSupported (0x0UL) /*!< Port size 25 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Supported (0x1UL) /*!< Port size 25 is supported. */ + +/* PORT_SIZE_26 @Bit 25 : Indicates whether the TPIU supports port size of 26-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos) /*!< Bit mask of + PORT_SIZE_26 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_26 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_26 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_NotSupported (0x0UL) /*!< Port size 26 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Supported (0x1UL) /*!< Port size 26 is supported. */ + +/* PORT_SIZE_27 @Bit 26 : Indicates whether the TPIU supports port size of 27-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos) /*!< Bit mask of + PORT_SIZE_27 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_27 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_27 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_NotSupported (0x0UL) /*!< Port size 27 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Supported (0x1UL) /*!< Port size 27 is supported. */ + +/* PORT_SIZE_28 @Bit 27 : Indicates whether the TPIU supports port size of 28-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos) /*!< Bit mask of + PORT_SIZE_28 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_28 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_28 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_NotSupported (0x0UL) /*!< Port size 28 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Supported (0x1UL) /*!< Port size 28 is supported. */ + +/* PORT_SIZE_29 @Bit 28 : Indicates whether the TPIU supports port size of 29-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos) /*!< Bit mask of + PORT_SIZE_29 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_29 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_29 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_NotSupported (0x0UL) /*!< Port size 29 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Supported (0x1UL) /*!< Port size 29 is supported. */ + +/* PORT_SIZE_30 @Bit 29 : Indicates whether the TPIU supports port size of 30-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos) /*!< Bit mask of + PORT_SIZE_30 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_30 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_30 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_NotSupported (0x0UL) /*!< Port size 30 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Supported (0x1UL) /*!< Port size 30 is supported. */ + +/* PORT_SIZE_31 @Bit 30 : Indicates whether the TPIU supports port size of 31-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos) /*!< Bit mask of + PORT_SIZE_31 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_31 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_31 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_NotSupported (0x0UL) /*!< Port size 31 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Supported (0x1UL) /*!< Port size 31 is supported. */ + +/* PORT_SIZE_32 @Bit 31 : Indicates whether the TPIU supports port size of 32-bit. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos) /*!< Bit mask of + PORT_SIZE_32 field.*/ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_32 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_32 field. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_NotSupported (0x0UL) /*!< Port size 32 is not supported. */ + #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Supported (0x1UL) /*!< Port size 32 is supported. */ + + +/* TPIU_CURRENTPORTSIZE: Each bit location is a single port size. One bit can be set, and indicates the current port size. */ + #define TPIU_CURRENTPORTSIZE_ResetValue (0x00000000UL) /*!< Reset value of CURRENTPORTSIZE register. */ + +/* PORT_SIZE_1 @Bit 0 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_1 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_1 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_NotSelected (0x0UL) /*!< Port size 1 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Selected (0x1UL) /*!< Port size 1 is selected. */ + +/* PORT_SIZE_2 @Bit 1 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_2 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_2 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_NotSelected (0x0UL) /*!< Port size 2 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Selected (0x1UL) /*!< Port size 2 is selected. */ + +/* PORT_SIZE_3 @Bit 2 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_3 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_3 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_NotSelected (0x0UL) /*!< Port size 3 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Selected (0x1UL) /*!< Port size 3 is selected. */ + +/* PORT_SIZE_4 @Bit 3 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_4 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_4 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_NotSelected (0x0UL) /*!< Port size 4 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Selected (0x1UL) /*!< Port size 4 is selected. */ + +/* PORT_SIZE_5 @Bit 4 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_5 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_5 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_NotSelected (0x0UL) /*!< Port size 5 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Selected (0x1UL) /*!< Port size 5 is selected. */ + +/* PORT_SIZE_6 @Bit 5 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_6 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_6 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_NotSelected (0x0UL) /*!< Port size 6 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Selected (0x1UL) /*!< Port size 6 is selected. */ + +/* PORT_SIZE_7 @Bit 6 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_7 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_7 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_NotSelected (0x0UL) /*!< Port size 7 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Selected (0x1UL) /*!< Port size 7 is selected. */ + +/* PORT_SIZE_8 @Bit 7 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_8 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_8 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_NotSelected (0x0UL) /*!< Port size 8 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Selected (0x1UL) /*!< Port size 8 is selected. */ + +/* PORT_SIZE_9 @Bit 8 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_9 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_9 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_NotSelected (0x0UL) /*!< Port size 9 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Selected (0x1UL) /*!< Port size 9 is selected. */ + +/* PORT_SIZE_10 @Bit 9 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_10 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_10 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_NotSelected (0x0UL) /*!< Port size 10 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Selected (0x1UL) /*!< Port size 10 is selected. */ + +/* PORT_SIZE_11 @Bit 10 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_11 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_11 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_NotSelected (0x0UL) /*!< Port size 11 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Selected (0x1UL) /*!< Port size 11 is selected. */ + +/* PORT_SIZE_12 @Bit 11 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_12 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_12 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_NotSelected (0x0UL) /*!< Port size 12 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Selected (0x1UL) /*!< Port size 12 is selected. */ + +/* PORT_SIZE_13 @Bit 12 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_13 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_13 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_NotSelected (0x0UL) /*!< Port size 13 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Selected (0x1UL) /*!< Port size 13 is selected. */ + +/* PORT_SIZE_14 @Bit 13 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_14 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_14 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_NotSelected (0x0UL) /*!< Port size 14 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Selected (0x1UL) /*!< Port size 14 is selected. */ + +/* PORT_SIZE_15 @Bit 14 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_15 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_15 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_NotSelected (0x0UL) /*!< Port size 15 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Selected (0x1UL) /*!< Port size 15 is selected. */ + +/* PORT_SIZE_16 @Bit 15 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_16 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_16 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_NotSelected (0x0UL) /*!< Port size 16 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Selected (0x1UL) /*!< Port size 16 is selected. */ + +/* PORT_SIZE_17 @Bit 16 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_17 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_17 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_NotSelected (0x0UL) /*!< Port size 17 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Selected (0x1UL) /*!< Port size 17 is selected. */ + +/* PORT_SIZE_18 @Bit 17 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_18 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_18 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_NotSelected (0x0UL) /*!< Port size 18 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Selected (0x1UL) /*!< Port size 18 is selected. */ + +/* PORT_SIZE_19 @Bit 18 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_19 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_19 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_NotSelected (0x0UL) /*!< Port size 19 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Selected (0x1UL) /*!< Port size 19 is selected. */ + +/* PORT_SIZE_20 @Bit 19 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_20 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_20 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_NotSelected (0x0UL) /*!< Port size 20 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Selected (0x1UL) /*!< Port size 20 is selected. */ + +/* PORT_SIZE_21 @Bit 20 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_21 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_21 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_NotSelected (0x0UL) /*!< Port size 21 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Selected (0x1UL) /*!< Port size 21 is selected. */ + +/* PORT_SIZE_22 @Bit 21 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_22 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_22 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_NotSelected (0x0UL) /*!< Port size 22 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Selected (0x1UL) /*!< Port size 22 is selected. */ + +/* PORT_SIZE_23 @Bit 22 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_23 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_23 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_NotSelected (0x0UL) /*!< Port size 23 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Selected (0x1UL) /*!< Port size 23 is selected. */ + +/* PORT_SIZE_24 @Bit 23 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_24 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_24 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_NotSelected (0x0UL) /*!< Port size 24 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Selected (0x1UL) /*!< Port size 24 is selected. */ + +/* PORT_SIZE_25 @Bit 24 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_25 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_25 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_NotSelected (0x0UL) /*!< Port size 25 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Selected (0x1UL) /*!< Port size 25 is selected. */ + +/* PORT_SIZE_26 @Bit 25 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_26 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_26 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_NotSelected (0x0UL) /*!< Port size 26 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Selected (0x1UL) /*!< Port size 26 is selected. */ + +/* PORT_SIZE_27 @Bit 26 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_27 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_27 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_NotSelected (0x0UL) /*!< Port size 27 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Selected (0x1UL) /*!< Port size 27 is selected. */ + +/* PORT_SIZE_28 @Bit 27 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_28 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_28 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_NotSelected (0x0UL) /*!< Port size 28 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Selected (0x1UL) /*!< Port size 28 is selected. */ + +/* PORT_SIZE_29 @Bit 28 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_29 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_29 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_NotSelected (0x0UL) /*!< Port size 29 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Selected (0x1UL) /*!< Port size 29 is selected. */ + +/* PORT_SIZE_30 @Bit 29 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_30 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_30 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_NotSelected (0x0UL) /*!< Port size 30 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Selected (0x1UL) /*!< Port size 30 is selected. */ + +/* PORT_SIZE_31 @Bit 30 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_31 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_31 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_NotSelected (0x0UL) /*!< Port size 31 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Selected (0x1UL) /*!< Port size 31 is selected. */ + +/* PORT_SIZE_32 @Bit 31 : Indicates which port size is currently selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32 + field.*/ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_32 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_32 field. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_NotSelected (0x0UL) /*!< Port size 32 is not selected. */ + #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Selected (0x1UL) /*!< Port size 32 is selected. */ + + +/* TPIU_SUPPORTEDTRIGGERMODES: The Supported_trigger_modes register indicates the implemented trigger counter multipliers and + other supported features of the trigger system. */ + + #define TPIU_SUPPORTEDTRIGGERMODES_ResetValue (0x00000000UL) /*!< Reset value of SUPPORTEDTRIGGERMODES register. */ + +/* MULT0 @Bit 0 : Indicates whether multiplying the trigger counter by 2^(0+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Pos (0UL) /*!< Position of MULT0 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT0_Pos) /*!< Bit mask of MULT0 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Min (0x0UL) /*!< Min enumerator value of MULT0 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Max (0x1UL) /*!< Max enumerator value of MULT0 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */ + +/* MULT1 @Bit 1 : Indicates whether multiplying the trigger counter by 2^(1+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Pos (1UL) /*!< Position of MULT1 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT1_Pos) /*!< Bit mask of MULT1 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Min (0x0UL) /*!< Min enumerator value of MULT1 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Max (0x1UL) /*!< Max enumerator value of MULT1 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */ + +/* MULT2 @Bit 2 : Indicates whether multiplying the trigger counter by 2^(2+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Pos (2UL) /*!< Position of MULT2 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT2_Pos) /*!< Bit mask of MULT2 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Min (0x0UL) /*!< Min enumerator value of MULT2 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Max (0x1UL) /*!< Max enumerator value of MULT2 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */ + +/* MULT3 @Bit 3 : Indicates whether multiplying the trigger counter by 2^(3+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Pos (3UL) /*!< Position of MULT3 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT3_Pos) /*!< Bit mask of MULT3 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Min (0x0UL) /*!< Min enumerator value of MULT3 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Max (0x1UL) /*!< Max enumerator value of MULT3 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */ + +/* MULT4 @Bit 4 : Indicates whether multiplying the trigger counter by 2^(4+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Pos (4UL) /*!< Position of MULT4 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT4_Pos) /*!< Bit mask of MULT4 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Min (0x0UL) /*!< Min enumerator value of MULT4 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Max (0x1UL) /*!< Max enumerator value of MULT4 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */ + #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */ + +/* TCOUNT8 @Bit 8 : Indicates whether an 8-bit wide counter register is implemented. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos (8UL) /*!< Position of TCOUNT8 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos) /*!< Bit mask of TCOUNT8 + field.*/ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Min (0x0UL) /*!< Min enumerator value of TCOUNT8 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Max (0x1UL) /*!< Max enumerator value of TCOUNT8 field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_NotImplemented (0x0UL) /*!< An 8-bit wide counter register is implemented. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Implemented (0x1UL) /*!< An 8-bit wide counter register is implemented. */ + +/* TRIGGERED @Bit 16 : A trigger has occurred and the counter has reached 0. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos (16UL) /*!< Position of TRIGGERED field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos) /*!< Bit mask of + TRIGGERED field.*/ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of TRIGGERED field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of TRIGGERED field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_NotOccured (0x0UL) /*!< Trigger has not occurred. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Occured (0x1UL) /*!< Trigger has occurred. */ + +/* TRGRUN @Bit 17 : A trigger has occurred but the counter is not at 0. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos (17UL) /*!< Position of TRGRUN field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos) /*!< Bit mask of TRGRUN field.*/ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Min (0x0UL) /*!< Min enumerator value of TRGRUN field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Max (0x1UL) /*!< Max enumerator value of TRGRUN field. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_NotOccured (0x0UL) /*!< Either a trigger has not occurred or the counter is at 0. */ + #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Occured (0x1UL) /*!< A trigger has occurred but the counter is not at 0. */ + + +/* TPIU_TRIGGERCOUNTERVALUE: The Trigger_counter_value register enables delaying the indication of triggers to any external + connected trace capture or storage devices. */ + + #define TPIU_TRIGGERCOUNTERVALUE_ResetValue (0x00000000UL) /*!< Reset value of TRIGGERCOUNTERVALUE register. */ + +/* TrigCount @Bits 0..7 : 8-bit counter value for the number of words to be output from the formatter before a trigger is + inserted. */ + + #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos (0UL) /*!< Position of TrigCount field. */ + #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Msk (0xFFUL << TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos) /*!< Bit mask of TrigCount + field.*/ + #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Min (0x00UL) /*!< Min value of TrigCount field. */ + #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Max (0xFFUL) /*!< Max size of TrigCount field. */ + + +/* TPIU_TRIGGERMULTIPLIER: The Trigger_multiplier register contains the selectors for the trigger counter multiplier. */ + #define TPIU_TRIGGERMULTIPLIER_ResetValue (0x00000000UL) /*!< Reset value of TRIGGERMULTIPLIER register. */ + +/* MULT0 @Bit 0 : Multiply the Trigger Counter by 2^n. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Pos (0UL) /*!< Position of MULT0 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT0_Pos) /*!< Bit mask of MULT0 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Min (0x0UL) /*!< Min enumerator value of MULT0 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Max (0x1UL) /*!< Max enumerator value of MULT0 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Disabled (0x0UL) /*!< Multiplier disabled. */ + #define TPIU_TRIGGERMULTIPLIER_MULT0_Enabled (0x1UL) /*!< Multiplier enabled. */ + +/* MULT1 @Bit 1 : Multiply the Trigger Counter by 2^n. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Pos (1UL) /*!< Position of MULT1 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT1_Pos) /*!< Bit mask of MULT1 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Min (0x0UL) /*!< Min enumerator value of MULT1 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Max (0x1UL) /*!< Max enumerator value of MULT1 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Disabled (0x0UL) /*!< Multiplier disabled. */ + #define TPIU_TRIGGERMULTIPLIER_MULT1_Enabled (0x1UL) /*!< Multiplier enabled. */ + +/* MULT2 @Bit 2 : Multiply the Trigger Counter by 2^n. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Pos (2UL) /*!< Position of MULT2 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT2_Pos) /*!< Bit mask of MULT2 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Min (0x0UL) /*!< Min enumerator value of MULT2 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Max (0x1UL) /*!< Max enumerator value of MULT2 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Disabled (0x0UL) /*!< Multiplier disabled. */ + #define TPIU_TRIGGERMULTIPLIER_MULT2_Enabled (0x1UL) /*!< Multiplier enabled. */ + +/* MULT3 @Bit 3 : Multiply the Trigger Counter by 2^n. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Pos (3UL) /*!< Position of MULT3 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT3_Pos) /*!< Bit mask of MULT3 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Min (0x0UL) /*!< Min enumerator value of MULT3 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Max (0x1UL) /*!< Max enumerator value of MULT3 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Disabled (0x0UL) /*!< Multiplier disabled. */ + #define TPIU_TRIGGERMULTIPLIER_MULT3_Enabled (0x1UL) /*!< Multiplier enabled. */ + +/* MULT4 @Bit 4 : Multiply the Trigger Counter by 2^n. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Pos (4UL) /*!< Position of MULT4 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT4_Pos) /*!< Bit mask of MULT4 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Min (0x0UL) /*!< Min enumerator value of MULT4 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Max (0x1UL) /*!< Max enumerator value of MULT4 field. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Disabled (0x0UL) /*!< Multiplier disabled. */ + #define TPIU_TRIGGERMULTIPLIER_MULT4_Enabled (0x1UL) /*!< Multiplier enabled. */ + + +/* TPIU_SUPPPORTEDTESTPATTERNMODES: The Supported_test_pattern_modes register provides a set of known bit sequences or patterns + that can be output over the trace port and can be detected by the TPA or other associated + trace capture device. */ + + #define TPIU_SUPPPORTEDTESTPATTERNMODES_ResetValue (0x00000000UL) /*!< Reset value of SUPPPORTEDTESTPATTERNMODES register. */ + +/* PATW1 @Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 + field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Min (0x0UL) /*!< Min enumerator value of PATW1 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Max (0x1UL) /*!< Max enumerator value of PATW1 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_NotSupported (0x0UL) /*!< Test pattern is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Supported (0x1UL) /*!< Test pattern is supported. */ + +/* PATW0 @Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 + field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Min (0x0UL) /*!< Min enumerator value of PATW0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Max (0x1UL) /*!< Max enumerator value of PATW0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_NotSupported (0x0UL) /*!< Test pattern is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Supported (0x1UL) /*!< Test pattern is supported. */ + +/* PATA5 @Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 + field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Min (0x0UL) /*!< Min enumerator value of PATA5 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Max (0x1UL) /*!< Max enumerator value of PATA5 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_NotSupported (0x0UL) /*!< Test pattern is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Supported (0x1UL) /*!< Test pattern is supported. */ + +/* PATF0 @Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 + field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Min (0x0UL) /*!< Min enumerator value of PATF0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Max (0x1UL) /*!< Max enumerator value of PATF0 field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_NotSupported (0x0UL) /*!< Test pattern is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Supported (0x1UL) /*!< Test pattern is supported. */ + +/* PTIMEEN @Bit 16 : Indicates whether timed mode is supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of + PTIMEEN field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Min (0x0UL) /*!< Min enumerator value of PTIMEEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Max (0x1UL) /*!< Max enumerator value of PTIMEEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_NotSupported (0x0UL) /*!< Mode is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Supported (0x1UL) /*!< Mode is supported. */ + +/* PCONTEN @Bit 17 : Indicates whether continuous mode is supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of + PCONTEN field.*/ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Min (0x0UL) /*!< Min enumerator value of PCONTEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Max (0x1UL) /*!< Max enumerator value of PCONTEN field. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_NotSupported (0x0UL) /*!< Mode is not supported. */ + #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Supported (0x1UL) /*!< Mode is supported. */ + + +/* TPIU_CURRENTTESTPATTERNMODES: Current_test_pattern_mode indicates the current test pattern or mode selected. */ + #define TPIU_CURRENTTESTPATTERNMODES_ResetValue (0x00000000UL) /*!< Reset value of CURRENTTESTPATTERNMODES register. */ + +/* PATW1 @Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Min (0x0UL) /*!< Min enumerator value of PATW1 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Max (0x1UL) /*!< Max enumerator value of PATW1 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Disabled (0x0UL) /*!< Test pattern is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Enabled (0x1UL) /*!< Test pattern is enabled. */ + +/* PATW0 @Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Min (0x0UL) /*!< Min enumerator value of PATW0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Max (0x1UL) /*!< Max enumerator value of PATW0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Disabled (0x0UL) /*!< Test pattern is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Enabled (0x1UL) /*!< Test pattern is enabled. */ + +/* PATA5 @Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Min (0x0UL) /*!< Min enumerator value of PATA5 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Max (0x1UL) /*!< Max enumerator value of PATA5 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Disabled (0x0UL) /*!< Test pattern is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Enabled (0x1UL) /*!< Test pattern is enabled. */ + +/* PATF0 @Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Min (0x0UL) /*!< Min enumerator value of PATF0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Max (0x1UL) /*!< Max enumerator value of PATF0 field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Disabled (0x0UL) /*!< Test pattern is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Enabled (0x1UL) /*!< Test pattern is enabled. */ + +/* PTIMEEN @Bit 16 : Indicates whether timed mode is supported. */ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Min (0x0UL) /*!< Min enumerator value of PTIMEEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Max (0x1UL) /*!< Max enumerator value of PTIMEEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Disabled (0x0UL) /*!< Mode is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Enabled (0x1UL) /*!< Mode is enabled. */ + +/* PCONTEN @Bit 17 : Indicates whether continuous mode is supported. */ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN + field.*/ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Min (0x0UL) /*!< Min enumerator value of PCONTEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Max (0x1UL) /*!< Max enumerator value of PCONTEN field. */ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Disabled (0x0UL) /*!< Mode is disabled. */ + #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Enabled (0x1UL) /*!< Mode is enabled. */ + + +/* TPIU_TPRCR: The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value + and a read returns the programmed value. */ + + #define TPIU_TPRCR_ResetValue (0x00000000UL) /*!< Reset value of TPRCR register. */ + +/* PATTCOUNT @Bits 0..7 : 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it + switches to the next pattern. */ + + #define TPIU_TPRCR_PATTCOUNT_Pos (0UL) /*!< Position of PATTCOUNT field. */ + #define TPIU_TPRCR_PATTCOUNT_Msk (0xFFUL << TPIU_TPRCR_PATTCOUNT_Pos) /*!< Bit mask of PATTCOUNT field. */ + #define TPIU_TPRCR_PATTCOUNT_Min (0x00UL) /*!< Min value of PATTCOUNT field. */ + #define TPIU_TPRCR_PATTCOUNT_Max (0xFFUL) /*!< Max size of PATTCOUNT field. */ + + +/* TPIU_FFSR: The FFSR register indicates the current status of the formatter and flush features available in the TPIU. */ + #define TPIU_FFSR_ResetValue (0x00000000UL) /*!< Reset value of FFSR register. */ + +/* FLINPROG @Bit 0 : Flush in progress. */ + #define TPIU_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */ + #define TPIU_FFSR_FLINPROG_Msk (0x1UL << TPIU_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */ + #define TPIU_FFSR_FLINPROG_Min (0x0UL) /*!< Min enumerator value of FLINPROG field. */ + #define TPIU_FFSR_FLINPROG_Max (0x1UL) /*!< Max enumerator value of FLINPROG field. */ + #define TPIU_FFSR_FLINPROG_NotInProgress (0x0UL) /*!< A flush is not in progress. */ + #define TPIU_FFSR_FLINPROG_InProgress (0x1UL) /*!< A flush is in progress. */ + +/* FTSTOPPED @Bit 1 : The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional + trace data on the ATB interface is ignored and atreadys goes HIGH. */ + + #define TPIU_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */ + #define TPIU_FFSR_FTSTOPPED_Msk (0x1UL << TPIU_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */ + #define TPIU_FFSR_FTSTOPPED_Min (0x0UL) /*!< Min enumerator value of FTSTOPPED field. */ + #define TPIU_FFSR_FTSTOPPED_Max (0x1UL) /*!< Max enumerator value of FTSTOPPED field. */ + #define TPIU_FFSR_FTSTOPPED_Running (0x0UL) /*!< Formatter has not stopped. */ + #define TPIU_FFSR_FTSTOPPED_Stopped (0x1UL) /*!< Formatter has stopped. */ + +/* TCPRESENT @Bit 2 : Indicates whether the TRACECTL pin is available for use. */ + #define TPIU_FFSR_TCPRESENT_Pos (2UL) /*!< Position of TCPRESENT field. */ + #define TPIU_FFSR_TCPRESENT_Msk (0x1UL << TPIU_FFSR_TCPRESENT_Pos) /*!< Bit mask of TCPRESENT field. */ + #define TPIU_FFSR_TCPRESENT_Min (0x0UL) /*!< Min enumerator value of TCPRESENT field. */ + #define TPIU_FFSR_TCPRESENT_Max (0x1UL) /*!< Max enumerator value of TCPRESENT field. */ + #define TPIU_FFSR_TCPRESENT_NotPresent (0x0UL) /*!< TRACECTL pin is not present. */ + #define TPIU_FFSR_TCPRESENT_Present (0x1UL) /*!< TRACECTL pin is present. */ + + +/* TPIU_FFCR: The FFCR register controls the generation of stop, trigger, and flush events. */ + #define TPIU_FFCR_ResetValue (0x00000000UL) /*!< Reset value of FFCR register. */ + +/* ENFTC @Bit 0 : Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, + where present. */ + + #define TPIU_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */ + #define TPIU_FFCR_ENFTC_Msk (0x1UL << TPIU_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */ + #define TPIU_FFCR_ENFTC_Min (0x0UL) /*!< Min enumerator value of ENFTC field. */ + #define TPIU_FFCR_ENFTC_Max (0x1UL) /*!< Max enumerator value of ENFTC field. */ + #define TPIU_FFCR_ENFTC_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_ENFTC_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* ENFCONT @Bit 1 : Is embedded in trigger packets and indicates that no cycle is using sync packets. */ + #define TPIU_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */ + #define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */ + #define TPIU_FFCR_ENFCONT_Min (0x0UL) /*!< Min enumerator value of ENFCONT field. */ + #define TPIU_FFCR_ENFCONT_Max (0x1UL) /*!< Max enumerator value of ENFCONT field. */ + #define TPIU_FFCR_ENFCONT_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_ENFCONT_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* FONFLIN @Bit 4 : Enables the use of the flushin connection. */ + #define TPIU_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */ + #define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */ + #define TPIU_FFCR_FONFLIN_Min (0x0UL) /*!< Min enumerator value of FONFLIN field. */ + #define TPIU_FFCR_FONFLIN_Max (0x1UL) /*!< Max enumerator value of FONFLIN field. */ + #define TPIU_FFCR_FONFLIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_FONFLIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* FONTRIG @Bit 5 : Initiates a manual flush of data in the system when a trigger event occurs. */ + #define TPIU_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */ + #define TPIU_FFCR_FONTRIG_Msk (0x1UL << TPIU_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */ + #define TPIU_FFCR_FONTRIG_Min (0x0UL) /*!< Min enumerator value of FONTRIG field. */ + #define TPIU_FFCR_FONTRIG_Max (0x1UL) /*!< Max enumerator value of FONTRIG field. */ + #define TPIU_FFCR_FONTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_FONTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* FONMANR @Bit 6 : Generates a flush. This bit is set to 0 when this flush is serviced. */ + #define TPIU_FFCR_FONMANR_Pos (6UL) /*!< Position of FONMANR field. */ + #define TPIU_FFCR_FONMANR_Msk (0x1UL << TPIU_FFCR_FONMANR_Pos) /*!< Bit mask of FONMANR field. */ + #define TPIU_FFCR_FONMANR_Min (0x0UL) /*!< Min enumerator value of FONMANR field. */ + #define TPIU_FFCR_FONMANR_Max (0x1UL) /*!< Max enumerator value of FONMANR field. */ + #define TPIU_FFCR_FONMANR_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_FONMANR_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* FONMANW @Bit 7 : Generates a flush. This bit is set to 1 when this flush is serviced. */ + #define TPIU_FFCR_FONMANW_Pos (7UL) /*!< Position of FONMANW field. */ + #define TPIU_FFCR_FONMANW_Msk (0x1UL << TPIU_FFCR_FONMANW_Pos) /*!< Bit mask of FONMANW field. */ + #define TPIU_FFCR_FONMANW_Min (0x0UL) /*!< Min enumerator value of FONMANW field. */ + #define TPIU_FFCR_FONMANW_Max (0x1UL) /*!< Max enumerator value of FONMANW field. */ + #define TPIU_FFCR_FONMANW_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_FONMANW_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* TRIGIN @Bit 8 : Indicates a trigger when trigin is asserted. */ + #define TPIU_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */ + #define TPIU_FFCR_TRIGIN_Msk (0x1UL << TPIU_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ + #define TPIU_FFCR_TRIGIN_Min (0x0UL) /*!< Min enumerator value of TRIGIN field. */ + #define TPIU_FFCR_TRIGIN_Max (0x1UL) /*!< Max enumerator value of TRIGIN field. */ + #define TPIU_FFCR_TRIGIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_TRIGIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* TRIGEVT @Bit 9 : Indicates a trigger on a trigger event. */ + #define TPIU_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */ + #define TPIU_FFCR_TRIGEVT_Msk (0x1UL << TPIU_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */ + #define TPIU_FFCR_TRIGEVT_Min (0x0UL) /*!< Min enumerator value of TRIGEVT field. */ + #define TPIU_FFCR_TRIGEVT_Max (0x1UL) /*!< Max enumerator value of TRIGEVT field. */ + #define TPIU_FFCR_TRIGEVT_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_TRIGEVT_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* TRIGFL @Bit 10 : Indicates a trigger when flush completion on afreadys is returned. */ + #define TPIU_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */ + #define TPIU_FFCR_TRIGFL_Msk (0x1UL << TPIU_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */ + #define TPIU_FFCR_TRIGFL_Min (0x0UL) /*!< Min enumerator value of TRIGFL field. */ + #define TPIU_FFCR_TRIGFL_Max (0x1UL) /*!< Max enumerator value of TRIGFL field. */ + #define TPIU_FFCR_TRIGFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_TRIGFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* STOPFL @Bit 12 : Forces the FIFO to drain off any part-completed packets. */ + #define TPIU_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */ + #define TPIU_FFCR_STOPFL_Msk (0x1UL << TPIU_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */ + #define TPIU_FFCR_STOPFL_Min (0x0UL) /*!< Min enumerator value of STOPFL field. */ + #define TPIU_FFCR_STOPFL_Max (0x1UL) /*!< Max enumerator value of STOPFL field. */ + #define TPIU_FFCR_STOPFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_STOPFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + +/* STOPTRIG @Bit 13 : Stops the formatter after a trigger event is observed. Reset to disabled or 0. */ + #define TPIU_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */ + #define TPIU_FFCR_STOPTRIG_Msk (0x1UL << TPIU_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */ + #define TPIU_FFCR_STOPTRIG_Min (0x0UL) /*!< Min enumerator value of STOPTRIG field. */ + #define TPIU_FFCR_STOPTRIG_Max (0x1UL) /*!< Max enumerator value of STOPTRIG field. */ + #define TPIU_FFCR_STOPTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */ + #define TPIU_FFCR_STOPTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */ + + +/* TPIU_FSCR: The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port + Analyzer (TPA) capture buffer size. */ + + #define TPIU_FSCR_ResetValue (0x00000000UL) /*!< Reset value of FSCR register. */ + +/* CYCCOUNT @Bits 0..11 : 12-bit counter reload value. Indicates the number of complete frames between full synchronization + packets. */ + + #define TPIU_FSCR_CYCCOUNT_Pos (0UL) /*!< Position of CYCCOUNT field. */ + #define TPIU_FSCR_CYCCOUNT_Msk (0xFFFUL << TPIU_FSCR_CYCCOUNT_Pos) /*!< Bit mask of CYCCOUNT field. */ + #define TPIU_FSCR_CYCCOUNT_Min (0x000UL) /*!< Min value of CYCCOUNT field. */ + #define TPIU_FSCR_CYCCOUNT_Max (0x400UL) /*!< Max size of CYCCOUNT field. */ + + +/* TPIU_EXTCTLINPORT: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, + or other solutions that might be added to the trace output pins either for pin control or a high-speed + trace port solution. */ + + #define TPIU_EXTCTLINPORT_ResetValue (0x00000000UL) /*!< Reset value of EXTCTLINPORT register. */ + +/* EXTCTLIN0 @Bit 0 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_Pos (0UL) /*!< Position of EXTCTLIN0 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN0_Pos) /*!< Bit mask of EXTCTLIN0 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN0 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN0 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_Low (0x0UL) /*!< Input EXTCTL0 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN0_High (0x1UL) /*!< Input EXTCTL0 is high. */ + +/* EXTCTLIN1 @Bit 1 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_Pos (1UL) /*!< Position of EXTCTLIN1 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN1_Pos) /*!< Bit mask of EXTCTLIN1 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN1 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN1 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_Low (0x0UL) /*!< Input EXTCTL1 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN1_High (0x1UL) /*!< Input EXTCTL1 is high. */ + +/* EXTCTLIN2 @Bit 2 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_Pos (2UL) /*!< Position of EXTCTLIN2 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN2_Pos) /*!< Bit mask of EXTCTLIN2 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN2 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN2 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_Low (0x0UL) /*!< Input EXTCTL2 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN2_High (0x1UL) /*!< Input EXTCTL2 is high. */ + +/* EXTCTLIN3 @Bit 3 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_Pos (3UL) /*!< Position of EXTCTLIN3 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN3_Pos) /*!< Bit mask of EXTCTLIN3 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN3 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN3 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_Low (0x0UL) /*!< Input EXTCTL3 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN3_High (0x1UL) /*!< Input EXTCTL3 is high. */ + +/* EXTCTLIN4 @Bit 4 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_Pos (4UL) /*!< Position of EXTCTLIN4 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN4_Pos) /*!< Bit mask of EXTCTLIN4 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN4 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN4 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_Low (0x0UL) /*!< Input EXTCTL4 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN4_High (0x1UL) /*!< Input EXTCTL4 is high. */ + +/* EXTCTLIN5 @Bit 5 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_Pos (5UL) /*!< Position of EXTCTLIN5 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN5_Pos) /*!< Bit mask of EXTCTLIN5 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN5 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN5 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_Low (0x0UL) /*!< Input EXTCTL5 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN5_High (0x1UL) /*!< Input EXTCTL5 is high. */ + +/* EXTCTLIN6 @Bit 6 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_Pos (6UL) /*!< Position of EXTCTLIN6 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN6_Pos) /*!< Bit mask of EXTCTLIN6 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN6 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN6 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_Low (0x0UL) /*!< Input EXTCTL6 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN6_High (0x1UL) /*!< Input EXTCTL6 is high. */ + +/* EXTCTLIN7 @Bit 7 : EXTCTL inputs. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_Pos (7UL) /*!< Position of EXTCTLIN7 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN7_Pos) /*!< Bit mask of EXTCTLIN7 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_Min (0x0UL) /*!< Min enumerator value of EXTCTLIN7 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_Max (0x1UL) /*!< Max enumerator value of EXTCTLIN7 field. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_Low (0x0UL) /*!< Input EXTCTL7 is low. */ + #define TPIU_EXTCTLINPORT_EXTCTLIN7_High (0x1UL) /*!< Input EXTCTL7 is high. */ + + +/* TPIU_EXTCTLOUTPORT: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, + or other solutions that might be added to the trace output pins either for pin control or a high speed + trace port solution. These ports are raw register banks that sample or export the corresponding external + pins. */ + + #define TPIU_EXTCTLOUTPORT_ResetValue (0x00000000UL) /*!< Reset value of EXTCTLOUTPORT register. */ + +/* EXTCTLOUT0 @Bit 0 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Pos (0UL) /*!< Position of EXTCTLOUT0 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Pos) /*!< Bit mask of EXTCTLOUT0 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT0 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT0 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Low (0x0UL) /*!< Output EXTCTL0 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_High (0x1UL) /*!< Output EXTCTL0 is high. */ + +/* EXTCTLOUT1 @Bit 1 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Pos (1UL) /*!< Position of EXTCTLOUT1 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Pos) /*!< Bit mask of EXTCTLOUT1 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT1 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT1 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Low (0x0UL) /*!< Output EXTCTL1 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_High (0x1UL) /*!< Output EXTCTL1 is high. */ + +/* EXTCTLOUT2 @Bit 2 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Pos (2UL) /*!< Position of EXTCTLOUT2 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Pos) /*!< Bit mask of EXTCTLOUT2 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT2 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT2 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Low (0x0UL) /*!< Output EXTCTL2 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_High (0x1UL) /*!< Output EXTCTL2 is high. */ + +/* EXTCTLOUT3 @Bit 3 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Pos (3UL) /*!< Position of EXTCTLOUT3 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Pos) /*!< Bit mask of EXTCTLOUT3 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT3 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT3 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Low (0x0UL) /*!< Output EXTCTL3 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_High (0x1UL) /*!< Output EXTCTL3 is high. */ + +/* EXTCTLOUT4 @Bit 4 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Pos (4UL) /*!< Position of EXTCTLOUT4 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Pos) /*!< Bit mask of EXTCTLOUT4 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT4 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT4 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Low (0x0UL) /*!< Output EXTCTL4 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_High (0x1UL) /*!< Output EXTCTL4 is high. */ + +/* EXTCTLOUT5 @Bit 5 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Pos (5UL) /*!< Position of EXTCTLOUT5 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Pos) /*!< Bit mask of EXTCTLOUT5 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT5 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT5 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Low (0x0UL) /*!< Output EXTCTL5 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_High (0x1UL) /*!< Output EXTCTL5 is high. */ + +/* EXTCTLOUT6 @Bit 6 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Pos (6UL) /*!< Position of EXTCTLOUT6 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Pos) /*!< Bit mask of EXTCTLOUT6 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT6 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT6 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Low (0x0UL) /*!< Output EXTCTL6 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_High (0x1UL) /*!< Output EXTCTL6 is high. */ + +/* EXTCTLOUT7 @Bit 7 : EXTCTL outputs. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Pos (7UL) /*!< Position of EXTCTLOUT7 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Pos) /*!< Bit mask of EXTCTLOUT7 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Min (0x0UL) /*!< Min enumerator value of EXTCTLOUT7 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Max (0x1UL) /*!< Max enumerator value of EXTCTLOUT7 field. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Low (0x0UL) /*!< Output EXTCTL7 is low. */ + #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_High (0x1UL) /*!< Output EXTCTL7 is high. */ + + +/* TPIU_ITTRFLINACK: The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. */ + #define TPIU_ITTRFLINACK_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLINACK register. */ + +/* TRIGINACK @Bit 0 : Sets the value of triginack. */ + #define TPIU_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */ + #define TPIU_ITTRFLINACK_TRIGINACK_Msk (0x1UL << TPIU_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */ + #define TPIU_ITTRFLINACK_TRIGINACK_Min (0x0UL) /*!< Min enumerator value of TRIGINACK field. */ + #define TPIU_ITTRFLINACK_TRIGINACK_Max (0x1UL) /*!< Max enumerator value of TRIGINACK field. */ + #define TPIU_ITTRFLINACK_TRIGINACK_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITTRFLINACK_TRIGINACK_High (0x1UL) /*!< Pin is logic 1. */ + +/* FLUSHINACK @Bit 1 : Sets the value of flushinack. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << TPIU_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_Min (0x0UL) /*!< Min enumerator value of FLUSHINACK field. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_Max (0x1UL) /*!< Max enumerator value of FLUSHINACK field. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITTRFLINACK_FLUSHINACK_High (0x1UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITTRFLIN: The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. */ + #define TPIU_ITTRFLIN_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLIN register. */ + +/* TRIGIN @Bit 0 : Reads the value of trigin. */ + #define TPIU_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */ + #define TPIU_ITTRFLIN_TRIGIN_Msk (0x1UL << TPIU_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ + #define TPIU_ITTRFLIN_TRIGIN_Min (0x0UL) /*!< Min enumerator value of TRIGIN field. */ + #define TPIU_ITTRFLIN_TRIGIN_Max (0x1UL) /*!< Max enumerator value of TRIGIN field. */ + #define TPIU_ITTRFLIN_TRIGIN_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITTRFLIN_TRIGIN_High (0x1UL) /*!< Pin is logic 1. */ + +/* FLUSHIN @Bit 1 : Reads the value of flushin. */ + #define TPIU_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */ + #define TPIU_ITTRFLIN_FLUSHIN_Msk (0x1UL << TPIU_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */ + #define TPIU_ITTRFLIN_FLUSHIN_Min (0x0UL) /*!< Min enumerator value of FLUSHIN field. */ + #define TPIU_ITTRFLIN_FLUSHIN_Max (0x1UL) /*!< Max enumerator value of FLUSHIN field. */ + #define TPIU_ITTRFLIN_FLUSHIN_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITTRFLIN_FLUSHIN_High (0x1UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITATBDATA0: The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when + atvalids is HIGH. */ + + #define TPIU_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register. */ + +/* ATDATA0 @Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define TPIU_ITATBDATA0_ATDATA0_Pos (0UL) /*!< Position of ATDATA0 field. */ + #define TPIU_ITATBDATA0_ATDATA0_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA0_Pos) /*!< Bit mask of ATDATA0 field. */ + #define TPIU_ITATBDATA0_ATDATA0_Min (0x0UL) /*!< Min enumerator value of ATDATA0 field. */ + #define TPIU_ITATBDATA0_ATDATA0_Max (0x1UL) /*!< Max enumerator value of ATDATA0 field. */ + #define TPIU_ITATBDATA0_ATDATA0_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBDATA0_ATDATA0_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA1 @Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define TPIU_ITATBDATA0_ATDATA1_Pos (1UL) /*!< Position of ATDATA1 field. */ + #define TPIU_ITATBDATA0_ATDATA1_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA1_Pos) /*!< Bit mask of ATDATA1 field. */ + #define TPIU_ITATBDATA0_ATDATA1_Min (0x0UL) /*!< Min enumerator value of ATDATA1 field. */ + #define TPIU_ITATBDATA0_ATDATA1_Max (0x1UL) /*!< Max enumerator value of ATDATA1 field. */ + #define TPIU_ITATBDATA0_ATDATA1_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBDATA0_ATDATA1_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA2 @Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define TPIU_ITATBDATA0_ATDATA2_Pos (2UL) /*!< Position of ATDATA2 field. */ + #define TPIU_ITATBDATA0_ATDATA2_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA2_Pos) /*!< Bit mask of ATDATA2 field. */ + #define TPIU_ITATBDATA0_ATDATA2_Min (0x0UL) /*!< Min enumerator value of ATDATA2 field. */ + #define TPIU_ITATBDATA0_ATDATA2_Max (0x1UL) /*!< Max enumerator value of ATDATA2 field. */ + #define TPIU_ITATBDATA0_ATDATA2_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBDATA0_ATDATA2_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA3 @Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define TPIU_ITATBDATA0_ATDATA3_Pos (3UL) /*!< Position of ATDATA3 field. */ + #define TPIU_ITATBDATA0_ATDATA3_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA3_Pos) /*!< Bit mask of ATDATA3 field. */ + #define TPIU_ITATBDATA0_ATDATA3_Min (0x0UL) /*!< Min enumerator value of ATDATA3 field. */ + #define TPIU_ITATBDATA0_ATDATA3_Max (0x1UL) /*!< Max enumerator value of ATDATA3 field. */ + #define TPIU_ITATBDATA0_ATDATA3_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBDATA0_ATDATA3_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATDATA4 @Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the + corresponding atdatam pin of the enabled port. */ + + #define TPIU_ITATBDATA0_ATDATA4_Pos (4UL) /*!< Position of ATDATA4 field. */ + #define TPIU_ITATBDATA0_ATDATA4_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA4_Pos) /*!< Bit mask of ATDATA4 field. */ + #define TPIU_ITATBDATA0_ATDATA4_Min (0x0UL) /*!< Min enumerator value of ATDATA4 field. */ + #define TPIU_ITATBDATA0_ATDATA4_Max (0x1UL) /*!< Max enumerator value of ATDATA4 field. */ + #define TPIU_ITATBDATA0_ATDATA4_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBDATA0_ATDATA4_High (0x1UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITATBCTR2: Enables control of the atreadys and afvalids outputs of the TPIU. */ + #define TPIU_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register. */ + +/* ATREADY @Bit 0 : Sets the value of afvalid. */ + #define TPIU_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */ + #define TPIU_ITATBCTR2_ATREADY_Msk (0x1UL << TPIU_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */ + #define TPIU_ITATBCTR2_ATREADY_Min (0x0UL) /*!< Min enumerator value of ATREADY field. */ + #define TPIU_ITATBCTR2_ATREADY_Max (0x1UL) /*!< Max enumerator value of ATREADY field. */ + #define TPIU_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */ + +/* AFVALID @Bit 1 : Sets the value of atready. */ + #define TPIU_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */ + #define TPIU_ITATBCTR2_AFVALID_Msk (0x1UL << TPIU_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */ + #define TPIU_ITATBCTR2_AFVALID_Min (0x0UL) /*!< Min enumerator value of AFVALID field. */ + #define TPIU_ITATBCTR2_AFVALID_Max (0x1UL) /*!< Max enumerator value of AFVALID field. */ + #define TPIU_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITATBCTR1: The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is + HIGH. */ + + #define TPIU_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register. */ + +/* ATID @Bits 0..6 : Reads the value of atids. */ + #define TPIU_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */ + #define TPIU_ITATBCTR1_ATID_Msk (0x7FUL << TPIU_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */ + #define TPIU_ITATBCTR1_ATID_Min (0x0UL) /*!< Min enumerator value of ATID field. */ + #define TPIU_ITATBCTR1_ATID_Max (0x1UL) /*!< Max enumerator value of ATID field. */ + #define TPIU_ITATBCTR1_ATID_Low (0x00UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR1_ATID_High (0x01UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITATBCTR0: The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To + ensure the integration registers work correctly in a system, the value of atbytess is only valid when + atvalids, bit[0], is HIGH. */ + + #define TPIU_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register. */ + +/* ATVALID @Bit 0 : Reads the value of atvalids. */ + #define TPIU_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ + #define TPIU_ITATBCTR0_ATVALID_Msk (0x1UL << TPIU_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ + #define TPIU_ITATBCTR0_ATVALID_Min (0x0UL) /*!< Min enumerator value of ATVALID field. */ + #define TPIU_ITATBCTR0_ATVALID_Max (0x1UL) /*!< Max enumerator value of ATVALID field. */ + #define TPIU_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */ + +/* AFREADY @Bit 2 : Reads the value of afreadys. */ + #define TPIU_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */ + #define TPIU_ITATBCTR0_AFREADY_Msk (0x1UL << TPIU_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ + #define TPIU_ITATBCTR0_AFREADY_Min (0x0UL) /*!< Min enumerator value of AFREADY field. */ + #define TPIU_ITATBCTR0_AFREADY_Max (0x1UL) /*!< Max enumerator value of AFREADY field. */ + #define TPIU_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */ + +/* ATBYTES @Bits 8..9 : Reads the value of atbytess. */ + #define TPIU_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ + #define TPIU_ITATBCTR0_ATBYTES_Msk (0x3UL << TPIU_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ + #define TPIU_ITATBCTR0_ATBYTES_Min (0x0UL) /*!< Min enumerator value of ATBYTES field. */ + #define TPIU_ITATBCTR0_ATBYTES_Max (0x1UL) /*!< Max enumerator value of ATBYTES field. */ + #define TPIU_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */ + #define TPIU_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */ + + +/* TPIU_ITCTRL: Used to enable topology detection. This register enables the component to switch from a functional mode, the + default behavior, to integration mode where the inputs and outputs of the component can be directly controlled + for integration testing and topology solving. */ + + #define TPIU_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register. */ + +/* INTEGRATIONMODE @Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration + functionality is implemented, this register must read as zero. */ + + #define TPIU_ITCTRL_INTEGRATIONMODE_Pos (0UL) /*!< Position of INTEGRATIONMODE field. */ + #define TPIU_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << TPIU_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field. */ + #define TPIU_ITCTRL_INTEGRATIONMODE_Min (0x0UL) /*!< Min enumerator value of INTEGRATIONMODE field. */ + #define TPIU_ITCTRL_INTEGRATIONMODE_Max (0x1UL) /*!< Max enumerator value of INTEGRATIONMODE field. */ + #define TPIU_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled. */ + #define TPIU_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled. */ + + +/* TPIU_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The + claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim + tag, and determines the number of claim bits implemented. */ + + #define TPIU_CLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of CLAIMSET register. */ + +/* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ + #define TPIU_CLAIMSET_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define TPIU_CLAIMSET_BIT0_Msk (0x1UL << TPIU_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define TPIU_CLAIMSET_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define TPIU_CLAIMSET_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define TPIU_CLAIMSET_BIT0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ + #define TPIU_CLAIMSET_BIT0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ + #define TPIU_CLAIMSET_BIT0_Set (0x1UL) /*!< Set claim bit 0. */ + +/* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ + #define TPIU_CLAIMSET_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define TPIU_CLAIMSET_BIT1_Msk (0x1UL << TPIU_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define TPIU_CLAIMSET_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define TPIU_CLAIMSET_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define TPIU_CLAIMSET_BIT1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ + #define TPIU_CLAIMSET_BIT1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ + #define TPIU_CLAIMSET_BIT1_Set (0x1UL) /*!< Set claim bit 1. */ + +/* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ + #define TPIU_CLAIMSET_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define TPIU_CLAIMSET_BIT2_Msk (0x1UL << TPIU_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define TPIU_CLAIMSET_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define TPIU_CLAIMSET_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define TPIU_CLAIMSET_BIT2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ + #define TPIU_CLAIMSET_BIT2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ + #define TPIU_CLAIMSET_BIT2_Set (0x1UL) /*!< Set claim bit 2. */ + +/* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ + #define TPIU_CLAIMSET_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define TPIU_CLAIMSET_BIT3_Msk (0x1UL << TPIU_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define TPIU_CLAIMSET_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define TPIU_CLAIMSET_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define TPIU_CLAIMSET_BIT3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ + #define TPIU_CLAIMSET_BIT3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ + #define TPIU_CLAIMSET_BIT3_Set (0x1UL) /*!< Set claim bit 3. */ + + +/* TPIU_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The + claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim + tag to 0 and determines the current value of the claim tag. */ + + #define TPIU_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register. */ + +/* BIT0 @Bit 0 : Read or clear claim bit 0. */ + #define TPIU_CLAIMCLR_BIT0_Pos (0UL) /*!< Position of BIT0 field. */ + #define TPIU_CLAIMCLR_BIT0_Msk (0x1UL << TPIU_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field. */ + #define TPIU_CLAIMCLR_BIT0_Min (0x0UL) /*!< Min enumerator value of BIT0 field. */ + #define TPIU_CLAIMCLR_BIT0_Max (0x1UL) /*!< Max enumerator value of BIT0 field. */ + #define TPIU_CLAIMCLR_BIT0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ + #define TPIU_CLAIMCLR_BIT0_Set (0x1UL) /*!< Claim bit 0 is set. */ + #define TPIU_CLAIMCLR_BIT0_Clear (0x1UL) /*!< Clear claim bit 0. */ + +/* BIT1 @Bit 1 : Read or clear claim bit 1. */ + #define TPIU_CLAIMCLR_BIT1_Pos (1UL) /*!< Position of BIT1 field. */ + #define TPIU_CLAIMCLR_BIT1_Msk (0x1UL << TPIU_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field. */ + #define TPIU_CLAIMCLR_BIT1_Min (0x0UL) /*!< Min enumerator value of BIT1 field. */ + #define TPIU_CLAIMCLR_BIT1_Max (0x1UL) /*!< Max enumerator value of BIT1 field. */ + #define TPIU_CLAIMCLR_BIT1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ + #define TPIU_CLAIMCLR_BIT1_Set (0x1UL) /*!< Claim bit 1 is set. */ + #define TPIU_CLAIMCLR_BIT1_Clear (0x1UL) /*!< Clear claim bit 1. */ + +/* BIT2 @Bit 2 : Read or clear claim bit 2. */ + #define TPIU_CLAIMCLR_BIT2_Pos (2UL) /*!< Position of BIT2 field. */ + #define TPIU_CLAIMCLR_BIT2_Msk (0x1UL << TPIU_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field. */ + #define TPIU_CLAIMCLR_BIT2_Min (0x0UL) /*!< Min enumerator value of BIT2 field. */ + #define TPIU_CLAIMCLR_BIT2_Max (0x1UL) /*!< Max enumerator value of BIT2 field. */ + #define TPIU_CLAIMCLR_BIT2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ + #define TPIU_CLAIMCLR_BIT2_Set (0x1UL) /*!< Claim bit 2 is set. */ + #define TPIU_CLAIMCLR_BIT2_Clear (0x1UL) /*!< Clear claim bit 2. */ + +/* BIT3 @Bit 3 : Read or clear claim bit 3. */ + #define TPIU_CLAIMCLR_BIT3_Pos (3UL) /*!< Position of BIT3 field. */ + #define TPIU_CLAIMCLR_BIT3_Msk (0x1UL << TPIU_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field. */ + #define TPIU_CLAIMCLR_BIT3_Min (0x0UL) /*!< Min enumerator value of BIT3 field. */ + #define TPIU_CLAIMCLR_BIT3_Max (0x1UL) /*!< Max enumerator value of BIT3 field. */ + #define TPIU_CLAIMCLR_BIT3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ + #define TPIU_CLAIMCLR_BIT3_Set (0x1UL) /*!< Claim bit 3 is set. */ + #define TPIU_CLAIMCLR_BIT3_Clear (0x1UL) /*!< Clear claim bit 3. */ + + +/* TPIU_LAR: This is used to enable write access to device registers. */ + #define TPIU_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register. */ + +/* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. + */ + + #define TPIU_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ + #define TPIU_LAR_ACCESS_Msk (0xFFFFFFFFUL << TPIU_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ + #define TPIU_LAR_ACCESS_Min (0xC5ACCE55UL) /*!< Min enumerator value of ACCESS field. */ + #define TPIU_LAR_ACCESS_Max (0xC5ACCE55UL) /*!< Max enumerator value of ACCESS field. */ + #define TPIU_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ + + +/* TPIU_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. + Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always + be present although there might not be any lock access control mechanism. The lock mechanism, where present and + locked, must block write accesses to any control register, except the Lock Access Register. For most components + this covers all registers except for the Lock Access Register. */ + + #define TPIU_LSR_ResetValue (0x00000000UL) /*!< Reset value of LSR register. */ + +/* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */ + #define TPIU_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ + #define TPIU_LSR_PRESENT_Msk (0x1UL << TPIU_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ + #define TPIU_LSR_PRESENT_Min (0x0UL) /*!< Min enumerator value of PRESENT field. */ + #define TPIU_LSR_PRESENT_Max (0x1UL) /*!< Max enumerator value of PRESENT field. */ + #define TPIU_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register + are ignored.*/ + #define TPIU_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ + +/* LOCKED @Bit 1 : Returns the current status of the Lock. */ + #define TPIU_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ + #define TPIU_LSR_LOCKED_Msk (0x1UL << TPIU_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ + #define TPIU_LSR_LOCKED_Min (0x0UL) /*!< Min enumerator value of LOCKED field. */ + #define TPIU_LSR_LOCKED_Max (0x1UL) /*!< Max enumerator value of LOCKED field. */ + #define TPIU_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ + #define TPIU_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control + registers are ignored. Reads are permitted.*/ + +/* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ + #define TPIU_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ + #define TPIU_LSR_TYPE_Msk (0x1UL << TPIU_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TPIU_LSR_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TPIU_LSR_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TPIU_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ + #define TPIU_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ + + +/* TPIU_AUTHSTATUS: Indicates the current level of tracing permitted by the system */ + #define TPIU_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register. */ + +/* NSID @Bits 0..1 : Non-secure Invasive Debug */ + #define TPIU_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ + #define TPIU_AUTHSTATUS_NSID_Msk (0x3UL << TPIU_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ + #define TPIU_AUTHSTATUS_NSID_Min (0x0UL) /*!< Min enumerator value of NSID field. */ + #define TPIU_AUTHSTATUS_NSID_Max (0x1UL) /*!< Max enumerator value of NSID field. */ + #define TPIU_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define TPIU_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */ + #define TPIU_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ + #define TPIU_AUTHSTATUS_NSNID_Msk (0x3UL << TPIU_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ + #define TPIU_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field. */ + #define TPIU_AUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field. */ + #define TPIU_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define TPIU_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SID @Bits 4..5 : Secure Invasive Debug */ + #define TPIU_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ + #define TPIU_AUTHSTATUS_SID_Msk (0x3UL << TPIU_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ + #define TPIU_AUTHSTATUS_SID_Min (0x0UL) /*!< Min enumerator value of SID field. */ + #define TPIU_AUTHSTATUS_SID_Max (0x1UL) /*!< Max enumerator value of SID field. */ + #define TPIU_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define TPIU_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ + +/* SNID @Bits 6..7 : Secure Non-Invasive Debug */ + #define TPIU_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ + #define TPIU_AUTHSTATUS_SNID_Msk (0x3UL << TPIU_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ + #define TPIU_AUTHSTATUS_SNID_Min (0x0UL) /*!< Min enumerator value of SNID field. */ + #define TPIU_AUTHSTATUS_SNID_Max (0x1UL) /*!< Max enumerator value of SNID field. */ + #define TPIU_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ + #define TPIU_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ + + +/* TPIU_DEVID: Indicates the capabilities of the component. */ + #define TPIU_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register. */ + +/* MUXNUM @Bits 0..4 : Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of + multiplexing on the input to the ATB. Currently only 0x00 is supported, that is, no multiplexing is + present. This value helps detect the ATB structure. */ + + #define TPIU_DEVID_MUXNUM_Pos (0UL) /*!< Position of MUXNUM field. */ + #define TPIU_DEVID_MUXNUM_Msk (0x1FUL << TPIU_DEVID_MUXNUM_Pos) /*!< Bit mask of MUXNUM field. */ + +/* CLKRELAT @Bit 5 : Indicates the relationship between atclk and traceclkin. */ + #define TPIU_DEVID_CLKRELAT_Pos (5UL) /*!< Position of CLKRELAT field. */ + #define TPIU_DEVID_CLKRELAT_Msk (0x1UL << TPIU_DEVID_CLKRELAT_Pos) /*!< Bit mask of CLKRELAT field. */ + #define TPIU_DEVID_CLKRELAT_Min (0x0UL) /*!< Min enumerator value of CLKRELAT field. */ + #define TPIU_DEVID_CLKRELAT_Max (0x1UL) /*!< Max enumerator value of CLKRELAT field. */ + #define TPIU_DEVID_CLKRELAT_Synchronous (0x0UL) /*!< atclk and traceclkin are synchronous. */ + #define TPIU_DEVID_CLKRELAT_ASynchronous (0x1UL) /*!< atclk and traceclkin are asynchronous. */ + +/* FIFOSIZE @Bits 6..8 : FIFO size in powers of 2. */ + #define TPIU_DEVID_FIFOSIZE_Pos (6UL) /*!< Position of FIFOSIZE field. */ + #define TPIU_DEVID_FIFOSIZE_Msk (0x7UL << TPIU_DEVID_FIFOSIZE_Pos) /*!< Bit mask of FIFOSIZE field. */ + #define TPIU_DEVID_FIFOSIZE_Min (0x2UL) /*!< Min enumerator value of FIFOSIZE field. */ + #define TPIU_DEVID_FIFOSIZE_Max (0x2UL) /*!< Max enumerator value of FIFOSIZE field. */ + #define TPIU_DEVID_FIFOSIZE_Entries4 (0x2UL) /*!< FIFO size of 4 entries, that is, 16 bytes. */ + +/* TCLKDATA @Bit 9 : Indicates whether trace clock plus data is supported. */ + #define TPIU_DEVID_TCLKDATA_Pos (9UL) /*!< Position of TCLKDATA field. */ + #define TPIU_DEVID_TCLKDATA_Msk (0x1UL << TPIU_DEVID_TCLKDATA_Pos) /*!< Bit mask of TCLKDATA field. */ + #define TPIU_DEVID_TCLKDATA_Min (0x0UL) /*!< Min enumerator value of TCLKDATA field. */ + #define TPIU_DEVID_TCLKDATA_Max (0x1UL) /*!< Max enumerator value of TCLKDATA field. */ + #define TPIU_DEVID_TCLKDATA_Supported (0x0UL) /*!< Trace clock and data is supported. */ + #define TPIU_DEVID_TCLKDATA_NotSupported (0x1UL) /*!< Trace clock and data is not supported. */ + +/* SWOMAN @Bit 10 : Indicates whether Serial Wire Output, Manchester encoded format, is supported. */ + #define TPIU_DEVID_SWOMAN_Pos (10UL) /*!< Position of SWOMAN field. */ + #define TPIU_DEVID_SWOMAN_Msk (0x1UL << TPIU_DEVID_SWOMAN_Pos) /*!< Bit mask of SWOMAN field. */ + #define TPIU_DEVID_SWOMAN_Min (0x0UL) /*!< Min enumerator value of SWOMAN field. */ + #define TPIU_DEVID_SWOMAN_Max (0x1UL) /*!< Max enumerator value of SWOMAN field. */ + #define TPIU_DEVID_SWOMAN_NotSupported (0x0UL) /*!< Serial Wire Output, Manchester encoded format, is not supported. */ + #define TPIU_DEVID_SWOMAN_Supported (0x1UL) /*!< Serial Wire Output, Manchester encoded format, is supported. */ + +/* SWOUARTNRZ @Bit 11 : Indicates whether Serial Wire Output, UART or NRZ, is supported. */ + #define TPIU_DEVID_SWOUARTNRZ_Pos (11UL) /*!< Position of SWOUARTNRZ field. */ + #define TPIU_DEVID_SWOUARTNRZ_Msk (0x1UL << TPIU_DEVID_SWOUARTNRZ_Pos) /*!< Bit mask of SWOUARTNRZ field. */ + #define TPIU_DEVID_SWOUARTNRZ_Min (0x0UL) /*!< Min enumerator value of SWOUARTNRZ field. */ + #define TPIU_DEVID_SWOUARTNRZ_Max (0x1UL) /*!< Max enumerator value of SWOUARTNRZ field. */ + #define TPIU_DEVID_SWOUARTNRZ_NotSupported (0x0UL) /*!< Serial Wire Output, UART or NRZ, is not supported. */ + #define TPIU_DEVID_SWOUARTNRZ_Supported (0x1UL) /*!< Serial Wire Output, UART or NRZ, is supported. */ + + +/* TPIU_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not + recognized. The debugger can then report this information. */ + + #define TPIU_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register. */ + +/* MAJOR @Bits 0..3 : The main type of the component */ + #define TPIU_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ + #define TPIU_DEVTYPE_MAJOR_Msk (0xFUL << TPIU_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ + #define TPIU_DEVTYPE_MAJOR_Min (0x1UL) /*!< Min enumerator value of MAJOR field. */ + #define TPIU_DEVTYPE_MAJOR_Max (0x1UL) /*!< Max enumerator value of MAJOR field. */ + #define TPIU_DEVTYPE_MAJOR_TraceSource (0x1UL) /*!< Peripheral is a trace sink. */ + +/* SUB @Bits 4..7 : The sub-type of the component */ + #define TPIU_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ + #define TPIU_DEVTYPE_SUB_Msk (0xFUL << TPIU_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ + #define TPIU_DEVTYPE_SUB_Min (0x1UL) /*!< Min enumerator value of SUB field. */ + #define TPIU_DEVTYPE_SUB_Max (0x1UL) /*!< Max enumerator value of SUB field. */ + #define TPIU_DEVTYPE_SUB_TracePort (0x1UL) /*!< Indicates that this component is a trace port component. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TSGEN ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct TSGEN ======================================================= */ +/** + * @brief Timestamp generator + */ + typedef struct { /*!< TSGEN Structure */ + __IOM uint32_t CNTCR; /*!< (@ 0x00000000) Counter Control Register */ + __IM uint32_t CNTSR; /*!< (@ 0x00000004) Counter Status Register */ + __IOM uint32_t CNTCVL; /*!< (@ 0x00000008) Current Counter Value Lower register */ + __IOM uint32_t CNTCVU; /*!< (@ 0x0000000C) Current Counter Value Upper register */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t CNTFID0; /*!< (@ 0x00000020) Base Frequency ID */ + __IM uint32_t RESERVED1[1003]; + __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ + __IM uint32_t RESERVED2[3]; + __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ + __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ + __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ + __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ + __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ + __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ + __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ + __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ + } NRF_TSGEN_Type; /*!< Size = 4096 (0x1000) */ + +/* TSGEN_CNTCR: Counter Control Register */ + #define TSGEN_CNTCR_ResetValue (0x00000000UL) /*!< Reset value of CNTCR register. */ + +/* EN @Bit 0 : Counter enable */ + #define TSGEN_CNTCR_EN_Pos (0UL) /*!< Position of EN field. */ + #define TSGEN_CNTCR_EN_Msk (0x1UL << TSGEN_CNTCR_EN_Pos) /*!< Bit mask of EN field. */ + #define TSGEN_CNTCR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TSGEN_CNTCR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TSGEN_CNTCR_EN_Disabled (0x0UL) /*!< (unspecified) */ + #define TSGEN_CNTCR_EN_Enabled (0x1UL) /*!< (unspecified) */ + +/* HDBG @Bit 1 : Halt on Debug */ + #define TSGEN_CNTCR_HDBG_Pos (1UL) /*!< Position of HDBG field. */ + #define TSGEN_CNTCR_HDBG_Msk (0x1UL << TSGEN_CNTCR_HDBG_Pos) /*!< Bit mask of HDBG field. */ + #define TSGEN_CNTCR_HDBG_Min (0x0UL) /*!< Min enumerator value of HDBG field. */ + #define TSGEN_CNTCR_HDBG_Max (0x1UL) /*!< Max enumerator value of HDBG field. */ + #define TSGEN_CNTCR_HDBG_Disabled (0x0UL) /*!< Do not halt on debug, HLTDBG signal into the counter has no effect. */ + #define TSGEN_CNTCR_HDBG_Enabled (0x1UL) /*!< Halt on debug, when HLTDBG is driven HIGH, the count value is held + static.*/ + + +/* TSGEN_CNTSR: Counter Status Register */ + #define TSGEN_CNTSR_ResetValue (0x00000000UL) /*!< Reset value of CNTSR register. */ + +/* DBGH @Bit 1 : Debug halted */ + #define TSGEN_CNTSR_DBGH_Pos (1UL) /*!< Position of DBGH field. */ + #define TSGEN_CNTSR_DBGH_Msk (0x1UL << TSGEN_CNTSR_DBGH_Pos) /*!< Bit mask of DBGH field. */ + + +/* TSGEN_CNTCVL: Current Counter Value Lower register */ + #define TSGEN_CNTCVL_ResetValue (0x00000000UL) /*!< Reset value of CNTCVL register. */ + +/* CNTCVL_L_32 @Bits 0..31 : Current value of Counter, lower 32 bits */ + #define TSGEN_CNTCVL_CNTCVL_L_32_Pos (0UL) /*!< Position of CNTCVL_L_32 field. */ + #define TSGEN_CNTCVL_CNTCVL_L_32_Msk (0xFFFFFFFFUL << TSGEN_CNTCVL_CNTCVL_L_32_Pos) /*!< Bit mask of CNTCVL_L_32 field. */ + + +/* TSGEN_CNTCVU: Current Counter Value Upper register */ + #define TSGEN_CNTCVU_ResetValue (0x00000000UL) /*!< Reset value of CNTCVU register. */ + +/* CNTCVU_U_32 @Bits 0..31 : Current value of Counter, upper 32 bits */ + #define TSGEN_CNTCVU_CNTCVU_U_32_Pos (0UL) /*!< Position of CNTCVU_U_32 field. */ + #define TSGEN_CNTCVU_CNTCVU_U_32_Msk (0xFFFFFFFFUL << TSGEN_CNTCVU_CNTCVU_U_32_Pos) /*!< Bit mask of CNTCVU_U_32 field. */ + + +/* TSGEN_CNTFID0: Base Frequency ID */ + #define TSGEN_CNTFID0_ResetValue (0x00000000UL) /*!< Reset value of CNTFID0 register. */ + +/* FREQ @Bits 0..31 : Frequency in number of ticks per second (up to 4 GHz) */ + #define TSGEN_CNTFID0_FREQ_Pos (0UL) /*!< Position of FREQ field. */ + #define TSGEN_CNTFID0_FREQ_Msk (0xFFFFFFFFUL << TSGEN_CNTFID0_FREQ_Pos) /*!< Bit mask of FREQ field. */ + + +/* TSGEN_PIDR4: Peripheral ID4 Register */ + #define TSGEN_PIDR4_ResetValue (0x00000004UL) /*!< Reset value of PIDR4 register. */ + +/* DES_2 @Bits 0..3 : JEDEC continuation code indicating the designer of the component, together with the identity code. */ + #define TSGEN_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ + #define TSGEN_PIDR4_DES_2_Msk (0xFUL << TSGEN_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ + +/* SIZE @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component + in powers of 2 from the standard 4KB. If a component only requires the standard 4KB, this must read as 0x0, + 4KB only. For 8KB set to 0x1, for 16KB set to 0x2, for 32KB set to 0x3, and so on. */ + + #define TSGEN_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ + #define TSGEN_PIDR4_SIZE_Msk (0xFUL << TSGEN_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + +/* TSGEN_PIDR0: Peripheral ID0 Register */ + #define TSGEN_PIDR0_ResetValue (0x00000001UL) /*!< Reset value of PIDR0 register. */ + +/* PART_0 @Bits 0..7 : Bits [7:0] of the component part number. This is selected by the designer of the component. */ + #define TSGEN_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ + #define TSGEN_PIDR0_PART_0_Msk (0xFFUL << TSGEN_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ + + +/* TSGEN_PIDR1: Peripheral ID1 Register */ + #define TSGEN_PIDR1_ResetValue (0x000000B1UL) /*!< Reset value of PIDR1 register. */ + +/* PART_1 @Bits 0..3 : Bits [11:8] of the component part number. This is selected by the designer of the component. */ + #define TSGEN_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ + #define TSGEN_PIDR1_PART_1_Msk (0xFUL << TSGEN_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ + +/* DES_0 @Bits 4..7 : Bits [3:0] of the JEDEC identity code indicating the designer of the component, together with the + continuation code. */ + + #define TSGEN_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ + #define TSGEN_PIDR1_DES_0_Msk (0xFUL << TSGEN_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ + + +/* TSGEN_PIDR2: Peripheral ID2 Register */ + #define TSGEN_PIDR2_ResetValue (0x0000001BUL) /*!< Reset value of PIDR2 register. */ + +/* DES_1 @Bits 0..2 : Bits [6:4] of the JEDEC identity code indicating the designer of the component, together with the + continuation code. */ + + #define TSGEN_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ + #define TSGEN_PIDR2_DES_1_Msk (0x7UL << TSGEN_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ + +/* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used. */ + #define TSGEN_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ + #define TSGEN_PIDR2_JEDEC_Msk (0x1UL << TSGEN_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ + +/* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This + only increases by 1 for both major and minor revisions and is used as a look-up to establish the exact + major and minor revision. */ + + #define TSGEN_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ + #define TSGEN_PIDR2_REVISION_Msk (0xFUL << TSGEN_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ + + +/* TSGEN_PIDR3: Peripheral ID3 Register */ + #define TSGEN_PIDR3_ResetValue (0x00000000UL) /*!< Reset value of PIDR3 register. */ + +/* CMOD @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the + component. In most cases this field is zero. */ + + #define TSGEN_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ + #define TSGEN_PIDR3_CMOD_Msk (0xFUL << TSGEN_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ + +/* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after + implementation. In most cases this field is zero. It is recommended that component designers ensure this + field can be changed by a metal fix if required, for example by driving it from registers that reset to + zero. */ + + #define TSGEN_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ + #define TSGEN_PIDR3_REVAND_Msk (0xFUL << TSGEN_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ + + +/* TSGEN_CIDR0: Component ID0 Register */ + #define TSGEN_CIDR0_ResetValue (0x0000000DUL) /*!< Reset value of CIDR0 register. */ + +/* PRMBL_0 @Bits 0..7 : Contains bits[7:0] of the component identification code. */ + #define TSGEN_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ + #define TSGEN_CIDR0_PRMBL_0_Msk (0xFFUL << TSGEN_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ + + +/* TSGEN_CIDR1: Component ID1 Register */ + #define TSGEN_CIDR1_ResetValue (0x000000F0UL) /*!< Reset value of CIDR1 register. */ + +/* PRMBL_1 @Bits 0..3 : Contains bits[11:8] of the component identification code. */ + #define TSGEN_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ + #define TSGEN_CIDR1_PRMBL_1_Msk (0xFUL << TSGEN_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ + +/* CLASS @Bits 4..7 : Class of the component, for example, ROM table or CoreSight component. */ + #define TSGEN_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ + #define TSGEN_CIDR1_CLASS_Msk (0xFUL << TSGEN_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ + + +/* TSGEN_CIDR2: Component ID2 Register */ + #define TSGEN_CIDR2_ResetValue (0x00000005UL) /*!< Reset value of CIDR2 register. */ + +/* PRMBL_2 @Bits 0..7 : Contains bits[23:16] of the component identification code. */ + #define TSGEN_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ + #define TSGEN_CIDR2_PRMBL_2_Msk (0xFFUL << TSGEN_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ + + +/* TSGEN_CIDR3: Component ID3 Register */ + #define TSGEN_CIDR3_ResetValue (0x000000B1UL) /*!< Reset value of CIDR3 register. */ + +/* PRMBL_3 @Bits 0..7 : Contains bits[31:24] of the component identification code. */ + #define TSGEN_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ + #define TSGEN_CIDR3_PRMBL_3_Msk (0xFFUL << TSGEN_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TWIM ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct TWIM_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [TWIM_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_TWIM_TASKS_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* TWIM_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define TWIM_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define TWIM_TASKS_DMA_RX_START_START_Pos (0UL) /*!< Position of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define TWIM_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================ Struct TWIM_TASKS_DMA_TX ================================================= */ +/** + * @brief TX [TWIM_TASKS_DMA_TX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_TWIM_TASKS_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define TWIM_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define TWIM_TASKS_DMA_TX_START_START_Pos (0UL) /*!< Position of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define TWIM_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define TWIM_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct TWIM_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [TWIM_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_TWIM_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ + __OM NRF_TWIM_TASKS_DMA_TX_Type TX; /*!< (@ 0x00000028) Peripheral tasks. */ +} NRF_TWIM_TASKS_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ============================================== Struct TWIM_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [TWIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_TWIM_SUBSCRIBE_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* TWIM_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */ + #define TWIM_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ============================================== Struct TWIM_SUBSCRIBE_DMA_TX =============================================== */ +/** + * @brief TX [TWIM_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_TWIM_SUBSCRIBE_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */ + #define TWIM_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct TWIM_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [TWIM_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_TWIM_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ + __IOM NRF_TWIM_SUBSCRIBE_DMA_TX_Type TX; /*!< (@ 0x00000028) Subscribe configuration for tasks */ +} NRF_TWIM_SUBSCRIBE_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ================================================ Struct TWIM_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [TWIM_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_TWIM_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIM_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct TWIM_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [TWIM_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_TWIM_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIM_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIM_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct TWIM_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [TWIM_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_TWIM_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_TWIM_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_TWIM_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct TWIM_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [TWIM_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_TWIM_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIM_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define TWIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define TWIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct TWIM_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [TWIM_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_TWIM_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIM_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define TWIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define TWIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct TWIM_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [TWIM_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_TWIM_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_TWIM_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_TWIM_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct TWIM_PSEL ===================================================== */ +/** + * @brief PSEL [TWIM_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} NRF_TWIM_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* TWIM_PSEL_SCL: Pin select for SCL signal */ + #define TWIM_PSEL_SCL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCL register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIM_PSEL_SCL_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Msk (0xFUL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIM_PSEL_SCL_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TWIM_PSEL_SDA: Pin select for SDA signal */ + #define TWIM_PSEL_SDA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDA register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIM_PSEL_SDA_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Msk (0xFUL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIM_PSEL_SDA_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct TWIM_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [TWIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_TWIM_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* TWIM_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define TWIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* TWIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct TWIM_DMA_RX ==================================================== */ +/** + * @brief RX [TWIM_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_TWIM_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_TWIM_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* TWIM_DMA_RX_PTR: RAM buffer start address */ + #define TWIM_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIM_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIM_DMA_RX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_RX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TWIM_DMA_RX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_RX_LIST: EasyDMA list type */ + #define TWIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct TWIM_DMA_TX ==================================================== */ +/** + * @brief TX [TWIM_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TWIM_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* TWIM_DMA_TX_PTR: RAM buffer start address */ + #define TWIM_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIM_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIM_DMA_TX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_TX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TWIM_DMA_TX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TWIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define TWIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIM_DMA_TX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIM_DMA_TX_LIST: EasyDMA list type */ + #define TWIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIM_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIM_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct TWIM_DMA ===================================================== */ +/** + * @brief DMA [TWIM_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_TWIM_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_TWIM_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_TWIM_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct TWIM ======================================================= */ +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA + */ + typedef struct { /*!< TWIM Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop TWI transaction. Must be issued while the TWI + master is not suspended.*/ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume TWI transaction */ + __IM uint32_t RESERVED2[5]; + __OM NRF_TWIM_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED3[11]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED4; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED5[5]; + __IOM NRF_TWIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) TWI error */ + __IM uint32_t RESERVED8[4]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000128) SUSPEND task has been issued, TWI traffic is now + suspended.*/ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x00000134) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000138) Byte boundary, starting to transmit the last byte */ + __IM uint32_t RESERVED10[4]; + __IOM NRF_TWIM_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED13[4]; + __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001A8) Publish configuration for event SUSPENDED */ + __IM uint32_t RESERVED14[2]; + __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001B4) Publish configuration for event LASTRX */ + __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001B8) Publish configuration for event LASTTX */ + __IM uint32_t RESERVED15[4]; + __IOM NRF_TWIM_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED17[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED18[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED19[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED20[8]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK source + selected.*/ + __IM uint32_t RESERVED21[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ + __IM uint32_t RESERVED22[29]; + __IOM NRF_TWIM_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED23[62]; + __IOM NRF_TWIM_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_TWIM_Type; /*!< Size = 1884 (0x75C) */ + +/* TWIM_TASKS_STOP: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + #define TWIM_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_SUSPEND: Suspend TWI transaction */ + #define TWIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_TASKS_RESUME: Resume TWI transaction */ + #define TWIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume TWI transaction */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TWIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define TWIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define TWIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIM_EVENTS_STOPPED: TWI stopped */ + #define TWIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : TWI stopped */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_ERROR: TWI error */ + #define TWIM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : TWI error */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_SUSPENDED: SUSPEND task has been issued, TWI traffic is now suspended. */ + #define TWIM_EVENTS_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SUSPENDED register. */ + +/* EVENTS_SUSPENDED @Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of + EVENTS_SUSPENDED field.*/ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SUSPENDED field. */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_LASTRX: Byte boundary, starting to receive the last byte */ + #define TWIM_EVENTS_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTRX register. */ + +/* EVENTS_LASTRX @Bit 0 : Byte boundary, starting to receive the last byte */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX + field.*/ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTRX field. */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_EVENTS_LASTTX: Byte boundary, starting to transmit the last byte */ + #define TWIM_EVENTS_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTTX register. */ + +/* EVENTS_LASTTX @Bit 0 : Byte boundary, starting to transmit the last byte */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX + field.*/ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTTX field. */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */ + + +/* TWIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define TWIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define TWIM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_SUSPENDED: Publish configuration for event SUSPENDED */ + #define TWIM_PUBLISH_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SUSPENDED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event SUSPENDED will publish to */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_SUSPENDED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_LASTRX: Publish configuration for event LASTRX */ + #define TWIM_PUBLISH_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTRX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LASTRX will publish to */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_LASTRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_PUBLISH_LASTTX: Publish configuration for event LASTTX */ + #define TWIM_PUBLISH_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTTX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event LASTTX will publish to */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIM_PUBLISH_LASTTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIM_SHORTS: Shortcuts between local events and tasks */ + #define TWIM_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* LASTTX_DMA_RX_START @Bit 7 : Shortcut between event LASTTX and task DMA.RX.START */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Pos (7UL) /*!< Position of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Msk (0x1UL << TWIM_SHORTS_LASTTX_DMA_RX_START_Pos) /*!< Bit mask of + LASTTX_DMA_RX_START field.*/ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of LASTTX_DMA_RX_START field. */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTTX_SUSPEND @Bit 8 : Shortcut between event LASTTX and task SUSPEND */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Min (0x0UL) /*!< Min enumerator value of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Max (0x1UL) /*!< Max enumerator value of LASTTX_SUSPEND field. */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTTX_STOP @Bit 9 : Shortcut between event LASTTX and task STOP */ + #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Min (0x0UL) /*!< Min enumerator value of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Max (0x1UL) /*!< Max enumerator value of LASTTX_STOP field. */ + #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTRX_DMA_TX_START @Bit 10 : Shortcut between event LASTRX and task DMA.TX.START */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Pos (10UL) /*!< Position of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Msk (0x1UL << TWIM_SHORTS_LASTRX_DMA_TX_START_Pos) /*!< Bit mask of + LASTRX_DMA_TX_START field.*/ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Min (0x0UL) /*!< Min enumerator value of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Max (0x1UL) /*!< Max enumerator value of LASTRX_DMA_TX_START field. */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTRX_DMA_TX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* LASTRX_STOP @Bit 12 : Shortcut between event LASTRX and task STOP */ + #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Min (0x0UL) /*!< Min enumerator value of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Max (0x1UL) /*!< Max enumerator value of LASTRX_STOP field. */ + #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TWIM_INTEN: Enable or disable interrupt */ + #define TWIM_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define TWIM_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* SUSPENDED @Bit 10 : Enable or disable interrupt for event SUSPENDED */ + #define TWIM_INTEN_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */ + +/* LASTRX @Bit 13 : Enable or disable interrupt for event LASTRX */ + #define TWIM_INTEN_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */ + +/* LASTTX @Bit 14 : Enable or disable interrupt for event LASTTX */ + #define TWIM_INTEN_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define TWIM_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Msk (0x1UL << TWIM_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define TWIM_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Msk (0x1UL << TWIM_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define TWIM_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Msk (0x1UL << TWIM_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Msk (0x1UL << TWIM_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Msk (0x1UL << TWIM_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Msk (0x1UL << TWIM_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define TWIM_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Msk (0x1UL << TWIM_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define TWIM_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Msk (0x1UL << TWIM_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define TWIM_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIM_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* TWIM_INTENSET: Enable interrupt */ + #define TWIM_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define TWIM_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SUSPENDED @Bit 10 : Write '1' to enable interrupt for event SUSPENDED */ + #define TWIM_INTENSET_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTRX @Bit 13 : Write '1' to enable interrupt for event LASTRX */ + #define TWIM_INTENSET_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTTX @Bit 14 : Write '1' to enable interrupt for event LASTTX */ + #define TWIM_INTENSET_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define TWIM_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Msk (0x1UL << TWIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define TWIM_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Msk (0x1UL << TWIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define TWIM_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define TWIM_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Msk (0x1UL << TWIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define TWIM_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Msk (0x1UL << TWIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define TWIM_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIM_INTENCLR: Disable interrupt */ + #define TWIM_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define TWIM_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* SUSPENDED @Bit 10 : Write '1' to disable interrupt for event SUSPENDED */ + #define TWIM_INTENCLR_SUSPENDED_Pos (10UL) /*!< Position of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of SUSPENDED field. */ + #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTRX @Bit 13 : Write '1' to disable interrupt for event LASTRX */ + #define TWIM_INTENCLR_LASTRX_Pos (13UL) /*!< Position of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Min (0x0UL) /*!< Min enumerator value of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Max (0x1UL) /*!< Max enumerator value of LASTRX field. */ + #define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* LASTTX @Bit 14 : Write '1' to disable interrupt for event LASTTX */ + #define TWIM_INTENCLR_LASTTX_Pos (14UL) /*!< Position of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Min (0x0UL) /*!< Min enumerator value of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Max (0x1UL) /*!< Max enumerator value of LASTTX field. */ + #define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define TWIM_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Msk (0x1UL << TWIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIM_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define TWIM_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Msk (0x1UL << TWIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIM_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define TWIM_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define TWIM_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIM_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define TWIM_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIM_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define TWIM_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIM_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define TWIM_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIM_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define TWIM_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Msk (0x1UL << TWIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIM_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define TWIM_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Msk (0x1UL << TWIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIM_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define TWIM_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIM_ERRORSRC: Error source */ + #define TWIM_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERRUN @Bit 0 : Overrun error */ + #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Min (0x0UL) /*!< Min enumerator value of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_Max (0x1UL) /*!< Max enumerator value of OVERRUN field. */ + #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */ + +/* ANACK @Bit 1 : NACK received after sending the address (write '1' to clear) */ + #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Min (0x0UL) /*!< Min enumerator value of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_Max (0x1UL) /*!< Max enumerator value of ANACK field. */ + #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */ + +/* DNACK @Bit 2 : NACK received after sending a data byte (write '1' to clear) */ + #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Min (0x0UL) /*!< Min enumerator value of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_Max (0x1UL) /*!< Max enumerator value of DNACK field. */ + #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ + + +/* TWIM_ENABLE: Enable TWIM */ + #define TWIM_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable TWIM */ + #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Max (0x6UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */ + #define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */ + + +/* TWIM_FREQUENCY: TWI frequency. Accuracy depends on the HFCLK source selected. */ + #define TWIM_FREQUENCY_ResetValue (0x04000000UL) /*!< Reset value of FREQUENCY register. */ + +/* FREQUENCY @Bits 0..31 : TWI master clock frequency */ + #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_Max (0xFF00000UL) /*!< Max enumerator value of FREQUENCY field. */ + #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps */ + + +/* TWIM_ADDRESS: Address used in the TWI transfer */ + #define TWIM_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..6 : Address used in the TWI transfer */ + #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ TWIS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct TWIS_TASKS_DMA_RX ================================================= */ +/** + * @brief RX [TWIS_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_TWIS_TASKS_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* TWIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================== Struct TWIS_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [TWIS_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_TWIS_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ +} NRF_TWIS_TASKS_DMA_Type; /*!< Size = 32 (0x020) */ + + +/* ============================================== Struct TWIS_SUBSCRIBE_DMA_RX =============================================== */ +/** + * @brief RX [TWIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_TWIS_SUBSCRIBE_DMA_RX_Type; /*!< Size = 32 (0x020) */ + +/* TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ================================================ Struct TWIS_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [TWIS_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_TWIS_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ +} NRF_TWIS_SUBSCRIBE_DMA_Type; /*!< Size = 32 (0x020) */ + + +/* ================================================ Struct TWIS_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [TWIS_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_TWIS_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================ Struct TWIS_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [TWIS_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_TWIS_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define TWIS_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define TWIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define TWIS_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define TWIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR + field.*/ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct TWIS_EVENTS_DMA ================================================== */ +/** + * @brief EVENTS_DMA [TWIS_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_TWIS_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_TWIS_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_TWIS_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct TWIS_PUBLISH_DMA_RX ================================================ */ +/** + * @brief RX [TWIS_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_TWIS_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* TWIS_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define TWIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define TWIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct TWIS_PUBLISH_DMA_TX ================================================ */ +/** + * @brief TX [TWIS_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_TWIS_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* TWIS_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define TWIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define TWIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================= Struct TWIS_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [TWIS_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_TWIS_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_TWIS_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_TWIS_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct TWIS_PSEL ===================================================== */ +/** + * @brief PSEL [TWIS_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} NRF_TWIS_PSEL_Type; /*!< Size = 8 (0x008) */ + +/* TWIS_PSEL_SCL: Pin select for SCL signal */ + #define TWIS_PSEL_SCL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SCL register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIS_PSEL_SCL_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Msk (0xFUL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIS_PSEL_SCL_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* TWIS_PSEL_SDA: Pin select for SDA signal */ + #define TWIS_PSEL_SDA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SDA register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define TWIS_PSEL_SDA_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Msk (0xFUL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define TWIS_PSEL_SDA_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct TWIS_DMA_RX_MATCH ================================================= */ +/** + * @brief MATCH [TWIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_TWIS_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* TWIS_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define TWIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* TWIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct TWIS_DMA_RX ==================================================== */ +/** + * @brief RX [TWIS_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IOM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_TWIS_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_TWIS_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* TWIS_DMA_RX_PTR: RAM buffer start address */ + #define TWIS_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIS_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIS_DMA_RX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_RX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TWIS_DMA_RX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TWIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define TWIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_RX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_RX_LIST: EasyDMA list type */ + #define TWIS_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct TWIS_DMA_TX ==================================================== */ +/** + * @brief TX [TWIS_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IOM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_TWIS_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* TWIS_DMA_TX_PTR: RAM buffer start address */ + #define TWIS_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define TWIS_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define TWIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* TWIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define TWIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define TWIS_DMA_TX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* TWIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each + MATCH event. */ + + #define TWIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_TX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define TWIS_DMA_TX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define TWIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define TWIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define TWIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define TWIS_DMA_TX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* TWIS_DMA_TX_LIST: EasyDMA list type */ + #define TWIS_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define TWIS_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Msk (0x7UL << TWIS_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define TWIS_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define TWIS_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ===================================================== Struct TWIS_DMA ===================================================== */ +/** + * @brief DMA [TWIS_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_TWIS_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_TWIS_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_TWIS_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ======================================================= Struct TWIS ======================================================= */ +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA + */ + typedef struct { /*!< TWIS Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000000C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000010) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000020) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000024) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[2]; + __OM NRF_TWIS_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000030) Peripheral tasks. */ + __IM uint32_t RESERVED4[13]; + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED5; + __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND */ + __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x00000090) Subscribe configuration for task RESUME */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000A0) Subscribe configuration for task PREPARERX */ + __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000A4) Subscribe configuration for task PREPARETX */ + __IM uint32_t RESERVED7[2]; + __IOM NRF_TWIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000B0) Subscribe configuration for tasks */ + __IM uint32_t RESERVED8[13]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED9[3]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) TWI error */ + __IM uint32_t RESERVED10[9]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x0000013C) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000140) Read command received */ + __IM uint32_t RESERVED11[2]; + __IOM NRF_TWIS_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IM uint32_t RESERVED12[4]; + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED13[3]; + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED14[9]; + __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001BC) Publish configuration for event WRITE */ + __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001C0) Publish configuration for event READ */ + __IM uint32_t RESERVED15[2]; + __IOM NRF_TWIS_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IM uint32_t RESERVED16[3]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED17[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED18[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had a match */ + __IM uint32_t RESERVED19[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED20[33]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) TWI slave address n */ + __IM uint32_t RESERVED21; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match mechanism*/ + __IM uint32_t RESERVED22[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an + over-read of the transmit buffer.*/ + __IM uint32_t RESERVED23[15]; + __IOM NRF_TWIS_PSEL_Type PSEL; /*!< (@ 0x00000600) (unspecified) */ + __IM uint32_t RESERVED24[62]; + __IOM NRF_TWIS_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_TWIS_Type; /*!< Size = 1884 (0x75C) */ + +/* TWIS_TASKS_STOP: Stop TWI transaction */ + #define TWIS_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop TWI transaction */ + #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_SUSPEND: Suspend TWI transaction */ + #define TWIS_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register. */ + +/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND + field.*/ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field. */ + #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_RESUME: Resume TWI transaction */ + #define TWIS_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register. */ + +/* TASKS_RESUME @Bit 0 : Resume TWI transaction */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field. */ + #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_PREPARERX: Prepare the TWI slave to respond to a write command */ + #define TWIS_TASKS_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARERX register. */ + +/* TASKS_PREPARERX @Bit 0 : Prepare the TWI slave to respond to a write command */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of + TASKS_PREPARERX field.*/ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARERX field. */ + #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_TASKS_PREPARETX: Prepare the TWI slave to respond to a read command */ + #define TWIS_TASKS_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARETX register. */ + +/* TASKS_PREPARETX @Bit 0 : Prepare the TWI slave to respond to a read command */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of + TASKS_PREPARETX field.*/ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARETX field. */ + #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */ + + +/* TWIS_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define TWIS_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */ + #define TWIS_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */ + #define TWIS_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_PREPARERX: Subscribe configuration for task PREPARERX */ + #define TWIS_SUBSCRIBE_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARERX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PREPARERX will subscribe to */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_SUBSCRIBE_PREPARETX: Subscribe configuration for task PREPARETX */ + #define TWIS_SUBSCRIBE_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARETX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task PREPARETX will subscribe to */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* TWIS_EVENTS_STOPPED: TWI stopped */ + #define TWIS_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : TWI stopped */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of + EVENTS_STOPPED field.*/ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_ERROR: TWI error */ + #define TWIS_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : TWI error */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_WRITE: Write command received */ + #define TWIS_EVENTS_WRITE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITE register. */ + +/* EVENTS_WRITE @Bit 0 : Write command received */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field.*/ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITE field. */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_EVENTS_READ: Read command received */ + #define TWIS_EVENTS_READ_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READ register. */ + +/* EVENTS_READ @Bit 0 : Read command received */ + #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Min (0x0UL) /*!< Min enumerator value of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_Max (0x1UL) /*!< Max enumerator value of EVENTS_READ field. */ + #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */ + #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */ + + +/* TWIS_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define TWIS_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define TWIS_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_WRITE: Publish configuration for event WRITE */ + #define TWIS_PUBLISH_WRITE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WRITE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event WRITE will publish to */ + #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_WRITE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_PUBLISH_READ: Publish configuration for event READ */ + #define TWIS_PUBLISH_READ_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READ register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READ will publish to */ + #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define TWIS_PUBLISH_READ_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ + #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ + #define TWIS_PUBLISH_READ_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define TWIS_PUBLISH_READ_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* TWIS_SHORTS: Shortcuts between local events and tasks */ + #define TWIS_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* WRITE_SUSPEND @Bit 13 : Shortcut between event WRITE and task SUSPEND */ + #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Min (0x0UL) /*!< Min enumerator value of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Max (0x1UL) /*!< Max enumerator value of WRITE_SUSPEND field. */ + #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* READ_SUSPEND @Bit 14 : Shortcut between event READ and task SUSPEND */ + #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Min (0x0UL) /*!< Min enumerator value of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Max (0x1UL) /*!< Max enumerator value of READ_SUSPEND field. */ + #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* TWIS_INTEN: Enable or disable interrupt */ + #define TWIS_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */ + #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define TWIS_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* WRITE @Bit 15 : Enable or disable interrupt for event WRITE */ + #define TWIS_INTEN_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTEN_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTEN_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */ + +/* READ @Bit 16 : Enable or disable interrupt for event READ */ + #define TWIS_INTEN_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTEN_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTEN_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define TWIS_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Msk (0x1UL << TWIS_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define TWIS_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Msk (0x1UL << TWIS_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define TWIS_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Msk (0x1UL << TWIS_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Msk (0x1UL << TWIS_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Msk (0x1UL << TWIS_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Msk (0x1UL << TWIS_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define TWIS_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Msk (0x1UL << TWIS_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define TWIS_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Msk (0x1UL << TWIS_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define TWIS_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define TWIS_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + + +/* TWIS_INTENSET: Enable interrupt */ + #define TWIS_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define TWIS_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITE @Bit 15 : Write '1' to enable interrupt for event WRITE */ + #define TWIS_INTENSET_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTENSET_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTENSET_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READ @Bit 16 : Write '1' to enable interrupt for event READ */ + #define TWIS_INTENSET_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTENSET_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTENSET_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define TWIS_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Msk (0x1UL << TWIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define TWIS_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Msk (0x1UL << TWIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define TWIS_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define TWIS_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Msk (0x1UL << TWIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define TWIS_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Msk (0x1UL << TWIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define TWIS_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define TWIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIS_INTENCLR: Disable interrupt */ + #define TWIS_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define TWIS_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* WRITE @Bit 15 : Write '1' to disable interrupt for event WRITE */ + #define TWIS_INTENCLR_WRITE_Pos (15UL) /*!< Position of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ + +/* READ @Bit 16 : Write '1' to disable interrupt for event READ */ + #define TWIS_INTENCLR_READ_Pos (16UL) /*!< Position of READ field. */ + #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ + #define TWIS_INTENCLR_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define TWIS_INTENCLR_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define TWIS_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Msk (0x1UL << TWIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define TWIS_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define TWIS_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Msk (0x1UL << TWIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define TWIS_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define TWIS_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define TWIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define TWIS_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define TWIS_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define TWIS_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define TWIS_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define TWIS_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define TWIS_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define TWIS_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define TWIS_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define TWIS_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Msk (0x1UL << TWIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define TWIS_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define TWIS_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Msk (0x1UL << TWIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define TWIS_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define TWIS_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define TWIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define TWIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define TWIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* TWIS_ERRORSRC: Error source */ + #define TWIS_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERFLOW @Bit 0 : RX buffer overflow detected, and prevented */ + #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field. */ + #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */ + +/* DNACK @Bit 2 : NACK sent after receiving a data byte */ + #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Min (0x0UL) /*!< Min enumerator value of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_Max (0x1UL) /*!< Max enumerator value of DNACK field. */ + #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ + +/* OVERREAD @Bit 3 : TX buffer over-read detected, and prevented */ + #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Min (0x0UL) /*!< Min enumerator value of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_Max (0x1UL) /*!< Max enumerator value of OVERREAD field. */ + #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */ + #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */ + + +/* TWIS_MATCH: Status register indicating which address had a match */ + #define TWIS_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH register. */ + +/* MATCH @Bit 0 : Indication of which address in ADDRESS that matched the incoming address */ + #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define TWIS_MATCH_MATCH_Min (0x0UL) /*!< Min value of MATCH field. */ + #define TWIS_MATCH_MATCH_Max (0x1UL) /*!< Max size of MATCH field. */ + + +/* TWIS_ENABLE: Enable TWIS */ + #define TWIS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable TWIS */ + #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Max (0x9UL) /*!< Max enumerator value of ENABLE field. */ + #define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */ + #define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */ + + +/* TWIS_ADDRESS: TWI slave address n */ + #define TWIS_ADDRESS_MaxCount (2UL) /*!< Max size of ADDRESS[2] array. */ + #define TWIS_ADDRESS_MaxIndex (1UL) /*!< Max index of ADDRESS[2] array. */ + #define TWIS_ADDRESS_MinIndex (0UL) /*!< Min index of ADDRESS[2] array. */ + #define TWIS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS[2] register. */ + +/* ADDRESS @Bits 0..6 : TWI slave address */ + #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* TWIS_CONFIG: Configuration register for the address match mechanism */ + #define TWIS_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register. */ + +/* ADDRESS0 @Bit 0 : Enable or disable address matching on ADDRESS[0] */ + #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Min (0x0UL) /*!< Min enumerator value of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Max (0x1UL) /*!< Max enumerator value of ADDRESS0 field. */ + #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */ + #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */ + +/* ADDRESS1 @Bit 1 : Enable or disable address matching on ADDRESS[1] */ + #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Min (0x0UL) /*!< Min enumerator value of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Max (0x1UL) /*!< Max enumerator value of ADDRESS1 field. */ + #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */ + #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */ + + +/* TWIS_ORC: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + #define TWIS_ORC_ResetValue (0x00000000UL) /*!< Reset value of ORC register. */ + +/* ORC @Bits 0..7 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ + #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ UARTE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================ Struct UARTE_TASKS_DMA_RX ================================================ */ +/** + * @brief RX [UARTE_TASKS_DMA_RX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ + __OM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit + in the CONFIG register.*/ + __OM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n] + bit in the CONFIG register.*/ +} NRF_UARTE_TASKS_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* UARTE_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define UARTE_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define UARTE_TASKS_DMA_RX_START_START_Pos (0UL) /*!< Position of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define UARTE_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask + of ENABLEMATCH field.*/ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit + mask of DISABLEMATCH field.*/ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field. */ + #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================ Struct UARTE_TASKS_DMA_TX ================================================ */ +/** + * @brief TX [UARTE_TASKS_DMA_TX] Peripheral tasks. + */ +typedef struct { + __OM uint32_t START; /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See + peripheral description for operation using easyDMA.*/ + __OM uint32_t STOP; /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an + END event.*/ +} NRF_UARTE_TASKS_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* UARTE_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using + easyDMA. */ + + #define UARTE_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */ + #define UARTE_TASKS_DMA_TX_START_START_Pos (0UL) /*!< Position of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Min (0x1UL) /*!< Min enumerator value of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Max (0x1UL) /*!< Max enumerator value of START field. */ + #define UARTE_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Pos (0UL) /*!< Position of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Min (0x1UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task */ + + + +/* ================================================= Struct UARTE_TASKS_DMA ================================================== */ +/** + * @brief TASKS_DMA [UARTE_TASKS_DMA] Peripheral tasks. + */ +typedef struct { + __OM NRF_UARTE_TASKS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral tasks. */ + __OM NRF_UARTE_TASKS_DMA_TX_Type TX; /*!< (@ 0x00000028) Peripheral tasks. */ +} NRF_UARTE_TASKS_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* ============================================== Struct UARTE_SUBSCRIBE_DMA_RX ============================================== */ +/** + * @brief RX [UARTE_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ + __IOM uint32_t ENABLEMATCH[4]; /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n] */ + __IOM uint32_t DISABLEMATCH[4]; /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n] */ +} NRF_UARTE_SUBSCRIBE_DMA_RX_Type; /*!< Size = 40 (0x028) */ + +/* UARTE_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */ + #define UARTE_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of + CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask + of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN + field.*/ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* ============================================== Struct UARTE_SUBSCRIBE_DMA_TX ============================================== */ +/** + * @brief TX [UARTE_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Subscribe configuration for task START */ + __IOM uint32_t STOP; /*!< (@ 0x00000004) Subscribe configuration for task STOP */ +} NRF_UARTE_SUBSCRIBE_DMA_TX_Type; /*!< Size = 8 (0x008) */ + +/* UARTE_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */ + #define UARTE_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + + +/* =============================================== Struct UARTE_SUBSCRIBE_DMA ================================================ */ +/** + * @brief SUBSCRIBE_DMA [UARTE_SUBSCRIBE_DMA] Subscribe configuration for tasks + */ +typedef struct { + __IOM NRF_UARTE_SUBSCRIBE_DMA_RX_Type RX; /*!< (@ 0x00000000) Subscribe configuration for tasks */ + __IOM NRF_UARTE_SUBSCRIBE_DMA_TX_Type TX; /*!< (@ 0x00000028) Subscribe configuration for tasks */ +} NRF_UARTE_SUBSCRIBE_DMA_Type; /*!< Size = 48 (0x030) */ + + +/* =============================================== Struct UARTE_EVENTS_DMA_RX ================================================ */ +/** + * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus. */ +} NRF_UARTE_EVENTS_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL) /*!< Position of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define UARTE_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_RX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of + BUSERROR field.*/ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define UARTE_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field. */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated */ + + + +/* =============================================== Struct UARTE_EVENTS_DMA_TX ================================================ */ +/** + * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events. + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/ + __IOM uint32_t READY; /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and + .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence.*/ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) An error occured during the bus transfer. */ +} NRF_UARTE_EVENTS_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */ + #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL) /*!< Position of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL) /*!< Min enumerator value of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_Max (0x1UL) /*!< Max enumerator value of END field. */ + #define UARTE_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them + to be written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be + written to prepare for the next sequence. */ + + #define UARTE_EVENTS_DMA_TX_READY_READY_Pos (0UL) /*!< Position of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field. */ + #define UARTE_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* BUSERROR @Bit 0 : An error occured during the bus transfer. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of + BUSERROR field.*/ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field. */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated */ + + + +/* ================================================= Struct UARTE_EVENTS_DMA ================================================= */ +/** + * @brief EVENTS_DMA [UARTE_EVENTS_DMA] Peripheral events. + */ +typedef struct { + __IOM NRF_UARTE_EVENTS_DMA_RX_Type RX; /*!< (@ 0x00000000) Peripheral events. */ + __IOM NRF_UARTE_EVENTS_DMA_TX_Type TX; /*!< (@ 0x0000001C) Peripheral events. */ +} NRF_UARTE_EVENTS_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* =============================================== Struct UARTE_PUBLISH_DMA_RX =============================================== */ +/** + * @brief RX [UARTE_PUBLISH_DMA_RX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ + __IOM uint32_t MATCH[4]; /*!< (@ 0x0000000C) Publish configuration for event MATCH[n] */ +} NRF_UARTE_PUBLISH_DMA_RX_Type; /*!< Size = 28 (0x01C) */ + +/* UARTE_PUBLISH_DMA_RX_END: Publish configuration for event END */ + #define UARTE_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_READY: Publish configuration for event READY */ + #define UARTE_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MaxCount (4UL) /*!< Max size of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL) /*!< Max index of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_MinIndex (0UL) /*!< Min index of MATCH[4] array. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* =============================================== Struct UARTE_PUBLISH_DMA_TX =============================================== */ +/** + * @brief TX [UARTE_PUBLISH_DMA_TX] Publish configuration for events + */ +typedef struct { + __IOM uint32_t END; /*!< (@ 0x00000000) Publish configuration for event END */ + __IOM uint32_t READY; /*!< (@ 0x00000004) Publish configuration for event READY */ + __IOM uint32_t BUSERROR; /*!< (@ 0x00000008) Publish configuration for event BUSERROR */ +} NRF_UARTE_PUBLISH_DMA_TX_Type; /*!< Size = 12 (0x00C) */ + +/* UARTE_PUBLISH_DMA_TX_END: Publish configuration for event END */ + #define UARTE_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_TX_READY: Publish configuration for event READY */ + #define UARTE_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX + field.*/ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + + +/* ================================================ Struct UARTE_PUBLISH_DMA ================================================= */ +/** + * @brief PUBLISH_DMA [UARTE_PUBLISH_DMA] Publish configuration for events + */ +typedef struct { + __IOM NRF_UARTE_PUBLISH_DMA_RX_Type RX; /*!< (@ 0x00000000) Publish configuration for events */ + __IOM NRF_UARTE_PUBLISH_DMA_TX_Type TX; /*!< (@ 0x0000001C) Publish configuration for events */ +} NRF_UARTE_PUBLISH_DMA_Type; /*!< Size = 40 (0x028) */ + + +/* ==================================================== Struct UARTE_PSEL ==================================================== */ +/** + * @brief PSEL [UARTE_PSEL] (unspecified) + */ +typedef struct { + __IOM uint32_t TXD; /*!< (@ 0x00000000) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000004) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x00000008) Pin select for RXD signal */ + __IOM uint32_t RTS; /*!< (@ 0x0000000C) Pin select for RTS signal */ +} NRF_UARTE_PSEL_Type; /*!< Size = 16 (0x010) */ + +/* UARTE_PSEL_TXD: Pin select for TXD signal */ + #define UARTE_PSEL_TXD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TXD register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_TXD_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Msk (0xFUL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_TXD_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_CTS: Pin select for CTS signal */ + #define UARTE_PSEL_CTS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CTS register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_CTS_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Msk (0xFUL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_CTS_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_RXD: Pin select for RXD signal */ + #define UARTE_PSEL_RXD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RXD register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_RXD_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Msk (0xFUL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_RXD_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */ + + +/* UARTE_PSEL_RTS: Pin select for RTS signal */ + #define UARTE_PSEL_RTS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RTS register. */ + +/* PIN @Bits 0..4 : Pin number */ + #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Min (0x00UL) /*!< Min value of PIN field. */ + #define UARTE_PSEL_RTS_PIN_Max (0x1FUL) /*!< Max size of PIN field. */ + +/* PORT @Bits 5..8 : Port number */ + #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Msk (0xFUL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Min (0x0UL) /*!< Min value of PORT field. */ + #define UARTE_PSEL_RTS_PORT_Max (0xFUL) /*!< Max size of PORT field. */ + +/* CONNECT @Bit 31 : Connection */ + #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Min (0x0UL) /*!< Min enumerator value of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Max (0x1UL) /*!< Max enumerator value of CONNECT field. */ + #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ + #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */ + + + +/* ================================================ Struct UARTE_DMA_RX_MATCH ================================================ */ +/** + * @brief MATCH [UARTE_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Configure individual match events */ + __IOM uint32_t CANDIDATE[4]; /*!< (@ 0x00000004) The data to look for - any match will trigger the + MATCH[n] event, if enabled.*/ +} NRF_UARTE_DMA_RX_MATCH_Type; /*!< Size = 20 (0x014) */ + +/* UARTE_DMA_RX_MATCH_CONFIG: Configure individual match events */ + #define UARTE_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* ENABLE0 @Bit 0 : Enable match filter 0 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE1 @Bit 1 : Enable match filter 1 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE2 @Bit 2 : Enable match filter 2 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ENABLE3 @Bit 3 : Enable match filter 3 */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled */ + #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled */ + +/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + +/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3 + field.*/ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field. */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task */ + #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received */ + + +/* UARTE_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register. */ + +/* DATA @Bits 0..31 : Data to look for */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA + field.*/ + + + +/* =================================================== Struct UARTE_DMA_RX =================================================== */ +/** + * @brief RX [UARTE_DMA_RX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ + __IOM NRF_UARTE_DMA_RX_MATCH_Type MATCH; /*!< (@ 0x00000024) Registers to control the behavior of the pattern + matcher engine*/ +} NRF_UARTE_DMA_RX_Type; /*!< Size = 56 (0x038) */ + +/* UARTE_DMA_RX_PTR: RAM buffer start address */ + #define UARTE_DMA_RX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define UARTE_DMA_RX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define UARTE_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* UARTE_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */ + #define UARTE_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define UARTE_DMA_RX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* UARTE_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after + each MATCH event. */ + + #define UARTE_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_RX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define UARTE_DMA_RX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define UARTE_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_DMA_RX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define UARTE_DMA_RX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_RX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_RX_LIST: EasyDMA list type */ + #define UARTE_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_RX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_RX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_RX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* =================================================== Struct UARTE_DMA_TX =================================================== */ +/** + * @brief TX [UARTE_DMA_TX] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED; + __IOM uint32_t PTR; /*!< (@ 0x00000004) RAM buffer start address */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000008) Maximum number of bytes in channel buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction, + updated after the END event. Also updated after each + MATCH event.*/ + __IM uint32_t CURRENTAMOUNT; /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/ + __IOM uint32_t LIST; /*!< (@ 0x00000014) EasyDMA list type */ + __IM uint32_t RESERVED1; + __IOM uint32_t TERMINATEONBUSERROR; /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is + detected.*/ + __IM uint32_t BUSERRORADDRESS; /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR + event.*/ +} NRF_UARTE_DMA_TX_Type; /*!< Size = 36 (0x024) */ + +/* UARTE_DMA_TX_PTR: RAM buffer start address */ + #define UARTE_DMA_TX_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */ + #define UARTE_DMA_TX_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define UARTE_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* UARTE_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */ + #define UARTE_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register. */ + +/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL) /*!< Min value of MAXCNT field. */ + #define UARTE_DMA_TX_MAXCNT_MAXCNT_Max (0x7FFFUL) /*!< Max size of MAXCNT field. */ + + +/* UARTE_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after + each MATCH event. */ + + #define UARTE_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_TX_CURRENTAMOUNT: Number of bytes transferred in the current transaction */ + #define UARTE_DMA_TX_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register. */ + +/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */ + #define UARTE_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ + #define UARTE_DMA_TX_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_DMA_TX_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT + field.*/ + #define UARTE_DMA_TX_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field. */ + #define UARTE_DMA_TX_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field. */ + + +/* UARTE_DMA_TX_LIST: EasyDMA list type */ + #define UARTE_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register. */ + +/* TYPE @Bits 0..2 : List type */ + #define UARTE_DMA_TX_LIST_TYPE_Pos (0UL) /*!< Position of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Msk (0x7UL << UARTE_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Max (0x1UL) /*!< Max enumerator value of TYPE field. */ + #define UARTE_DMA_TX_LIST_TYPE_Disabled (0x0UL) /*!< Disable EasyDMA list */ + #define UARTE_DMA_TX_LIST_TYPE_ArrayList (0x1UL) /*!< Use array list */ + + +/* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register. */ + +/* ENABLE @Bit 0 : (unspecified) */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of + ENABLE field.*/ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable */ + #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register. */ + +/* ADDRESS @Bits 0..31 : (unspecified) */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + + +/* ==================================================== Struct UARTE_DMA ===================================================== */ +/** + * @brief DMA [UARTE_DMA] (unspecified) + */ +typedef struct { + __IOM NRF_UARTE_DMA_RX_Type RX; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UARTE_DMA_TX_Type TX; /*!< (@ 0x00000038) (unspecified) */ +} NRF_UARTE_DMA_Type; /*!< Size = 92 (0x05C) */ + +/* ====================================================== Struct UARTE ======================================================= */ +/** + * @brief UART with EasyDMA + */ + typedef struct { /*!< UARTE Structure */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000001C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[2]; + __OM NRF_UARTE_TASKS_DMA_Type TASKS_DMA; /*!< (@ 0x00000028) Peripheral tasks. */ + __IM uint32_t RESERVED2[17]; + __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x0000009C) Subscribe configuration for task FLUSHRX */ + __IM uint32_t RESERVED3[2]; + __IOM NRF_UARTE_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks */ + __IM uint32_t RESERVED4[10]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000010C) Data sent from TXD */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000110) Data received in RXD (but potentially not yet + transferred to Data RAM)*/ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000114) Error detected */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000124) Receiver timeout */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000130) Transmitter stopped */ + __IM uint32_t RESERVED8[6]; + __IOM NRF_UARTE_EVENTS_DMA_Type EVENTS_DMA; /*!< (@ 0x0000014C) Peripheral events. */ + __IOM uint32_t EVENTS_FRAMETIMEOUT; /*!< (@ 0x00000174) Timed out due to bus being idle while receiving data. */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ + __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ + __IM uint32_t RESERVED10; + __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000018C) Publish configuration for event TXDRDY */ + __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000190) Publish configuration for event RXDRDY */ + __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000194) Publish configuration for event ERROR */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001A4) Publish configuration for event RXTO */ + __IM uint32_t RESERVED12[2]; + __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001B0) Publish configuration for event TXSTOPPED */ + __IM uint32_t RESERVED13[6]; + __IOM NRF_UARTE_PUBLISH_DMA_Type PUBLISH_DMA; /*!< (@ 0x000001CC) Publish configuration for events */ + __IOM uint32_t PUBLISH_FRAMETIMEOUT; /*!< (@ 0x000001F4) Publish configuration for event FRAMETIMEOUT */ + __IM uint32_t RESERVED14[2]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED15[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED16[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED17[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED18[8]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected.*/ + __IM uint32_t RESERVED19[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity, hardware flow control, + framesize, and packet timeout.*/ + __IM uint32_t RESERVED20; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000574) Set the address of the UARTE for RX when used in 9 bit + data frame mode.*/ + __IOM uint32_t FRAMETIMEOUT; /*!< (@ 0x00000578) Set the number of UARTE bits to count before triggering + packet timeout.*/ + __IM uint32_t RESERVED21[34]; + __IOM NRF_UARTE_PSEL_Type PSEL; /*!< (@ 0x00000604) (unspecified) */ + __IM uint32_t RESERVED22[59]; + __IOM NRF_UARTE_DMA_Type DMA; /*!< (@ 0x00000700) (unspecified) */ + } NRF_UARTE_Type; /*!< Size = 1884 (0x75C) */ + +/* UARTE_TASKS_FLUSHRX: Flush RX FIFO into RX buffer */ + #define UARTE_TASKS_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHRX register. */ + +/* TASKS_FLUSHRX @Bit 0 : Flush RX FIFO into RX buffer */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX + field.*/ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHRX field. */ + #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */ + + +/* UARTE_SUBSCRIBE_FLUSHRX: Subscribe configuration for task FLUSHRX */ + #define UARTE_SUBSCRIBE_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_FLUSHRX register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task FLUSHRX will subscribe to */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* UARTE_EVENTS_CTS: CTS is activated (set low). Clear To Send. */ + #define UARTE_EVENTS_CTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTS register. */ + +/* EVENTS_CTS @Bit 0 : CTS is activated (set low). Clear To Send. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTS field. */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_NCTS: CTS is deactivated (set high). Not Clear To Send. */ + #define UARTE_EVENTS_NCTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NCTS register. */ + +/* EVENTS_NCTS @Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Min (0x0UL) /*!< Min enumerator value of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Max (0x1UL) /*!< Max enumerator value of EVENTS_NCTS field. */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_TXDRDY: Data sent from TXD */ + #define UARTE_EVENTS_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDRDY register. */ + +/* EVENTS_TXDRDY @Bit 0 : Data sent from TXD */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY + field.*/ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDRDY field. */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_RXDRDY: Data received in RXD (but potentially not yet transferred to Data RAM) */ + #define UARTE_EVENTS_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXDRDY register. */ + +/* EVENTS_RXDRDY @Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY + field.*/ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXDRDY field. */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_ERROR: Error detected */ + #define UARTE_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register. */ + +/* EVENTS_ERROR @Bit 0 : Error detected */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR + field.*/ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field. */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_RXTO: Receiver timeout */ + #define UARTE_EVENTS_RXTO_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXTO register. */ + +/* EVENTS_RXTO @Bit 0 : Receiver timeout */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXTO field. */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_TXSTOPPED: Transmitter stopped */ + #define UARTE_EVENTS_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTOPPED register. */ + +/* EVENTS_TXSTOPPED @Bit 0 : Transmitter stopped */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of + EVENTS_TXSTOPPED field.*/ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTOPPED field. */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_EVENTS_FRAMETIMEOUT: Timed out due to bus being idle while receiving data. */ + #define UARTE_EVENTS_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMETIMEOUT register. */ + +/* EVENTS_FRAMETIMEOUT @Bit 0 : Timed out due to bus being idle while receiving data. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos (0UL) /*!< Position of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Msk (0x1UL << UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos) /*!< + Bit mask of EVENTS_FRAMETIMEOUT field.*/ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMETIMEOUT field. */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ + #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Generated (0x1UL) /*!< Event generated */ + + +/* UARTE_PUBLISH_CTS: Publish configuration for event CTS */ + #define UARTE_PUBLISH_CTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event CTS will publish to */ + #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_CTS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_NCTS: Publish configuration for event NCTS */ + #define UARTE_PUBLISH_NCTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NCTS register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event NCTS will publish to */ + #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_NCTS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_TXDRDY: Publish configuration for event TXDRDY */ + #define UARTE_PUBLISH_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXDRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXDRDY will publish to */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_TXDRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_RXDRDY: Publish configuration for event RXDRDY */ + #define UARTE_PUBLISH_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXDRDY register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXDRDY will publish to */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_RXDRDY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_ERROR: Publish configuration for event ERROR */ + #define UARTE_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */ + #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_ERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_RXTO: Publish configuration for event RXTO */ + #define UARTE_PUBLISH_RXTO_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXTO register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXTO will publish to */ + #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_RXTO_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_TXSTOPPED: Publish configuration for event TXSTOPPED */ + #define UARTE_PUBLISH_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXSTOPPED will publish to */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_PUBLISH_FRAMETIMEOUT: Publish configuration for event FRAMETIMEOUT */ + #define UARTE_PUBLISH_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMETIMEOUT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event FRAMETIMEOUT will publish to */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Msk (0x1UL << UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* UARTE_SHORTS: Shortcuts between local events and tasks */ + #define UARTE_SHORTS_ResetValue (0x00000000UL) /*!< Reset value of SHORTS register. */ + +/* DMA_RX_END_DMA_RX_START @Bit 5 : Shortcut between event DMA.RX.END and task DMA.RX.START */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos (5UL) /*!< Position of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos) /*!< Bit mask of + DMA_RX_END_DMA_RX_START field.*/ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_START field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_END_DMA_RX_STOP @Bit 6 : Shortcut between event DMA.RX.END and task DMA.RX.STOP */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos (6UL) /*!< Position of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos) /*!< Bit mask of + DMA_RX_END_DMA_RX_STOP field.*/ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_STOP field. */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_TX_END_DMA_TX_STOP @Bit 18 : Shortcut between event DMA.TX.END and task DMA.TX.STOP */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos (18UL) /*!< Position of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos) /*!< Bit mask of + DMA_TX_END_DMA_TX_STOP field.*/ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_TX_END_DMA_TX_STOP field. */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!< + Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!< + Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!< + Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows + daisy-chaining match events. */ + + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field. */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!< + Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) + /*!< Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) + /*!< Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) + /*!< Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut */ + +/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) + /*!< Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 + field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of + DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut */ + +/* FRAMETIMEOUT_DMA_RX_STOP @Bit 29 : Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos (29UL) /*!< Position of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos) /*!< Bit mask of + FRAMETIMEOUT_DMA_RX_STOP field.*/ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT_DMA_RX_STOP field. */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ + #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ + + +/* UARTE_INTEN: Enable or disable interrupt */ + #define UARTE_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CTS @Bit 0 : Enable or disable interrupt for event CTS */ + #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTEN_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTEN_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */ + +/* NCTS @Bit 1 : Enable or disable interrupt for event NCTS */ + #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTEN_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTEN_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */ + +/* TXDRDY @Bit 3 : Enable or disable interrupt for event TXDRDY */ + #define UARTE_INTEN_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */ + +/* RXDRDY @Bit 4 : Enable or disable interrupt for event RXDRDY */ + #define UARTE_INTEN_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */ + +/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */ + #define UARTE_INTEN_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTEN_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTEN_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ + +/* RXTO @Bit 9 : Enable or disable interrupt for event RXTO */ + #define UARTE_INTEN_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTEN_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTEN_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */ + +/* TXSTOPPED @Bit 12 : Enable or disable interrupt for event TXSTOPPED */ + #define UARTE_INTEN_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */ + +/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */ + #define UARTE_INTEN_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Msk (0x1UL << UARTE_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTEN_DMARXEND_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */ + #define UARTE_INTEN_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Msk (0x1UL << UARTE_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTEN_DMARXREADY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */ + #define UARTE_INTEN_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTEN_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Msk (0x1UL << UARTE_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTEN_DMARXMATCH0_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH0_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTEN_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Msk (0x1UL << UARTE_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTEN_DMARXMATCH1_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH1_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTEN_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Msk (0x1UL << UARTE_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTEN_DMARXMATCH2_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH2_Enabled (0x1UL) /*!< Enable */ + +/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTEN_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Msk (0x1UL << UARTE_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTEN_DMARXMATCH3_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMARXMATCH3_Enabled (0x1UL) /*!< Enable */ + +/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */ + #define UARTE_INTEN_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Msk (0x1UL << UARTE_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTEN_DMATXEND_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXEND_Enabled (0x1UL) /*!< Enable */ + +/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */ + #define UARTE_INTEN_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Msk (0x1UL << UARTE_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTEN_DMATXREADY_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXREADY_Enabled (0x1UL) /*!< Enable */ + +/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */ + #define UARTE_INTEN_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_DMATXBUSERROR_Enabled (0x1UL) /*!< Enable */ + +/* FRAMETIMEOUT @Bit 29 : Enable or disable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTEN_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTEN_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTEN_FRAMETIMEOUT_Disabled (0x0UL) /*!< Disable */ + #define UARTE_INTEN_FRAMETIMEOUT_Enabled (0x1UL) /*!< Enable */ + + +/* UARTE_INTENSET: Enable interrupt */ + #define UARTE_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CTS @Bit 0 : Write '1' to enable interrupt for event CTS */ + #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTENSET_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTENSET_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NCTS @Bit 1 : Write '1' to enable interrupt for event NCTS */ + #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTENSET_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTENSET_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDRDY @Bit 3 : Write '1' to enable interrupt for event TXDRDY */ + #define UARTE_INTENSET_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXDRDY @Bit 4 : Write '1' to enable interrupt for event RXDRDY */ + #define UARTE_INTENSET_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */ + #define UARTE_INTENSET_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTENSET_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTENSET_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXTO @Bit 9 : Write '1' to enable interrupt for event RXTO */ + #define UARTE_INTENSET_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTENSET_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTENSET_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXSTOPPED @Bit 12 : Write '1' to enable interrupt for event TXSTOPPED */ + #define UARTE_INTENSET_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */ + #define UARTE_INTENSET_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Msk (0x1UL << UARTE_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTENSET_DMARXEND_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */ + #define UARTE_INTENSET_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Msk (0x1UL << UARTE_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTENSET_DMARXREADY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */ + #define UARTE_INTENSET_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENSET_DMARXBUSERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTENSET_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENSET_DMARXMATCH0_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTENSET_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENSET_DMARXMATCH1_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTENSET_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENSET_DMARXMATCH2_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTENSET_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENSET_DMARXMATCH3_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */ + #define UARTE_INTENSET_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Msk (0x1UL << UARTE_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTENSET_DMATXEND_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */ + #define UARTE_INTENSET_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Msk (0x1UL << UARTE_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTENSET_DMATXREADY_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */ + #define UARTE_INTENSET_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENSET_DMATXBUSERROR_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMETIMEOUT @Bit 29 : Write '1' to enable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTENSET_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENSET_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENSET_FRAMETIMEOUT_Set (0x1UL) /*!< Enable */ + #define UARTE_INTENSET_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENSET_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* UARTE_INTENCLR: Disable interrupt */ + #define UARTE_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CTS @Bit 0 : Write '1' to disable interrupt for event CTS */ + #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ + #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ + #define UARTE_INTENCLR_CTS_Min (0x0UL) /*!< Min enumerator value of CTS field. */ + #define UARTE_INTENCLR_CTS_Max (0x1UL) /*!< Max enumerator value of CTS field. */ + #define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* NCTS @Bit 1 : Write '1' to disable interrupt for event NCTS */ + #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Min (0x0UL) /*!< Min enumerator value of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Max (0x1UL) /*!< Max enumerator value of NCTS field. */ + #define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXDRDY @Bit 3 : Write '1' to disable interrupt for event TXDRDY */ + #define UARTE_INTENCLR_TXDRDY_Pos (3UL) /*!< Position of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Min (0x0UL) /*!< Min enumerator value of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Max (0x1UL) /*!< Max enumerator value of TXDRDY field. */ + #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXDRDY @Bit 4 : Write '1' to disable interrupt for event RXDRDY */ + #define UARTE_INTENCLR_RXDRDY_Pos (4UL) /*!< Position of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Min (0x0UL) /*!< Min enumerator value of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Max (0x1UL) /*!< Max enumerator value of RXDRDY field. */ + #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */ + #define UARTE_INTENCLR_ERROR_Pos (5UL) /*!< Position of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field. */ + #define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* RXTO @Bit 9 : Write '1' to disable interrupt for event RXTO */ + #define UARTE_INTENCLR_RXTO_Pos (9UL) /*!< Position of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Min (0x0UL) /*!< Min enumerator value of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Max (0x1UL) /*!< Max enumerator value of RXTO field. */ + #define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TXSTOPPED @Bit 12 : Write '1' to disable interrupt for event TXSTOPPED */ + #define UARTE_INTENCLR_TXSTOPPED_Pos (12UL) /*!< Position of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of TXSTOPPED field. */ + #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */ + #define UARTE_INTENCLR_DMARXEND_Pos (19UL) /*!< Position of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Msk (0x1UL << UARTE_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Min (0x0UL) /*!< Min enumerator value of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Max (0x1UL) /*!< Max enumerator value of DMARXEND field. */ + #define UARTE_INTENCLR_DMARXEND_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */ + #define UARTE_INTENCLR_DMARXREADY_Pos (20UL) /*!< Position of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Msk (0x1UL << UARTE_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Min (0x0UL) /*!< Min enumerator value of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Max (0x1UL) /*!< Max enumerator value of DMARXREADY field. */ + #define UARTE_INTENCLR_DMARXREADY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */ + #define UARTE_INTENCLR_DMARXBUSERROR_Pos (21UL) /*!< Position of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMARXBUSERROR field. */ + #define UARTE_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */ + #define UARTE_INTENCLR_DMARXMATCH0_Pos (22UL) /*!< Position of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH0 field. */ + #define UARTE_INTENCLR_DMARXMATCH0_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */ + #define UARTE_INTENCLR_DMARXMATCH1_Pos (23UL) /*!< Position of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH1 field. */ + #define UARTE_INTENCLR_DMARXMATCH1_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */ + #define UARTE_INTENCLR_DMARXMATCH2_Pos (24UL) /*!< Position of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH2 field. */ + #define UARTE_INTENCLR_DMARXMATCH2_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */ + #define UARTE_INTENCLR_DMARXMATCH3_Pos (25UL) /*!< Position of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Min (0x0UL) /*!< Min enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Max (0x1UL) /*!< Max enumerator value of DMARXMATCH3 field. */ + #define UARTE_INTENCLR_DMARXMATCH3_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */ + #define UARTE_INTENCLR_DMATXEND_Pos (26UL) /*!< Position of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Msk (0x1UL << UARTE_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Min (0x0UL) /*!< Min enumerator value of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Max (0x1UL) /*!< Max enumerator value of DMATXEND field. */ + #define UARTE_INTENCLR_DMATXEND_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXEND_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXEND_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */ + #define UARTE_INTENCLR_DMATXREADY_Pos (27UL) /*!< Position of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Msk (0x1UL << UARTE_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Min (0x0UL) /*!< Min enumerator value of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Max (0x1UL) /*!< Max enumerator value of DMATXREADY field. */ + #define UARTE_INTENCLR_DMATXREADY_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXREADY_Enabled (0x1UL) /*!< Read: Enabled */ + +/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */ + #define UARTE_INTENCLR_DMATXBUSERROR_Pos (28UL) /*!< Position of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Min (0x0UL) /*!< Min enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Max (0x1UL) /*!< Max enumerator value of DMATXBUSERROR field. */ + #define UARTE_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled */ + +/* FRAMETIMEOUT @Bit 29 : Write '1' to disable interrupt for event FRAMETIMEOUT */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Pos (29UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENCLR_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Clear (0x1UL) /*!< Disable */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define UARTE_INTENCLR_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* UARTE_ERRORSRC: Error source */ + #define UARTE_ERRORSRC_ResetValue (0x00000000UL) /*!< Reset value of ERRORSRC register. */ + +/* OVERRUN @Bit 0 : Overrun error */ + #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Min (0x0UL) /*!< Min enumerator value of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_Max (0x1UL) /*!< Max enumerator value of OVERRUN field. */ + #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */ + +/* PARITY @Bit 1 : Parity error */ + #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_Max (0x1UL) /*!< Max enumerator value of PARITY field. */ + #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */ + +/* FRAMING @Bit 2 : Framing error occurred */ + #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Min (0x0UL) /*!< Min enumerator value of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_Max (0x1UL) /*!< Max enumerator value of FRAMING field. */ + #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */ + +/* BREAK @Bit 3 : Break condition */ + #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Min (0x0UL) /*!< Min enumerator value of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_Max (0x1UL) /*!< Max enumerator value of BREAK field. */ + #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */ + #define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */ + + +/* UARTE_ENABLE: Enable UART */ + #define UARTE_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bits 0..3 : Enable or disable UARTE */ + #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Max (0x8UL) /*!< Max enumerator value of ENABLE field. */ + #define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */ + #define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */ + + +/* UARTE_BAUDRATE: Baud rate. Accuracy depends on the HFCLK source selected. */ + #define UARTE_BAUDRATE_ResetValue (0x04000000UL) /*!< Reset value of BAUDRATE register. */ + +/* BAUDRATE @Bits 0..31 : Baud rate */ + #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Min (0x4F000UL) /*!< Min enumerator value of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field. */ + #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ + #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ + #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ + #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ + + +/* UARTE_CONFIG: Configuration of parity, hardware flow control, framesize, and packet timeout. */ + #define UARTE_CONFIG_ResetValue (0x00001000UL) /*!< Reset value of CONFIG register. */ + +/* HWFC @Bit 0 : Hardware flow control */ + #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ + #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ + #define UARTE_CONFIG_HWFC_Min (0x0UL) /*!< Min enumerator value of HWFC field. */ + #define UARTE_CONFIG_HWFC_Max (0x1UL) /*!< Max enumerator value of HWFC field. */ + #define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */ + #define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */ + +/* PARITY @Bits 1..3 : Parity */ + #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ + #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ + #define UARTE_CONFIG_PARITY_Min (0x0UL) /*!< Min enumerator value of PARITY field. */ + #define UARTE_CONFIG_PARITY_Max (0x7UL) /*!< Max enumerator value of PARITY field. */ + #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ + #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* STOP @Bit 4 : Stop bits */ + #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ + #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ + #define UARTE_CONFIG_STOP_Min (0x0UL) /*!< Min enumerator value of STOP field. */ + #define UARTE_CONFIG_STOP_Max (0x1UL) /*!< Max enumerator value of STOP field. */ + #define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */ + #define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */ + +/* PARITYTYPE @Bit 8 : Even or odd parity type */ + #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Min (0x0UL) /*!< Min enumerator value of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Max (0x1UL) /*!< Max enumerator value of PARITYTYPE field. */ + #define UARTE_CONFIG_PARITYTYPE_Even (0x0UL) /*!< Even parity */ + #define UARTE_CONFIG_PARITYTYPE_Odd (0x1UL) /*!< Odd parity */ + +/* FRAMESIZE @Bits 9..12 : Set the data frame size */ + #define UARTE_CONFIG_FRAMESIZE_Pos (9UL) /*!< Position of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Msk (0xFUL << UARTE_CONFIG_FRAMESIZE_Pos) /*!< Bit mask of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Min (0x4UL) /*!< Min enumerator value of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_Max (0x9UL) /*!< Max enumerator value of FRAMESIZE field. */ + #define UARTE_CONFIG_FRAMESIZE_9bit (0x9UL) /*!< 9 bit data frame size. 9th bit is treated as address bit. */ + #define UARTE_CONFIG_FRAMESIZE_8bit (0x8UL) /*!< 8 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_7bit (0x7UL) /*!< 7 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_6bit (0x6UL) /*!< 6 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_5bit (0x5UL) /*!< 5 bit data frame size. */ + #define UARTE_CONFIG_FRAMESIZE_4bit (0x4UL) /*!< 4 bit data frame size. */ + +/* ENDIAN @Bit 13 : Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. */ + #define UARTE_CONFIG_ENDIAN_Pos (13UL) /*!< Position of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Msk (0x1UL << UARTE_CONFIG_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Min (0x0UL) /*!< Min enumerator value of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_Max (0x1UL) /*!< Max enumerator value of ENDIAN field. */ + #define UARTE_CONFIG_ENDIAN_MSB (0x0UL) /*!< Data is trimmed from MSB end. */ + #define UARTE_CONFIG_ENDIAN_LSB (0x1UL) /*!< Data is trimmed from LSB end. */ + +/* FRAMETIMEOUT @Bit 14 : Enable packet timeout. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Pos (14UL) /*!< Position of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Msk (0x1UL << UARTE_CONFIG_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT field. */ + #define UARTE_CONFIG_FRAMETIMEOUT_DISABLED (0x0UL) /*!< Packet timeout is disabled. */ + #define UARTE_CONFIG_FRAMETIMEOUT_ENABLED (0x1UL) /*!< Packet timeout is enabled. */ + + +/* UARTE_ADDRESS: Set the address of the UARTE for RX when used in 9 bit data frame mode. */ + #define UARTE_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..7 : Set address */ + #define UARTE_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UARTE_ADDRESS_ADDRESS_Msk (0xFFUL << UARTE_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* UARTE_FRAMETIMEOUT: Set the number of UARTE bits to count before triggering packet timeout. */ + #define UARTE_FRAMETIMEOUT_ResetValue (0x00000010UL) /*!< Reset value of FRAMETIMEOUT register. */ + +/* COUNTERTOP @Bits 0..9 : Number of UARTE bits before timeout. */ + #define UARTE_FRAMETIMEOUT_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ + #define UARTE_FRAMETIMEOUT_COUNTERTOP_Msk (0x3FFUL << UARTE_FRAMETIMEOUT_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ===================================================== Struct UICR_MEM ===================================================== */ +/** + * @brief MEM [UICR_MEM] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Memory configuration of the memory region */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Size of the memory region */ +} NRF_UICR_MEM_Type; /*!< Size = 8 (0x008) */ + #define UICR_MEM_MaxCount (16UL) /*!< Size of MEM[16] array. */ + #define UICR_MEM_MaxIndex (15UL) /*!< Max index of MEM[16] array. */ + #define UICR_MEM_MinIndex (0UL) /*!< Min index of MEM[16] array. */ + +/* UICR_MEM_CONFIG: Memory configuration of the memory region */ + #define UICR_MEM_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* READ @Bit 0 : (unspecified) */ + #define UICR_MEM_CONFIG_READ_Pos (0UL) /*!< Position of READ field. */ + #define UICR_MEM_CONFIG_READ_Msk (0x1UL << UICR_MEM_CONFIG_READ_Pos) /*!< Bit mask of READ field. */ + #define UICR_MEM_CONFIG_READ_Min (0x0UL) /*!< Min enumerator value of READ field. */ + #define UICR_MEM_CONFIG_READ_Max (0x1UL) /*!< Max enumerator value of READ field. */ + #define UICR_MEM_CONFIG_READ_NotAllowed (0x1UL) /*!< Read access to MEM[n] is not allowed */ + #define UICR_MEM_CONFIG_READ_Allowed (0x0UL) /*!< Read access to MEM[n] is allowed */ + +/* WRITE @Bit 1 : (unspecified) */ + #define UICR_MEM_CONFIG_WRITE_Pos (1UL) /*!< Position of WRITE field. */ + #define UICR_MEM_CONFIG_WRITE_Msk (0x1UL << UICR_MEM_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field. */ + #define UICR_MEM_CONFIG_WRITE_Min (0x0UL) /*!< Min enumerator value of WRITE field. */ + #define UICR_MEM_CONFIG_WRITE_Max (0x1UL) /*!< Max enumerator value of WRITE field. */ + #define UICR_MEM_CONFIG_WRITE_NotAllowed (0x1UL) /*!< Write access to MEM[n] is not allowed */ + #define UICR_MEM_CONFIG_WRITE_Allowed (0x0UL) /*!< Write access to MEM[n] is allowed */ + +/* EXECUTE @Bit 2 : (unspecified) */ + #define UICR_MEM_CONFIG_EXECUTE_Pos (2UL) /*!< Position of EXECUTE field. */ + #define UICR_MEM_CONFIG_EXECUTE_Msk (0x1UL << UICR_MEM_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ + #define UICR_MEM_CONFIG_EXECUTE_Min (0x0UL) /*!< Min enumerator value of EXECUTE field. */ + #define UICR_MEM_CONFIG_EXECUTE_Max (0x1UL) /*!< Max enumerator value of EXECUTE field. */ + #define UICR_MEM_CONFIG_EXECUTE_NotAllowed (0x1UL) /*!< SW execution from MEM[n] is not allowed */ + #define UICR_MEM_CONFIG_EXECUTE_Allowed (0x0UL) /*!< SW execution from MEM[n] is allowed */ + +/* SECURE @Bit 3 : (unspecified) */ + #define UICR_MEM_CONFIG_SECURE_Pos (3UL) /*!< Position of SECURE field. */ + #define UICR_MEM_CONFIG_SECURE_Msk (0x1UL << UICR_MEM_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define UICR_MEM_CONFIG_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define UICR_MEM_CONFIG_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define UICR_MEM_CONFIG_SECURE_Secure (0x1UL) /*!< Non-secure access to MEM[n] is not allowed */ + #define UICR_MEM_CONFIG_SECURE_NonSecure (0x0UL) /*!< Non-secure access to MEM[n] is allowed */ + +/* NSC @Bit 4 : (unspecified) */ + #define UICR_MEM_CONFIG_NSC_Pos (4UL) /*!< Position of NSC field. */ + #define UICR_MEM_CONFIG_NSC_Msk (0x1UL << UICR_MEM_CONFIG_NSC_Pos) /*!< Bit mask of NSC field. */ + #define UICR_MEM_CONFIG_NSC_Min (0x0UL) /*!< Min enumerator value of NSC field. */ + #define UICR_MEM_CONFIG_NSC_Max (0x1UL) /*!< Max enumerator value of NSC field. */ + #define UICR_MEM_CONFIG_NSC_Disabled (0x1UL) /*!< Memory region is not non-secure callable */ + #define UICR_MEM_CONFIG_NSC_Enabled (0x0UL) /*!< Memory region is non-secure callable */ + +/* OWNERID @Bits 8..11 : Memory owner identification */ + #define UICR_MEM_CONFIG_OWNERID_Pos (8UL) /*!< Position of OWNERID field. */ + #define UICR_MEM_CONFIG_OWNERID_Msk (0xFUL << UICR_MEM_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define UICR_MEM_CONFIG_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define UICR_MEM_CONFIG_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + +/* ADDRESS @Bits 12..31 : Memory region start address, bits [31:12] */ + #define UICR_MEM_CONFIG_ADDRESS_Pos (12UL) /*!< Position of ADDRESS field. */ + #define UICR_MEM_CONFIG_ADDRESS_Msk (0xFFFFFUL << UICR_MEM_CONFIG_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* UICR_MEM_SIZE: Size of the memory region */ + #define UICR_MEM_SIZE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SIZE register. */ + +/* SIZE @Bits 0..31 : Memory size in bytes */ + #define UICR_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ + #define UICR_MEM_SIZE_SIZE_Msk (0xFFFFFFFFUL << UICR_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + + +/* =================================================== Struct UICR_PERIPH ==================================================== */ +/** + * @brief PERIPH [UICR_PERIPH] (unspecified) + */ +typedef struct { + __IOM uint32_t CONFIG; /*!< (@ 0x00000000) Peripheral configuration */ +} NRF_UICR_PERIPH_Type; /*!< Size = 4 (0x004) */ + #define UICR_PERIPH_MaxCount (192UL) /*!< Size of PERIPH[192] array. */ + #define UICR_PERIPH_MaxIndex (191UL) /*!< Max index of PERIPH[192] array. */ + #define UICR_PERIPH_MinIndex (0UL) /*!< Min index of PERIPH[192] array. */ + +/* UICR_PERIPH_CONFIG: Peripheral configuration */ + #define UICR_PERIPH_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* SECURE @Bit 3 : Peripheral security mapping */ + #define UICR_PERIPH_CONFIG_SECURE_Pos (3UL) /*!< Position of SECURE field. */ + #define UICR_PERIPH_CONFIG_SECURE_Msk (0x1UL << UICR_PERIPH_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define UICR_PERIPH_CONFIG_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define UICR_PERIPH_CONFIG_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define UICR_PERIPH_CONFIG_SECURE_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */ + #define UICR_PERIPH_CONFIG_SECURE_NonSecure (0x0UL) /*!< Peripheral is mapped in non-secure peripheral address space. */ + +/* DMASEC @Bit 5 : Security attribution for the DMA transfer */ + #define UICR_PERIPH_CONFIG_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ + #define UICR_PERIPH_CONFIG_DMASEC_Msk (0x1UL << UICR_PERIPH_CONFIG_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ + #define UICR_PERIPH_CONFIG_DMASEC_Min (0x0UL) /*!< Min enumerator value of DMASEC field. */ + #define UICR_PERIPH_CONFIG_DMASEC_Max (0x1UL) /*!< Max enumerator value of DMASEC field. */ + #define UICR_PERIPH_CONFIG_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute + set*/ + #define UICR_PERIPH_CONFIG_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure + attribute set*/ + +/* PROCESSOR @Bits 8..11 : Processor ID of the processor that will receive the peripheral IRQ */ + #define UICR_PERIPH_CONFIG_PROCESSOR_Pos (8UL) /*!< Position of PROCESSOR field. */ + #define UICR_PERIPH_CONFIG_PROCESSOR_Msk (0xFUL << UICR_PERIPH_CONFIG_PROCESSOR_Pos) /*!< Bit mask of PROCESSOR field. */ + +/* ADDRESS @Bits 12..31 : Peripheral address, bits [31:12] */ + #define UICR_PERIPH_CONFIG_ADDRESS_Pos (12UL) /*!< Position of ADDRESS field. */ + #define UICR_PERIPH_CONFIG_ADDRESS_Msk (0xFFFFFUL << UICR_PERIPH_CONFIG_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + + +/* ================================================== Struct UICR_GPIOTE_CH ================================================== */ +/** + * @brief CH [UICR_GPIOTE_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the channels of GPIOTE[n] */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the channels of GPIOTE[n] */ +} NRF_UICR_GPIOTE_CH_Type; /*!< Size = 8 (0x008) */ + +/* UICR_GPIOTE_CH_OWN: Request ownership of the channels of GPIOTE[n] */ + #define UICR_GPIOTE_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_GPIOTE_CH_OWN_CH0_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_GPIOTE_CH_OWN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_GPIOTE_CH_OWN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_GPIOTE_CH_OWN_CH0_NotOwn (0x1UL) /*!< Do not own the channel 0 */ + #define UICR_GPIOTE_CH_OWN_CH0_Own (0x0UL) /*!< Own the channel 0 */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_GPIOTE_CH_OWN_CH1_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_GPIOTE_CH_OWN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_GPIOTE_CH_OWN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_GPIOTE_CH_OWN_CH1_NotOwn (0x1UL) /*!< Do not own the channel 1 */ + #define UICR_GPIOTE_CH_OWN_CH1_Own (0x0UL) /*!< Own the channel 1 */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_GPIOTE_CH_OWN_CH2_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_GPIOTE_CH_OWN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_GPIOTE_CH_OWN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_GPIOTE_CH_OWN_CH2_NotOwn (0x1UL) /*!< Do not own the channel 2 */ + #define UICR_GPIOTE_CH_OWN_CH2_Own (0x0UL) /*!< Own the channel 2 */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_GPIOTE_CH_OWN_CH3_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_GPIOTE_CH_OWN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_GPIOTE_CH_OWN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_GPIOTE_CH_OWN_CH3_NotOwn (0x1UL) /*!< Do not own the channel 3 */ + #define UICR_GPIOTE_CH_OWN_CH3_Own (0x0UL) /*!< Own the channel 3 */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_GPIOTE_CH_OWN_CH4_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_GPIOTE_CH_OWN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_GPIOTE_CH_OWN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_GPIOTE_CH_OWN_CH4_NotOwn (0x1UL) /*!< Do not own the channel 4 */ + #define UICR_GPIOTE_CH_OWN_CH4_Own (0x0UL) /*!< Own the channel 4 */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_GPIOTE_CH_OWN_CH5_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_GPIOTE_CH_OWN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_GPIOTE_CH_OWN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_GPIOTE_CH_OWN_CH5_NotOwn (0x1UL) /*!< Do not own the channel 5 */ + #define UICR_GPIOTE_CH_OWN_CH5_Own (0x0UL) /*!< Own the channel 5 */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_GPIOTE_CH_OWN_CH6_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_GPIOTE_CH_OWN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_GPIOTE_CH_OWN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_GPIOTE_CH_OWN_CH6_NotOwn (0x1UL) /*!< Do not own the channel 6 */ + #define UICR_GPIOTE_CH_OWN_CH6_Own (0x0UL) /*!< Own the channel 6 */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_GPIOTE_CH_OWN_CH7_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_GPIOTE_CH_OWN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_GPIOTE_CH_OWN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_GPIOTE_CH_OWN_CH7_NotOwn (0x1UL) /*!< Do not own the channel 7 */ + #define UICR_GPIOTE_CH_OWN_CH7_Own (0x0UL) /*!< Own the channel 7 */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_GPIOTE_CH_OWN_CH8_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_GPIOTE_CH_OWN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_GPIOTE_CH_OWN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_GPIOTE_CH_OWN_CH8_NotOwn (0x1UL) /*!< Do not own the channel 8 */ + #define UICR_GPIOTE_CH_OWN_CH8_Own (0x0UL) /*!< Own the channel 8 */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_GPIOTE_CH_OWN_CH9_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_GPIOTE_CH_OWN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_GPIOTE_CH_OWN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_GPIOTE_CH_OWN_CH9_NotOwn (0x1UL) /*!< Do not own the channel 9 */ + #define UICR_GPIOTE_CH_OWN_CH9_Own (0x0UL) /*!< Own the channel 9 */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_GPIOTE_CH_OWN_CH10_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_GPIOTE_CH_OWN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_GPIOTE_CH_OWN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_GPIOTE_CH_OWN_CH10_NotOwn (0x1UL) /*!< Do not own the channel 10 */ + #define UICR_GPIOTE_CH_OWN_CH10_Own (0x0UL) /*!< Own the channel 10 */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_GPIOTE_CH_OWN_CH11_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_GPIOTE_CH_OWN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_GPIOTE_CH_OWN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_GPIOTE_CH_OWN_CH11_NotOwn (0x1UL) /*!< Do not own the channel 11 */ + #define UICR_GPIOTE_CH_OWN_CH11_Own (0x0UL) /*!< Own the channel 11 */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_GPIOTE_CH_OWN_CH12_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_GPIOTE_CH_OWN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_GPIOTE_CH_OWN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_GPIOTE_CH_OWN_CH12_NotOwn (0x1UL) /*!< Do not own the channel 12 */ + #define UICR_GPIOTE_CH_OWN_CH12_Own (0x0UL) /*!< Own the channel 12 */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_GPIOTE_CH_OWN_CH13_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_GPIOTE_CH_OWN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_GPIOTE_CH_OWN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_GPIOTE_CH_OWN_CH13_NotOwn (0x1UL) /*!< Do not own the channel 13 */ + #define UICR_GPIOTE_CH_OWN_CH13_Own (0x0UL) /*!< Own the channel 13 */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_GPIOTE_CH_OWN_CH14_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_GPIOTE_CH_OWN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_GPIOTE_CH_OWN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_GPIOTE_CH_OWN_CH14_NotOwn (0x1UL) /*!< Do not own the channel 14 */ + #define UICR_GPIOTE_CH_OWN_CH14_Own (0x0UL) /*!< Own the channel 14 */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_GPIOTE_CH_OWN_CH15_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_GPIOTE_CH_OWN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_GPIOTE_CH_OWN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_GPIOTE_CH_OWN_CH15_NotOwn (0x1UL) /*!< Do not own the channel 15 */ + #define UICR_GPIOTE_CH_OWN_CH15_Own (0x0UL) /*!< Own the channel 15 */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_GPIOTE_CH_OWN_CH16_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_GPIOTE_CH_OWN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_GPIOTE_CH_OWN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_GPIOTE_CH_OWN_CH16_NotOwn (0x1UL) /*!< Do not own the channel 16 */ + #define UICR_GPIOTE_CH_OWN_CH16_Own (0x0UL) /*!< Own the channel 16 */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_GPIOTE_CH_OWN_CH17_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_GPIOTE_CH_OWN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_GPIOTE_CH_OWN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_GPIOTE_CH_OWN_CH17_NotOwn (0x1UL) /*!< Do not own the channel 17 */ + #define UICR_GPIOTE_CH_OWN_CH17_Own (0x0UL) /*!< Own the channel 17 */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_GPIOTE_CH_OWN_CH18_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_GPIOTE_CH_OWN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_GPIOTE_CH_OWN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_GPIOTE_CH_OWN_CH18_NotOwn (0x1UL) /*!< Do not own the channel 18 */ + #define UICR_GPIOTE_CH_OWN_CH18_Own (0x0UL) /*!< Own the channel 18 */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_GPIOTE_CH_OWN_CH19_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_GPIOTE_CH_OWN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_GPIOTE_CH_OWN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_GPIOTE_CH_OWN_CH19_NotOwn (0x1UL) /*!< Do not own the channel 19 */ + #define UICR_GPIOTE_CH_OWN_CH19_Own (0x0UL) /*!< Own the channel 19 */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_GPIOTE_CH_OWN_CH20_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_GPIOTE_CH_OWN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_GPIOTE_CH_OWN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_GPIOTE_CH_OWN_CH20_NotOwn (0x1UL) /*!< Do not own the channel 20 */ + #define UICR_GPIOTE_CH_OWN_CH20_Own (0x0UL) /*!< Own the channel 20 */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_GPIOTE_CH_OWN_CH21_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_GPIOTE_CH_OWN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_GPIOTE_CH_OWN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_GPIOTE_CH_OWN_CH21_NotOwn (0x1UL) /*!< Do not own the channel 21 */ + #define UICR_GPIOTE_CH_OWN_CH21_Own (0x0UL) /*!< Own the channel 21 */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_GPIOTE_CH_OWN_CH22_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_GPIOTE_CH_OWN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_GPIOTE_CH_OWN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_GPIOTE_CH_OWN_CH22_NotOwn (0x1UL) /*!< Do not own the channel 22 */ + #define UICR_GPIOTE_CH_OWN_CH22_Own (0x0UL) /*!< Own the channel 22 */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_GPIOTE_CH_OWN_CH23_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_GPIOTE_CH_OWN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_GPIOTE_CH_OWN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_GPIOTE_CH_OWN_CH23_NotOwn (0x1UL) /*!< Do not own the channel 23 */ + #define UICR_GPIOTE_CH_OWN_CH23_Own (0x0UL) /*!< Own the channel 23 */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_GPIOTE_CH_OWN_CH24_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_GPIOTE_CH_OWN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_GPIOTE_CH_OWN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_GPIOTE_CH_OWN_CH24_NotOwn (0x1UL) /*!< Do not own the channel 24 */ + #define UICR_GPIOTE_CH_OWN_CH24_Own (0x0UL) /*!< Own the channel 24 */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_GPIOTE_CH_OWN_CH25_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_GPIOTE_CH_OWN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_GPIOTE_CH_OWN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_GPIOTE_CH_OWN_CH25_NotOwn (0x1UL) /*!< Do not own the channel 25 */ + #define UICR_GPIOTE_CH_OWN_CH25_Own (0x0UL) /*!< Own the channel 25 */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_GPIOTE_CH_OWN_CH26_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_GPIOTE_CH_OWN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_GPIOTE_CH_OWN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_GPIOTE_CH_OWN_CH26_NotOwn (0x1UL) /*!< Do not own the channel 26 */ + #define UICR_GPIOTE_CH_OWN_CH26_Own (0x0UL) /*!< Own the channel 26 */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_GPIOTE_CH_OWN_CH27_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_GPIOTE_CH_OWN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_GPIOTE_CH_OWN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_GPIOTE_CH_OWN_CH27_NotOwn (0x1UL) /*!< Do not own the channel 27 */ + #define UICR_GPIOTE_CH_OWN_CH27_Own (0x0UL) /*!< Own the channel 27 */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_GPIOTE_CH_OWN_CH28_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_GPIOTE_CH_OWN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_GPIOTE_CH_OWN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_GPIOTE_CH_OWN_CH28_NotOwn (0x1UL) /*!< Do not own the channel 28 */ + #define UICR_GPIOTE_CH_OWN_CH28_Own (0x0UL) /*!< Own the channel 28 */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_GPIOTE_CH_OWN_CH29_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_GPIOTE_CH_OWN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_GPIOTE_CH_OWN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_GPIOTE_CH_OWN_CH29_NotOwn (0x1UL) /*!< Do not own the channel 29 */ + #define UICR_GPIOTE_CH_OWN_CH29_Own (0x0UL) /*!< Own the channel 29 */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_GPIOTE_CH_OWN_CH30_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_GPIOTE_CH_OWN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_GPIOTE_CH_OWN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_GPIOTE_CH_OWN_CH30_NotOwn (0x1UL) /*!< Do not own the channel 30 */ + #define UICR_GPIOTE_CH_OWN_CH30_Own (0x0UL) /*!< Own the channel 30 */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_GPIOTE_CH_OWN_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_GPIOTE_CH_OWN_CH31_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_GPIOTE_CH_OWN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_GPIOTE_CH_OWN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_GPIOTE_CH_OWN_CH31_NotOwn (0x1UL) /*!< Do not own the channel 31 */ + #define UICR_GPIOTE_CH_OWN_CH31_Own (0x0UL) /*!< Own the channel 31 */ + + +/* UICR_GPIOTE_CH_SECURE: Request permission for the channels of GPIOTE[n] */ + #define UICR_GPIOTE_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_GPIOTE_CH_SECURE_CH0_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_GPIOTE_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_GPIOTE_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_GPIOTE_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_GPIOTE_CH_SECURE_CH1_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_GPIOTE_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_GPIOTE_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_GPIOTE_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_GPIOTE_CH_SECURE_CH2_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_GPIOTE_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_GPIOTE_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_GPIOTE_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_GPIOTE_CH_SECURE_CH3_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_GPIOTE_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_GPIOTE_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_GPIOTE_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_GPIOTE_CH_SECURE_CH4_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_GPIOTE_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_GPIOTE_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_GPIOTE_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_GPIOTE_CH_SECURE_CH5_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_GPIOTE_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_GPIOTE_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_GPIOTE_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_GPIOTE_CH_SECURE_CH6_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_GPIOTE_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_GPIOTE_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_GPIOTE_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_GPIOTE_CH_SECURE_CH7_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_GPIOTE_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_GPIOTE_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_GPIOTE_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_GPIOTE_CH_SECURE_CH8_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_GPIOTE_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_GPIOTE_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_GPIOTE_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_GPIOTE_CH_SECURE_CH9_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_GPIOTE_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_GPIOTE_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_GPIOTE_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_GPIOTE_CH_SECURE_CH10_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_GPIOTE_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_GPIOTE_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_GPIOTE_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_GPIOTE_CH_SECURE_CH11_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_GPIOTE_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_GPIOTE_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_GPIOTE_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_GPIOTE_CH_SECURE_CH12_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_GPIOTE_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_GPIOTE_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_GPIOTE_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_GPIOTE_CH_SECURE_CH13_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_GPIOTE_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_GPIOTE_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_GPIOTE_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_GPIOTE_CH_SECURE_CH14_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_GPIOTE_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_GPIOTE_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_GPIOTE_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_GPIOTE_CH_SECURE_CH15_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_GPIOTE_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_GPIOTE_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_GPIOTE_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_GPIOTE_CH_SECURE_CH16_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_GPIOTE_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_GPIOTE_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_GPIOTE_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_GPIOTE_CH_SECURE_CH17_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_GPIOTE_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_GPIOTE_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_GPIOTE_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_GPIOTE_CH_SECURE_CH18_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_GPIOTE_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_GPIOTE_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_GPIOTE_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_GPIOTE_CH_SECURE_CH19_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_GPIOTE_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_GPIOTE_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_GPIOTE_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_GPIOTE_CH_SECURE_CH20_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_GPIOTE_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_GPIOTE_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_GPIOTE_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_GPIOTE_CH_SECURE_CH21_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_GPIOTE_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_GPIOTE_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_GPIOTE_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_GPIOTE_CH_SECURE_CH22_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_GPIOTE_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_GPIOTE_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_GPIOTE_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_GPIOTE_CH_SECURE_CH23_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_GPIOTE_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_GPIOTE_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_GPIOTE_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_GPIOTE_CH_SECURE_CH24_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_GPIOTE_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_GPIOTE_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_GPIOTE_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_GPIOTE_CH_SECURE_CH25_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_GPIOTE_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_GPIOTE_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_GPIOTE_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_GPIOTE_CH_SECURE_CH26_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_GPIOTE_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_GPIOTE_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_GPIOTE_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_GPIOTE_CH_SECURE_CH27_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_GPIOTE_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_GPIOTE_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_GPIOTE_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_GPIOTE_CH_SECURE_CH28_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_GPIOTE_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_GPIOTE_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_GPIOTE_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_GPIOTE_CH_SECURE_CH29_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_GPIOTE_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_GPIOTE_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_GPIOTE_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_GPIOTE_CH_SECURE_CH30_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_GPIOTE_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_GPIOTE_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_GPIOTE_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_GPIOTE_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_GPIOTE_CH_SECURE_CH31_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_GPIOTE_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_GPIOTE_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_GPIOTE_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure */ + #define UICR_GPIOTE_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure */ + + + +/* =================================================== Struct UICR_GPIOTE ==================================================== */ +/** + * @brief GPIOTE [UICR_GPIOTE] (unspecified) + */ +typedef struct { + __IOM uint32_t INSTANCE; /*!< (@ 0x00000000) Address of the GPIOTE instance associated with + GPIOTE[n]*/ + __IOM NRF_UICR_GPIOTE_CH_Type CH; /*!< (@ 0x00000004) (unspecified) */ +} NRF_UICR_GPIOTE_Type; /*!< Size = 12 (0x00C) */ + #define UICR_GPIOTE_MaxCount (4UL) /*!< Size of GPIOTE[4] array. */ + #define UICR_GPIOTE_MaxIndex (3UL) /*!< Max index of GPIOTE[4] array. */ + #define UICR_GPIOTE_MinIndex (0UL) /*!< Min index of GPIOTE[4] array. */ + +/* UICR_GPIOTE_INSTANCE: Address of the GPIOTE instance associated with GPIOTE[n] */ + #define UICR_GPIOTE_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register. */ + +/* ADDRESS @Bits 0..31 : Instance address */ + #define UICR_GPIOTE_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICR_GPIOTE_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_GPIOTE_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + + +/* ================================================ Struct UICR_IPCT_LOCAL_CH ================================================ */ +/** + * @brief CH [UICR_IPCT_LOCAL_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t SECURE; /*!< (@ 0x00000000) Request permission for the channels of IPCT in the + local domain*/ +} NRF_UICR_IPCT_LOCAL_CH_Type; /*!< Size = 4 (0x004) */ + +/* UICR_IPCT_LOCAL_CH_SECURE: Request permission for the channels of IPCT in the local domain */ + #define UICR_IPCT_LOCAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure */ + #define UICR_IPCT_LOCAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure */ + + + +/* ============================================ Struct UICR_IPCT_LOCAL_INTERRUPT ============================================= */ +/** + * @brief INTERRUPT [UICR_IPCT_LOCAL_INTERRUPT] (unspecified) + */ +typedef struct { + __IOM uint32_t SECURE; /*!< (@ 0x00000000) Request permission for the interrupts of IPCT in the + local domain*/ +} NRF_UICR_IPCT_LOCAL_INTERRUPT_Type; /*!< Size = 4 (0x004) */ + +/* UICR_IPCT_LOCAL_INTERRUPT_SECURE: Request permission for the interrupts of IPCT in the local domain */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* INT0 @Bit 0 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Pos (0UL) /*!< Position of INT0 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Pos) /*!< Bit mask of INT0 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Secure (0x1UL) /*!< The interrupt 0 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_NonSecure (0x0UL) /*!< The interrupt 0 is non-secure */ + +/* INT1 @Bit 1 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Pos (1UL) /*!< Position of INT1 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Pos) /*!< Bit mask of INT1 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Secure (0x1UL) /*!< The interrupt 1 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_NonSecure (0x0UL) /*!< The interrupt 1 is non-secure */ + +/* INT2 @Bit 2 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Pos (2UL) /*!< Position of INT2 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Pos) /*!< Bit mask of INT2 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Secure (0x1UL) /*!< The interrupt 2 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_NonSecure (0x0UL) /*!< The interrupt 2 is non-secure */ + +/* INT3 @Bit 3 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Pos (3UL) /*!< Position of INT3 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Pos) /*!< Bit mask of INT3 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Secure (0x1UL) /*!< The interrupt 3 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_NonSecure (0x0UL) /*!< The interrupt 3 is non-secure */ + +/* INT4 @Bit 4 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Pos (4UL) /*!< Position of INT4 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Pos) /*!< Bit mask of INT4 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Secure (0x1UL) /*!< The interrupt 4 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_NonSecure (0x0UL) /*!< The interrupt 4 is non-secure */ + +/* INT5 @Bit 5 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Pos (5UL) /*!< Position of INT5 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Pos) /*!< Bit mask of INT5 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Secure (0x1UL) /*!< The interrupt 5 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_NonSecure (0x0UL) /*!< The interrupt 5 is non-secure */ + +/* INT6 @Bit 6 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Pos (6UL) /*!< Position of INT6 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Pos) /*!< Bit mask of INT6 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Secure (0x1UL) /*!< The interrupt 6 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_NonSecure (0x0UL) /*!< The interrupt 6 is non-secure */ + +/* INT7 @Bit 7 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Pos (7UL) /*!< Position of INT7 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Pos) /*!< Bit mask of INT7 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Secure (0x1UL) /*!< The interrupt 7 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_NonSecure (0x0UL) /*!< The interrupt 7 is non-secure */ + +/* INT8 @Bit 8 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Pos (8UL) /*!< Position of INT8 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Pos) /*!< Bit mask of INT8 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Secure (0x1UL) /*!< The interrupt 8 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_NonSecure (0x0UL) /*!< The interrupt 8 is non-secure */ + +/* INT9 @Bit 9 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Pos (9UL) /*!< Position of INT9 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Pos) /*!< Bit mask of INT9 + field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Secure (0x1UL) /*!< The interrupt 9 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_NonSecure (0x0UL) /*!< The interrupt 9 is non-secure */ + +/* INT10 @Bit 10 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Pos (10UL) /*!< Position of INT10 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Pos) /*!< Bit mask of + INT10 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Secure (0x1UL) /*!< The interrupt 10 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_NonSecure (0x0UL) /*!< The interrupt 10 is non-secure */ + +/* INT11 @Bit 11 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Pos (11UL) /*!< Position of INT11 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Pos) /*!< Bit mask of + INT11 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Secure (0x1UL) /*!< The interrupt 11 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_NonSecure (0x0UL) /*!< The interrupt 11 is non-secure */ + +/* INT12 @Bit 12 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Pos (12UL) /*!< Position of INT12 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Pos) /*!< Bit mask of + INT12 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Secure (0x1UL) /*!< The interrupt 12 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_NonSecure (0x0UL) /*!< The interrupt 12 is non-secure */ + +/* INT13 @Bit 13 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Pos (13UL) /*!< Position of INT13 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Pos) /*!< Bit mask of + INT13 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Secure (0x1UL) /*!< The interrupt 13 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_NonSecure (0x0UL) /*!< The interrupt 13 is non-secure */ + +/* INT14 @Bit 14 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Pos (14UL) /*!< Position of INT14 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Pos) /*!< Bit mask of + INT14 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Secure (0x1UL) /*!< The interrupt 14 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_NonSecure (0x0UL) /*!< The interrupt 14 is non-secure */ + +/* INT15 @Bit 15 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Pos (15UL) /*!< Position of INT15 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Pos) /*!< Bit mask of + INT15 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Secure (0x1UL) /*!< The interrupt 15 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_NonSecure (0x0UL) /*!< The interrupt 15 is non-secure */ + +/* INT16 @Bit 16 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Pos (16UL) /*!< Position of INT16 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Pos) /*!< Bit mask of + INT16 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Secure (0x1UL) /*!< The interrupt 16 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_NonSecure (0x0UL) /*!< The interrupt 16 is non-secure */ + +/* INT17 @Bit 17 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Pos (17UL) /*!< Position of INT17 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Pos) /*!< Bit mask of + INT17 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Secure (0x1UL) /*!< The interrupt 17 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_NonSecure (0x0UL) /*!< The interrupt 17 is non-secure */ + +/* INT18 @Bit 18 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Pos (18UL) /*!< Position of INT18 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Pos) /*!< Bit mask of + INT18 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Secure (0x1UL) /*!< The interrupt 18 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_NonSecure (0x0UL) /*!< The interrupt 18 is non-secure */ + +/* INT19 @Bit 19 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Pos (19UL) /*!< Position of INT19 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Pos) /*!< Bit mask of + INT19 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Secure (0x1UL) /*!< The interrupt 19 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_NonSecure (0x0UL) /*!< The interrupt 19 is non-secure */ + +/* INT20 @Bit 20 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Pos (20UL) /*!< Position of INT20 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Pos) /*!< Bit mask of + INT20 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Secure (0x1UL) /*!< The interrupt 20 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_NonSecure (0x0UL) /*!< The interrupt 20 is non-secure */ + +/* INT21 @Bit 21 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Pos (21UL) /*!< Position of INT21 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Pos) /*!< Bit mask of + INT21 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Secure (0x1UL) /*!< The interrupt 21 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_NonSecure (0x0UL) /*!< The interrupt 21 is non-secure */ + +/* INT22 @Bit 22 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Pos (22UL) /*!< Position of INT22 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Pos) /*!< Bit mask of + INT22 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Secure (0x1UL) /*!< The interrupt 22 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_NonSecure (0x0UL) /*!< The interrupt 22 is non-secure */ + +/* INT23 @Bit 23 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Pos (23UL) /*!< Position of INT23 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Pos) /*!< Bit mask of + INT23 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Secure (0x1UL) /*!< The interrupt 23 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_NonSecure (0x0UL) /*!< The interrupt 23 is non-secure */ + +/* INT24 @Bit 24 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Pos (24UL) /*!< Position of INT24 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Pos) /*!< Bit mask of + INT24 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Secure (0x1UL) /*!< The interrupt 24 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_NonSecure (0x0UL) /*!< The interrupt 24 is non-secure */ + +/* INT25 @Bit 25 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Pos (25UL) /*!< Position of INT25 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Pos) /*!< Bit mask of + INT25 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Secure (0x1UL) /*!< The interrupt 25 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_NonSecure (0x0UL) /*!< The interrupt 25 is non-secure */ + +/* INT26 @Bit 26 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Pos (26UL) /*!< Position of INT26 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Pos) /*!< Bit mask of + INT26 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Secure (0x1UL) /*!< The interrupt 26 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_NonSecure (0x0UL) /*!< The interrupt 26 is non-secure */ + +/* INT27 @Bit 27 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Pos (27UL) /*!< Position of INT27 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Pos) /*!< Bit mask of + INT27 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Secure (0x1UL) /*!< The interrupt 27 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_NonSecure (0x0UL) /*!< The interrupt 27 is non-secure */ + +/* INT28 @Bit 28 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Pos (28UL) /*!< Position of INT28 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Pos) /*!< Bit mask of + INT28 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Secure (0x1UL) /*!< The interrupt 28 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_NonSecure (0x0UL) /*!< The interrupt 28 is non-secure */ + +/* INT29 @Bit 29 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Pos (29UL) /*!< Position of INT29 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Pos) /*!< Bit mask of + INT29 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Secure (0x1UL) /*!< The interrupt 29 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_NonSecure (0x0UL) /*!< The interrupt 29 is non-secure */ + +/* INT30 @Bit 30 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Pos (30UL) /*!< Position of INT30 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Pos) /*!< Bit mask of + INT30 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Secure (0x1UL) /*!< The interrupt 30 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_NonSecure (0x0UL) /*!< The interrupt 30 is non-secure */ + +/* INT31 @Bit 31 : Interrupt number */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Pos (31UL) /*!< Position of INT31 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Pos) /*!< Bit mask of + INT31 field.*/ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field. */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Secure (0x1UL) /*!< The interrupt 31 is secure */ + #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_NonSecure (0x0UL) /*!< The interrupt 31 is non-secure */ + + + +/* ================================================= Struct UICR_IPCT_LOCAL ================================================== */ +/** + * @brief LOCAL [UICR_IPCT_LOCAL] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_IPCT_LOCAL_CH_Type CH; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UICR_IPCT_LOCAL_INTERRUPT_Type INTERRUPT; /*!< (@ 0x00000004) (unspecified) */ +} NRF_UICR_IPCT_LOCAL_Type; /*!< Size = 8 (0x008) */ + + +/* =============================================== Struct UICR_IPCT_GLOBAL_CH ================================================ */ +/** + * @brief CH [UICR_IPCT_GLOBAL_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the channels of IPCT[n] in Global + domain*/ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the channels of IPCT[n] in + Global domain*/ +} NRF_UICR_IPCT_GLOBAL_CH_Type; /*!< Size = 8 (0x008) */ + +/* UICR_IPCT_GLOBAL_CH_OWN: Request ownership of the channels of IPCT[n] in Global domain */ + #define UICR_IPCT_GLOBAL_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_NotOwn (0x1UL) /*!< Do not own the channel 0 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Own (0x0UL) /*!< Own the channel 0 */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_NotOwn (0x1UL) /*!< Do not own the channel 1 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Own (0x0UL) /*!< Own the channel 1 */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_NotOwn (0x1UL) /*!< Do not own the channel 2 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Own (0x0UL) /*!< Own the channel 2 */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_NotOwn (0x1UL) /*!< Do not own the channel 3 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Own (0x0UL) /*!< Own the channel 3 */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_NotOwn (0x1UL) /*!< Do not own the channel 4 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Own (0x0UL) /*!< Own the channel 4 */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_NotOwn (0x1UL) /*!< Do not own the channel 5 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Own (0x0UL) /*!< Own the channel 5 */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_NotOwn (0x1UL) /*!< Do not own the channel 6 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Own (0x0UL) /*!< Own the channel 6 */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_NotOwn (0x1UL) /*!< Do not own the channel 7 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Own (0x0UL) /*!< Own the channel 7 */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_NotOwn (0x1UL) /*!< Do not own the channel 8 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Own (0x0UL) /*!< Own the channel 8 */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_NotOwn (0x1UL) /*!< Do not own the channel 9 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Own (0x0UL) /*!< Own the channel 9 */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_NotOwn (0x1UL) /*!< Do not own the channel 10 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Own (0x0UL) /*!< Own the channel 10 */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_NotOwn (0x1UL) /*!< Do not own the channel 11 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Own (0x0UL) /*!< Own the channel 11 */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_NotOwn (0x1UL) /*!< Do not own the channel 12 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Own (0x0UL) /*!< Own the channel 12 */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_NotOwn (0x1UL) /*!< Do not own the channel 13 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Own (0x0UL) /*!< Own the channel 13 */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_NotOwn (0x1UL) /*!< Do not own the channel 14 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Own (0x0UL) /*!< Own the channel 14 */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_NotOwn (0x1UL) /*!< Do not own the channel 15 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Own (0x0UL) /*!< Own the channel 15 */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_NotOwn (0x1UL) /*!< Do not own the channel 16 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Own (0x0UL) /*!< Own the channel 16 */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_NotOwn (0x1UL) /*!< Do not own the channel 17 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Own (0x0UL) /*!< Own the channel 17 */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_NotOwn (0x1UL) /*!< Do not own the channel 18 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Own (0x0UL) /*!< Own the channel 18 */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_NotOwn (0x1UL) /*!< Do not own the channel 19 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Own (0x0UL) /*!< Own the channel 19 */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_NotOwn (0x1UL) /*!< Do not own the channel 20 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Own (0x0UL) /*!< Own the channel 20 */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_NotOwn (0x1UL) /*!< Do not own the channel 21 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Own (0x0UL) /*!< Own the channel 21 */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_NotOwn (0x1UL) /*!< Do not own the channel 22 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Own (0x0UL) /*!< Own the channel 22 */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_NotOwn (0x1UL) /*!< Do not own the channel 23 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Own (0x0UL) /*!< Own the channel 23 */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_NotOwn (0x1UL) /*!< Do not own the channel 24 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Own (0x0UL) /*!< Own the channel 24 */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_NotOwn (0x1UL) /*!< Do not own the channel 25 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Own (0x0UL) /*!< Own the channel 25 */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_NotOwn (0x1UL) /*!< Do not own the channel 26 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Own (0x0UL) /*!< Own the channel 26 */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_NotOwn (0x1UL) /*!< Do not own the channel 27 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Own (0x0UL) /*!< Own the channel 27 */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_NotOwn (0x1UL) /*!< Do not own the channel 28 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Own (0x0UL) /*!< Own the channel 28 */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_NotOwn (0x1UL) /*!< Do not own the channel 29 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Own (0x0UL) /*!< Own the channel 29 */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_NotOwn (0x1UL) /*!< Do not own the channel 30 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Own (0x0UL) /*!< Own the channel 30 */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_NotOwn (0x1UL) /*!< Do not own the channel 31 */ + #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Own (0x0UL) /*!< Own the channel 31 */ + + +/* UICR_IPCT_GLOBAL_CH_SECURE: Request permission for the channels of IPCT[n] in Global domain */ + #define UICR_IPCT_GLOBAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure */ + #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure */ + + + +/* ============================================ Struct UICR_IPCT_GLOBAL_INTERRUPT ============================================ */ +/** + * @brief INTERRUPT [UICR_IPCT_GLOBAL_INTERRUPT] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the interrupts of IPCT[n] in + Global domain*/ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the interrupts of IPCT[n] in + Global domain*/ +} NRF_UICR_IPCT_GLOBAL_INTERRUPT_Type; /*!< Size = 8 (0x008) */ + +/* UICR_IPCT_GLOBAL_INTERRUPT_OWN: Request ownership of the interrupts of IPCT[n] in Global domain */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* INT0 @Bit 0 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Pos (0UL) /*!< Position of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Pos) /*!< Bit mask of INT0 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_NotOwn (0x1UL) /*!< Do not own the interrupt 0 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Own (0x0UL) /*!< Own the interrupt 0 */ + +/* INT1 @Bit 1 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Pos (1UL) /*!< Position of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Pos) /*!< Bit mask of INT1 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_NotOwn (0x1UL) /*!< Do not own the interrupt 1 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Own (0x0UL) /*!< Own the interrupt 1 */ + +/* INT2 @Bit 2 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Pos (2UL) /*!< Position of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Pos) /*!< Bit mask of INT2 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_NotOwn (0x1UL) /*!< Do not own the interrupt 2 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Own (0x0UL) /*!< Own the interrupt 2 */ + +/* INT3 @Bit 3 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Pos (3UL) /*!< Position of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Pos) /*!< Bit mask of INT3 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_NotOwn (0x1UL) /*!< Do not own the interrupt 3 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Own (0x0UL) /*!< Own the interrupt 3 */ + +/* INT4 @Bit 4 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Pos (4UL) /*!< Position of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Pos) /*!< Bit mask of INT4 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_NotOwn (0x1UL) /*!< Do not own the interrupt 4 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Own (0x0UL) /*!< Own the interrupt 4 */ + +/* INT5 @Bit 5 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Pos (5UL) /*!< Position of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Pos) /*!< Bit mask of INT5 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_NotOwn (0x1UL) /*!< Do not own the interrupt 5 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Own (0x0UL) /*!< Own the interrupt 5 */ + +/* INT6 @Bit 6 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Pos (6UL) /*!< Position of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Pos) /*!< Bit mask of INT6 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_NotOwn (0x1UL) /*!< Do not own the interrupt 6 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Own (0x0UL) /*!< Own the interrupt 6 */ + +/* INT7 @Bit 7 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Pos (7UL) /*!< Position of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Pos) /*!< Bit mask of INT7 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_NotOwn (0x1UL) /*!< Do not own the interrupt 7 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Own (0x0UL) /*!< Own the interrupt 7 */ + +/* INT8 @Bit 8 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Pos (8UL) /*!< Position of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Pos) /*!< Bit mask of INT8 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_NotOwn (0x1UL) /*!< Do not own the interrupt 8 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Own (0x0UL) /*!< Own the interrupt 8 */ + +/* INT9 @Bit 9 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Pos (9UL) /*!< Position of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Pos) /*!< Bit mask of INT9 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_NotOwn (0x1UL) /*!< Do not own the interrupt 9 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Own (0x0UL) /*!< Own the interrupt 9 */ + +/* INT10 @Bit 10 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Pos (10UL) /*!< Position of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Pos) /*!< Bit mask of INT10 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_NotOwn (0x1UL) /*!< Do not own the interrupt 10 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Own (0x0UL) /*!< Own the interrupt 10 */ + +/* INT11 @Bit 11 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Pos (11UL) /*!< Position of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Pos) /*!< Bit mask of INT11 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_NotOwn (0x1UL) /*!< Do not own the interrupt 11 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Own (0x0UL) /*!< Own the interrupt 11 */ + +/* INT12 @Bit 12 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Pos (12UL) /*!< Position of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Pos) /*!< Bit mask of INT12 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_NotOwn (0x1UL) /*!< Do not own the interrupt 12 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Own (0x0UL) /*!< Own the interrupt 12 */ + +/* INT13 @Bit 13 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Pos (13UL) /*!< Position of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Pos) /*!< Bit mask of INT13 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_NotOwn (0x1UL) /*!< Do not own the interrupt 13 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Own (0x0UL) /*!< Own the interrupt 13 */ + +/* INT14 @Bit 14 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Pos (14UL) /*!< Position of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Pos) /*!< Bit mask of INT14 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_NotOwn (0x1UL) /*!< Do not own the interrupt 14 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Own (0x0UL) /*!< Own the interrupt 14 */ + +/* INT15 @Bit 15 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Pos (15UL) /*!< Position of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Pos) /*!< Bit mask of INT15 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_NotOwn (0x1UL) /*!< Do not own the interrupt 15 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Own (0x0UL) /*!< Own the interrupt 15 */ + +/* INT16 @Bit 16 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Pos (16UL) /*!< Position of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Pos) /*!< Bit mask of INT16 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_NotOwn (0x1UL) /*!< Do not own the interrupt 16 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Own (0x0UL) /*!< Own the interrupt 16 */ + +/* INT17 @Bit 17 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Pos (17UL) /*!< Position of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Pos) /*!< Bit mask of INT17 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_NotOwn (0x1UL) /*!< Do not own the interrupt 17 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Own (0x0UL) /*!< Own the interrupt 17 */ + +/* INT18 @Bit 18 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Pos (18UL) /*!< Position of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Pos) /*!< Bit mask of INT18 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_NotOwn (0x1UL) /*!< Do not own the interrupt 18 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Own (0x0UL) /*!< Own the interrupt 18 */ + +/* INT19 @Bit 19 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Pos (19UL) /*!< Position of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Pos) /*!< Bit mask of INT19 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_NotOwn (0x1UL) /*!< Do not own the interrupt 19 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Own (0x0UL) /*!< Own the interrupt 19 */ + +/* INT20 @Bit 20 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Pos (20UL) /*!< Position of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Pos) /*!< Bit mask of INT20 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_NotOwn (0x1UL) /*!< Do not own the interrupt 20 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Own (0x0UL) /*!< Own the interrupt 20 */ + +/* INT21 @Bit 21 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Pos (21UL) /*!< Position of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Pos) /*!< Bit mask of INT21 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_NotOwn (0x1UL) /*!< Do not own the interrupt 21 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Own (0x0UL) /*!< Own the interrupt 21 */ + +/* INT22 @Bit 22 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Pos (22UL) /*!< Position of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Pos) /*!< Bit mask of INT22 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_NotOwn (0x1UL) /*!< Do not own the interrupt 22 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Own (0x0UL) /*!< Own the interrupt 22 */ + +/* INT23 @Bit 23 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Pos (23UL) /*!< Position of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Pos) /*!< Bit mask of INT23 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_NotOwn (0x1UL) /*!< Do not own the interrupt 23 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Own (0x0UL) /*!< Own the interrupt 23 */ + +/* INT24 @Bit 24 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Pos (24UL) /*!< Position of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Pos) /*!< Bit mask of INT24 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_NotOwn (0x1UL) /*!< Do not own the interrupt 24 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Own (0x0UL) /*!< Own the interrupt 24 */ + +/* INT25 @Bit 25 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Pos (25UL) /*!< Position of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Pos) /*!< Bit mask of INT25 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_NotOwn (0x1UL) /*!< Do not own the interrupt 25 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Own (0x0UL) /*!< Own the interrupt 25 */ + +/* INT26 @Bit 26 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Pos (26UL) /*!< Position of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Pos) /*!< Bit mask of INT26 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_NotOwn (0x1UL) /*!< Do not own the interrupt 26 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Own (0x0UL) /*!< Own the interrupt 26 */ + +/* INT27 @Bit 27 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Pos (27UL) /*!< Position of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Pos) /*!< Bit mask of INT27 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_NotOwn (0x1UL) /*!< Do not own the interrupt 27 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Own (0x0UL) /*!< Own the interrupt 27 */ + +/* INT28 @Bit 28 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Pos (28UL) /*!< Position of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Pos) /*!< Bit mask of INT28 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_NotOwn (0x1UL) /*!< Do not own the interrupt 28 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Own (0x0UL) /*!< Own the interrupt 28 */ + +/* INT29 @Bit 29 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Pos (29UL) /*!< Position of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Pos) /*!< Bit mask of INT29 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_NotOwn (0x1UL) /*!< Do not own the interrupt 29 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Own (0x0UL) /*!< Own the interrupt 29 */ + +/* INT30 @Bit 30 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Pos (30UL) /*!< Position of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Pos) /*!< Bit mask of INT30 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_NotOwn (0x1UL) /*!< Do not own the interrupt 30 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Own (0x0UL) /*!< Own the interrupt 30 */ + +/* INT31 @Bit 31 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Pos (31UL) /*!< Position of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Pos) /*!< Bit mask of INT31 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_NotOwn (0x1UL) /*!< Do not own the interrupt 31 */ + #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Own (0x0UL) /*!< Own the interrupt 31 */ + + +/* UICR_IPCT_GLOBAL_INTERRUPT_SECURE: Request permission for the interrupts of IPCT[n] in Global domain */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* INT0 @Bit 0 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Pos (0UL) /*!< Position of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Pos) /*!< Bit mask of INT0 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Secure (0x1UL) /*!< The interrupt 0 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_NonSecure (0x0UL) /*!< The interrupt 0 is non-secure */ + +/* INT1 @Bit 1 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Pos (1UL) /*!< Position of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Pos) /*!< Bit mask of INT1 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Secure (0x1UL) /*!< The interrupt 1 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_NonSecure (0x0UL) /*!< The interrupt 1 is non-secure */ + +/* INT2 @Bit 2 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Pos (2UL) /*!< Position of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Pos) /*!< Bit mask of INT2 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Secure (0x1UL) /*!< The interrupt 2 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_NonSecure (0x0UL) /*!< The interrupt 2 is non-secure */ + +/* INT3 @Bit 3 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Pos (3UL) /*!< Position of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Pos) /*!< Bit mask of INT3 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Secure (0x1UL) /*!< The interrupt 3 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_NonSecure (0x0UL) /*!< The interrupt 3 is non-secure */ + +/* INT4 @Bit 4 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Pos (4UL) /*!< Position of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Pos) /*!< Bit mask of INT4 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Secure (0x1UL) /*!< The interrupt 4 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_NonSecure (0x0UL) /*!< The interrupt 4 is non-secure */ + +/* INT5 @Bit 5 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Pos (5UL) /*!< Position of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Pos) /*!< Bit mask of INT5 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Secure (0x1UL) /*!< The interrupt 5 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_NonSecure (0x0UL) /*!< The interrupt 5 is non-secure */ + +/* INT6 @Bit 6 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Pos (6UL) /*!< Position of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Pos) /*!< Bit mask of INT6 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Secure (0x1UL) /*!< The interrupt 6 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_NonSecure (0x0UL) /*!< The interrupt 6 is non-secure */ + +/* INT7 @Bit 7 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Pos (7UL) /*!< Position of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Pos) /*!< Bit mask of INT7 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Secure (0x1UL) /*!< The interrupt 7 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_NonSecure (0x0UL) /*!< The interrupt 7 is non-secure */ + +/* INT8 @Bit 8 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Pos (8UL) /*!< Position of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Pos) /*!< Bit mask of INT8 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Secure (0x1UL) /*!< The interrupt 8 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_NonSecure (0x0UL) /*!< The interrupt 8 is non-secure */ + +/* INT9 @Bit 9 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Pos (9UL) /*!< Position of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Pos) /*!< Bit mask of INT9 + field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Secure (0x1UL) /*!< The interrupt 9 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_NonSecure (0x0UL) /*!< The interrupt 9 is non-secure */ + +/* INT10 @Bit 10 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Pos (10UL) /*!< Position of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Pos) /*!< Bit mask of + INT10 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Secure (0x1UL) /*!< The interrupt 10 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_NonSecure (0x0UL) /*!< The interrupt 10 is non-secure */ + +/* INT11 @Bit 11 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Pos (11UL) /*!< Position of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Pos) /*!< Bit mask of + INT11 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Secure (0x1UL) /*!< The interrupt 11 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_NonSecure (0x0UL) /*!< The interrupt 11 is non-secure */ + +/* INT12 @Bit 12 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Pos (12UL) /*!< Position of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Pos) /*!< Bit mask of + INT12 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Secure (0x1UL) /*!< The interrupt 12 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_NonSecure (0x0UL) /*!< The interrupt 12 is non-secure */ + +/* INT13 @Bit 13 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Pos (13UL) /*!< Position of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Pos) /*!< Bit mask of + INT13 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Secure (0x1UL) /*!< The interrupt 13 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_NonSecure (0x0UL) /*!< The interrupt 13 is non-secure */ + +/* INT14 @Bit 14 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Pos (14UL) /*!< Position of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Pos) /*!< Bit mask of + INT14 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Secure (0x1UL) /*!< The interrupt 14 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_NonSecure (0x0UL) /*!< The interrupt 14 is non-secure */ + +/* INT15 @Bit 15 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Pos (15UL) /*!< Position of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Pos) /*!< Bit mask of + INT15 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Secure (0x1UL) /*!< The interrupt 15 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_NonSecure (0x0UL) /*!< The interrupt 15 is non-secure */ + +/* INT16 @Bit 16 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Pos (16UL) /*!< Position of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Pos) /*!< Bit mask of + INT16 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Secure (0x1UL) /*!< The interrupt 16 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_NonSecure (0x0UL) /*!< The interrupt 16 is non-secure */ + +/* INT17 @Bit 17 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Pos (17UL) /*!< Position of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Pos) /*!< Bit mask of + INT17 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Secure (0x1UL) /*!< The interrupt 17 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_NonSecure (0x0UL) /*!< The interrupt 17 is non-secure */ + +/* INT18 @Bit 18 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Pos (18UL) /*!< Position of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Pos) /*!< Bit mask of + INT18 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Secure (0x1UL) /*!< The interrupt 18 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_NonSecure (0x0UL) /*!< The interrupt 18 is non-secure */ + +/* INT19 @Bit 19 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Pos (19UL) /*!< Position of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Pos) /*!< Bit mask of + INT19 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Secure (0x1UL) /*!< The interrupt 19 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_NonSecure (0x0UL) /*!< The interrupt 19 is non-secure */ + +/* INT20 @Bit 20 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Pos (20UL) /*!< Position of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Pos) /*!< Bit mask of + INT20 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Secure (0x1UL) /*!< The interrupt 20 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_NonSecure (0x0UL) /*!< The interrupt 20 is non-secure */ + +/* INT21 @Bit 21 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Pos (21UL) /*!< Position of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Pos) /*!< Bit mask of + INT21 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Secure (0x1UL) /*!< The interrupt 21 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_NonSecure (0x0UL) /*!< The interrupt 21 is non-secure */ + +/* INT22 @Bit 22 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Pos (22UL) /*!< Position of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Pos) /*!< Bit mask of + INT22 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Secure (0x1UL) /*!< The interrupt 22 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_NonSecure (0x0UL) /*!< The interrupt 22 is non-secure */ + +/* INT23 @Bit 23 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Pos (23UL) /*!< Position of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Pos) /*!< Bit mask of + INT23 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Secure (0x1UL) /*!< The interrupt 23 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_NonSecure (0x0UL) /*!< The interrupt 23 is non-secure */ + +/* INT24 @Bit 24 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Pos (24UL) /*!< Position of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Pos) /*!< Bit mask of + INT24 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Secure (0x1UL) /*!< The interrupt 24 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_NonSecure (0x0UL) /*!< The interrupt 24 is non-secure */ + +/* INT25 @Bit 25 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Pos (25UL) /*!< Position of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Pos) /*!< Bit mask of + INT25 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Secure (0x1UL) /*!< The interrupt 25 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_NonSecure (0x0UL) /*!< The interrupt 25 is non-secure */ + +/* INT26 @Bit 26 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Pos (26UL) /*!< Position of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Pos) /*!< Bit mask of + INT26 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Secure (0x1UL) /*!< The interrupt 26 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_NonSecure (0x0UL) /*!< The interrupt 26 is non-secure */ + +/* INT27 @Bit 27 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Pos (27UL) /*!< Position of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Pos) /*!< Bit mask of + INT27 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Secure (0x1UL) /*!< The interrupt 27 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_NonSecure (0x0UL) /*!< The interrupt 27 is non-secure */ + +/* INT28 @Bit 28 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Pos (28UL) /*!< Position of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Pos) /*!< Bit mask of + INT28 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Secure (0x1UL) /*!< The interrupt 28 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_NonSecure (0x0UL) /*!< The interrupt 28 is non-secure */ + +/* INT29 @Bit 29 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Pos (29UL) /*!< Position of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Pos) /*!< Bit mask of + INT29 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Secure (0x1UL) /*!< The interrupt 29 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_NonSecure (0x0UL) /*!< The interrupt 29 is non-secure */ + +/* INT30 @Bit 30 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Pos (30UL) /*!< Position of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Pos) /*!< Bit mask of + INT30 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Secure (0x1UL) /*!< The interrupt 30 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_NonSecure (0x0UL) /*!< The interrupt 30 is non-secure */ + +/* INT31 @Bit 31 : Interrupt number */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Pos (31UL) /*!< Position of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Pos) /*!< Bit mask of + INT31 field.*/ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field. */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Secure (0x1UL) /*!< The interrupt 31 is secure */ + #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_NonSecure (0x0UL) /*!< The interrupt 31 is non-secure */ + + + +/* ================================================= Struct UICR_IPCT_GLOBAL ================================================= */ +/** + * @brief GLOBAL [UICR_IPCT_GLOBAL] (unspecified) + */ +typedef struct { + __IOM uint32_t INSTANCE; /*!< (@ 0x00000000) Address of the IPCT instance associated with + IPCT[n].GLOBAL*/ + __IOM NRF_UICR_IPCT_GLOBAL_CH_Type CH; /*!< (@ 0x00000004) (unspecified) */ + __IOM NRF_UICR_IPCT_GLOBAL_INTERRUPT_Type INTERRUPT; /*!< (@ 0x0000000C) (unspecified) */ +} NRF_UICR_IPCT_GLOBAL_Type; /*!< Size = 20 (0x014) */ + #define UICR_IPCT_GLOBAL_MaxCount (2UL) /*!< Size of GLOBAL[2] array. */ + #define UICR_IPCT_GLOBAL_MaxIndex (1UL) /*!< Max index of GLOBAL[2] array. */ + #define UICR_IPCT_GLOBAL_MinIndex (0UL) /*!< Min index of GLOBAL[2] array. */ + +/* UICR_IPCT_GLOBAL_INSTANCE: Address of the IPCT instance associated with IPCT[n].GLOBAL */ + #define UICR_IPCT_GLOBAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register. */ + +/* ADDRESS @Bits 0..31 : Instance address */ + #define UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + + +/* ==================================================== Struct UICR_IPCT ===================================================== */ +/** + * @brief IPCT [UICR_IPCT] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_IPCT_LOCAL_Type LOCAL; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UICR_IPCT_GLOBAL_Type GLOBAL[2]; /*!< (@ 0x00000008) (unspecified) */ +} NRF_UICR_IPCT_Type; /*!< Size = 48 (0x030) */ + + +/* ============================================= Struct UICR_DPPI_LOCAL_CH_LINK ============================================== */ +/** + * @brief LINK [UICR_DPPI_LOCAL_CH_LINK] (unspecified) + */ +typedef struct { + __IOM uint32_t DIR; /*!< (@ 0x00000000) Request linking the channels of DPPI[n] in local domain + as source or sink*/ + __IOM uint32_t EN; /*!< (@ 0x00000004) Request linking of the channels of DPPI[n] in the local + domain*/ +} NRF_UICR_DPPI_LOCAL_CH_LINK_Type; /*!< Size = 8 (0x008) */ + +/* UICR_DPPI_LOCAL_CH_LINK_DIR: Request linking the channels of DPPI[n] in local domain as source or sink */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIR register. */ + +/* CH0 @Bit 0 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Source (0x1UL) /*!< The channel 0 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Sink (0x0UL) /*!< The channel 0 is linked as sink */ + +/* CH1 @Bit 1 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Source (0x1UL) /*!< The channel 1 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Sink (0x0UL) /*!< The channel 1 is linked as sink */ + +/* CH2 @Bit 2 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Source (0x1UL) /*!< The channel 2 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Sink (0x0UL) /*!< The channel 2 is linked as sink */ + +/* CH3 @Bit 3 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Source (0x1UL) /*!< The channel 3 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Sink (0x0UL) /*!< The channel 3 is linked as sink */ + +/* CH4 @Bit 4 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Source (0x1UL) /*!< The channel 4 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Sink (0x0UL) /*!< The channel 4 is linked as sink */ + +/* CH5 @Bit 5 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Source (0x1UL) /*!< The channel 5 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Sink (0x0UL) /*!< The channel 5 is linked as sink */ + +/* CH6 @Bit 6 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Source (0x1UL) /*!< The channel 6 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Sink (0x0UL) /*!< The channel 6 is linked as sink */ + +/* CH7 @Bit 7 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Source (0x1UL) /*!< The channel 7 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Sink (0x0UL) /*!< The channel 7 is linked as sink */ + +/* CH8 @Bit 8 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Source (0x1UL) /*!< The channel 8 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Sink (0x0UL) /*!< The channel 8 is linked as sink */ + +/* CH9 @Bit 9 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Source (0x1UL) /*!< The channel 9 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Sink (0x0UL) /*!< The channel 9 is linked as sink */ + +/* CH10 @Bit 10 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Source (0x1UL) /*!< The channel 10 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Sink (0x0UL) /*!< The channel 10 is linked as sink */ + +/* CH11 @Bit 11 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Source (0x1UL) /*!< The channel 11 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Sink (0x0UL) /*!< The channel 11 is linked as sink */ + +/* CH12 @Bit 12 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Source (0x1UL) /*!< The channel 12 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Sink (0x0UL) /*!< The channel 12 is linked as sink */ + +/* CH13 @Bit 13 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Source (0x1UL) /*!< The channel 13 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Sink (0x0UL) /*!< The channel 13 is linked as sink */ + +/* CH14 @Bit 14 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Source (0x1UL) /*!< The channel 14 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Sink (0x0UL) /*!< The channel 14 is linked as sink */ + +/* CH15 @Bit 15 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Source (0x1UL) /*!< The channel 15 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Sink (0x0UL) /*!< The channel 15 is linked as sink */ + +/* CH16 @Bit 16 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Source (0x1UL) /*!< The channel 16 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Sink (0x0UL) /*!< The channel 16 is linked as sink */ + +/* CH17 @Bit 17 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Source (0x1UL) /*!< The channel 17 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Sink (0x0UL) /*!< The channel 17 is linked as sink */ + +/* CH18 @Bit 18 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Source (0x1UL) /*!< The channel 18 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Sink (0x0UL) /*!< The channel 18 is linked as sink */ + +/* CH19 @Bit 19 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Source (0x1UL) /*!< The channel 19 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Sink (0x0UL) /*!< The channel 19 is linked as sink */ + +/* CH20 @Bit 20 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Source (0x1UL) /*!< The channel 20 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Sink (0x0UL) /*!< The channel 20 is linked as sink */ + +/* CH21 @Bit 21 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Source (0x1UL) /*!< The channel 21 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Sink (0x0UL) /*!< The channel 21 is linked as sink */ + +/* CH22 @Bit 22 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Source (0x1UL) /*!< The channel 22 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Sink (0x0UL) /*!< The channel 22 is linked as sink */ + +/* CH23 @Bit 23 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Source (0x1UL) /*!< The channel 23 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Sink (0x0UL) /*!< The channel 23 is linked as sink */ + +/* CH24 @Bit 24 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Source (0x1UL) /*!< The channel 24 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Sink (0x0UL) /*!< The channel 24 is linked as sink */ + +/* CH25 @Bit 25 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Source (0x1UL) /*!< The channel 25 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Sink (0x0UL) /*!< The channel 25 is linked as sink */ + +/* CH26 @Bit 26 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Source (0x1UL) /*!< The channel 26 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Sink (0x0UL) /*!< The channel 26 is linked as sink */ + +/* CH27 @Bit 27 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Source (0x1UL) /*!< The channel 27 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Sink (0x0UL) /*!< The channel 27 is linked as sink */ + +/* CH28 @Bit 28 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Source (0x1UL) /*!< The channel 28 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Sink (0x0UL) /*!< The channel 28 is linked as sink */ + +/* CH29 @Bit 29 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Source (0x1UL) /*!< The channel 29 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Sink (0x0UL) /*!< The channel 29 is linked as sink */ + +/* CH30 @Bit 30 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Source (0x1UL) /*!< The channel 30 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Sink (0x0UL) /*!< The channel 30 is linked as sink */ + +/* CH31 @Bit 31 : Link direction */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Source (0x1UL) /*!< The channel 31 is linked as source */ + #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Sink (0x0UL) /*!< The channel 31 is linked as sink */ + + +/* UICR_DPPI_LOCAL_CH_LINK_EN: Request linking of the channels of DPPI[n] in the local domain */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of EN register. */ + +/* CH0 @Bit 0 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Disabled (0x1UL) /*!< The channel 0 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Enabled (0x0UL) /*!< The channel 0 is enabled */ + +/* CH1 @Bit 1 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Disabled (0x1UL) /*!< The channel 1 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Enabled (0x0UL) /*!< The channel 1 is enabled */ + +/* CH2 @Bit 2 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Disabled (0x1UL) /*!< The channel 2 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Enabled (0x0UL) /*!< The channel 2 is enabled */ + +/* CH3 @Bit 3 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Disabled (0x1UL) /*!< The channel 3 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Enabled (0x0UL) /*!< The channel 3 is enabled */ + +/* CH4 @Bit 4 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Disabled (0x1UL) /*!< The channel 4 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Enabled (0x0UL) /*!< The channel 4 is enabled */ + +/* CH5 @Bit 5 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Disabled (0x1UL) /*!< The channel 5 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Enabled (0x0UL) /*!< The channel 5 is enabled */ + +/* CH6 @Bit 6 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Disabled (0x1UL) /*!< The channel 6 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Enabled (0x0UL) /*!< The channel 6 is enabled */ + +/* CH7 @Bit 7 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Disabled (0x1UL) /*!< The channel 7 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Enabled (0x0UL) /*!< The channel 7 is enabled */ + +/* CH8 @Bit 8 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Disabled (0x1UL) /*!< The channel 8 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Enabled (0x0UL) /*!< The channel 8 is enabled */ + +/* CH9 @Bit 9 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Disabled (0x1UL) /*!< The channel 9 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Enabled (0x0UL) /*!< The channel 9 is enabled */ + +/* CH10 @Bit 10 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Disabled (0x1UL) /*!< The channel 10 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Enabled (0x0UL) /*!< The channel 10 is enabled */ + +/* CH11 @Bit 11 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Disabled (0x1UL) /*!< The channel 11 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Enabled (0x0UL) /*!< The channel 11 is enabled */ + +/* CH12 @Bit 12 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Disabled (0x1UL) /*!< The channel 12 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Enabled (0x0UL) /*!< The channel 12 is enabled */ + +/* CH13 @Bit 13 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Disabled (0x1UL) /*!< The channel 13 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Enabled (0x0UL) /*!< The channel 13 is enabled */ + +/* CH14 @Bit 14 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Disabled (0x1UL) /*!< The channel 14 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Enabled (0x0UL) /*!< The channel 14 is enabled */ + +/* CH15 @Bit 15 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Disabled (0x1UL) /*!< The channel 15 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Enabled (0x0UL) /*!< The channel 15 is enabled */ + +/* CH16 @Bit 16 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Disabled (0x1UL) /*!< The channel 16 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Enabled (0x0UL) /*!< The channel 16 is enabled */ + +/* CH17 @Bit 17 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Disabled (0x1UL) /*!< The channel 17 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Enabled (0x0UL) /*!< The channel 17 is enabled */ + +/* CH18 @Bit 18 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Disabled (0x1UL) /*!< The channel 18 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Enabled (0x0UL) /*!< The channel 18 is enabled */ + +/* CH19 @Bit 19 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Disabled (0x1UL) /*!< The channel 19 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Enabled (0x0UL) /*!< The channel 19 is enabled */ + +/* CH20 @Bit 20 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Disabled (0x1UL) /*!< The channel 20 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Enabled (0x0UL) /*!< The channel 20 is enabled */ + +/* CH21 @Bit 21 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Disabled (0x1UL) /*!< The channel 21 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Enabled (0x0UL) /*!< The channel 21 is enabled */ + +/* CH22 @Bit 22 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Disabled (0x1UL) /*!< The channel 22 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Enabled (0x0UL) /*!< The channel 22 is enabled */ + +/* CH23 @Bit 23 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Disabled (0x1UL) /*!< The channel 23 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Enabled (0x0UL) /*!< The channel 23 is enabled */ + +/* CH24 @Bit 24 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Disabled (0x1UL) /*!< The channel 24 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Enabled (0x0UL) /*!< The channel 24 is enabled */ + +/* CH25 @Bit 25 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Disabled (0x1UL) /*!< The channel 25 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Enabled (0x0UL) /*!< The channel 25 is enabled */ + +/* CH26 @Bit 26 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Disabled (0x1UL) /*!< The channel 26 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Enabled (0x0UL) /*!< The channel 26 is enabled */ + +/* CH27 @Bit 27 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Disabled (0x1UL) /*!< The channel 27 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Enabled (0x0UL) /*!< The channel 27 is enabled */ + +/* CH28 @Bit 28 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Disabled (0x1UL) /*!< The channel 28 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Enabled (0x0UL) /*!< The channel 28 is enabled */ + +/* CH29 @Bit 29 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Disabled (0x1UL) /*!< The channel 29 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Enabled (0x0UL) /*!< The channel 29 is enabled */ + +/* CH30 @Bit 30 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Disabled (0x1UL) /*!< The channel 30 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Enabled (0x0UL) /*!< The channel 30 is enabled */ + +/* CH31 @Bit 31 : Link enable */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Disabled (0x1UL) /*!< The channel 31 is disabled */ + #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Enabled (0x0UL) /*!< The channel 31 is enabled */ + + + +/* ================================================ Struct UICR_DPPI_LOCAL_CH ================================================ */ +/** + * @brief CH [UICR_DPPI_LOCAL_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t SECURE; /*!< (@ 0x00000000) Request permission for the channels of DPPI[n] in the + local domain*/ + __IOM NRF_UICR_DPPI_LOCAL_CH_LINK_Type LINK; /*!< (@ 0x00000004) (unspecified) */ +} NRF_UICR_DPPI_LOCAL_CH_Type; /*!< Size = 12 (0x00C) */ + +/* UICR_DPPI_LOCAL_CH_SECURE: Request permission for the channels of DPPI[n] in the local domain */ + #define UICR_DPPI_LOCAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure */ + #define UICR_DPPI_LOCAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure */ + + + +/* =============================================== Struct UICR_DPPI_LOCAL_CHG ================================================ */ +/** + * @brief CHG [UICR_DPPI_LOCAL_CHG] (unspecified) + */ +typedef struct { + __IOM uint32_t SECURE; /*!< (@ 0x00000000) Request permission for the channel groups of DPPI[n] in + the local domain*/ +} NRF_UICR_DPPI_LOCAL_CHG_Type; /*!< Size = 4 (0x004) */ + +/* UICR_DPPI_LOCAL_CHG_SECURE: Request permission for the channel groups of DPPI[n] in the local domain */ + #define UICR_DPPI_LOCAL_CHG_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CHG0 @Bit 0 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Pos (0UL) /*!< Position of CHG0 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Pos) /*!< Bit mask of CHG0 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Min (0x0UL) /*!< Min enumerator value of CHG0 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Max (0x1UL) /*!< Max enumerator value of CHG0 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Secure (0x1UL) /*!< The channel group 0 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_NonSecure (0x0UL) /*!< The channel group 0 is non-secure */ + +/* CHG1 @Bit 1 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Pos (1UL) /*!< Position of CHG1 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Pos) /*!< Bit mask of CHG1 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Min (0x0UL) /*!< Min enumerator value of CHG1 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Max (0x1UL) /*!< Max enumerator value of CHG1 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Secure (0x1UL) /*!< The channel group 1 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_NonSecure (0x0UL) /*!< The channel group 1 is non-secure */ + +/* CHG2 @Bit 2 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Pos (2UL) /*!< Position of CHG2 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Pos) /*!< Bit mask of CHG2 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Min (0x0UL) /*!< Min enumerator value of CHG2 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Max (0x1UL) /*!< Max enumerator value of CHG2 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Secure (0x1UL) /*!< The channel group 2 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_NonSecure (0x0UL) /*!< The channel group 2 is non-secure */ + +/* CHG3 @Bit 3 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Pos (3UL) /*!< Position of CHG3 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Pos) /*!< Bit mask of CHG3 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Min (0x0UL) /*!< Min enumerator value of CHG3 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Max (0x1UL) /*!< Max enumerator value of CHG3 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Secure (0x1UL) /*!< The channel group 3 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_NonSecure (0x0UL) /*!< The channel group 3 is non-secure */ + +/* CHG4 @Bit 4 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Pos (4UL) /*!< Position of CHG4 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Pos) /*!< Bit mask of CHG4 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Min (0x0UL) /*!< Min enumerator value of CHG4 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Max (0x1UL) /*!< Max enumerator value of CHG4 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Secure (0x1UL) /*!< The channel group 4 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_NonSecure (0x0UL) /*!< The channel group 4 is non-secure */ + +/* CHG5 @Bit 5 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Pos (5UL) /*!< Position of CHG5 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Pos) /*!< Bit mask of CHG5 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Min (0x0UL) /*!< Min enumerator value of CHG5 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Max (0x1UL) /*!< Max enumerator value of CHG5 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Secure (0x1UL) /*!< The channel group 5 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_NonSecure (0x0UL) /*!< The channel group 5 is non-secure */ + +/* CHG6 @Bit 6 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Pos (6UL) /*!< Position of CHG6 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Pos) /*!< Bit mask of CHG6 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Min (0x0UL) /*!< Min enumerator value of CHG6 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Max (0x1UL) /*!< Max enumerator value of CHG6 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Secure (0x1UL) /*!< The channel group 6 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_NonSecure (0x0UL) /*!< The channel group 6 is non-secure */ + +/* CHG7 @Bit 7 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Pos (7UL) /*!< Position of CHG7 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Pos) /*!< Bit mask of CHG7 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Min (0x0UL) /*!< Min enumerator value of CHG7 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Max (0x1UL) /*!< Max enumerator value of CHG7 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Secure (0x1UL) /*!< The channel group 7 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_NonSecure (0x0UL) /*!< The channel group 7 is non-secure */ + +/* CHG8 @Bit 8 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Pos (8UL) /*!< Position of CHG8 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Pos) /*!< Bit mask of CHG8 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Min (0x0UL) /*!< Min enumerator value of CHG8 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Max (0x1UL) /*!< Max enumerator value of CHG8 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Secure (0x1UL) /*!< The channel group 8 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_NonSecure (0x0UL) /*!< The channel group 8 is non-secure */ + +/* CHG9 @Bit 9 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Pos (9UL) /*!< Position of CHG9 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Pos) /*!< Bit mask of CHG9 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Min (0x0UL) /*!< Min enumerator value of CHG9 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Max (0x1UL) /*!< Max enumerator value of CHG9 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Secure (0x1UL) /*!< The channel group 9 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_NonSecure (0x0UL) /*!< The channel group 9 is non-secure */ + +/* CHG10 @Bit 10 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Pos (10UL) /*!< Position of CHG10 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Pos) /*!< Bit mask of CHG10 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Secure (0x1UL) /*!< The channel group 10 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_NonSecure (0x0UL) /*!< The channel group 10 is non-secure */ + +/* CHG11 @Bit 11 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Pos (11UL) /*!< Position of CHG11 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Pos) /*!< Bit mask of CHG11 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Secure (0x1UL) /*!< The channel group 11 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_NonSecure (0x0UL) /*!< The channel group 11 is non-secure */ + +/* CHG12 @Bit 12 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Pos (12UL) /*!< Position of CHG12 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Pos) /*!< Bit mask of CHG12 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Secure (0x1UL) /*!< The channel group 12 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_NonSecure (0x0UL) /*!< The channel group 12 is non-secure */ + +/* CHG13 @Bit 13 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Pos (13UL) /*!< Position of CHG13 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Pos) /*!< Bit mask of CHG13 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Secure (0x1UL) /*!< The channel group 13 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_NonSecure (0x0UL) /*!< The channel group 13 is non-secure */ + +/* CHG14 @Bit 14 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Pos (14UL) /*!< Position of CHG14 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Pos) /*!< Bit mask of CHG14 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Secure (0x1UL) /*!< The channel group 14 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_NonSecure (0x0UL) /*!< The channel group 14 is non-secure */ + +/* CHG15 @Bit 15 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Pos (15UL) /*!< Position of CHG15 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Pos) /*!< Bit mask of CHG15 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Secure (0x1UL) /*!< The channel group 15 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_NonSecure (0x0UL) /*!< The channel group 15 is non-secure */ + +/* CHG16 @Bit 16 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Pos (16UL) /*!< Position of CHG16 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Pos) /*!< Bit mask of CHG16 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Secure (0x1UL) /*!< The channel group 16 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_NonSecure (0x0UL) /*!< The channel group 16 is non-secure */ + +/* CHG17 @Bit 17 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Pos (17UL) /*!< Position of CHG17 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Pos) /*!< Bit mask of CHG17 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Secure (0x1UL) /*!< The channel group 17 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_NonSecure (0x0UL) /*!< The channel group 17 is non-secure */ + +/* CHG18 @Bit 18 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Pos (18UL) /*!< Position of CHG18 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Pos) /*!< Bit mask of CHG18 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Secure (0x1UL) /*!< The channel group 18 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_NonSecure (0x0UL) /*!< The channel group 18 is non-secure */ + +/* CHG19 @Bit 19 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Pos (19UL) /*!< Position of CHG19 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Pos) /*!< Bit mask of CHG19 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Secure (0x1UL) /*!< The channel group 19 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_NonSecure (0x0UL) /*!< The channel group 19 is non-secure */ + +/* CHG20 @Bit 20 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Pos (20UL) /*!< Position of CHG20 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Pos) /*!< Bit mask of CHG20 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Secure (0x1UL) /*!< The channel group 20 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_NonSecure (0x0UL) /*!< The channel group 20 is non-secure */ + +/* CHG21 @Bit 21 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Pos (21UL) /*!< Position of CHG21 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Pos) /*!< Bit mask of CHG21 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Secure (0x1UL) /*!< The channel group 21 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_NonSecure (0x0UL) /*!< The channel group 21 is non-secure */ + +/* CHG22 @Bit 22 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Pos (22UL) /*!< Position of CHG22 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Pos) /*!< Bit mask of CHG22 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Secure (0x1UL) /*!< The channel group 22 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_NonSecure (0x0UL) /*!< The channel group 22 is non-secure */ + +/* CHG23 @Bit 23 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Pos (23UL) /*!< Position of CHG23 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Pos) /*!< Bit mask of CHG23 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Secure (0x1UL) /*!< The channel group 23 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_NonSecure (0x0UL) /*!< The channel group 23 is non-secure */ + +/* CHG24 @Bit 24 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Pos (24UL) /*!< Position of CHG24 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Pos) /*!< Bit mask of CHG24 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Secure (0x1UL) /*!< The channel group 24 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_NonSecure (0x0UL) /*!< The channel group 24 is non-secure */ + +/* CHG25 @Bit 25 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Pos (25UL) /*!< Position of CHG25 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Pos) /*!< Bit mask of CHG25 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Secure (0x1UL) /*!< The channel group 25 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_NonSecure (0x0UL) /*!< The channel group 25 is non-secure */ + +/* CHG26 @Bit 26 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Pos (26UL) /*!< Position of CHG26 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Pos) /*!< Bit mask of CHG26 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Secure (0x1UL) /*!< The channel group 26 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_NonSecure (0x0UL) /*!< The channel group 26 is non-secure */ + +/* CHG27 @Bit 27 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Pos (27UL) /*!< Position of CHG27 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Pos) /*!< Bit mask of CHG27 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Secure (0x1UL) /*!< The channel group 27 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_NonSecure (0x0UL) /*!< The channel group 27 is non-secure */ + +/* CHG28 @Bit 28 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Pos (28UL) /*!< Position of CHG28 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Pos) /*!< Bit mask of CHG28 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Secure (0x1UL) /*!< The channel group 28 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_NonSecure (0x0UL) /*!< The channel group 28 is non-secure */ + +/* CHG29 @Bit 29 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Pos (29UL) /*!< Position of CHG29 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Pos) /*!< Bit mask of CHG29 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Secure (0x1UL) /*!< The channel group 29 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_NonSecure (0x0UL) /*!< The channel group 29 is non-secure */ + +/* CHG30 @Bit 30 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Pos (30UL) /*!< Position of CHG30 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Pos) /*!< Bit mask of CHG30 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Secure (0x1UL) /*!< The channel group 30 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_NonSecure (0x0UL) /*!< The channel group 30 is non-secure */ + +/* CHG31 @Bit 31 : Channel group number */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Pos (31UL) /*!< Position of CHG31 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Pos) /*!< Bit mask of CHG31 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field. */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Secure (0x1UL) /*!< The channel group 31 is secure */ + #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_NonSecure (0x0UL) /*!< The channel group 31 is non-secure */ + + + +/* ================================================= Struct UICR_DPPI_LOCAL ================================================== */ +/** + * @brief LOCAL [UICR_DPPI_LOCAL] (unspecified) + */ +typedef struct { + __IOM uint32_t INSTANCE; /*!< (@ 0x00000000) Address of the DPPI instance associated with + DPPI[n].LOCAL*/ + __IOM NRF_UICR_DPPI_LOCAL_CH_Type CH; /*!< (@ 0x00000004) (unspecified) */ + __IOM NRF_UICR_DPPI_LOCAL_CHG_Type CHG; /*!< (@ 0x00000010) (unspecified) */ +} NRF_UICR_DPPI_LOCAL_Type; /*!< Size = 20 (0x014) */ + #define UICR_DPPI_LOCAL_MaxCount (2UL) /*!< Size of LOCAL[2] array. */ + #define UICR_DPPI_LOCAL_MaxIndex (1UL) /*!< Max index of LOCAL[2] array. */ + #define UICR_DPPI_LOCAL_MinIndex (0UL) /*!< Min index of LOCAL[2] array. */ + +/* UICR_DPPI_LOCAL_INSTANCE: Address of the DPPI instance associated with DPPI[n].LOCAL */ + #define UICR_DPPI_LOCAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register. */ + +/* ADDRESS @Bits 0..31 : Instance address */ + #define UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + + +/* ============================================= Struct UICR_DPPI_GLOBAL_CH_LINK ============================================= */ +/** + * @brief LINK [UICR_DPPI_GLOBAL_CH_LINK] (unspecified) + */ +typedef struct { + __IOM uint32_t DIR; /*!< (@ 0x00000000) Request linking the channels of DPPI[n] in Global + domain as source or sink*/ + __IOM uint32_t EN; /*!< (@ 0x00000004) Request linking of the channels of DPPI[n] in the + Global domain*/ +} NRF_UICR_DPPI_GLOBAL_CH_LINK_Type; /*!< Size = 8 (0x008) */ + +/* UICR_DPPI_GLOBAL_CH_LINK_DIR: Request linking the channels of DPPI[n] in Global domain as source or sink */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIR register. */ + +/* CH0 @Bit 0 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Source (0x1UL) /*!< The channel 0 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Sink (0x0UL) /*!< The channel 0 is linked as sink */ + +/* CH1 @Bit 1 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Source (0x1UL) /*!< The channel 1 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Sink (0x0UL) /*!< The channel 1 is linked as sink */ + +/* CH2 @Bit 2 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Source (0x1UL) /*!< The channel 2 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Sink (0x0UL) /*!< The channel 2 is linked as sink */ + +/* CH3 @Bit 3 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Source (0x1UL) /*!< The channel 3 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Sink (0x0UL) /*!< The channel 3 is linked as sink */ + +/* CH4 @Bit 4 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Source (0x1UL) /*!< The channel 4 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Sink (0x0UL) /*!< The channel 4 is linked as sink */ + +/* CH5 @Bit 5 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Source (0x1UL) /*!< The channel 5 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Sink (0x0UL) /*!< The channel 5 is linked as sink */ + +/* CH6 @Bit 6 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Source (0x1UL) /*!< The channel 6 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Sink (0x0UL) /*!< The channel 6 is linked as sink */ + +/* CH7 @Bit 7 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Source (0x1UL) /*!< The channel 7 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Sink (0x0UL) /*!< The channel 7 is linked as sink */ + +/* CH8 @Bit 8 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Source (0x1UL) /*!< The channel 8 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Sink (0x0UL) /*!< The channel 8 is linked as sink */ + +/* CH9 @Bit 9 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Source (0x1UL) /*!< The channel 9 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Sink (0x0UL) /*!< The channel 9 is linked as sink */ + +/* CH10 @Bit 10 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Source (0x1UL) /*!< The channel 10 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Sink (0x0UL) /*!< The channel 10 is linked as sink */ + +/* CH11 @Bit 11 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Source (0x1UL) /*!< The channel 11 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Sink (0x0UL) /*!< The channel 11 is linked as sink */ + +/* CH12 @Bit 12 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Source (0x1UL) /*!< The channel 12 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Sink (0x0UL) /*!< The channel 12 is linked as sink */ + +/* CH13 @Bit 13 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Source (0x1UL) /*!< The channel 13 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Sink (0x0UL) /*!< The channel 13 is linked as sink */ + +/* CH14 @Bit 14 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Source (0x1UL) /*!< The channel 14 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Sink (0x0UL) /*!< The channel 14 is linked as sink */ + +/* CH15 @Bit 15 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Source (0x1UL) /*!< The channel 15 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Sink (0x0UL) /*!< The channel 15 is linked as sink */ + +/* CH16 @Bit 16 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Source (0x1UL) /*!< The channel 16 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Sink (0x0UL) /*!< The channel 16 is linked as sink */ + +/* CH17 @Bit 17 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Source (0x1UL) /*!< The channel 17 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Sink (0x0UL) /*!< The channel 17 is linked as sink */ + +/* CH18 @Bit 18 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Source (0x1UL) /*!< The channel 18 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Sink (0x0UL) /*!< The channel 18 is linked as sink */ + +/* CH19 @Bit 19 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Source (0x1UL) /*!< The channel 19 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Sink (0x0UL) /*!< The channel 19 is linked as sink */ + +/* CH20 @Bit 20 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Source (0x1UL) /*!< The channel 20 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Sink (0x0UL) /*!< The channel 20 is linked as sink */ + +/* CH21 @Bit 21 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Source (0x1UL) /*!< The channel 21 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Sink (0x0UL) /*!< The channel 21 is linked as sink */ + +/* CH22 @Bit 22 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Source (0x1UL) /*!< The channel 22 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Sink (0x0UL) /*!< The channel 22 is linked as sink */ + +/* CH23 @Bit 23 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Source (0x1UL) /*!< The channel 23 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Sink (0x0UL) /*!< The channel 23 is linked as sink */ + +/* CH24 @Bit 24 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Source (0x1UL) /*!< The channel 24 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Sink (0x0UL) /*!< The channel 24 is linked as sink */ + +/* CH25 @Bit 25 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Source (0x1UL) /*!< The channel 25 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Sink (0x0UL) /*!< The channel 25 is linked as sink */ + +/* CH26 @Bit 26 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Source (0x1UL) /*!< The channel 26 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Sink (0x0UL) /*!< The channel 26 is linked as sink */ + +/* CH27 @Bit 27 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Source (0x1UL) /*!< The channel 27 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Sink (0x0UL) /*!< The channel 27 is linked as sink */ + +/* CH28 @Bit 28 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Source (0x1UL) /*!< The channel 28 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Sink (0x0UL) /*!< The channel 28 is linked as sink */ + +/* CH29 @Bit 29 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Source (0x1UL) /*!< The channel 29 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Sink (0x0UL) /*!< The channel 29 is linked as sink */ + +/* CH30 @Bit 30 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Source (0x1UL) /*!< The channel 30 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Sink (0x0UL) /*!< The channel 30 is linked as sink */ + +/* CH31 @Bit 31 : Link direction */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Source (0x1UL) /*!< The channel 31 is linked as source */ + #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Sink (0x0UL) /*!< The channel 31 is linked as sink */ + + +/* UICR_DPPI_GLOBAL_CH_LINK_EN: Request linking of the channels of DPPI[n] in the Global domain */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of EN register. */ + +/* CH0 @Bit 0 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Disabled (0x1UL) /*!< The channel 0 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Enabled (0x0UL) /*!< The channel 0 is enabled */ + +/* CH1 @Bit 1 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Disabled (0x1UL) /*!< The channel 1 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Enabled (0x0UL) /*!< The channel 1 is enabled */ + +/* CH2 @Bit 2 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Disabled (0x1UL) /*!< The channel 2 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Enabled (0x0UL) /*!< The channel 2 is enabled */ + +/* CH3 @Bit 3 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Disabled (0x1UL) /*!< The channel 3 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Enabled (0x0UL) /*!< The channel 3 is enabled */ + +/* CH4 @Bit 4 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Disabled (0x1UL) /*!< The channel 4 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Enabled (0x0UL) /*!< The channel 4 is enabled */ + +/* CH5 @Bit 5 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Disabled (0x1UL) /*!< The channel 5 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Enabled (0x0UL) /*!< The channel 5 is enabled */ + +/* CH6 @Bit 6 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Disabled (0x1UL) /*!< The channel 6 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Enabled (0x0UL) /*!< The channel 6 is enabled */ + +/* CH7 @Bit 7 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Disabled (0x1UL) /*!< The channel 7 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Enabled (0x0UL) /*!< The channel 7 is enabled */ + +/* CH8 @Bit 8 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Disabled (0x1UL) /*!< The channel 8 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Enabled (0x0UL) /*!< The channel 8 is enabled */ + +/* CH9 @Bit 9 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Disabled (0x1UL) /*!< The channel 9 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Enabled (0x0UL) /*!< The channel 9 is enabled */ + +/* CH10 @Bit 10 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Disabled (0x1UL) /*!< The channel 10 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Enabled (0x0UL) /*!< The channel 10 is enabled */ + +/* CH11 @Bit 11 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Disabled (0x1UL) /*!< The channel 11 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Enabled (0x0UL) /*!< The channel 11 is enabled */ + +/* CH12 @Bit 12 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Disabled (0x1UL) /*!< The channel 12 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Enabled (0x0UL) /*!< The channel 12 is enabled */ + +/* CH13 @Bit 13 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Disabled (0x1UL) /*!< The channel 13 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Enabled (0x0UL) /*!< The channel 13 is enabled */ + +/* CH14 @Bit 14 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Disabled (0x1UL) /*!< The channel 14 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Enabled (0x0UL) /*!< The channel 14 is enabled */ + +/* CH15 @Bit 15 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Disabled (0x1UL) /*!< The channel 15 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Enabled (0x0UL) /*!< The channel 15 is enabled */ + +/* CH16 @Bit 16 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Disabled (0x1UL) /*!< The channel 16 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Enabled (0x0UL) /*!< The channel 16 is enabled */ + +/* CH17 @Bit 17 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Disabled (0x1UL) /*!< The channel 17 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Enabled (0x0UL) /*!< The channel 17 is enabled */ + +/* CH18 @Bit 18 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Disabled (0x1UL) /*!< The channel 18 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Enabled (0x0UL) /*!< The channel 18 is enabled */ + +/* CH19 @Bit 19 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Disabled (0x1UL) /*!< The channel 19 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Enabled (0x0UL) /*!< The channel 19 is enabled */ + +/* CH20 @Bit 20 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Disabled (0x1UL) /*!< The channel 20 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Enabled (0x0UL) /*!< The channel 20 is enabled */ + +/* CH21 @Bit 21 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Disabled (0x1UL) /*!< The channel 21 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Enabled (0x0UL) /*!< The channel 21 is enabled */ + +/* CH22 @Bit 22 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Disabled (0x1UL) /*!< The channel 22 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Enabled (0x0UL) /*!< The channel 22 is enabled */ + +/* CH23 @Bit 23 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Disabled (0x1UL) /*!< The channel 23 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Enabled (0x0UL) /*!< The channel 23 is enabled */ + +/* CH24 @Bit 24 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Disabled (0x1UL) /*!< The channel 24 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Enabled (0x0UL) /*!< The channel 24 is enabled */ + +/* CH25 @Bit 25 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Disabled (0x1UL) /*!< The channel 25 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Enabled (0x0UL) /*!< The channel 25 is enabled */ + +/* CH26 @Bit 26 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Disabled (0x1UL) /*!< The channel 26 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Enabled (0x0UL) /*!< The channel 26 is enabled */ + +/* CH27 @Bit 27 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Disabled (0x1UL) /*!< The channel 27 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Enabled (0x0UL) /*!< The channel 27 is enabled */ + +/* CH28 @Bit 28 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Disabled (0x1UL) /*!< The channel 28 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Enabled (0x0UL) /*!< The channel 28 is enabled */ + +/* CH29 @Bit 29 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Disabled (0x1UL) /*!< The channel 29 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Enabled (0x0UL) /*!< The channel 29 is enabled */ + +/* CH30 @Bit 30 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Disabled (0x1UL) /*!< The channel 30 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Enabled (0x0UL) /*!< The channel 30 is enabled */ + +/* CH31 @Bit 31 : Link enable */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Disabled (0x1UL) /*!< The channel 31 is disabled */ + #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Enabled (0x0UL) /*!< The channel 31 is enabled */ + + + +/* =============================================== Struct UICR_DPPI_GLOBAL_CH ================================================ */ +/** + * @brief CH [UICR_DPPI_GLOBAL_CH] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the channels of DPPI[n] in Global + Domain*/ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the channels of DPPI[n] in + Global domain*/ + __IOM NRF_UICR_DPPI_GLOBAL_CH_LINK_Type LINK; /*!< (@ 0x00000008) (unspecified) */ +} NRF_UICR_DPPI_GLOBAL_CH_Type; /*!< Size = 16 (0x010) */ + +/* UICR_DPPI_GLOBAL_CH_OWN: Request ownership of the channels of DPPI[n] in Global Domain */ + #define UICR_DPPI_GLOBAL_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_NotOwn (0x1UL) /*!< Do not own the channel 0 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Own (0x0UL) /*!< Own the channel 0 */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_NotOwn (0x1UL) /*!< Do not own the channel 1 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Own (0x0UL) /*!< Own the channel 1 */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_NotOwn (0x1UL) /*!< Do not own the channel 2 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Own (0x0UL) /*!< Own the channel 2 */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_NotOwn (0x1UL) /*!< Do not own the channel 3 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Own (0x0UL) /*!< Own the channel 3 */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_NotOwn (0x1UL) /*!< Do not own the channel 4 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Own (0x0UL) /*!< Own the channel 4 */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_NotOwn (0x1UL) /*!< Do not own the channel 5 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Own (0x0UL) /*!< Own the channel 5 */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_NotOwn (0x1UL) /*!< Do not own the channel 6 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Own (0x0UL) /*!< Own the channel 6 */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_NotOwn (0x1UL) /*!< Do not own the channel 7 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Own (0x0UL) /*!< Own the channel 7 */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_NotOwn (0x1UL) /*!< Do not own the channel 8 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Own (0x0UL) /*!< Own the channel 8 */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_NotOwn (0x1UL) /*!< Do not own the channel 9 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Own (0x0UL) /*!< Own the channel 9 */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_NotOwn (0x1UL) /*!< Do not own the channel 10 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Own (0x0UL) /*!< Own the channel 10 */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_NotOwn (0x1UL) /*!< Do not own the channel 11 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Own (0x0UL) /*!< Own the channel 11 */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_NotOwn (0x1UL) /*!< Do not own the channel 12 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Own (0x0UL) /*!< Own the channel 12 */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_NotOwn (0x1UL) /*!< Do not own the channel 13 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Own (0x0UL) /*!< Own the channel 13 */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_NotOwn (0x1UL) /*!< Do not own the channel 14 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Own (0x0UL) /*!< Own the channel 14 */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_NotOwn (0x1UL) /*!< Do not own the channel 15 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Own (0x0UL) /*!< Own the channel 15 */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_NotOwn (0x1UL) /*!< Do not own the channel 16 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Own (0x0UL) /*!< Own the channel 16 */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_NotOwn (0x1UL) /*!< Do not own the channel 17 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Own (0x0UL) /*!< Own the channel 17 */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_NotOwn (0x1UL) /*!< Do not own the channel 18 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Own (0x0UL) /*!< Own the channel 18 */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_NotOwn (0x1UL) /*!< Do not own the channel 19 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Own (0x0UL) /*!< Own the channel 19 */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_NotOwn (0x1UL) /*!< Do not own the channel 20 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Own (0x0UL) /*!< Own the channel 20 */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_NotOwn (0x1UL) /*!< Do not own the channel 21 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Own (0x0UL) /*!< Own the channel 21 */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_NotOwn (0x1UL) /*!< Do not own the channel 22 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Own (0x0UL) /*!< Own the channel 22 */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_NotOwn (0x1UL) /*!< Do not own the channel 23 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Own (0x0UL) /*!< Own the channel 23 */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_NotOwn (0x1UL) /*!< Do not own the channel 24 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Own (0x0UL) /*!< Own the channel 24 */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_NotOwn (0x1UL) /*!< Do not own the channel 25 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Own (0x0UL) /*!< Own the channel 25 */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_NotOwn (0x1UL) /*!< Do not own the channel 26 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Own (0x0UL) /*!< Own the channel 26 */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_NotOwn (0x1UL) /*!< Do not own the channel 27 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Own (0x0UL) /*!< Own the channel 27 */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_NotOwn (0x1UL) /*!< Do not own the channel 28 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Own (0x0UL) /*!< Own the channel 28 */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_NotOwn (0x1UL) /*!< Do not own the channel 29 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Own (0x0UL) /*!< Own the channel 29 */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_NotOwn (0x1UL) /*!< Do not own the channel 30 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Own (0x0UL) /*!< Own the channel 30 */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_NotOwn (0x1UL) /*!< Do not own the channel 31 */ + #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Own (0x0UL) /*!< Own the channel 31 */ + + +/* UICR_DPPI_GLOBAL_CH_SECURE: Request permission for the channels of DPPI[n] in Global domain */ + #define UICR_DPPI_GLOBAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CH0 @Bit 0 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Pos (0UL) /*!< Position of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure */ + +/* CH1 @Bit 1 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Pos (1UL) /*!< Position of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure */ + +/* CH2 @Bit 2 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Pos (2UL) /*!< Position of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure */ + +/* CH3 @Bit 3 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Pos (3UL) /*!< Position of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure */ + +/* CH4 @Bit 4 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Pos (4UL) /*!< Position of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure */ + +/* CH5 @Bit 5 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Pos (5UL) /*!< Position of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure */ + +/* CH6 @Bit 6 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Pos (6UL) /*!< Position of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure */ + +/* CH7 @Bit 7 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Pos (7UL) /*!< Position of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure */ + +/* CH8 @Bit 8 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Pos (8UL) /*!< Position of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure */ + +/* CH9 @Bit 9 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Pos (9UL) /*!< Position of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure */ + +/* CH10 @Bit 10 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure */ + +/* CH11 @Bit 11 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure */ + +/* CH12 @Bit 12 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure */ + +/* CH13 @Bit 13 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure */ + +/* CH14 @Bit 14 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure */ + +/* CH15 @Bit 15 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure */ + +/* CH16 @Bit 16 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure */ + +/* CH17 @Bit 17 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure */ + +/* CH18 @Bit 18 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure */ + +/* CH19 @Bit 19 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure */ + +/* CH20 @Bit 20 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure */ + +/* CH21 @Bit 21 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure */ + +/* CH22 @Bit 22 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure */ + +/* CH23 @Bit 23 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure */ + +/* CH24 @Bit 24 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure */ + +/* CH25 @Bit 25 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure */ + +/* CH26 @Bit 26 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure */ + +/* CH27 @Bit 27 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure */ + +/* CH28 @Bit 28 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure */ + +/* CH29 @Bit 29 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure */ + +/* CH30 @Bit 30 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure */ + +/* CH31 @Bit 31 : Channel number */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field. */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure */ + #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure */ + + + +/* =============================================== Struct UICR_DPPI_GLOBAL_CHG =============================================== */ +/** + * @brief CHG [UICR_DPPI_GLOBAL_CHG] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the channel groups of DPPI[n] in + Global domain*/ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the channel groups of DPPI[n] in + Global domain*/ +} NRF_UICR_DPPI_GLOBAL_CHG_Type; /*!< Size = 8 (0x008) */ + +/* UICR_DPPI_GLOBAL_CHG_OWN: Request ownership of the channel groups of DPPI[n] in Global domain */ + #define UICR_DPPI_GLOBAL_CHG_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* CHG0 @Bit 0 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Pos (0UL) /*!< Position of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Pos) /*!< Bit mask of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Min (0x0UL) /*!< Min enumerator value of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Max (0x1UL) /*!< Max enumerator value of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_NotOwn (0x1UL) /*!< Do not own the channel group 0 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Own (0x0UL) /*!< Own the channel group 0 */ + +/* CHG1 @Bit 1 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Pos (1UL) /*!< Position of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Pos) /*!< Bit mask of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Min (0x0UL) /*!< Min enumerator value of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Max (0x1UL) /*!< Max enumerator value of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_NotOwn (0x1UL) /*!< Do not own the channel group 1 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Own (0x0UL) /*!< Own the channel group 1 */ + +/* CHG2 @Bit 2 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Pos (2UL) /*!< Position of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Pos) /*!< Bit mask of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Min (0x0UL) /*!< Min enumerator value of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Max (0x1UL) /*!< Max enumerator value of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_NotOwn (0x1UL) /*!< Do not own the channel group 2 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Own (0x0UL) /*!< Own the channel group 2 */ + +/* CHG3 @Bit 3 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Pos (3UL) /*!< Position of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Pos) /*!< Bit mask of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Min (0x0UL) /*!< Min enumerator value of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Max (0x1UL) /*!< Max enumerator value of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_NotOwn (0x1UL) /*!< Do not own the channel group 3 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Own (0x0UL) /*!< Own the channel group 3 */ + +/* CHG4 @Bit 4 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Pos (4UL) /*!< Position of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Pos) /*!< Bit mask of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Min (0x0UL) /*!< Min enumerator value of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Max (0x1UL) /*!< Max enumerator value of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_NotOwn (0x1UL) /*!< Do not own the channel group 4 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Own (0x0UL) /*!< Own the channel group 4 */ + +/* CHG5 @Bit 5 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Pos (5UL) /*!< Position of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Pos) /*!< Bit mask of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Min (0x0UL) /*!< Min enumerator value of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Max (0x1UL) /*!< Max enumerator value of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_NotOwn (0x1UL) /*!< Do not own the channel group 5 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Own (0x0UL) /*!< Own the channel group 5 */ + +/* CHG6 @Bit 6 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Pos (6UL) /*!< Position of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Pos) /*!< Bit mask of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Min (0x0UL) /*!< Min enumerator value of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Max (0x1UL) /*!< Max enumerator value of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_NotOwn (0x1UL) /*!< Do not own the channel group 6 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Own (0x0UL) /*!< Own the channel group 6 */ + +/* CHG7 @Bit 7 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Pos (7UL) /*!< Position of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Pos) /*!< Bit mask of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Min (0x0UL) /*!< Min enumerator value of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Max (0x1UL) /*!< Max enumerator value of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_NotOwn (0x1UL) /*!< Do not own the channel group 7 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Own (0x0UL) /*!< Own the channel group 7 */ + +/* CHG8 @Bit 8 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Pos (8UL) /*!< Position of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Pos) /*!< Bit mask of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Min (0x0UL) /*!< Min enumerator value of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Max (0x1UL) /*!< Max enumerator value of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_NotOwn (0x1UL) /*!< Do not own the channel group 8 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Own (0x0UL) /*!< Own the channel group 8 */ + +/* CHG9 @Bit 9 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Pos (9UL) /*!< Position of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Pos) /*!< Bit mask of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Min (0x0UL) /*!< Min enumerator value of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Max (0x1UL) /*!< Max enumerator value of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_NotOwn (0x1UL) /*!< Do not own the channel group 9 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Own (0x0UL) /*!< Own the channel group 9 */ + +/* CHG10 @Bit 10 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Pos (10UL) /*!< Position of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Pos) /*!< Bit mask of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_NotOwn (0x1UL) /*!< Do not own the channel group 10 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Own (0x0UL) /*!< Own the channel group 10 */ + +/* CHG11 @Bit 11 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Pos (11UL) /*!< Position of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Pos) /*!< Bit mask of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_NotOwn (0x1UL) /*!< Do not own the channel group 11 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Own (0x0UL) /*!< Own the channel group 11 */ + +/* CHG12 @Bit 12 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Pos (12UL) /*!< Position of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Pos) /*!< Bit mask of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_NotOwn (0x1UL) /*!< Do not own the channel group 12 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Own (0x0UL) /*!< Own the channel group 12 */ + +/* CHG13 @Bit 13 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Pos (13UL) /*!< Position of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Pos) /*!< Bit mask of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_NotOwn (0x1UL) /*!< Do not own the channel group 13 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Own (0x0UL) /*!< Own the channel group 13 */ + +/* CHG14 @Bit 14 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Pos (14UL) /*!< Position of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Pos) /*!< Bit mask of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_NotOwn (0x1UL) /*!< Do not own the channel group 14 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Own (0x0UL) /*!< Own the channel group 14 */ + +/* CHG15 @Bit 15 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Pos (15UL) /*!< Position of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Pos) /*!< Bit mask of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_NotOwn (0x1UL) /*!< Do not own the channel group 15 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Own (0x0UL) /*!< Own the channel group 15 */ + +/* CHG16 @Bit 16 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Pos (16UL) /*!< Position of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Pos) /*!< Bit mask of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_NotOwn (0x1UL) /*!< Do not own the channel group 16 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Own (0x0UL) /*!< Own the channel group 16 */ + +/* CHG17 @Bit 17 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Pos (17UL) /*!< Position of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Pos) /*!< Bit mask of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_NotOwn (0x1UL) /*!< Do not own the channel group 17 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Own (0x0UL) /*!< Own the channel group 17 */ + +/* CHG18 @Bit 18 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Pos (18UL) /*!< Position of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Pos) /*!< Bit mask of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_NotOwn (0x1UL) /*!< Do not own the channel group 18 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Own (0x0UL) /*!< Own the channel group 18 */ + +/* CHG19 @Bit 19 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Pos (19UL) /*!< Position of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Pos) /*!< Bit mask of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_NotOwn (0x1UL) /*!< Do not own the channel group 19 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Own (0x0UL) /*!< Own the channel group 19 */ + +/* CHG20 @Bit 20 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Pos (20UL) /*!< Position of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Pos) /*!< Bit mask of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_NotOwn (0x1UL) /*!< Do not own the channel group 20 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Own (0x0UL) /*!< Own the channel group 20 */ + +/* CHG21 @Bit 21 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Pos (21UL) /*!< Position of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Pos) /*!< Bit mask of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_NotOwn (0x1UL) /*!< Do not own the channel group 21 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Own (0x0UL) /*!< Own the channel group 21 */ + +/* CHG22 @Bit 22 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Pos (22UL) /*!< Position of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Pos) /*!< Bit mask of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_NotOwn (0x1UL) /*!< Do not own the channel group 22 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Own (0x0UL) /*!< Own the channel group 22 */ + +/* CHG23 @Bit 23 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Pos (23UL) /*!< Position of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Pos) /*!< Bit mask of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_NotOwn (0x1UL) /*!< Do not own the channel group 23 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Own (0x0UL) /*!< Own the channel group 23 */ + +/* CHG24 @Bit 24 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Pos (24UL) /*!< Position of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Pos) /*!< Bit mask of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_NotOwn (0x1UL) /*!< Do not own the channel group 24 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Own (0x0UL) /*!< Own the channel group 24 */ + +/* CHG25 @Bit 25 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Pos (25UL) /*!< Position of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Pos) /*!< Bit mask of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_NotOwn (0x1UL) /*!< Do not own the channel group 25 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Own (0x0UL) /*!< Own the channel group 25 */ + +/* CHG26 @Bit 26 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Pos (26UL) /*!< Position of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Pos) /*!< Bit mask of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_NotOwn (0x1UL) /*!< Do not own the channel group 26 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Own (0x0UL) /*!< Own the channel group 26 */ + +/* CHG27 @Bit 27 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Pos (27UL) /*!< Position of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Pos) /*!< Bit mask of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_NotOwn (0x1UL) /*!< Do not own the channel group 27 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Own (0x0UL) /*!< Own the channel group 27 */ + +/* CHG28 @Bit 28 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Pos (28UL) /*!< Position of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Pos) /*!< Bit mask of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_NotOwn (0x1UL) /*!< Do not own the channel group 28 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Own (0x0UL) /*!< Own the channel group 28 */ + +/* CHG29 @Bit 29 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Pos (29UL) /*!< Position of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Pos) /*!< Bit mask of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_NotOwn (0x1UL) /*!< Do not own the channel group 29 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Own (0x0UL) /*!< Own the channel group 29 */ + +/* CHG30 @Bit 30 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Pos (30UL) /*!< Position of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Pos) /*!< Bit mask of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_NotOwn (0x1UL) /*!< Do not own the channel group 30 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Own (0x0UL) /*!< Own the channel group 30 */ + +/* CHG31 @Bit 31 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Pos (31UL) /*!< Position of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Pos) /*!< Bit mask of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_NotOwn (0x1UL) /*!< Do not own the channel group 31 */ + #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Own (0x0UL) /*!< Own the channel group 31 */ + + +/* UICR_DPPI_GLOBAL_CHG_SECURE: Request permission for the channel groups of DPPI[n] in Global domain */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CHG0 @Bit 0 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Pos (0UL) /*!< Position of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Pos) /*!< Bit mask of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Min (0x0UL) /*!< Min enumerator value of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Max (0x1UL) /*!< Max enumerator value of CHG0 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Secure (0x1UL) /*!< The channel group 0 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_NonSecure (0x0UL) /*!< The channel group 0 is non-secure */ + +/* CHG1 @Bit 1 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Pos (1UL) /*!< Position of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Pos) /*!< Bit mask of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Min (0x0UL) /*!< Min enumerator value of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Max (0x1UL) /*!< Max enumerator value of CHG1 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Secure (0x1UL) /*!< The channel group 1 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_NonSecure (0x0UL) /*!< The channel group 1 is non-secure */ + +/* CHG2 @Bit 2 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Pos (2UL) /*!< Position of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Pos) /*!< Bit mask of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Min (0x0UL) /*!< Min enumerator value of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Max (0x1UL) /*!< Max enumerator value of CHG2 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Secure (0x1UL) /*!< The channel group 2 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_NonSecure (0x0UL) /*!< The channel group 2 is non-secure */ + +/* CHG3 @Bit 3 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Pos (3UL) /*!< Position of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Pos) /*!< Bit mask of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Min (0x0UL) /*!< Min enumerator value of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Max (0x1UL) /*!< Max enumerator value of CHG3 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Secure (0x1UL) /*!< The channel group 3 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_NonSecure (0x0UL) /*!< The channel group 3 is non-secure */ + +/* CHG4 @Bit 4 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Pos (4UL) /*!< Position of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Pos) /*!< Bit mask of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Min (0x0UL) /*!< Min enumerator value of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Max (0x1UL) /*!< Max enumerator value of CHG4 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Secure (0x1UL) /*!< The channel group 4 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_NonSecure (0x0UL) /*!< The channel group 4 is non-secure */ + +/* CHG5 @Bit 5 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Pos (5UL) /*!< Position of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Pos) /*!< Bit mask of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Min (0x0UL) /*!< Min enumerator value of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Max (0x1UL) /*!< Max enumerator value of CHG5 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Secure (0x1UL) /*!< The channel group 5 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_NonSecure (0x0UL) /*!< The channel group 5 is non-secure */ + +/* CHG6 @Bit 6 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Pos (6UL) /*!< Position of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Pos) /*!< Bit mask of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Min (0x0UL) /*!< Min enumerator value of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Max (0x1UL) /*!< Max enumerator value of CHG6 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Secure (0x1UL) /*!< The channel group 6 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_NonSecure (0x0UL) /*!< The channel group 6 is non-secure */ + +/* CHG7 @Bit 7 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Pos (7UL) /*!< Position of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Pos) /*!< Bit mask of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Min (0x0UL) /*!< Min enumerator value of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Max (0x1UL) /*!< Max enumerator value of CHG7 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Secure (0x1UL) /*!< The channel group 7 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_NonSecure (0x0UL) /*!< The channel group 7 is non-secure */ + +/* CHG8 @Bit 8 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Pos (8UL) /*!< Position of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Pos) /*!< Bit mask of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Min (0x0UL) /*!< Min enumerator value of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Max (0x1UL) /*!< Max enumerator value of CHG8 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Secure (0x1UL) /*!< The channel group 8 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_NonSecure (0x0UL) /*!< The channel group 8 is non-secure */ + +/* CHG9 @Bit 9 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Pos (9UL) /*!< Position of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Pos) /*!< Bit mask of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Min (0x0UL) /*!< Min enumerator value of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Max (0x1UL) /*!< Max enumerator value of CHG9 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Secure (0x1UL) /*!< The channel group 9 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_NonSecure (0x0UL) /*!< The channel group 9 is non-secure */ + +/* CHG10 @Bit 10 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Pos (10UL) /*!< Position of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Pos) /*!< Bit mask of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Secure (0x1UL) /*!< The channel group 10 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_NonSecure (0x0UL) /*!< The channel group 10 is non-secure */ + +/* CHG11 @Bit 11 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Pos (11UL) /*!< Position of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Pos) /*!< Bit mask of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Secure (0x1UL) /*!< The channel group 11 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_NonSecure (0x0UL) /*!< The channel group 11 is non-secure */ + +/* CHG12 @Bit 12 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Pos (12UL) /*!< Position of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Pos) /*!< Bit mask of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Secure (0x1UL) /*!< The channel group 12 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_NonSecure (0x0UL) /*!< The channel group 12 is non-secure */ + +/* CHG13 @Bit 13 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Pos (13UL) /*!< Position of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Pos) /*!< Bit mask of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Secure (0x1UL) /*!< The channel group 13 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_NonSecure (0x0UL) /*!< The channel group 13 is non-secure */ + +/* CHG14 @Bit 14 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Pos (14UL) /*!< Position of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Pos) /*!< Bit mask of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Secure (0x1UL) /*!< The channel group 14 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_NonSecure (0x0UL) /*!< The channel group 14 is non-secure */ + +/* CHG15 @Bit 15 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Pos (15UL) /*!< Position of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Pos) /*!< Bit mask of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Secure (0x1UL) /*!< The channel group 15 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_NonSecure (0x0UL) /*!< The channel group 15 is non-secure */ + +/* CHG16 @Bit 16 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Pos (16UL) /*!< Position of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Pos) /*!< Bit mask of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Secure (0x1UL) /*!< The channel group 16 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_NonSecure (0x0UL) /*!< The channel group 16 is non-secure */ + +/* CHG17 @Bit 17 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Pos (17UL) /*!< Position of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Pos) /*!< Bit mask of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Secure (0x1UL) /*!< The channel group 17 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_NonSecure (0x0UL) /*!< The channel group 17 is non-secure */ + +/* CHG18 @Bit 18 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Pos (18UL) /*!< Position of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Pos) /*!< Bit mask of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Secure (0x1UL) /*!< The channel group 18 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_NonSecure (0x0UL) /*!< The channel group 18 is non-secure */ + +/* CHG19 @Bit 19 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Pos (19UL) /*!< Position of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Pos) /*!< Bit mask of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Secure (0x1UL) /*!< The channel group 19 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_NonSecure (0x0UL) /*!< The channel group 19 is non-secure */ + +/* CHG20 @Bit 20 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Pos (20UL) /*!< Position of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Pos) /*!< Bit mask of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Secure (0x1UL) /*!< The channel group 20 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_NonSecure (0x0UL) /*!< The channel group 20 is non-secure */ + +/* CHG21 @Bit 21 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Pos (21UL) /*!< Position of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Pos) /*!< Bit mask of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Secure (0x1UL) /*!< The channel group 21 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_NonSecure (0x0UL) /*!< The channel group 21 is non-secure */ + +/* CHG22 @Bit 22 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Pos (22UL) /*!< Position of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Pos) /*!< Bit mask of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Secure (0x1UL) /*!< The channel group 22 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_NonSecure (0x0UL) /*!< The channel group 22 is non-secure */ + +/* CHG23 @Bit 23 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Pos (23UL) /*!< Position of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Pos) /*!< Bit mask of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Secure (0x1UL) /*!< The channel group 23 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_NonSecure (0x0UL) /*!< The channel group 23 is non-secure */ + +/* CHG24 @Bit 24 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Pos (24UL) /*!< Position of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Pos) /*!< Bit mask of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Secure (0x1UL) /*!< The channel group 24 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_NonSecure (0x0UL) /*!< The channel group 24 is non-secure */ + +/* CHG25 @Bit 25 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Pos (25UL) /*!< Position of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Pos) /*!< Bit mask of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Secure (0x1UL) /*!< The channel group 25 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_NonSecure (0x0UL) /*!< The channel group 25 is non-secure */ + +/* CHG26 @Bit 26 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Pos (26UL) /*!< Position of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Pos) /*!< Bit mask of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Secure (0x1UL) /*!< The channel group 26 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_NonSecure (0x0UL) /*!< The channel group 26 is non-secure */ + +/* CHG27 @Bit 27 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Pos (27UL) /*!< Position of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Pos) /*!< Bit mask of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Secure (0x1UL) /*!< The channel group 27 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_NonSecure (0x0UL) /*!< The channel group 27 is non-secure */ + +/* CHG28 @Bit 28 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Pos (28UL) /*!< Position of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Pos) /*!< Bit mask of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Secure (0x1UL) /*!< The channel group 28 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_NonSecure (0x0UL) /*!< The channel group 28 is non-secure */ + +/* CHG29 @Bit 29 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Pos (29UL) /*!< Position of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Pos) /*!< Bit mask of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Secure (0x1UL) /*!< The channel group 29 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_NonSecure (0x0UL) /*!< The channel group 29 is non-secure */ + +/* CHG30 @Bit 30 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Pos (30UL) /*!< Position of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Pos) /*!< Bit mask of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Secure (0x1UL) /*!< The channel group 30 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_NonSecure (0x0UL) /*!< The channel group 30 is non-secure */ + +/* CHG31 @Bit 31 : Channel group number */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Pos (31UL) /*!< Position of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Pos) /*!< Bit mask of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field. */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Secure (0x1UL) /*!< The channel group 31 is secure */ + #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_NonSecure (0x0UL) /*!< The channel group 31 is non-secure */ + + + +/* ================================================= Struct UICR_DPPI_GLOBAL ================================================= */ +/** + * @brief GLOBAL [UICR_DPPI_GLOBAL] (unspecified) + */ +typedef struct { + __IOM uint32_t INSTANCE; /*!< (@ 0x00000000) Address of the DPPI instance associated with + DPPI[n].GLOBAL*/ + __IOM NRF_UICR_DPPI_GLOBAL_CH_Type CH; /*!< (@ 0x00000004) (unspecified) */ + __IOM NRF_UICR_DPPI_GLOBAL_CHG_Type CHG; /*!< (@ 0x00000014) (unspecified) */ +} NRF_UICR_DPPI_GLOBAL_Type; /*!< Size = 28 (0x01C) */ + #define UICR_DPPI_GLOBAL_MaxCount (12UL) /*!< Size of GLOBAL[12] array. */ + #define UICR_DPPI_GLOBAL_MaxIndex (11UL) /*!< Max index of GLOBAL[12] array. */ + #define UICR_DPPI_GLOBAL_MinIndex (0UL) /*!< Min index of GLOBAL[12] array. */ + +/* UICR_DPPI_GLOBAL_INSTANCE: Address of the DPPI instance associated with DPPI[n].GLOBAL */ + #define UICR_DPPI_GLOBAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register. */ + +/* ADDRESS @Bits 0..31 : Instance address */ + #define UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + + +/* ==================================================== Struct UICR_DPPI ===================================================== */ +/** + * @brief DPPI [UICR_DPPI] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_DPPI_LOCAL_Type LOCAL[2]; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UICR_DPPI_GLOBAL_Type GLOBAL[12]; /*!< (@ 0x00000028) (unspecified) */ +} NRF_UICR_DPPI_Type; /*!< Size = 376 (0x178) */ + + +/* =================================================== Struct UICR_GRTC_CC =================================================== */ +/** + * @brief CC [UICR_GRTC_CC] (unspecified) + */ +typedef struct { + __IOM uint32_t OWN; /*!< (@ 0x00000000) Request ownership of the CCs of GRTCGRTC */ + __IOM uint32_t SECURE; /*!< (@ 0x00000004) Request permission for the CCs of GRTC */ +} NRF_UICR_GRTC_CC_Type; /*!< Size = 8 (0x008) */ + +/* UICR_GRTC_CC_OWN: Request ownership of the CCs of GRTCGRTC */ + #define UICR_GRTC_CC_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register. */ + +/* CC0 @Bit 0 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC0_Pos (0UL) /*!< Position of CC0 field. */ + #define UICR_GRTC_CC_OWN_CC0_Msk (0x1UL << UICR_GRTC_CC_OWN_CC0_Pos) /*!< Bit mask of CC0 field. */ + #define UICR_GRTC_CC_OWN_CC0_Min (0x0UL) /*!< Min enumerator value of CC0 field. */ + #define UICR_GRTC_CC_OWN_CC0_Max (0x1UL) /*!< Max enumerator value of CC0 field. */ + #define UICR_GRTC_CC_OWN_CC0_NotOwn (0x1UL) /*!< Do not own the CC register 0 */ + #define UICR_GRTC_CC_OWN_CC0_Own (0x0UL) /*!< Own the CC register 0 */ + +/* CC1 @Bit 1 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC1_Pos (1UL) /*!< Position of CC1 field. */ + #define UICR_GRTC_CC_OWN_CC1_Msk (0x1UL << UICR_GRTC_CC_OWN_CC1_Pos) /*!< Bit mask of CC1 field. */ + #define UICR_GRTC_CC_OWN_CC1_Min (0x0UL) /*!< Min enumerator value of CC1 field. */ + #define UICR_GRTC_CC_OWN_CC1_Max (0x1UL) /*!< Max enumerator value of CC1 field. */ + #define UICR_GRTC_CC_OWN_CC1_NotOwn (0x1UL) /*!< Do not own the CC register 1 */ + #define UICR_GRTC_CC_OWN_CC1_Own (0x0UL) /*!< Own the CC register 1 */ + +/* CC2 @Bit 2 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC2_Pos (2UL) /*!< Position of CC2 field. */ + #define UICR_GRTC_CC_OWN_CC2_Msk (0x1UL << UICR_GRTC_CC_OWN_CC2_Pos) /*!< Bit mask of CC2 field. */ + #define UICR_GRTC_CC_OWN_CC2_Min (0x0UL) /*!< Min enumerator value of CC2 field. */ + #define UICR_GRTC_CC_OWN_CC2_Max (0x1UL) /*!< Max enumerator value of CC2 field. */ + #define UICR_GRTC_CC_OWN_CC2_NotOwn (0x1UL) /*!< Do not own the CC register 2 */ + #define UICR_GRTC_CC_OWN_CC2_Own (0x0UL) /*!< Own the CC register 2 */ + +/* CC3 @Bit 3 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC3_Pos (3UL) /*!< Position of CC3 field. */ + #define UICR_GRTC_CC_OWN_CC3_Msk (0x1UL << UICR_GRTC_CC_OWN_CC3_Pos) /*!< Bit mask of CC3 field. */ + #define UICR_GRTC_CC_OWN_CC3_Min (0x0UL) /*!< Min enumerator value of CC3 field. */ + #define UICR_GRTC_CC_OWN_CC3_Max (0x1UL) /*!< Max enumerator value of CC3 field. */ + #define UICR_GRTC_CC_OWN_CC3_NotOwn (0x1UL) /*!< Do not own the CC register 3 */ + #define UICR_GRTC_CC_OWN_CC3_Own (0x0UL) /*!< Own the CC register 3 */ + +/* CC4 @Bit 4 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC4_Pos (4UL) /*!< Position of CC4 field. */ + #define UICR_GRTC_CC_OWN_CC4_Msk (0x1UL << UICR_GRTC_CC_OWN_CC4_Pos) /*!< Bit mask of CC4 field. */ + #define UICR_GRTC_CC_OWN_CC4_Min (0x0UL) /*!< Min enumerator value of CC4 field. */ + #define UICR_GRTC_CC_OWN_CC4_Max (0x1UL) /*!< Max enumerator value of CC4 field. */ + #define UICR_GRTC_CC_OWN_CC4_NotOwn (0x1UL) /*!< Do not own the CC register 4 */ + #define UICR_GRTC_CC_OWN_CC4_Own (0x0UL) /*!< Own the CC register 4 */ + +/* CC5 @Bit 5 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC5_Pos (5UL) /*!< Position of CC5 field. */ + #define UICR_GRTC_CC_OWN_CC5_Msk (0x1UL << UICR_GRTC_CC_OWN_CC5_Pos) /*!< Bit mask of CC5 field. */ + #define UICR_GRTC_CC_OWN_CC5_Min (0x0UL) /*!< Min enumerator value of CC5 field. */ + #define UICR_GRTC_CC_OWN_CC5_Max (0x1UL) /*!< Max enumerator value of CC5 field. */ + #define UICR_GRTC_CC_OWN_CC5_NotOwn (0x1UL) /*!< Do not own the CC register 5 */ + #define UICR_GRTC_CC_OWN_CC5_Own (0x0UL) /*!< Own the CC register 5 */ + +/* CC6 @Bit 6 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC6_Pos (6UL) /*!< Position of CC6 field. */ + #define UICR_GRTC_CC_OWN_CC6_Msk (0x1UL << UICR_GRTC_CC_OWN_CC6_Pos) /*!< Bit mask of CC6 field. */ + #define UICR_GRTC_CC_OWN_CC6_Min (0x0UL) /*!< Min enumerator value of CC6 field. */ + #define UICR_GRTC_CC_OWN_CC6_Max (0x1UL) /*!< Max enumerator value of CC6 field. */ + #define UICR_GRTC_CC_OWN_CC6_NotOwn (0x1UL) /*!< Do not own the CC register 6 */ + #define UICR_GRTC_CC_OWN_CC6_Own (0x0UL) /*!< Own the CC register 6 */ + +/* CC7 @Bit 7 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC7_Pos (7UL) /*!< Position of CC7 field. */ + #define UICR_GRTC_CC_OWN_CC7_Msk (0x1UL << UICR_GRTC_CC_OWN_CC7_Pos) /*!< Bit mask of CC7 field. */ + #define UICR_GRTC_CC_OWN_CC7_Min (0x0UL) /*!< Min enumerator value of CC7 field. */ + #define UICR_GRTC_CC_OWN_CC7_Max (0x1UL) /*!< Max enumerator value of CC7 field. */ + #define UICR_GRTC_CC_OWN_CC7_NotOwn (0x1UL) /*!< Do not own the CC register 7 */ + #define UICR_GRTC_CC_OWN_CC7_Own (0x0UL) /*!< Own the CC register 7 */ + +/* CC8 @Bit 8 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC8_Pos (8UL) /*!< Position of CC8 field. */ + #define UICR_GRTC_CC_OWN_CC8_Msk (0x1UL << UICR_GRTC_CC_OWN_CC8_Pos) /*!< Bit mask of CC8 field. */ + #define UICR_GRTC_CC_OWN_CC8_Min (0x0UL) /*!< Min enumerator value of CC8 field. */ + #define UICR_GRTC_CC_OWN_CC8_Max (0x1UL) /*!< Max enumerator value of CC8 field. */ + #define UICR_GRTC_CC_OWN_CC8_NotOwn (0x1UL) /*!< Do not own the CC register 8 */ + #define UICR_GRTC_CC_OWN_CC8_Own (0x0UL) /*!< Own the CC register 8 */ + +/* CC9 @Bit 9 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC9_Pos (9UL) /*!< Position of CC9 field. */ + #define UICR_GRTC_CC_OWN_CC9_Msk (0x1UL << UICR_GRTC_CC_OWN_CC9_Pos) /*!< Bit mask of CC9 field. */ + #define UICR_GRTC_CC_OWN_CC9_Min (0x0UL) /*!< Min enumerator value of CC9 field. */ + #define UICR_GRTC_CC_OWN_CC9_Max (0x1UL) /*!< Max enumerator value of CC9 field. */ + #define UICR_GRTC_CC_OWN_CC9_NotOwn (0x1UL) /*!< Do not own the CC register 9 */ + #define UICR_GRTC_CC_OWN_CC9_Own (0x0UL) /*!< Own the CC register 9 */ + +/* CC10 @Bit 10 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC10_Pos (10UL) /*!< Position of CC10 field. */ + #define UICR_GRTC_CC_OWN_CC10_Msk (0x1UL << UICR_GRTC_CC_OWN_CC10_Pos) /*!< Bit mask of CC10 field. */ + #define UICR_GRTC_CC_OWN_CC10_Min (0x0UL) /*!< Min enumerator value of CC10 field. */ + #define UICR_GRTC_CC_OWN_CC10_Max (0x1UL) /*!< Max enumerator value of CC10 field. */ + #define UICR_GRTC_CC_OWN_CC10_NotOwn (0x1UL) /*!< Do not own the CC register 10 */ + #define UICR_GRTC_CC_OWN_CC10_Own (0x0UL) /*!< Own the CC register 10 */ + +/* CC11 @Bit 11 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC11_Pos (11UL) /*!< Position of CC11 field. */ + #define UICR_GRTC_CC_OWN_CC11_Msk (0x1UL << UICR_GRTC_CC_OWN_CC11_Pos) /*!< Bit mask of CC11 field. */ + #define UICR_GRTC_CC_OWN_CC11_Min (0x0UL) /*!< Min enumerator value of CC11 field. */ + #define UICR_GRTC_CC_OWN_CC11_Max (0x1UL) /*!< Max enumerator value of CC11 field. */ + #define UICR_GRTC_CC_OWN_CC11_NotOwn (0x1UL) /*!< Do not own the CC register 11 */ + #define UICR_GRTC_CC_OWN_CC11_Own (0x0UL) /*!< Own the CC register 11 */ + +/* CC12 @Bit 12 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC12_Pos (12UL) /*!< Position of CC12 field. */ + #define UICR_GRTC_CC_OWN_CC12_Msk (0x1UL << UICR_GRTC_CC_OWN_CC12_Pos) /*!< Bit mask of CC12 field. */ + #define UICR_GRTC_CC_OWN_CC12_Min (0x0UL) /*!< Min enumerator value of CC12 field. */ + #define UICR_GRTC_CC_OWN_CC12_Max (0x1UL) /*!< Max enumerator value of CC12 field. */ + #define UICR_GRTC_CC_OWN_CC12_NotOwn (0x1UL) /*!< Do not own the CC register 12 */ + #define UICR_GRTC_CC_OWN_CC12_Own (0x0UL) /*!< Own the CC register 12 */ + +/* CC13 @Bit 13 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC13_Pos (13UL) /*!< Position of CC13 field. */ + #define UICR_GRTC_CC_OWN_CC13_Msk (0x1UL << UICR_GRTC_CC_OWN_CC13_Pos) /*!< Bit mask of CC13 field. */ + #define UICR_GRTC_CC_OWN_CC13_Min (0x0UL) /*!< Min enumerator value of CC13 field. */ + #define UICR_GRTC_CC_OWN_CC13_Max (0x1UL) /*!< Max enumerator value of CC13 field. */ + #define UICR_GRTC_CC_OWN_CC13_NotOwn (0x1UL) /*!< Do not own the CC register 13 */ + #define UICR_GRTC_CC_OWN_CC13_Own (0x0UL) /*!< Own the CC register 13 */ + +/* CC14 @Bit 14 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC14_Pos (14UL) /*!< Position of CC14 field. */ + #define UICR_GRTC_CC_OWN_CC14_Msk (0x1UL << UICR_GRTC_CC_OWN_CC14_Pos) /*!< Bit mask of CC14 field. */ + #define UICR_GRTC_CC_OWN_CC14_Min (0x0UL) /*!< Min enumerator value of CC14 field. */ + #define UICR_GRTC_CC_OWN_CC14_Max (0x1UL) /*!< Max enumerator value of CC14 field. */ + #define UICR_GRTC_CC_OWN_CC14_NotOwn (0x1UL) /*!< Do not own the CC register 14 */ + #define UICR_GRTC_CC_OWN_CC14_Own (0x0UL) /*!< Own the CC register 14 */ + +/* CC15 @Bit 15 : Capture/compare register number */ + #define UICR_GRTC_CC_OWN_CC15_Pos (15UL) /*!< Position of CC15 field. */ + #define UICR_GRTC_CC_OWN_CC15_Msk (0x1UL << UICR_GRTC_CC_OWN_CC15_Pos) /*!< Bit mask of CC15 field. */ + #define UICR_GRTC_CC_OWN_CC15_Min (0x0UL) /*!< Min enumerator value of CC15 field. */ + #define UICR_GRTC_CC_OWN_CC15_Max (0x1UL) /*!< Max enumerator value of CC15 field. */ + #define UICR_GRTC_CC_OWN_CC15_NotOwn (0x1UL) /*!< Do not own the CC register 15 */ + #define UICR_GRTC_CC_OWN_CC15_Own (0x0UL) /*!< Own the CC register 15 */ + + +/* UICR_GRTC_CC_SECURE: Request permission for the CCs of GRTC */ + #define UICR_GRTC_CC_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register. */ + +/* CC0 @Bit 0 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC0_Pos (0UL) /*!< Position of CC0 field. */ + #define UICR_GRTC_CC_SECURE_CC0_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC0_Pos) /*!< Bit mask of CC0 field. */ + #define UICR_GRTC_CC_SECURE_CC0_Min (0x0UL) /*!< Min enumerator value of CC0 field. */ + #define UICR_GRTC_CC_SECURE_CC0_Max (0x1UL) /*!< Max enumerator value of CC0 field. */ + #define UICR_GRTC_CC_SECURE_CC0_Secure (0x1UL) /*!< The CC register 0 is secure */ + #define UICR_GRTC_CC_SECURE_CC0_NonSecure (0x0UL) /*!< The CC register 0 is non-secure */ + +/* CC1 @Bit 1 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC1_Pos (1UL) /*!< Position of CC1 field. */ + #define UICR_GRTC_CC_SECURE_CC1_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC1_Pos) /*!< Bit mask of CC1 field. */ + #define UICR_GRTC_CC_SECURE_CC1_Min (0x0UL) /*!< Min enumerator value of CC1 field. */ + #define UICR_GRTC_CC_SECURE_CC1_Max (0x1UL) /*!< Max enumerator value of CC1 field. */ + #define UICR_GRTC_CC_SECURE_CC1_Secure (0x1UL) /*!< The CC register 1 is secure */ + #define UICR_GRTC_CC_SECURE_CC1_NonSecure (0x0UL) /*!< The CC register 1 is non-secure */ + +/* CC2 @Bit 2 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC2_Pos (2UL) /*!< Position of CC2 field. */ + #define UICR_GRTC_CC_SECURE_CC2_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC2_Pos) /*!< Bit mask of CC2 field. */ + #define UICR_GRTC_CC_SECURE_CC2_Min (0x0UL) /*!< Min enumerator value of CC2 field. */ + #define UICR_GRTC_CC_SECURE_CC2_Max (0x1UL) /*!< Max enumerator value of CC2 field. */ + #define UICR_GRTC_CC_SECURE_CC2_Secure (0x1UL) /*!< The CC register 2 is secure */ + #define UICR_GRTC_CC_SECURE_CC2_NonSecure (0x0UL) /*!< The CC register 2 is non-secure */ + +/* CC3 @Bit 3 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC3_Pos (3UL) /*!< Position of CC3 field. */ + #define UICR_GRTC_CC_SECURE_CC3_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC3_Pos) /*!< Bit mask of CC3 field. */ + #define UICR_GRTC_CC_SECURE_CC3_Min (0x0UL) /*!< Min enumerator value of CC3 field. */ + #define UICR_GRTC_CC_SECURE_CC3_Max (0x1UL) /*!< Max enumerator value of CC3 field. */ + #define UICR_GRTC_CC_SECURE_CC3_Secure (0x1UL) /*!< The CC register 3 is secure */ + #define UICR_GRTC_CC_SECURE_CC3_NonSecure (0x0UL) /*!< The CC register 3 is non-secure */ + +/* CC4 @Bit 4 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC4_Pos (4UL) /*!< Position of CC4 field. */ + #define UICR_GRTC_CC_SECURE_CC4_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC4_Pos) /*!< Bit mask of CC4 field. */ + #define UICR_GRTC_CC_SECURE_CC4_Min (0x0UL) /*!< Min enumerator value of CC4 field. */ + #define UICR_GRTC_CC_SECURE_CC4_Max (0x1UL) /*!< Max enumerator value of CC4 field. */ + #define UICR_GRTC_CC_SECURE_CC4_Secure (0x1UL) /*!< The CC register 4 is secure */ + #define UICR_GRTC_CC_SECURE_CC4_NonSecure (0x0UL) /*!< The CC register 4 is non-secure */ + +/* CC5 @Bit 5 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC5_Pos (5UL) /*!< Position of CC5 field. */ + #define UICR_GRTC_CC_SECURE_CC5_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC5_Pos) /*!< Bit mask of CC5 field. */ + #define UICR_GRTC_CC_SECURE_CC5_Min (0x0UL) /*!< Min enumerator value of CC5 field. */ + #define UICR_GRTC_CC_SECURE_CC5_Max (0x1UL) /*!< Max enumerator value of CC5 field. */ + #define UICR_GRTC_CC_SECURE_CC5_Secure (0x1UL) /*!< The CC register 5 is secure */ + #define UICR_GRTC_CC_SECURE_CC5_NonSecure (0x0UL) /*!< The CC register 5 is non-secure */ + +/* CC6 @Bit 6 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC6_Pos (6UL) /*!< Position of CC6 field. */ + #define UICR_GRTC_CC_SECURE_CC6_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC6_Pos) /*!< Bit mask of CC6 field. */ + #define UICR_GRTC_CC_SECURE_CC6_Min (0x0UL) /*!< Min enumerator value of CC6 field. */ + #define UICR_GRTC_CC_SECURE_CC6_Max (0x1UL) /*!< Max enumerator value of CC6 field. */ + #define UICR_GRTC_CC_SECURE_CC6_Secure (0x1UL) /*!< The CC register 6 is secure */ + #define UICR_GRTC_CC_SECURE_CC6_NonSecure (0x0UL) /*!< The CC register 6 is non-secure */ + +/* CC7 @Bit 7 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC7_Pos (7UL) /*!< Position of CC7 field. */ + #define UICR_GRTC_CC_SECURE_CC7_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC7_Pos) /*!< Bit mask of CC7 field. */ + #define UICR_GRTC_CC_SECURE_CC7_Min (0x0UL) /*!< Min enumerator value of CC7 field. */ + #define UICR_GRTC_CC_SECURE_CC7_Max (0x1UL) /*!< Max enumerator value of CC7 field. */ + #define UICR_GRTC_CC_SECURE_CC7_Secure (0x1UL) /*!< The CC register 7 is secure */ + #define UICR_GRTC_CC_SECURE_CC7_NonSecure (0x0UL) /*!< The CC register 7 is non-secure */ + +/* CC8 @Bit 8 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC8_Pos (8UL) /*!< Position of CC8 field. */ + #define UICR_GRTC_CC_SECURE_CC8_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC8_Pos) /*!< Bit mask of CC8 field. */ + #define UICR_GRTC_CC_SECURE_CC8_Min (0x0UL) /*!< Min enumerator value of CC8 field. */ + #define UICR_GRTC_CC_SECURE_CC8_Max (0x1UL) /*!< Max enumerator value of CC8 field. */ + #define UICR_GRTC_CC_SECURE_CC8_Secure (0x1UL) /*!< The CC register 8 is secure */ + #define UICR_GRTC_CC_SECURE_CC8_NonSecure (0x0UL) /*!< The CC register 8 is non-secure */ + +/* CC9 @Bit 9 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC9_Pos (9UL) /*!< Position of CC9 field. */ + #define UICR_GRTC_CC_SECURE_CC9_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC9_Pos) /*!< Bit mask of CC9 field. */ + #define UICR_GRTC_CC_SECURE_CC9_Min (0x0UL) /*!< Min enumerator value of CC9 field. */ + #define UICR_GRTC_CC_SECURE_CC9_Max (0x1UL) /*!< Max enumerator value of CC9 field. */ + #define UICR_GRTC_CC_SECURE_CC9_Secure (0x1UL) /*!< The CC register 9 is secure */ + #define UICR_GRTC_CC_SECURE_CC9_NonSecure (0x0UL) /*!< The CC register 9 is non-secure */ + +/* CC10 @Bit 10 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC10_Pos (10UL) /*!< Position of CC10 field. */ + #define UICR_GRTC_CC_SECURE_CC10_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC10_Pos) /*!< Bit mask of CC10 field. */ + #define UICR_GRTC_CC_SECURE_CC10_Min (0x0UL) /*!< Min enumerator value of CC10 field. */ + #define UICR_GRTC_CC_SECURE_CC10_Max (0x1UL) /*!< Max enumerator value of CC10 field. */ + #define UICR_GRTC_CC_SECURE_CC10_Secure (0x1UL) /*!< The CC register 10 is secure */ + #define UICR_GRTC_CC_SECURE_CC10_NonSecure (0x0UL) /*!< The CC register 10 is non-secure */ + +/* CC11 @Bit 11 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC11_Pos (11UL) /*!< Position of CC11 field. */ + #define UICR_GRTC_CC_SECURE_CC11_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC11_Pos) /*!< Bit mask of CC11 field. */ + #define UICR_GRTC_CC_SECURE_CC11_Min (0x0UL) /*!< Min enumerator value of CC11 field. */ + #define UICR_GRTC_CC_SECURE_CC11_Max (0x1UL) /*!< Max enumerator value of CC11 field. */ + #define UICR_GRTC_CC_SECURE_CC11_Secure (0x1UL) /*!< The CC register 11 is secure */ + #define UICR_GRTC_CC_SECURE_CC11_NonSecure (0x0UL) /*!< The CC register 11 is non-secure */ + +/* CC12 @Bit 12 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC12_Pos (12UL) /*!< Position of CC12 field. */ + #define UICR_GRTC_CC_SECURE_CC12_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC12_Pos) /*!< Bit mask of CC12 field. */ + #define UICR_GRTC_CC_SECURE_CC12_Min (0x0UL) /*!< Min enumerator value of CC12 field. */ + #define UICR_GRTC_CC_SECURE_CC12_Max (0x1UL) /*!< Max enumerator value of CC12 field. */ + #define UICR_GRTC_CC_SECURE_CC12_Secure (0x1UL) /*!< The CC register 12 is secure */ + #define UICR_GRTC_CC_SECURE_CC12_NonSecure (0x0UL) /*!< The CC register 12 is non-secure */ + +/* CC13 @Bit 13 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC13_Pos (13UL) /*!< Position of CC13 field. */ + #define UICR_GRTC_CC_SECURE_CC13_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC13_Pos) /*!< Bit mask of CC13 field. */ + #define UICR_GRTC_CC_SECURE_CC13_Min (0x0UL) /*!< Min enumerator value of CC13 field. */ + #define UICR_GRTC_CC_SECURE_CC13_Max (0x1UL) /*!< Max enumerator value of CC13 field. */ + #define UICR_GRTC_CC_SECURE_CC13_Secure (0x1UL) /*!< The CC register 13 is secure */ + #define UICR_GRTC_CC_SECURE_CC13_NonSecure (0x0UL) /*!< The CC register 13 is non-secure */ + +/* CC14 @Bit 14 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC14_Pos (14UL) /*!< Position of CC14 field. */ + #define UICR_GRTC_CC_SECURE_CC14_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC14_Pos) /*!< Bit mask of CC14 field. */ + #define UICR_GRTC_CC_SECURE_CC14_Min (0x0UL) /*!< Min enumerator value of CC14 field. */ + #define UICR_GRTC_CC_SECURE_CC14_Max (0x1UL) /*!< Max enumerator value of CC14 field. */ + #define UICR_GRTC_CC_SECURE_CC14_Secure (0x1UL) /*!< The CC register 14 is secure */ + #define UICR_GRTC_CC_SECURE_CC14_NonSecure (0x0UL) /*!< The CC register 14 is non-secure */ + +/* CC15 @Bit 15 : Capture/compare register number */ + #define UICR_GRTC_CC_SECURE_CC15_Pos (15UL) /*!< Position of CC15 field. */ + #define UICR_GRTC_CC_SECURE_CC15_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC15_Pos) /*!< Bit mask of CC15 field. */ + #define UICR_GRTC_CC_SECURE_CC15_Min (0x0UL) /*!< Min enumerator value of CC15 field. */ + #define UICR_GRTC_CC_SECURE_CC15_Max (0x1UL) /*!< Max enumerator value of CC15 field. */ + #define UICR_GRTC_CC_SECURE_CC15_Secure (0x1UL) /*!< The CC register 15 is secure */ + #define UICR_GRTC_CC_SECURE_CC15_NonSecure (0x0UL) /*!< The CC register 15 is non-secure */ + + + +/* ==================================================== Struct UICR_GRTC ===================================================== */ +/** + * @brief GRTC [UICR_GRTC] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_GRTC_CC_Type CC; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_GRTC_Type; /*!< Size = 8 (0x008) */ + + +/* =================================================== Struct UICR_MAILBOX =================================================== */ +/** + * @brief MAILBOX [UICR_MAILBOX] (unspecified) + */ +typedef struct { + __IOM uint32_t ADDRESS; /*!< (@ 0x00000000) Memory start address of mailbox n */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Configuration of mailbox n */ +} NRF_UICR_MAILBOX_Type; /*!< Size = 8 (0x008) */ + #define UICR_MAILBOX_MaxCount (8UL) /*!< Size of MAILBOX[8] array. */ + #define UICR_MAILBOX_MaxIndex (7UL) /*!< Max index of MAILBOX[8] array. */ + #define UICR_MAILBOX_MinIndex (0UL) /*!< Min index of MAILBOX[8] array. */ + +/* UICR_MAILBOX_ADDRESS: Memory start address of mailbox n */ + #define UICR_MAILBOX_ADDRESS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDRESS register. */ + +/* ADDRESS @Bits 0..31 : Memory address */ + #define UICR_MAILBOX_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICR_MAILBOX_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UICR_MAILBOX_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* UICR_MAILBOX_CONFIG: Configuration of mailbox n */ + #define UICR_MAILBOX_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register. */ + +/* SECURE @Bit 3 : Permission */ + #define UICR_MAILBOX_CONFIG_SECURE_Pos (3UL) /*!< Position of SECURE field. */ + #define UICR_MAILBOX_CONFIG_SECURE_Msk (0x1UL << UICR_MAILBOX_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field. */ + #define UICR_MAILBOX_CONFIG_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field. */ + #define UICR_MAILBOX_CONFIG_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field. */ + #define UICR_MAILBOX_CONFIG_SECURE_Secure (0x1UL) /*!< The mailbox memory is secure */ + #define UICR_MAILBOX_CONFIG_SECURE_NonSecure (0x0UL) /*!< The mailbox memory is non-secure */ + +/* OWNERID @Bits 8..11 : Remote owner identification */ + #define UICR_MAILBOX_CONFIG_OWNERID_Pos (8UL) /*!< Position of OWNERID field. */ + #define UICR_MAILBOX_CONFIG_OWNERID_Msk (0xFUL << UICR_MAILBOX_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field. */ + #define UICR_MAILBOX_CONFIG_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field. */ + #define UICR_MAILBOX_CONFIG_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field. */ + +/* SIZE @Bits 16..31 : Memory size */ + #define UICR_MAILBOX_CONFIG_SIZE_Pos (16UL) /*!< Position of SIZE field. */ + #define UICR_MAILBOX_CONFIG_SIZE_Msk (0xFFFFUL << UICR_MAILBOX_CONFIG_SIZE_Pos) /*!< Bit mask of SIZE field. */ + + + +/* ================================================ Struct UICR_TRACE_ETBSINK ================================================ */ +/** + * @brief ETBSINK [UICR_TRACE_ETBSINK] (unspecified) + */ +typedef struct { + __IOM uint32_t SOURCES; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_TRACE_ETBSINK_Type; /*!< Size = 4 (0x004) */ + +/* UICR_TRACE_ETBSINK_SOURCES: (unspecified) */ + #define UICR_TRACE_ETBSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register. */ + +/* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of + STMMAINCORE field.*/ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of + ETMMAINCORE field.*/ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* STMHWEVENTS @Bit 2 : STM HW events trace */ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of + STMHWEVENTS field.*/ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested */ + +/* STMPPR @Bit 3 : STM trace from PPR CPU */ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR field.*/ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested */ + +/* STMFLPR @Bit 4 : STM trace from FLPR CPU */ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR + field.*/ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field. */ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested */ + + + +/* =============================================== Struct UICR_TRACE_TPIUSINK ================================================ */ +/** + * @brief TPIUSINK [UICR_TRACE_TPIUSINK] (unspecified) + */ +typedef struct { + __IOM uint32_t SOURCES; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_TRACE_TPIUSINK_Type; /*!< Size = 4 (0x004) */ + +/* UICR_TRACE_TPIUSINK_SOURCES: (unspecified) */ + #define UICR_TRACE_TPIUSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register. */ + +/* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of + STMMAINCORE field.*/ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of + ETMMAINCORE field.*/ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* STMHWEVENTS @Bit 2 : STM HW events trace */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of + STMHWEVENTS field.*/ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested */ + +/* STMPPR @Bit 3 : STM trace from PPR CPU */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR + field.*/ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested */ + +/* STMFLPR @Bit 4 : STM trace from FLPR CPU */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR + field.*/ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field. */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested */ + + + +/* ================================================ Struct UICR_TRACE_ETRSINK ================================================ */ +/** + * @brief ETRSINK [UICR_TRACE_ETRSINK] (unspecified) + */ +typedef struct { + __IOM uint32_t SOURCES; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_TRACE_ETRSINK_Type; /*!< Size = 4 (0x004) */ + +/* UICR_TRACE_ETRSINK_SOURCES: (unspecified) */ + #define UICR_TRACE_ETRSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register. */ + +/* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of + STMMAINCORE field.*/ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of + ETMMAINCORE field.*/ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field. */ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested */ + +/* STMHWEVENTS @Bit 2 : STM HW events trace */ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of + STMHWEVENTS field.*/ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested */ + +/* STMPPR @Bit 3 : STM trace from PPR CPU */ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR field.*/ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested */ + +/* STMFLPR @Bit 4 : STM trace from FLPR CPU */ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR + field.*/ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field. */ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested */ + #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested */ + + + +/* ==================================================== Struct UICR_TRACE ==================================================== */ +/** + * @brief TRACE [UICR_TRACE] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_TRACE_ETBSINK_Type ETBSINK; /*!< (@ 0x00000000) (unspecified) */ + __IOM NRF_UICR_TRACE_TPIUSINK_Type TPIUSINK; /*!< (@ 0x00000004) (unspecified) */ + __IOM NRF_UICR_TRACE_ETRSINK_Type ETRSINK; /*!< (@ 0x00000008) (unspecified) */ + __IOM uint32_t PORTCONFIG; /*!< (@ 0x0000000C) Trace port speed configuration */ +} NRF_UICR_TRACE_Type; /*!< Size = 16 (0x010) */ + +/* UICR_TRACE_PORTCONFIG: Trace port speed configuration */ + #define UICR_TRACE_PORTCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PORTCONFIG register. */ + +/* PORTCONFIG @Bits 0..1 : (unspecified) */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Pos (0UL) /*!< Position of PORTCONFIG field. */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Msk (0x3UL << UICR_TRACE_PORTCONFIG_PORTCONFIG_Pos) /*!< Bit mask of PORTCONFIG + field.*/ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Min (0x0UL) /*!< Min enumerator value of PORTCONFIG field. */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Max (0x3UL) /*!< Max enumerator value of PORTCONFIG field. */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_FullSpeed (0x3UL) /*!< Full speed */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_HalfSpeed (0x2UL) /*!< Half speed */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_QuarterSpeed (0x1UL) /*!< One quarter speed */ + #define UICR_TRACE_PORTCONFIG_PORTCONFIG_EightSpeed (0x0UL) /*!< One eigth speed */ + + + +/* ============================================== Struct UICR_TAMPER_DETECTION =============================================== */ +/** + * @brief DETECTION [UICR_TAMPER_DETECTION] Tamper policy configuration for detected security events. + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) (unspecified) */ + __IOM uint32_t RESPONSE0; /*!< (@ 0x00000004) (unspecified) */ + __IOM uint32_t RESPONSE1; /*!< (@ 0x00000008) (unspecified) */ + __IOM uint32_t TEMPDETECTORCONFIG; /*!< (@ 0x0000000C) (unspecified) */ +} NRF_UICR_TAMPER_DETECTION_Type; /*!< Size = 16 (0x010) */ + +/* UICR_TAMPER_DETECTION_ENABLE: (unspecified) */ + #define UICR_TAMPER_DETECTION_ENABLE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ENABLE register. */ + +/* GlobalEnable @Bit 0 : Enable tamper detection. When disabled all tamper enable and policy switches are ignored. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Pos (0UL) /*!< Position of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Pos) /*!< Bit mask + of GlobalEnable field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Min (0x0UL) /*!< Min enumerator value of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Max (0x1UL) /*!< Max enumerator value of GlobalEnable field. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Enable (0x0UL) /*!< Enable tamper detection. */ + #define UICR_TAMPER_DETECTION_ENABLE_GlobalEnable_Disable (0x1UL) /*!< Disable tamper detection. */ + +/* VoltageLevel @Bit 1 : Enable voltage level detectors (VDETs) on supply lines. An automatic system reset is issued when + voltage on the corresponding supply line is too low. */ + + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Pos (1UL) /*!< Position of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Pos) /*!< Bit mask + of VoltageLevel field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Min (0x0UL) /*!< Min enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Max (0x1UL) /*!< Max enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Enable (0x0UL) /*!< Enable voltage level detectors. */ + #define UICR_TAMPER_DETECTION_ENABLE_VoltageLevel_Disable (0x1UL) /*!< Disable voltage level detectors. */ + +/* ExternalActiveShield @Bit 4 : Enable external active shield detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Pos (4UL) /*!< Position of ExternalActiveShield field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Pos) + /*!< Bit mask of ExternalActiveShield field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Min (0x0UL) /*!< Min enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Max (0x1UL) /*!< Max enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Enable (0x0UL) /*!< Enable external active shield detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ExternalActiveShield_Disable (0x1UL) /*!< Disable external active shield detector. */ + +/* HardFault @Bit 7 : Configure if tamper prevention should react on hard faults. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Pos (7UL) /*!< Position of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_HardFault_Pos) /*!< Bit mask of + HardFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Min (0x0UL) /*!< Min enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Max (0x1UL) /*!< Max enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Enable (0x0UL) /*!< Enable hard fault detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_HardFault_Disable (0x1UL) /*!< Disable hard fault detector. */ + +/* ApiFault @Bit 8 : Configure if tamper prevention should react on invalid API usage. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Pos (8UL) /*!< Position of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_ApiFault_Pos) /*!< Bit mask of + ApiFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Min (0x0UL) /*!< Min enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Max (0x1UL) /*!< Max enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Enable (0x0UL) /*!< Enable API fault detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_ApiFault_Disable (0x1UL) /*!< Disable API fault detector. */ + +/* AdacFault @Bit 9 : Configure if tamper prevention should react on invalid ADAC usage. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Pos (9UL) /*!< Position of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_AdacFault_Pos) /*!< Bit mask of + AdacFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Min (0x0UL) /*!< Min enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Max (0x1UL) /*!< Max enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Enable (0x0UL) /*!< Enable invalid ADAC usage detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_AdacFault_Disable (0x1UL) /*!< Disable invalid ADAC usage detector. */ + +/* StateFault @Bit 10 : Configure if tamper prevention should react on invalid firmware execution state. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Pos (10UL) /*!< Position of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_StateFault_Pos) /*!< Bit mask of + StateFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Min (0x0UL) /*!< Min enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Max (0x1UL) /*!< Max enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Enable (0x0UL) /*!< Enable invalid firmware execution state detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_StateFault_Disable (0x1UL) /*!< Disable invalid firmware execution state detector. */ + +/* TemperatureFault @Bit 11 : Configure if tamper prevention should react when on-die temperature exceeds a valid range. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Pos (11UL) /*!< Position of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Msk (0x1UL << UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Pos) /*!< + Bit mask of TemperatureFault field.*/ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Min (0x0UL) /*!< Min enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Max (0x1UL) /*!< Max enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Enable (0x0UL) /*!< Enable invalid out-of-range temperature detector. */ + #define UICR_TAMPER_DETECTION_ENABLE_TemperatureFault_Disable (0x1UL) /*!< Disable invalid out-of-range temperature detector.*/ + + +/* UICR_TAMPER_DETECTION_RESPONSE0: (unspecified) */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RESPONSE0 register. */ + +/* VoltageLevel @Bits 0..3 : Configure tamper policy for invalid voltage level on supply lines. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Pos (0UL) /*!< Position of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Pos) /*!< Bit + mask of VoltageLevel field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Min (0x2UL) /*!< Min enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_Max (0xFUL) /*!< Max enumerator value of VoltageLevel field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_1Hour (0x4UL) /*!< Block secure services until device has been powered + and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_VoltageLevel_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* Watchdog @Bits 4..7 : Configure tamper policy for watchdog timer. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Pos (4UL) /*!< Position of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Pos) /*!< Bit mask of + Watchdog field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Min (0x2UL) /*!< Min enumerator value of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_Max (0xFUL) /*!< Max enumerator value of Watchdog field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_Watchdog_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* ExternalActiveShield @Bits 12..15 : Configure tamper policy for external active shield. BICR is used to specify which + channels (GPIOs) are enabled. */ + + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Pos (12UL) /*!< Position of ExternalActiveShield field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Pos) + /*!< Bit mask of ExternalActiveShield field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Min (0x1UL) /*!< Min enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Max (0xFUL) /*!< Max enumerator value of ExternalActiveShield + field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_Manual (0x1UL) /*!< Block secure services until requested to + unblock secure services. Allows user application to + take required actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_PowerCycle (0x2UL) /*!< Block secure services until power cycling + the device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_15Minutes (0x3UL) /*!< Block secure services until device has + been powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, + this bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ExternalActiveShield_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + +/* InternalDetectors @Bits 20..23 : Configure tamper policy for internal detectors including glitch detector, signal protector + and CRACEN detector. See for more information. An automatic reset is issued upon detection. + */ + + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Pos (20UL) /*!< Position of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Pos) + /*!< Bit mask of InternalDetectors field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Min (0x2UL) /*!< Min enumerator value of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_Max (0xFUL) /*!< Max enumerator value of InternalDetectors field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_PowerCycle (0x2UL) /*!< Block secure services until power cycling + the device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_InternalDetectors_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + +/* HardFault @Bits 24..27 : Configure tamper policy for hard fault. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Pos (24UL) /*!< Position of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Pos) /*!< Bit mask + of HardFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Min (0x1UL) /*!< Min enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Max (0xFUL) /*!< Max enumerator value of HardFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_HardFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* ApiFault @Bits 28..31 : Configure tamper policy for invalid API usage. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Pos (28UL) /*!< Position of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Pos) /*!< Bit mask of + ApiFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Min (0x1UL) /*!< Min enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Max (0xFUL) /*!< Max enumerator value of ApiFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE0_ApiFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + + +/* UICR_TAMPER_DETECTION_RESPONSE1: (unspecified) */ + #define UICR_TAMPER_DETECTION_RESPONSE1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RESPONSE1 register. */ + +/* AdacFault @Bits 0..3 : Configure tamper policy for invalid ADAC usage. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Pos (0UL) /*!< Position of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Pos) /*!< Bit mask + of AdacFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Min (0x1UL) /*!< Min enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Max (0xFUL) /*!< Max enumerator value of AdacFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_AdacFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* StateFault @Bits 4..7 : Configure tamper policy for illegal firmware execution state. Automatic reset is issued be secure + domain before secure services are permitted again. */ + + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Pos (4UL) /*!< Position of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Pos) /*!< Bit mask + of StateFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Min (0x1UL) /*!< Min enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Max (0xFUL) /*!< Max enumerator value of StateFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_Manual (0x1UL) /*!< Block secure services until requested to unblock secure + services. Allows user application to take required + actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_15Minutes (0x3UL) /*!< Block secure services until device has been powered + and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_1Hour (0x4UL) /*!< Block secure services until device has been powered and + idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this bricks + the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_StateFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic reset. */ + +/* TemperatureFault @Bits 8..11 : Configure out-of-range on-die temperature tamper policy. A reset is required to continue + providing secure services once the on-temperature is within valid operating conditions again. + This reset is automatically triggered by the secure domain. */ + + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Pos (8UL) /*!< Position of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Msk (0xFUL << UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Pos) + /*!< Bit mask of TemperatureFault field.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Min (0x1UL) /*!< Min enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Max (0xFUL) /*!< Max enumerator value of TemperatureFault field. */ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_Manual (0x1UL) /*!< Block secure services until requested to unblock + secure services. Allows user application to take + required actions.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_PowerCycle (0x2UL) /*!< Block secure services until power cycling the + device.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_15Minutes (0x3UL) /*!< Block secure services until device has been + powered and idle for 15 minutes.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_1Hour (0x4UL) /*!< Block secure services until device has been + powered and idle for one hour.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_LCSDiscarded (0xAUL) /*!< Transition to LCS Discarded. Warning, this + bricks the device permanently.*/ + #define UICR_TAMPER_DETECTION_RESPONSE1_TemperatureFault_ResetOnly (0xFUL) /*!< No addition penalty besides the automatic + reset.*/ + + +/* UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG: (unspecified) */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TEMPDETECTORCONFIG register. */ + +/* TemperatureDetectionStrategy @Bits 0..1 : Configure when on-die temperature sensor should check the temperature. */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Pos (0UL) /*!< Position of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Msk (0x3UL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Pos) + /*!< Bit mask of TemperatureDetectionStrategy + field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Min (0x1UL) /*!< Min enumerator value of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Max (0x3UL) /*!< Max enumerator value of + TemperatureDetectionStrategy field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_Periodically (0x1UL) /*!< On-die temperature + sensor is read periodically with selected interval.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_OnServiceCallAndPeriodically (0x2UL) /*!< On-die + temperature sensor is read before each secure + service call and periodically with selected + interval.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionStrategy_OnServiceCallOnly (0x3UL) /*!< On-die + temperature sensor is read before each secure + service call.*/ + +/* TemperatureDetectionInterval @Bits 2..3 : Configure interval for on-die temperature reading if periodic reading is enabled. */ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Pos (2UL) /*!< Position of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Msk (0x3UL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Pos) + /*!< Bit mask of TemperatureDetectionInterval + field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Min (0x0UL) /*!< Min enumerator value of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_Max (0x3UL) /*!< Max enumerator value of + TemperatureDetectionInterval field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_1Minute (0x0UL) /*!< On-die temperature sensor + is read with one minute intervals.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_15Minutes (0x2UL) /*!< On-die temperature sensor + is read with 15 minutes intervals.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_TemperatureDetectionInterval_1Hour (0x3UL) /*!< On-die temperature sensor is + read with one hour intervals.*/ + +/* LowTemperatureThresholdShift @Bits 4..11 : Low temperature detection threshold shift in degrees Celsius. The low temperature + threshold is calculated by adding the threshold shift to the minimum operating + temperature of the SoC. */ + + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Pos (4UL) /*!< Position of + LowTemperatureThresholdShift field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Msk (0xFFUL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_LowTemperatureThresholdShift_Pos) + /*!< Bit mask of LowTemperatureThresholdShift + field.*/ + +/* HighTemperatureThresholdShift @Bits 12..19 : High temperature detection threshold shift in degrees Celsius. The high + temperature threshold is calculated by subtracting the threshold shift from the + maximum operating temperature of the SoC. */ + + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Pos (12UL) /*!< Position of + HighTemperatureThresholdShift field.*/ + #define UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Msk (0xFFUL << UICR_TAMPER_DETECTION_TEMPDETECTORCONFIG_HighTemperatureThresholdShift_Pos) + /*!< Bit mask of HighTemperatureThresholdShift + field.*/ + + + +/* =========================================== Struct UICR_TAMPER_COUNTERMEASURES ============================================ */ +/** + * @brief COUNTERMEASURES [UICR_TAMPER_COUNTERMEASURES] Configuration of countermeasures. + */ +typedef struct { + __IOM uint32_t ENABLE; /*!< (@ 0x00000000) (unspecified) */ +} NRF_UICR_TAMPER_COUNTERMEASURES_Type; /*!< Size = 4 (0x004) */ + +/* UICR_TAMPER_COUNTERMEASURES_ENABLE: (unspecified) */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ENABLE register. */ + +/* DPAAES @Bit 0 : Configure Differential Power Analysis countermeasure for CRACEN AES. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Pos (0UL) /*!< Position of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Pos) /*!< Bit mask + of DPAAES field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Min (0x0UL) /*!< Min enumerator value of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Max (0x1UL) /*!< Max enumerator value of DPAAES field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAAES_Disable (0x1UL) /*!< Disable countermeasure. */ + +/* DPAPK @Bit 1 : Configure Differential Power Analysis countermeasure for CRACEN PK. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Pos (1UL) /*!< Position of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Pos) /*!< Bit mask of + DPAPK field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Min (0x0UL) /*!< Min enumerator value of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Max (0x1UL) /*!< Max enumerator value of DPAPK field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_DPAPK_Disable (0x1UL) /*!< Disable countermeasure. */ + +/* ClockDithering @Bit 9 : Configure the clock dithering countermeasure. When enabled clock will be randomly jittered based on + TRNG. */ + + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Pos (9UL) /*!< Position of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Msk (0x1UL << UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Pos) + /*!< Bit mask of ClockDithering field.*/ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Min (0x0UL) /*!< Min enumerator value of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Max (0x1UL) /*!< Max enumerator value of ClockDithering field. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Enable (0x0UL) /*!< Enable countermeasure. */ + #define UICR_TAMPER_COUNTERMEASURES_ENABLE_ClockDithering_Disable (0x1UL) /*!< Disable countermeasure. */ + + + +/* =================================================== Struct UICR_TAMPER ==================================================== */ +/** + * @brief TAMPER [UICR_TAMPER] (unspecified) + */ +typedef struct { + __IOM NRF_UICR_TAMPER_DETECTION_Type DETECTION; /*!< (@ 0x00000000) Tamper policy configuration for detected security + events.*/ + __IOM NRF_UICR_TAMPER_COUNTERMEASURES_Type COUNTERMEASURES; /*!< (@ 0x00000010) Configuration of countermeasures. */ +} NRF_UICR_TAMPER_Type; /*!< Size = 20 (0x014) */ + +/* ======================================================= Struct UICR ======================================================= */ +/** + * @brief User information configuration registers + */ + typedef struct { /*!< UICR Structure */ + __IOM NRF_UICR_MEM_Type MEM[16]; /*!< (@ 0x00000000) (unspecified) */ + __IM uint32_t RESERVED[32]; + __IOM NRF_UICR_PERIPH_Type PERIPH[192]; /*!< (@ 0x00000100) (unspecified) */ + __IM uint32_t RESERVED1[32]; + __IOM NRF_UICR_GPIOTE_Type GPIOTE[4]; /*!< (@ 0x00000480) (unspecified) */ + __IOM NRF_UICR_IPCT_Type IPCT; /*!< (@ 0x000004B0) (unspecified) */ + __IOM NRF_UICR_DPPI_Type DPPI; /*!< (@ 0x000004E0) (unspecified) */ + __IM uint32_t RESERVED2[2]; + __IOM NRF_UICR_GRTC_Type GRTC; /*!< (@ 0x00000660) (unspecified) */ + __IM uint32_t RESERVED3[6]; + __IOM uint32_t IPCMAP[16]; /*!< (@ 0x00000680) Request configuration for the channel n of IPCMAP */ + __IM uint32_t RESERVED4[16]; + __IOM NRF_UICR_MAILBOX_Type MAILBOX[8]; /*!< (@ 0x00000700) (unspecified) */ + __IOM NRF_UICR_TRACE_Type TRACE; /*!< (@ 0x00000740) (unspecified) */ + __IM uint32_t RESERVED5[4]; + __IOM NRF_UICR_TAMPER_Type TAMPER; /*!< (@ 0x00000760) (unspecified) */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t INITSVTOR; /*!< (@ 0x00000780) Initial value of the secure VTOR (Vector Table Offset + Register) after CPU reset.*/ + __IOM uint32_t INITNSVTOR; /*!< (@ 0x00000784) Initial value of the non-secure VTOR (Vector Table + Offset Register).*/ + __IM uint32_t RESERVED7[29]; + __IOM uint32_t PTREXTUICR; /*!< (@ 0x000007FC) Pointer to extended UICR. */ + } NRF_UICR_Type; /*!< Size = 2048 (0x800) */ + +/* UICR_IPCMAP: Request configuration for the channel n of IPCMAP */ + #define UICR_IPCMAP_MaxCount (16UL) /*!< Max size of IPCMAP[16] array. */ + #define UICR_IPCMAP_MaxIndex (15UL) /*!< Max index of IPCMAP[16] array. */ + #define UICR_IPCMAP_MinIndex (0UL) /*!< Min index of IPCMAP[16] array. */ + #define UICR_IPCMAP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of IPCMAP[16] register. */ + +/* IPCTCHSINK @Bits 0..7 : IPCT channel number (sink side) */ + #define UICR_IPCMAP_IPCTCHSINK_Pos (0UL) /*!< Position of IPCTCHSINK field. */ + #define UICR_IPCMAP_IPCTCHSINK_Msk (0xFFUL << UICR_IPCMAP_IPCTCHSINK_Pos) /*!< Bit mask of IPCTCHSINK field. */ + +/* DOMAINIDSINK @Bits 8..11 : Domain ID (sink side) */ + #define UICR_IPCMAP_DOMAINIDSINK_Pos (8UL) /*!< Position of DOMAINIDSINK field. */ + #define UICR_IPCMAP_DOMAINIDSINK_Msk (0xFUL << UICR_IPCMAP_DOMAINIDSINK_Pos) /*!< Bit mask of DOMAINIDSINK field. */ + +/* IPCTCHSOURCE @Bits 16..23 : IPCT channel number (source side) */ + #define UICR_IPCMAP_IPCTCHSOURCE_Pos (16UL) /*!< Position of IPCTCHSOURCE field. */ + #define UICR_IPCMAP_IPCTCHSOURCE_Msk (0xFFUL << UICR_IPCMAP_IPCTCHSOURCE_Pos) /*!< Bit mask of IPCTCHSOURCE field. */ + +/* DOMAINIDSOURCE @Bits 24..27 : Domain ID (source side) */ + #define UICR_IPCMAP_DOMAINIDSOURCE_Pos (24UL) /*!< Position of DOMAINIDSOURCE field. */ + #define UICR_IPCMAP_DOMAINIDSOURCE_Msk (0xFUL << UICR_IPCMAP_DOMAINIDSOURCE_Pos) /*!< Bit mask of DOMAINIDSOURCE field. */ + + +/* UICR_INITSVTOR: Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. */ + #define UICR_INITSVTOR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INITSVTOR register. */ + +/* INITSVTOR @Bits 0..31 : Initial value of the VTOR. */ + #define UICR_INITSVTOR_INITSVTOR_Pos (0UL) /*!< Position of INITSVTOR field. */ + #define UICR_INITSVTOR_INITSVTOR_Msk (0xFFFFFFFFUL << UICR_INITSVTOR_INITSVTOR_Pos) /*!< Bit mask of INITSVTOR field. */ + + +/* UICR_INITNSVTOR: Initial value of the non-secure VTOR (Vector Table Offset Register). */ + #define UICR_INITNSVTOR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INITNSVTOR register. */ + +/* INITNSVTOR @Bits 0..31 : Initial value of the VTOR. */ + #define UICR_INITNSVTOR_INITNSVTOR_Pos (0UL) /*!< Position of INITNSVTOR field. */ + #define UICR_INITNSVTOR_INITNSVTOR_Msk (0xFFFFFFFFUL << UICR_INITNSVTOR_INITNSVTOR_Pos) /*!< Bit mask of INITNSVTOR field. */ + + +/* UICR_PTREXTUICR: Pointer to extended UICR. */ + #define UICR_PTREXTUICR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PTREXTUICR register. */ + +/* PTREXTUICR @Bits 0..31 : Pointer to extended UICR. */ + #define UICR_PTREXTUICR_PTREXTUICR_Pos (0UL) /*!< Position of PTREXTUICR field. */ + #define UICR_PTREXTUICR_PTREXTUICR_Msk (0xFFFFFFFFUL << UICR_PTREXTUICR_PTREXTUICR_Pos) /*!< Bit mask of PTREXTUICR field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ UICREXTENDED ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ============================================== Struct UICREXTENDED_GPIO_PIN =============================================== */ +/** + * @brief PIN [UICREXTENDED_GPIO_PIN] (unspecified) + */ +typedef struct { + __IOM uint32_t CTRLSEL; /*!< (@ 0x00000000) CTRLSEL values for PIN[o] of GPIO port P[n] */ +} NRF_UICREXTENDED_GPIO_PIN_Type; /*!< Size = 4 (0x004) */ + #define UICREXTENDED_GPIO_PIN_MaxCount (14UL) /*!< Size of PIN[14] array. */ + #define UICREXTENDED_GPIO_PIN_MaxIndex (13UL) /*!< Max index of PIN[14] array. */ + #define UICREXTENDED_GPIO_PIN_MinIndex (0UL) /*!< Min index of PIN[14] array. */ + +/* UICREXTENDED_GPIO_PIN_CTRLSEL: CTRLSEL values for PIN[o] of GPIO port P[n] */ + +/* CTRLSEL @Bits 0..2 : CTRLSEL value */ + #define UICREXTENDED_GPIO_PIN_CTRLSEL_CTRLSEL_Pos (0UL) /*!< Position of CTRLSEL field. */ + #define UICREXTENDED_GPIO_PIN_CTRLSEL_CTRLSEL_Msk (0x7UL << UICREXTENDED_GPIO_PIN_CTRLSEL_CTRLSEL_Pos) /*!< Bit mask of + CTRLSEL field.*/ + + + +/* ================================================ Struct UICREXTENDED_GPIO ================================================= */ +/** + * @brief GPIO [UICREXTENDED_GPIO] (unspecified) + */ +typedef struct { + __IOM uint32_t INSTANCE; /*!< (@ 0x00000000) Address of the GPIO instance associated with GPIO[n] */ + __IOM uint32_t OWN; /*!< (@ 0x00000004) Request ownership of the pins at GPIO port P[n] */ + __IOM uint32_t SECURE; /*!< (@ 0x00000008) Request permission for the pins at GPIO port P[n] */ + __IOM NRF_UICREXTENDED_GPIO_PIN_Type PIN[14]; /*!< (@ 0x0000000C) (unspecified) */ +} NRF_UICREXTENDED_GPIO_Type; /*!< Size = 68 (0x044) */ + #define UICREXTENDED_GPIO_MaxCount (14UL) /*!< Size of GPIO[14] array. */ + #define UICREXTENDED_GPIO_MaxIndex (13UL) /*!< Max index of GPIO[14] array. */ + #define UICREXTENDED_GPIO_MinIndex (0UL) /*!< Min index of GPIO[14] array. */ + +/* UICREXTENDED_GPIO_INSTANCE: Address of the GPIO instance associated with GPIO[n] */ + +/* ADDRESS @Bits 0..31 : Instance address */ + #define UICREXTENDED_GPIO_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define UICREXTENDED_GPIO_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICREXTENDED_GPIO_INSTANCE_ADDRESS_Pos) /*!< Bit mask of + ADDRESS field.*/ + + +/* UICREXTENDED_GPIO_OWN: Request ownership of the pins at GPIO port P[n] */ + +/* PIN0 @Bit 0 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define UICREXTENDED_GPIO_OWN_PIN0_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define UICREXTENDED_GPIO_OWN_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define UICREXTENDED_GPIO_OWN_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define UICREXTENDED_GPIO_OWN_PIN0_NotOwn (0x1UL) /*!< Do not own the pin 0 */ + #define UICREXTENDED_GPIO_OWN_PIN0_Own (0x0UL) /*!< Own the pin 0 */ + +/* PIN1 @Bit 1 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define UICREXTENDED_GPIO_OWN_PIN1_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define UICREXTENDED_GPIO_OWN_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define UICREXTENDED_GPIO_OWN_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define UICREXTENDED_GPIO_OWN_PIN1_NotOwn (0x1UL) /*!< Do not own the pin 1 */ + #define UICREXTENDED_GPIO_OWN_PIN1_Own (0x0UL) /*!< Own the pin 1 */ + +/* PIN2 @Bit 2 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define UICREXTENDED_GPIO_OWN_PIN2_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define UICREXTENDED_GPIO_OWN_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define UICREXTENDED_GPIO_OWN_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define UICREXTENDED_GPIO_OWN_PIN2_NotOwn (0x1UL) /*!< Do not own the pin 2 */ + #define UICREXTENDED_GPIO_OWN_PIN2_Own (0x0UL) /*!< Own the pin 2 */ + +/* PIN3 @Bit 3 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define UICREXTENDED_GPIO_OWN_PIN3_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define UICREXTENDED_GPIO_OWN_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define UICREXTENDED_GPIO_OWN_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define UICREXTENDED_GPIO_OWN_PIN3_NotOwn (0x1UL) /*!< Do not own the pin 3 */ + #define UICREXTENDED_GPIO_OWN_PIN3_Own (0x0UL) /*!< Own the pin 3 */ + +/* PIN4 @Bit 4 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define UICREXTENDED_GPIO_OWN_PIN4_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define UICREXTENDED_GPIO_OWN_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define UICREXTENDED_GPIO_OWN_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define UICREXTENDED_GPIO_OWN_PIN4_NotOwn (0x1UL) /*!< Do not own the pin 4 */ + #define UICREXTENDED_GPIO_OWN_PIN4_Own (0x0UL) /*!< Own the pin 4 */ + +/* PIN5 @Bit 5 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define UICREXTENDED_GPIO_OWN_PIN5_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define UICREXTENDED_GPIO_OWN_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define UICREXTENDED_GPIO_OWN_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define UICREXTENDED_GPIO_OWN_PIN5_NotOwn (0x1UL) /*!< Do not own the pin 5 */ + #define UICREXTENDED_GPIO_OWN_PIN5_Own (0x0UL) /*!< Own the pin 5 */ + +/* PIN6 @Bit 6 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define UICREXTENDED_GPIO_OWN_PIN6_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define UICREXTENDED_GPIO_OWN_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define UICREXTENDED_GPIO_OWN_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define UICREXTENDED_GPIO_OWN_PIN6_NotOwn (0x1UL) /*!< Do not own the pin 6 */ + #define UICREXTENDED_GPIO_OWN_PIN6_Own (0x0UL) /*!< Own the pin 6 */ + +/* PIN7 @Bit 7 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define UICREXTENDED_GPIO_OWN_PIN7_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define UICREXTENDED_GPIO_OWN_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define UICREXTENDED_GPIO_OWN_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define UICREXTENDED_GPIO_OWN_PIN7_NotOwn (0x1UL) /*!< Do not own the pin 7 */ + #define UICREXTENDED_GPIO_OWN_PIN7_Own (0x0UL) /*!< Own the pin 7 */ + +/* PIN8 @Bit 8 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define UICREXTENDED_GPIO_OWN_PIN8_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define UICREXTENDED_GPIO_OWN_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define UICREXTENDED_GPIO_OWN_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define UICREXTENDED_GPIO_OWN_PIN8_NotOwn (0x1UL) /*!< Do not own the pin 8 */ + #define UICREXTENDED_GPIO_OWN_PIN8_Own (0x0UL) /*!< Own the pin 8 */ + +/* PIN9 @Bit 9 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define UICREXTENDED_GPIO_OWN_PIN9_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define UICREXTENDED_GPIO_OWN_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define UICREXTENDED_GPIO_OWN_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define UICREXTENDED_GPIO_OWN_PIN9_NotOwn (0x1UL) /*!< Do not own the pin 9 */ + #define UICREXTENDED_GPIO_OWN_PIN9_Own (0x0UL) /*!< Own the pin 9 */ + +/* PIN10 @Bit 10 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define UICREXTENDED_GPIO_OWN_PIN10_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define UICREXTENDED_GPIO_OWN_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define UICREXTENDED_GPIO_OWN_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define UICREXTENDED_GPIO_OWN_PIN10_NotOwn (0x1UL) /*!< Do not own the pin 10 */ + #define UICREXTENDED_GPIO_OWN_PIN10_Own (0x0UL) /*!< Own the pin 10 */ + +/* PIN11 @Bit 11 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define UICREXTENDED_GPIO_OWN_PIN11_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define UICREXTENDED_GPIO_OWN_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define UICREXTENDED_GPIO_OWN_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define UICREXTENDED_GPIO_OWN_PIN11_NotOwn (0x1UL) /*!< Do not own the pin 11 */ + #define UICREXTENDED_GPIO_OWN_PIN11_Own (0x0UL) /*!< Own the pin 11 */ + +/* PIN12 @Bit 12 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define UICREXTENDED_GPIO_OWN_PIN12_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define UICREXTENDED_GPIO_OWN_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define UICREXTENDED_GPIO_OWN_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define UICREXTENDED_GPIO_OWN_PIN12_NotOwn (0x1UL) /*!< Do not own the pin 12 */ + #define UICREXTENDED_GPIO_OWN_PIN12_Own (0x0UL) /*!< Own the pin 12 */ + +/* PIN13 @Bit 13 : Pin number */ + #define UICREXTENDED_GPIO_OWN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define UICREXTENDED_GPIO_OWN_PIN13_Msk (0x1UL << UICREXTENDED_GPIO_OWN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define UICREXTENDED_GPIO_OWN_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define UICREXTENDED_GPIO_OWN_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define UICREXTENDED_GPIO_OWN_PIN13_NotOwn (0x1UL) /*!< Do not own the pin 13 */ + #define UICREXTENDED_GPIO_OWN_PIN13_Own (0x0UL) /*!< Own the pin 13 */ + + +/* UICREXTENDED_GPIO_SECURE: Request permission for the pins at GPIO port P[n] */ + +/* PIN0 @Bit 0 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN0_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN0_Secure (0x1UL) /*!< The pin 0 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN0_NonSecure (0x0UL) /*!< The pin 0 is non-secure */ + +/* PIN1 @Bit 1 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN1_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN1_Secure (0x1UL) /*!< The pin 1 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN1_NonSecure (0x0UL) /*!< The pin 1 is non-secure */ + +/* PIN2 @Bit 2 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN2_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN2_Secure (0x1UL) /*!< The pin 2 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN2_NonSecure (0x0UL) /*!< The pin 2 is non-secure */ + +/* PIN3 @Bit 3 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN3_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN3_Secure (0x1UL) /*!< The pin 3 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN3_NonSecure (0x0UL) /*!< The pin 3 is non-secure */ + +/* PIN4 @Bit 4 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN4_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN4_Secure (0x1UL) /*!< The pin 4 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN4_NonSecure (0x0UL) /*!< The pin 4 is non-secure */ + +/* PIN5 @Bit 5 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN5_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN5_Secure (0x1UL) /*!< The pin 5 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN5_NonSecure (0x0UL) /*!< The pin 5 is non-secure */ + +/* PIN6 @Bit 6 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN6_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN6_Secure (0x1UL) /*!< The pin 6 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN6_NonSecure (0x0UL) /*!< The pin 6 is non-secure */ + +/* PIN7 @Bit 7 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN7_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN7_Secure (0x1UL) /*!< The pin 7 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN7_NonSecure (0x0UL) /*!< The pin 7 is non-secure */ + +/* PIN8 @Bit 8 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN8_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN8_Secure (0x1UL) /*!< The pin 8 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN8_NonSecure (0x0UL) /*!< The pin 8 is non-secure */ + +/* PIN9 @Bit 9 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN9_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN9_Secure (0x1UL) /*!< The pin 9 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN9_NonSecure (0x0UL) /*!< The pin 9 is non-secure */ + +/* PIN10 @Bit 10 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN10_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN10_Secure (0x1UL) /*!< The pin 10 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN10_NonSecure (0x0UL) /*!< The pin 10 is non-secure */ + +/* PIN11 @Bit 11 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN11_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN11_Secure (0x1UL) /*!< The pin 11 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN11_NonSecure (0x0UL) /*!< The pin 11 is non-secure */ + +/* PIN12 @Bit 12 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN12_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN12_Secure (0x1UL) /*!< The pin 12 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN12_NonSecure (0x0UL) /*!< The pin 12 is non-secure */ + +/* PIN13 @Bit 13 : Pin number */ + #define UICREXTENDED_GPIO_SECURE_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN13_Msk (0x1UL << UICREXTENDED_GPIO_SECURE_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define UICREXTENDED_GPIO_SECURE_PIN13_Secure (0x1UL) /*!< The pin 13 is secure */ + #define UICREXTENDED_GPIO_SECURE_PIN13_NonSecure (0x0UL) /*!< The pin 13 is non-secure */ + + +/* =================================================== Struct UICREXTENDED =================================================== */ +/** + * @brief Extended UICR. + */ + typedef struct { /*!< UICREXTENDED Structure */ + __IOM NRF_UICREXTENDED_GPIO_Type GPIO[14]; /*!< (@ 0x00000000) (unspecified) */ + } NRF_UICREXTENDED_Type; /*!< Size = 952 (0x3B8) */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ USBHS ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ====================================================== Struct USBHS ======================================================= */ +/** + * @brief USBHS + */ + typedef struct { /*!< USBHS Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the USB peripheral. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_CORE; /*!< (@ 0x00000100) Event indicating that interrupt triggered at USBHS + core*/ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000400) Enable USB peripheral. */ + } NRF_USBHS_Type; /*!< Size = 1028 (0x404) */ + +/* USBHS_TASKS_START: Start the USB peripheral. */ + #define USBHS_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start the USB peripheral. */ + #define USBHS_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Msk (0x1UL << USBHS_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define USBHS_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* USBHS_EVENTS_CORE: Event indicating that interrupt triggered at USBHS core */ + #define USBHS_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE register. */ + +/* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at USBHS core */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_Pos (0UL) /*!< Position of EVENTS_CORE field. */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << USBHS_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated */ + #define USBHS_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated */ + + +/* USBHS_INTEN: Enable or disable interrupt */ + #define USBHS_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* CORE @Bit 0 : Enable or disable interrupt for event CORE */ + #define USBHS_INTEN_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_INTEN_CORE_Msk (0x1UL << USBHS_INTEN_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_INTEN_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_INTEN_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_INTEN_CORE_Disabled (0x0UL) /*!< Disable */ + #define USBHS_INTEN_CORE_Enabled (0x1UL) /*!< Enable */ + + +/* USBHS_INTENSET: Enable interrupt */ + #define USBHS_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */ + #define USBHS_INTENSET_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_INTENSET_CORE_Msk (0x1UL << USBHS_INTENSET_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_INTENSET_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_INTENSET_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_INTENSET_CORE_Set (0x1UL) /*!< Enable */ + #define USBHS_INTENSET_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define USBHS_INTENSET_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* USBHS_INTENCLR: Disable interrupt */ + #define USBHS_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */ + #define USBHS_INTENCLR_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_INTENCLR_CORE_Msk (0x1UL << USBHS_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_INTENCLR_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_INTENCLR_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_INTENCLR_CORE_Clear (0x1UL) /*!< Disable */ + #define USBHS_INTENCLR_CORE_Disabled (0x0UL) /*!< Read: Disabled */ + #define USBHS_INTENCLR_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* USBHS_INTPEND: Pending interrupts */ + #define USBHS_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* CORE @Bit 0 : Read pending status of interrupt for event CORE */ + #define USBHS_INTPEND_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_INTPEND_CORE_Msk (0x1UL << USBHS_INTPEND_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_INTPEND_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_INTPEND_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_INTPEND_CORE_NotPending (0x0UL) /*!< Read: Not pending */ + #define USBHS_INTPEND_CORE_Pending (0x1UL) /*!< Read: Pending */ + + +/* USBHS_ENABLE: Enable USB peripheral. */ + #define USBHS_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* CORE @Bit 0 : Enable USB Controller */ + #define USBHS_ENABLE_CORE_Pos (0UL) /*!< Position of CORE field. */ + #define USBHS_ENABLE_CORE_Msk (0x1UL << USBHS_ENABLE_CORE_Pos) /*!< Bit mask of CORE field. */ + #define USBHS_ENABLE_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ + #define USBHS_ENABLE_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + #define USBHS_ENABLE_CORE_Disabled (0x0UL) /*!< USB Controller disabled. */ + #define USBHS_ENABLE_CORE_Enabled (0x1UL) /*!< USB Controller enabled. */ + +/* PHY @Bit 1 : Enable USB PHY */ + #define USBHS_ENABLE_PHY_Pos (1UL) /*!< Position of PHY field. */ + #define USBHS_ENABLE_PHY_Msk (0x1UL << USBHS_ENABLE_PHY_Pos) /*!< Bit mask of PHY field. */ + #define USBHS_ENABLE_PHY_Min (0x0UL) /*!< Min enumerator value of PHY field. */ + #define USBHS_ENABLE_PHY_Max (0x1UL) /*!< Max enumerator value of PHY field. */ + #define USBHS_ENABLE_PHY_Disabled (0x0UL) /*!< USB PHY disabled. */ + #define USBHS_ENABLE_PHY_Enabled (0x1UL) /*!< USB PHY enabled. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ USBHSCORE ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct USBHSCORE_HC =================================================== */ +/** + * @brief HC [USBHSCORE_HC] (unspecified) + */ +typedef struct { + __IOM uint32_t CHAR; /*!< (@ 0x00000000) Host Channel Characteristics Register */ + __IM uint32_t RESERVED; + __IOM uint32_t INT; /*!< (@ 0x00000008) Host Channel Interrupt Register */ + __IOM uint32_t INTMSK; /*!< (@ 0x0000000C) Host Channel Interrupt Mask Register */ + __IOM uint32_t TSIZ; /*!< (@ 0x00000010) Host Channel Transfer Size Register */ + __IOM uint32_t DMA; /*!< (@ 0x00000014) Host Channel DMA Address Register */ +} NRF_USBHSCORE_HC_Type; /*!< Size = 24 (0x018) */ + #define USBHSCORE_HC_MaxCount (16UL) /*!< Size of HC[16] array. */ + #define USBHSCORE_HC_MaxIndex (15UL) /*!< Max index of HC[16] array. */ + #define USBHSCORE_HC_MinIndex (0UL) /*!< Min index of HC[16] array. */ + +/* USBHSCORE_HC_CHAR: Host Channel Characteristics Register */ + #define USBHSCORE_HC_CHAR_ResetValue (0x00000000UL) /*!< Reset value of CHAR register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_HC_CHAR_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_HC_CHAR_MPS_Msk (0x7FFUL << USBHSCORE_HC_CHAR_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* EPNUM @Bits 11..14 : Endpoint Number (EPNum) */ + #define USBHSCORE_HC_CHAR_EPNUM_Pos (11UL) /*!< Position of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Msk (0xFUL << USBHSCORE_HC_CHAR_EPNUM_Pos) /*!< Bit mask of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Min (0x0UL) /*!< Min enumerator value of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_Max (0xFUL) /*!< Max enumerator value of EPNUM field. */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_HC_CHAR_EPNUM_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* EPDIR @Bit 15 : Endpoint Direction (EPDir) */ + #define USBHSCORE_HC_CHAR_EPDIR_Pos (15UL) /*!< Position of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Msk (0x1UL << USBHSCORE_HC_CHAR_EPDIR_Pos) /*!< Bit mask of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Min (0x0UL) /*!< Min enumerator value of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_Max (0x1UL) /*!< Max enumerator value of EPDIR field. */ + #define USBHSCORE_HC_CHAR_EPDIR_OUT (0x0UL) /*!< OUT Direction */ + #define USBHSCORE_HC_CHAR_EPDIR_IN (0x1UL) /*!< IN Direction */ + +/* LSPDDEV @Bit 17 : Low-Speed Device (LSpdDev) */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Pos (17UL) /*!< Position of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Msk (0x1UL << USBHSCORE_HC_CHAR_LSPDDEV_Pos) /*!< Bit mask of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Min (0x0UL) /*!< Min enumerator value of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_Max (0x1UL) /*!< Max enumerator value of LSPDDEV field. */ + #define USBHSCORE_HC_CHAR_LSPDDEV_DISABLED (0x0UL) /*!< Not Communicating with low speed device */ + #define USBHSCORE_HC_CHAR_LSPDDEV_ENABLED (0x1UL) /*!< Communicating with low speed device */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_HC_CHAR_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Msk (0x3UL << USBHSCORE_HC_CHAR_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_HC_CHAR_EPTYPE_CTRL (0x0UL) /*!< Control */ + #define USBHSCORE_HC_CHAR_EPTYPE_ISOC (0x1UL) /*!< Isochronous */ + #define USBHSCORE_HC_CHAR_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_HC_CHAR_EPTYPE_INTERR (0x3UL) /*!< Interrupt */ + +/* EC @Bits 20..21 : Multi Count (MC) / Error Count (EC) */ + #define USBHSCORE_HC_CHAR_EC_Pos (20UL) /*!< Position of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Msk (0x3UL << USBHSCORE_HC_CHAR_EC_Pos) /*!< Bit mask of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Min (0x1UL) /*!< Min enumerator value of EC field. */ + #define USBHSCORE_HC_CHAR_EC_Max (0x3UL) /*!< Max enumerator value of EC field. */ + #define USBHSCORE_HC_CHAR_EC_TRANSONE (0x1UL) /*!< 1 transaction */ + #define USBHSCORE_HC_CHAR_EC_TRANSTWO (0x2UL) /*!< 2 transactions to be issued for this endpoint per microframe */ + #define USBHSCORE_HC_CHAR_EC_TRANSTHREE (0x3UL) /*!< 3 transactions to be issued for this endpoint per microframe */ + +/* DEVADDR @Bits 22..28 : Device Address (DevAddr) */ + #define USBHSCORE_HC_CHAR_DEVADDR_Pos (22UL) /*!< Position of DEVADDR field. */ + #define USBHSCORE_HC_CHAR_DEVADDR_Msk (0x7FUL << USBHSCORE_HC_CHAR_DEVADDR_Pos) /*!< Bit mask of DEVADDR field. */ + +/* ODDFRM @Bit 29 : Odd Frame (OddFrm) */ + #define USBHSCORE_HC_CHAR_ODDFRM_Pos (29UL) /*!< Position of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Msk (0x1UL << USBHSCORE_HC_CHAR_ODDFRM_Pos) /*!< Bit mask of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Min (0x0UL) /*!< Min enumerator value of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_Max (0x1UL) /*!< Max enumerator value of ODDFRM field. */ + #define USBHSCORE_HC_CHAR_ODDFRM_EFRAME (0x0UL) /*!< Even Frame Transfer */ + #define USBHSCORE_HC_CHAR_ODDFRM_OFRAME (0x1UL) /*!< Odd Frame Transfer */ + +/* CHDIS @Bit 30 : Channel Disable (ChDis) */ + #define USBHSCORE_HC_CHAR_CHDIS_Pos (30UL) /*!< Position of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Msk (0x1UL << USBHSCORE_HC_CHAR_CHDIS_Pos) /*!< Bit mask of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Min (0x0UL) /*!< Min enumerator value of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_Max (0x1UL) /*!< Max enumerator value of CHDIS field. */ + #define USBHSCORE_HC_CHAR_CHDIS_INACTIVE (0x0UL) /*!< Transmit/Recieve normal */ + #define USBHSCORE_HC_CHAR_CHDIS_ACTIVE (0x1UL) /*!< Stop transmitting/receiving data on channel */ + +/* CHENA @Bit 31 : Channel Enable (ChEna) */ + #define USBHSCORE_HC_CHAR_CHENA_Pos (31UL) /*!< Position of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Msk (0x1UL << USBHSCORE_HC_CHAR_CHENA_Pos) /*!< Bit mask of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Min (0x0UL) /*!< Min enumerator value of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_Max (0x1UL) /*!< Max enumerator value of CHENA field. */ + #define USBHSCORE_HC_CHAR_CHENA_DISABLED (0x0UL) /*!< If Scatter/Gather mode is enabled, indicates that the descriptor + structure is not yet ready. If Scatter/Gather mode is disabled, + indicates that the channel is disabled.*/ + #define USBHSCORE_HC_CHAR_CHENA_ENABLED (0x1UL) /*!< If Scatter/Gather mode is enabled, indicates that the descriptor + structure and data buffer with data is set up and this channel can + access the descriptor. If Scatter/Gather mode is disabled, indicates + that the channel is enabled.*/ + + +/* USBHSCORE_HC_INT: Host Channel Interrupt Register */ + #define USBHSCORE_HC_INT_ResetValue (0x00000000UL) /*!< Reset value of INT register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed (XferCompl) */ + #define USBHSCORE_HC_INT_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Msk (0x1UL << USBHSCORE_HC_INT_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_HC_INT_XFERCOMPL_INACTIVE (0x0UL) /*!< Transfer in progress or No Active Transfer */ + #define USBHSCORE_HC_INT_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer completed normally without any errors */ + +/* CHHLTD @Bit 1 : Channel Halted (ChHltd) */ + #define USBHSCORE_HC_INT_CHHLTD_Pos (1UL) /*!< Position of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Msk (0x1UL << USBHSCORE_HC_INT_CHHLTD_Pos) /*!< Bit mask of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Min (0x0UL) /*!< Min enumerator value of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_Max (0x1UL) /*!< Max enumerator value of CHHLTD field. */ + #define USBHSCORE_HC_INT_CHHLTD_INACTIVE (0x0UL) /*!< Channel not halted */ + #define USBHSCORE_HC_INT_CHHLTD_ACTIVE (0x1UL) /*!< Channel Halted */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_HC_INT_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Msk (0x1UL << USBHSCORE_HC_INT_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_HC_INT_AHBERR_INACTIVE (0x0UL) /*!< No AHB error */ + #define USBHSCORE_HC_INT_AHBERR_ACTIVE (0x1UL) /*!< AHB error during AHB read/write */ + +/* STALL @Bit 3 : STALL Response Received Interrupt (STALL) */ + #define USBHSCORE_HC_INT_STALL_Pos (3UL) /*!< Position of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Msk (0x1UL << USBHSCORE_HC_INT_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_HC_INT_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_HC_INT_STALL_INACTIVE (0x0UL) /*!< No Stall Response Received Interrupt */ + #define USBHSCORE_HC_INT_STALL_ACTIVE (0x1UL) /*!< Stall Response Received Interrupt */ + +/* NAK @Bit 4 : NAK Response Received Interrupt (NAK) */ + #define USBHSCORE_HC_INT_NAK_Pos (4UL) /*!< Position of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Msk (0x1UL << USBHSCORE_HC_INT_NAK_Pos) /*!< Bit mask of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Min (0x0UL) /*!< Min enumerator value of NAK field. */ + #define USBHSCORE_HC_INT_NAK_Max (0x1UL) /*!< Max enumerator value of NAK field. */ + #define USBHSCORE_HC_INT_NAK_INACTIVE (0x0UL) /*!< No NAK Response Received Interrupt */ + #define USBHSCORE_HC_INT_NAK_ACTIVE (0x1UL) /*!< NAK Response Received Interrupt */ + +/* ACK @Bit 5 : ACK Response Received/Transmitted Interrupt (ACK) */ + #define USBHSCORE_HC_INT_ACK_Pos (5UL) /*!< Position of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Msk (0x1UL << USBHSCORE_HC_INT_ACK_Pos) /*!< Bit mask of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Min (0x0UL) /*!< Min enumerator value of ACK field. */ + #define USBHSCORE_HC_INT_ACK_Max (0x1UL) /*!< Max enumerator value of ACK field. */ + #define USBHSCORE_HC_INT_ACK_INACTIVE (0x0UL) /*!< No ACK Response Received or Transmitted Interrupt */ + #define USBHSCORE_HC_INT_ACK_ACTIVE (0x1UL) /*!< ACK Response Received or Transmitted Interrup */ + +/* NYET @Bit 6 : NYET Response Received Interrupt (NYET) */ + #define USBHSCORE_HC_INT_NYET_Pos (6UL) /*!< Position of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Msk (0x1UL << USBHSCORE_HC_INT_NYET_Pos) /*!< Bit mask of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Min (0x0UL) /*!< Min enumerator value of NYET field. */ + #define USBHSCORE_HC_INT_NYET_Max (0x1UL) /*!< Max enumerator value of NYET field. */ + #define USBHSCORE_HC_INT_NYET_INACTIVE (0x0UL) /*!< No NYET Response Received Interrupt */ + #define USBHSCORE_HC_INT_NYET_ACTIVE (0x1UL) /*!< NYET Response Received Interrupt */ + +/* XACTERR @Bit 7 : Transaction Error (XactErr) */ + #define USBHSCORE_HC_INT_XACTERR_Pos (7UL) /*!< Position of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Msk (0x1UL << USBHSCORE_HC_INT_XACTERR_Pos) /*!< Bit mask of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Min (0x0UL) /*!< Min enumerator value of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_Max (0x1UL) /*!< Max enumerator value of XACTERR field. */ + #define USBHSCORE_HC_INT_XACTERR_INACTIVE (0x0UL) /*!< No Transaction Error */ + #define USBHSCORE_HC_INT_XACTERR_ACTIVE (0x1UL) /*!< Transaction Error */ + +/* BBLERR @Bit 8 : Babble Error (BblErr) */ + #define USBHSCORE_HC_INT_BBLERR_Pos (8UL) /*!< Position of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Msk (0x1UL << USBHSCORE_HC_INT_BBLERR_Pos) /*!< Bit mask of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Min (0x0UL) /*!< Min enumerator value of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_Max (0x1UL) /*!< Max enumerator value of BBLERR field. */ + #define USBHSCORE_HC_INT_BBLERR_INACTIVE (0x0UL) /*!< No Babble Error */ + #define USBHSCORE_HC_INT_BBLERR_ACTIVE (0x1UL) /*!< Babble Error */ + +/* FRMOVRUN @Bit 9 : Frame Overrun (FrmOvrun). */ + #define USBHSCORE_HC_INT_FRMOVRUN_Pos (9UL) /*!< Position of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Msk (0x1UL << USBHSCORE_HC_INT_FRMOVRUN_Pos) /*!< Bit mask of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Min (0x0UL) /*!< Min enumerator value of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_Max (0x1UL) /*!< Max enumerator value of FRMOVRUN field. */ + #define USBHSCORE_HC_INT_FRMOVRUN_INACTIVE (0x0UL) /*!< No Frame Overrun */ + #define USBHSCORE_HC_INT_FRMOVRUN_ACTIVE (0x1UL) /*!< Frame Overrun */ + +/* DATATGLERR @Bit 10 : (unspecified) */ + #define USBHSCORE_HC_INT_DATATGLERR_Pos (10UL) /*!< Position of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Msk (0x1UL << USBHSCORE_HC_INT_DATATGLERR_Pos) /*!< Bit mask of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Min (0x0UL) /*!< Min enumerator value of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_Max (0x1UL) /*!< Max enumerator value of DATATGLERR field. */ + #define USBHSCORE_HC_INT_DATATGLERR_INACTIVE (0x0UL) /*!< No Data Toggle Error */ + #define USBHSCORE_HC_INT_DATATGLERR_ACTIVE (0x1UL) /*!< Data Toggle Error */ + + +/* USBHSCORE_HC_INTMSK: Host Channel Interrupt Mask Register */ + #define USBHSCORE_HC_INTMSK_ResetValue (0x00000000UL) /*!< Reset value of INTMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK + field.*/ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Transfer Completed Mask */ + #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Mask */ + +/* CHHLTDMSK @Bit 1 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos (1UL) /*!< Position of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos) /*!< Bit mask of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Min (0x0UL) /*!< Min enumerator value of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Max (0x1UL) /*!< Max enumerator value of CHHLTDMSK field. */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_MASK (0x0UL) /*!< Channel Halted Mask */ + #define USBHSCORE_HC_INTMSK_CHHLTDMSK_NOMASK (0x1UL) /*!< No Channel Halted Mask */ + +/* AHBERRMSK @Bit 2 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_MASK (0x0UL) /*!< AHB Error Mask */ + #define USBHSCORE_HC_INTMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Mask */ + +/* STALLMSK @Bit 3 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Pos (3UL) /*!< Position of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_STALLMSK_Pos) /*!< Bit mask of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Min (0x0UL) /*!< Min enumerator value of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_Max (0x1UL) /*!< Max enumerator value of STALLMSK field. */ + #define USBHSCORE_HC_INTMSK_STALLMSK_MASK (0x0UL) /*!< Mask STALL Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_STALLMSK_NOMASK (0x1UL) /*!< No STALL Response Received Interrupt Mask */ + +/* NAKMSK @Bit 4 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Pos (4UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_HC_INTMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_NAKMSK_NOMASK (0x1UL) /*!< No NAK Response Received Interrupt Mask */ + +/* ACKMSK @Bit 5 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Pos (5UL) /*!< Position of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_ACKMSK_Pos) /*!< Bit mask of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Min (0x0UL) /*!< Min enumerator value of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_Max (0x1UL) /*!< Max enumerator value of ACKMSK field. */ + #define USBHSCORE_HC_INTMSK_ACKMSK_MASK (0x0UL) /*!< Mask ACK Response Received/Transmitted Interrupt */ + #define USBHSCORE_HC_INTMSK_ACKMSK_NOMASK (0x1UL) /*!< No ACK Response Received/Transmitted Interrupt Mask */ + +/* NYETMSK @Bit 6 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Pos (6UL) /*!< Position of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Min (0x0UL) /*!< Min enumerator value of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_Max (0x1UL) /*!< Max enumerator value of NYETMSK field. */ + #define USBHSCORE_HC_INTMSK_NYETMSK_MASK (0x0UL) /*!< Mask NYET Response Received Interrupt */ + #define USBHSCORE_HC_INTMSK_NYETMSK_NOMASK (0x1UL) /*!< No NYET Response Received Interrupt Mask */ + +/* XACTERRMSK @Bit 7 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Pos (7UL) /*!< Position of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XACTERRMSK_Pos) /*!< Bit mask of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Min (0x0UL) /*!< Min enumerator value of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_Max (0x1UL) /*!< Max enumerator value of XACTERRMSK field. */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_MASK (0x0UL) /*!< Mask Transaction Error */ + #define USBHSCORE_HC_INTMSK_XACTERRMSK_NOMASK (0x1UL) /*!< No Transaction Error Mask */ + +/* BBLERRMSK @Bit 8 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Pos (8UL) /*!< Position of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_BBLERRMSK_Pos) /*!< Bit mask of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Min (0x0UL) /*!< Min enumerator value of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_Max (0x1UL) /*!< Max enumerator value of BBLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_MASK (0x0UL) /*!< Mask Babble Error */ + #define USBHSCORE_HC_INTMSK_BBLERRMSK_NOMASK (0x1UL) /*!< No Babble Error Mask */ + +/* FRMOVRUNMSK @Bit 9 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos (9UL) /*!< Position of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos) /*!< Bit mask of FRMOVRUNMSK + field.*/ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Min (0x0UL) /*!< Min enumerator value of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Max (0x1UL) /*!< Max enumerator value of FRMOVRUNMSK field. */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_MASK (0x0UL) /*!< Mask Overrun Mask */ + #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_NOMASK (0x1UL) /*!< No Frame Overrun Mask */ + +/* DATATGLERRMSK @Bit 10 : (unspecified) */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos (10UL) /*!< Position of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos) /*!< Bit mask of DATATGLERRMSK + field.*/ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Min (0x0UL) /*!< Min enumerator value of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Max (0x1UL) /*!< Max enumerator value of DATATGLERRMSK field. */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_MASK (0x0UL) /*!< Mask Data Toggle Error */ + #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_NOMASK (0x1UL) /*!< No Data Toggle Error Mask */ + + +/* USBHSCORE_HC_TSIZ: Host Channel Transfer Size Register */ + #define USBHSCORE_HC_TSIZ_ResetValue (0x00000000UL) /*!< Reset value of TSIZ register. */ + +/* XFERSIZE @Bits 0..18 : Non-Scatter/Gather DMA Mode: */ + #define USBHSCORE_HC_TSIZ_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_HC_TSIZ_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_HC_TSIZ_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Non-Scatter/Gather DMA Mode: */ + #define USBHSCORE_HC_TSIZ_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_HC_TSIZ_PKTCNT_Msk (0x3FFUL << USBHSCORE_HC_TSIZ_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* PID @Bits 29..30 : PID (Pid) */ + #define USBHSCORE_HC_TSIZ_PID_Pos (29UL) /*!< Position of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Msk (0x3UL << USBHSCORE_HC_TSIZ_PID_Pos) /*!< Bit mask of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Min (0x0UL) /*!< Min enumerator value of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_Max (0x3UL) /*!< Max enumerator value of PID field. */ + #define USBHSCORE_HC_TSIZ_PID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_HC_TSIZ_PID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_HC_TSIZ_PID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_HC_TSIZ_PID_MDATA (0x3UL) /*!< MDATA (non-control)/SETUP (control) */ + +/* DOPNG @Bit 31 : Do Ping (DoPng) */ + #define USBHSCORE_HC_TSIZ_DOPNG_Pos (31UL) /*!< Position of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Msk (0x1UL << USBHSCORE_HC_TSIZ_DOPNG_Pos) /*!< Bit mask of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Min (0x0UL) /*!< Min enumerator value of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_Max (0x1UL) /*!< Max enumerator value of DOPNG field. */ + #define USBHSCORE_HC_TSIZ_DOPNG_NOPING (0x0UL) /*!< No ping protocol */ + #define USBHSCORE_HC_TSIZ_DOPNG_PING (0x1UL) /*!< Ping protocol */ + + +/* USBHSCORE_HC_DMA: Host Channel DMA Address Register */ + #define USBHSCORE_HC_DMA_ResetValue (0x00000000UL) /*!< Reset value of DMA register. */ + +/* DMAADDR @Bits 0..31 : In Buffer DMA Mode: */ + #define USBHSCORE_HC_DMA_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_HC_DMA_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_HC_DMA_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + + +/* ============================================== Struct USBHSCORE_DWCOTGDFIFO =============================================== */ +/** + * @brief DWCOTGDFIFO [USBHSCORE_DWCOTGDFIFO] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[1024]; /*!< (@ 0x00000000) Data FIFO Access Register Map 0 */ +} NRF_USBHSCORE_DWCOTGDFIFO_Type; /*!< Size = 4096 (0x1000) */ + #define USBHSCORE_DWCOTGDFIFO_MaxCount (16UL) /*!< Size of DWCOTGDFIFO[16] array. */ + #define USBHSCORE_DWCOTGDFIFO_MaxIndex (15UL) /*!< Max index of DWCOTGDFIFO[16] array. */ + #define USBHSCORE_DWCOTGDFIFO_MinIndex (0UL) /*!< Min index of DWCOTGDFIFO[16] array. */ + + +/* ======================================== Struct USBHSCORE_DWCOTGDFIFODIRECTACCESS ========================================= */ +/** + * @brief DWCOTGDFIFODIRECTACCESS [USBHSCORE_DWCOTGDFIFODIRECTACCESS] (unspecified) + */ +typedef struct { + __IOM uint32_t DATA[32768]; /*!< (@ 0x00000000) Data FIFO Direct Access Register Map */ +} NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type; /*!< Size = 131072 (0x20000) */ + +/* ==================================================== Struct USBHSCORE ===================================================== */ +/** + * @brief USBHSCORE + */ + typedef struct { /*!< USBHSCORE Structure */ + __IOM uint32_t GOTGCTL; /*!< (@ 0x00000000) Control and Status Register */ + __IOM uint32_t GOTGINT; /*!< (@ 0x00000004) Interrupt Register */ + __IOM uint32_t GAHBCFG; /*!< (@ 0x00000008) AHB Configuration Register */ + __IOM uint32_t GUSBCFG; /*!< (@ 0x0000000C) USB Configuration Register */ + __IOM uint32_t GRSTCTL; /*!< (@ 0x00000010) Reset Register */ + __IOM uint32_t GINTSTS; /*!< (@ 0x00000014) Interrupt Register */ + __IOM uint32_t GINTMSK; /*!< (@ 0x00000018) Interrupt Mask Register */ + __IOM uint32_t GRXSTSR; /*!< (@ 0x0000001C) Receive Status Debug Read Register */ + __IOM uint32_t GRXSTSP; /*!< (@ 0x00000020) Receive Status Read/Pop Register */ + __IOM uint32_t GRXFSIZ; /*!< (@ 0x00000024) Receive FIFO Size Register */ + __IOM uint32_t GNPTXFSIZ; /*!< (@ 0x00000028) Non-periodic Transmit FIFO Size Register */ + __IOM uint32_t GNPTXSTS; /*!< (@ 0x0000002C) Non-periodic Transmit FIFO/Queue Status Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GGPIO; /*!< (@ 0x00000038) General Purpose Input/Output Register */ + __IOM uint32_t GUID; /*!< (@ 0x0000003C) User ID Register */ + __IOM uint32_t GSNPSID; /*!< (@ 0x00000040) Synopsys ID Register */ + __IOM uint32_t GHWCFG1; /*!< (@ 0x00000044) User Hardware Configuration 1 Register */ + __IOM uint32_t GHWCFG2; /*!< (@ 0x00000048) User Hardware Configuration 2 Register */ + __IOM uint32_t GHWCFG3; /*!< (@ 0x0000004C) User Hardware Configuration 3 Register */ + __IOM uint32_t GHWCFG4; /*!< (@ 0x00000050) User Hardware Configuration 4 Register */ + __IOM uint32_t GLPMCFG; /*!< (@ 0x00000054) LPM Config Register */ + __IOM uint32_t GPWRDN; /*!< (@ 0x00000058) Global Power Down Register */ + __IOM uint32_t GDFIFOCFG; /*!< (@ 0x0000005C) Global DFIFO Configuration Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t GINTMSK2; /*!< (@ 0x00000068) Interrupt Mask Register 2 */ + __IOM uint32_t GINTSTS2; /*!< (@ 0x0000006C) Interrupt Register 2 */ + __IM uint32_t RESERVED2[36]; + __IOM uint32_t HPTXFSIZ; /*!< (@ 0x00000100) Host Periodic Transmit FIFO Size Register */ + __IOM uint32_t DIEPTXF[8]; /*!< (@ 0x00000104) Device IN Endpoint Transmit FIFO Size Register */ + __IM uint32_t RESERVED3[183]; + __IOM uint32_t HCFG; /*!< (@ 0x00000400) Host Configuration Register */ + __IOM uint32_t HFIR; /*!< (@ 0x00000404) Host Frame Interval Register */ + __IOM uint32_t HFNUM; /*!< (@ 0x00000408) Host Frame Number/Frame Time Remaining Register */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t HAINT; /*!< (@ 0x00000414) Host All Channels Interrupt Register */ + __IOM uint32_t HAINTMSK; /*!< (@ 0x00000418) Host All Channels Interrupt Mask Register */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t HPRT; /*!< (@ 0x00000440) Host Port Control and Status Register */ + __IM uint32_t RESERVED6[47]; + __IOM NRF_USBHSCORE_HC_Type HC[16]; /*!< (@ 0x00000500) (unspecified) */ + __IM uint32_t RESERVED7[96]; + __IOM uint32_t DCFG; /*!< (@ 0x00000800) Device Configuration Register */ + __IOM uint32_t DCTL; /*!< (@ 0x00000804) Device Control Register */ + __IOM uint32_t DSTS; /*!< (@ 0x00000808) Device Status Register */ + __IM uint32_t RESERVED8; + __IOM uint32_t DIEPMSK; /*!< (@ 0x00000810) Device IN Endpoint Common Interrupt Mask Register */ + __IOM uint32_t DOEPMSK; /*!< (@ 0x00000814) Device OUT Endpoint Common Interrupt Mask Register */ + __IOM uint32_t DAINT; /*!< (@ 0x00000818) Device All Endpoints Interrupt Register */ + __IOM uint32_t DAINTMSK; /*!< (@ 0x0000081C) Device All Endpoints Interrupt Mask Register */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t DVBUSDIS; /*!< (@ 0x00000828) Device VBUS Discharge Time Register */ + __IOM uint32_t DVBUSPULSE; /*!< (@ 0x0000082C) Device VBUS Pulsing Time Register */ + __IOM uint32_t DTHRCTL; /*!< (@ 0x00000830) Device Threshold Control Register */ + __IOM uint32_t DIEPEMPMSK; /*!< (@ 0x00000834) Device IN Endpoint FIFO Empty Interrupt Mask Register */ + __IM uint32_t RESERVED10[50]; + __IOM uint32_t DIEPCTL0; /*!< (@ 0x00000900) Device Control IN Endpoint 0 Control Register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DIEPINT0; /*!< (@ 0x00000908) Device IN Endpoint 0 Interrupt Register */ + __IM uint32_t RESERVED12; + __IOM uint32_t DIEPTSIZ0; /*!< (@ 0x00000910) Device IN Endpoint 0 Transfer Size Register */ + __IOM uint32_t DIEPDMA0; /*!< (@ 0x00000914) Device IN Endpoint 0 DMA Address Register */ + __IOM uint32_t DTXFSTS0; /*!< (@ 0x00000918) Device IN Endpoint Transmit FIFO Status Register 0 */ + __IM uint32_t RESERVED13; + __IOM uint32_t DIEPCTL1; /*!< (@ 0x00000920) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED14; + __IOM uint32_t DIEPINT1; /*!< (@ 0x00000928) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED15; + __IOM uint32_t DIEPTSIZ1; /*!< (@ 0x00000930) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA1; /*!< (@ 0x00000934) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS1; /*!< (@ 0x00000938) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED16; + __IOM uint32_t DIEPCTL2; /*!< (@ 0x00000940) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED17; + __IOM uint32_t DIEPINT2; /*!< (@ 0x00000948) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED18; + __IOM uint32_t DIEPTSIZ2; /*!< (@ 0x00000950) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA2; /*!< (@ 0x00000954) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS2; /*!< (@ 0x00000958) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED19; + __IOM uint32_t DIEPCTL3; /*!< (@ 0x00000960) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED20; + __IOM uint32_t DIEPINT3; /*!< (@ 0x00000968) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED21; + __IOM uint32_t DIEPTSIZ3; /*!< (@ 0x00000970) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA3; /*!< (@ 0x00000974) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS3; /*!< (@ 0x00000978) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED22; + __IOM uint32_t DIEPCTL4; /*!< (@ 0x00000980) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED23; + __IOM uint32_t DIEPINT4; /*!< (@ 0x00000988) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED24; + __IOM uint32_t DIEPTSIZ4; /*!< (@ 0x00000990) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA4; /*!< (@ 0x00000994) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS4; /*!< (@ 0x00000998) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED25; + __IOM uint32_t DIEPCTL5; /*!< (@ 0x000009A0) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED26; + __IOM uint32_t DIEPINT5; /*!< (@ 0x000009A8) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED27; + __IOM uint32_t DIEPTSIZ5; /*!< (@ 0x000009B0) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA5; /*!< (@ 0x000009B4) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS5; /*!< (@ 0x000009B8) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED28; + __IOM uint32_t DIEPCTL6; /*!< (@ 0x000009C0) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED29; + __IOM uint32_t DIEPINT6; /*!< (@ 0x000009C8) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED30; + __IOM uint32_t DIEPTSIZ6; /*!< (@ 0x000009D0) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA6; /*!< (@ 0x000009D4) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS6; /*!< (@ 0x000009D8) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED31; + __IOM uint32_t DIEPCTL7; /*!< (@ 0x000009E0) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED32; + __IOM uint32_t DIEPINT7; /*!< (@ 0x000009E8) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED33; + __IOM uint32_t DIEPTSIZ7; /*!< (@ 0x000009F0) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA7; /*!< (@ 0x000009F4) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS7; /*!< (@ 0x000009F8) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED34; + __IOM uint32_t DIEPCTL8; /*!< (@ 0x00000A00) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED35; + __IOM uint32_t DIEPINT8; /*!< (@ 0x00000A08) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED36; + __IOM uint32_t DIEPTSIZ8; /*!< (@ 0x00000A10) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA8; /*!< (@ 0x00000A14) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS8; /*!< (@ 0x00000A18) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED37; + __IOM uint32_t DIEPCTL9; /*!< (@ 0x00000A20) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED38; + __IOM uint32_t DIEPINT9; /*!< (@ 0x00000A28) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED39; + __IOM uint32_t DIEPTSIZ9; /*!< (@ 0x00000A30) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA9; /*!< (@ 0x00000A34) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS9; /*!< (@ 0x00000A38) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED40; + __IOM uint32_t DIEPCTL10; /*!< (@ 0x00000A40) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED41; + __IOM uint32_t DIEPINT10; /*!< (@ 0x00000A48) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED42; + __IOM uint32_t DIEPTSIZ10; /*!< (@ 0x00000A50) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA10; /*!< (@ 0x00000A54) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS10; /*!< (@ 0x00000A58) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED43; + __IOM uint32_t DIEPCTL11; /*!< (@ 0x00000A60) Device Control IN Endpoint Control Register */ + __IM uint32_t RESERVED44; + __IOM uint32_t DIEPINT11; /*!< (@ 0x00000A68) Device IN Endpoint Interrupt Register */ + __IM uint32_t RESERVED45; + __IOM uint32_t DIEPTSIZ11; /*!< (@ 0x00000A70) Device IN Endpoint Transfer Size Register */ + __IOM uint32_t DIEPDMA11; /*!< (@ 0x00000A74) Device IN Endpoint DMA Address Register */ + __IOM uint32_t DTXFSTS11; /*!< (@ 0x00000A78) Device IN Endpoint Transmit FIFO Status Register */ + __IM uint32_t RESERVED46[33]; + __IOM uint32_t DOEPCTL0; /*!< (@ 0x00000B00) Device Control OUT Endpoint 0 Control Register */ + __IM uint32_t RESERVED47; + __IOM uint32_t DOEPINT0; /*!< (@ 0x00000B08) Device OUT Endpoint 0 Interrupt Register */ + __IM uint32_t RESERVED48; + __IOM uint32_t DOEPTSIZ0; /*!< (@ 0x00000B10) Device OUT Endpoint 0 Transfer Size Register */ + __IOM uint32_t DOEPDMA0; /*!< (@ 0x00000B14) Device OUT Endpoint 0 DMA Address Register */ + __IM uint32_t RESERVED49[2]; + __IOM uint32_t DOEPCTL1; /*!< (@ 0x00000B20) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED50; + __IOM uint32_t DOEPINT1; /*!< (@ 0x00000B28) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED51; + __IOM uint32_t DOEPTSIZ1; /*!< (@ 0x00000B30) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA1; /*!< (@ 0x00000B34) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED52[2]; + __IOM uint32_t DOEPCTL2; /*!< (@ 0x00000B40) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED53; + __IOM uint32_t DOEPINT2; /*!< (@ 0x00000B48) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED54; + __IOM uint32_t DOEPTSIZ2; /*!< (@ 0x00000B50) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA2; /*!< (@ 0x00000B54) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED55[2]; + __IOM uint32_t DOEPCTL3; /*!< (@ 0x00000B60) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED56; + __IOM uint32_t DOEPINT3; /*!< (@ 0x00000B68) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED57; + __IOM uint32_t DOEPTSIZ3; /*!< (@ 0x00000B70) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA3; /*!< (@ 0x00000B74) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED58[2]; + __IOM uint32_t DOEPCTL4; /*!< (@ 0x00000B80) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED59; + __IOM uint32_t DOEPINT4; /*!< (@ 0x00000B88) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED60; + __IOM uint32_t DOEPTSIZ4; /*!< (@ 0x00000B90) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA4; /*!< (@ 0x00000B94) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED61[2]; + __IOM uint32_t DOEPCTL5; /*!< (@ 0x00000BA0) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED62; + __IOM uint32_t DOEPINT5; /*!< (@ 0x00000BA8) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED63; + __IOM uint32_t DOEPTSIZ5; /*!< (@ 0x00000BB0) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA5; /*!< (@ 0x00000BB4) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED64[50]; + __IOM uint32_t DOEPCTL12; /*!< (@ 0x00000C80) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED65; + __IOM uint32_t DOEPINT12; /*!< (@ 0x00000C88) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED66; + __IOM uint32_t DOEPTSIZ12; /*!< (@ 0x00000C90) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA12; /*!< (@ 0x00000C94) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED67[2]; + __IOM uint32_t DOEPCTL13; /*!< (@ 0x00000CA0) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED68; + __IOM uint32_t DOEPINT13; /*!< (@ 0x00000CA8) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED69; + __IOM uint32_t DOEPTSIZ13; /*!< (@ 0x00000CB0) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA13; /*!< (@ 0x00000CB4) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED70[2]; + __IOM uint32_t DOEPCTL14; /*!< (@ 0x00000CC0) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED71; + __IOM uint32_t DOEPINT14; /*!< (@ 0x00000CC8) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED72; + __IOM uint32_t DOEPTSIZ14; /*!< (@ 0x00000CD0) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA14; /*!< (@ 0x00000CD4) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED73[2]; + __IOM uint32_t DOEPCTL15; /*!< (@ 0x00000CE0) Device Control OUT Endpoint Control Register */ + __IM uint32_t RESERVED74; + __IOM uint32_t DOEPINT15; /*!< (@ 0x00000CE8) Device OUT Endpoint Interrupt Register */ + __IM uint32_t RESERVED75; + __IOM uint32_t DOEPTSIZ15; /*!< (@ 0x00000CF0) Device OUT Endpoint Transfer Size Register */ + __IOM uint32_t DOEPDMA15; /*!< (@ 0x00000CF4) Device OUT Endpoint DMA Address Register */ + __IM uint32_t RESERVED76[66]; + __IOM uint32_t PCGCCTL; /*!< (@ 0x00000E00) Power and Clock Gating Control Register */ + __IM uint32_t RESERVED77[63]; + __IOM uint32_t GSTARFXDIS; /*!< (@ 0x00000F00) Global STAR Fix Disable Register */ + __IM uint32_t RESERVED78[63]; + __IOM NRF_USBHSCORE_DWCOTGDFIFO_Type DWCOTGDFIFO[16]; /*!< (@ 0x00001000) (unspecified) */ + __IM uint32_t RESERVED79[15360]; + __IOM NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type DWCOTGDFIFODIRECTACCESS; /*!< (@ 0x00020000) (unspecified) */ + } NRF_USBHSCORE_Type; /*!< Size = 262144 (0x40000) */ + +/* USBHSCORE_GOTGCTL: Control and Status Register */ + #define USBHSCORE_GOTGCTL_ResetValue (0x000D0000UL) /*!< Reset value of GOTGCTL register. */ + +/* VBVALIDOVEN @Bit 2 : Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos (2UL) /*!< Position of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos) /*!< Bit mask of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of VBVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_DISABLED (0x0UL) /*!< Override is disabled and bvalid signal from the respective PHY + selected is used internally by the controller*/ + #define USBHSCORE_GOTGCTL_VBVALIDOVEN_ENABLED (0x1UL) /*!< The vbus-valid signal received from the PHY is overridden with + GOTGCTL.VbvalidOvVal*/ + +/* VBVALIDOVVAL @Bit 3 : Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos (3UL) /*!< Position of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos) /*!< Bit mask of VBVALIDOVVAL field.*/ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of VBVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET0 (0x0UL) /*!< vbusvalid value when GOTGCTL.VbvalidOvEn = 1 */ + #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET1 (0x1UL) /*!< vbusvalid value when GOTGCTL.VbvalidOvEn is 1 */ + +/* AVALIDOVEN @Bit 4 : Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Pos (4UL) /*!< Position of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVEN_Pos) /*!< Bit mask of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of AVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_DISABLED (0x0UL) /*!< Derive AValid from PHY */ + #define USBHSCORE_GOTGCTL_AVALIDOVEN_ENABLED (0x1UL) /*!< Derive Avalid from GOTGCTL.AvalidOvVal */ + +/* AVALIDOVVAL @Bit 5 : Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal) */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos (5UL) /*!< Position of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos) /*!< Bit mask of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of AVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE0 (0x0UL) /*!< Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1 */ + #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE1 (0x1UL) /*!< Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1 */ + +/* BVALIDOVEN @Bit 6 : Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Pos (6UL) /*!< Position of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVEN_Pos) /*!< Bit mask of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Min (0x0UL) /*!< Min enumerator value of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_Max (0x1UL) /*!< Max enumerator value of BVALIDOVEN field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_DISABLED (0x0UL) /*!< Override is disabled and bvalid signal from the respective PHY + selected is used internally by the core*/ + #define USBHSCORE_GOTGCTL_BVALIDOVEN_ENABLED (0x1UL) /*!< Internally Bvalid received from the PHY is overridden with + GOTGCTL.BvalidOvVal*/ + +/* BVALIDOVVAL @Bit 7 : Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos (7UL) /*!< Position of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos) /*!< Bit mask of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of BVALIDOVVAL field. */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE0 (0x0UL) /*!< Bvalid value when GOTGCTL.BvalidOvEn =1 */ + #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE1 (0x1UL) /*!< Bvalid value when GOTGCTL.BvalidOvEn =1 */ + +/* DBNCEFLTRBYPASS @Bit 15 : Mode: Host and Device. Debounce Filter Bypass */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos (15UL) /*!< Position of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos) /*!< Bit mask of + DBNCEFLTRBYPASS field.*/ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Min (0x0UL) /*!< Min enumerator value of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Max (0x1UL) /*!< Max enumerator value of DBNCEFLTRBYPASS field. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_DISABLED (0x0UL) /*!< Debounce Filter Bypass is disabled. */ + #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_ENABLED (0x1UL) /*!< Debounce Filter Bypass is enabled. */ + +/* CONIDSTS @Bit 16 : Mode: Host and Device. Connector ID Status (ConIDSts) */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Pos (16UL) /*!< Position of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Msk (0x1UL << USBHSCORE_GOTGCTL_CONIDSTS_Pos) /*!< Bit mask of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Min (0x0UL) /*!< Min enumerator value of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_Max (0x1UL) /*!< Max enumerator value of CONIDSTS field. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_MODEA (0x0UL) /*!< The core is in A-Device mode. */ + #define USBHSCORE_GOTGCTL_CONIDSTS_MODEB (0x1UL) /*!< The core is in B-Device mode. */ + +/* DBNCTIME @Bit 17 : Mode: Host only. Long/Short Debounce Time (DbncTime) */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Pos (17UL) /*!< Position of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCTIME_Pos) /*!< Bit mask of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Min (0x0UL) /*!< Min enumerator value of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_Max (0x1UL) /*!< Max enumerator value of DBNCTIME field. */ + #define USBHSCORE_GOTGCTL_DBNCTIME_LONG (0x0UL) /*!< Long debounce time, used for physical connections (100 ms + 2.5 + micro-sec)*/ + #define USBHSCORE_GOTGCTL_DBNCTIME_SHORT (0x1UL) /*!< Short debounce time, used for soft connections (2.5 micro-sec) */ + +/* ASESVLD @Bit 18 : Mode: Host only. A-Session Valid (ASesVld) */ + #define USBHSCORE_GOTGCTL_ASESVLD_Pos (18UL) /*!< Position of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_ASESVLD_Pos) /*!< Bit mask of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Min (0x0UL) /*!< Min enumerator value of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_Max (0x1UL) /*!< Max enumerator value of ASESVLD field. */ + #define USBHSCORE_GOTGCTL_ASESVLD_NOTVALID (0x0UL) /*!< A-session is not valid. */ + #define USBHSCORE_GOTGCTL_ASESVLD_VALID (0x1UL) /*!< A-session is valid. */ + +/* BSESVLD @Bit 19 : Mode: Device only. B-Session Valid (BSesVld) */ + #define USBHSCORE_GOTGCTL_BSESVLD_Pos (19UL) /*!< Position of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_BSESVLD_Pos) /*!< Bit mask of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Min (0x0UL) /*!< Min enumerator value of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_Max (0x1UL) /*!< Max enumerator value of BSESVLD field. */ + #define USBHSCORE_GOTGCTL_BSESVLD_NOTVALID (0x0UL) /*!< B-session is not valid. */ + #define USBHSCORE_GOTGCTL_BSESVLD_VALID (0x1UL) /*!< B-session is valid. */ + +/* OTGVER @Bit 20 : OTG Version (OTGVer) */ + #define USBHSCORE_GOTGCTL_OTGVER_Pos (20UL) /*!< Position of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Msk (0x1UL << USBHSCORE_GOTGCTL_OTGVER_Pos) /*!< Bit mask of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Min (0x0UL) /*!< Min enumerator value of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_Max (0x1UL) /*!< Max enumerator value of OTGVER field. */ + #define USBHSCORE_GOTGCTL_OTGVER_VER13 (0x0UL) /*!< Supports OTG Version 1.3 */ + #define USBHSCORE_GOTGCTL_OTGVER_VER20 (0x1UL) /*!< Supports OTG Version 2.0 */ + +/* CURMOD @Bit 21 : Current Mode of Operation (CurMod) */ + #define USBHSCORE_GOTGCTL_CURMOD_Pos (21UL) /*!< Position of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Msk (0x1UL << USBHSCORE_GOTGCTL_CURMOD_Pos) /*!< Bit mask of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Min (0x0UL) /*!< Min enumerator value of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_Max (0x1UL) /*!< Max enumerator value of CURMOD field. */ + #define USBHSCORE_GOTGCTL_CURMOD_DEVICEMODE (0x0UL) /*!< Current mode is device mode. */ + #define USBHSCORE_GOTGCTL_CURMOD_HOSTMODE (0x1UL) /*!< Current mode is host mode. */ + +/* MULTVALIDBC @Bits 22..26 : Mode: Host and Device. Multi Valued ID pin (MultValIdBC) */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Pos (22UL) /*!< Position of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GOTGCTL_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Min (0x1UL) /*!< Min enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_Max (0x10UL) /*!< Max enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_C (0x01UL) /*!< B-Device connected to ACA. VBUS is on. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_B (0x02UL) /*!< B-Device connected to ACA. VBUS is off. */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_A (0x04UL) /*!< A-Device connected to ACA */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_GND (0x08UL) /*!< A-Device not connected to ACA */ + #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_FLOAT (0x10UL) /*!< B-Device not connected to ACA */ + +/* CHIRPEN @Bit 27 : Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending + an actual Chirp 'K' signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, + this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always + operates at High Speed and High speed chirp is not used */ + + #define USBHSCORE_GOTGCTL_CHIRPEN_Pos (27UL) /*!< Position of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Msk (0x1UL << USBHSCORE_GOTGCTL_CHIRPEN_Pos) /*!< Bit mask of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Min (0x0UL) /*!< Min enumerator value of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_Max (0x1UL) /*!< Max enumerator value of CHIRPEN field. */ + #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRP_DISABLE (0x0UL) /*!< The controller does not assert chirp_on before sending an actual + Chirp 'K' signal on USB.*/ + #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRP_ENABLE (0x1UL) /*!< The controller asserts chirp_on before sending an actual Chirp 'K' + signal on USB.*/ + + +/* USBHSCORE_GOTGINT: Interrupt Register */ + #define USBHSCORE_GOTGINT_ResetValue (0x00000000UL) /*!< Reset value of GOTGINT register. */ + +/* SESENDDET @Bit 2 : Mode: Host and Device. Session End Detected (SesEndDet) */ + #define USBHSCORE_GOTGINT_SESENDDET_Pos (2UL) /*!< Position of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Msk (0x1UL << USBHSCORE_GOTGINT_SESENDDET_Pos) /*!< Bit mask of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Min (0x0UL) /*!< Min enumerator value of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_Max (0x1UL) /*!< Max enumerator value of SESENDDET field. */ + #define USBHSCORE_GOTGINT_SESENDDET_INACTIVE (0x0UL) /*!< Session is Active */ + #define USBHSCORE_GOTGINT_SESENDDET_ACTIVE (0x1UL) /*!< SessionEnd utmiotg_bvalid signal is deasserted */ + +/* SESREQSUCSTSCHNG @Bit 8 : Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos (8UL) /*!< Position of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos) /*!< Bit mask of + SESREQSUCSTSCHNG field.*/ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of SESREQSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_INACTIVE (0x0UL) /*!< No Change in Session Request Status */ + #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_ACTIVE (0x1UL) /*!< Session Request Status has changed */ + +/* HSTNEGSUCSTSCHNG @Bit 9 : Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos (9UL) /*!< Position of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos) /*!< Bit mask of + HSTNEGSUCSTSCHNG field.*/ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of HSTNEGSUCSTSCHNG field. */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_INACTIVE (0x0UL) /*!< No Change */ + #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_ACTIVE (0x1UL) /*!< Host Negotiation Status Change */ + +/* HSTNEGDET @Bit 17 : Mode:Host and Device. Host Negotiation Detected (HstNegDet) */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Pos (17UL) /*!< Position of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGDET_Pos) /*!< Bit mask of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Min (0x0UL) /*!< Min enumerator value of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_Max (0x1UL) /*!< Max enumerator value of HSTNEGDET field. */ + #define USBHSCORE_GOTGINT_HSTNEGDET_INACTIVE (0x0UL) /*!< No Active HNP Request */ + #define USBHSCORE_GOTGINT_HSTNEGDET_ACTIVE (0x1UL) /*!< Active HNP request detected */ + +/* ADEVTOUTCHG @Bit 18 : Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos (18UL) /*!< Position of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Msk (0x1UL << USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos) /*!< Bit mask of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Min (0x0UL) /*!< Min enumerator value of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Max (0x1UL) /*!< Max enumerator value of ADEVTOUTCHG field. */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_INACTIVE (0x0UL) /*!< No A-Device Timeout */ + #define USBHSCORE_GOTGINT_ADEVTOUTCHG_ACTIVE (0x1UL) /*!< A-Device Timeout */ + +/* DBNCEDONE @Bit 19 : Mode: Host only. Debounce Done (DbnceDone) */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Pos (19UL) /*!< Position of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Msk (0x1UL << USBHSCORE_GOTGINT_DBNCEDONE_Pos) /*!< Bit mask of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Min (0x0UL) /*!< Min enumerator value of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_Max (0x1UL) /*!< Max enumerator value of DBNCEDONE field. */ + #define USBHSCORE_GOTGINT_DBNCEDONE_INACTIVE (0x0UL) /*!< After Connect waiting for Debounce to complete */ + #define USBHSCORE_GOTGINT_DBNCEDONE_ACTIVE (0x1UL) /*!< Debounce completed */ + +/* MULTVALIPCHNG @Bit 20 : This bit when set indicates that there is a change in the value of at least one ACA pin value. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos (20UL) /*!< Position of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos) /*!< Bit mask of MULTVALIPCHNG + field.*/ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Min (0x0UL) /*!< Min enumerator value of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Max (0x1UL) /*!< Max enumerator value of MULTVALIPCHNG field. */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_NO_ACA_PIN_CHANGE (0x0UL) /*!< Indicates there is no change in ACA pin value */ + #define USBHSCORE_GOTGINT_MULTVALIPCHNG_ACA_PIN_CHANGE (0x1UL) /*!< Indicates there is a change in ACA pin value */ + + +/* USBHSCORE_GAHBCFG: AHB Configuration Register */ + #define USBHSCORE_GAHBCFG_ResetValue (0x00000000UL) /*!< Reset value of GAHBCFG register. */ + +/* GLBLINTRMSK @Bit 0 : Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos (0UL) /*!< Position of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Msk (0x1UL << USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos) /*!< Bit mask of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Min (0x0UL) /*!< Min enumerator value of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Max (0x1UL) /*!< Max enumerator value of GLBLINTRMSK field. */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_MASK (0x0UL) /*!< Mask the interrupt assertion to the application */ + #define USBHSCORE_GAHBCFG_GLBLINTRMSK_NOMASK (0x1UL) /*!< Unmask the interrupt assertion to the application. */ + +/* HBSTLEN @Bits 1..4 : Mode: Host and device. Burst Length/Type (HBstLen) */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Pos (1UL) /*!< Position of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Msk (0xFUL << USBHSCORE_GAHBCFG_HBSTLEN_Pos) /*!< Bit mask of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Min (0x0UL) /*!< Min enumerator value of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_Max (0x8UL) /*!< Max enumerator value of HBSTLEN field. */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD1ORSINGLE (0x0UL) /*!< 1 word or single */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD4ORINCR (0x1UL) /*!< 4 words or INCR */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD8 (0x2UL) /*!< 8 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD16ORINCR4 (0x3UL) /*!< 16 words or INCR4 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD32 (0x4UL) /*!< 32 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD64ORINCR8 (0x5UL) /*!< 64 words or INCR8 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD128 (0x6UL) /*!< 128 words */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORD256ORINCR16 (0x7UL) /*!< 256 words or INCR16 */ + #define USBHSCORE_GAHBCFG_HBSTLEN_WORDX (0x8UL) /*!< Others reserved */ + +/* DMAEN @Bit 5 : Mode: Host and device. DMA Enable (DMAEn) */ + #define USBHSCORE_GAHBCFG_DMAEN_Pos (5UL) /*!< Position of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Msk (0x1UL << USBHSCORE_GAHBCFG_DMAEN_Pos) /*!< Bit mask of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Min (0x0UL) /*!< Min enumerator value of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_Max (0x1UL) /*!< Max enumerator value of DMAEN field. */ + #define USBHSCORE_GAHBCFG_DMAEN_SLAVEMODE (0x0UL) /*!< Core operates in Slave mode */ + #define USBHSCORE_GAHBCFG_DMAEN_DMAMODE (0x1UL) /*!< Core operates in a DMA mode */ + +/* NPTXFEMPLVL @Bit 7 : Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos (7UL) /*!< Position of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Msk (0x1UL << USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos) /*!< Bit mask of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Min (0x0UL) /*!< Min enumerator value of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Max (0x1UL) /*!< Max enumerator value of NPTXFEMPLVL field. */ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (0x0UL) /*!< DIEPINTn.TxFEmp interrupt indicates that the Non-Periodic TxFIFO + is half empty or that the IN Endpoint TxFIFO is half empty.*/ + #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_EMPTY (0x1UL) /*!< GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is + completely empty or that the IN Endpoint TxFIFO is completely empty.*/ + +/* REMMEMSUPP @Bit 21 : Mode: Host and Device. Remote Memory Support (RemMemSupp) */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Pos (21UL) /*!< Position of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Msk (0x1UL << USBHSCORE_GAHBCFG_REMMEMSUPP_Pos) /*!< Bit mask of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Min (0x0UL) /*!< Min enumerator value of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_Max (0x1UL) /*!< Max enumerator value of REMMEMSUPP field. */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_DISABLED (0x0UL) /*!< Remote Memory Support Feature disabled */ + #define USBHSCORE_GAHBCFG_REMMEMSUPP_ENABLED (0x1UL) /*!< Remote Memory Support Feature enabled */ + +/* NOTIALLDMAWRIT @Bit 22 : Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos (22UL) /*!< Position of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Msk (0x1UL << USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos) /*!< Bit mask of NOTIALLDMAWRIT + field.*/ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Min (0x0UL) /*!< Min enumerator value of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Max (0x1UL) /*!< Max enumerator value of NOTIALLDMAWRIT field. */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_LASTTRANS (0x0UL) /*!< (unspecified) */ + #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_ALLTRANS (0x1UL) /*!< The core asserts int_dma_req for all the DMA write transactions + on the AHB interface along with int_dma_done, + chep_last_transact and chep_number signal informations. The + core waits for sys_dma_done signal for all the DMA write + transactions in order to complete the transfer of a particular + Channel/Endpoint*/ + +/* AHBSINGLE @Bit 23 : Mode: Host and Device. AHB Single Support (AHBSingle) */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Pos (23UL) /*!< Position of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Msk (0x1UL << USBHSCORE_GAHBCFG_AHBSINGLE_Pos) /*!< Bit mask of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Min (0x0UL) /*!< Min enumerator value of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_Max (0x1UL) /*!< Max enumerator value of AHBSINGLE field. */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_INCRBURST (0x0UL) /*!< The remaining data in the transfer is sent using INCR burst size */ + #define USBHSCORE_GAHBCFG_AHBSINGLE_SINGLEBURST (0x1UL) /*!< The remaining data in the transfer is sent using Single burst + size*/ + + +/* USBHSCORE_GUSBCFG: USB Configuration Register */ + #define USBHSCORE_GUSBCFG_ResetValue (0x10001400UL) /*!< Reset value of GUSBCFG register. */ + +/* TOUTCAL @Bits 0..2 : Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Pos (0UL) /*!< Position of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Msk (0x7UL << USBHSCORE_GUSBCFG_TOUTCAL_Pos) /*!< Bit mask of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Min (0x0UL) /*!< Min enumerator value of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_Max (0x7UL) /*!< Max enumerator value of TOUTCAL field. */ + #define USBHSCORE_GUSBCFG_TOUTCAL_ZERO (0x0UL) /*!< Add 0 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_ONE (0x1UL) /*!< Add 1 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_TWO (0x2UL) /*!< Add 2 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_THREE (0x3UL) /*!< Add 3 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_FOUR (0x4UL) /*!< Add 4 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_FIVE (0x5UL) /*!< Add 5 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_SIX (0x6UL) /*!< Add 6 PHY clocks */ + #define USBHSCORE_GUSBCFG_TOUTCAL_SEVEN (0x7UL) /*!< Add 7 PHY clocks */ + +/* PHYIF @Bit 3 : Mode: Host and Device. PHY Interface (PHYIf) */ + #define USBHSCORE_GUSBCFG_PHYIF_Pos (3UL) /*!< Position of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYIF_Pos) /*!< Bit mask of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Min (0x0UL) /*!< Min enumerator value of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_Max (0x1UL) /*!< Max enumerator value of PHYIF field. */ + #define USBHSCORE_GUSBCFG_PHYIF_BITS8 (0x0UL) /*!< PHY 8bit Mode */ + #define USBHSCORE_GUSBCFG_PHYIF_BITS16 (0x1UL) /*!< PHY 16bit Mode */ + +/* ULPIUTMISEL @Bit 4 : Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos (4UL) /*!< Position of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Msk (0x1UL << USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos) /*!< Bit mask of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Min (0x0UL) /*!< Min enumerator value of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Max (0x1UL) /*!< Max enumerator value of ULPIUTMISEL field. */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_UTMI (0x0UL) /*!< UTMI+ Interface */ + #define USBHSCORE_GUSBCFG_ULPIUTMISEL_ULPI (0x1UL) /*!< ULPI Interface */ + +/* FSINTF @Bit 5 : Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) */ + #define USBHSCORE_GUSBCFG_FSINTF_Pos (5UL) /*!< Position of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Msk (0x1UL << USBHSCORE_GUSBCFG_FSINTF_Pos) /*!< Bit mask of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Min (0x0UL) /*!< Min enumerator value of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_Max (0x1UL) /*!< Max enumerator value of FSINTF field. */ + #define USBHSCORE_GUSBCFG_FSINTF_FS6PIN (0x0UL) /*!< 6-pin unidirectional full-speed serial interface */ + #define USBHSCORE_GUSBCFG_FSINTF_FS3PIN (0x1UL) /*!< 3-pin bidirectional full-speed serial interface */ + +/* PHYSEL @Bit 6 : PHYSel */ + #define USBHSCORE_GUSBCFG_PHYSEL_Pos (6UL) /*!< Position of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYSEL_Pos) /*!< Bit mask of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Min (0x0UL) /*!< Min enumerator value of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_Max (0x1UL) /*!< Max enumerator value of PHYSEL field. */ + #define USBHSCORE_GUSBCFG_PHYSEL_USB20 (0x0UL) /*!< USB 2.0 high-speed UTMI+ or ULPI PHY is selected */ + #define USBHSCORE_GUSBCFG_PHYSEL_USB11 (0x1UL) /*!< USB 1.1 full-speed serial transceiver is selected */ + +/* USBTRDTIM @Bits 10..13 : Mode: Device only. USB Turnaround Time (USBTrdTim) */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Pos (10UL) /*!< Position of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Msk (0xFUL << USBHSCORE_GUSBCFG_USBTRDTIM_Pos) /*!< Bit mask of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Min (0x5UL) /*!< Min enumerator value of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_Max (0x9UL) /*!< Max enumerator value of USBTRDTIM field. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME16BIT (0x5UL) /*!< MAC interface is 16-bit UTMI+. */ + #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME8BIT (0x9UL) /*!< MAC interface is 8-bit UTMI+. */ + +/* PHYLPWRCLKSEL @Bit 15 : PHY Low-Power Clock Select (PhyLPwrClkSel) */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos (15UL) /*!< Position of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos) /*!< Bit mask of PHYLPWRCLKSEL + field.*/ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Min (0x0UL) /*!< Min enumerator value of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Max (0x1UL) /*!< Max enumerator value of PHYLPWRCLKSEL field. */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_INTPLLCLK (0x0UL) /*!< 480-MHz Internal PLL clock */ + #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_EXTCLK (0x1UL) /*!< 48-MHz External Clock */ + +/* TERMSELDLPULSE @Bit 22 : Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos (22UL) /*!< Position of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Msk (0x1UL << USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos) /*!< Bit mask of TERMSELDLPULSE + field.*/ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Min (0x0UL) /*!< Min enumerator value of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Max (0x1UL) /*!< Max enumerator value of TERMSELDLPULSE field. */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TXVALID (0x0UL) /*!< Data line pulsing using utmi_txvalid */ + #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TERMSEL (0x1UL) /*!< Data line pulsing using utmi_termsel */ + +/* ICUSBCAP @Bit 26 : Mode: Host and Device. IC_USB-Capable (IC_USBCap) */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Pos (26UL) /*!< Position of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Msk (0x1UL << USBHSCORE_GUSBCFG_ICUSBCAP_Pos) /*!< Bit mask of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Min (0x0UL) /*!< Min enumerator value of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_Max (0x1UL) /*!< Max enumerator value of ICUSBCAP field. */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_NOTSELECTED (0x0UL) /*!< IC_USB PHY Interface is not selected */ + #define USBHSCORE_GUSBCFG_ICUSBCAP_SELECTED (0x1UL) /*!< IC_USB PHY Interface is selected */ + +/* TXENDDELAY @Bit 28 : Mode: Device only. Tx End Delay (TxEndDelay) */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Pos (28UL) /*!< Position of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Msk (0x1UL << USBHSCORE_GUSBCFG_TXENDDELAY_Pos) /*!< Bit mask of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Min (0x0UL) /*!< Min enumerator value of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_Max (0x1UL) /*!< Max enumerator value of TXENDDELAY field. */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_TXENDDELAY_ENABLED (0x1UL) /*!< Tx End delay */ + +/* FORCEHSTMODE @Bit 29 : Mode: Host and device. Force Host Mode (ForceHstMode) */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos (29UL) /*!< Position of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos) /*!< Bit mask of FORCEHSTMODE field.*/ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Min (0x0UL) /*!< Min enumerator value of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Max (0x1UL) /*!< Max enumerator value of FORCEHSTMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_FORCEHSTMODE_ENABLED (0x1UL) /*!< Force Host Mode */ + +/* FORCEDEVMODE @Bit 30 : Mode:Host and device. Force Device Mode (ForceDevMode) */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos (30UL) /*!< Position of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos) /*!< Bit mask of FORCEDEVMODE field.*/ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Min (0x0UL) /*!< Min enumerator value of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Max (0x1UL) /*!< Max enumerator value of FORCEDEVMODE field. */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_DISABLED (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_FORCEDEVMODE_ENABLED (0x1UL) /*!< Force Device Mode */ + +/* CORRUPTTXPKT @Bit 31 : Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos (31UL) /*!< Position of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Msk (0x1UL << USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos) /*!< Bit mask of CORRUPTTXPKT field.*/ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Min (0x0UL) /*!< Min enumerator value of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Max (0x1UL) /*!< Max enumerator value of CORRUPTTXPKT field. */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Disabled (0x0UL) /*!< Normal Mode */ + #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Enabled (0x1UL) /*!< Debug Mode */ + + +/* USBHSCORE_GRSTCTL: Reset Register */ + #define USBHSCORE_GRSTCTL_ResetValue (0x80000000UL) /*!< Reset value of GRSTCTL register. */ + +/* CSFTRST @Bit 0 : Mode: Host and Device. Core Soft Reset (CSftRst) */ + #define USBHSCORE_GRSTCTL_CSFTRST_Pos (0UL) /*!< Position of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRST_Pos) /*!< Bit mask of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Min (0x0UL) /*!< Min enumerator value of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_Max (0x1UL) /*!< Max enumerator value of CSFTRST field. */ + #define USBHSCORE_GRSTCTL_CSFTRST_NOTACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_CSFTRST_ACTIVE (0x1UL) /*!< Resets hclk and phy_clock domains */ + +/* PIUFSSFTRST @Bit 1 : Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos (1UL) /*!< Position of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos) /*!< Bit mask of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Min (0x0UL) /*!< Min enumerator value of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Max (0x1UL) /*!< Max enumerator value of PIUFSSFTRST field. */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESET_INACTIVE (0x0UL) /*!< No Reset */ + #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESET_ACTIVE (0x1UL) /*!< PIU FS Dedicated Controller Soft Reset */ + +/* FRMCNTRRST @Bit 2 : Mode: Host only. Host Frame Counter Reset (FrmCntrRst) */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Pos (2UL) /*!< Position of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Msk (0x1UL << USBHSCORE_GRSTCTL_FRMCNTRRST_Pos) /*!< Bit mask of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Min (0x0UL) /*!< Min enumerator value of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_Max (0x1UL) /*!< Max enumerator value of FRMCNTRRST field. */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_NOTACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_FRMCNTRRST_ACTIVE (0x1UL) /*!< Host Frame Counter Reset */ + +/* RXFFLSH @Bit 4 : Mode: Host and Device. RxFIFO Flush (RxFFlsh) */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Pos (4UL) /*!< Position of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_RXFFLSH_Pos) /*!< Bit mask of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Min (0x0UL) /*!< Min enumerator value of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_Max (0x1UL) /*!< Max enumerator value of RXFFLSH field. */ + #define USBHSCORE_GRSTCTL_RXFFLSH_INACTIVE (0x0UL) /*!< Does not flush the entire RxFIFO */ + #define USBHSCORE_GRSTCTL_RXFFLSH_ACTIVE (0x1UL) /*!< Flushes the entire RxFIFO */ + +/* TXFFLSH @Bit 5 : Mode: Host and Device. TxFIFO Flush (TxFFlsh) */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Pos (5UL) /*!< Position of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_TXFFLSH_Pos) /*!< Bit mask of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Min (0x0UL) /*!< Min enumerator value of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_Max (0x1UL) /*!< Max enumerator value of TXFFLSH field. */ + #define USBHSCORE_GRSTCTL_TXFFLSH_INACTIVE (0x0UL) /*!< No Flush */ + #define USBHSCORE_GRSTCTL_TXFFLSH_ACTIVE (0x1UL) /*!< Selectively flushes a single or all transmit FIFOs */ + +/* TXFNUM @Bits 6..10 : Mode: Host and Device. TxFIFO Number (TxFNum) */ + #define USBHSCORE_GRSTCTL_TXFNUM_Pos (6UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Msk (0x1FUL << USBHSCORE_GRSTCTL_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_Max (0x10UL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF0 (0x00UL) /*!< -Periodic TxFIFO flush in host mode -Periodic TxFIFO 0 flush in device + mode when in shared FIFO operation -TXFIFO 0 flush in device mode when + in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF1 (0x01UL) /*!< -Periodic TxFIFO flush in host mode -Periodic TxFIFO 1 flush in device + mode when in shared FIFO operation -TXFIFO 1 flush in device mode when + in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF2 (0x02UL) /*!< -Periodic TxFIFO 2 flush in device mode when in shared FIFO operation + -TXFIFO 2 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF3 (0x03UL) /*!< -Periodic TxFIFO 3 flush in device mode when in shared FIFO operation + -TXFIFO 3 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF4 (0x04UL) /*!< -Periodic TxFIFO 4 flush in device mode when in shared FIFO operation + -TXFIFO 4 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF5 (0x05UL) /*!< -Periodic TxFIFO 5 flush in device mode when in shared FIFO operation + -TXFIFO 5 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF6 (0x06UL) /*!< -Periodic TxFIFO 6 flush in device mode when in shared FIFO operation + -TXFIFO 6 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF7 (0x07UL) /*!< -Periodic TxFIFO 7 flush in device mode when in shared FIFO operation + -TXFIFO 7 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF8 (0x08UL) /*!< -Periodic TxFIFO 8 flush in device mode when in shared FIFO operation + -TXFIFO 8 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF9 (0x09UL) /*!< -Periodic TxFIFO 9 flush in device mode when in shared FIFO operation + -TXFIFO 9 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF10 (0x0AUL) /*!< -Periodic TxFIFO 10 flush in device mode when in shared FIFO operation + -TXFIFO 10 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF11 (0x0BUL) /*!< -Periodic TxFIFO 11 flush in device mode when in shared FIFO operation + -TXFIFO 11 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF12 (0x0CUL) /*!< -Periodic TxFIFO 12 flush in device mode when in shared FIFO operation + -TXFIFO 12 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF13 (0x0DUL) /*!< -Periodic TxFIFO 13 flush in Device mode when in shared FIFO operation + -TXFIFO 13 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF14 (0x0EUL) /*!< -Periodic TxFIFO 14 flush in Device mode when in shared FIFO operation + -TXFIFO 14 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF15 (0x0FUL) /*!< -Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation + - TXFIFO 15 flush in device mode when in dedicated FIFO mode*/ + #define USBHSCORE_GRSTCTL_TXFNUM_TXF16 (0x10UL) /*!< Flush all the transmit FIFOs in device or host mode */ + +/* CSFTRSTDONE @Bit 29 : Mode: Host and Device. Core Soft Reset Done (CSftRstDone) */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos (29UL) /*!< Position of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos) /*!< Bit mask of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Min (0x0UL) /*!< Min enumerator value of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Max (0x1UL) /*!< Max enumerator value of CSFTRSTDONE field. */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_INACTIVE (0x0UL) /*!< No reset */ + #define USBHSCORE_GRSTCTL_CSFTRSTDONE_ACTIVE (0x1UL) /*!< Core Soft Reset is done */ + +/* DMAREQ @Bit 30 : Mode: Host and Device. DMA Request Signal (DMAReq) */ + #define USBHSCORE_GRSTCTL_DMAREQ_Pos (30UL) /*!< Position of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Msk (0x1UL << USBHSCORE_GRSTCTL_DMAREQ_Pos) /*!< Bit mask of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Min (0x0UL) /*!< Min enumerator value of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_Max (0x1UL) /*!< Max enumerator value of DMAREQ field. */ + #define USBHSCORE_GRSTCTL_DMAREQ_INACTIVE (0x0UL) /*!< No DMA request */ + #define USBHSCORE_GRSTCTL_DMAREQ_ACTIVE (0x1UL) /*!< DMA request is in progress */ + +/* AHBIDLE @Bit 31 : Mode: Host and Device. AHB Master Idle (AHBIdle) */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Pos (31UL) /*!< Position of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Msk (0x1UL << USBHSCORE_GRSTCTL_AHBIDLE_Pos) /*!< Bit mask of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Min (0x0UL) /*!< Min enumerator value of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_Max (0x1UL) /*!< Max enumerator value of AHBIDLE field. */ + #define USBHSCORE_GRSTCTL_AHBIDLE_INACTIVE (0x0UL) /*!< Not Idle */ + #define USBHSCORE_GRSTCTL_AHBIDLE_ACTIVE (0x1UL) /*!< AHB Master Idle */ + + +/* USBHSCORE_GINTSTS: Interrupt Register */ + #define USBHSCORE_GINTSTS_ResetValue (0x00000020UL) /*!< Reset value of GINTSTS register. */ + +/* CURMOD @Bit 0 : Mode: Host and Device. Current Mode of Operation (CurMod) */ + #define USBHSCORE_GINTSTS_CURMOD_Pos (0UL) /*!< Position of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Msk (0x1UL << USBHSCORE_GINTSTS_CURMOD_Pos) /*!< Bit mask of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Min (0x0UL) /*!< Min enumerator value of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_Max (0x1UL) /*!< Max enumerator value of CURMOD field. */ + #define USBHSCORE_GINTSTS_CURMOD_DEVICE (0x0UL) /*!< Device mode */ + #define USBHSCORE_GINTSTS_CURMOD_HOST (0x1UL) /*!< Host mode */ + +/* MODEMIS @Bit 1 : Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) */ + #define USBHSCORE_GINTSTS_MODEMIS_Pos (1UL) /*!< Position of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Msk (0x1UL << USBHSCORE_GINTSTS_MODEMIS_Pos) /*!< Bit mask of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Min (0x0UL) /*!< Min enumerator value of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_Max (0x1UL) /*!< Max enumerator value of MODEMIS field. */ + #define USBHSCORE_GINTSTS_MODEMIS_INACTIVE (0x0UL) /*!< No Mode Mismatch Interrupt */ + #define USBHSCORE_GINTSTS_MODEMIS_ACTIVE (0x1UL) /*!< Mode Mismatch Interrupt */ + +/* OTGINT @Bit 2 : Mode: Host and Device. OTG Interrupt (OTGInt) */ + #define USBHSCORE_GINTSTS_OTGINT_Pos (2UL) /*!< Position of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Msk (0x1UL << USBHSCORE_GINTSTS_OTGINT_Pos) /*!< Bit mask of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Min (0x0UL) /*!< Min enumerator value of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_Max (0x1UL) /*!< Max enumerator value of OTGINT field. */ + #define USBHSCORE_GINTSTS_OTGINT_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_GINTSTS_OTGINT_ACTIVE (0x1UL) /*!< OTG Interrupt */ + +/* SOF @Bit 3 : Mode: Host and Device. Start of (micro)Frame (Sof) */ + #define USBHSCORE_GINTSTS_SOF_Pos (3UL) /*!< Position of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Msk (0x1UL << USBHSCORE_GINTSTS_SOF_Pos) /*!< Bit mask of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Min (0x0UL) /*!< Min enumerator value of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_Max (0x1UL) /*!< Max enumerator value of SOF field. */ + #define USBHSCORE_GINTSTS_SOF_INTACTIVE (0x0UL) /*!< No Start of Frame */ + #define USBHSCORE_GINTSTS_SOF_ACTIVE (0x1UL) /*!< Start of Frame */ + +/* RXFLVL @Bit 4 : Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) */ + #define USBHSCORE_GINTSTS_RXFLVL_Pos (4UL) /*!< Position of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Msk (0x1UL << USBHSCORE_GINTSTS_RXFLVL_Pos) /*!< Bit mask of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Min (0x0UL) /*!< Min enumerator value of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_Max (0x1UL) /*!< Max enumerator value of RXFLVL field. */ + #define USBHSCORE_GINTSTS_RXFLVL_INACTIVE (0x0UL) /*!< Rx Fifo is empty */ + #define USBHSCORE_GINTSTS_RXFLVL_ACTIVE (0x1UL) /*!< Rx Fifo is not empty */ + +/* NPTXFEMP @Bit 5 : Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Pos (5UL) /*!< Position of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Msk (0x1UL << USBHSCORE_GINTSTS_NPTXFEMP_Pos) /*!< Bit mask of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Min (0x0UL) /*!< Min enumerator value of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_Max (0x1UL) /*!< Max enumerator value of NPTXFEMP field. */ + #define USBHSCORE_GINTSTS_NPTXFEMP_INACTIVE (0x0UL) /*!< Non-periodic TxFIFO is not empty */ + #define USBHSCORE_GINTSTS_NPTXFEMP_ACTIVE (0x1UL) /*!< Non-periodic TxFIFO is empty */ + +/* GINNAKEFF @Bit 6 : Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Pos (6UL) /*!< Position of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GINNAKEFF_Pos) /*!< Bit mask of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Min (0x0UL) /*!< Min enumerator value of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_Max (0x1UL) /*!< Max enumerator value of GINNAKEFF field. */ + #define USBHSCORE_GINTSTS_GINNAKEFF_INACTIVE (0x0UL) /*!< Global Non-periodic IN NAK not active */ + #define USBHSCORE_GINTSTS_GINNAKEFF_ACTIVE (0x1UL) /*!< Set Global Non-periodic IN NAK bit */ + +/* GOUTNAKEFF @Bit 7 : Mode: Device only. Global OUT NAK Effective (GOUTNakEff) */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Pos (7UL) /*!< Position of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GOUTNAKEFF_Pos) /*!< Bit mask of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Min (0x0UL) /*!< Min enumerator value of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_Max (0x1UL) /*!< Max enumerator value of GOUTNAKEFF field. */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_GOUTNAKEFF_ACTIVE (0x1UL) /*!< Global OUT NAK Effective */ + +/* ERLYSUSP @Bit 10 : Mode: Device only. Early Suspend (ErlySusp) */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Pos (10UL) /*!< Position of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_ERLYSUSP_Pos) /*!< Bit mask of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Min (0x0UL) /*!< Min enumerator value of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_Max (0x1UL) /*!< Max enumerator value of ERLYSUSP field. */ + #define USBHSCORE_GINTSTS_ERLYSUSP_INACTIVE (0x0UL) /*!< No Idle state detected */ + #define USBHSCORE_GINTSTS_ERLYSUSP_ACTIVE (0x1UL) /*!< 3ms of Idle state detected */ + +/* USBSUSP @Bit 11 : Mode: Device only. USB Suspend (USBSusp) */ + #define USBHSCORE_GINTSTS_USBSUSP_Pos (11UL) /*!< Position of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_USBSUSP_Pos) /*!< Bit mask of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Min (0x0UL) /*!< Min enumerator value of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_Max (0x1UL) /*!< Max enumerator value of USBSUSP field. */ + #define USBHSCORE_GINTSTS_USBSUSP_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_USBSUSP_ACTIVE (0x1UL) /*!< USB Suspend */ + +/* USBRST @Bit 12 : Mode: Device only. USB Reset (USBRst) */ + #define USBHSCORE_GINTSTS_USBRST_Pos (12UL) /*!< Position of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Msk (0x1UL << USBHSCORE_GINTSTS_USBRST_Pos) /*!< Bit mask of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Min (0x0UL) /*!< Min enumerator value of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_Max (0x1UL) /*!< Max enumerator value of USBRST field. */ + #define USBHSCORE_GINTSTS_USBRST_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_USBRST_ACTIVE (0x1UL) /*!< USB Reset */ + +/* ENUMDONE @Bit 13 : Mode: Device only. Enumeration Done (EnumDone) */ + #define USBHSCORE_GINTSTS_ENUMDONE_Pos (13UL) /*!< Position of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Msk (0x1UL << USBHSCORE_GINTSTS_ENUMDONE_Pos) /*!< Bit mask of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Min (0x0UL) /*!< Min enumerator value of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_Max (0x1UL) /*!< Max enumerator value of ENUMDONE field. */ + #define USBHSCORE_GINTSTS_ENUMDONE_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_ENUMDONE_ACTIVE (0x1UL) /*!< Enumeration Done */ + +/* ISOOUTDROP @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Pos (14UL) /*!< Position of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Msk (0x1UL << USBHSCORE_GINTSTS_ISOOUTDROP_Pos) /*!< Bit mask of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Min (0x0UL) /*!< Min enumerator value of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_Max (0x1UL) /*!< Max enumerator value of ISOOUTDROP field. */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_ISOOUTDROP_ACTIVE (0x1UL) /*!< Isochronous OUT Packet Dropped Interrupt */ + +/* EOPF @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt (EOPF) */ + #define USBHSCORE_GINTSTS_EOPF_Pos (15UL) /*!< Position of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Msk (0x1UL << USBHSCORE_GINTSTS_EOPF_Pos) /*!< Bit mask of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Min (0x0UL) /*!< Min enumerator value of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_Max (0x1UL) /*!< Max enumerator value of EOPF field. */ + #define USBHSCORE_GINTSTS_EOPF_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_EOPF_ACTIVE (0x1UL) /*!< End of Periodic Frame Interrupt */ + +/* RSTRDONEINT @Bit 16 : Mode: Device only. Restore Done Interrupt (RstrDoneInt) */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Pos (16UL) /*!< Position of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Msk (0x1UL << USBHSCORE_GINTSTS_RSTRDONEINT_Pos) /*!< Bit mask of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Min (0x0UL) /*!< Min enumerator value of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_Max (0x1UL) /*!< Max enumerator value of RSTRDONEINT field. */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_RSTRDONEINT_ACTIVE (0x1UL) /*!< Restore Done Interrupt */ + +/* EPMIS @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt (EPMis) */ + #define USBHSCORE_GINTSTS_EPMIS_Pos (17UL) /*!< Position of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Msk (0x1UL << USBHSCORE_GINTSTS_EPMIS_Pos) /*!< Bit mask of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Min (0x0UL) /*!< Min enumerator value of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_Max (0x1UL) /*!< Max enumerator value of EPMIS field. */ + #define USBHSCORE_GINTSTS_EPMIS_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_EPMIS_ACTIVE (0x1UL) /*!< Endpoint Mismatch Interrupt */ + +/* IEPINT @Bit 18 : Mode: Device only. IN Endpoints Interrupt (IEPInt) */ + #define USBHSCORE_GINTSTS_IEPINT_Pos (18UL) /*!< Position of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_IEPINT_Pos) /*!< Bit mask of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Min (0x0UL) /*!< Min enumerator value of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_Max (0x1UL) /*!< Max enumerator value of IEPINT field. */ + #define USBHSCORE_GINTSTS_IEPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_IEPINT_ACTIVE (0x1UL) /*!< IN Endpoints Interrupt */ + +/* OEPINT @Bit 19 : Mode: Device only. OUT Endpoints Interrupt (OEPInt) */ + #define USBHSCORE_GINTSTS_OEPINT_Pos (19UL) /*!< Position of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_OEPINT_Pos) /*!< Bit mask of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Min (0x0UL) /*!< Min enumerator value of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_Max (0x1UL) /*!< Max enumerator value of OEPINT field. */ + #define USBHSCORE_GINTSTS_OEPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_OEPINT_ACTIVE (0x1UL) /*!< OUT Endpoints Interrupt */ + +/* INCOMPISOIN @Bit 20 : Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Pos (20UL) /*!< Position of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPISOIN_Pos) /*!< Bit mask of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Min (0x0UL) /*!< Min enumerator value of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_Max (0x1UL) /*!< Max enumerator value of INCOMPISOIN field. */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_INCOMPISOIN_ACTIVE (0x1UL) /*!< Incomplete Isochronous IN Transfer */ + +/* INCOMPLP @Bit 21 : Incomplete Periodic Transfer (incomplP) */ + #define USBHSCORE_GINTSTS_INCOMPLP_Pos (21UL) /*!< Position of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPLP_Pos) /*!< Bit mask of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Min (0x0UL) /*!< Min enumerator value of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_Max (0x1UL) /*!< Max enumerator value of INCOMPLP field. */ + #define USBHSCORE_GINTSTS_INCOMPLP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_INCOMPLP_ACTIVE (0x1UL) /*!< Incomplete Periodic Transfer */ + +/* FETSUSP @Bit 22 : Mode: Device only. Data Fetch Suspended (FetSusp) */ + #define USBHSCORE_GINTSTS_FETSUSP_Pos (22UL) /*!< Position of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_FETSUSP_Pos) /*!< Bit mask of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Min (0x0UL) /*!< Min enumerator value of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_Max (0x1UL) /*!< Max enumerator value of FETSUSP field. */ + #define USBHSCORE_GINTSTS_FETSUSP_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_FETSUSP_ACTIVE (0x1UL) /*!< Data Fetch Suspended */ + +/* RESETDET @Bit 23 : Mode: Device only. Reset detected Interrupt (ResetDet) */ + #define USBHSCORE_GINTSTS_RESETDET_Pos (23UL) /*!< Position of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Msk (0x1UL << USBHSCORE_GINTSTS_RESETDET_Pos) /*!< Bit mask of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Min (0x0UL) /*!< Min enumerator value of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_Max (0x1UL) /*!< Max enumerator value of RESETDET field. */ + #define USBHSCORE_GINTSTS_RESETDET_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_RESETDET_ACTIVE (0x1UL) /*!< Reset detected Interrupt */ + +/* PRTINT @Bit 24 : Mode: Host only. Host Port Interrupt (PrtInt) */ + #define USBHSCORE_GINTSTS_PRTINT_Pos (24UL) /*!< Position of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Msk (0x1UL << USBHSCORE_GINTSTS_PRTINT_Pos) /*!< Bit mask of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Min (0x0UL) /*!< Min enumerator value of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_Max (0x1UL) /*!< Max enumerator value of PRTINT field. */ + #define USBHSCORE_GINTSTS_PRTINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_PRTINT_ACTIVE (0x1UL) /*!< Host Port Interrupt */ + +/* HCHINT @Bit 25 : Mode: Host only. Host Channels Interrupt (HChInt) */ + #define USBHSCORE_GINTSTS_HCHINT_Pos (25UL) /*!< Position of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Msk (0x1UL << USBHSCORE_GINTSTS_HCHINT_Pos) /*!< Bit mask of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Min (0x0UL) /*!< Min enumerator value of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_Max (0x1UL) /*!< Max enumerator value of HCHINT field. */ + #define USBHSCORE_GINTSTS_HCHINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_HCHINT_ACTIVE (0x1UL) /*!< Host Channels Interrupt */ + +/* LPMINT @Bit 27 : Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int). */ + #define USBHSCORE_GINTSTS_LPMINT_Pos (27UL) /*!< Position of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Msk (0x1UL << USBHSCORE_GINTSTS_LPMINT_Pos) /*!< Bit mask of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Min (0x0UL) /*!< Min enumerator value of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_Max (0x1UL) /*!< Max enumerator value of LPMINT field. */ + #define USBHSCORE_GINTSTS_LPMINT_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_LPMINT_ACTIVE (0x1UL) /*!< LPM Transaction Received Interrupt */ + +/* CONIDSTSCHNG @Bit 28 : Mode: Host and Device. Connector ID Status Change (ConIDStsChng) */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos (28UL) /*!< Position of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Msk (0x1UL << USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos) /*!< Bit mask of CONIDSTSCHNG field.*/ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNG field. */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_INACTIVE (0x0UL) /*!< Not Active */ + #define USBHSCORE_GINTSTS_CONIDSTSCHNG_ACTIVE (0x1UL) /*!< Connector ID Status Change */ + +/* DISCONNINT @Bit 29 : Mode: Host only. Disconnect Detected Interrupt (DisconnInt) */ + #define USBHSCORE_GINTSTS_DISCONNINT_Pos (29UL) /*!< Position of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Msk (0x1UL << USBHSCORE_GINTSTS_DISCONNINT_Pos) /*!< Bit mask of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Min (0x0UL) /*!< Min enumerator value of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_Max (0x1UL) /*!< Max enumerator value of DISCONNINT field. */ + #define USBHSCORE_GINTSTS_DISCONNINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_DISCONNINT_ACTIVE (0x1UL) /*!< Disconnect Detected Interrupt */ + +/* SESSREQINT @Bit 30 : Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) */ + #define USBHSCORE_GINTSTS_SESSREQINT_Pos (30UL) /*!< Position of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Msk (0x1UL << USBHSCORE_GINTSTS_SESSREQINT_Pos) /*!< Bit mask of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Min (0x0UL) /*!< Min enumerator value of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_Max (0x1UL) /*!< Max enumerator value of SESSREQINT field. */ + #define USBHSCORE_GINTSTS_SESSREQINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_SESSREQINT_ACTIVE (0x1UL) /*!< Session Request New Session Detected Interrupt */ + +/* WKUPINT @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) */ + #define USBHSCORE_GINTSTS_WKUPINT_Pos (31UL) /*!< Position of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Msk (0x1UL << USBHSCORE_GINTSTS_WKUPINT_Pos) /*!< Bit mask of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Min (0x0UL) /*!< Min enumerator value of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_Max (0x1UL) /*!< Max enumerator value of WKUPINT field. */ + #define USBHSCORE_GINTSTS_WKUPINT_INACTIVE (0x0UL) /*!< Not active */ + #define USBHSCORE_GINTSTS_WKUPINT_ACTIVE (0x1UL) /*!< Resume or Remote Wakeup Detected Interrupt */ + + +/* USBHSCORE_GINTMSK: Interrupt Mask Register */ + #define USBHSCORE_GINTMSK_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK register. */ + +/* MODEMISMSK @Bit 1 : Mode: Host and Device. Mode Mismatch Interrupt Mask (ModeMisMsk) */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Pos (1UL) /*!< Position of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_MODEMISMSK_Pos) /*!< Bit mask of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Min (0x0UL) /*!< Min enumerator value of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_Max (0x1UL) /*!< Max enumerator value of MODEMISMSK field. */ + #define USBHSCORE_GINTMSK_MODEMISMSK_MASK (0x0UL) /*!< Mode Mismatch Interrupt Mask */ + #define USBHSCORE_GINTMSK_MODEMISMSK_NOMASK (0x1UL) /*!< No Mode Mismatch Interrupt Mask */ + +/* OTGINTMSK @Bit 2 : Mode: Host and Device. OTG Interrupt Mask (OTGIntMsk) */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Pos (2UL) /*!< Position of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OTGINTMSK_Pos) /*!< Bit mask of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Min (0x0UL) /*!< Min enumerator value of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_Max (0x1UL) /*!< Max enumerator value of OTGINTMSK field. */ + #define USBHSCORE_GINTMSK_OTGINTMSK_MASK (0x0UL) /*!< OTG Interrupt Mask */ + #define USBHSCORE_GINTMSK_OTGINTMSK_NOMASK (0x1UL) /*!< No OTG Interrupt Mask */ + +/* SOFMSK @Bit 3 : Mode: Host and Device. Start of (micro)Frame Mask (SofMsk) */ + #define USBHSCORE_GINTMSK_SOFMSK_Pos (3UL) /*!< Position of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SOFMSK_Pos) /*!< Bit mask of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Min (0x0UL) /*!< Min enumerator value of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_Max (0x1UL) /*!< Max enumerator value of SOFMSK field. */ + #define USBHSCORE_GINTMSK_SOFMSK_MASK (0x0UL) /*!< Start of Frame Mask */ + #define USBHSCORE_GINTMSK_SOFMSK_NOMASK (0x1UL) /*!< No Start of Frame Mask */ + +/* RXFLVLMSK @Bit 4 : Mode: Host and Device. Receive FIFO Non-Empty Mask (RxFLvlMsk) */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Pos (4UL) /*!< Position of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RXFLVLMSK_Pos) /*!< Bit mask of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Min (0x0UL) /*!< Min enumerator value of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_Max (0x1UL) /*!< Max enumerator value of RXFLVLMSK field. */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_MASK (0x0UL) /*!< Receive FIFO Non-Empty Mask */ + #define USBHSCORE_GINTMSK_RXFLVLMSK_NOMASK (0x1UL) /*!< No Receive FIFO Non-Empty Mask */ + +/* NPTXFEMPMSK @Bit 5 : Mode: Host and Device. Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk) */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos (5UL) /*!< Position of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos) /*!< Bit mask of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of NPTXFEMPMSK field. */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_MASK (0x0UL) /*!< Non-periodic TxFIFO Empty Mask */ + #define USBHSCORE_GINTMSK_NPTXFEMPMSK_NOMASK (0x1UL) /*!< No Non-periodic TxFIFO Empty Mask */ + +/* GINNAKEFFMSK @Bit 6 : Mode: Device only,. Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos (6UL) /*!< Position of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos) /*!< Bit mask of GINNAKEFFMSK field.*/ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GINNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_MASK (0x0UL) /*!< Global Non-periodic IN NAK Effective Mask */ + #define USBHSCORE_GINTMSK_GINNAKEFFMSK_NOMASK (0x1UL) /*!< No Global Non-periodic IN NAK Effective Mask */ + +/* GOUTNAKEFFMSK @Bit 7 : Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos (7UL) /*!< Position of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos) /*!< Bit mask of GOUTNAKEFFMSK + field.*/ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GOUTNAKEFFMSK field. */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_MASK (0x0UL) /*!< Global OUT NAK Effective Mask */ + #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_NOMASK (0x1UL) /*!< No Global OUT NAK Effective Mask */ + +/* ERLYSUSPMSK @Bit 10 : Mode: Device only. Early Suspend Mask (ErlySuspMsk) */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos (10UL) /*!< Position of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos) /*!< Bit mask of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Min (0x0UL) /*!< Min enumerator value of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Max (0x1UL) /*!< Max enumerator value of ERLYSUSPMSK field. */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_MASK (0x0UL) /*!< Early Suspend Mask */ + #define USBHSCORE_GINTMSK_ERLYSUSPMSK_NOMASK (0x1UL) /*!< No Early Suspend Mask */ + +/* USBSUSPMSK @Bit 11 : Mode: Device only. USB Suspend Mask (USBSuspMsk) */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Pos (11UL) /*!< Position of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBSUSPMSK_Pos) /*!< Bit mask of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Min (0x0UL) /*!< Min enumerator value of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_Max (0x1UL) /*!< Max enumerator value of USBSUSPMSK field. */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_MASK (0x0UL) /*!< USB Suspend Mask */ + #define USBHSCORE_GINTMSK_USBSUSPMSK_NOMASK (0x1UL) /*!< No USB Suspend Mask */ + +/* USBRSTMSK @Bit 12 : Mode: Device only. USB Reset Mask (USBRstMsk) */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Pos (12UL) /*!< Position of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBRSTMSK_Pos) /*!< Bit mask of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Min (0x0UL) /*!< Min enumerator value of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_Max (0x1UL) /*!< Max enumerator value of USBRSTMSK field. */ + #define USBHSCORE_GINTMSK_USBRSTMSK_MASK (0x0UL) /*!< USB Reset Mask */ + #define USBHSCORE_GINTMSK_USBRSTMSK_NOMASK (0x1UL) /*!< No USB Reset Mask */ + +/* ENUMDONEMSK @Bit 13 : Mode: Device only. Enumeration Done Mask (EnumDoneMsk) */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Pos (13UL) /*!< Position of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ENUMDONEMSK_Pos) /*!< Bit mask of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Min (0x0UL) /*!< Min enumerator value of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_Max (0x1UL) /*!< Max enumerator value of ENUMDONEMSK field. */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_MASK (0x0UL) /*!< Enumeration Done Mask */ + #define USBHSCORE_GINTMSK_ENUMDONEMSK_NOMASK (0x1UL) /*!< No Enumeration Done Mask */ + +/* ISOOUTDROPMSK @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos (14UL) /*!< Position of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos) /*!< Bit mask of ISOOUTDROPMSK + field.*/ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Min (0x0UL) /*!< Min enumerator value of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Max (0x1UL) /*!< Max enumerator value of ISOOUTDROPMSK field. */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_MASK (0x0UL) /*!< Isochronous OUT Packet Dropped Interrupt Mask */ + #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_NOMASK (0x1UL) /*!< No Isochronous OUT Packet Dropped Interrupt Mask */ + +/* EOPFMSK @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) */ + #define USBHSCORE_GINTMSK_EOPFMSK_Pos (15UL) /*!< Position of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EOPFMSK_Pos) /*!< Bit mask of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Min (0x0UL) /*!< Min enumerator value of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_Max (0x1UL) /*!< Max enumerator value of EOPFMSK field. */ + #define USBHSCORE_GINTMSK_EOPFMSK_MASK (0x0UL) /*!< End of Periodic Frame Interrupt Mask */ + #define USBHSCORE_GINTMSK_EOPFMSK_NOMASK (0x1UL) /*!< No End of Periodic Frame Interrupt Mask */ + +/* RSTRDONEINTMSK @Bit 16 : Mode: Host and Device. Restore Done Interrupt Mask (RstrDoneIntMsk) */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos (16UL) /*!< Position of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos) /*!< Bit mask of RSTRDONEINTMSK + field.*/ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Min (0x0UL) /*!< Min enumerator value of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Max (0x1UL) /*!< Max enumerator value of RSTRDONEINTMSK field. */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_MASK (0x0UL) /*!< Restore Done Interrupt Mask */ + #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_NOMASK (0x1UL) /*!< No Restore Done Interrupt Mask */ + +/* EPMISMSK @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) */ + #define USBHSCORE_GINTMSK_EPMISMSK_Pos (17UL) /*!< Position of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EPMISMSK_Pos) /*!< Bit mask of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Min (0x0UL) /*!< Min enumerator value of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_Max (0x1UL) /*!< Max enumerator value of EPMISMSK field. */ + #define USBHSCORE_GINTMSK_EPMISMSK_MASK (0x0UL) /*!< Endpoint Mismatch Interrupt Mask */ + #define USBHSCORE_GINTMSK_EPMISMSK_NOMASK (0x1UL) /*!< No Endpoint Mismatch Interrupt Mask */ + +/* IEPINTMSK @Bit 18 : Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Pos (18UL) /*!< Position of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_IEPINTMSK_Pos) /*!< Bit mask of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Min (0x0UL) /*!< Min enumerator value of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_Max (0x1UL) /*!< Max enumerator value of IEPINTMSK field. */ + #define USBHSCORE_GINTMSK_IEPINTMSK_MASK (0x0UL) /*!< IN Endpoints Interrupt Mask */ + #define USBHSCORE_GINTMSK_IEPINTMSK_NOMASK (0x1UL) /*!< No IN Endpoints Interrupt Mask */ + +/* OEPINTMSK @Bit 19 : Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Pos (19UL) /*!< Position of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OEPINTMSK_Pos) /*!< Bit mask of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Min (0x0UL) /*!< Min enumerator value of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_Max (0x1UL) /*!< Max enumerator value of OEPINTMSK field. */ + #define USBHSCORE_GINTMSK_OEPINTMSK_MASK (0x0UL) /*!< OUT Endpoints Interrupt Mask */ + #define USBHSCORE_GINTMSK_OEPINTMSK_NOMASK (0x1UL) /*!< No OUT Endpoints Interrupt Mask */ + +/* INCOMPLPMSK @Bit 21 : Incomplete Periodic Transfer Mask (incomplPMsk) */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Pos (21UL) /*!< Position of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_INCOMPLPMSK_Pos) /*!< Bit mask of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Min (0x0UL) /*!< Min enumerator value of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_Max (0x1UL) /*!< Max enumerator value of INCOMPLPMSK field. */ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_MASK (0x0UL) /*!< Host mode: Incomplete Periodic Transfer MaskDevice mode: Incomplete + Isochronous OUT Transfer Mask*/ + #define USBHSCORE_GINTMSK_INCOMPLPMSK_NOMASK (0x1UL) /*!< Host mode: No Incomplete Periodic Transfer MaskDevice mode: No + Incomplete Isochronous OUT Transfer Mask*/ + +/* FETSUSPMSK @Bit 22 : Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Pos (22UL) /*!< Position of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_FETSUSPMSK_Pos) /*!< Bit mask of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Min (0x0UL) /*!< Min enumerator value of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_Max (0x1UL) /*!< Max enumerator value of FETSUSPMSK field. */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_MASK (0x0UL) /*!< Data Fetch Suspended Mask */ + #define USBHSCORE_GINTMSK_FETSUSPMSK_NOMASK (0x1UL) /*!< No Data Fetch Suspended Mask */ + +/* RESETDETMSK @Bit 23 : Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Pos (23UL) /*!< Position of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Min (0x0UL) /*!< Min enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_Max (0x1UL) /*!< Max enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GINTMSK_RESETDETMSK_MASK (0x0UL) /*!< Reset detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_RESETDETMSK_NOMASK (0x1UL) /*!< No Reset detected Interrupt Mask */ + +/* PRTINTMSK @Bit 24 : Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Pos (24UL) /*!< Position of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_PRTINTMSK_Pos) /*!< Bit mask of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Min (0x0UL) /*!< Min enumerator value of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_Max (0x1UL) /*!< Max enumerator value of PRTINTMSK field. */ + #define USBHSCORE_GINTMSK_PRTINTMSK_MASK (0x0UL) /*!< Host Port Interrupt Mask */ + #define USBHSCORE_GINTMSK_PRTINTMSK_NOMASK (0x1UL) /*!< No Host Port Interrupt Mask */ + +/* HCHINTMSK @Bit 25 : Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Pos (25UL) /*!< Position of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_HCHINTMSK_Pos) /*!< Bit mask of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Min (0x0UL) /*!< Min enumerator value of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_Max (0x1UL) /*!< Max enumerator value of HCHINTMSK field. */ + #define USBHSCORE_GINTMSK_HCHINTMSK_MASK (0x0UL) /*!< Host Channels Interrupt Mask */ + #define USBHSCORE_GINTMSK_HCHINTMSK_NOMASK (0x1UL) /*!< No Host Channels Interrupt Mask */ + +/* LPMINTMSK @Bit 27 : Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Pos (27UL) /*!< Position of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_LPMINTMSK_Pos) /*!< Bit mask of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Min (0x0UL) /*!< Min enumerator value of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_Max (0x1UL) /*!< Max enumerator value of LPMINTMSK field. */ + #define USBHSCORE_GINTMSK_LPMINTMSK_MASK (0x0UL) /*!< LPM Transaction received interrupt Mask */ + #define USBHSCORE_GINTMSK_LPMINTMSK_NOMASK (0x1UL) /*!< No LPM Transaction received interrupt Mask */ + +/* CONIDSTSCHNGMSK @Bit 28 : Mode: Host and Device. Connector ID Status Change Mask (ConIDStsChngMsk) */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos (28UL) /*!< Position of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Msk (0x1UL << USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos) /*!< Bit mask of + CONIDSTSCHNGMSK field.*/ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNGMSK field. */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_MASK (0x0UL) /*!< Connector ID Status Change Mask */ + #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_NOMASK (0x1UL) /*!< No Connector ID Status Change Mask */ + +/* DISCONNINTMSK @Bit 29 : Mode: Host and Device. Disconnect Detected Interrupt Mask (DisconnIntMsk) */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Pos (29UL) /*!< Position of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_DISCONNINTMSK_Pos) /*!< Bit mask of DISCONNINTMSK + field.*/ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNINTMSK field. */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_MASK (0x0UL) /*!< Disconnect Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_DISCONNINTMSK_NOMASK (0x1UL) /*!< No Disconnect Detected Interrupt Mask */ + +/* SESSREQINTMSK @Bit 30 : Mode: Host and Device. Session Request/New Session Detected Interrupt Mask (SessReqIntMsk) */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Pos (30UL) /*!< Position of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SESSREQINTMSK_Pos) /*!< Bit mask of SESSREQINTMSK + field.*/ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Min (0x0UL) /*!< Min enumerator value of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_Max (0x1UL) /*!< Max enumerator value of SESSREQINTMSK field. */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_MASK (0x0UL) /*!< Session Request or New Session Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_SESSREQINTMSK_NOMASK (0x1UL) /*!< No Session Request or New Session Detected Interrupt Mask */ + +/* WKUPINTMSK @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Pos (31UL) /*!< Position of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_WKUPINTMSK_Pos) /*!< Bit mask of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Min (0x0UL) /*!< Min enumerator value of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_Max (0x1UL) /*!< Max enumerator value of WKUPINTMSK field. */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_MASK (0x0UL) /*!< Resume or Remote Wakeup Detected Interrupt Mask */ + #define USBHSCORE_GINTMSK_WKUPINTMSK_NOMASK (0x1UL) /*!< Unmask Resume Remote Wakeup Detected Interrupt */ + + +/* USBHSCORE_GRXSTSR: Receive Status Debug Read Register */ + #define USBHSCORE_GRXSTSR_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSR register. */ + +/* CHNUM @Bits 0..3 : Channel Number (ChNum) */ + #define USBHSCORE_GRXSTSR_CHNUM_Pos (0UL) /*!< Position of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSR_CHNUM_Pos) /*!< Bit mask of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Min (0x0UL) /*!< Min enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_Max (0xFUL) /*!< Max enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP0 (0x0UL) /*!< Channel or EndPoint 0 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP1 (0x1UL) /*!< Channel or EndPoint 1 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP2 (0x2UL) /*!< Channel or EndPoint 2 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP3 (0x3UL) /*!< Channel or EndPoint 3 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP4 (0x4UL) /*!< Channel or EndPoint 4 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP5 (0x5UL) /*!< Channel or EndPoint 5 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP6 (0x6UL) /*!< Channel or EndPoint 6 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP7 (0x7UL) /*!< Channel or EndPoint 7 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP8 (0x8UL) /*!< Channel or EndPoint 8 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP9 (0x9UL) /*!< Channel or EndPoint 9 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP10 (0xAUL) /*!< Channel or EndPoint 10 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP11 (0xBUL) /*!< Channel or EndPoint 11 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP12 (0xCUL) /*!< Channel or EndPoint 12 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP13 (0xDUL) /*!< Channel or EndPoint 13 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP14 (0xEUL) /*!< Channel or EndPoint 14 */ + #define USBHSCORE_GRXSTSR_CHNUM_CHEP15 (0xFUL) /*!< Channel or EndPoint 15 */ + +/* BCNT @Bits 4..14 : Byte Count (BCnt) */ + #define USBHSCORE_GRXSTSR_BCNT_Pos (4UL) /*!< Position of BCNT field. */ + #define USBHSCORE_GRXSTSR_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSR_BCNT_Pos) /*!< Bit mask of BCNT field. */ + +/* DPID @Bits 15..16 : Data PID (DPID) */ + #define USBHSCORE_GRXSTSR_DPID_Pos (15UL) /*!< Position of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Msk (0x3UL << USBHSCORE_GRXSTSR_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_Max (0x3UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSR_DPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_GRXSTSR_DPID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_GRXSTSR_DPID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_GRXSTSR_DPID_MDATA (0x3UL) /*!< MDATA */ + +/* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Pos (17UL) /*!< Position of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSR_PKTSTS_Pos) /*!< Bit mask of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Min (0x1UL) /*!< Min enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_Max (0x7UL) /*!< Max enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSR_PKTSTS_OUTNAK (0x1UL) /*!< Global OUT NAK in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSR_PKTSTS_INOUTDPRX (0x2UL) /*!< IN data packet received in host mode and OUT data packet received in + device mode*/ + #define USBHSCORE_GRXSTSR_PKTSTS_INOUTTRCOM (0x3UL) /*!< IN or OUT transfer completed in both host and device mode (triggers + an interrupt)*/ + #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPCOM (0x4UL) /*!< SETUP transaction completed in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSR_PKTSTS_DTTOG (0x5UL) /*!< Data toggle error (triggers an interrupt) in host mode */ + #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPRX (0x6UL) /*!< SETUP data packet received in device mode */ + #define USBHSCORE_GRXSTSR_PKTSTS_CHHALT (0x7UL) /*!< Channel halted in host mode (triggers an interrupt) */ + +/* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */ + #define USBHSCORE_GRXSTSR_FN_Pos (21UL) /*!< Position of FN field. */ + #define USBHSCORE_GRXSTSR_FN_Msk (0xFUL << USBHSCORE_GRXSTSR_FN_Pos) /*!< Bit mask of FN field. */ + + +/* USBHSCORE_GRXSTSP: Receive Status Read/Pop Register */ + #define USBHSCORE_GRXSTSP_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSP register. */ + +/* CHNUM @Bits 0..3 : Channel Number (ChNum) */ + #define USBHSCORE_GRXSTSP_CHNUM_Pos (0UL) /*!< Position of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSP_CHNUM_Pos) /*!< Bit mask of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Min (0x0UL) /*!< Min enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_Max (0xFUL) /*!< Max enumerator value of CHNUM field. */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP0 (0x0UL) /*!< Channel or EndPoint 0 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP1 (0x1UL) /*!< Channel or EndPoint 1 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP2 (0x2UL) /*!< Channel or EndPoint 2 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP3 (0x3UL) /*!< Channel or EndPoint 3 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP4 (0x4UL) /*!< Channel or EndPoint 4 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP5 (0x5UL) /*!< Channel or EndPoint 5 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP6 (0x6UL) /*!< Channel or EndPoint 6 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP7 (0x7UL) /*!< Channel or EndPoint 7 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP8 (0x8UL) /*!< Channel or EndPoint 8 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP9 (0x9UL) /*!< Channel or EndPoint 9 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP10 (0xAUL) /*!< Channel or EndPoint 10 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP11 (0xBUL) /*!< Channel or EndPoint 11 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP12 (0xCUL) /*!< Channel or EndPoint 12 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP13 (0xDUL) /*!< Channel or EndPoint 13 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP14 (0xEUL) /*!< Channel or EndPoint 14 */ + #define USBHSCORE_GRXSTSP_CHNUM_CHEP15 (0xFUL) /*!< Channel or EndPoint 15 */ + +/* BCNT @Bits 4..14 : Byte Count (BCnt) */ + #define USBHSCORE_GRXSTSP_BCNT_Pos (4UL) /*!< Position of BCNT field. */ + #define USBHSCORE_GRXSTSP_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSP_BCNT_Pos) /*!< Bit mask of BCNT field. */ + +/* DPID @Bits 15..16 : Data PID (DPID) */ + #define USBHSCORE_GRXSTSP_DPID_Pos (15UL) /*!< Position of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Msk (0x3UL << USBHSCORE_GRXSTSP_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_Max (0x3UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_GRXSTSP_DPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_GRXSTSP_DPID_DATA2 (0x1UL) /*!< DATA2 */ + #define USBHSCORE_GRXSTSP_DPID_DATA1 (0x2UL) /*!< DATA1 */ + #define USBHSCORE_GRXSTSP_DPID_MDATA (0x3UL) /*!< MDATA */ + +/* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Pos (17UL) /*!< Position of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSP_PKTSTS_Pos) /*!< Bit mask of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Min (0x1UL) /*!< Min enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_Max (0x5UL) /*!< Max enumerator value of PKTSTS field. */ + #define USBHSCORE_GRXSTSP_PKTSTS_OUTNAK (0x1UL) /*!< Global OUT NAK in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSP_PKTSTS_INOUTDPRX (0x2UL) /*!< IN data packet received in host mode and OUT data packet received in + device mode*/ + #define USBHSCORE_GRXSTSP_PKTSTS_INOUTTRCOM (0x3UL) /*!< IN or OUT transfer completed in both host and device mode (triggers + an interrupt)*/ + #define USBHSCORE_GRXSTSP_PKTSTS_DSETUPCOM (0x4UL) /*!< SETUP transaction completed in device mode (triggers an interrupt) */ + #define USBHSCORE_GRXSTSP_PKTSTS_DTTOG (0x5UL) /*!< Data toggle error (triggers an interrupt) in host mode */ + +/* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */ + #define USBHSCORE_GRXSTSP_FN_Pos (21UL) /*!< Position of FN field. */ + #define USBHSCORE_GRXSTSP_FN_Msk (0xFUL << USBHSCORE_GRXSTSP_FN_Pos) /*!< Bit mask of FN field. */ + + +/* USBHSCORE_GRXFSIZ: Receive FIFO Size Register */ + #define USBHSCORE_GRXFSIZ_ResetValue (0x00000224UL) /*!< Reset value of GRXFSIZ register. */ + +/* RXFDEP @Bits 0..9 : Mode: Host and Device. RxFIFO Depth (RxFDep) */ + #define USBHSCORE_GRXFSIZ_RXFDEP_Pos (0UL) /*!< Position of RXFDEP field. */ + #define USBHSCORE_GRXFSIZ_RXFDEP_Msk (0x3FFUL << USBHSCORE_GRXFSIZ_RXFDEP_Pos) /*!< Bit mask of RXFDEP field. */ + + +/* USBHSCORE_GNPTXFSIZ: Non-periodic Transmit FIFO Size Register */ + #define USBHSCORE_GNPTXFSIZ_ResetValue (0x02000224UL) /*!< Reset value of GNPTXFSIZ register. */ + +/* NPTXFSTADDR @Bits 0..9 : Non-periodic Transmit RAM Start Address (NPTxFStAddr) */ + #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos (0UL) /*!< Position of NPTXFSTADDR field. */ + #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Msk (0x3FFUL << USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos) /*!< Bit mask of NPTXFSTADDR + field.*/ + +/* NPTXFDEP @Bits 16..25 : Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) */ + #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos (16UL) /*!< Position of NPTXFDEP field. */ + #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Msk (0x3FFUL << USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos) /*!< Bit mask of NPTXFDEP field. */ + + +/* USBHSCORE_GNPTXSTS: Non-periodic Transmit FIFO/Queue Status Register */ + #define USBHSCORE_GNPTXSTS_ResetValue (0x00080200UL) /*!< Reset value of GNPTXSTS register. */ + +/* NPTXFSPCAVAIL @Bits 0..15 : Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) */ + #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos (0UL) /*!< Position of NPTXFSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos) /*!< Bit mask of NPTXFSPCAVAIL + field.*/ + +/* NPTXQSPCAVAIL @Bits 16..23 : Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos (16UL) /*!< Position of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Msk (0xFFUL << USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos) /*!< Bit mask of NPTXQSPCAVAIL + field.*/ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Min (0x0UL) /*!< Min enumerator value of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Max (0x8UL) /*!< Max enumerator value of NPTXQSPCAVAIL field. */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_FULL (0x00UL) /*!< Non-periodic Transmit Request Queue is full */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE1 (0x01UL) /*!< 1 location available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE2 (0x02UL) /*!< 2 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE3 (0x03UL) /*!< 3 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE4 (0x04UL) /*!< 4 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE5 (0x05UL) /*!< 5 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE6 (0x06UL) /*!< 6 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE7 (0x07UL) /*!< 7 locations available */ + #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE8 (0x08UL) /*!< 8 locations available */ + +/* NPTXQTOP @Bits 24..30 : Top of the Non-periodic Transmit Request Queue (NPTxQTop) */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Pos (24UL) /*!< Position of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USBHSCORE_GNPTXSTS_NPTXQTOP_Pos) /*!< Bit mask of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Min (0x0UL) /*!< Min enumerator value of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_Max (0x3UL) /*!< Max enumerator value of NPTXQTOP field. */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_INOUTTK (0x00UL) /*!< IN/OUT token */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_ZEROTX (0x01UL) /*!< Zero-length transmit packet (device IN/host OUT) */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_PINGCSPLIT (0x02UL) /*!< PING/CSPLIT token */ + #define USBHSCORE_GNPTXSTS_NPTXQTOP_CHNHALT (0x03UL) /*!< Channel halt command */ + + +/* USBHSCORE_GGPIO: General Purpose Input/Output Register */ + #define USBHSCORE_GGPIO_ResetValue (0x00000000UL) /*!< Reset value of GGPIO register. */ + +/* GPI @Bits 0..15 : (unspecified) */ + #define USBHSCORE_GGPIO_GPI_Pos (0UL) /*!< Position of GPI field. */ + #define USBHSCORE_GGPIO_GPI_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPI_Pos) /*!< Bit mask of GPI field. */ + +/* GPO @Bits 16..31 : (unspecified) */ + #define USBHSCORE_GGPIO_GPO_Pos (16UL) /*!< Position of GPO field. */ + #define USBHSCORE_GGPIO_GPO_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPO_Pos) /*!< Bit mask of GPO field. */ + + +/* USBHSCORE_GUID: User ID Register */ + #define USBHSCORE_GUID_ResetValue (0x00000000UL) /*!< Reset value of GUID register. */ + +/* GUID @Bits 0..31 : User ID (UserID) Application-programmable ID field. */ + #define USBHSCORE_GUID_GUID_Pos (0UL) /*!< Position of GUID field. */ + #define USBHSCORE_GUID_GUID_Msk (0xFFFFFFFFUL << USBHSCORE_GUID_GUID_Pos) /*!< Bit mask of GUID field. */ + + +/* USBHSCORE_GSNPSID: Synopsys ID Register */ + #define USBHSCORE_GSNPSID_ResetValue (0x4F54430AUL) /*!< Reset value of GSNPSID register. */ + +/* SYNOPSYSID @Bits 0..31 : Release number of the controller being used currently. */ + #define USBHSCORE_GSNPSID_SYNOPSYSID_Pos (0UL) /*!< Position of SYNOPSYSID field. */ + #define USBHSCORE_GSNPSID_SYNOPSYSID_Msk (0xFFFFFFFFUL << USBHSCORE_GSNPSID_SYNOPSYSID_Pos) /*!< Bit mask of SYNOPSYSID + field.*/ + + +/* USBHSCORE_GHWCFG1: User Hardware Configuration 1 Register */ + #define USBHSCORE_GHWCFG1_ResetValue (0xAA555000UL) /*!< Reset value of GHWCFG1 register. */ + +/* EPDIR @Bits 0..31 : This 32-bit field uses two bits per */ + #define USBHSCORE_GHWCFG1_EPDIR_Pos (0UL) /*!< Position of EPDIR field. */ + #define USBHSCORE_GHWCFG1_EPDIR_Msk (0xFFFFFFFFUL << USBHSCORE_GHWCFG1_EPDIR_Pos) /*!< Bit mask of EPDIR field. */ + + +/* USBHSCORE_GHWCFG2: User Hardware Configuration 2 Register */ + #define USBHSCORE_GHWCFG2_ResetValue (0x228BFC72UL) /*!< Reset value of GHWCFG2 register. */ + +/* OTGMODE @Bits 0..2 : Mode of Operation (OtgMode) */ + #define USBHSCORE_GHWCFG2_OTGMODE_Pos (0UL) /*!< Position of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Msk (0x7UL << USBHSCORE_GHWCFG2_OTGMODE_Pos) /*!< Bit mask of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Min (0x0UL) /*!< Min enumerator value of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_Max (0x6UL) /*!< Max enumerator value of OTGMODE field. */ + #define USBHSCORE_GHWCFG2_OTGMODE_HNPSRP (0x0UL) /*!< HNP- and SRP-Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPOTG (0x1UL) /*!< SRP-Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_NHNPNSRP (0x2UL) /*!< Non-HNP and Non-SRP Capable OTG (Host and Device) */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPD (0x3UL) /*!< SRP-Capable Device */ + #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGD (0x4UL) /*!< Non-OTG Device */ + #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPH (0x5UL) /*!< SRP-Capable Host */ + #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGH (0x6UL) /*!< Non-OTG Host */ + +/* OTGARCH @Bits 3..4 : Architecture (OtgArch) */ + #define USBHSCORE_GHWCFG2_OTGARCH_Pos (3UL) /*!< Position of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Msk (0x3UL << USBHSCORE_GHWCFG2_OTGARCH_Pos) /*!< Bit mask of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Min (0x0UL) /*!< Min enumerator value of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_Max (0x2UL) /*!< Max enumerator value of OTGARCH field. */ + #define USBHSCORE_GHWCFG2_OTGARCH_SLAVEMODE (0x0UL) /*!< Slave Mode */ + #define USBHSCORE_GHWCFG2_OTGARCH_EXTERNALDMA (0x1UL) /*!< External DMA Mode */ + #define USBHSCORE_GHWCFG2_OTGARCH_INTERNALDMA (0x2UL) /*!< Internal DMA Mode */ + +/* SINGPNT @Bit 5 : Point-to-Point (SingPnt) */ + #define USBHSCORE_GHWCFG2_SINGPNT_Pos (5UL) /*!< Position of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Msk (0x1UL << USBHSCORE_GHWCFG2_SINGPNT_Pos) /*!< Bit mask of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Min (0x0UL) /*!< Min enumerator value of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_Max (0x1UL) /*!< Max enumerator value of SINGPNT field. */ + #define USBHSCORE_GHWCFG2_SINGPNT_MULTIPOINT (0x0UL) /*!< Multi-point application (hub and split support) */ + #define USBHSCORE_GHWCFG2_SINGPNT_SINGLEPOINT (0x1UL) /*!< Single-point application (no hub and split support) */ + +/* HSPHYTYPE @Bits 6..7 : High-Speed PHY Interface Type (HSPhyType) */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Pos (6UL) /*!< Position of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_HSPHYTYPE_Pos) /*!< Bit mask of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Min (0x0UL) /*!< Min enumerator value of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_Max (0x3UL) /*!< Max enumerator value of HSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_NOHS (0x0UL) /*!< High-Speed interface not supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPLUS (0x1UL) /*!< High Speed Interface UTMI+ is supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_ULPI (0x2UL) /*!< High Speed Interface ULPI is supported */ + #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPUSULPI (0x3UL) /*!< High Speed Interfaces UTMI+ and ULPI is supported */ + +/* FSPHYTYPE @Bits 8..9 : Full-Speed PHY Interface Type (FSPhyType) */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Pos (8UL) /*!< Position of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_FSPHYTYPE_Pos) /*!< Bit mask of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Min (0x0UL) /*!< Min enumerator value of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_Max (0x3UL) /*!< Max enumerator value of FSPHYTYPE field. */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_NO_FS (0x0UL) /*!< Full-speed interface not supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FS (0x1UL) /*!< Dedicated full-speed interface is supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSUTMI (0x2UL) /*!< FS pins shared with UTMI+ pins is supported */ + #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSULPI (0x3UL) /*!< FS pins shared with ULPI pins is supported */ + +/* NUMDEVEPS @Bits 10..13 : Number of Device Endpoints (NumDevEps) */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Pos (10UL) /*!< Position of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMDEVEPS_Pos) /*!< Bit mask of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Min (0x0UL) /*!< Min enumerator value of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_Max (0xFUL) /*!< Max enumerator value of NUMDEVEPS field. */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* NUMHSTCHNL @Bits 14..17 : Number of Host Channels (NumHstChnl) */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos (14UL) /*!< Position of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos) /*!< Bit mask of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Min (0x0UL) /*!< Min enumerator value of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Max (0xFUL) /*!< Max enumerator value of NUMHSTCHNL field. */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH0 (0x0UL) /*!< Host Channel 1 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH1 (0x1UL) /*!< Host Channel 2 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH2 (0x2UL) /*!< Host Channel 3 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH3 (0x3UL) /*!< Host Channel 4 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH4 (0x4UL) /*!< Host Channel 5 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH5 (0x5UL) /*!< Host Channel 6 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH6 (0x6UL) /*!< Host Channel 7 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH7 (0x7UL) /*!< Host Channel 8 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH8 (0x8UL) /*!< Host Channel 9 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH9 (0x9UL) /*!< Host Channel 10 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH10 (0xAUL) /*!< Host Channel 11 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH11 (0xBUL) /*!< Host Channel 12 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH12 (0xCUL) /*!< Host Channel 13 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH13 (0xDUL) /*!< Host Channel 14 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH14 (0xEUL) /*!< Host Channel 15 */ + #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH15 (0xFUL) /*!< Host Channel 16 */ + +/* PERIOSUPPORT @Bit 18 : Periodic OUT Channels Supported in Host Mode (PerioSupport) */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos (18UL) /*!< Position of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos) /*!< Bit mask of PERIOSUPPORT field.*/ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Min (0x0UL) /*!< Min enumerator value of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Max (0x1UL) /*!< Max enumerator value of PERIOSUPPORT field. */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_DISABLED (0x0UL) /*!< Periodic OUT Channels is not supported in Host Mode */ + #define USBHSCORE_GHWCFG2_PERIOSUPPORT_ENABLED (0x1UL) /*!< Periodic OUT Channels Supported in Host Mode Supported */ + +/* DYNFIFOSIZING @Bit 19 : Dynamic FIFO Sizing Enabled (DynFifoSizing) */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos (19UL) /*!< Position of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Msk (0x1UL << USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos) /*!< Bit mask of DYNFIFOSIZING + field.*/ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Min (0x0UL) /*!< Min enumerator value of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Max (0x1UL) /*!< Max enumerator value of DYNFIFOSIZING field. */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_DISABLED (0x0UL) /*!< Dynamic FIFO Sizing Disabled */ + #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_ENABLED (0x1UL) /*!< Dynamic FIFO Sizing Enabled */ + +/* MULTIPROCINTRPT @Bit 20 : Multi Processor Interrupt Enabled (MultiProcIntrpt) */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos (20UL) /*!< Position of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Msk (0x1UL << USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos) /*!< Bit mask of + MULTIPROCINTRPT field.*/ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Min (0x0UL) /*!< Min enumerator value of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Max (0x1UL) /*!< Max enumerator value of MULTIPROCINTRPT field. */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_DISABLED (0x0UL) /*!< No Multi Processor Interrupt Enabled */ + #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_ENABLED (0x1UL) /*!< Multi Processor Interrupt Enabled */ + +/* NPTXQDEPTH @Bits 22..23 : Non-periodic Request Queue Depth (NPTxQDepth) */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos (22UL) /*!< Position of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos) /*!< Bit mask of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Min (0x0UL) /*!< Min enumerator value of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Max (0x2UL) /*!< Max enumerator value of NPTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_TWO (0x0UL) /*!< Queue size 2 */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_FOUR (0x1UL) /*!< Queue size 4 */ + #define USBHSCORE_GHWCFG2_NPTXQDEPTH_EIGHT (0x2UL) /*!< Queue size 8 */ + +/* PTXQDEPTH @Bits 24..25 : Host Mode Periodic Request Queue Depth (PTxQDepth) */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Pos (24UL) /*!< Position of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_PTXQDEPTH_Pos) /*!< Bit mask of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Min (0x0UL) /*!< Min enumerator value of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_Max (0x3UL) /*!< Max enumerator value of PTXQDEPTH field. */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE2 (0x0UL) /*!< Queue Depth 2 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE4 (0x1UL) /*!< Queue Depth 4 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE8 (0x2UL) /*!< Queue Depth 8 */ + #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE16 (0x3UL) /*!< Queue Depth 16 */ + +/* TKNQDEPTH @Bits 26..30 : Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) */ + #define USBHSCORE_GHWCFG2_TKNQDEPTH_Pos (26UL) /*!< Position of TKNQDEPTH field. */ + #define USBHSCORE_GHWCFG2_TKNQDEPTH_Msk (0x1FUL << USBHSCORE_GHWCFG2_TKNQDEPTH_Pos) /*!< Bit mask of TKNQDEPTH field. */ + + +/* USBHSCORE_GHWCFG3: User Hardware Configuration 3 Register */ + #define USBHSCORE_GHWCFG3_ResetValue (0x0BEAC0E8UL) /*!< Reset value of GHWCFG3 register. */ + +/* XFERSIZEWIDTH @Bits 0..3 : Width of Transfer Size Counters (XferSizeWidth) */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos (0UL) /*!< Position of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Msk (0xFUL << USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos) /*!< Bit mask of XFERSIZEWIDTH + field.*/ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Max (0x8UL) /*!< Max enumerator value of XFERSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH11 (0x0UL) /*!< Width of Transfer Size Counter 11 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH12 (0x1UL) /*!< Width of Transfer Size Counter 12 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH13 (0x2UL) /*!< Width of Transfer Size Counter 13 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH14 (0x3UL) /*!< Width of Transfer Size Counter 14 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH15 (0x4UL) /*!< Width of Transfer Size Counter 15 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH16 (0x5UL) /*!< Width of Transfer Size Counter 16 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH17 (0x6UL) /*!< Width of Transfer Size Counter 17 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH18 (0x7UL) /*!< Width of Transfer Size Counter 18 bits */ + #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH19 (0x8UL) /*!< Width of Transfer Size Counter 19 bits */ + +/* PKTSIZEWIDTH @Bits 4..6 : Width of Packet Size Counters (PktSizeWidth) */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos (4UL) /*!< Position of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Msk (0x7UL << USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos) /*!< Bit mask of PKTSIZEWIDTH field.*/ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Max (0x6UL) /*!< Max enumerator value of PKTSIZEWIDTH field. */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS4 (0x0UL) /*!< Width of Packet Size Counter 4 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS5 (0x1UL) /*!< Width of Packet Size Counter 5 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS6 (0x2UL) /*!< Width of Packet Size Counter 6 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS7 (0x3UL) /*!< Width of Packet Size Counter 7 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS8 (0x4UL) /*!< Width of Packet Size Counter 8 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS9 (0x5UL) /*!< Width of Packet Size Counter 9 */ + #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS10 (0x6UL) /*!< Width of Packet Size Counter 10 */ + +/* OTGEN @Bit 7 : OTG Function Enabled (OtgEn) */ + #define USBHSCORE_GHWCFG3_OTGEN_Pos (7UL) /*!< Position of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Msk (0x1UL << USBHSCORE_GHWCFG3_OTGEN_Pos) /*!< Bit mask of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Min (0x0UL) /*!< Min enumerator value of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_Max (0x1UL) /*!< Max enumerator value of OTGEN field. */ + #define USBHSCORE_GHWCFG3_OTGEN_DISABLED (0x0UL) /*!< Not OTG Capable */ + #define USBHSCORE_GHWCFG3_OTGEN_ENABLED (0x1UL) /*!< OTG Capable */ + +/* I2CINTSEL @Bit 8 : I2C Selection (I2CIntSel) */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Pos (8UL) /*!< Position of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Msk (0x1UL << USBHSCORE_GHWCFG3_I2CINTSEL_Pos) /*!< Bit mask of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Min (0x0UL) /*!< Min enumerator value of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_Max (0x1UL) /*!< Max enumerator value of I2CINTSEL field. */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_DISABLED (0x0UL) /*!< I2C Interface is not available */ + #define USBHSCORE_GHWCFG3_I2CINTSEL_ENABLED (0x1UL) /*!< I2C Interface is available */ + +/* VNDCTLSUPT @Bit 9 : Vendor Control Interface Support (VndctlSupt) */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos (9UL) /*!< Position of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Msk (0x1UL << USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos) /*!< Bit mask of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Min (0x0UL) /*!< Min enumerator value of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Max (0x1UL) /*!< Max enumerator value of VNDCTLSUPT field. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_DISABLED (0x0UL) /*!< Vendor Control Interface is not available. */ + #define USBHSCORE_GHWCFG3_VNDCTLSUPT_ENABLED (0x1UL) /*!< Vendor Control Interface is available. */ + +/* OPTFEATURE @Bit 10 : Optional Features Removed (OptFeature) */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Pos (10UL) /*!< Position of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Msk (0x1UL << USBHSCORE_GHWCFG3_OPTFEATURE_Pos) /*!< Bit mask of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Min (0x0UL) /*!< Min enumerator value of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_Max (0x1UL) /*!< Max enumerator value of OPTFEATURE field. */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_DISABLED (0x0UL) /*!< Optional features were not Removed */ + #define USBHSCORE_GHWCFG3_OPTFEATURE_ENABLED (0x1UL) /*!< Optional Features have been Removed */ + +/* RSTTYPE @Bit 11 : Reset Style for Clocked always Blocks in RTL (RstType) */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Pos (11UL) /*!< Position of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Msk (0x1UL << USBHSCORE_GHWCFG3_RSTTYPE_Pos) /*!< Bit mask of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Min (0x0UL) /*!< Min enumerator value of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_Max (0x1UL) /*!< Max enumerator value of RSTTYPE field. */ + #define USBHSCORE_GHWCFG3_RSTTYPE_ASYNCRST (0x0UL) /*!< Asynchronous reset is used in the core */ + #define USBHSCORE_GHWCFG3_RSTTYPE_SYNCRST (0x1UL) /*!< Synchronous reset is used in the core */ + +/* ADPSUPPORT @Bit 12 : This bit indicates whether ADP logic is present within or external to the controller */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Pos (12UL) /*!< Position of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_ADPSUPPORT_Pos) /*!< Bit mask of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Min (0x0UL) /*!< Min enumerator value of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_Max (0x1UL) /*!< Max enumerator value of ADPSUPPORT field. */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_DISABLED (0x0UL) /*!< ADP logic is not present along with the controller */ + #define USBHSCORE_GHWCFG3_ADPSUPPORT_ENABLED (0x1UL) /*!< ADP logic is present along with the controller */ + +/* HSICMODE @Bit 13 : HSIC mode specified for Mode of Operation */ + #define USBHSCORE_GHWCFG3_HSICMODE_Pos (13UL) /*!< Position of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_HSICMODE_Pos) /*!< Bit mask of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Min (0x0UL) /*!< Min enumerator value of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_Max (0x1UL) /*!< Max enumerator value of HSICMODE field. */ + #define USBHSCORE_GHWCFG3_HSICMODE_DISABLED (0x0UL) /*!< No HSIC capability */ + #define USBHSCORE_GHWCFG3_HSICMODE_ENABLED (0x1UL) /*!< HSIC-capable with shared UTMI PHY interface */ + +/* BCSUPPORT @Bit 14 : This bit indicates the controller support for Battery Charger. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Pos (14UL) /*!< Position of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_BCSUPPORT_Pos) /*!< Bit mask of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Min (0x0UL) /*!< Min enumerator value of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_Max (0x1UL) /*!< Max enumerator value of BCSUPPORT field. */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_DISABLED (0x0UL) /*!< No Battery Charger Support */ + #define USBHSCORE_GHWCFG3_BCSUPPORT_ENABLED (0x1UL) /*!< Battery Charger Support present */ + +/* LPMMODE @Bit 15 : LPM mode specified for Mode of Operation. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Pos (15UL) /*!< Position of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_LPMMODE_Pos) /*!< Bit mask of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Min (0x0UL) /*!< Min enumerator value of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_Max (0x1UL) /*!< Max enumerator value of LPMMODE field. */ + #define USBHSCORE_GHWCFG3_LPMMODE_DISABLED (0x0UL) /*!< LPM disabled */ + #define USBHSCORE_GHWCFG3_LPMMODE_ENABLED (0x1UL) /*!< LPM enabled */ + +/* DFIFODEPTH @Bits 16..31 : DFIFO Depth (DfifoDepth - EP_LOC_CNT) */ + #define USBHSCORE_GHWCFG3_DFIFODEPTH_Pos (16UL) /*!< Position of DFIFODEPTH field. */ + #define USBHSCORE_GHWCFG3_DFIFODEPTH_Msk (0xFFFFUL << USBHSCORE_GHWCFG3_DFIFODEPTH_Pos) /*!< Bit mask of DFIFODEPTH field. */ + + +/* USBHSCORE_GHWCFG4: User Hardware Configuration 4 Register */ + #define USBHSCORE_GHWCFG4_ResetValue (0x1E10AA60UL) /*!< Reset value of GHWCFG4 register. */ + +/* NUMDEVPERIOEPS @Bits 0..3 : Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos (0UL) /*!< Position of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos) /*!< Bit mask of NUMDEVPERIOEPS + field.*/ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Min (0x0UL) /*!< Min enumerator value of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Max (0xFUL) /*!< Max enumerator value of NUMDEVPERIOEPS field. */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value0 (0x0UL) /*!< Number of Periodic IN EPs is 0 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value1 (0x1UL) /*!< Number of Periodic IN EPs is 1 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value2 (0x2UL) /*!< Number of Periodic IN EPs is 2 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value3 (0x3UL) /*!< Number of Periodic IN EPs is 3 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value4 (0x4UL) /*!< Number of Periodic IN EPs is 4 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value5 (0x5UL) /*!< Number of Periodic IN EPs is 5 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value6 (0x6UL) /*!< Number of Periodic IN EPs is 6 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value7 (0x7UL) /*!< Number of Periodic IN EPs is 7 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value8 (0x8UL) /*!< Number of Periodic IN EPs is 8 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value9 (0x9UL) /*!< Number of Periodic IN EPs is 9 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value10 (0xAUL) /*!< Number of Periodic IN EPs is 10 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value11 (0xBUL) /*!< Number of Periodic IN EPs is 11 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value12 (0xCUL) /*!< Number of Periodic IN EPs is 12 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value13 (0xDUL) /*!< Number of Periodic IN EPs is 13 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value14 (0xEUL) /*!< Number of Periodic IN EPs is 14 */ + #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value15 (0xFUL) /*!< Number of Periodic IN EPs is 15 */ + +/* PARTIALPWRDN @Bit 4 : Enable Partial Power Down (PartialPwrDn) */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos (4UL) /*!< Position of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Msk (0x1UL << USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos) /*!< Bit mask of PARTIALPWRDN field.*/ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Min (0x0UL) /*!< Min enumerator value of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Max (0x1UL) /*!< Max enumerator value of PARTIALPWRDN field. */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_DISABLED (0x0UL) /*!< Partial Power Down disabled */ + #define USBHSCORE_GHWCFG4_PARTIALPWRDN_ENABLED (0x1UL) /*!< Partial Power Down enabled */ + +/* AHBFREQ @Bit 5 : Minimum AHB Frequency Less Than 60 MHz (AhbFreq) */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Pos (5UL) /*!< Position of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Msk (0x1UL << USBHSCORE_GHWCFG4_AHBFREQ_Pos) /*!< Bit mask of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Min (0x0UL) /*!< Min enumerator value of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_Max (0x1UL) /*!< Max enumerator value of AHBFREQ field. */ + #define USBHSCORE_GHWCFG4_AHBFREQ_DISABLED (0x0UL) /*!< Minimum AHB Frequency More Than 60 MHz */ + #define USBHSCORE_GHWCFG4_AHBFREQ_ENABLED (0x1UL) /*!< Minimum AHB Frequency Less Than 60 MHz */ + +/* HIBERNATION @Bit 6 : Enable Hibernation (Hibernation) */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Pos (6UL) /*!< Position of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_HIBERNATION_Pos) /*!< Bit mask of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Min (0x0UL) /*!< Min enumerator value of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_Max (0x1UL) /*!< Max enumerator value of HIBERNATION field. */ + #define USBHSCORE_GHWCFG4_HIBERNATION_DISABLED (0x0UL) /*!< Hibernation feature disabled */ + #define USBHSCORE_GHWCFG4_HIBERNATION_ENABLED (0x1UL) /*!< Hibernation feature enabled */ + +/* EXTENDEDHIBERNATION @Bit 7 : Enable Hibernation */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos (7UL) /*!< Position of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos) /*!< Bit mask of + EXTENDEDHIBERNATION field.*/ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Min (0x0UL) /*!< Min enumerator value of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Max (0x1UL) /*!< Max enumerator value of EXTENDEDHIBERNATION field. */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_DISABLED (0x0UL) /*!< Extended Hibernation feature not enabled */ + #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_ENABLED (0x1UL) /*!< Extended Hibernation feature enabled */ + +/* ENHANCEDLPMSUPT1 @Bit 9 : Enhanced LPM Support1 (EnhancedLPMSupt1) */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos (9UL) /*!< Position of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos) /*!< Bit mask of + ENHANCEDLPMSUPT1 field.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Min (0x0UL) /*!< Min enumerator value of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT1 field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_DISABLED (0x0UL) /*!< Reject L1 Request even if Non-Periodic (Bulk/Interrupt) + TxFIFO is not empty.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_ENABLED (0x1UL) /*!< Accept L1 Request even if Non-Periodic (Bulk/Interrupt) TxFIFO + is not empty*/ + +/* SERVINTFLOW @Bit 10 : Service Interval Flow */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Pos (10UL) /*!< Position of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Msk (0x1UL << USBHSCORE_GHWCFG4_SERVINTFLOW_Pos) /*!< Bit mask of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Min (0x0UL) /*!< Min enumerator value of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_Max (0x1UL) /*!< Max enumerator value of SERVINTFLOW field. */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_DISABLED (0x0UL) /*!< Service Interval Flow not supported */ + #define USBHSCORE_GHWCFG4_SERVINTFLOW_ENABLED (0x1UL) /*!< Service Interval Flow supported */ + +/* IPGISOCSUPT @Bit 11 : Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos (11UL) /*!< Position of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Min (0x0UL) /*!< Min enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Max (0x1UL) /*!< Max enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_DISABLED (0x0UL) /*!< Interpacket Gap ISOC OUT Worst-case Support is Disabled */ + #define USBHSCORE_GHWCFG4_IPGISOCSUPT_ENABLED (0x1UL) /*!< Interpacket Gap ISOC OUT Worst-case Support is Enabled (Default) */ + +/* ACGSUPT @Bit 12 : Active Clock Gating Support */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Pos (12UL) /*!< Position of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ACGSUPT_Pos) /*!< Bit mask of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Min (0x0UL) /*!< Min enumerator value of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_Max (0x1UL) /*!< Max enumerator value of ACGSUPT field. */ + #define USBHSCORE_GHWCFG4_ACGSUPT_DISABLED (0x0UL) /*!< (unspecified) */ + #define USBHSCORE_GHWCFG4_ACGSUPT_ENABLED (0x1UL) /*!< Active Clock Gating Support */ + +/* ENHANCEDLPMSUPT @Bit 13 : Enhanced LPM Support (EnhancedLPMSupt) */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos (13UL) /*!< Position of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos) /*!< Bit mask of + ENHANCEDLPMSUPT field.*/ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Min (0x1UL) /*!< Min enumerator value of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT field. */ + #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_ENABLED (0x1UL) /*!< Enhanced LPM Support is enabled */ + +/* PHYDATAWIDTH @Bits 14..15 : UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos (14UL) /*!< Position of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Msk (0x3UL << USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos) /*!< Bit mask of PHYDATAWIDTH field.*/ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Max (0x2UL) /*!< Max enumerator value of PHYDATAWIDTH field. */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH1 (0x0UL) /*!< 8 bits */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH2 (0x1UL) /*!< 16 bits */ + #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH3 (0x2UL) /*!< 8/16 bits, software selectable */ + +/* NUMCTLEPS @Bits 16..19 : Number of Device Mode Control Endpoints in Addition to */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Pos (16UL) /*!< Position of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMCTLEPS_Pos) /*!< Bit mask of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Min (0x0UL) /*!< Min enumerator value of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_Max (0xFUL) /*!< Max enumerator value of NUMCTLEPS field. */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT0 (0x0UL) /*!< End point 0 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT1 (0x1UL) /*!< End point 1 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT2 (0x2UL) /*!< End point 2 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT3 (0x3UL) /*!< End point 3 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT4 (0x4UL) /*!< End point 4 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT5 (0x5UL) /*!< End point 5 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT6 (0x6UL) /*!< End point 6 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT7 (0x7UL) /*!< End point 7 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT8 (0x8UL) /*!< End point 8 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT9 (0x9UL) /*!< End point 9 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT10 (0xAUL) /*!< End point 10 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT11 (0xBUL) /*!< End point 11 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT12 (0xCUL) /*!< End point 12 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT13 (0xDUL) /*!< End point 13 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT14 (0xEUL) /*!< End point 14 */ + #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT15 (0xFUL) /*!< End point 15 */ + +/* IDDGFLTR @Bit 20 : IDDIG Filter Enable (IddgFltr) */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Pos (20UL) /*!< Position of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_IDDGFLTR_Pos) /*!< Bit mask of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Min (0x0UL) /*!< Min enumerator value of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_Max (0x1UL) /*!< Max enumerator value of IDDGFLTR field. */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_DISABLED (0x0UL) /*!< Iddig Filter Disabled */ + #define USBHSCORE_GHWCFG4_IDDGFLTR_ENABLED (0x1UL) /*!< Iddig Filter Enabled */ + +/* VBUSVALIDFLTR @Bit 21 : VBUS Valid Filter Enabled (VBusValidFltr) */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos (21UL) /*!< Position of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos) /*!< Bit mask of VBUSVALIDFLTR + field.*/ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of VBUSVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_DISABLED (0x0UL) /*!< Vbus Valid Filter Disabled */ + #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_ENABLED (0x1UL) /*!< Vbus Valid Filter Enabled */ + +/* AVALIDFLTR @Bit 22 : a_valid Filter Enabled (AValidFltr) */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Pos (22UL) /*!< Position of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_AVALIDFLTR_Pos) /*!< Bit mask of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of AVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_DISABLED (0x0UL) /*!< No filter */ + #define USBHSCORE_GHWCFG4_AVALIDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* BVALIDFLTR @Bit 23 : b_valid Filter Enabled (BValidFltr) */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Pos (23UL) /*!< Position of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_BVALIDFLTR_Pos) /*!< Bit mask of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of BVALIDFLTR field. */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_DISABLED (0x0UL) /*!< No Filter */ + #define USBHSCORE_GHWCFG4_BVALIDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* SESSENDFLTR @Bit 24 : session_end Filter Enabled (SessEndFltr) */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Pos (24UL) /*!< Position of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_SESSENDFLTR_Pos) /*!< Bit mask of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Min (0x0UL) /*!< Min enumerator value of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_Max (0x1UL) /*!< Max enumerator value of SESSENDFLTR field. */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_DISABLED (0x0UL) /*!< No filter */ + #define USBHSCORE_GHWCFG4_SESSENDFLTR_ENABLED (0x1UL) /*!< Filter */ + +/* DEDFIFOMODE @Bit 25 : Enable Dedicated Transmit FIFO for device IN Endpoints */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos (25UL) /*!< Position of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Msk (0x1UL << USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos) /*!< Bit mask of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Min (0x0UL) /*!< Min enumerator value of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Max (0x1UL) /*!< Max enumerator value of DEDFIFOMODE field. */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_DISABLED (0x0UL) /*!< Dedicated Transmit FIFO Operation not enabled */ + #define USBHSCORE_GHWCFG4_DEDFIFOMODE_ENABLED (0x1UL) /*!< Dedicated Transmit FIFO Operation enabled */ + +/* INEPS @Bits 26..29 : Number of Device Mode IN Endpoints Including Control Endpoints (INEps) */ + #define USBHSCORE_GHWCFG4_INEPS_Pos (26UL) /*!< Position of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_INEPS_Pos) /*!< Bit mask of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Min (0x0UL) /*!< Min enumerator value of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_Max (0xFUL) /*!< Max enumerator value of INEPS field. */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT1 (0x0UL) /*!< 1 IN Endpoint */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT2 (0x1UL) /*!< 2 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT3 (0x2UL) /*!< 3 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT4 (0x3UL) /*!< 4 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT5 (0x4UL) /*!< 5 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT6 (0x5UL) /*!< 6 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT7 (0x6UL) /*!< 7 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT8 (0x7UL) /*!< 8 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT9 (0x8UL) /*!< 9 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT10 (0x9UL) /*!< 10 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT11 (0xAUL) /*!< 11 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT12 (0xBUL) /*!< 12 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT13 (0xCUL) /*!< 13 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT14 (0xDUL) /*!< 14 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT15 (0xEUL) /*!< 15 IN Endpoints */ + #define USBHSCORE_GHWCFG4_INEPS_ENDPT16 (0xFUL) /*!< 16 IN Endpoints */ + +/* DESCDMAENABLED @Bit 30 : Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos (30UL) /*!< Position of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos) /*!< Bit mask of DESCDMAENABLED + field.*/ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Min (0x0UL) /*!< Min enumerator value of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Max (0x1UL) /*!< Max enumerator value of DESCDMAENABLED field. */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_DISABLE (0x0UL) /*!< Non-Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMAENABLED_ENABLE (0x1UL) /*!< Scatter/Gather DMA configuration */ + +/* DESCDMA @Bit 31 : Scatter/Gather DMA configuration */ + #define USBHSCORE_GHWCFG4_DESCDMA_Pos (31UL) /*!< Position of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMA_Pos) /*!< Bit mask of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Min (0x0UL) /*!< Min enumerator value of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_Max (0x1UL) /*!< Max enumerator value of DESCDMA field. */ + #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG1 (0x0UL) /*!< Non Dynamic configuration */ + #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG2 (0x1UL) /*!< Dynamic configuration */ + + +/* USBHSCORE_GLPMCFG: LPM Config Register */ + #define USBHSCORE_GLPMCFG_ResetValue (0x00000000UL) /*!< Reset value of GLPMCFG register. */ + +/* LPMCAP @Bit 0 : LPM-Capable (LPMCap) */ + #define USBHSCORE_GLPMCFG_LPMCAP_Pos (0UL) /*!< Position of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMCAP_Pos) /*!< Bit mask of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Min (0x0UL) /*!< Min enumerator value of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_Max (0x1UL) /*!< Max enumerator value of LPMCAP field. */ + #define USBHSCORE_GLPMCFG_LPMCAP_DISABLED (0x0UL) /*!< LPM capability is not enabled */ + #define USBHSCORE_GLPMCFG_LPMCAP_ENABLED (0x1UL) /*!< LPM capability is enabled */ + +/* APPL1RES @Bit 1 : Mode: Device only. LPM response programmed by application (AppL1Res) */ + #define USBHSCORE_GLPMCFG_APPL1RES_Pos (1UL) /*!< Position of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Msk (0x1UL << USBHSCORE_GLPMCFG_APPL1RES_Pos) /*!< Bit mask of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Min (0x0UL) /*!< Min enumerator value of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_Max (0x1UL) /*!< Max enumerator value of APPL1RES field. */ + #define USBHSCORE_GLPMCFG_APPL1RES_NYET_RESP (0x0UL) /*!< The core responds with a NYET when an error is detected in either of + the LPM token packets due to corruption*/ + #define USBHSCORE_GLPMCFG_APPL1RES_ACK_RESP (0x1UL) /*!< The core responds with an ACK only on a successful LPM transaction */ + +/* HIRD @Bits 2..5 : Host-Initiated Resume Duration (HIRD) */ + #define USBHSCORE_GLPMCFG_HIRD_Pos (2UL) /*!< Position of HIRD field. */ + #define USBHSCORE_GLPMCFG_HIRD_Msk (0xFUL << USBHSCORE_GLPMCFG_HIRD_Pos) /*!< Bit mask of HIRD field. */ + +/* BREMOTEWAKE @Bit 6 : RemoteWakeEnable (bRemoteWake) */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos (6UL) /*!< Position of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Msk (0x1UL << USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos) /*!< Bit mask of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Min (0x0UL) /*!< Min enumerator value of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Max (0x1UL) /*!< Max enumerator value of BREMOTEWAKE field. */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_DISABLED (0x0UL) /*!< Remote Wakeup is disabled */ + #define USBHSCORE_GLPMCFG_BREMOTEWAKE_ENABLED (0x1UL) /*!< In Host or device mode, this field takes the value of remote wake + up*/ + +/* ENBLSLPM @Bit 7 : Enable utmi_sleep_n (EnblSlpM) */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Pos (7UL) /*!< Position of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_ENBLSLPM_Pos) /*!< Bit mask of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Min (0x0UL) /*!< Min enumerator value of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_Max (0x1UL) /*!< Max enumerator value of ENBLSLPM field. */ + #define USBHSCORE_GLPMCFG_ENBLSLPM_DISABLED (0x0UL) /*!< utmi_sleep_n assertion from the core is not transferred to the + external PHY*/ + #define USBHSCORE_GLPMCFG_ENBLSLPM_ENABLED (0x1UL) /*!< utmi_sleep_n assertion from the core is transferred to the external + PHY when utmi_l1_suspend_n cannot be asserted*/ + +/* HIRDTHRES @Bits 8..12 : BESL/HIRD Threshold (HIRD_Thres) */ + #define USBHSCORE_GLPMCFG_HIRDTHRES_Pos (8UL) /*!< Position of HIRDTHRES field. */ + #define USBHSCORE_GLPMCFG_HIRDTHRES_Msk (0x1FUL << USBHSCORE_GLPMCFG_HIRDTHRES_Pos) /*!< Bit mask of HIRDTHRES field. */ + +/* COREL1RES @Bits 13..14 : LPM Response (CoreL1Res) */ + #define USBHSCORE_GLPMCFG_COREL1RES_Pos (13UL) /*!< Position of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Msk (0x3UL << USBHSCORE_GLPMCFG_COREL1RES_Pos) /*!< Bit mask of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Min (0x0UL) /*!< Min enumerator value of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_Max (0x3UL) /*!< Max enumerator value of COREL1RES field. */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP1 (0x0UL) /*!< ERROR : No handshake response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP2 (0x1UL) /*!< STALL response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP3 (0x2UL) /*!< NYET response */ + #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP4 (0x3UL) /*!< ACK response */ + +/* SLPSTS @Bit 15 : Port Sleep Status (SlpSts) */ + #define USBHSCORE_GLPMCFG_SLPSTS_Pos (15UL) /*!< Position of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_SLPSTS_Pos) /*!< Bit mask of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Min (0x0UL) /*!< Min enumerator value of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_Max (0x1UL) /*!< Max enumerator value of SLPSTS field. */ + #define USBHSCORE_GLPMCFG_SLPSTS_CORE_NOT_IN_L1 (0x0UL) /*!< In Host or Device mode, this bit indicates core is not in L1 */ + #define USBHSCORE_GLPMCFG_SLPSTS_CORE_IN_L1 (0x1UL) /*!< In Host mode, this bit indicates the core transitions to Sleep state + as a successful LPM transaction. In Device mode, the core enters the + Sleep state when an ACK response is sent to an LPM transaction*/ + +/* L1RESUMEOK @Bit 16 : Sleep State Resume OK (L1ResumeOK) */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Pos (16UL) /*!< Position of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Msk (0x1UL << USBHSCORE_GLPMCFG_L1RESUMEOK_Pos) /*!< Bit mask of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Min (0x0UL) /*!< Min enumerator value of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_Max (0x1UL) /*!< Max enumerator value of L1RESUMEOK field. */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_NOTOK (0x0UL) /*!< The application/core cannot start Resume from Sleep state */ + #define USBHSCORE_GLPMCFG_L1RESUMEOK_OK (0x1UL) /*!< The application/core can start Resume from Sleep state */ + +/* LPMCHNLINDX @Bits 17..20 : LPM Channel Index */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos (17UL) /*!< Position of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Msk (0xFUL << USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos) /*!< Bit mask of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Min (0x0UL) /*!< Min enumerator value of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Max (0xFUL) /*!< Max enumerator value of LPMCHNLINDX field. */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH0 (0x0UL) /*!< Channel 0 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH1 (0x1UL) /*!< Channel 1 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH2 (0x2UL) /*!< Channel 2 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH3 (0x3UL) /*!< Channel 3 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH4 (0x4UL) /*!< Channel 4 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH5 (0x5UL) /*!< Channel 5 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH6 (0x6UL) /*!< Channel 6 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH7 (0x7UL) /*!< Channel 7 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH8 (0x8UL) /*!< Channel 8 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH9 (0x9UL) /*!< Channel 9 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH10 (0xAUL) /*!< Channel 10 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH11 (0xBUL) /*!< Channel 11 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH12 (0xCUL) /*!< Channel 12 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH13 (0xDUL) /*!< Channel 13 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH14 (0xEUL) /*!< Channel 14 */ + #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH15 (0xFUL) /*!< Channel15 */ + +/* LPMRETRYCNT @Bits 21..23 : LPM Retry Count (LPM_Retry_Cnt) */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos (21UL) /*!< Position of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos) /*!< Bit mask of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Min (0x0UL) /*!< Min enumerator value of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Max (0x7UL) /*!< Max enumerator value of LPMRETRYCNT field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY0 (0x0UL) /*!< Zero LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY1 (0x1UL) /*!< One LPM retry */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY2 (0x2UL) /*!< Two LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY3 (0x3UL) /*!< Three LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY4 (0x4UL) /*!< Four LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY5 (0x5UL) /*!< Five LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY6 (0x6UL) /*!< Six LPM retries */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY7 (0x7UL) /*!< Seven LPM retries */ + +/* SNDLPM @Bit 24 : Send LPM Transaction (SndLPM) */ + #define USBHSCORE_GLPMCFG_SNDLPM_Pos (24UL) /*!< Position of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_SNDLPM_Pos) /*!< Bit mask of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Min (0x0UL) /*!< Min enumerator value of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_Max (0x1UL) /*!< Max enumerator value of SNDLPM field. */ + #define USBHSCORE_GLPMCFG_SNDLPM_DISABLED (0x0UL) /*!< In host-only mode: Received the response from the device for the LPM + transaction*/ + #define USBHSCORE_GLPMCFG_SNDLPM_ENABLED (0x1UL) /*!< In host-only mode: Sending LPM transaction containing EXT and LPM + tokens*/ + +/* LPMRETRYCNTSTS @Bits 25..27 : LPM Retry Count Status (LPM_RetryCnt_Sts) */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos (25UL) /*!< Position of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos) /*!< Bit mask of LPMRETRYCNTSTS + field.*/ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Min (0x0UL) /*!< Min enumerator value of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Max (0x7UL) /*!< Max enumerator value of LPMRETRYCNTSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM0 (0x0UL) /*!< Zero LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM1 (0x1UL) /*!< One LPM retry remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM2 (0x2UL) /*!< Two LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM3 (0x3UL) /*!< Three LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM4 (0x4UL) /*!< Four LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM5 (0x5UL) /*!< Five LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM6 (0x6UL) /*!< Six LPM retries remaining */ + #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM7 (0x7UL) /*!< Seven LPM retries remaining */ + +/* LPMENBESL @Bit 28 : LPM Enable BESL (LPM_EnBESL) */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Pos (28UL) /*!< Position of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMENBESL_Pos) /*!< Bit mask of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Min (0x0UL) /*!< Min enumerator value of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_Max (0x1UL) /*!< Max enumerator value of LPMENBESL field. */ + #define USBHSCORE_GLPMCFG_LPMENBESL_DISABLED (0x0UL) /*!< BESL is disabled */ + #define USBHSCORE_GLPMCFG_LPMENBESL_ENABLED (0x1UL) /*!< BESL is enabled as defined in LPM Errata */ + +/* LPMRESTORESLPSTS @Bit 29 : LPM Restore Sleep Status (LPM_RestoreSlpSts) */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos (29UL) /*!< Position of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos) /*!< Bit mask of + LPMRESTORESLPSTS field.*/ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Min (0x0UL) /*!< Min enumerator value of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Max (0x1UL) /*!< Max enumerator value of LPMRESTORESLPSTS field. */ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_DISABLED (0x0UL) /*!< Puts the core in Shallow Sleep mode based on the BESL value + from the Host*/ + #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_ENABLED (0x1UL) /*!< Puts the core in Deep Sleep mode based on the BESL value from + the Host*/ + + +/* USBHSCORE_GPWRDN: Global Power Down Register */ + #define USBHSCORE_GPWRDN_ResetValue (0x00000010UL) /*!< Reset value of GPWRDN register. */ + +/* PMUINTSEL @Bit 0 : PMU Interrupt Select (PMUIntSel) */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Pos (0UL) /*!< Position of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Msk (0x1UL << USBHSCORE_GPWRDN_PMUINTSEL_Pos) /*!< Bit mask of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Min (0x0UL) /*!< Min enumerator value of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_Max (0x1UL) /*!< Max enumerator value of PMUINTSEL field. */ + #define USBHSCORE_GPWRDN_PMUINTSEL_DISABLE (0x0UL) /*!< Internal DWC_otg_core interrupt is selected */ + #define USBHSCORE_GPWRDN_PMUINTSEL_ENABLE (0x1UL) /*!< External DWC_otg_pmu interrupt is selected */ + +/* PMUACTV @Bit 1 : PMU Active (PMUActv) */ + #define USBHSCORE_GPWRDN_PMUACTV_Pos (1UL) /*!< Position of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Msk (0x1UL << USBHSCORE_GPWRDN_PMUACTV_Pos) /*!< Bit mask of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Min (0x0UL) /*!< Min enumerator value of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_Max (0x1UL) /*!< Max enumerator value of PMUACTV field. */ + #define USBHSCORE_GPWRDN_PMUACTV_DISABLE (0x0UL) /*!< Disable PMU module */ + #define USBHSCORE_GPWRDN_PMUACTV_ENABLE (0x1UL) /*!< Enable PMU module */ + +/* RESTORE @Bit 2 : Restore */ + #define USBHSCORE_GPWRDN_RESTORE_Pos (2UL) /*!< Position of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Msk (0x1UL << USBHSCORE_GPWRDN_RESTORE_Pos) /*!< Bit mask of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Min (0x0UL) /*!< Min enumerator value of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_Max (0x1UL) /*!< Max enumerator value of RESTORE field. */ + #define USBHSCORE_GPWRDN_RESTORE_DISABLE (0x0UL) /*!< The controller in normal mode of operation */ + #define USBHSCORE_GPWRDN_RESTORE_ENABLE (0x1UL) /*!< The controller in Restore mode */ + +/* PWRDNCLMP @Bit 3 : Power Down Clamp (PwrDnClmp) */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Pos (3UL) /*!< Position of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNCLMP_Pos) /*!< Bit mask of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Min (0x0UL) /*!< Min enumerator value of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_Max (0x1UL) /*!< Max enumerator value of PWRDNCLMP field. */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_DISABLE (0x0UL) /*!< Disable PMU power clamp */ + #define USBHSCORE_GPWRDN_PWRDNCLMP_ENABLE (0x1UL) /*!< Enable PMU power clamp */ + +/* PWRDNRSTN @Bit 4 : Power Down ResetN (PwrDnRst_n) */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Pos (4UL) /*!< Position of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNRSTN_Pos) /*!< Bit mask of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Min (0x0UL) /*!< Min enumerator value of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_Max (0x1UL) /*!< Max enumerator value of PWRDNRSTN field. */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_DISABLE (0x0UL) /*!< Reset the controller */ + #define USBHSCORE_GPWRDN_PWRDNRSTN_ENABLE (0x1UL) /*!< The controller is in normal operation */ + +/* PWRDNSWTCH @Bit 5 : Power Down Switch (PwrDnSwtch) */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Pos (5UL) /*!< Position of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNSWTCH_Pos) /*!< Bit mask of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Min (0x0UL) /*!< Min enumerator value of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_Max (0x1UL) /*!< Max enumerator value of PWRDNSWTCH field. */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_ON (0x0UL) /*!< The controller is in ON state */ + #define USBHSCORE_GPWRDN_PWRDNSWTCH_OFF (0x1UL) /*!< The controller is in OFF state */ + +/* DISABLEVBUS @Bit 6 : DisableVBUS */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Pos (6UL) /*!< Position of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Msk (0x1UL << USBHSCORE_GPWRDN_DISABLEVBUS_Pos) /*!< Bit mask of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Min (0x0UL) /*!< Min enumerator value of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_Max (0x1UL) /*!< Max enumerator value of DISABLEVBUS field. */ + #define USBHSCORE_GPWRDN_DISABLEVBUS_DISABLED (0x0UL) /*!< Host mode:HPRT0.PrtPwr was not programmed to 0, and in Device + mode:Session Valid*/ + #define USBHSCORE_GPWRDN_DISABLEVBUS_ENABLED (0x1UL) /*!< Host mode:HPRT0.PrtPwr was programmed to 0 and in Device + mode:Session End*/ + +/* LNSTSCHNG @Bit 7 : Line State Change (LnStsChng) */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Pos (7UL) /*!< Position of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Msk (0x1UL << USBHSCORE_GPWRDN_LNSTSCHNG_Pos) /*!< Bit mask of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Min (0x0UL) /*!< Min enumerator value of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_Max (0x1UL) /*!< Max enumerator value of LNSTSCHNG field. */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_DISABLED (0x0UL) /*!< No LineState change on USB */ + #define USBHSCORE_GPWRDN_LNSTSCHNG_ENABLED (0x1UL) /*!< LineState change on USB */ + +/* LINESTAGECHANGEMSK @Bit 8 : LineStageChangeMsk */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos (8UL) /*!< Position of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Msk (0x1UL << USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos) /*!< Bit mask of + LINESTAGECHANGEMSK field.*/ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Min (0x0UL) /*!< Min enumerator value of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Max (0x1UL) /*!< Max enumerator value of LINESTAGECHANGEMSK field. */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_NOMASK (0x0UL) /*!< No LineStateChange Interrupt Mask */ + #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_MASK (0x1UL) /*!< Mask for LineStateChange Interrupt */ + +/* RESETDETECTED @Bit 9 : ResetDetected */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Pos (9UL) /*!< Position of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETECTED_Pos) /*!< Bit mask of RESETDETECTED + field.*/ + #define USBHSCORE_GPWRDN_RESETDETECTED_Min (0x0UL) /*!< Min enumerator value of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_Max (0x1UL) /*!< Max enumerator value of RESETDETECTED field. */ + #define USBHSCORE_GPWRDN_RESETDETECTED_DISABLED (0x0UL) /*!< Reset not detected */ + #define USBHSCORE_GPWRDN_RESETDETECTED_ENABLED (0x1UL) /*!< Reset detected */ + +/* RESETDETMSK @Bit 10 : ResetDetMsk */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Pos (10UL) /*!< Position of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Min (0x0UL) /*!< Min enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_Max (0x1UL) /*!< Max enumerator value of RESETDETMSK field. */ + #define USBHSCORE_GPWRDN_RESETDETMSK_NOMASK (0x0UL) /*!< No ResetDetect Interrupt Mask */ + #define USBHSCORE_GPWRDN_RESETDETMSK_MASK (0x1UL) /*!< Mask for ResetDetect Interrupt */ + +/* DISCONNECTDETECT @Bit 11 : DisconnectDetect */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos (11UL) /*!< Position of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos) /*!< Bit mask of + DISCONNECTDETECT field.*/ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECT field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_DISABLED (0x0UL) /*!< Disconnect not detected */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECT_ENABLED (0x1UL) /*!< Disconnect detected */ + +/* DISCONNECTDETECTMSK @Bit 12 : DisconnectDetectMsk */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos (12UL) /*!< Position of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos) /*!< Bit mask of + DISCONNECTDETECTMSK field.*/ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECTMSK field. */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_NOMASK (0x0UL) /*!< No DisconnectDetect Interrupt Mask */ + #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_MASK (0x1UL) /*!< Mask for DisconnectDetect Interrupt */ + +/* CONNECTDET @Bit 13 : ConnectDet */ + #define USBHSCORE_GPWRDN_CONNECTDET_Pos (13UL) /*!< Position of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Msk (0x1UL << USBHSCORE_GPWRDN_CONNECTDET_Pos) /*!< Bit mask of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Min (0x0UL) /*!< Min enumerator value of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_Max (0x1UL) /*!< Max enumerator value of CONNECTDET field. */ + #define USBHSCORE_GPWRDN_CONNECTDET_DISABLED (0x0UL) /*!< Connect not detected */ + #define USBHSCORE_GPWRDN_CONNECTDET_ENABLED (0x1UL) /*!< Connect detected */ + +/* CONNDETMSK @Bit 14 : ConnDetMsk */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Pos (14UL) /*!< Position of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_CONNDETMSK_Pos) /*!< Bit mask of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Min (0x0UL) /*!< Min enumerator value of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_Max (0x1UL) /*!< Max enumerator value of CONNDETMSK field. */ + #define USBHSCORE_GPWRDN_CONNDETMSK_NOMASK (0x0UL) /*!< No ConnectDet Interrupt Mask */ + #define USBHSCORE_GPWRDN_CONNDETMSK_MASK (0x1UL) /*!< Mask for ConnectDet Interrupt */ + +/* SRPDETECT @Bit 15 : SRPDetect */ + #define USBHSCORE_GPWRDN_SRPDETECT_Pos (15UL) /*!< Position of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECT_Pos) /*!< Bit mask of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Min (0x0UL) /*!< Min enumerator value of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_Max (0x1UL) /*!< Max enumerator value of SRPDETECT field. */ + #define USBHSCORE_GPWRDN_SRPDETECT_DISABLED (0x0UL) /*!< SRP not detected */ + #define USBHSCORE_GPWRDN_SRPDETECT_ENABLED (0x1UL) /*!< SRP detected */ + +/* SRPDETECTMSK @Bit 16 : SRPDetectMsk */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Pos (16UL) /*!< Position of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECTMSK_Pos) /*!< Bit mask of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Min (0x0UL) /*!< Min enumerator value of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_Max (0x1UL) /*!< Max enumerator value of SRPDETECTMSK field. */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_NOMASK (0x0UL) /*!< No SRPDetect Interrupt Mask */ + #define USBHSCORE_GPWRDN_SRPDETECTMSK_MASK (0x1UL) /*!< Mask for SRPDetect Interrupt */ + +/* STSCHNGINT @Bit 17 : Status Change Interrupt (StsChngInt) */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Pos (17UL) /*!< Position of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINT_Pos) /*!< Bit mask of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Min (0x0UL) /*!< Min enumerator value of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_Max (0x1UL) /*!< Max enumerator value of STSCHNGINT field. */ + #define USBHSCORE_GPWRDN_STSCHNGINT_DISABLED (0x0UL) /*!< No Status change */ + #define USBHSCORE_GPWRDN_STSCHNGINT_ENABLED (0x1UL) /*!< Status change detected */ + +/* STSCHNGINTMSK @Bit 18 : StsChngIntMsk */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos (18UL) /*!< Position of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos) /*!< Bit mask of STSCHNGINTMSK + field.*/ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Min (0x0UL) /*!< Min enumerator value of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Max (0x1UL) /*!< Max enumerator value of STSCHNGINTMSK field. */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_NOMASK (0x0UL) /*!< No Status Change Interrupt Mask */ + #define USBHSCORE_GPWRDN_STSCHNGINTMSK_MASK (0x1UL) /*!< Mask for Status Change Interrupt */ + +/* LINESTATE @Bits 19..20 : LineState */ + #define USBHSCORE_GPWRDN_LINESTATE_Pos (19UL) /*!< Position of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Msk (0x3UL << USBHSCORE_GPWRDN_LINESTATE_Pos) /*!< Bit mask of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Min (0x0UL) /*!< Min enumerator value of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_Max (0x3UL) /*!< Max enumerator value of LINESTATE field. */ + #define USBHSCORE_GPWRDN_LINESTATE_LS1 (0x0UL) /*!< Linestate on USB: DM = 0, DP = 0 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS2 (0x1UL) /*!< Linestate on USB: DM = 0, DP = 1 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS3 (0x2UL) /*!< Linestate on USB: DM = 1, DP = 0 */ + #define USBHSCORE_GPWRDN_LINESTATE_LS4 (0x3UL) /*!< Linestate on USB: Not-defined */ + +/* IDDIG @Bit 21 : This bit indicates the status of the signal IDDIG. The application must read this bit after receiving + GPWRDN.StsChngInt and decode based on the previous value stored by the application. */ + + #define USBHSCORE_GPWRDN_IDDIG_Pos (21UL) /*!< Position of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Msk (0x1UL << USBHSCORE_GPWRDN_IDDIG_Pos) /*!< Bit mask of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Min (0x0UL) /*!< Min enumerator value of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_Max (0x1UL) /*!< Max enumerator value of IDDIG field. */ + #define USBHSCORE_GPWRDN_IDDIG_DISABLED (0x0UL) /*!< Host Mode */ + #define USBHSCORE_GPWRDN_IDDIG_ENABLED (0x1UL) /*!< Device Mode */ + +/* BSESSVLD @Bit 22 : B Session Valid (BSessVld) */ + #define USBHSCORE_GPWRDN_BSESSVLD_Pos (22UL) /*!< Position of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Msk (0x1UL << USBHSCORE_GPWRDN_BSESSVLD_Pos) /*!< Bit mask of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Min (0x0UL) /*!< Min enumerator value of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_Max (0x1UL) /*!< Max enumerator value of BSESSVLD field. */ + #define USBHSCORE_GPWRDN_BSESSVLD_NOTVALID (0x0UL) /*!< B_Valid is 0 */ + #define USBHSCORE_GPWRDN_BSESSVLD_VALID (0x1UL) /*!< B_Valid is 1 */ + +/* MULTVALIDBC @Bits 24..28 : MultValIdBC */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Pos (24UL) /*!< Position of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GPWRDN_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Min (0x0UL) /*!< Min enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_Max (0x1FUL) /*!< Max enumerator value of MULTVALIDBC field. */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_0 (0x00UL) /*!< OTG device as B-device */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_C (0x01UL) /*!< OTG device as B-device, can connect */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_B (0x02UL) /*!< OTG device as B-device, cannot connect */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_A (0x04UL) /*!< OTG device as A-device */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_GND (0x08UL) /*!< ID_OTG pin is grounded */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_A_RID_GND (0x0CUL) /*!< OTG device as A-device, RID_A=1 and RID_GND=1 */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_FLOAT (0x10UL) /*!< ID pull down when ID_OTG is floating */ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_C_RID_FLOAT (0x11UL) /*!< OTG device as B-device, can connect, RID_C=1 and + RID_FLOAT=1*/ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_B_RID_FLOAT (0x12UL) /*!< OTG device as B-device, cannot connect, RID_B=1 and + RID_FLOAT=1*/ + #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_1 (0x1FUL) /*!< OTG device as A-device */ + + +/* USBHSCORE_GDFIFOCFG: Global DFIFO Configuration Register */ + #define USBHSCORE_GDFIFOCFG_ResetValue (0x0BEA0C00UL) /*!< Reset value of GDFIFOCFG register. */ + +/* GDFIFOCFG @Bits 0..15 : GDFIFOCfg */ + #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos (0UL) /*!< Position of GDFIFOCFG field. */ + #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos) /*!< Bit mask of GDFIFOCFG field. */ + +/* EPINFOBASEADDR @Bits 16..31 : This field provides the start address of the EP info controller. */ + #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos (16UL) /*!< Position of EPINFOBASEADDR field. */ + #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos) /*!< Bit mask of + EPINFOBASEADDR field.*/ + + +/* USBHSCORE_GINTMSK2: Interrupt Mask Register 2 */ + #define USBHSCORE_GINTMSK2_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK2 register. */ + +/* GINTMSK2 @Bits 0..31 : (unspecified) */ + #define USBHSCORE_GINTMSK2_GINTMSK2_Pos (0UL) /*!< Position of GINTMSK2 field. */ + #define USBHSCORE_GINTMSK2_GINTMSK2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTMSK2_GINTMSK2_Pos) /*!< Bit mask of GINTMSK2 field. */ + + +/* USBHSCORE_GINTSTS2: Interrupt Register 2 */ + #define USBHSCORE_GINTSTS2_ResetValue (0x00000000UL) /*!< Reset value of GINTSTS2 register. */ + +/* GINTSTS2 @Bits 0..31 : (unspecified) */ + #define USBHSCORE_GINTSTS2_GINTSTS2_Pos (0UL) /*!< Position of GINTSTS2 field. */ + #define USBHSCORE_GINTSTS2_GINTSTS2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTSTS2_GINTSTS2_Pos) /*!< Bit mask of GINTSTS2 field. */ + + +/* USBHSCORE_HPTXFSIZ: Host Periodic Transmit FIFO Size Register */ + #define USBHSCORE_HPTXFSIZ_ResetValue (0x04000424UL) /*!< Reset value of HPTXFSIZ register. */ + +/* PTXFSTADDR @Bits 0..10 : Host Periodic TxFIFO Start Address (PTxFStAddr) */ + #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos (0UL) /*!< Position of PTXFSTADDR field. */ + #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Msk (0x7FFUL << USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos) /*!< Bit mask of PTXFSTADDR field. */ + +/* PTXFSIZE @Bits 16..26 : Host Periodic TxFIFO Depth (PTxFSize) */ + #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos (16UL) /*!< Position of PTXFSIZE field. */ + #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Msk (0x7FFUL << USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos) /*!< Bit mask of PTXFSIZE field. */ + + +/* USBHSCORE_DIEPTXF: Device IN Endpoint Transmit FIFO Size Register */ + #define USBHSCORE_DIEPTXF_MaxCount (7UL) /*!< Max size of DIEPTXF[8] array. */ + #define USBHSCORE_DIEPTXF_MaxIndex (7UL) /*!< Max index of DIEPTXF[8] array. */ + #define USBHSCORE_DIEPTXF_MinIndex (1UL) /*!< Min index of DIEPTXF[8] array. */ + #define USBHSCORE_DIEPTXF_ResetValue (0x02000424UL) /*!< Reset value of DIEPTXF[8] register. */ + +/* INEPNTXFSTADDR @Bits 0..10 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */ + #define USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field. */ + #define USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Msk (0x7FFUL << USBHSCORE_DIEPTXF_INEPNTXFSTADDR_Pos) /*!< Bit mask of INEPNTXFSTADDR + field.*/ + +/* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */ + #define USBHSCORE_DIEPTXF_INEPNTXFDEP_Pos (16UL) /*!< Position of INEPNTXFDEP field. */ + #define USBHSCORE_DIEPTXF_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP field. */ + + +/* USBHSCORE_HCFG: Host Configuration Register */ + #define USBHSCORE_HCFG_ResetValue (0x00000200UL) /*!< Reset value of HCFG register. */ + +/* FSLSPCLKSEL @Bits 0..1 : FS/LS PHY Clock Select (FSLSPclkSel) */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Pos (0UL) /*!< Position of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Msk (0x3UL << USBHSCORE_HCFG_FSLSPCLKSEL_Pos) /*!< Bit mask of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Min (0x0UL) /*!< Min enumerator value of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_Max (0x2UL) /*!< Max enumerator value of FSLSPCLKSEL field. */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK3060 (0x0UL) /*!< PHY clock is running at 30/60 MHz */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK48 (0x1UL) /*!< PHY clock is running at 48 MHz */ + #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK6 (0x2UL) /*!< PHY clock is running at 6 MHz */ + +/* FSLSSUPP @Bit 2 : FS- and LS-Only Support (FSLSSupp) */ + #define USBHSCORE_HCFG_FSLSSUPP_Pos (2UL) /*!< Position of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Msk (0x1UL << USBHSCORE_HCFG_FSLSSUPP_Pos) /*!< Bit mask of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Min (0x0UL) /*!< Min enumerator value of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_Max (0x1UL) /*!< Max enumerator value of FSLSSUPP field. */ + #define USBHSCORE_HCFG_FSLSSUPP_HSFSLS (0x0UL) /*!< HS/FS/LS, based on the maximum speed supported by the connected + device*/ + #define USBHSCORE_HCFG_FSLSSUPP_FSLS (0x1UL) /*!< FS/LS-only, even if the connected device can support HS */ + +/* ENA32KHZS @Bit 7 : Enable 32 KHz Suspend mode (Ena32KHzS) */ + #define USBHSCORE_HCFG_ENA32KHZS_Pos (7UL) /*!< Position of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Msk (0x1UL << USBHSCORE_HCFG_ENA32KHZS_Pos) /*!< Bit mask of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Min (0x0UL) /*!< Min enumerator value of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_Max (0x1UL) /*!< Max enumerator value of ENA32KHZS field. */ + #define USBHSCORE_HCFG_ENA32KHZS_DISABLED (0x0UL) /*!< 32 KHz Suspend mode disabled */ + #define USBHSCORE_HCFG_ENA32KHZS_ENABLED (0x1UL) /*!< 32 KHz Suspend mode enabled */ + +/* RESVALID @Bits 8..15 : Resume Validation Period (ResValid) */ + #define USBHSCORE_HCFG_RESVALID_Pos (8UL) /*!< Position of RESVALID field. */ + #define USBHSCORE_HCFG_RESVALID_Msk (0xFFUL << USBHSCORE_HCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field. */ + +/* MODECHTIMEN @Bit 31 : Mode Change Ready Timer Enable (ModeChTimEn) */ + #define USBHSCORE_HCFG_MODECHTIMEN_Pos (31UL) /*!< Position of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Msk (0x1UL << USBHSCORE_HCFG_MODECHTIMEN_Pos) /*!< Bit mask of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Min (0x0UL) /*!< Min enumerator value of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_Max (0x1UL) /*!< Max enumerator value of MODECHTIMEN field. */ + #define USBHSCORE_HCFG_MODECHTIMEN_ENABLED (0x0UL) /*!< The Host core waits for either 200 PHY clock cycles or a linestate of + SE0 at the end of resume to change the opmode from 0x2 to 0x0*/ + #define USBHSCORE_HCFG_MODECHTIMEN_DISABLED (0x1UL) /*!< The Host core waits only for a linestate of SE0 at the end of resume + to change the opmode from 0x2 to 0x0*/ + + +/* USBHSCORE_HFIR: Host Frame Interval Register */ + #define USBHSCORE_HFIR_ResetValue (0x0000EA60UL) /*!< Reset value of HFIR register. */ + +/* FRINT @Bits 0..15 : Frame Interval (FrInt) */ + #define USBHSCORE_HFIR_FRINT_Pos (0UL) /*!< Position of FRINT field. */ + #define USBHSCORE_HFIR_FRINT_Msk (0xFFFFUL << USBHSCORE_HFIR_FRINT_Pos) /*!< Bit mask of FRINT field. */ + +/* HFIRRLDCTRL @Bit 16 : Reload Control (HFIRRldCtrl) */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Pos (16UL) /*!< Position of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Msk (0x1UL << USBHSCORE_HFIR_HFIRRLDCTRL_Pos) /*!< Bit mask of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Min (0x0UL) /*!< Min enumerator value of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_Max (0x1UL) /*!< Max enumerator value of HFIRRLDCTRL field. */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_DISABLED (0x0UL) /*!< The HFIR cannot be reloaded dynamically */ + #define USBHSCORE_HFIR_HFIRRLDCTRL_ENABLED (0x1UL) /*!< The HFIR can be dynamically reloaded during runtime */ + + +/* USBHSCORE_HFNUM: Host Frame Number/Frame Time Remaining Register */ + #define USBHSCORE_HFNUM_ResetValue (0x00003FFFUL) /*!< Reset value of HFNUM register. */ + +/* FRNUM @Bits 0..15 : Frame Number (FrNum) */ + #define USBHSCORE_HFNUM_FRNUM_Pos (0UL) /*!< Position of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRNUM_Pos) /*!< Bit mask of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Min (0x0UL) /*!< Min enumerator value of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_Max (0x1UL) /*!< Max enumerator value of FRNUM field. */ + #define USBHSCORE_HFNUM_FRNUM_INACTIVE (0x0000UL) /*!< No SOF is transmitted */ + #define USBHSCORE_HFNUM_FRNUM_ACTIVE (0x0001UL) /*!< SOF is transmitted */ + +/* FRREM @Bits 16..31 : Frame Time Remaining (FrRem) */ + #define USBHSCORE_HFNUM_FRREM_Pos (16UL) /*!< Position of FRREM field. */ + #define USBHSCORE_HFNUM_FRREM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRREM_Pos) /*!< Bit mask of FRREM field. */ + + +/* USBHSCORE_HAINT: Host All Channels Interrupt Register */ + #define USBHSCORE_HAINT_ResetValue (0x00000000UL) /*!< Reset value of HAINT register. */ + +/* HAINT @Bits 0..15 : (unspecified) */ + #define USBHSCORE_HAINT_HAINT_Pos (0UL) /*!< Position of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Msk (0xFFFFUL << USBHSCORE_HAINT_HAINT_Pos) /*!< Bit mask of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Min (0x0UL) /*!< Min enumerator value of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_Max (0x1UL) /*!< Max enumerator value of HAINT field. */ + #define USBHSCORE_HAINT_HAINT_INACTIVE (0x0000UL) /*!< Not active */ + #define USBHSCORE_HAINT_HAINT_ACTIVE (0x0001UL) /*!< Host Channel Interrupt */ + + +/* USBHSCORE_HAINTMSK: Host All Channels Interrupt Mask Register */ + #define USBHSCORE_HAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of HAINTMSK register. */ + +/* HAINTMSK @Bits 0..15 : Channel Interrupt Mask (HAINTMsk) */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Pos (0UL) /*!< Position of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Msk (0xFFFFUL << USBHSCORE_HAINTMSK_HAINTMSK_Pos) /*!< Bit mask of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Min (0x0UL) /*!< Min enumerator value of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_Max (0x1UL) /*!< Max enumerator value of HAINTMSK field. */ + #define USBHSCORE_HAINTMSK_HAINTMSK_UNMASK (0x0000UL) /*!< Unmask Channel interrupt */ + #define USBHSCORE_HAINTMSK_HAINTMSK_MASK (0x0001UL) /*!< Mask Channel interrupt */ + + +/* USBHSCORE_HPRT: Host Port Control and Status Register */ + #define USBHSCORE_HPRT_ResetValue (0x00000000UL) /*!< Reset value of HPRT register. */ + +/* PRTCONNSTS @Bit 0 : Port Connect Status (PrtConnSts) */ + #define USBHSCORE_HPRT_PRTCONNSTS_Pos (0UL) /*!< Position of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNSTS_Pos) /*!< Bit mask of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Min (0x0UL) /*!< Min enumerator value of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_Max (0x1UL) /*!< Max enumerator value of PRTCONNSTS field. */ + #define USBHSCORE_HPRT_PRTCONNSTS_NOTATTACHED (0x0UL) /*!< No device is attached to the port */ + #define USBHSCORE_HPRT_PRTCONNSTS_ATTACHED (0x1UL) /*!< A device is attached to the port */ + +/* PRTCONNDET @Bit 1 : Port Connect Detected (PrtConnDet) */ + #define USBHSCORE_HPRT_PRTCONNDET_Pos (1UL) /*!< Position of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNDET_Pos) /*!< Bit mask of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Min (0x0UL) /*!< Min enumerator value of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_Max (0x1UL) /*!< Max enumerator value of PRTCONNDET field. */ + #define USBHSCORE_HPRT_PRTCONNDET_INACTIVE (0x0UL) /*!< No device connection detected */ + #define USBHSCORE_HPRT_PRTCONNDET_ACTIVE (0x1UL) /*!< Device connection detected */ + +/* PRTENA @Bit 2 : Port Enable (PrtEna) */ + #define USBHSCORE_HPRT_PRTENA_Pos (2UL) /*!< Position of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Msk (0x1UL << USBHSCORE_HPRT_PRTENA_Pos) /*!< Bit mask of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Min (0x0UL) /*!< Min enumerator value of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_Max (0x1UL) /*!< Max enumerator value of PRTENA field. */ + #define USBHSCORE_HPRT_PRTENA_DISABLED (0x0UL) /*!< Port disabled */ + #define USBHSCORE_HPRT_PRTENA_ENABLED (0x1UL) /*!< Port enabled */ + +/* PRTENCHNG @Bit 3 : Port Enable/Disable Change (PrtEnChng) */ + #define USBHSCORE_HPRT_PRTENCHNG_Pos (3UL) /*!< Position of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTENCHNG_Pos) /*!< Bit mask of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Min (0x0UL) /*!< Min enumerator value of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_Max (0x1UL) /*!< Max enumerator value of PRTENCHNG field. */ + #define USBHSCORE_HPRT_PRTENCHNG_INACTIVE (0x0UL) /*!< Port Enable bit 2 has not changed */ + #define USBHSCORE_HPRT_PRTENCHNG_ACTIVE (0x1UL) /*!< Port Enable bit 2 changed */ + +/* PRTOVRCURRACT @Bit 4 : Port Overcurrent Active (PrtOvrCurrAct) */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Pos (4UL) /*!< Position of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRACT_Pos) /*!< Bit mask of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Min (0x0UL) /*!< Min enumerator value of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_Max (0x1UL) /*!< Max enumerator value of PRTOVRCURRACT field. */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_INACTIVE (0x0UL) /*!< No overcurrent condition */ + #define USBHSCORE_HPRT_PRTOVRCURRACT_ACTIVE (0x1UL) /*!< Overcurrent condition */ + +/* PRTOVRCURRCHNG @Bit 5 : Port Overcurrent Change (PrtOvrCurrChng) */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos (5UL) /*!< Position of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos) /*!< Bit mask of PRTOVRCURRCHNG field.*/ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Min (0x0UL) /*!< Min enumerator value of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Max (0x1UL) /*!< Max enumerator value of PRTOVRCURRCHNG field. */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_INACTIVE (0x0UL) /*!< Status of port overcurrent status is not changed */ + #define USBHSCORE_HPRT_PRTOVRCURRCHNG_ACTIVE (0x1UL) /*!< Status of port overcurrent changed */ + +/* PRTRES @Bit 6 : Port Resume (PrtRes) */ + #define USBHSCORE_HPRT_PRTRES_Pos (6UL) /*!< Position of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Msk (0x1UL << USBHSCORE_HPRT_PRTRES_Pos) /*!< Bit mask of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Min (0x0UL) /*!< Min enumerator value of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_Max (0x1UL) /*!< Max enumerator value of PRTRES field. */ + #define USBHSCORE_HPRT_PRTRES_NORESUME (0x0UL) /*!< No resume driven */ + #define USBHSCORE_HPRT_PRTRES_RESUME (0x1UL) /*!< Resume driven */ + +/* PRTSUSP @Bit 7 : Port Suspend (PrtSusp) */ + #define USBHSCORE_HPRT_PRTSUSP_Pos (7UL) /*!< Position of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Msk (0x1UL << USBHSCORE_HPRT_PRTSUSP_Pos) /*!< Bit mask of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Min (0x0UL) /*!< Min enumerator value of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_Max (0x1UL) /*!< Max enumerator value of PRTSUSP field. */ + #define USBHSCORE_HPRT_PRTSUSP_INACTIVE (0x0UL) /*!< Port not in Suspend mode */ + #define USBHSCORE_HPRT_PRTSUSP_ACTIVE (0x1UL) /*!< Port in Suspend mode */ + +/* PRTRST @Bit 8 : Port Reset (PrtRst) */ + #define USBHSCORE_HPRT_PRTRST_Pos (8UL) /*!< Position of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Msk (0x1UL << USBHSCORE_HPRT_PRTRST_Pos) /*!< Bit mask of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Min (0x0UL) /*!< Min enumerator value of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_Max (0x1UL) /*!< Max enumerator value of PRTRST field. */ + #define USBHSCORE_HPRT_PRTRST_DISABLED (0x0UL) /*!< Port not in reset */ + #define USBHSCORE_HPRT_PRTRST_ENABLED (0x1UL) /*!< Port in reset */ + +/* PRTLNSTS @Bits 10..11 : Port Line Status (PrtLnSts) */ + #define USBHSCORE_HPRT_PRTLNSTS_Pos (10UL) /*!< Position of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Msk (0x3UL << USBHSCORE_HPRT_PRTLNSTS_Pos) /*!< Bit mask of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Min (0x1UL) /*!< Min enumerator value of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_Max (0x2UL) /*!< Max enumerator value of PRTLNSTS field. */ + #define USBHSCORE_HPRT_PRTLNSTS_PLUSD (0x1UL) /*!< Logic level of D+ */ + #define USBHSCORE_HPRT_PRTLNSTS_MINUSD (0x2UL) /*!< Logic level of D- */ + +/* PRTPWR @Bit 12 : Port Power (PrtPwr) */ + #define USBHSCORE_HPRT_PRTPWR_Pos (12UL) /*!< Position of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Msk (0x1UL << USBHSCORE_HPRT_PRTPWR_Pos) /*!< Bit mask of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Min (0x0UL) /*!< Min enumerator value of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_Max (0x1UL) /*!< Max enumerator value of PRTPWR field. */ + #define USBHSCORE_HPRT_PRTPWR_OFF (0x0UL) /*!< Power off */ + #define USBHSCORE_HPRT_PRTPWR_ON (0x1UL) /*!< Power on */ + +/* PRTTSTCTL @Bits 13..16 : Port Test Control (PrtTstCtl) */ + #define USBHSCORE_HPRT_PRTTSTCTL_Pos (13UL) /*!< Position of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Msk (0xFUL << USBHSCORE_HPRT_PRTTSTCTL_Pos) /*!< Bit mask of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Min (0x0UL) /*!< Min enumerator value of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_Max (0x5UL) /*!< Max enumerator value of PRTTSTCTL field. */ + #define USBHSCORE_HPRT_PRTTSTCTL_DISABLED (0x0UL) /*!< Test mode disabled */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTJ (0x1UL) /*!< Test_J mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTK (0x2UL) /*!< Test_K mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTSN (0x3UL) /*!< Test_SE0_NAK mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTPM (0x4UL) /*!< Test_Packet mode */ + #define USBHSCORE_HPRT_PRTTSTCTL_TESTFENB (0x5UL) /*!< Test_force_Enable */ + +/* PRTSPD @Bits 17..18 : Port Speed (PrtSpd) */ + #define USBHSCORE_HPRT_PRTSPD_Pos (17UL) /*!< Position of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Msk (0x3UL << USBHSCORE_HPRT_PRTSPD_Pos) /*!< Bit mask of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Min (0x0UL) /*!< Min enumerator value of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_Max (0x2UL) /*!< Max enumerator value of PRTSPD field. */ + #define USBHSCORE_HPRT_PRTSPD_HIGHSPD (0x0UL) /*!< High speed */ + #define USBHSCORE_HPRT_PRTSPD_FULLSPD (0x1UL) /*!< Full speed */ + #define USBHSCORE_HPRT_PRTSPD_LOWSPD (0x2UL) /*!< Low speed */ + + +/* USBHSCORE_DCFG: Device Configuration Register */ + #define USBHSCORE_DCFG_ResetValue (0x08020000UL) /*!< Reset value of DCFG register. */ + +/* DEVSPD @Bits 0..1 : Device Speed (DevSpd) */ + #define USBHSCORE_DCFG_DEVSPD_Pos (0UL) /*!< Position of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Msk (0x3UL << USBHSCORE_DCFG_DEVSPD_Pos) /*!< Bit mask of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Min (0x0UL) /*!< Min enumerator value of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_Max (0x3UL) /*!< Max enumerator value of DEVSPD field. */ + #define USBHSCORE_DCFG_DEVSPD_USBHS20 (0x0UL) /*!< High speed USB 2.0 PHY clock is 30 MHz or 60 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBFS20 (0x1UL) /*!< Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBLS116 (0x2UL) /*!< Low speed USB 1.1 transceiver clock is 6 MHz */ + #define USBHSCORE_DCFG_DEVSPD_USBFS1148 (0x3UL) /*!< Full speed USB 1.1 transceiver clock is 48 MHz */ + +/* NZSTSOUTHSHK @Bit 2 : Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Pos (2UL) /*!< Position of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Msk (0x1UL << USBHSCORE_DCFG_NZSTSOUTHSHK_Pos) /*!< Bit mask of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Min (0x0UL) /*!< Min enumerator value of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_Max (0x1UL) /*!< Max enumerator value of NZSTSOUTHSHK field. */ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDOUT (0x0UL) /*!< Send the received OUT packet to the application (zero-length or + non-zero length) and send a handshake based on NAK and STALL bits for + the endpoint in the Devce Endpoint Control Register*/ + #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDSTALL (0x1UL) /*!< Send a STALL handshake on a nonzero-length status OUT transaction + and do not send the received OUT packet to the application*/ + +/* ENA32KHZSUSP @Bit 3 : Enable 32 KHz Suspend mode (Ena32KHzSusp) */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Pos (3UL) /*!< Position of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Msk (0x1UL << USBHSCORE_DCFG_ENA32KHZSUSP_Pos) /*!< Bit mask of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Min (0x0UL) /*!< Min enumerator value of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_Max (0x1UL) /*!< Max enumerator value of ENA32KHZSUSP field. */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_DISABLED (0x0UL) /*!< USB 1.1 Full-Speed Serial Transceiver not selected */ + #define USBHSCORE_DCFG_ENA32KHZSUSP_ENABLED (0x1UL) /*!< USB 1.1 Full-Speed Serial Transceiver Interface selected */ + +/* DEVADDR @Bits 4..10 : Device Address (DevAddr) */ + #define USBHSCORE_DCFG_DEVADDR_Pos (4UL) /*!< Position of DEVADDR field. */ + #define USBHSCORE_DCFG_DEVADDR_Msk (0x7FUL << USBHSCORE_DCFG_DEVADDR_Pos) /*!< Bit mask of DEVADDR field. */ + +/* PERFRINT @Bits 11..12 : Periodic Frame Interval (PerFrInt) */ + #define USBHSCORE_DCFG_PERFRINT_Pos (11UL) /*!< Position of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Msk (0x3UL << USBHSCORE_DCFG_PERFRINT_Pos) /*!< Bit mask of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Min (0x0UL) /*!< Min enumerator value of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_Max (0x3UL) /*!< Max enumerator value of PERFRINT field. */ + #define USBHSCORE_DCFG_PERFRINT_EOPF80 (0x0UL) /*!< 80 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF85 (0x1UL) /*!< 85 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF90 (0x2UL) /*!< 90 percent of the (micro)Frame interval */ + #define USBHSCORE_DCFG_PERFRINT_EOPF95 (0x3UL) /*!< 95 percent of the (micro)Frame interval */ + +/* XCVRDLY @Bit 14 : XCVRDLY */ + #define USBHSCORE_DCFG_XCVRDLY_Pos (14UL) /*!< Position of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Msk (0x1UL << USBHSCORE_DCFG_XCVRDLY_Pos) /*!< Bit mask of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Min (0x0UL) /*!< Min enumerator value of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_Max (0x1UL) /*!< Max enumerator value of XCVRDLY field. */ + #define USBHSCORE_DCFG_XCVRDLY_DISABLE (0x0UL) /*!< No delay between xcvr_sel and txvalid during Device chirp */ + #define USBHSCORE_DCFG_XCVRDLY_ENABLE (0x1UL) /*!< Enable delay between xcvr_sel and txvalid during Device chirp */ + +/* ERRATICINTMSK @Bit 15 : Erratic Error Interrupt Mask */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Pos (15UL) /*!< Position of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Msk (0x1UL << USBHSCORE_DCFG_ERRATICINTMSK_Pos) /*!< Bit mask of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Min (0x0UL) /*!< Min enumerator value of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_Max (0x1UL) /*!< Max enumerator value of ERRATICINTMSK field. */ + #define USBHSCORE_DCFG_ERRATICINTMSK_NOMASK (0x0UL) /*!< Early suspend interrupt is generated on erratic error */ + #define USBHSCORE_DCFG_ERRATICINTMSK_MASK (0x1UL) /*!< Mask early suspend interrupt on erratic error */ + +/* IPGISOCSUPT @Bit 17 : Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Pos (17UL) /*!< Position of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_DCFG_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Min (0x0UL) /*!< Min enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_Max (0x1UL) /*!< Max enumerator value of IPGISOCSUPT field. */ + #define USBHSCORE_DCFG_IPGISOCSUPT_DISABLED (0x0UL) /*!< Worst-Case Inter-Packet Gap ISOC OUT Support is disabled */ + #define USBHSCORE_DCFG_IPGISOCSUPT_ENABLED (0x1UL) /*!< Worst-Case Inter-Packet Gap ISOC OUT Support is enabled */ + +/* PERSCHINTVL @Bits 24..25 : Periodic Scheduling Interval (PerSchIntvl) */ + #define USBHSCORE_DCFG_PERSCHINTVL_Pos (24UL) /*!< Position of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Msk (0x3UL << USBHSCORE_DCFG_PERSCHINTVL_Pos) /*!< Bit mask of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Min (0x0UL) /*!< Min enumerator value of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_Max (0x2UL) /*!< Max enumerator value of PERSCHINTVL field. */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF25 (0x0UL) /*!< 25 percent of (micro)Frame */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF50 (0x1UL) /*!< 50 percent of (micro)Frame */ + #define USBHSCORE_DCFG_PERSCHINTVL_MF75 (0x2UL) /*!< 75 percent of (micro)Frame */ + +/* RESVALID @Bits 26..31 : Resume Validation Period (ResValid) */ + #define USBHSCORE_DCFG_RESVALID_Pos (26UL) /*!< Position of RESVALID field. */ + #define USBHSCORE_DCFG_RESVALID_Msk (0x3FUL << USBHSCORE_DCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field. */ + + +/* USBHSCORE_DCTL: Device Control Register */ + #define USBHSCORE_DCTL_ResetValue (0x00000002UL) /*!< Reset value of DCTL register. */ + +/* RMTWKUPSIG @Bit 0 : Remote Wakeup Signaling (RmtWkUpSig) */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Pos (0UL) /*!< Position of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Msk (0x1UL << USBHSCORE_DCTL_RMTWKUPSIG_Pos) /*!< Bit mask of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Min (0x0UL) /*!< Min enumerator value of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_Max (0x1UL) /*!< Max enumerator value of RMTWKUPSIG field. */ + #define USBHSCORE_DCTL_RMTWKUPSIG_DISABLEDRMWKUP (0x0UL) /*!< Core does not send Remote Wakeup Signaling */ + #define USBHSCORE_DCTL_RMTWKUPSIG_ENABLERMWKUP (0x1UL) /*!< Core sends Remote Wakeup Signaling */ + +/* SFTDISCON @Bit 1 : Soft Disconnect (SftDiscon) */ + #define USBHSCORE_DCTL_SFTDISCON_Pos (1UL) /*!< Position of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Msk (0x1UL << USBHSCORE_DCTL_SFTDISCON_Pos) /*!< Bit mask of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Min (0x0UL) /*!< Min enumerator value of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_Max (0x1UL) /*!< Max enumerator value of SFTDISCON field. */ + #define USBHSCORE_DCTL_SFTDISCON_NODISCONNECT (0x0UL) /*!< The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, + which generates a device connect event to the USB host*/ + #define USBHSCORE_DCTL_SFTDISCON_DISCONNECT (0x1UL) /*!< The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which + generates a device disconnect event to the USB host*/ + +/* GNPINNAKSTS @Bit 2 : Global Non-periodic IN NAK Status (GNPINNakSts) */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Pos (2UL) /*!< Position of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GNPINNAKSTS_Pos) /*!< Bit mask of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Min (0x0UL) /*!< Min enumerator value of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_Max (0x1UL) /*!< Max enumerator value of GNPINNAKSTS field. */ + #define USBHSCORE_DCTL_GNPINNAKSTS_INACTIVE (0x0UL) /*!< A handshake is sent out based on the data availability in the + transmit FIFO*/ + #define USBHSCORE_DCTL_GNPINNAKSTS_ACTIVE (0x1UL) /*!< A NAK handshake is sent out on all non-periodic IN endpoints, + irrespective of the data availability in the transmit FIFO.*/ + +/* GOUTNAKSTS @Bit 3 : Global OUT NAK Status (GOUTNakSts) */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Pos (3UL) /*!< Position of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GOUTNAKSTS_Pos) /*!< Bit mask of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Min (0x0UL) /*!< Min enumerator value of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_Max (0x1UL) /*!< Max enumerator value of GOUTNAKSTS field. */ + #define USBHSCORE_DCTL_GOUTNAKSTS_INACTIVE (0x0UL) /*!< A handshake is sent based on the FIFO Status and the NAK and STALL bit + settings.*/ + #define USBHSCORE_DCTL_GOUTNAKSTS_ACTIVE (0x1UL) /*!< No data is written to the RxFIFO, irrespective of space availability. + Sends a NAK handshake on all packets, except on SETUP transactions. + All isochronous OUT packets are dropped.*/ + +/* TSTCTL @Bits 4..6 : Test Control (TstCtl) */ + #define USBHSCORE_DCTL_TSTCTL_Pos (4UL) /*!< Position of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Msk (0x7UL << USBHSCORE_DCTL_TSTCTL_Pos) /*!< Bit mask of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Min (0x0UL) /*!< Min enumerator value of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_Max (0x5UL) /*!< Max enumerator value of TSTCTL field. */ + #define USBHSCORE_DCTL_TSTCTL_DISABLED (0x0UL) /*!< Test mode disabled */ + #define USBHSCORE_DCTL_TSTCTL_TESTJ (0x1UL) /*!< Test_J mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTK (0x2UL) /*!< Test_K mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTSN (0x3UL) /*!< Test_SE0_NAK mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTPM (0x4UL) /*!< Test_Packet mode */ + #define USBHSCORE_DCTL_TSTCTL_TESTFE (0x5UL) /*!< Test_force_Enable */ + +/* SGNPINNAK @Bit 7 : Set Global Non-periodic IN NAK (SGNPInNak) */ + #define USBHSCORE_DCTL_SGNPINNAK_Pos (7UL) /*!< Position of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_SGNPINNAK_Pos) /*!< Bit mask of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Min (0x0UL) /*!< Min enumerator value of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_Max (0x1UL) /*!< Max enumerator value of SGNPINNAK field. */ + #define USBHSCORE_DCTL_SGNPINNAK_DISABLE (0x0UL) /*!< Disable Global Non-periodic IN NAK */ + #define USBHSCORE_DCTL_SGNPINNAK_ENABLE (0x1UL) /*!< Set Global Non-periodic IN NAK */ + +/* CGNPINNAK @Bit 8 : Clear Global Non-periodic IN NAK (CGNPInNak) */ + #define USBHSCORE_DCTL_CGNPINNAK_Pos (8UL) /*!< Position of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_CGNPINNAK_Pos) /*!< Bit mask of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Min (0x0UL) /*!< Min enumerator value of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_Max (0x1UL) /*!< Max enumerator value of CGNPINNAK field. */ + #define USBHSCORE_DCTL_CGNPINNAK_DISABLE (0x0UL) /*!< Disable Global Non-periodic IN NAK */ + #define USBHSCORE_DCTL_CGNPINNAK_ENABLE (0x1UL) /*!< Clear Global Non-periodic IN NAK */ + +/* SGOUTNAK @Bit 9 : Set Global OUT NAK (SGOUTNak) */ + #define USBHSCORE_DCTL_SGOUTNAK_Pos (9UL) /*!< Position of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_SGOUTNAK_Pos) /*!< Bit mask of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Min (0x0UL) /*!< Min enumerator value of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_Max (0x1UL) /*!< Max enumerator value of SGOUTNAK field. */ + #define USBHSCORE_DCTL_SGOUTNAK_DISABLED (0x0UL) /*!< Disable Global OUT NAK */ + #define USBHSCORE_DCTL_SGOUTNAK_ENABLED (0x1UL) /*!< Set Global OUT NAK */ + +/* CGOUTNAK @Bit 10 : Clear Global OUT NAK (CGOUTNak) */ + #define USBHSCORE_DCTL_CGOUTNAK_Pos (10UL) /*!< Position of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_CGOUTNAK_Pos) /*!< Bit mask of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Min (0x0UL) /*!< Min enumerator value of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_Max (0x1UL) /*!< Max enumerator value of CGOUTNAK field. */ + #define USBHSCORE_DCTL_CGOUTNAK_DISABLED (0x0UL) /*!< Disable Clear Global OUT NAK */ + #define USBHSCORE_DCTL_CGOUTNAK_ENABLED (0x1UL) /*!< Clear Global OUT NAK */ + +/* PWRONPRGDONE @Bit 11 : Power-On Programming Done (PWROnPrgDone) */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Pos (11UL) /*!< Position of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Msk (0x1UL << USBHSCORE_DCTL_PWRONPRGDONE_Pos) /*!< Bit mask of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Min (0x0UL) /*!< Min enumerator value of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_Max (0x1UL) /*!< Max enumerator value of PWRONPRGDONE field. */ + #define USBHSCORE_DCTL_PWRONPRGDONE_NOTDONE (0x0UL) /*!< Power-On Programming not done */ + #define USBHSCORE_DCTL_PWRONPRGDONE_DONE (0x1UL) /*!< Power-On Programming Done */ + +/* IGNRFRMNUM @Bit 15 : Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Pos (15UL) /*!< Position of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Msk (0x1UL << USBHSCORE_DCTL_IGNRFRMNUM_Pos) /*!< Bit mask of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Min (0x0UL) /*!< Min enumerator value of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_Max (0x1UL) /*!< Max enumerator value of IGNRFRMNUM field. */ + #define USBHSCORE_DCTL_IGNRFRMNUM_DISABLED (0x0UL) /*!< Scatter/Gather DMA Mode: The core transmits the packets only in the + frame number in which they are intended to be + transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt + feature is disabled.*/ + #define USBHSCORE_DCTL_IGNRFRMNUM_ENABLED (0x1UL) /*!< Scatter/Gather DMA Mode: The core ignores the frame number, sending + packets immediately as the packets are ready.Non-Scatter/Gather DMA + Mode: Periodic Transfer Interrupt feature is enabled.*/ + +/* NAKONBBLE @Bit 16 : NAK on Babble Error (NakOnBble) */ + #define USBHSCORE_DCTL_NAKONBBLE_Pos (16UL) /*!< Position of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Msk (0x1UL << USBHSCORE_DCTL_NAKONBBLE_Pos) /*!< Bit mask of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Min (0x0UL) /*!< Min enumerator value of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_Max (0x1UL) /*!< Max enumerator value of NAKONBBLE field. */ + #define USBHSCORE_DCTL_NAKONBBLE_DISABLED (0x0UL) /*!< Disable NAK on Babble Error */ + #define USBHSCORE_DCTL_NAKONBBLE_ENABLED (0x1UL) /*!< NAK on Babble Error */ + +/* DEEPSLEEPBESLREJECT @Bit 18 : DeepSleepBESLReject */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos (18UL) /*!< Position of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Msk (0x1UL << USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos) /*!< Bit mask of + DEEPSLEEPBESLREJECT field.*/ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Min (0x0UL) /*!< Min enumerator value of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Max (0x1UL) /*!< Max enumerator value of DEEPSLEEPBESLREJECT field. */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_DISABLED (0x0UL) /*!< Deep Sleep BESL Reject feature is disabled */ + #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_ENABLED (0x1UL) /*!< Deep Sleep BESL Reject feature is enabled */ + +/* SERVINT @Bit 19 : Service Interval based scheduling for Isochronous IN Endpoints */ + #define USBHSCORE_DCTL_SERVINT_Pos (19UL) /*!< Position of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Msk (0x1UL << USBHSCORE_DCTL_SERVINT_Pos) /*!< Bit mask of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Min (0x0UL) /*!< Min enumerator value of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_Max (0x1UL) /*!< Max enumerator value of SERVINT field. */ + #define USBHSCORE_DCTL_SERVINT_DISABLED (0x0UL) /*!< The controller behavior depends on DCTL.IgnrFrmNum field. */ + #define USBHSCORE_DCTL_SERVINT_ENABLED (0x1UL) /*!< Scatter/Gather DMA Mode: The controller can transmit the packets in + any frame of the service interval.*/ + +/* UTMITXVLDCORRDIS @Bit 30 : Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface. */ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_Pos (30UL) /*!< Position of UTMITXVLDCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_Msk (0x1UL << USBHSCORE_DCTL_UTMITXVLDCORRDIS_Pos) /*!< Bit mask of UTMITXVLDCORRDIS + field.*/ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_Min (0x0UL) /*!< Min enumerator value of UTMITXVLDCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_Max (0x1UL) /*!< Max enumerator value of UTMITXVLDCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_DISABLED (0x0UL) /*!< Opmode, XcvrSel, TermSel are changed by the Device Controller + after TxValid goes LOW (1'b0)on soft disconnect.*/ + #define USBHSCORE_DCTL_UTMITXVLDCORRDIS_ENABLED (0x1UL) /*!< Opmode, XcvrSel, TermSel are changed by the Device Controller + immediately on soft disconnect.*/ + +/* UTMITERMSELCORRDIS @Bit 31 : Disable the correction of TermSel on UTMI Interface. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Pos (31UL) /*!< Position of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Msk (0x1UL << USBHSCORE_DCTL_UTMITERMSELCORRDIS_Pos) /*!< Bit mask of + UTMITERMSELCORRDIS field.*/ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Min (0x0UL) /*!< Min enumerator value of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_Max (0x1UL) /*!< Max enumerator value of UTMITERMSELCORRDIS field. */ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_DISABLED (0x0UL) /*!< Valid Combination of XcvrSel and TermSel is driven by the + Device Controller.*/ + #define USBHSCORE_DCTL_UTMITERMSELCORRDIS_ENABLED (0x1UL) /*!< Invalid Combination of XcvrSel and TermSel is driven by the + Device Controller.*/ + + +/* USBHSCORE_DSTS: Device Status Register */ + #define USBHSCORE_DSTS_ResetValue (0x00000002UL) /*!< Reset value of DSTS register. */ + +/* SUSPSTS @Bit 0 : Suspend Status (SuspSts) */ + #define USBHSCORE_DSTS_SUSPSTS_Pos (0UL) /*!< Position of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Msk (0x1UL << USBHSCORE_DSTS_SUSPSTS_Pos) /*!< Bit mask of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Min (0x0UL) /*!< Min enumerator value of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_Max (0x1UL) /*!< Max enumerator value of SUSPSTS field. */ + #define USBHSCORE_DSTS_SUSPSTS_INACTIVE (0x0UL) /*!< No suspend state */ + #define USBHSCORE_DSTS_SUSPSTS_ACTIVE (0x1UL) /*!< Suspend state */ + +/* ENUMSPD @Bits 1..2 : Enumerated Speed (EnumSpd) */ + #define USBHSCORE_DSTS_ENUMSPD_Pos (1UL) /*!< Position of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Msk (0x3UL << USBHSCORE_DSTS_ENUMSPD_Pos) /*!< Bit mask of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Min (0x0UL) /*!< Min enumerator value of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_Max (0x3UL) /*!< Max enumerator value of ENUMSPD field. */ + #define USBHSCORE_DSTS_ENUMSPD_HS3060 (0x0UL) /*!< High speed (PHY clock is running at 30 or 60 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_FS3060 (0x1UL) /*!< Full speed (PHY clock is running at 30 or 60 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_LS6 (0x2UL) /*!< Low speed (PHY clock is running at 6 MHz) */ + #define USBHSCORE_DSTS_ENUMSPD_FS48 (0x3UL) /*!< Full speed (PHY clock is running at 48 MHz) */ + +/* ERRTICERR @Bit 3 : Erratic Error (ErrticErr) */ + #define USBHSCORE_DSTS_ERRTICERR_Pos (3UL) /*!< Position of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Msk (0x1UL << USBHSCORE_DSTS_ERRTICERR_Pos) /*!< Bit mask of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Min (0x0UL) /*!< Min enumerator value of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_Max (0x1UL) /*!< Max enumerator value of ERRTICERR field. */ + #define USBHSCORE_DSTS_ERRTICERR_INACTIVE (0x0UL) /*!< No Erratic Error */ + #define USBHSCORE_DSTS_ERRTICERR_ACTIVE (0x1UL) /*!< Erratic Error */ + +/* SOFFN @Bits 8..21 : Frame or Microframe Number of the Received SOF (SOFFN) */ + #define USBHSCORE_DSTS_SOFFN_Pos (8UL) /*!< Position of SOFFN field. */ + #define USBHSCORE_DSTS_SOFFN_Msk (0x3FFFUL << USBHSCORE_DSTS_SOFFN_Pos) /*!< Bit mask of SOFFN field. */ + +/* DEVLNSTS @Bits 22..23 : Device Line Status (DevLnSts) */ + #define USBHSCORE_DSTS_DEVLNSTS_Pos (22UL) /*!< Position of DEVLNSTS field. */ + #define USBHSCORE_DSTS_DEVLNSTS_Msk (0x3UL << USBHSCORE_DSTS_DEVLNSTS_Pos) /*!< Bit mask of DEVLNSTS field. */ + + +/* USBHSCORE_DIEPMSK: Device IN Endpoint Common Interrupt Mask Register */ + #define USBHSCORE_DIEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Mask Transfer Completed Interrupt */ + #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Interrupt Mask */ + +/* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos (1UL) /*!< Position of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Min (0x0UL) /*!< Min enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Max (0x1UL) /*!< Max enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< Mask Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< No Endpoint Disabled Interrupt Mask */ + +/* AHBERRMSK @Bit 2 : AHB Error Mask (AHBErrMsk) */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_MASK (0x0UL) /*!< Mask AHB Error Interrupt */ + #define USBHSCORE_DIEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Interrupt Mask */ + +/* TIMEOUTMSK @Bit 3 : Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos (3UL) /*!< Position of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos) /*!< Bit mask of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Min (0x0UL) /*!< Min enumerator value of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Max (0x1UL) /*!< Max enumerator value of TIMEOUTMSK field. */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_MASK (0x0UL) /*!< Mask Timeout Condition Interrupt */ + #define USBHSCORE_DIEPMSK_TIMEOUTMSK_NOMASK (0x1UL) /*!< No Timeout Condition Interrupt Mask */ + +/* INTKNTXFEMPMSK @Bit 4 : IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos (4UL) /*!< Position of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos) /*!< Bit mask of INTKNTXFEMPMSK + field.*/ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMPMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_MASK (0x0UL) /*!< Mask IN Token Received When TxFIFO Empty Interrupt */ + #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_NOMASK (0x1UL) /*!< No IN Token Received When TxFIFO Empty Interrupt */ + +/* INTKNEPMISMSK @Bit 5 : IN Token received with EP Mismatch Mask (INTknEPMisMsk) */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos (5UL) /*!< Position of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos) /*!< Bit mask of INTKNEPMISMSK + field.*/ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Min (0x0UL) /*!< Min enumerator value of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Max (0x1UL) /*!< Max enumerator value of INTKNEPMISMSK field. */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_MASK (0x0UL) /*!< Mask IN Token received with EP Mismatch Interrupt */ + #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_NOMASK (0x1UL) /*!< No Mask IN Token received with EP Mismatch Interrupt */ + +/* INEPNAKEFFMSK @Bit 6 : IN Endpoint NAK Effective Mask (INEPNakEffMsk) */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos (6UL) /*!< Position of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos) /*!< Bit mask of INEPNAKEFFMSK + field.*/ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFFMSK field. */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_MASK (0x0UL) /*!< Mask IN Endpoint NAK Effective Interrupt */ + #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_NOMASK (0x1UL) /*!< No IN Endpoint NAK Effective Interrupt Mask */ + +/* TXFIFOUNDRNMSK @Bit 8 : Fifo Underrun Mask (TxfifoUndrnMsk) */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos (8UL) /*!< Position of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos) /*!< Bit mask of TXFIFOUNDRNMSK + field.*/ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRNMSK field. */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_MASK (0x0UL) /*!< Mask Fifo Underrun Interrupt */ + #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_NOMASK (0x1UL) /*!< No Fifo Underrun Interrupt Mask */ + +/* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */ + #define USBHSCORE_DIEPMSK_NAKMSK_Pos (13UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_DIEPMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Interrupt */ + #define USBHSCORE_DIEPMSK_NAKMSK_NOMASK (0x1UL) /*!< No Mask NAK Interrupt */ + + +/* USBHSCORE_DOEPMSK: Device OUT Endpoint Common Interrupt Mask Register */ + #define USBHSCORE_DOEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DOEPMSK register. */ + +/* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field. */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< Mask Transfer Completed Interrupt */ + #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< No Transfer Completed Interrupt Mask */ + +/* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos (1UL) /*!< Position of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Min (0x0UL) /*!< Min enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Max (0x1UL) /*!< Max enumerator value of EPDISBLDMSK field. */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< Mask Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< No Endpoint Disabled Interrupt Mask */ + +/* AHBERRMSK @Bit 2 : AHB Error (AHBErrMsk) */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Pos (2UL) /*!< Position of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Min (0x0UL) /*!< Min enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_Max (0x1UL) /*!< Max enumerator value of AHBERRMSK field. */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_MASK (0x0UL) /*!< Mask AHB Error Interrupt */ + #define USBHSCORE_DOEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< No AHB Error Interrupt Mask */ + +/* SETUPMSK @Bit 3 : SETUP Phase Done Mask (SetUPMsk) */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Pos (3UL) /*!< Position of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_SETUPMSK_Pos) /*!< Bit mask of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Min (0x0UL) /*!< Min enumerator value of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_Max (0x1UL) /*!< Max enumerator value of SETUPMSK field. */ + #define USBHSCORE_DOEPMSK_SETUPMSK_MASK (0x0UL) /*!< Mask SETUP Phase Done Interrupt */ + #define USBHSCORE_DOEPMSK_SETUPMSK_NOMASK (0x1UL) /*!< No SETUP Phase Done Interrupt Mask */ + +/* OUTTKNEPDISMSK @Bit 4 : OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos (4UL) /*!< Position of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos) /*!< Bit mask of OUTTKNEPDISMSK + field.*/ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDISMSK field. */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_MASK (0x0UL) /*!< Mask OUT Token Received when Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_NOMASK (0x1UL) /*!< No OUT Token Received when Endpoint Disabled Interrupt Mask */ + +/* STSPHSERCVDMSK @Bit 5 : Status Phase Received Mask (StsPhseRcvdMsk) */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos (5UL) /*!< Position of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos) /*!< Bit mask of STSPHSERCVDMSK + field.*/ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVDMSK field. */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_MASK (0x0UL) /*!< Status Phase Received Mask */ + #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_NOMASK (0x1UL) /*!< No Status Phase Received Mask */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received Mask (Back2BackSETup) */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_MASK (0x0UL) /*!< Mask Back-to-Back SETUP Packets Received Interrupt */ + #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_NOMASK (0x1UL) /*!< No Back-to-Back SETUP Packets Received Interrupt Mask */ + +/* OUTPKTERRMSK @Bit 8 : OUT Packet Error Mask (OutPktErrMsk) */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos (8UL) /*!< Position of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos) /*!< Bit mask of OUTPKTERRMSK field.*/ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Min (0x0UL) /*!< Min enumerator value of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Max (0x1UL) /*!< Max enumerator value of OUTPKTERRMSK field. */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_MASK (0x0UL) /*!< Mask OUT Packet Error Interrupt */ + #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_NOMASK (0x1UL) /*!< No OUT Packet Error Interrupt Mask */ + +/* BBLEERRMSK @Bit 12 : Babble Error interrupt Mask (BbleErrMsk) */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Pos (12UL) /*!< Position of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_BBLEERRMSK_Pos) /*!< Bit mask of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Min (0x0UL) /*!< Min enumerator value of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_Max (0x1UL) /*!< Max enumerator value of BBLEERRMSK field. */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_MASK (0x0UL) /*!< Mask Babble Error Interrupt */ + #define USBHSCORE_DOEPMSK_BBLEERRMSK_NOMASK (0x1UL) /*!< No Babble Error Interrupt Mask */ + +/* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */ + #define USBHSCORE_DOEPMSK_NAKMSK_Pos (13UL) /*!< Position of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Min (0x0UL) /*!< Min enumerator value of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_Max (0x1UL) /*!< Max enumerator value of NAKMSK field. */ + #define USBHSCORE_DOEPMSK_NAKMSK_MASK (0x0UL) /*!< Mask NAK Interrupt */ + #define USBHSCORE_DOEPMSK_NAKMSK_NOMASK (0x1UL) /*!< No NAK Interrupt Mask */ + +/* NYETMSK @Bit 14 : NYET interrupt Mask (NYETMsk) */ + #define USBHSCORE_DOEPMSK_NYETMSK_Pos (14UL) /*!< Position of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Min (0x0UL) /*!< Min enumerator value of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_Max (0x1UL) /*!< Max enumerator value of NYETMSK field. */ + #define USBHSCORE_DOEPMSK_NYETMSK_MASK (0x0UL) /*!< Mask NYET Interrupt */ + #define USBHSCORE_DOEPMSK_NYETMSK_NOMASK (0x1UL) /*!< No NYET Interrupt Mask */ + + +/* USBHSCORE_DAINT: Device All Endpoints Interrupt Register */ + #define USBHSCORE_DAINT_ResetValue (0x00000000UL) /*!< Reset value of DAINT register. */ + +/* INEPINT0 @Bit 0 : IN Endpoint 0 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT0_Pos (0UL) /*!< Position of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Msk (0x1UL << USBHSCORE_DAINT_INEPINT0_Pos) /*!< Bit mask of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Min (0x0UL) /*!< Min enumerator value of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_Max (0x1UL) /*!< Max enumerator value of INEPINT0 field. */ + #define USBHSCORE_DAINT_INEPINT0_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT0_ACTIVE (0x1UL) /*!< Interrupt is active for IN EP0 */ + +/* INEPINT1 @Bit 1 : IN Endpoint 1 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT1_Pos (1UL) /*!< Position of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Msk (0x1UL << USBHSCORE_DAINT_INEPINT1_Pos) /*!< Bit mask of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Min (0x0UL) /*!< Min enumerator value of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_Max (0x1UL) /*!< Max enumerator value of INEPINT1 field. */ + #define USBHSCORE_DAINT_INEPINT1_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT1_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT2 @Bit 2 : IN Endpoint 2 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT2_Pos (2UL) /*!< Position of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Msk (0x1UL << USBHSCORE_DAINT_INEPINT2_Pos) /*!< Bit mask of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Min (0x0UL) /*!< Min enumerator value of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_Max (0x1UL) /*!< Max enumerator value of INEPINT2 field. */ + #define USBHSCORE_DAINT_INEPINT2_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT2_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT3 @Bit 3 : IN Endpoint 3 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT3_Pos (3UL) /*!< Position of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Msk (0x1UL << USBHSCORE_DAINT_INEPINT3_Pos) /*!< Bit mask of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Min (0x0UL) /*!< Min enumerator value of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_Max (0x1UL) /*!< Max enumerator value of INEPINT3 field. */ + #define USBHSCORE_DAINT_INEPINT3_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT3_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT4 @Bit 4 : IN Endpoint 4 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT4_Pos (4UL) /*!< Position of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Msk (0x1UL << USBHSCORE_DAINT_INEPINT4_Pos) /*!< Bit mask of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Min (0x0UL) /*!< Min enumerator value of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_Max (0x1UL) /*!< Max enumerator value of INEPINT4 field. */ + #define USBHSCORE_DAINT_INEPINT4_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT4_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT5 @Bit 5 : IN Endpoint 5 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT5_Pos (5UL) /*!< Position of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Msk (0x1UL << USBHSCORE_DAINT_INEPINT5_Pos) /*!< Bit mask of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Min (0x0UL) /*!< Min enumerator value of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_Max (0x1UL) /*!< Max enumerator value of INEPINT5 field. */ + #define USBHSCORE_DAINT_INEPINT5_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT5_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT6 @Bit 6 : IN Endpoint 6 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT6_Pos (6UL) /*!< Position of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Msk (0x1UL << USBHSCORE_DAINT_INEPINT6_Pos) /*!< Bit mask of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Min (0x0UL) /*!< Min enumerator value of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_Max (0x1UL) /*!< Max enumerator value of INEPINT6 field. */ + #define USBHSCORE_DAINT_INEPINT6_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT6_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT7 @Bit 7 : IN Endpoint 7 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT7_Pos (7UL) /*!< Position of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Msk (0x1UL << USBHSCORE_DAINT_INEPINT7_Pos) /*!< Bit mask of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Min (0x0UL) /*!< Min enumerator value of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_Max (0x1UL) /*!< Max enumerator value of INEPINT7 field. */ + #define USBHSCORE_DAINT_INEPINT7_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT7_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT8 @Bit 8 : IN Endpoint 8 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT8_Pos (8UL) /*!< Position of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Msk (0x1UL << USBHSCORE_DAINT_INEPINT8_Pos) /*!< Bit mask of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Min (0x0UL) /*!< Min enumerator value of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_Max (0x1UL) /*!< Max enumerator value of INEPINT8 field. */ + #define USBHSCORE_DAINT_INEPINT8_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT8_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT9 @Bit 9 : IN Endpoint 9 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT9_Pos (9UL) /*!< Position of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Msk (0x1UL << USBHSCORE_DAINT_INEPINT9_Pos) /*!< Bit mask of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Min (0x0UL) /*!< Min enumerator value of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_Max (0x1UL) /*!< Max enumerator value of INEPINT9 field. */ + #define USBHSCORE_DAINT_INEPINT9_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT9_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT10 @Bit 10 : IN Endpoint 10 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT10_Pos (10UL) /*!< Position of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Msk (0x1UL << USBHSCORE_DAINT_INEPINT10_Pos) /*!< Bit mask of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Min (0x0UL) /*!< Min enumerator value of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_Max (0x1UL) /*!< Max enumerator value of INEPINT10 field. */ + #define USBHSCORE_DAINT_INEPINT10_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT10_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* INEPINT11 @Bit 11 : IN Endpoint 11 Interrupt Bit */ + #define USBHSCORE_DAINT_INEPINT11_Pos (11UL) /*!< Position of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Msk (0x1UL << USBHSCORE_DAINT_INEPINT11_Pos) /*!< Bit mask of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Min (0x0UL) /*!< Min enumerator value of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_Max (0x1UL) /*!< Max enumerator value of INEPINT11 field. */ + #define USBHSCORE_DAINT_INEPINT11_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_INEPINT11_ACTIVE (0x1UL) /*!< Interrupt is active for the IN EP */ + +/* OUTEPINT0 @Bit 16 : OUT Endpoint 0 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT0_Pos (16UL) /*!< Position of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT0_Pos) /*!< Bit mask of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Min (0x0UL) /*!< Min enumerator value of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_Max (0x1UL) /*!< Max enumerator value of OUTEPINT0 field. */ + #define USBHSCORE_DAINT_OUTEPINT0_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT0_ACTIVE (0x1UL) /*!< Interrupt is active for OUT EP0 */ + +/* OUTEPINT1 @Bit 17 : OUT Endpoint 1 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT1_Pos (17UL) /*!< Position of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT1_Pos) /*!< Bit mask of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Min (0x0UL) /*!< Min enumerator value of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_Max (0x1UL) /*!< Max enumerator value of OUTEPINT1 field. */ + #define USBHSCORE_DAINT_OUTEPINT1_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT1_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT2 @Bit 18 : OUT Endpoint 2 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT2_Pos (18UL) /*!< Position of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT2_Pos) /*!< Bit mask of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Min (0x0UL) /*!< Min enumerator value of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_Max (0x1UL) /*!< Max enumerator value of OUTEPINT2 field. */ + #define USBHSCORE_DAINT_OUTEPINT2_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT2_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT3 @Bit 19 : OUT Endpoint 3 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT3_Pos (19UL) /*!< Position of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT3_Pos) /*!< Bit mask of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Min (0x0UL) /*!< Min enumerator value of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_Max (0x1UL) /*!< Max enumerator value of OUTEPINT3 field. */ + #define USBHSCORE_DAINT_OUTEPINT3_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT3_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT4 @Bit 20 : OUT Endpoint 4 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT4_Pos (20UL) /*!< Position of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT4_Pos) /*!< Bit mask of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Min (0x0UL) /*!< Min enumerator value of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_Max (0x1UL) /*!< Max enumerator value of OUTEPINT4 field. */ + #define USBHSCORE_DAINT_OUTEPINT4_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT4_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT5 @Bit 21 : OUT Endpoint 5 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT5_Pos (21UL) /*!< Position of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT5_Pos) /*!< Bit mask of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Min (0x0UL) /*!< Min enumerator value of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_Max (0x1UL) /*!< Max enumerator value of OUTEPINT5 field. */ + #define USBHSCORE_DAINT_OUTEPINT5_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT5_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT12 @Bit 28 : OUT Endpoint 12 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT12_Pos (28UL) /*!< Position of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT12_Pos) /*!< Bit mask of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Min (0x0UL) /*!< Min enumerator value of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_Max (0x1UL) /*!< Max enumerator value of OUTEPINT12 field. */ + #define USBHSCORE_DAINT_OUTEPINT12_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT12_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT13 @Bit 29 : OUT Endpoint 13 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT13_Pos (29UL) /*!< Position of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT13_Pos) /*!< Bit mask of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Min (0x0UL) /*!< Min enumerator value of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_Max (0x1UL) /*!< Max enumerator value of OUTEPINT13 field. */ + #define USBHSCORE_DAINT_OUTEPINT13_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT13_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT14 @Bit 30 : OUT Endpoint 14 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT14_Pos (30UL) /*!< Position of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT14_Pos) /*!< Bit mask of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Min (0x0UL) /*!< Min enumerator value of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_Max (0x1UL) /*!< Max enumerator value of OUTEPINT14 field. */ + #define USBHSCORE_DAINT_OUTEPINT14_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT14_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + +/* OUTEPINT15 @Bit 31 : OUT Endpoint 15 Interrupt Bit */ + #define USBHSCORE_DAINT_OUTEPINT15_Pos (31UL) /*!< Position of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT15_Pos) /*!< Bit mask of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Min (0x0UL) /*!< Min enumerator value of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_Max (0x1UL) /*!< Max enumerator value of OUTEPINT15 field. */ + #define USBHSCORE_DAINT_OUTEPINT15_INACTIVE (0x0UL) /*!< No Interrupt */ + #define USBHSCORE_DAINT_OUTEPINT15_ACTIVE (0x1UL) /*!< Interrupt is active for the OUT EP */ + + +/* USBHSCORE_DAINTMSK: Device All Endpoints Interrupt Mask Register */ + #define USBHSCORE_DAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of DAINTMSK register. */ + +/* INEPMSK0 @Bit 0 : IN Endpoint 0 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Pos (0UL) /*!< Position of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK0_Pos) /*!< Bit mask of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Min (0x0UL) /*!< Min enumerator value of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_Max (0x1UL) /*!< Max enumerator value of INEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK0_MASK (0x0UL) /*!< Mask IN Endpoint 0 Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK0_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK1 @Bit 1 : IN Endpoint 1 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Pos (1UL) /*!< Position of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK1_Pos) /*!< Bit mask of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Min (0x0UL) /*!< Min enumerator value of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_Max (0x1UL) /*!< Max enumerator value of INEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK1_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK1_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK2 @Bit 2 : IN Endpoint 2 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Pos (2UL) /*!< Position of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK2_Pos) /*!< Bit mask of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Min (0x0UL) /*!< Min enumerator value of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_Max (0x1UL) /*!< Max enumerator value of INEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK2_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK2_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK3 @Bit 3 : IN Endpoint 3 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Pos (3UL) /*!< Position of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK3_Pos) /*!< Bit mask of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Min (0x0UL) /*!< Min enumerator value of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_Max (0x1UL) /*!< Max enumerator value of INEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK3_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK3_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK4 @Bit 4 : IN Endpoint 4 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Pos (4UL) /*!< Position of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK4_Pos) /*!< Bit mask of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Min (0x0UL) /*!< Min enumerator value of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_Max (0x1UL) /*!< Max enumerator value of INEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK4_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK4_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK5 @Bit 5 : IN Endpoint 5 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Pos (5UL) /*!< Position of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK5_Pos) /*!< Bit mask of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Min (0x0UL) /*!< Min enumerator value of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_Max (0x1UL) /*!< Max enumerator value of INEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK5_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK5_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK6 @Bit 6 : IN Endpoint 6 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Pos (6UL) /*!< Position of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK6_Pos) /*!< Bit mask of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Min (0x0UL) /*!< Min enumerator value of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_Max (0x1UL) /*!< Max enumerator value of INEPMSK6 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK6_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK6_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK7 @Bit 7 : IN Endpoint 7 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Pos (7UL) /*!< Position of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK7_Pos) /*!< Bit mask of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Min (0x0UL) /*!< Min enumerator value of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_Max (0x1UL) /*!< Max enumerator value of INEPMSK7 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK7_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK7_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK8 @Bit 8 : IN Endpoint 8 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Pos (8UL) /*!< Position of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK8_Pos) /*!< Bit mask of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Min (0x0UL) /*!< Min enumerator value of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_Max (0x1UL) /*!< Max enumerator value of INEPMSK8 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK8_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK8_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK9 @Bit 9 : IN Endpoint 9 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Pos (9UL) /*!< Position of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK9_Pos) /*!< Bit mask of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Min (0x0UL) /*!< Min enumerator value of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_Max (0x1UL) /*!< Max enumerator value of INEPMSK9 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK9_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK9_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK10 @Bit 10 : IN Endpoint 10 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Pos (10UL) /*!< Position of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK10_Pos) /*!< Bit mask of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Min (0x0UL) /*!< Min enumerator value of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_Max (0x1UL) /*!< Max enumerator value of INEPMSK10 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK10_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK10_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* INEPMSK11 @Bit 11 : IN Endpoint 11 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Pos (11UL) /*!< Position of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK11_Pos) /*!< Bit mask of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Min (0x0UL) /*!< Min enumerator value of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_Max (0x1UL) /*!< Max enumerator value of INEPMSK11 field. */ + #define USBHSCORE_DAINTMSK_INEPMSK11_MASK (0x0UL) /*!< Mask IN Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_INEPMSK11_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK0 @Bit 16 : OUT Endpoint 0 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Pos (16UL) /*!< Position of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK0_Pos) /*!< Bit mask of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK0 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_MASK (0x0UL) /*!< Mask OUT Endpoint 0 Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK0_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK1 @Bit 17 : OUT Endpoint 1 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Pos (17UL) /*!< Position of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK1_Pos) /*!< Bit mask of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK1 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK1_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK2 @Bit 18 : OUT Endpoint 2 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Pos (18UL) /*!< Position of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK2_Pos) /*!< Bit mask of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK2 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK2_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK3 @Bit 19 : OUT Endpoint 3 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Pos (19UL) /*!< Position of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK3_Pos) /*!< Bit mask of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK3 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK3_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK4 @Bit 20 : OUT Endpoint 4 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Pos (20UL) /*!< Position of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK4_Pos) /*!< Bit mask of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK4 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK4_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK5 @Bit 21 : OUT Endpoint 5 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Pos (21UL) /*!< Position of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK5_Pos) /*!< Bit mask of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK5 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK5_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK12 @Bit 28 : OUT Endpoint 12 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Pos (28UL) /*!< Position of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK12_Pos) /*!< Bit mask of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK12 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK12_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK13 @Bit 29 : OUT Endpoint 13 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Pos (29UL) /*!< Position of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK13_Pos) /*!< Bit mask of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK13 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK13_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK14 @Bit 30 : OUT Endpoint 14 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Pos (30UL) /*!< Position of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK14_Pos) /*!< Bit mask of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK14 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK14_NOMASK (0x1UL) /*!< No Interrupt mask */ + +/* OUTEPMSK15 @Bit 31 : OUT Endpoint 15 Interrupt mask Bit */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Pos (31UL) /*!< Position of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK15_Pos) /*!< Bit mask of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Min (0x0UL) /*!< Min enumerator value of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_Max (0x1UL) /*!< Max enumerator value of OUTEPMSK15 field. */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_MASK (0x0UL) /*!< Mask OUT Endpoint Interrupt */ + #define USBHSCORE_DAINTMSK_OUTEPMSK15_NOMASK (0x1UL) /*!< No Interrupt mask */ + + +/* USBHSCORE_DVBUSDIS: Device VBUS Discharge Time Register */ + #define USBHSCORE_DVBUSDIS_ResetValue (0x000017D7UL) /*!< Reset value of DVBUSDIS register. */ + +/* DVBUSDIS @Bits 0..15 : Device VBUS Discharge Time (DVBUSDis) */ + #define USBHSCORE_DVBUSDIS_DVBUSDIS_Pos (0UL) /*!< Position of DVBUSDIS field. */ + #define USBHSCORE_DVBUSDIS_DVBUSDIS_Msk (0xFFFFUL << USBHSCORE_DVBUSDIS_DVBUSDIS_Pos) /*!< Bit mask of DVBUSDIS field. */ + + +/* USBHSCORE_DVBUSPULSE: Device VBUS Pulsing Time Register */ + #define USBHSCORE_DVBUSPULSE_ResetValue (0x000005B8UL) /*!< Reset value of DVBUSPULSE register. */ + +/* DVBUSPULSE @Bits 0..11 : Device VBUS Pulsing Time (DVBUSPulse) */ + #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos (0UL) /*!< Position of DVBUSPULSE field. */ + #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Msk (0xFFFUL << USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos) /*!< Bit mask of DVBUSPULSE + field.*/ + + +/* USBHSCORE_DTHRCTL: Device Threshold Control Register */ + #define USBHSCORE_DTHRCTL_ResetValue (0x08100020UL) /*!< Reset value of DTHRCTL register. */ + +/* NONISOTHREN @Bit 0 : Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Pos (0UL) /*!< Position of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_NONISOTHREN_Pos) /*!< Bit mask of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Min (0x0UL) /*!< Min enumerator value of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_Max (0x1UL) /*!< Max enumerator value of NONISOTHREN field. */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_DISABLED (0x0UL) /*!< No thresholding */ + #define USBHSCORE_DTHRCTL_NONISOTHREN_ENABLED (0x1UL) /*!< Enable thresholding for non-isochronous IN endpoints */ + +/* ISOTHREN @Bit 1 : (unspecified) */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Pos (1UL) /*!< Position of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_ISOTHREN_Pos) /*!< Bit mask of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Min (0x0UL) /*!< Min enumerator value of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_Max (0x1UL) /*!< Max enumerator value of ISOTHREN field. */ + #define USBHSCORE_DTHRCTL_ISOTHREN_DISABLED (0x0UL) /*!< No thresholding */ + #define USBHSCORE_DTHRCTL_ISOTHREN_ENABLED (0x1UL) /*!< Enables thresholding for isochronous IN endpoints */ + +/* TXTHRLEN @Bits 2..10 : Transmit Threshold Length (TxThrLen) */ + #define USBHSCORE_DTHRCTL_TXTHRLEN_Pos (2UL) /*!< Position of TXTHRLEN field. */ + #define USBHSCORE_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_TXTHRLEN_Pos) /*!< Bit mask of TXTHRLEN field. */ + +/* AHBTHRRATIO @Bits 11..12 : AHB Threshold Ratio (AHBThrRatio) */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos (11UL) /*!< Position of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Msk (0x3UL << USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos) /*!< Bit mask of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Min (0x0UL) /*!< Min enumerator value of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Max (0x3UL) /*!< Max enumerator value of AHBTHRRATIO field. */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESZERO (0x0UL) /*!< AHB threshold = MAC threshold */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESONE (0x1UL) /*!< AHB threshold = MAC threshold /2 */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTWO (0x2UL) /*!< AHB threshold = MAC threshold /4 */ + #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTHREE (0x3UL) /*!< AHB threshold = MAC threshold /8 */ + +/* RXTHREN @Bit 16 : Receive Threshold Enable (RxThrEn) */ + #define USBHSCORE_DTHRCTL_RXTHREN_Pos (16UL) /*!< Position of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_RXTHREN_Pos) /*!< Bit mask of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Min (0x0UL) /*!< Min enumerator value of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_Max (0x1UL) /*!< Max enumerator value of RXTHREN field. */ + #define USBHSCORE_DTHRCTL_RXTHREN_DISABLED (0x0UL) /*!< Disable thresholding */ + #define USBHSCORE_DTHRCTL_RXTHREN_ENABLED (0x1UL) /*!< Enable thresholding in the receive direction */ + +/* RXTHRLEN @Bits 17..25 : Receive Threshold Length (RxThrLen) */ + #define USBHSCORE_DTHRCTL_RXTHRLEN_Pos (17UL) /*!< Position of RXTHRLEN field. */ + #define USBHSCORE_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_RXTHRLEN_Pos) /*!< Bit mask of RXTHRLEN field. */ + +/* ARBPRKEN @Bit 27 : Arbiter Parking Enable (ArbPrkEn) */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Pos (27UL) /*!< Position of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Msk (0x1UL << USBHSCORE_DTHRCTL_ARBPRKEN_Pos) /*!< Bit mask of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Min (0x0UL) /*!< Min enumerator value of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_Max (0x1UL) /*!< Max enumerator value of ARBPRKEN field. */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_DISABLED (0x0UL) /*!< Disable DMA arbiter parking */ + #define USBHSCORE_DTHRCTL_ARBPRKEN_ENABLED (0x1UL) /*!< Enable DMA arbiter parking for IN endpoints */ + + +/* USBHSCORE_DIEPEMPMSK: Device IN Endpoint FIFO Empty Interrupt Mask Register */ + #define USBHSCORE_DIEPEMPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPEMPMSK register. */ + +/* INEPTXFEMPMSK @Bits 0..15 : IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos (0UL) /*!< Position of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Msk (0xFFFFUL << USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos) /*!< Bit mask of + INEPTXFEMPMSK field.*/ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Min (0x1UL) /*!< Min enumerator value of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Max (0x8000UL) /*!< Max enumerator value of INEPTXFEMPMSK field. */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP0_MASK (0x0001UL) /*!< Mask IN EP0 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP1_MASK (0x0002UL) /*!< Mask IN EP1 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP2_MASK (0x0004UL) /*!< Mask IN EP2 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP3_MASK (0x0008UL) /*!< Mask IN EP3 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP4_MASK (0x0010UL) /*!< Mask IN EP4 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP5_MASK (0x0020UL) /*!< Mask IN EP5 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP6_MASK (0x0040UL) /*!< Mask IN EP6 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP7_MASK (0x0080UL) /*!< Mask IN EP7 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP8_MASK (0x0100UL) /*!< Mask IN EP8 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP9_MASK (0x0200UL) /*!< Mask IN EP9 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP10_MASK (0x0400UL) /*!< Mask IN EP10 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP11_MASK (0x0800UL) /*!< Mask IN EP11 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP12_MASK (0x1000UL) /*!< Mask IN EP12 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP13_MASK (0x2000UL) /*!< Mask IN EP13 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP14_MASK (0x4000UL) /*!< Mask IN EP14 Tx FIFO Empty Interrupt */ + #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP15_MASK (0x8000UL) /*!< Mask IN EP15 Tx FIFO Empty Interrupt */ + + +/* USBHSCORE_DIEPCTL0: Device Control IN Endpoint 0 Control Register */ + #define USBHSCORE_DIEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DIEPCTL0 register. */ + +/* MPS @Bits 0..1 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL0_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DIEPCTL0_MPS_Pos) /*!< Bit mask of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Min (0x0UL) /*!< Min enumerator value of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_Max (0x3UL) /*!< Max enumerator value of MPS field. */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES64 (0x0UL) /*!< 64 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES32 (0x1UL) /*!< 32 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES16 (0x2UL) /*!< 16 bytes */ + #define USBHSCORE_DIEPCTL0_MPS_BYTES8 (0x3UL) /*!< 8 bytes */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Min (0x1UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL0_USBACTEP_ACTIVE0 (0x1UL) /*!< Control endpoint is always active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL0_NAKSTS_ACTIVE (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_Max (0x0UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL0_EPTYPE_ACTIVE (0x0UL) /*!< Endpoint Control 0 */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL0_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL0_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL0_STALL_INACTIVE (0x0UL) /*!< No Stall */ + #define USBHSCORE_DIEPCTL0_STALL_ACTIVE (0x1UL) /*!< Stall Handshake */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL0_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DIEPCTL0_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL0_CNAK_NOCLEAR (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_CNAK_CLEAR (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : (unspecified) */ + #define USBHSCORE_DIEPCTL0_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL0_SNAK_NOSET (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_SNAK_SET (0x1UL) /*!< Set NAK */ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL0_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL0_EPDIS_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_EPDIS_ACTIVE (0x1UL) /*!< Disabled Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL0_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL0_EPENA_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DIEPCTL0_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT0: Device IN Endpoint 0 Interrupt Register */ + #define USBHSCORE_DIEPINT0_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT0 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Completed Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT0_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT0_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT0_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT0_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT0_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT0_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received when TxFIFO Empty interrupt */ + #define USBHSCORE_DIEPINT0_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received when TxFIFO Empty Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT0_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT0_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_INACTIVE (0x0UL) /*!< No IN Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT0_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT0_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT0_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT0_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Fifo Underrun interrupt */ + #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< Fifo Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT0_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT0_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT0_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ0: Device IN Endpoint 0 Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ0 register. */ + +/* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..20 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ0_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ0_PKTCNT_Msk (0x3UL << USBHSCORE_DIEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + + +/* USBHSCORE_DIEPDMA0: Device IN Endpoint 0 DMA Address Register */ + #define USBHSCORE_DIEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA0 register. */ + +/* DMAADDR @Bits 0..31 : DMAAddr */ + #define USBHSCORE_DIEPDMA0_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS0: Device IN Endpoint Transmit FIFO Status Register 0 */ + #define USBHSCORE_DTXFSTS0_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS0 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL1: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL1 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL1_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL1_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL1_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL1_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL1_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL1_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL1_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL1_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL1_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL1_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL1_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL1_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL1_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL1_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL1_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL1_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL1_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL1_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL1_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL1_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL1_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL1_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL1_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL1_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL1_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL1_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL1_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL1_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT1: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT1_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT1 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT1_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT1_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT1_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT1_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT1_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT1_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT1_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT1_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT1_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT1_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT1_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT1_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT1_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT1_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT1_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT1_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT1_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ1: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ1 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ1_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ1_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ1_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ1_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA1: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA1 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA1_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS1: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS1_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS1 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL2: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL2 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL2_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL2_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL2_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL2_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL2_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL2_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL2_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL2_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL2_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL2_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL2_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL2_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL2_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL2_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL2_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL2_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL2_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL2_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL2_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL2_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL2_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL2_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL2_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL2_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL2_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL2_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL2_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL2_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT2: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT2_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT2 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT2_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT2_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT2_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT2_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT2_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT2_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT2_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT2_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT2_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT2_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT2_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT2_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT2_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT2_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT2_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT2_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT2_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ2: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ2 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ2_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ2_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ2_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ2_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA2: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA2 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA2_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS2: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS2_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS2 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL3: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL3 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL3_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL3_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL3_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL3_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL3_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL3_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL3_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL3_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL3_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL3_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL3_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL3_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL3_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL3_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL3_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL3_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL3_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL3_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL3_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL3_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL3_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL3_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL3_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL3_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL3_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL3_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL3_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL3_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT3: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT3_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT3 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT3_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT3_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT3_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT3_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT3_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT3_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT3_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT3_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT3_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT3_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT3_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT3_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT3_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT3_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT3_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT3_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT3_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ3: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ3 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ3_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ3_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ3_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ3_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA3: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA3 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA3_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS3: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS3_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS3 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL4: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL4 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL4_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL4_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL4_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL4_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL4_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL4_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL4_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL4_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL4_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL4_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL4_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL4_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL4_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL4_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL4_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL4_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL4_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL4_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL4_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL4_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL4_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL4_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL4_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL4_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL4_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL4_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL4_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL4_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT4: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT4_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT4 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT4_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT4_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT4_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT4_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT4_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT4_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT4_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT4_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT4_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT4_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT4_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT4_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT4_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT4_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT4_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT4_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT4_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ4: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ4 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ4_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ4_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ4_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ4_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA4: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA4 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA4_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS4: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS4_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS4 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL5: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL5 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL5_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL5_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL5_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL5_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL5_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL5_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL5_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL5_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL5_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL5_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL5_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL5_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL5_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL5_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL5_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL5_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL5_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL5_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL5_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL5_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL5_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL5_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL5_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL5_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL5_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL5_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL5_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL5_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT5: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT5_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT5 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT5_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT5_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT5_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT5_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT5_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT5_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT5_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT5_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT5_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT5_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT5_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT5_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT5_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT5_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT5_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT5_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT5_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ5: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ5 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ5_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ5_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ5_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ5_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA5: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA5 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA5_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS5: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS5_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS5 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL6: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL6_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL6 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL6_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL6_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL6_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL6_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL6_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL6_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL6_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL6_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL6_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL6_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL6_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL6_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL6_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL6_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL6_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL6_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL6_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL6_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL6_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL6_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL6_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL6_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL6_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL6_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL6_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL6_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL6_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL6_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL6_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL6_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL6_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL6_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL6_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL6_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL6_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL6_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL6_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL6_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL6_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT6: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT6_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT6 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT6_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT6_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT6_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT6_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT6_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT6_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT6_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT6_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT6_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT6_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT6_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT6_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT6_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT6_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT6_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT6_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT6_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT6_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT6_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT6_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT6_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT6_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT6_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT6_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT6_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT6_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT6_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT6_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT6_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT6_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT6_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ6: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ6_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ6 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ6_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ6_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ6_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ6_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ6_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ6_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA6: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA6_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA6 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA6_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA6_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA6_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS6: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS6_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS6 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL7: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL7_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL7 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL7_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL7_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL7_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL7_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL7_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL7_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL7_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL7_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL7_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL7_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL7_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL7_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL7_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL7_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL7_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL7_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL7_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL7_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL7_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL7_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL7_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL7_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL7_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL7_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL7_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL7_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL7_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL7_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL7_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL7_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL7_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL7_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL7_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL7_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL7_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL7_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL7_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL7_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL7_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT7: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT7_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT7 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT7_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT7_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT7_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT7_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT7_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT7_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT7_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT7_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT7_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT7_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT7_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT7_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT7_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT7_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT7_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT7_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT7_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT7_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT7_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT7_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT7_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT7_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT7_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT7_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT7_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT7_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT7_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT7_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT7_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT7_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT7_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ7: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ7_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ7 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ7_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ7_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ7_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ7_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ7_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ7_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA7: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA7_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA7 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA7_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA7_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA7_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS7: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS7_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS7 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL8: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL8_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL8 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL8_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL8_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL8_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL8_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL8_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL8_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL8_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL8_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL8_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL8_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL8_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL8_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL8_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL8_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL8_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL8_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL8_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL8_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL8_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL8_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL8_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL8_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL8_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL8_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL8_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL8_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL8_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL8_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL8_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL8_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL8_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL8_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL8_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL8_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL8_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL8_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL8_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL8_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL8_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT8: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT8_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT8 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT8_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT8_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT8_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT8_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT8_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT8_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT8_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT8_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT8_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT8_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT8_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT8_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT8_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT8_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT8_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT8_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT8_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT8_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT8_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT8_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT8_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT8_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT8_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT8_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT8_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT8_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT8_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT8_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT8_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT8_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT8_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ8: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ8_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ8 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ8_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ8_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ8_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ8_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ8_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ8_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA8: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA8_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA8 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA8_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA8_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA8_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS8: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS8_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS8 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL9: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL9_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL9 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL9_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL9_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL9_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL9_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL9_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL9_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL9_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL9_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL9_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL9_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL9_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL9_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL9_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL9_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL9_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL9_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL9_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL9_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL9_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL9_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL9_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL9_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL9_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL9_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL9_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL9_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL9_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL9_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL9_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL9_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL9_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL9_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL9_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL9_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL9_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL9_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL9_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL9_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL9_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT9: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT9_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT9 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT9_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT9_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT9_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT9_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT9_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT9_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT9_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT9_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT9_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT9_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT9_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT9_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT9_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT9_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT9_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT9_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT9_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT9_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT9_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT9_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT9_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT9_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT9_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT9_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT9_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT9_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT9_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT9_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT9_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT9_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT9_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ9: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ9_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ9 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ9_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ9_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ9_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ9_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ9_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ9_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA9: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA9_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA9 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA9_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA9_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA9_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS9: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS9_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS9 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL10: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL10_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL10 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL10_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL10_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL10_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL10_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL10_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL10_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL10_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL10_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL10_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL10_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL10_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL10_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL10_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL10_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL10_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL10_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL10_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL10_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL10_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL10_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL10_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL10_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL10_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL10_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL10_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL10_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL10_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL10_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL10_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL10_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL10_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL10_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL10_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL10_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL10_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL10_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL10_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL10_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL10_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT10: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT10_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT10 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT10_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT10_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT10_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT10_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT10_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT10_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT10_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT10_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT10_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT10_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT10_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT10_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT10_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT10_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT10_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT10_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT10_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT10_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT10_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT10_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT10_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT10_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT10_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT10_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT10_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT10_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT10_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT10_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT10_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT10_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT10_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ10: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ10_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ10 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ10_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ10_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ10_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ10_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ10_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ10_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA10: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA10_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA10 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA10_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA10_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA10_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS10: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS10_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS10 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DIEPCTL11: Device Control IN Endpoint Control Register */ + #define USBHSCORE_DIEPCTL11_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL11 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DIEPCTL11_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DIEPCTL11_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL11_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL11_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DIEPCTL11_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DIEPCTL11_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : (unspecified) */ + #define USBHSCORE_DIEPCTL11_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL11_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DIEPCTL11_DPID_DATA0EVENFRM (0x0UL) /*!< DATA0 or Even Frame */ + #define USBHSCORE_DIEPCTL11_DPID_DATA1ODDFRM (0x1UL) /*!< DATA1 or Odd Frame */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL11_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DIEPCTL11_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DIEPCTL11_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL11_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DIEPCTL11_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DIEPCTL11_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DIEPCTL11_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DIEPCTL11_EPTYPE_INTERRUP (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DIEPCTL11_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL11_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DIEPCTL11_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DIEPCTL11_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Pos (22UL) /*!< Position of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL11_TXFNUM_Pos) /*!< Bit mask of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Min (0x0UL) /*!< Min enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_Max (0xFUL) /*!< Max enumerator value of TXFNUM field. */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO0 (0x0UL) /*!< Tx FIFO 0 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO1 (0x1UL) /*!< Tx FIFO 1 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO2 (0x2UL) /*!< Tx FIFO 2 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO3 (0x3UL) /*!< Tx FIFO 3 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO4 (0x4UL) /*!< Tx FIFO 4 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO5 (0x5UL) /*!< Tx FIFO 5 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO6 (0x6UL) /*!< Tx FIFO 6 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO7 (0x7UL) /*!< Tx FIFO 7 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO8 (0x8UL) /*!< Tx FIFO 8 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO9 (0x9UL) /*!< Tx FIFO 9 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO10 (0xAUL) /*!< Tx FIFO 10 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO11 (0xBUL) /*!< Tx FIFO 11 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO12 (0xCUL) /*!< Tx FIFO 12 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO13 (0xDUL) /*!< Tx FIFO 13 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO14 (0xEUL) /*!< Tx FIFO 14 */ + #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO15 (0xFUL) /*!< Tx FIFO 15 */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DIEPCTL11_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DIEPCTL11_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DIEPCTL11_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DIEPCTL11_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DIEPCTL11_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DIEPCTL11_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DIEPCTL11_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even (micro)Frame */ + #define USBHSCORE_DIEPCTL11_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to Even + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DIEPCTL11_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd (micro)Frame */ + #define USBHSCORE_DIEPCTL11_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to Odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DIEPCTL11_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DIEPCTL11_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL11_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DIEPCTL11_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DIEPCTL11_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DIEPCTL11_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DIEPINT11: Device IN Endpoint Interrupt Register */ + #define USBHSCORE_DIEPINT11_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT11 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT11_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DIEPINT11_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT11_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DIEPINT11_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DIEPINT11_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DIEPINT11_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT11_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DIEPINT11_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DIEPINT11_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Pos (3UL) /*!< Position of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT11_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define USBHSCORE_DIEPINT11_TIMEOUT_INACTIVE (0x0UL) /*!< No Timeout interrupt */ + #define USBHSCORE_DIEPINT11_TIMEOUT_ACTIVE (0x1UL) /*!< Timeout interrupt */ + +/* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos (4UL) /*!< Position of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP + field.*/ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field. */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_INACTIVE (0x0UL) /*!< No IN Token Received interrupt */ + #define USBHSCORE_DIEPINT11_INTKNTXFEMP_ACTIVE (0x1UL) /*!< IN Token Received Interrupt */ + +/* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Pos (5UL) /*!< Position of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field. */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_INACTIVE (0x0UL) /*!< No IN Token Received with EP Mismatch interrupt */ + #define USBHSCORE_DIEPINT11_INTKNEPMIS_ACTIVE (0x1UL) /*!< IN Token Received with EP Mismatch interrupt */ + +/* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Pos (6UL) /*!< Position of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT11_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field. */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_INACTIVE (0x0UL) /*!< No Endpoint NAK Effective interrupt */ + #define USBHSCORE_DIEPINT11_INEPNAKEFF_ACTIVE (0x1UL) /*!< IN Endpoint NAK Effective interrupt */ + +/* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */ + #define USBHSCORE_DIEPINT11_TXFEMP_Pos (7UL) /*!< Position of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFEMP_Pos) /*!< Bit mask of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Min (0x0UL) /*!< Min enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_Max (0x1UL) /*!< Max enumerator value of TXFEMP field. */ + #define USBHSCORE_DIEPINT11_TXFEMP_INACTIVE (0x0UL) /*!< No Transmit FIFO Empty interrupt */ + #define USBHSCORE_DIEPINT11_TXFEMP_ACTIVE (0x1UL) /*!< Transmit FIFO Empty interrupt */ + +/* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos (8UL) /*!< Position of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN + field.*/ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field. */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< No Tx FIFO Underrun interrupt */ + #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< TxFIFO Underrun interrupt */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DIEPINT11_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT11_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DIEPINT11_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DIEPINT11_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT11_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT11_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DIEPINT11_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT11_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DIEPINT11_BBLEERR_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DIEPINT11_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DIEPINT11_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DIEPINT11_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + + +/* USBHSCORE_DIEPTSIZ11: Device IN Endpoint Transfer Size Register */ + #define USBHSCORE_DIEPTSIZ11_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ11 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DIEPTSIZ11_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DIEPTSIZ11_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ11_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* MC @Bits 29..30 : MC */ + #define USBHSCORE_DIEPTSIZ11_MC_Pos (29UL) /*!< Position of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ11_MC_Pos) /*!< Bit mask of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Min (0x1UL) /*!< Min enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_Max (0x3UL) /*!< Max enumerator value of MC field. */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETONE (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETTWO (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DIEPTSIZ11_MC_PACKETTHREE (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DIEPDMA11: Device IN Endpoint DMA Address Register */ + #define USBHSCORE_DIEPDMA11_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA11 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DIEPDMA11_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DIEPDMA11_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA11_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DTXFSTS11: Device IN Endpoint Transmit FIFO Status Register */ + #define USBHSCORE_DTXFSTS11_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS11 register. */ + +/* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */ + #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field. */ + #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of + INEPTXFSPCAVAIL field.*/ + + +/* USBHSCORE_DOEPCTL0: Device Control OUT Endpoint 0 Control Register */ + #define USBHSCORE_DOEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DOEPCTL0 register. */ + +/* MPS @Bits 0..1 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL0_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DOEPCTL0_MPS_Pos) /*!< Bit mask of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Min (0x0UL) /*!< Min enumerator value of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_Max (0x3UL) /*!< Max enumerator value of MPS field. */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE64 (0x0UL) /*!< 64 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE32 (0x1UL) /*!< 32 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE16 (0x2UL) /*!< 16 bytes */ + #define USBHSCORE_DOEPCTL0_MPS_BYTE8 (0x3UL) /*!< 8 bytes */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Min (0x1UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL0_USBACTEP_ACTIVE (0x1UL) /*!< USB Active Endpoint 0 */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL0_NAKSTS_ACTIVE (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_Max (0x0UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL0_EPTYPE_ACTIVE (0x0UL) /*!< Endpoint Control 0 */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL0_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL0_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL0_STALL_INACTIVE (0x0UL) /*!< No Stall */ + #define USBHSCORE_DOEPCTL0_STALL_ACTIVE (0x1UL) /*!< Stall Handshake */ + +/* CNAK @Bit 26 : Clear NAK (CNAK) */ + #define USBHSCORE_DOEPCTL0_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL0_CNAK_NOCLEAR (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_CNAK_CLEAR (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL0_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL0_SNAK_NOSET (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_SNAK_SET (0x1UL) /*!< Set NAK */ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL0_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_Max (0x0UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL0_EPDIS_INACTIVE (0x0UL) /*!< No Endpoint disable */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL0_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL0_EPENA_INACTIVE (0x0UL) /*!< No action */ + #define USBHSCORE_DOEPCTL0_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT0: Device OUT Endpoint 0 Interrupt Register */ + #define USBHSCORE_DOEPINT0_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT0 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT0_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT0_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT0_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT0_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT0_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT0_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT0_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT0_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT0_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT0_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT0_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT0_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT0_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ0: Device OUT Endpoint 0 Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ0 register. */ + +/* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bit 19 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ0_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ0_PKTCNT_Msk (0x1UL << USBHSCORE_DOEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* SUPCNT @Bits 29..30 : SETUP Packet Count (SUPCnt) */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Pos (29UL) /*!< Position of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Msk (0x3UL << USBHSCORE_DOEPTSIZ0_SUPCNT_Pos) /*!< Bit mask of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Min (0x1UL) /*!< Min enumerator value of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_Max (0x3UL) /*!< Max enumerator value of SUPCNT field. */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_ONEPACKET (0x1UL) /*!< 1 packet */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_TWOPACKET (0x2UL) /*!< 2 packets */ + #define USBHSCORE_DOEPTSIZ0_SUPCNT_THREEPACKET (0x3UL) /*!< 3 packets */ + + +/* USBHSCORE_DOEPDMA0: Device OUT Endpoint 0 DMA Address Register */ + #define USBHSCORE_DOEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA0 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA0_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL1: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL1 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL1_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL1_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL1_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL1_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL1_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL1_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL1_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL1_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL1_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL1_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL1_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL1_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL1_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL1_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL1_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL1_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL1_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL1_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL1_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL1_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL1_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL1_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL1_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL1_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL1_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL1_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL1_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT1: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT1_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT1 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT1_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT1_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT1_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT1_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT1_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT1_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT1_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT1_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT1_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT1_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT1_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT1_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT1_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ1: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ1 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ1_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ1_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ1_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA1: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA1 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA1_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL2: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL2 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL2_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL2_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL2_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL2_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL2_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL2_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL2_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL2_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL2_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL2_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL2_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL2_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL2_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL2_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL2_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL2_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL2_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL2_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL2_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL2_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL2_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL2_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL2_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL2_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL2_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL2_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL2_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT2: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT2_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT2 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT2_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT2_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT2_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT2_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT2_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT2_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT2_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT2_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT2_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT2_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT2_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT2_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT2_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ2: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ2 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ2_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ2_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ2_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA2: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA2 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA2_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL3: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL3 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL3_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL3_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL3_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL3_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL3_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL3_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL3_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL3_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL3_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL3_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL3_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL3_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL3_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL3_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL3_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL3_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL3_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL3_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL3_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL3_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL3_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL3_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL3_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL3_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL3_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL3_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL3_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT3: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT3_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT3 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT3_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT3_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT3_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT3_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT3_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT3_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT3_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT3_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT3_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT3_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT3_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT3_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT3_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ3: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ3 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ3_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ3_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ3_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA3: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA3 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA3_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL4: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL4 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL4_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL4_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL4_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL4_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL4_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL4_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL4_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL4_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL4_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL4_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL4_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL4_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL4_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL4_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL4_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL4_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL4_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL4_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL4_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL4_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL4_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL4_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL4_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL4_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL4_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL4_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL4_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT4: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT4_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT4 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT4_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT4_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT4_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT4_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT4_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT4_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT4_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT4_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT4_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT4_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT4_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT4_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT4_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ4: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ4 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ4_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ4_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ4_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA4: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA4 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA4_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL5: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL5 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL5_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL5_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL5_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL5_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL5_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL5_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL5_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL5_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL5_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL5_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL5_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL5_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL5_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL5_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL5_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL5_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL5_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL5_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL5_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL5_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL5_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL5_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL5_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL5_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL5_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL5_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL5_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT5: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT5_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT5 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT5_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT5_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT5_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT5_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT5_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT5_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT5_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP + field.*/ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT5_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT5_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT5_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT5_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT5_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT5_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ5: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ5 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ5_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ5_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ5_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA5: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA5 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA5_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL12: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL12_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL12 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL12_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL12_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL12_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL12_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL12_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL12_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL12_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL12_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL12_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL12_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL12_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL12_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL12_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL12_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL12_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL12_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL12_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL12_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL12_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL12_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL12_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL12_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL12_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL12_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL12_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL12_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL12_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL12_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL12_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL12_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL12_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL12_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL12_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL12_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL12_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL12_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL12_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL12_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT12: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT12_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT12 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT12_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT12_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT12_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT12_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT12_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT12_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT12_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT12_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT12_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT12_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT12_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT12_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT12_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT12_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT12_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT12_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT12_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT12_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT12_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT12_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT12_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT12_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT12_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT12_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT12_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT12_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT12_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ12: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ12_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ12 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ12_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ12_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ12_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ12_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ12_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA12: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA12_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA12 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA12_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA12_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA12_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL13: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL13_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL13 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL13_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL13_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL13_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL13_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL13_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL13_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL13_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL13_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL13_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL13_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL13_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL13_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL13_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL13_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL13_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL13_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL13_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL13_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL13_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL13_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL13_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL13_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL13_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL13_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL13_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL13_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL13_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL13_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL13_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL13_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL13_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL13_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL13_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL13_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL13_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL13_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL13_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL13_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT13: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT13_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT13 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT13_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT13_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT13_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT13_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT13_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT13_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT13_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT13_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT13_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT13_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT13_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT13_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT13_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT13_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT13_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT13_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT13_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT13_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT13_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT13_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT13_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT13_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT13_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT13_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT13_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT13_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT13_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ13: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ13_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ13 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ13_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ13_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ13_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ13_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ13_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA13: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA13_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA13 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA13_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA13_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA13_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL14: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL14_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL14 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL14_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL14_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL14_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL14_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL14_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL14_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL14_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL14_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL14_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL14_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL14_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL14_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL14_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL14_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL14_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL14_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL14_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL14_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL14_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL14_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL14_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL14_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL14_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL14_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL14_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL14_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL14_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL14_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL14_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL14_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL14_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL14_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL14_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL14_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL14_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL14_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL14_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL14_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT14: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT14_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT14 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT14_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT14_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT14_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT14_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT14_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT14_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT14_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT14_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT14_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT14_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT14_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT14_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT14_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT14_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT14_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT14_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT14_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT14_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT14_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT14_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT14_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT14_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT14_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT14_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT14_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT14_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT14_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ14: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ14_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ14 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ14_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ14_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ14_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ14_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ14_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA14: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA14_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA14 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA14_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA14_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA14_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_DOEPCTL15: Device Control OUT Endpoint Control Register */ + #define USBHSCORE_DOEPCTL15_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL15 register. */ + +/* MPS @Bits 0..10 : Maximum Packet Size (MPS) */ + #define USBHSCORE_DOEPCTL15_MPS_Pos (0UL) /*!< Position of MPS field. */ + #define USBHSCORE_DOEPCTL15_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL15_MPS_Pos) /*!< Bit mask of MPS field. */ + +/* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Pos (15UL) /*!< Position of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL15_USBACTEP_Pos) /*!< Bit mask of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Min (0x0UL) /*!< Min enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_Max (0x1UL) /*!< Max enumerator value of USBACTEP field. */ + #define USBHSCORE_DOEPCTL15_USBACTEP_DISABLED (0x0UL) /*!< Not Active */ + #define USBHSCORE_DOEPCTL15_USBACTEP_ENABLED (0x1UL) /*!< USB Active Endpoint */ + +/* DPID @Bit 16 : Endpoint Data PID (DPID) */ + #define USBHSCORE_DOEPCTL15_DPID_Pos (16UL) /*!< Position of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL15_DPID_Pos) /*!< Bit mask of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Min (0x0UL) /*!< Min enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_Max (0x1UL) /*!< Max enumerator value of DPID field. */ + #define USBHSCORE_DOEPCTL15_DPID_INACTIVE (0x0UL) /*!< Endpoint Data PID not active */ + #define USBHSCORE_DOEPCTL15_DPID_ACTIVE (0x1UL) /*!< Endpoint Data PID active */ + +/* NAKSTS @Bit 17 : NAK Status (NAKSts) */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Pos (17UL) /*!< Position of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL15_NAKSTS_Pos) /*!< Bit mask of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Min (0x0UL) /*!< Min enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_Max (0x1UL) /*!< Max enumerator value of NAKSTS field. */ + #define USBHSCORE_DOEPCTL15_NAKSTS_NONNAK (0x0UL) /*!< The core is transmitting non-NAK handshakes based on the FIFO status */ + #define USBHSCORE_DOEPCTL15_NAKSTS_NAK (0x1UL) /*!< The core is transmitting NAK handshakes on this endpoint */ + +/* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Pos (18UL) /*!< Position of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL15_EPTYPE_Pos) /*!< Bit mask of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Min (0x0UL) /*!< Min enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_Max (0x3UL) /*!< Max enumerator value of EPTYPE field. */ + #define USBHSCORE_DOEPCTL15_EPTYPE_CONTROL (0x0UL) /*!< Control */ + #define USBHSCORE_DOEPCTL15_EPTYPE_ISOCHRONOUS (0x1UL) /*!< Isochronous */ + #define USBHSCORE_DOEPCTL15_EPTYPE_BULK (0x2UL) /*!< Bulk */ + #define USBHSCORE_DOEPCTL15_EPTYPE_INTERRUPT (0x3UL) /*!< Interrupt */ + +/* STALL @Bit 21 : STALL Handshake (Stall) */ + #define USBHSCORE_DOEPCTL15_STALL_Pos (21UL) /*!< Position of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL15_STALL_Pos) /*!< Bit mask of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Min (0x0UL) /*!< Min enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_Max (0x1UL) /*!< Max enumerator value of STALL field. */ + #define USBHSCORE_DOEPCTL15_STALL_INACTIVE (0x0UL) /*!< STALL All non-active tokens */ + #define USBHSCORE_DOEPCTL15_STALL_ACTIVE (0x1UL) /*!< STALL All Active Tokens */ + +/* CNAK @Bit 26 : (unspecified) */ + #define USBHSCORE_DOEPCTL15_CNAK_Pos (26UL) /*!< Position of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_CNAK_Pos) /*!< Bit mask of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Min (0x0UL) /*!< Min enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_Max (0x1UL) /*!< Max enumerator value of CNAK field. */ + #define USBHSCORE_DOEPCTL15_CNAK_INACTIVE (0x0UL) /*!< No Clear NAK */ + #define USBHSCORE_DOEPCTL15_CNAK_ACTIVE (0x1UL) /*!< Clear NAK */ + +/* SNAK @Bit 27 : Set NAK (SNAK) */ + #define USBHSCORE_DOEPCTL15_SNAK_Pos (27UL) /*!< Position of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_SNAK_Pos) /*!< Bit mask of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Min (0x0UL) /*!< Min enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_Max (0x1UL) /*!< Max enumerator value of SNAK field. */ + #define USBHSCORE_DOEPCTL15_SNAK_INACTIVE (0x0UL) /*!< No Set NAK */ + #define USBHSCORE_DOEPCTL15_SNAK_ACTIVE (0x1UL) /*!< Set NAK */ + +/* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Pos (28UL) /*!< Position of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD0PID_Pos) /*!< Bit mask of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Min (0x0UL) /*!< Min enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_Max (0x1UL) /*!< Max enumerator value of SETD0PID field. */ + #define USBHSCORE_DOEPCTL15_SETD0PID_DISABLED (0x0UL) /*!< Disables Set DATA0 PID or Do not force Even Frame */ + #define USBHSCORE_DOEPCTL15_SETD0PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Pos (29UL) /*!< Position of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD1PID_Pos) /*!< Bit mask of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Min (0x0UL) /*!< Min enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_Max (0x1UL) /*!< Max enumerator value of SETD1PID field. */ + #define USBHSCORE_DOEPCTL15_SETD1PID_DISABLED (0x0UL) /*!< Disables Set DATA1 PID or Do not force Odd Frame */ + #define USBHSCORE_DOEPCTL15_SETD1PID_ENABLED (0x1UL) /*!< Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd + (micro)Frame*/ + +/* EPDIS @Bit 30 : Endpoint Disable (EPDis) */ + #define USBHSCORE_DOEPCTL15_EPDIS_Pos (30UL) /*!< Position of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPDIS_Pos) /*!< Bit mask of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Min (0x0UL) /*!< Min enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_Max (0x1UL) /*!< Max enumerator value of EPDIS field. */ + #define USBHSCORE_DOEPCTL15_EPDIS_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL15_EPDIS_ACTIVE (0x1UL) /*!< Disable Endpoint */ + +/* EPENA @Bit 31 : Endpoint Enable (EPEna) */ + #define USBHSCORE_DOEPCTL15_EPENA_Pos (31UL) /*!< Position of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPENA_Pos) /*!< Bit mask of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Min (0x0UL) /*!< Min enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_Max (0x1UL) /*!< Max enumerator value of EPENA field. */ + #define USBHSCORE_DOEPCTL15_EPENA_INACTIVE (0x0UL) /*!< No Action */ + #define USBHSCORE_DOEPCTL15_EPENA_ACTIVE (0x1UL) /*!< Enable Endpoint */ + + +/* USBHSCORE_DOEPINT15: Device OUT Endpoint Interrupt Register */ + #define USBHSCORE_DOEPINT15_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT15 register. */ + +/* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Pos (0UL) /*!< Position of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT15_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Min (0x0UL) /*!< Min enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_Max (0x1UL) /*!< Max enumerator value of XFERCOMPL field. */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_INACTIVE (0x0UL) /*!< No Transfer Complete Interrupt */ + #define USBHSCORE_DOEPINT15_XFERCOMPL_ACTIVE (0x1UL) /*!< Transfer Complete Interrupt */ + +/* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Pos (1UL) /*!< Position of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT15_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Min (0x0UL) /*!< Min enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_Max (0x1UL) /*!< Max enumerator value of EPDISBLD field. */ + #define USBHSCORE_DOEPINT15_EPDISBLD_INACTIVE (0x0UL) /*!< No Endpoint Disabled Interrupt */ + #define USBHSCORE_DOEPINT15_EPDISBLD_ACTIVE (0x1UL) /*!< Endpoint Disabled Interrupt */ + +/* AHBERR @Bit 2 : AHB Error (AHBErr) */ + #define USBHSCORE_DOEPINT15_AHBERR_Pos (2UL) /*!< Position of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT15_AHBERR_Pos) /*!< Bit mask of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Min (0x0UL) /*!< Min enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_Max (0x1UL) /*!< Max enumerator value of AHBERR field. */ + #define USBHSCORE_DOEPINT15_AHBERR_INACTIVE (0x0UL) /*!< No AHB Error Interrupt */ + #define USBHSCORE_DOEPINT15_AHBERR_ACTIVE (0x1UL) /*!< AHB Error interrupt */ + +/* SETUP @Bit 3 : SETUP Phase Done (SetUp) */ + #define USBHSCORE_DOEPINT15_SETUP_Pos (3UL) /*!< Position of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_SETUP_Pos) /*!< Bit mask of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Min (0x0UL) /*!< Min enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_Max (0x1UL) /*!< Max enumerator value of SETUP field. */ + #define USBHSCORE_DOEPINT15_SETUP_INACTIVE (0x0UL) /*!< No SETUP Phase Done */ + #define USBHSCORE_DOEPINT15_SETUP_ACTIVE (0x1UL) /*!< SETUP Phase Done */ + +/* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos (4UL) /*!< Position of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS + field.*/ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field. */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< No OUT Token Received When Endpoint Disabled */ + #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< OUT Token Received When Endpoint Disabled */ + +/* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Pos (5UL) /*!< Position of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD + field.*/ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field. */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_INACTIVE (0x0UL) /*!< No Status Phase Received for Control Write */ + #define USBHSCORE_DOEPINT15_STSPHSERCVD_ACTIVE (0x1UL) /*!< Status Phase Received for Control Write */ + +/* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos) /*!< Bit mask of + BACK2BACKSETUP field.*/ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field. */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< No Back-to-Back SETUP Packets Received */ + #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< Back-to-Back SETUP Packets Received */ + +/* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Pos (8UL) /*!< Position of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Min (0x0UL) /*!< Min enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_Max (0x1UL) /*!< Max enumerator value of OUTPKTERR field. */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_INACTIVE (0x0UL) /*!< No OUT Packet Error */ + #define USBHSCORE_DOEPINT15_OUTPKTERR_ACTIVE (0x1UL) /*!< OUT Packet Error */ + +/* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */ + #define USBHSCORE_DOEPINT15_BNAINTR_Pos (9UL) /*!< Position of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT15_BNAINTR_Pos) /*!< Bit mask of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Min (0x0UL) /*!< Min enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_Max (0x1UL) /*!< Max enumerator value of BNAINTR field. */ + #define USBHSCORE_DOEPINT15_BNAINTR_INACTIVE (0x0UL) /*!< No BNA interrupt */ + #define USBHSCORE_DOEPINT15_BNAINTR_ACTIVE (0x1UL) /*!< BNA interrupt */ + +/* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Pos (11UL) /*!< Position of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT15_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Min (0x0UL) /*!< Min enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_Max (0x1UL) /*!< Max enumerator value of PKTDRPSTS field. */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_INACTIVE (0x0UL) /*!< No interrupt */ + #define USBHSCORE_DOEPINT15_PKTDRPSTS_ACTIVE (0x1UL) /*!< Packet Drop Status interrupt */ + +/* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */ + #define USBHSCORE_DOEPINT15_BBLEERR_Pos (12UL) /*!< Position of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT15_BBLEERR_Pos) /*!< Bit mask of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Min (0x0UL) /*!< Min enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_Max (0x1UL) /*!< Max enumerator value of BBLEERR field. */ + #define USBHSCORE_DOEPINT15_BBLEERR_INACTIVE (0x0UL) /*!< No BbleErr interrupt */ + #define USBHSCORE_DOEPINT15_BBLEERR_ACTIVE (0x1UL) /*!< BbleErr interrupt */ + +/* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Pos (13UL) /*!< Position of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Min (0x0UL) /*!< Min enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_Max (0x1UL) /*!< Max enumerator value of NAKINTRPT field. */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_INACTIVE (0x0UL) /*!< No NAK interrupt */ + #define USBHSCORE_DOEPINT15_NAKINTRPT_ACTIVE (0x1UL) /*!< NAK Interrupt */ + +/* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Pos (14UL) /*!< Position of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field. */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_INACTIVE (0x0UL) /*!< No NYET interrupt */ + #define USBHSCORE_DOEPINT15_NYETINTRPT_ACTIVE (0x1UL) /*!< NYET Interrupt */ + +/* STUPPKTRCVD @Bit 15 : Setup Packet Received */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD + field.*/ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field. */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< No Setup packet received */ + #define USBHSCORE_DOEPINT15_STUPPKTRCVD_RCVD (0x1UL) /*!< Setup packet received */ + + +/* USBHSCORE_DOEPTSIZ15: Device OUT Endpoint Transfer Size Register */ + #define USBHSCORE_DOEPTSIZ15_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ15 register. */ + +/* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */ + #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos (0UL) /*!< Position of XFERSIZE field. */ + #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field. */ + +/* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */ + #define USBHSCORE_DOEPTSIZ15_PKTCNT_Pos (19UL) /*!< Position of PKTCNT field. */ + #define USBHSCORE_DOEPTSIZ15_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ15_PKTCNT_Pos) /*!< Bit mask of PKTCNT field. */ + +/* RXDPID @Bits 29..30 : RxDPID */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Pos (29UL) /*!< Position of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ15_RXDPID_Pos) /*!< Bit mask of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Min (0x0UL) /*!< Min enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_Max (0x3UL) /*!< Max enumerator value of RXDPID field. */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA0 (0x0UL) /*!< DATA0 */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA2PACKET1 (0x1UL) /*!< DATA2 or 1 packet */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA1PACKET2 (0x2UL) /*!< DATA1 or 2 packets */ + #define USBHSCORE_DOEPTSIZ15_RXDPID_MDATAPACKET3 (0x3UL) /*!< MDATA or 3 packets */ + + +/* USBHSCORE_DOEPDMA15: Device OUT Endpoint DMA Address Register */ + #define USBHSCORE_DOEPDMA15_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA15 register. */ + +/* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */ + #define USBHSCORE_DOEPDMA15_DMAADDR_Pos (0UL) /*!< Position of DMAADDR field. */ + #define USBHSCORE_DOEPDMA15_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA15_DMAADDR_Pos) /*!< Bit mask of DMAADDR field. */ + + +/* USBHSCORE_PCGCCTL: Power and Clock Gating Control Register */ + #define USBHSCORE_PCGCCTL_ResetValue (0x880A0000UL) /*!< Reset value of PCGCCTL register. */ + +/* STOPPCLK @Bit 0 : Stop Pclk (StopPclk) */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Pos (0UL) /*!< Position of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Msk (0x1UL << USBHSCORE_PCGCCTL_STOPPCLK_Pos) /*!< Bit mask of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Min (0x0UL) /*!< Min enumerator value of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_Max (0x1UL) /*!< Max enumerator value of STOPPCLK field. */ + #define USBHSCORE_PCGCCTL_STOPPCLK_DISABLED (0x0UL) /*!< Disable Stop Pclk */ + #define USBHSCORE_PCGCCTL_STOPPCLK_ENABLED (0x1UL) /*!< Enable Stop Pclk */ + +/* GATEHCLK @Bit 1 : Gate Hclk (GateHclk) */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Pos (1UL) /*!< Position of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Msk (0x1UL << USBHSCORE_PCGCCTL_GATEHCLK_Pos) /*!< Bit mask of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Min (0x0UL) /*!< Min enumerator value of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_Max (0x1UL) /*!< Max enumerator value of GATEHCLK field. */ + #define USBHSCORE_PCGCCTL_GATEHCLK_DISABLED (0x0UL) /*!< Clears this bit when the USB is resumed or a new session starts */ + #define USBHSCORE_PCGCCTL_GATEHCLK_ENABLED (0x1UL) /*!< Sets this bit to gate hclk to modules when the USB is suspended or the + session is not valid*/ + +/* RSTPDWNMODULE @Bit 3 : Reset Power-Down Modules (RstPdwnModule) */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos (3UL) /*!< Position of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Msk (0x1UL << USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos) /*!< Bit mask of RSTPDWNMODULE + field.*/ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Min (0x0UL) /*!< Min enumerator value of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Max (0x1UL) /*!< Max enumerator value of RSTPDWNMODULE field. */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_ON (0x0UL) /*!< Power is turned on */ + #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_OFF (0x1UL) /*!< Power is turned off */ + +/* ENBLL1GATING @Bit 5 : Enable Sleep Clock Gating */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Pos (5UL) /*!< Position of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Msk (0x1UL << USBHSCORE_PCGCCTL_ENBLL1GATING_Pos) /*!< Bit mask of ENBLL1GATING field.*/ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Min (0x0UL) /*!< Min enumerator value of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_Max (0x1UL) /*!< Max enumerator value of ENBLL1GATING field. */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_DISABLED (0x0UL) /*!< The PHY clock is not gated in Sleep state */ + #define USBHSCORE_PCGCCTL_ENBLL1GATING_ENABLED (0x1UL) /*!< The Core internal clock gating is enabled in Sleep state */ + +/* PHYSLEEP @Bit 6 : PHY In Sleep */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Pos (6UL) /*!< Position of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Msk (0x1UL << USBHSCORE_PCGCCTL_PHYSLEEP_Pos) /*!< Bit mask of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Min (0x0UL) /*!< Min enumerator value of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_Max (0x1UL) /*!< Max enumerator value of PHYSLEEP field. */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_INACTIVE (0x0UL) /*!< Phy not in Sleep state */ + #define USBHSCORE_PCGCCTL_PHYSLEEP_ACTIVE (0x1UL) /*!< Phy in Sleep state */ + +/* L1SUSPENDED @Bit 7 : L1 Deep Sleep */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Pos (7UL) /*!< Position of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Msk (0x1UL << USBHSCORE_PCGCCTL_L1SUSPENDED_Pos) /*!< Bit mask of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Min (0x0UL) /*!< Min enumerator value of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_Max (0x1UL) /*!< Max enumerator value of L1SUSPENDED field. */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_INACTIVE (0x0UL) /*!< Non Deep Sleep */ + #define USBHSCORE_PCGCCTL_L1SUSPENDED_ACTIVE (0x1UL) /*!< Deep Sleep */ + +/* RESTOREMODE @Bit 9 : Restore Mode (RestoreMode) */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Pos (9UL) /*!< Position of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Msk (0x1UL << USBHSCORE_PCGCCTL_RESTOREMODE_Pos) /*!< Bit mask of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Min (0x0UL) /*!< Min enumerator value of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_Max (0x1UL) /*!< Max enumerator value of RESTOREMODE field. */ + #define USBHSCORE_PCGCCTL_RESTOREMODE_DISABLED (0x0UL) /*!< In Host mode,this bit indicates Host-initiated Resume and Reset. + In Device mode, this bit indicates Device-initiated Remote Wakeup*/ + #define USBHSCORE_PCGCCTL_RESTOREMODE_ENABLED (0x1UL) /*!< In Host mode,this bit indicates Device-initiated Remote Wakeup. In + Device mode, this bit indicates Host-initiated Resume and Reset*/ + +/* ESSREGRESTORED @Bit 13 : Essential Register Values Restored (EssRegRestored) */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos (13UL) /*!< Position of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Msk (0x1UL << USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos) /*!< Bit mask of ESSREGRESTORED + field.*/ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Min (0x0UL) /*!< Min enumerator value of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Max (0x1UL) /*!< Max enumerator value of ESSREGRESTORED field. */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_NOT_RESTORED (0x0UL) /*!< Register values of essential registers are not restored */ + #define USBHSCORE_PCGCCTL_ESSREGRESTORED_RESTORED (0x1UL) /*!< Register values of essential registers have been restored */ + +/* RESTOREVALUE @Bits 14..31 : Restore Value (RestoreValue) */ + #define USBHSCORE_PCGCCTL_RESTOREVALUE_Pos (14UL) /*!< Position of RESTOREVALUE field. */ + #define USBHSCORE_PCGCCTL_RESTOREVALUE_Msk (0x3FFFFUL << USBHSCORE_PCGCCTL_RESTOREVALUE_Pos) /*!< Bit mask of RESTOREVALUE + field.*/ + + +/* USBHSCORE_GSTARFXDIS: Global STAR Fix Disable Register */ + #define USBHSCORE_GSTARFXDIS_ResetValue (0x00002200UL) /*!< Reset value of GSTARFXDIS register. */ + +/* HOSTIGNORESRMTWKUPDIS @Bit 0 : Disable the STAR fix added for Device controller to go back to low power mode when Host + ignores Remote wakeup */ + + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Pos (0UL) /*!< Position of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Pos) /*!< Bit mask + of HOSTIGNORESRMTWKUPDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Min (0x0UL) /*!< Min enumerator value of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_Max (0x1UL) /*!< Max enumerator value of HOSTIGNORESRMTWKUPDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_ENABLE_FIX (0x0UL) /*!< Device controller goes back into SUSPENDED state + when host ignores Remote Wakeup*/ + #define USBHSCORE_GSTARFXDIS_HOSTIGNORESRMTWKUPDIS_DISABLE_FIX (0x1UL) /*!< Device controller waits indefinitely without + entering SUSPENDED state when host ignores the + Remote Wakeup*/ + +/* RESUMEFRMCHKBUSDIS @Bit 1 : Disable the STAR fix added for Device controller to detect lineK and move to RESUMING state after + the 50us pull-up delay ends */ + + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Pos (1UL) /*!< Position of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Pos) /*!< Bit mask of + RESUMEFRMCHKBUSDIS field.*/ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Min (0x0UL) /*!< Min enumerator value of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_Max (0x1UL) /*!< Max enumerator value of RESUMEFRMCHKBUSDIS field. */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_ENABLE_FIX (0x0UL) /*!< Device controller detects line K and resumes */ + #define USBHSCORE_GSTARFXDIS_RESUMEFRMCHKBUSDIS_DISABLE_FIX (0x1UL) /*!< Device controller does not detect line K and resume */ + +/* IGNORECTLOUTDATA0DIS @Bit 2 : Disable the STAR fix added for Device controller to reject DATA0 for the first Control OUT Data + Phase and Control Status OUT Phase */ + + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Pos (2UL) /*!< Position of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Pos) /*!< Bit mask + of IGNORECTLOUTDATA0DIS field.*/ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Min (0x0UL) /*!< Min enumerator value of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_Max (0x1UL) /*!< Max enumerator value of IGNORECTLOUTDATA0DIS field. */ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_ENABLE_FIX (0x0UL) /*!< Transaction Error reported when host sends DATA0 + PID*/ + #define USBHSCORE_GSTARFXDIS_IGNORECTLOUTDATA0DIS_DISABLE_FIX (0x1UL) /*!< Transaction Error not reported when host sends + DATA0 PID*/ + +/* SSPLITSTALLNYETERRDIS @Bit 3 : Disable the STAR fix added for Host controller to flag error for SSPLIT STALL/NYET */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Pos (3UL) /*!< Position of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Pos) /*!< Bit mask + of SSPLITSTALLNYETERRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Min (0x0UL) /*!< Min enumerator value of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_Max (0x1UL) /*!< Max enumerator value of SSPLITSTALLNYETERRDIS field. */ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_ENABLE_FIX (0x0UL) /*!< Transaction Error reported when device sends + STALL/NYET for SSPLIT*/ + #define USBHSCORE_GSTARFXDIS_SSPLITSTALLNYETERRDIS_DISABLE_FIX (0x1UL) /*!< Transaction Error not reported when device sends + STALL/NYET for SSPLIT*/ + +/* ACCEPTISOCSPLITDATA1DIS @Bit 4 : Disable the STAR fix added for Host controller to accept DATA1 PID from device for ISOC + Split transfers */ + + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Pos (4UL) /*!< Position of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Pos) /*!< Bit + mask of ACCEPTISOCSPLITDATA1DIS field.*/ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Min (0x0UL) /*!< Min enumerator value of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_Max (0x1UL) /*!< Max enumerator value of ACCEPTISOCSPLITDATA1DIS field. */ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_ENABLE_FIX (0x0UL) /*!< Transaction Error not reported when device sends + DATA1 PID for ISOC Split*/ + #define USBHSCORE_GSTARFXDIS_ACCEPTISOCSPLITDATA1DIS_DISABLE_FIX (0x1UL) /*!< Transaction Error reported when device sends + DATA1 PID for ISOC Split*/ + +/* HANDLEFAULTYCABLEDIS @Bit 5 : Disable the STAR fix added for Host controller to handle Faulty cable scenarios */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Pos (5UL) /*!< Position of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Pos) /*!< Bit mask + of HANDLEFAULTYCABLEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Min (0x0UL) /*!< Min enumerator value of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_Max (0x1UL) /*!< Max enumerator value of HANDLEFAULTYCABLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_ENABLE_FIX (0x0UL) /*!< Fix for handling faulty cable enabled */ + #define USBHSCORE_GSTARFXDIS_HANDLEFAULTYCABLEDIS_DISABLE_FIX (0x1UL) /*!< Fix for handling faulty cable disabled */ + +/* LSIPGINCRDIS @Bit 6 : Disable the STAR fix added for Host controller LS mode IPG increment from 2 LS bit times to 3 LS bit + times */ + + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Pos (6UL) /*!< Position of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Pos) /*!< Bit mask of LSIPGINCRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Min (0x0UL) /*!< Min enumerator value of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_Max (0x1UL) /*!< Max enumerator value of LSIPGINCRDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_ENABLE_FIX (0x0UL) /*!< Host LS mode IPG is 3 LS bit times */ + #define USBHSCORE_GSTARFXDIS_LSIPGINCRDIS_DISABLE_FIX (0x1UL) /*!< Host LS mode IPG is 2 LS bit times */ + +/* FSDISCIDLEDIS @Bit 7 : Disable the STAR fix added for Device controller to transition to IDLE state during FS device + disconnect */ + + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Pos (7UL) /*!< Position of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Pos) /*!< Bit mask of + FSDISCIDLEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Min (0x0UL) /*!< Min enumerator value of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_Max (0x1UL) /*!< Max enumerator value of FSDISCIDLEDIS field. */ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_ENABLE_FIX (0x0UL) /*!< Device controller transitions to IDLE state during FS + device disconnect*/ + #define USBHSCORE_GSTARFXDIS_FSDISCIDLEDIS_DISABLE_FIX (0x1UL) /*!< Device controller does not transition to IDLE state during + FS device disconnect*/ + +/* CONCURRENTRMTWKUPUSBRESUMEDIS @Bit 8 : Disable the STAR fix added for Device controller to not start Remote Wakeup signalling + when USB resume has already started */ + + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Pos (8UL) /*!< Position of CONCURRENTRMTWKUPUSBRESUMEDIS field. */ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Pos) + /*!< Bit mask of CONCURRENTRMTWKUPUSBRESUMEDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Min (0x0UL) /*!< Min enumerator value of + CONCURRENTRMTWKUPUSBRESUMEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_Max (0x1UL) /*!< Max enumerator value of + CONCURRENTRMTWKUPUSBRESUMEDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_ENABLE_FIX (0x0UL) /*!< Device controller does not start remote + wakeup signalling when host resume has already + started*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEDIS_DISABLE_FIX (0x1UL) /*!< Device controller is allowed to start + remote wakeup signalling when host resume has + already started*/ + +/* CONCURRENTRMTWKUPUSBRESUMEHIBDIS @Bit 9 : Disable the STAR fix added for Device controller to not hang when Remote Wakeup + signalling clashes with Host resume */ + + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_Pos (9UL) /*!< Position of CONCURRENTRMTWKUPUSBRESUMEHIBDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_Pos) + /*!< Bit mask of CONCURRENTRMTWKUPUSBRESUMEHIBDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_Min (0x0UL) /*!< Min enumerator value of + CONCURRENTRMTWKUPUSBRESUMEHIBDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_Max (0x1UL) /*!< Max enumerator value of + CONCURRENTRMTWKUPUSBRESUMEHIBDIS field.*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_ENABLE_FIX (0x0UL) /*!< Device controller does not hang when + remote wakeup signalling clashes with host resume + during Hibernation exit*/ + #define USBHSCORE_GSTARFXDIS_CONCURRENTRMTWKUPUSBRESUMEHIBDIS_DISABLE_FIX (0x1UL) /*!< Device controller hangs when remote + wakeup signalling clashes with host resume during + Hibernation exit*/ + +/* LSIPGCHKAFTERNAKSTALLFORINDIS @Bit 10 : Disable the STAR fix added for Host controller to wait for IPG duration to send next + token after receiving NAK/STALL for previous IN token with FS/LS device */ + + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Pos (10UL) /*!< Position of LSIPGCHKAFTERNAKSTALLFORINDIS field. */ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Pos) + /*!< Bit mask of LSIPGCHKAFTERNAKSTALLFORINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Min (0x0UL) /*!< Min enumerator value of + LSIPGCHKAFTERNAKSTALLFORINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_Max (0x1UL) /*!< Max enumerator value of + LSIPGCHKAFTERNAKSTALLFORINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_ENABLE_FIX (0x0UL) /*!< Host controller checks IPG after NAK/STALL + for IN token*/ + #define USBHSCORE_GSTARFXDIS_LSIPGCHKAFTERNAKSTALLFORINDIS_DISABLE_FIX (0x1UL) /*!< Host controller does not check IPG after + NAK/STALL for IN token*/ + +/* PHYIOPXCVRSELTXVLDCORRDIS @Bit 11 : Disable the STAR fix added for Host controller to increase the gap between + utmi_xcvrselect switching and utmi_txvalid assertion in LS/FS mode */ + + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Pos (11UL) /*!< Position of PHYIOPXCVRSELTXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Pos) /*!< + Bit mask of PHYIOPXCVRSELTXVLDCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Min (0x0UL) /*!< Min enumerator value of PHYIOPXCVRSELTXVLDCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_Max (0x1UL) /*!< Max enumerator value of PHYIOPXCVRSELTXVLDCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_ENABLE_FIX (0x0UL) /*!< Host controller asserts utmi_txvalid at least 2 + utmi_clk cycles after utmi_xcvrselect switching*/ + #define USBHSCORE_GSTARFXDIS_PHYIOPXCVRSELTXVLDCORRDIS_DISABLE_FIX (0x1UL) /*!< Host controller can assert utmi_txvalid after + 1 utmi_clk cycle of utmi_xcvrselect switching*/ + +/* ULPIXCVRSELSWITCHCORRDIS @Bit 12 : Disable the STAR fix added for Host controller to increase the preamble transceiver select + switch delay to accommodate time taken for ULPI function control write */ + + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Pos (12UL) /*!< Position of ULPIXCVRSELSWITCHCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Pos) /*!< + Bit mask of ULPIXCVRSELSWITCHCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Min (0x0UL) /*!< Min enumerator value of ULPIXCVRSELSWITCHCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_Max (0x1UL) /*!< Max enumerator value of ULPIXCVRSELSWITCHCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_ENABLE_FIX (0x0UL) /*!< Host controller waits for previous functional + register update to complete before switching the + transceiver select again or asserting txvalid*/ + #define USBHSCORE_GSTARFXDIS_ULPIXCVRSELSWITCHCORRDIS_DISABLE_FIX (0x1UL) /*!< Host controller does not wait for the previous + functional register update to complete before + switching the transceiver select again or asserting + txvalid*/ + +/* XACTERRDATA0CTRLSTSINDIS @Bit 13 : Disable the STAR fix added for Host controller to report transaction error when DATA0 PID + is received for CTRL STATUS IN transfer in DMA mode */ + + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Pos (13UL) /*!< Position of XACTERRDATA0CTRLSTSINDIS field. */ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Pos) /*!< + Bit mask of XACTERRDATA0CTRLSTSINDIS field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Min (0x0UL) /*!< Min enumerator value of XACTERRDATA0CTRLSTSINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_Max (0x1UL) /*!< Max enumerator value of XACTERRDATA0CTRLSTSINDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_ENABLE_FIX (0x0UL) /*!< Host controller reports transaction error when + DATA0 PID is received for CTRL STATUS IN transfer in + DMA mode*/ + #define USBHSCORE_GSTARFXDIS_XACTERRDATA0CTRLSTSINDIS_DISABLE_FIX (0x1UL) /*!< Host controller retries the transfer when DATA0 + PID is received for CTRL STATUS IN transfer in DMA + mode*/ + +/* HOSTUTMITXVLDCORRDIS @Bit 16 : Disable the correction to OpMode/XcvrSel/TermSel on UTMI Interface in Host mode. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Pos (16UL) /*!< Position of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Pos) /*!< Bit mask + of HOSTUTMITXVLDCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Min (0x0UL) /*!< Min enumerator value of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_Max (0x1UL) /*!< Max enumerator value of HOSTUTMITXVLDCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_ENABLE_FIX (0x0UL) /*!< Opmode, XcvrSel, TermSel are changed by the Host + Controller after TxValid goes LOW (1'b0)*/ + #define USBHSCORE_GSTARFXDIS_HOSTUTMITXVLDCORRDIS_DISABLE_FIX (0x1UL) /*!< Opmode, XcvrSel, TermSel are changed by the Host + Controller without waiting for TxValid to go LOW + (1'b0) during SOF transmission*/ + +/* OPMODEXCVRSELCHIRPENCORRDIS @Bit 17 : Disable the STAR fix added for correcting Opmode and XcvrSel on UTMI Interface when + reset is detected in suspend state. */ + + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Pos (17UL) /*!< Position of OPMODEXCVRSELCHIRPENCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Pos) + /*!< Bit mask of OPMODEXCVRSELCHIRPENCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Min (0x0UL) /*!< Min enumerator value of OPMODEXCVRSELCHIRPENCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_Max (0x1UL) /*!< Max enumerator value of OPMODEXCVRSELCHIRPENCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_ENABLE_FIX (0x0UL) /*!< Valid Combination of Opmode and XcvrSel is + driven when reset is detected in suspend state*/ + #define USBHSCORE_GSTARFXDIS_OPMODEXCVRSELCHIRPENCORRDIS_DISABLE_FIX (0x1UL) /*!< Invalid Combination of Opmode and XcvrSel is + driven when reset is detected in suspend state*/ + +/* TXVALIDDEASSERTIONCORRDIS @Bit 18 : Disable the STAR fix added for correcting Txvalid deassertion on UTMI Interface when soft + disconnect is done. */ + + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Pos (18UL) /*!< Position of TXVALIDDEASSERTIONCORRDIS field. */ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Pos) /*!< + Bit mask of TXVALIDDEASSERTIONCORRDIS field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Min (0x0UL) /*!< Min enumerator value of TXVALIDDEASSERTIONCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_Max (0x1UL) /*!< Max enumerator value of TXVALIDDEASSERTIONCORRDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_ENABLE_FIX (0x0UL) /*!< Txvalid is deasserted during soft disconnect + after receiving Txready from the PHY*/ + #define USBHSCORE_GSTARFXDIS_TXVALIDDEASSERTIONCORRDIS_DISABLE_FIX (0x1UL) /*!< Txvalid is deasserted during soft disconnect + without waiting for Txready from the PHY*/ + +/* HOSTNOXFERAFTERPRTDISFIXDIS @Bit 19 : Disable the STAR fix added for correcting Host behavior when port is disabled. */ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Pos (19UL) /*!< Position of HOSTNOXFERAFTERPRTDISFIXDIS field. */ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Msk (0x1UL << USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Pos) + /*!< Bit mask of HOSTNOXFERAFTERPRTDISFIXDIS field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Min (0x0UL) /*!< Min enumerator value of HOSTNOXFERAFTERPRTDISFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_Max (0x1UL) /*!< Max enumerator value of HOSTNOXFERAFTERPRTDISFIXDIS + field.*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_ENABLE_FIX (0x0UL) /*!< Txvalid is not asserted when port is + disabled*/ + #define USBHSCORE_GSTARFXDIS_HOSTNOXFERAFTERPRTDISFIXDIS_DISABLE_FIX (0x1UL) /*!< Txvalid can be asserted when port is + disabled*/ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VDMADESCRIPTOR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ================================================== Struct VDMADESCRIPTOR ================================================== */ +/** + * @brief Job descriptor for vector-based DMA. + */ + typedef struct { /*!< VDMADESCRIPTOR Structure */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Pointer to data buffer. */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000004) Job configuration. Configuration of attributes and + buffer length.*/ + } NRF_VDMADESCRIPTOR_Type; /*!< Size = 8 (0x008) */ + +/* VDMADESCRIPTOR_PTR: Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register. */ + +/* PTR @Bits 0..31 : Pointer to data buffer. */ + #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ + #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + + +/* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */ + #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register. */ + +/* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL) /*!< Position of CNT field. */ + #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* ATTRIBUTE @Bits 24..29 : Job attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0x0UL) /*!< Min enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0x6UL) /*!< Max enumerator value of ATTRIBUTE field. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_ByteSwap (0x00UL) /*!< Byte swap attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_JobList (0x01UL) /*!< Job list attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_BufferFill (0x02UL) /*!< Buffer fill attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_FixedSize (0x03UL) /*!< Fixed size attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_StaticAddress (0x04UL) /*!< Static address attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_PlainDataBufferWrite (0x05UL) /*!< Plain data buffer write attribute. */ + #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Crc (0x06UL) /*!< CRC attribute. */ + +/* ACCESSTYPE @Bit 30 : Type of access. */ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Pos (30UL) /*!< Position of ACCESSTYPE field. */ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Msk (0x1UL << VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Pos) /*!< Bit mask of ACCESSTYPE + field.*/ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Min (0x0UL) /*!< Min enumerator value of ACCESSTYPE field. */ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Max (0x1UL) /*!< Max enumerator value of ACCESSTYPE field. */ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Memory (0x0UL) /*!< Memory access. */ + #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Peripheral (0x1UL) /*!< Peripheral register access. */ + +/* SELECTJOBENABLE @Bit 31 : Enables generation of event EVENTS_SELECTJOBDONE. */ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Pos (31UL) /*!< Position of SELECTJOBENABLE field. */ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Msk (0x1UL << VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Pos) /*!< Bit mask of + SELECTJOBENABLE field.*/ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Min (0x0UL) /*!< Min enumerator value of SELECTJOBENABLE field. */ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Max (0x1UL) /*!< Max enumerator value of SELECTJOBENABLE field. */ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Disable (0x0UL) /*!< Event is not generated. */ + #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Enable (0x1UL) /*!< Event is generated. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VPR ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* =================================================== Struct VPR_DEBUGIF ==================================================== */ +/** + * @brief DEBUGIF [VPR_DEBUGIF] (unspecified) + */ +typedef struct { + __IM uint32_t RESERVED[4]; + __IOM uint32_t DATA0; /*!< (@ 0x00000010) Abstract Data 0. Read/write data for argument 0 */ + __IOM uint32_t DATA1; /*!< (@ 0x00000014) Abstract Data 1. Read/write data for argument 1 */ + __IM uint32_t RESERVED1[10]; + __IOM uint32_t DMCONTROL; /*!< (@ 0x00000040) Debug Module Control */ + __IM uint32_t DMSTATUS; /*!< (@ 0x00000044) Debug Module Status */ + __IOM uint32_t HARTINFO; /*!< (@ 0x00000048) Hart Information */ + __IOM uint32_t HALTSUM1; /*!< (@ 0x0000004C) Halt Summary 1 */ + __IOM uint32_t HAWINDOWSEL; /*!< (@ 0x00000050) Hart Array Window Select */ + __IOM uint32_t HAWINDOW; /*!< (@ 0x00000054) Hart Array Window */ + __IOM uint32_t ABSTRACTCS; /*!< (@ 0x00000058) Abstract Control and Status */ + __OM uint32_t ABSTRACTCMD; /*!< (@ 0x0000005C) Abstract command */ + __IOM uint32_t ABSTRACTAUTO; /*!< (@ 0x00000060) Abstract Command Autoexec */ + __IOM uint32_t CONFSTRPTR[4]; /*!< (@ 0x00000064) Configuration String Pointer [n] */ + __IOM uint32_t NEXTDM; /*!< (@ 0x00000074) Next Debug Module */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t PROGBUF[16]; /*!< (@ 0x00000080) Program Buffer [n] */ + __IOM uint32_t AUTHDATA; /*!< (@ 0x000000C0) Authentication Data */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t HALTSUM2; /*!< (@ 0x000000D0) Halt Summary 2 */ + __IOM uint32_t HALTSUM3; /*!< (@ 0x000000D4) Halt Summary 3 */ + __IM uint32_t RESERVED4; + __IOM uint32_t SBADDRESS3; /*!< (@ 0x000000DC) System Bus Addres 127:96 */ + __IOM uint32_t SBCS; /*!< (@ 0x000000E0) System Bus Access Control and Status */ + __IOM uint32_t SBADDRESS0; /*!< (@ 0x000000E4) System Bus Addres 31:0 */ + __IOM uint32_t SBADDRESS1; /*!< (@ 0x000000E8) System Bus Addres 63:32 */ + __IOM uint32_t SBADDRESS2; /*!< (@ 0x000000EC) System Bus Addres 95:64 */ + __IOM uint32_t SBDATA0; /*!< (@ 0x000000F0) System Bus Data 31:0 */ + __IOM uint32_t SBDATA1; /*!< (@ 0x000000F4) System Bus Data 63:32 */ + __IOM uint32_t SBDATA2; /*!< (@ 0x000000F8) System Bus Data 95:64 */ + __IOM uint32_t SBDATA3; /*!< (@ 0x000000FC) System Bus Data 127:96 */ + __IOM uint32_t HALTSUM0; /*!< (@ 0x00000100) Halt summary 0 */ +} NRF_VPR_DEBUGIF_Type; /*!< Size = 260 (0x104) */ + +/* VPR_DEBUGIF_DATA0: Abstract Data 0. Read/write data for argument 0 */ + #define VPR_DEBUGIF_DATA0_ResetValue (0x00000000UL) /*!< Reset value of DATA0 register. */ + +/* DATA0 @Bits 0..31 : Abstract Data 0 */ + #define VPR_DEBUGIF_DATA0_DATA0_Pos (0UL) /*!< Position of DATA0 field. */ + #define VPR_DEBUGIF_DATA0_DATA0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA0_DATA0_Pos) /*!< Bit mask of DATA0 field. */ + + +/* VPR_DEBUGIF_DATA1: Abstract Data 1. Read/write data for argument 1 */ + #define VPR_DEBUGIF_DATA1_ResetValue (0x00000000UL) /*!< Reset value of DATA1 register. */ + +/* DATA1 @Bits 0..31 : Abstract Data 1 */ + #define VPR_DEBUGIF_DATA1_DATA1_Pos (0UL) /*!< Position of DATA1 field. */ + #define VPR_DEBUGIF_DATA1_DATA1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA1_DATA1_Pos) /*!< Bit mask of DATA1 field. */ + + +/* VPR_DEBUGIF_DMCONTROL: Debug Module Control */ + #define VPR_DEBUGIF_DMCONTROL_ResetValue (0x00000000UL) /*!< Reset value of DMCONTROL register. */ + +/* DMACTIVE @Bit 0 : Reset signal for the debug module. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos (0UL) /*!< Position of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos) /*!< Bit mask of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Min (0x0UL) /*!< Min enumerator value of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Max (0x1UL) /*!< Max enumerator value of DMACTIVE field. */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled (0x0UL) /*!< Reset the debug module itself */ + #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled (0x1UL) /*!< Normal operation */ + +/* NDMRESET @Bit 1 : Reset signal output from the debug module to the system. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos (1UL) /*!< Position of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos) /*!< Bit mask of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Min (0x0UL) /*!< Min enumerator value of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Max (0x1UL) /*!< Max enumerator value of NDMRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive (0x0UL) /*!< Reset inactive */ + #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Active (0x1UL) /*!< Reset active */ + +/* CLRRESETHALTREQ @Bit 2 : Clear the halt on reset request. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos (2UL) /*!< Position of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos) /*!< Bit mask of + CLRRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of CLRRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Clear (0x1UL) /*!< Clears the halt on reset request */ + +/* SETRESETHALTREQ @Bit 3 : Set the halt on reset request. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos (3UL) /*!< Position of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos) /*!< Bit mask of + SETRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of SETRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Clear (0x1UL) /*!< Sets the halt on reset request */ + +/* HARTSELHI @Bits 6..15 : The high 10 bits of hartsel. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos (6UL) /*!< Position of HARTSELHI field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos) /*!< Bit mask of HARTSELHI + field.*/ + +/* HARTSELLO @Bits 16..25 : The low 10 bits of hartsel. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos (16UL) /*!< Position of HARTSELLO field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos) /*!< Bit mask of HARTSELLO + field.*/ + +/* HASEL @Bit 26 : Definition of currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Pos (26UL) /*!< Position of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HASEL_Pos) /*!< Bit mask of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Min (0x0UL) /*!< Min enumerator value of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Max (0x1UL) /*!< Max enumerator value of HASEL field. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Single (0x0UL) /*!< Single hart selected. */ + #define VPR_DEBUGIF_DMCONTROL_HASEL_Multiple (0x1UL) /*!< Multiple harts selected */ + +/* ACKHAVERESET @Bit 28 : Clear the havereset. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos (28UL) /*!< Position of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos) /*!< Bit mask of ACKHAVERESET + field.*/ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Min (0x0UL) /*!< Min enumerator value of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Max (0x1UL) /*!< Max enumerator value of ACKHAVERESET field. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Clear (0x1UL) /*!< Clears the havereset for selected harts. */ + +/* HARTRESET @Bit 29 : Reset harts. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos (29UL) /*!< Position of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos) /*!< Bit mask of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Min (0x0UL) /*!< Min enumerator value of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Max (0x1UL) /*!< Max enumerator value of HARTRESET field. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Deasserted (0x0UL) /*!< Reset de-asserted. */ + #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Asserted (0x1UL) /*!< Reset asserted. */ + +/* RESUMEREQ @Bit 30 : Resume currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos (30UL) /*!< Position of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos) /*!< Bit mask of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Min (0x0UL) /*!< Min enumerator value of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Max (0x1UL) /*!< Max enumerator value of RESUMEREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_NoOperation (0x0UL) /*!< No operation when written 0. */ + #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Resumed (0x1UL) /*!< Currently selected harts resumed. */ + +/* HALTREQ @Bit 31 : Halt currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos (31UL) /*!< Position of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos) /*!< Bit mask of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Min (0x0UL) /*!< Min enumerator value of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Max (0x1UL) /*!< Max enumerator value of HALTREQ field. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Clear (0x0UL) /*!< Clears halt request bit for all currently selected harts. */ + #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Halt (0x1UL) /*!< Currently selected harts halted. */ + + +/* VPR_DEBUGIF_DMSTATUS: Debug Module Status */ + #define VPR_DEBUGIF_DMSTATUS_ResetValue (0x00400082UL) /*!< Reset value of DMSTATUS register. */ + +/* VERSION @Bits 0..3 : Version of the debug module. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Pos (0UL) /*!< Position of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Msk (0xFUL << VPR_DEBUGIF_DMSTATUS_VERSION_Pos) /*!< Bit mask of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Min (0x0UL) /*!< Min enumerator value of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_Max (0xFUL) /*!< Max enumerator value of VERSION field. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_NotPresent (0x0UL) /*!< Debug module not present. */ + #define VPR_DEBUGIF_DMSTATUS_VERSION_V011 (0x1UL) /*!< There is a Debug Module and it conforms to version 0.11 of this + specifcation.*/ + #define VPR_DEBUGIF_DMSTATUS_VERSION_V013 (0x2UL) /*!< There is a Debug Module and it conforms to version 0.13 of this + specifcation.*/ + #define VPR_DEBUGIF_DMSTATUS_VERSION_NonConform (0xFUL) /*!< There is a Debug Module but it does not conform to any available + version of the spec.*/ + +/* CONFSTRPTRVALID @Bit 4 : Configuration string. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos (4UL) /*!< Position of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos) /*!< Bit mask of + CONFSTRPTRVALID field.*/ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Min (0x0UL) /*!< Min enumerator value of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Max (0x1UL) /*!< Max enumerator value of CONFSTRPTRVALID field. */ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_NotRelevant (0x0UL) /*!< The confstrptr0..confstrptr3 holds information which is + not relevant to the configuration string.*/ + #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Address (0x1UL) /*!< The confstrptr0..confstrptr3 holds the address of the + configuration string.*/ + +/* HASRESETHALTREQ @Bit 5 : Halt-on-reset support status. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos (5UL) /*!< Position of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos) /*!< Bit mask of + HASRESETHALTREQ field.*/ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of HASRESETHALTREQ field. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_No (0x0UL) /*!< Halt-on-reset is supported. */ + #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Yes (0x1UL) /*!< Halt-on-reset is not supported. */ + +/* AUTHBUSY @Bit 6 : Authentication busy status. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos (6UL) /*!< Position of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos) /*!< Bit mask of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Min (0x0UL) /*!< Min enumerator value of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Max (0x1UL) /*!< Max enumerator value of AUTHBUSY field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_No (0x0UL) /*!< The authentication module is ready. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Yes (0x1UL) /*!< The authentication module is busy. */ + +/* AUTHENTICATED @Bit 7 : Authentication status. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos (7UL) /*!< Position of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos) /*!< Bit mask of + AUTHENTICATED field.*/ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Min (0x0UL) /*!< Min enumerator value of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Max (0x1UL) /*!< Max enumerator value of AUTHENTICATED field. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_No (0x0UL) /*!< Authentication required before using the debug module. */ + #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Yes (0x1UL) /*!< Authentication passed. */ + +/* ANYHALTED @Bit 8 : Any currently selected harts halted status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos (8UL) /*!< Position of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos) /*!< Bit mask of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Min (0x0UL) /*!< Min enumerator value of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Max (0x1UL) /*!< Max enumerator value of ANYHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_No (0x0UL) /*!< None of the currently selected harts halted. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Yes (0x1UL) /*!< Any of the currently selected harts halted. */ + +/* ALLHALTED @Bit 9 : All currently selected harts halted status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos (9UL) /*!< Position of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos) /*!< Bit mask of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Min (0x0UL) /*!< Min enumerator value of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Max (0x1UL) /*!< Max enumerator value of ALLHALTED field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_No (0x0UL) /*!< Not all of the currently selected harts halted. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Yes (0x1UL) /*!< All of the currently selected harts halted. */ + +/* ANYRUNNING @Bit 10 : Any currently selected harts running status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos (10UL) /*!< Position of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos) /*!< Bit mask of ANYRUNNING field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Min (0x0UL) /*!< Min enumerator value of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Max (0x1UL) /*!< Max enumerator value of ANYRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_No (0x0UL) /*!< None of the currently selected harts running. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Yes (0x1UL) /*!< Any of the currently selected harts running. */ + +/* ALLRUNNING @Bit 11 : All currently selected harts running status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos (11UL) /*!< Position of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos) /*!< Bit mask of ALLRUNNING field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Min (0x0UL) /*!< Min enumerator value of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Max (0x1UL) /*!< Max enumerator value of ALLRUNNING field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_No (0x0UL) /*!< Not all of the currently selected harts running. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Yes (0x1UL) /*!< All of the currently selected harts running. */ + +/* ANYUNAVAIL @Bit 12 : Any currently selected harts unavailable status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos (12UL) /*!< Position of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos) /*!< Bit mask of ANYUNAVAIL field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ANYUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_No (0x0UL) /*!< None of the currently selected harts unavailable. */ + #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Yes (0x1UL) /*!< Any of the currently selected harts unavailable. */ + +/* ALLUNAVAIL @Bit 13 : All currently selected harts unavailable status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos (13UL) /*!< Position of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos) /*!< Bit mask of ALLUNAVAIL field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ALLUNAVAIL field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_No (0x0UL) /*!< Not all of the currently selected harts unavailable. */ + #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Yes (0x1UL) /*!< All of the currently selected harts unavailable. */ + +/* ANYNONEXISTENT @Bit 14 : Any currently selected harts nonexistent status. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos (14UL) /*!< Position of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos) /*!< Bit mask of + ANYNONEXISTENT field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ANYNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_No (0x0UL) /*!< None of the currently selected harts nonexistent. */ + #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Yes (0x1UL) /*!< Any of the currently selected harts nonexistent. */ + +/* ALLNONEXISTENT @Bit 15 : All currently selected harts nonexistent status. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos (15UL) /*!< Position of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos) /*!< Bit mask of + ALLNONEXISTENT field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ALLNONEXISTENT field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_No (0x0UL) /*!< Not all of the currently selected harts nonexistent. */ + #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Yes (0x1UL) /*!< All of the currently selected harts nonexistent. */ + +/* ANYRESUMEACK @Bit 16 : Any currently selected harts acknowledged last resume request. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos (16UL) /*!< Position of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos) /*!< Bit mask of ANYRESUMEACK + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ANYRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_No (0x0UL) /*!< None of the currently selected harts acknowledged last resume + request.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Yes (0x1UL) /*!< Any of the currently selected harts acknowledged last resume + request.*/ + +/* ALLRESUMEACK @Bit 17 : All currently selected harts acknowledged last resume */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos (17UL) /*!< Position of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos) /*!< Bit mask of ALLRESUMEACK + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ALLRESUMEACK field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_No (0x0UL) /*!< Not all of the currently selected harts acknowledged last resume + request.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Yes (0x1UL) /*!< All of the currently selected harts acknowledged last resume + request.*/ + +/* ANYHAVERESET @Bit 18 : Any currently selected harts have been reset and reset is not acknowledged. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos (18UL) /*!< Position of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos) /*!< Bit mask of ANYHAVERESET + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Min (0x0UL) /*!< Min enumerator value of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Max (0x1UL) /*!< Max enumerator value of ANYHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_No (0x0UL) /*!< None of the currently selected harts have been reset and reset is + not acknowledget.*/ + #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Yes (0x1UL) /*!< Any of the currently selected harts have been reset and reset is + not acknowledge.*/ + +/* ALLHAVERESET @Bit 19 : All currently selected harts have been reset and reset is not acknowledge */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos (19UL) /*!< Position of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos) /*!< Bit mask of ALLHAVERESET + field.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Min (0x0UL) /*!< Min enumerator value of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Max (0x1UL) /*!< Max enumerator value of ALLHAVERESET field. */ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_No (0x0UL) /*!< Not all of the currently selected harts have been reset and reset is + not acknowledge.*/ + #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Yes (0x1UL) /*!< All of the currently selected harts have been reset and reset is + not acknowledge.*/ + +/* IMPEBREAK @Bit 22 : Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos (22UL) /*!< Position of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos) /*!< Bit mask of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Min (0x0UL) /*!< Min enumerator value of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Max (0x1UL) /*!< Max enumerator value of IMPEBREAK field. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_No (0x0UL) /*!< No implicit ebreak instruction. */ + #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Yes (0x1UL) /*!< Implicit ebreak instruction. */ + + +/* VPR_DEBUGIF_HARTINFO: Hart Information */ + #define VPR_DEBUGIF_HARTINFO_ResetValue (0x00000000UL) /*!< Reset value of HARTINFO register. */ + +/* DATAADDR @Bits 0..11 : Data Address */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Pos (0UL) /*!< Position of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Msk (0xFFFUL << VPR_DEBUGIF_HARTINFO_DATAADDR_Pos) /*!< Bit mask of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Min (0x800UL) /*!< Min value of DATAADDR field. */ + #define VPR_DEBUGIF_HARTINFO_DATAADDR_Max (0x7FFUL) /*!< Max size of DATAADDR field. */ + +/* DATASIZE @Bits 12..15 : Data Size */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Pos (12UL) /*!< Position of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_DATASIZE_Pos) /*!< Bit mask of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Min (0x0UL) /*!< Min value of DATASIZE field. */ + #define VPR_DEBUGIF_HARTINFO_DATASIZE_Max (0xCUL) /*!< Max size of DATASIZE field. */ + +/* DATAACCESS @Bit 16 : Data Access */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos (16UL) /*!< Position of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Msk (0x1UL << VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos) /*!< Bit mask of DATAACCESS field.*/ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Min (0x0UL) /*!< Min enumerator value of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Max (0x1UL) /*!< Max enumerator value of DATAACCESS field. */ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_No (0x0UL) /*!< The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN + bits in size, and corresponds to a single argument.*/ + #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Yes (0x1UL) /*!< The data registers are shadowed in the hart's memory map. Each + register takes up 4 bytes in the memory map.*/ + +/* NSCRATCH @Bits 20..23 : Number of dscratch registers */ + #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos (20UL) /*!< Position of NSCRATCH field. */ + #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos) /*!< Bit mask of NSCRATCH field. */ + + +/* VPR_DEBUGIF_HALTSUM1: Halt Summary 1 */ + #define VPR_DEBUGIF_HALTSUM1_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM1 register. */ + +/* HALTSUM1 @Bits 0..31 : Halt Summary 1 */ + #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos (0UL) /*!< Position of HALTSUM1 field. */ + #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos) /*!< Bit mask of HALTSUM1 + field.*/ + + +/* VPR_DEBUGIF_HAWINDOWSEL: Hart Array Window Select */ + #define VPR_DEBUGIF_HAWINDOWSEL_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOWSEL register. */ + +/* HAWINDOWSEL @Bits 0..14 : The high bits of this field may be tied to 0, depending on how large the array mask register is. + E.g. on a system with 48 harts only bit 0 of this field may actually be writable. */ + + #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos (0UL) /*!< Position of HAWINDOWSEL field. */ + #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Msk (0x7FFFUL << VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos) /*!< Bit mask of + HAWINDOWSEL field.*/ + + +/* VPR_DEBUGIF_HAWINDOW: Hart Array Window */ + #define VPR_DEBUGIF_HAWINDOW_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOW register. */ + +/* MASKDATA @Bits 0..31 : Mask data. */ + #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos (0UL) /*!< Position of MASKDATA field. */ + #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos) /*!< Bit mask of MASKDATA + field.*/ + + +/* VPR_DEBUGIF_ABSTRACTCS: Abstract Control and Status */ + #define VPR_DEBUGIF_ABSTRACTCS_ResetValue (0x01000002UL) /*!< Reset value of ABSTRACTCS register. */ + +/* DATACOUNT @Bits 0..3 : Number of data registers that are implemented as part of the abstract command interface. Valid sizes + are 1..12. */ + + #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos (0UL) /*!< Position of DATACOUNT field. */ + #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Msk (0xFUL << VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos) /*!< Bit mask of DATACOUNT + field.*/ + +/* CMDERR @Bits 8..10 : Command error when the abstract command fails. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos (8UL) /*!< Position of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Msk (0x7UL << VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos) /*!< Bit mask of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Min (0x0UL) /*!< Min enumerator value of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Max (0x7UL) /*!< Max enumerator value of CMDERR field. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NoError (0x0UL) /*!< No error. */ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Busy (0x1UL) /*!< An abstract command was executing while command, abstractcs, or + abstractauto was written, or when one of the data or progbuf registers + was read or written. This status is only written if cmderr contains 0*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NotSupported (0x2UL) /*!< The requested command is notsupported, regardless of whether + the hart is running or not.*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Exception (0x3UL) /*!< An exception occurred while executing the command (e.g. while + executing theProgram Buffer).*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_HaltResume (0x4UL) /*!< The abstract command couldn't execute because the hart wasn't in + the required state (running/halted). or unavailable.*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Bus (0x5UL) /*!< The abstract command failed due to abus error (e.g. alignment, access + size, or timeout).*/ + #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Other (0x7UL) /*!< The command failed for another reason. */ + +/* BUSY @Bit 12 : Abstract command execution status. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos (12UL) /*!< Position of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Msk (0x1UL << VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos) /*!< Bit mask of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_NotBusy (0x0UL) /*!< Not busy. */ + #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Busy (0x1UL) /*!< An abstract command is currently being executed. This bit is set as + soon as command is written, and is not cleared until that command has + completed.*/ + +/* PROGBUFSIZE @Bits 24..28 : Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. */ + #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos (24UL) /*!< Position of PROGBUFSIZE field. */ + #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Msk (0x1FUL << VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos) /*!< Bit mask of PROGBUFSIZE + field.*/ + + +/* VPR_DEBUGIF_ABSTRACTCMD: Abstract command */ + #define VPR_DEBUGIF_ABSTRACTCMD_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTCMD register. */ + +/* CONTROL @Bits 0..23 : This Field is interpreted in a command specific manner, described for each abstract command. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos (0UL) /*!< Position of CONTROL field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Msk (0xFFFFFFUL << VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos) /*!< Bit mask of CONTROL + field.*/ + +/* CMDTYPE @Bits 24..31 : The type determines the overall functionality of this abstract command. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos (24UL) /*!< Position of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Msk (0xFFUL << VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos) /*!< Bit mask of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Min (0x0UL) /*!< Min enumerator value of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Max (0x2UL) /*!< Max enumerator value of CMDTYPE field. */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_REGACCESS (0x00UL) /*!< Register Access Command */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_QUICKACCESS (0x01UL) /*!< Quick Access Command */ + #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_MEMACCESS (0x02UL) /*!< Memory Access Command */ + + +/* VPR_DEBUGIF_ABSTRACTAUTO: Abstract Command Autoexec */ + #define VPR_DEBUGIF_ABSTRACTAUTO_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTAUTO register. */ + +/* AUTOEXECDATA @Bits 0..11 : When a bit in this field is 1, read or write accesses to the corresponding data word cause the + command in command to be executed again. */ + + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos (0UL) /*!< Position of AUTOEXECDATA field. */ + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Msk (0xFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos) /*!< Bit mask of + AUTOEXECDATA field.*/ + +/* AUTOEXECPROGBUF @Bits 16..31 : When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause + the command in command to be executed again. */ + + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos (16UL) /*!< Position of AUTOEXECPROGBUF field. */ + #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Msk (0xFFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos) /*!< Bit mask + of AUTOEXECPROGBUF field.*/ + + +/* VPR_DEBUGIF_CONFSTRPTR: Configuration String Pointer [n] */ + #define VPR_DEBUGIF_CONFSTRPTR_MaxCount (4UL) /*!< Max size of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_MaxIndex (3UL) /*!< Max index of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_MinIndex (0UL) /*!< Min index of CONFSTRPTR[4] array. */ + #define VPR_DEBUGIF_CONFSTRPTR_ResetValue (0x00000000UL) /*!< Reset value of CONFSTRPTR[4] register. */ + +/* ADDR @Bits 0..31 : Address */ + #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* VPR_DEBUGIF_NEXTDM: Next Debug Module */ + #define VPR_DEBUGIF_NEXTDM_ResetValue (0x00000000UL) /*!< Reset value of NEXTDM register. */ + +/* ADDR @Bits 0..31 : Address */ + #define VPR_DEBUGIF_NEXTDM_ADDR_Pos (0UL) /*!< Position of ADDR field. */ + #define VPR_DEBUGIF_NEXTDM_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_NEXTDM_ADDR_Pos) /*!< Bit mask of ADDR field. */ + + +/* VPR_DEBUGIF_PROGBUF: Program Buffer [n] */ + #define VPR_DEBUGIF_PROGBUF_MaxCount (16UL) /*!< Max size of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_MaxIndex (15UL) /*!< Max index of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_MinIndex (0UL) /*!< Min index of PROGBUF[16] array. */ + #define VPR_DEBUGIF_PROGBUF_ResetValue (0x00000000UL) /*!< Reset value of PROGBUF[16] register. */ + +/* DATA @Bits 0..31 : Data */ + #define VPR_DEBUGIF_PROGBUF_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_PROGBUF_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_PROGBUF_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_AUTHDATA: Authentication Data */ + #define VPR_DEBUGIF_AUTHDATA_ResetValue (0x00000000UL) /*!< Reset value of AUTHDATA register. */ + +/* DATA @Bits 0..31 : Data */ + #define VPR_DEBUGIF_AUTHDATA_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_AUTHDATA_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_AUTHDATA_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_HALTSUM2: Halt Summary 2 */ + #define VPR_DEBUGIF_HALTSUM2_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM2 register. */ + +/* HALTSUM2 @Bits 0..31 : Halt Summary 2 */ + #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos (0UL) /*!< Position of HALTSUM2 field. */ + #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos) /*!< Bit mask of HALTSUM2 + field.*/ + + +/* VPR_DEBUGIF_HALTSUM3: Halt Summary 3 */ + #define VPR_DEBUGIF_HALTSUM3_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM3 register. */ + +/* HALTSUM3 @Bits 0..31 : Halt Summary 3 */ + #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos (0UL) /*!< Position of HALTSUM3 field. */ + #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos) /*!< Bit mask of HALTSUM3 + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS3: System Bus Addres 127:96 */ + #define VPR_DEBUGIF_SBADDRESS3_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS3 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBCS: System Bus Access Control and Status */ + #define VPR_DEBUGIF_SBCS_ResetValue (0x20000000UL) /*!< Reset value of SBCS register. */ + +/* SBACCESS8 @Bit 0 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Pos (0UL) /*!< Position of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS8_Pos) /*!< Bit mask of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Min (0x1UL) /*!< Min enumerator value of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_Max (0x1UL) /*!< Max enumerator value of SBACCESS8 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS8_sbaccess8 (0x1UL) /*!< 8-bit system bus accesses are supported. */ + +/* SBACCESS16 @Bit 1 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Pos (1UL) /*!< Position of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS16_Pos) /*!< Bit mask of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Min (0x1UL) /*!< Min enumerator value of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_Max (0x1UL) /*!< Max enumerator value of SBACCESS16 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS16_sbaccess16 (0x1UL) /*!< 16-bit system bus accesses are supported. */ + +/* SBACCESS32 @Bit 2 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Pos (2UL) /*!< Position of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS32_Pos) /*!< Bit mask of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Min (0x1UL) /*!< Min enumerator value of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_Max (0x1UL) /*!< Max enumerator value of SBACCESS32 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS32_sbaccess32 (0x1UL) /*!< 32-bit system bus accesses are supported. */ + +/* SBACCESS64 @Bit 3 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Pos (3UL) /*!< Position of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS64_Pos) /*!< Bit mask of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Min (0x1UL) /*!< Min enumerator value of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_Max (0x1UL) /*!< Max enumerator value of SBACCESS64 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS64_sbaccess64 (0x1UL) /*!< 64-bit system bus accesses are supported. */ + +/* SBACCESS128 @Bit 4 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Pos (4UL) /*!< Position of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS128_Pos) /*!< Bit mask of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Min (0x1UL) /*!< Min enumerator value of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_Max (0x1UL) /*!< Max enumerator value of SBACCESS128 field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS128_sbaccess128 (0x1UL) /*!< 128-bit system bus accesses are supported. */ + +/* SBASIZE @Bits 5..11 : Width of system bus addresses in bits. (0 indicates there is no bus access support.) */ + #define VPR_DEBUGIF_SBCS_SBASIZE_Pos (5UL) /*!< Position of SBASIZE field. */ + #define VPR_DEBUGIF_SBCS_SBASIZE_Msk (0x7FUL << VPR_DEBUGIF_SBCS_SBASIZE_Pos) /*!< Bit mask of SBASIZE field. */ + +/* SBERROR @Bits 12..14 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBERROR_Pos (12UL) /*!< Position of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBERROR_Pos) /*!< Bit mask of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Min (0x0UL) /*!< Min enumerator value of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Max (0x7UL) /*!< Max enumerator value of SBERROR field. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Normal (0x0UL) /*!< There was no bus error. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Timeout (0x1UL) /*!< There was a timeout. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Address (0x2UL) /*!< A bad address was accessed. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Alignment (0x3UL) /*!< There was an alignment error. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Size (0x4UL) /*!< An access of unsupported size was requested. */ + #define VPR_DEBUGIF_SBCS_SBERROR_Other (0x7UL) /*!< Other. */ + +/* SBREADONDATA @Bit 15 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Pos (15UL) /*!< Position of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONDATA_Pos) /*!< Bit mask of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Min (0x1UL) /*!< Min enumerator value of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_Max (0x1UL) /*!< Max enumerator value of SBREADONDATA field. */ + #define VPR_DEBUGIF_SBCS_SBREADONDATA_sbreadondata (0x1UL) /*!< Every read from sbdata0 automatically triggers a system bus + read at the (possibly autoincremented) address.*/ + +/* SBAUTOINCREMENT @Bit 16 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos (16UL) /*!< Position of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos) /*!< Bit mask of SBAUTOINCREMENT + field.*/ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Min (0x1UL) /*!< Min enumerator value of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Max (0x1UL) /*!< Max enumerator value of SBAUTOINCREMENT field. */ + #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_sbautoincrement (0x1UL) /*!< sbaddress is incremented by the access size (in bytes) + selected in sbaccess after every system bus access.*/ + +/* SBACCESS @Bits 17..19 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Pos (17UL) /*!< Position of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBACCESS_Pos) /*!< Bit mask of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Min (0x0UL) /*!< Min enumerator value of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_Max (0x4UL) /*!< Max enumerator value of SBACCESS field. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size8 (0x0UL) /*!< 8-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size16 (0x1UL) /*!< 16-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size32 (0x2UL) /*!< 32-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size64 (0x3UL) /*!< 64-bit. */ + #define VPR_DEBUGIF_SBCS_SBACCESS_size128 (0x4UL) /*!< 128-bit. */ + +/* SBREADONADDR @Bit 20 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Pos (20UL) /*!< Position of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONADDR_Pos) /*!< Bit mask of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Min (0x1UL) /*!< Min enumerator value of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_Max (0x1UL) /*!< Max enumerator value of SBREADONADDR field. */ + #define VPR_DEBUGIF_SBCS_SBREADONADDR_sbreadonaddr (0x1UL) /*!< Every write to sbaddress0 automatically triggers a system bus + read at the new address.*/ + +/* SBBUSY @Bit 21 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Pos (21UL) /*!< Position of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSY_Pos) /*!< Bit mask of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Min (0x0UL) /*!< Min enumerator value of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_Max (0x1UL) /*!< Max enumerator value of SBBUSY field. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_notbusy (0x0UL) /*!< System bus master is not busy. */ + #define VPR_DEBUGIF_SBCS_SBBUSY_busy (0x1UL) /*!< System bus master is busy. */ + +/* SBBUSYERROR @Bit 22 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos (22UL) /*!< Position of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos) /*!< Bit mask of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Min (0x0UL) /*!< Min enumerator value of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Max (0x1UL) /*!< Max enumerator value of SBBUSYERROR field. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_noerror (0x0UL) /*!< No error. */ + #define VPR_DEBUGIF_SBCS_SBBUSYERROR_error (0x1UL) /*!< Debugger access attempted while one in progress. */ + +/* SBVERSION @Bits 29..31 : (unspecified) */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Pos (29UL) /*!< Position of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBVERSION_Pos) /*!< Bit mask of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Min (0x0UL) /*!< Min enumerator value of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_Max (0x1UL) /*!< Max enumerator value of SBVERSION field. */ + #define VPR_DEBUGIF_SBCS_SBVERSION_version0 (0x0UL) /*!< The System Bus interface conforms to mainline drafts of thia RISC-V + External Debug Support spec older than 1 January, 2018.*/ + #define VPR_DEBUGIF_SBCS_SBVERSION_version1 (0x1UL) /*!< The System Bus interface conforms to RISC-V External Debug Support + version 0.14.0-DRAFT. Other values are reserved for future versions.*/ + + +/* VPR_DEBUGIF_SBADDRESS0: System Bus Addres 31:0 */ + #define VPR_DEBUGIF_SBADDRESS0_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS0 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 31:0 of the physical address in sbaddress. */ + #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS1: System Bus Addres 63:32 */ + #define VPR_DEBUGIF_SBADDRESS1_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS1 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBADDRESS2: System Bus Addres 95:64 */ + #define VPR_DEBUGIF_SBADDRESS2_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS2 register. */ + +/* ADDRESS @Bits 0..31 : Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide). */ + #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ + #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos) /*!< Bit mask of ADDRESS + field.*/ + + +/* VPR_DEBUGIF_SBDATA0: System Bus Data 31:0 */ + #define VPR_DEBUGIF_SBDATA0_ResetValue (0x00000000UL) /*!< Reset value of SBDATA0 register. */ + +/* DATA @Bits 0..31 : Accesses bits 31:0 of sbdata */ + #define VPR_DEBUGIF_SBDATA0_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA0_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA0_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA1: System Bus Data 63:32 */ + #define VPR_DEBUGIF_SBDATA1_ResetValue (0x00000000UL) /*!< Reset value of SBDATA1 register. */ + +/* DATA @Bits 0..31 : Accesses bits 63:32 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA1_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA1_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA2: System Bus Data 95:64 */ + #define VPR_DEBUGIF_SBDATA2_ResetValue (0x00000000UL) /*!< Reset value of SBDATA2 register. */ + +/* DATA @Bits 0..31 : Accesses bits 95:64 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA2_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA2_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA2_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_SBDATA3: System Bus Data 127:96 */ + #define VPR_DEBUGIF_SBDATA3_ResetValue (0x00000000UL) /*!< Reset value of SBDATA3 register. */ + +/* DATA @Bits 0..31 : Accesses bits 127:96 of sbdata (if the system bus is that wide). */ + #define VPR_DEBUGIF_SBDATA3_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPR_DEBUGIF_SBDATA3_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA3_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/* VPR_DEBUGIF_HALTSUM0: Halt summary 0 */ + #define VPR_DEBUGIF_HALTSUM0_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM0 register. */ + +/* HALTSUM0 @Bits 0..31 : Halt summary 0 */ + #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos (0UL) /*!< Position of HALTSUM0 field. */ + #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos) /*!< Bit mask of HALTSUM0 + field.*/ + + +/* ======================================================= Struct VPR ======================================================== */ +/** + * @brief VPR peripheral registers + */ + typedef struct { /*!< VPR Structure */ + __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) VPR task [n] register */ + __IOM uint32_t SUBSCRIBE_TRIGGER[32]; /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n] */ + __IOM uint32_t EVENTS_TRIGGERED[32]; /*!< (@ 0x00000100) VPR event [n] register */ + __IOM uint32_t PUBLISH_TRIGGERED[32]; /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n] */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ + __IM uint32_t RESERVED1[60]; + __IOM NRF_VPR_DEBUGIF_Type DEBUGIF; /*!< (@ 0x00000400) (unspecified) */ + __IM uint32_t RESERVED2[191]; + __IOM uint32_t CPURUN; /*!< (@ 0x00000800) State of the CPU after a core reset */ + __IM uint32_t RESERVED3; + __IOM uint32_t INITPC; /*!< (@ 0x00000808) Initial value of the PC at CPU start. */ + } NRF_VPR_Type; /*!< Size = 2060 (0x80C) */ + +/* VPR_TASKS_TRIGGER: VPR task [n] register */ + #define VPR_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ + #define VPR_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ + #define VPR_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ + #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + +/* TASKS_TRIGGER @Bit 0 : VPR task [n] register */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER + field.*/ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +/* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */ + #define VPR_SUBSCRIBE_TRIGGER_MaxCount (32UL) /*!< Max size of SUBSCRIBE_TRIGGER[32] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (31UL) /*!< Max index of SUBSCRIBE_TRIGGER[32] array. */ + #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL) /*!< Min index of SUBSCRIBE_TRIGGER[32] array. */ + #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[32] register. */ + +/* EN @Bit 31 : Subscription enable bit */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << VPR_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define VPR_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* VPR_EVENTS_TRIGGERED: VPR event [n] register */ + #define VPR_EVENTS_TRIGGERED_MaxCount (32UL) /*!< Max size of EVENTS_TRIGGERED[32] array. */ + #define VPR_EVENTS_TRIGGERED_MaxIndex (31UL) /*!< Max index of EVENTS_TRIGGERED[32] array. */ + #define VPR_EVENTS_TRIGGERED_MinIndex (0UL) /*!< Min index of EVENTS_TRIGGERED[32] array. */ + #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register. */ + +/* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of + EVENTS_TRIGGERED field.*/ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field. */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ + #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ + + +/* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */ + #define VPR_PUBLISH_TRIGGERED_MaxCount (32UL) /*!< Max size of PUBLISH_TRIGGERED[32] array. */ + #define VPR_PUBLISH_TRIGGERED_MaxIndex (31UL) /*!< Max index of PUBLISH_TRIGGERED[32] array. */ + #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL) /*!< Min index of PUBLISH_TRIGGERED[32] array. */ + #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[32] register. */ + +/* EN @Bit 31 : Publication enable bit */ + #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Msk (0x1UL << VPR_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define VPR_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* VPR_INTEN: Enable or disable interrupt */ + #define VPR_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ + #define VPR_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define VPR_INTEN_TRIGGERED0_Msk (0x1UL << VPR_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define VPR_INTEN_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define VPR_INTEN_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define VPR_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ + #define VPR_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define VPR_INTEN_TRIGGERED1_Msk (0x1UL << VPR_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define VPR_INTEN_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define VPR_INTEN_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define VPR_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ + #define VPR_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define VPR_INTEN_TRIGGERED2_Msk (0x1UL << VPR_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define VPR_INTEN_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define VPR_INTEN_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define VPR_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ + #define VPR_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define VPR_INTEN_TRIGGERED3_Msk (0x1UL << VPR_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define VPR_INTEN_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define VPR_INTEN_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define VPR_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ + #define VPR_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define VPR_INTEN_TRIGGERED4_Msk (0x1UL << VPR_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define VPR_INTEN_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define VPR_INTEN_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define VPR_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ + #define VPR_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define VPR_INTEN_TRIGGERED5_Msk (0x1UL << VPR_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define VPR_INTEN_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define VPR_INTEN_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define VPR_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ + #define VPR_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define VPR_INTEN_TRIGGERED6_Msk (0x1UL << VPR_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define VPR_INTEN_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define VPR_INTEN_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define VPR_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ + #define VPR_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define VPR_INTEN_TRIGGERED7_Msk (0x1UL << VPR_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define VPR_INTEN_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define VPR_INTEN_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define VPR_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ + #define VPR_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define VPR_INTEN_TRIGGERED8_Msk (0x1UL << VPR_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define VPR_INTEN_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define VPR_INTEN_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define VPR_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ + #define VPR_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define VPR_INTEN_TRIGGERED9_Msk (0x1UL << VPR_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define VPR_INTEN_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define VPR_INTEN_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define VPR_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ + #define VPR_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define VPR_INTEN_TRIGGERED10_Msk (0x1UL << VPR_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define VPR_INTEN_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define VPR_INTEN_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define VPR_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ + #define VPR_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define VPR_INTEN_TRIGGERED11_Msk (0x1UL << VPR_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define VPR_INTEN_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define VPR_INTEN_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define VPR_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ + #define VPR_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define VPR_INTEN_TRIGGERED12_Msk (0x1UL << VPR_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define VPR_INTEN_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define VPR_INTEN_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define VPR_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ + #define VPR_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define VPR_INTEN_TRIGGERED13_Msk (0x1UL << VPR_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define VPR_INTEN_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define VPR_INTEN_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define VPR_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ + #define VPR_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define VPR_INTEN_TRIGGERED14_Msk (0x1UL << VPR_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define VPR_INTEN_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define VPR_INTEN_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define VPR_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ + #define VPR_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define VPR_INTEN_TRIGGERED15_Msk (0x1UL << VPR_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define VPR_INTEN_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define VPR_INTEN_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define VPR_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */ + #define VPR_INTEN_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTEN_TRIGGERED16_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED16_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */ + #define VPR_INTEN_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Msk (0x1UL << VPR_INTEN_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTEN_TRIGGERED17_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED17_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */ + #define VPR_INTEN_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Msk (0x1UL << VPR_INTEN_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTEN_TRIGGERED18_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED18_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */ + #define VPR_INTEN_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Msk (0x1UL << VPR_INTEN_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTEN_TRIGGERED19_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED19_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */ + #define VPR_INTEN_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Msk (0x1UL << VPR_INTEN_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTEN_TRIGGERED20_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED20_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */ + #define VPR_INTEN_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Msk (0x1UL << VPR_INTEN_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTEN_TRIGGERED21_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED21_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */ + #define VPR_INTEN_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Msk (0x1UL << VPR_INTEN_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */ + #define VPR_INTEN_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define VPR_INTEN_TRIGGERED23_Msk (0x1UL << VPR_INTEN_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define VPR_INTEN_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define VPR_INTEN_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define VPR_INTEN_TRIGGERED23_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED23_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */ + #define VPR_INTEN_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define VPR_INTEN_TRIGGERED24_Msk (0x1UL << VPR_INTEN_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define VPR_INTEN_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define VPR_INTEN_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define VPR_INTEN_TRIGGERED24_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED24_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */ + #define VPR_INTEN_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define VPR_INTEN_TRIGGERED25_Msk (0x1UL << VPR_INTEN_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define VPR_INTEN_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define VPR_INTEN_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define VPR_INTEN_TRIGGERED25_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED25_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */ + #define VPR_INTEN_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define VPR_INTEN_TRIGGERED26_Msk (0x1UL << VPR_INTEN_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define VPR_INTEN_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define VPR_INTEN_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define VPR_INTEN_TRIGGERED26_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED26_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */ + #define VPR_INTEN_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define VPR_INTEN_TRIGGERED27_Msk (0x1UL << VPR_INTEN_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define VPR_INTEN_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define VPR_INTEN_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define VPR_INTEN_TRIGGERED27_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED27_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */ + #define VPR_INTEN_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define VPR_INTEN_TRIGGERED28_Msk (0x1UL << VPR_INTEN_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define VPR_INTEN_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define VPR_INTEN_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define VPR_INTEN_TRIGGERED28_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED28_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */ + #define VPR_INTEN_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define VPR_INTEN_TRIGGERED29_Msk (0x1UL << VPR_INTEN_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define VPR_INTEN_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define VPR_INTEN_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define VPR_INTEN_TRIGGERED29_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED29_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */ + #define VPR_INTEN_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define VPR_INTEN_TRIGGERED30_Msk (0x1UL << VPR_INTEN_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define VPR_INTEN_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define VPR_INTEN_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define VPR_INTEN_TRIGGERED30_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED30_Enabled (0x1UL) /*!< Enable */ + +/* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */ + #define VPR_INTEN_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define VPR_INTEN_TRIGGERED31_Msk (0x1UL << VPR_INTEN_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define VPR_INTEN_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define VPR_INTEN_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define VPR_INTEN_TRIGGERED31_Disabled (0x0UL) /*!< Disable */ + #define VPR_INTEN_TRIGGERED31_Enabled (0x1UL) /*!< Enable */ + + +/* VPR_INTENSET: Enable interrupt */ + #define VPR_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ + #define VPR_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define VPR_INTENSET_TRIGGERED0_Msk (0x1UL << VPR_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define VPR_INTENSET_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define VPR_INTENSET_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define VPR_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ + #define VPR_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define VPR_INTENSET_TRIGGERED1_Msk (0x1UL << VPR_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define VPR_INTENSET_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define VPR_INTENSET_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define VPR_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ + #define VPR_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define VPR_INTENSET_TRIGGERED2_Msk (0x1UL << VPR_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define VPR_INTENSET_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define VPR_INTENSET_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define VPR_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ + #define VPR_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define VPR_INTENSET_TRIGGERED3_Msk (0x1UL << VPR_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define VPR_INTENSET_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define VPR_INTENSET_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define VPR_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ + #define VPR_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define VPR_INTENSET_TRIGGERED4_Msk (0x1UL << VPR_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define VPR_INTENSET_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define VPR_INTENSET_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define VPR_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ + #define VPR_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define VPR_INTENSET_TRIGGERED5_Msk (0x1UL << VPR_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define VPR_INTENSET_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define VPR_INTENSET_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define VPR_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ + #define VPR_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define VPR_INTENSET_TRIGGERED6_Msk (0x1UL << VPR_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define VPR_INTENSET_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define VPR_INTENSET_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define VPR_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ + #define VPR_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define VPR_INTENSET_TRIGGERED7_Msk (0x1UL << VPR_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define VPR_INTENSET_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define VPR_INTENSET_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define VPR_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ + #define VPR_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define VPR_INTENSET_TRIGGERED8_Msk (0x1UL << VPR_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define VPR_INTENSET_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define VPR_INTENSET_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define VPR_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ + #define VPR_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define VPR_INTENSET_TRIGGERED9_Msk (0x1UL << VPR_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define VPR_INTENSET_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define VPR_INTENSET_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define VPR_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ + #define VPR_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define VPR_INTENSET_TRIGGERED10_Msk (0x1UL << VPR_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define VPR_INTENSET_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define VPR_INTENSET_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define VPR_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ + #define VPR_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define VPR_INTENSET_TRIGGERED11_Msk (0x1UL << VPR_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define VPR_INTENSET_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define VPR_INTENSET_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define VPR_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ + #define VPR_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define VPR_INTENSET_TRIGGERED12_Msk (0x1UL << VPR_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define VPR_INTENSET_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define VPR_INTENSET_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define VPR_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ + #define VPR_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define VPR_INTENSET_TRIGGERED13_Msk (0x1UL << VPR_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define VPR_INTENSET_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define VPR_INTENSET_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define VPR_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ + #define VPR_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define VPR_INTENSET_TRIGGERED14_Msk (0x1UL << VPR_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define VPR_INTENSET_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define VPR_INTENSET_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define VPR_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ + #define VPR_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define VPR_INTENSET_TRIGGERED15_Msk (0x1UL << VPR_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define VPR_INTENSET_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define VPR_INTENSET_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define VPR_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */ + #define VPR_INTENSET_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTENSET_TRIGGERED16_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */ + #define VPR_INTENSET_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Msk (0x1UL << VPR_INTENSET_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTENSET_TRIGGERED17_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */ + #define VPR_INTENSET_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Msk (0x1UL << VPR_INTENSET_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTENSET_TRIGGERED18_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */ + #define VPR_INTENSET_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Msk (0x1UL << VPR_INTENSET_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTENSET_TRIGGERED19_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */ + #define VPR_INTENSET_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Msk (0x1UL << VPR_INTENSET_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTENSET_TRIGGERED20_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */ + #define VPR_INTENSET_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Msk (0x1UL << VPR_INTENSET_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTENSET_TRIGGERED21_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */ + #define VPR_INTENSET_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Msk (0x1UL << VPR_INTENSET_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTENSET_TRIGGERED22_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */ + #define VPR_INTENSET_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define VPR_INTENSET_TRIGGERED23_Msk (0x1UL << VPR_INTENSET_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define VPR_INTENSET_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define VPR_INTENSET_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define VPR_INTENSET_TRIGGERED23_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */ + #define VPR_INTENSET_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define VPR_INTENSET_TRIGGERED24_Msk (0x1UL << VPR_INTENSET_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define VPR_INTENSET_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define VPR_INTENSET_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define VPR_INTENSET_TRIGGERED24_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */ + #define VPR_INTENSET_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define VPR_INTENSET_TRIGGERED25_Msk (0x1UL << VPR_INTENSET_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define VPR_INTENSET_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define VPR_INTENSET_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define VPR_INTENSET_TRIGGERED25_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */ + #define VPR_INTENSET_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define VPR_INTENSET_TRIGGERED26_Msk (0x1UL << VPR_INTENSET_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define VPR_INTENSET_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define VPR_INTENSET_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define VPR_INTENSET_TRIGGERED26_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */ + #define VPR_INTENSET_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define VPR_INTENSET_TRIGGERED27_Msk (0x1UL << VPR_INTENSET_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define VPR_INTENSET_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define VPR_INTENSET_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define VPR_INTENSET_TRIGGERED27_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */ + #define VPR_INTENSET_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define VPR_INTENSET_TRIGGERED28_Msk (0x1UL << VPR_INTENSET_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define VPR_INTENSET_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define VPR_INTENSET_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define VPR_INTENSET_TRIGGERED28_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */ + #define VPR_INTENSET_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define VPR_INTENSET_TRIGGERED29_Msk (0x1UL << VPR_INTENSET_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define VPR_INTENSET_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define VPR_INTENSET_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define VPR_INTENSET_TRIGGERED29_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */ + #define VPR_INTENSET_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define VPR_INTENSET_TRIGGERED30_Msk (0x1UL << VPR_INTENSET_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define VPR_INTENSET_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define VPR_INTENSET_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define VPR_INTENSET_TRIGGERED30_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */ + #define VPR_INTENSET_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define VPR_INTENSET_TRIGGERED31_Msk (0x1UL << VPR_INTENSET_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define VPR_INTENSET_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define VPR_INTENSET_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define VPR_INTENSET_TRIGGERED31_Set (0x1UL) /*!< Enable */ + #define VPR_INTENSET_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENSET_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VPR_INTENCLR: Disable interrupt */ + #define VPR_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ + #define VPR_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define VPR_INTENCLR_TRIGGERED0_Msk (0x1UL << VPR_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define VPR_INTENCLR_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define VPR_INTENCLR_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define VPR_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ + #define VPR_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define VPR_INTENCLR_TRIGGERED1_Msk (0x1UL << VPR_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define VPR_INTENCLR_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define VPR_INTENCLR_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define VPR_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ + #define VPR_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define VPR_INTENCLR_TRIGGERED2_Msk (0x1UL << VPR_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define VPR_INTENCLR_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define VPR_INTENCLR_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define VPR_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ + #define VPR_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define VPR_INTENCLR_TRIGGERED3_Msk (0x1UL << VPR_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define VPR_INTENCLR_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define VPR_INTENCLR_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define VPR_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ + #define VPR_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define VPR_INTENCLR_TRIGGERED4_Msk (0x1UL << VPR_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define VPR_INTENCLR_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define VPR_INTENCLR_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define VPR_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ + #define VPR_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define VPR_INTENCLR_TRIGGERED5_Msk (0x1UL << VPR_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define VPR_INTENCLR_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define VPR_INTENCLR_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define VPR_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ + #define VPR_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define VPR_INTENCLR_TRIGGERED6_Msk (0x1UL << VPR_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define VPR_INTENCLR_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define VPR_INTENCLR_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define VPR_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ + #define VPR_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define VPR_INTENCLR_TRIGGERED7_Msk (0x1UL << VPR_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define VPR_INTENCLR_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define VPR_INTENCLR_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define VPR_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ + #define VPR_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define VPR_INTENCLR_TRIGGERED8_Msk (0x1UL << VPR_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define VPR_INTENCLR_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define VPR_INTENCLR_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define VPR_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ + #define VPR_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define VPR_INTENCLR_TRIGGERED9_Msk (0x1UL << VPR_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define VPR_INTENCLR_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define VPR_INTENCLR_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define VPR_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ + #define VPR_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define VPR_INTENCLR_TRIGGERED10_Msk (0x1UL << VPR_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define VPR_INTENCLR_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define VPR_INTENCLR_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define VPR_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ + #define VPR_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define VPR_INTENCLR_TRIGGERED11_Msk (0x1UL << VPR_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define VPR_INTENCLR_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define VPR_INTENCLR_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define VPR_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ + #define VPR_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define VPR_INTENCLR_TRIGGERED12_Msk (0x1UL << VPR_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define VPR_INTENCLR_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define VPR_INTENCLR_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define VPR_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ + #define VPR_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define VPR_INTENCLR_TRIGGERED13_Msk (0x1UL << VPR_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define VPR_INTENCLR_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define VPR_INTENCLR_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define VPR_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ + #define VPR_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define VPR_INTENCLR_TRIGGERED14_Msk (0x1UL << VPR_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define VPR_INTENCLR_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define VPR_INTENCLR_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define VPR_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ + #define VPR_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define VPR_INTENCLR_TRIGGERED15_Msk (0x1UL << VPR_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define VPR_INTENCLR_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define VPR_INTENCLR_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define VPR_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */ + #define VPR_INTENCLR_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTENCLR_TRIGGERED16_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */ + #define VPR_INTENCLR_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Msk (0x1UL << VPR_INTENCLR_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTENCLR_TRIGGERED17_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */ + #define VPR_INTENCLR_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Msk (0x1UL << VPR_INTENCLR_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTENCLR_TRIGGERED18_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */ + #define VPR_INTENCLR_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Msk (0x1UL << VPR_INTENCLR_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTENCLR_TRIGGERED19_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */ + #define VPR_INTENCLR_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Msk (0x1UL << VPR_INTENCLR_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTENCLR_TRIGGERED20_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */ + #define VPR_INTENCLR_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Msk (0x1UL << VPR_INTENCLR_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTENCLR_TRIGGERED21_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */ + #define VPR_INTENCLR_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Msk (0x1UL << VPR_INTENCLR_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTENCLR_TRIGGERED22_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */ + #define VPR_INTENCLR_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define VPR_INTENCLR_TRIGGERED23_Msk (0x1UL << VPR_INTENCLR_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define VPR_INTENCLR_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define VPR_INTENCLR_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define VPR_INTENCLR_TRIGGERED23_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */ + #define VPR_INTENCLR_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define VPR_INTENCLR_TRIGGERED24_Msk (0x1UL << VPR_INTENCLR_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define VPR_INTENCLR_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define VPR_INTENCLR_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define VPR_INTENCLR_TRIGGERED24_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */ + #define VPR_INTENCLR_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define VPR_INTENCLR_TRIGGERED25_Msk (0x1UL << VPR_INTENCLR_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define VPR_INTENCLR_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define VPR_INTENCLR_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define VPR_INTENCLR_TRIGGERED25_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */ + #define VPR_INTENCLR_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define VPR_INTENCLR_TRIGGERED26_Msk (0x1UL << VPR_INTENCLR_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define VPR_INTENCLR_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define VPR_INTENCLR_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define VPR_INTENCLR_TRIGGERED26_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */ + #define VPR_INTENCLR_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define VPR_INTENCLR_TRIGGERED27_Msk (0x1UL << VPR_INTENCLR_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define VPR_INTENCLR_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define VPR_INTENCLR_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define VPR_INTENCLR_TRIGGERED27_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */ + #define VPR_INTENCLR_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define VPR_INTENCLR_TRIGGERED28_Msk (0x1UL << VPR_INTENCLR_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define VPR_INTENCLR_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define VPR_INTENCLR_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define VPR_INTENCLR_TRIGGERED28_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */ + #define VPR_INTENCLR_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define VPR_INTENCLR_TRIGGERED29_Msk (0x1UL << VPR_INTENCLR_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define VPR_INTENCLR_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define VPR_INTENCLR_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define VPR_INTENCLR_TRIGGERED29_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */ + #define VPR_INTENCLR_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define VPR_INTENCLR_TRIGGERED30_Msk (0x1UL << VPR_INTENCLR_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define VPR_INTENCLR_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define VPR_INTENCLR_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define VPR_INTENCLR_TRIGGERED30_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled */ + +/* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */ + #define VPR_INTENCLR_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define VPR_INTENCLR_TRIGGERED31_Msk (0x1UL << VPR_INTENCLR_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define VPR_INTENCLR_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define VPR_INTENCLR_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define VPR_INTENCLR_TRIGGERED31_Clear (0x1UL) /*!< Disable */ + #define VPR_INTENCLR_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled */ + #define VPR_INTENCLR_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* VPR_INTPEND: Pending interrupts */ + #define VPR_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register. */ + +/* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */ + #define VPR_INTPEND_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ + #define VPR_INTPEND_TRIGGERED0_Msk (0x1UL << VPR_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ + #define VPR_INTPEND_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field. */ + #define VPR_INTPEND_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field. */ + #define VPR_INTPEND_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */ + #define VPR_INTPEND_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ + #define VPR_INTPEND_TRIGGERED1_Msk (0x1UL << VPR_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ + #define VPR_INTPEND_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field. */ + #define VPR_INTPEND_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field. */ + #define VPR_INTPEND_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */ + #define VPR_INTPEND_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ + #define VPR_INTPEND_TRIGGERED2_Msk (0x1UL << VPR_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ + #define VPR_INTPEND_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field. */ + #define VPR_INTPEND_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field. */ + #define VPR_INTPEND_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */ + #define VPR_INTPEND_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ + #define VPR_INTPEND_TRIGGERED3_Msk (0x1UL << VPR_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ + #define VPR_INTPEND_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field. */ + #define VPR_INTPEND_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field. */ + #define VPR_INTPEND_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */ + #define VPR_INTPEND_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ + #define VPR_INTPEND_TRIGGERED4_Msk (0x1UL << VPR_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ + #define VPR_INTPEND_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field. */ + #define VPR_INTPEND_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field. */ + #define VPR_INTPEND_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */ + #define VPR_INTPEND_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ + #define VPR_INTPEND_TRIGGERED5_Msk (0x1UL << VPR_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ + #define VPR_INTPEND_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field. */ + #define VPR_INTPEND_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field. */ + #define VPR_INTPEND_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */ + #define VPR_INTPEND_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ + #define VPR_INTPEND_TRIGGERED6_Msk (0x1UL << VPR_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ + #define VPR_INTPEND_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field. */ + #define VPR_INTPEND_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field. */ + #define VPR_INTPEND_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */ + #define VPR_INTPEND_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ + #define VPR_INTPEND_TRIGGERED7_Msk (0x1UL << VPR_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ + #define VPR_INTPEND_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field. */ + #define VPR_INTPEND_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field. */ + #define VPR_INTPEND_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */ + #define VPR_INTPEND_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ + #define VPR_INTPEND_TRIGGERED8_Msk (0x1UL << VPR_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ + #define VPR_INTPEND_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field. */ + #define VPR_INTPEND_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field. */ + #define VPR_INTPEND_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */ + #define VPR_INTPEND_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ + #define VPR_INTPEND_TRIGGERED9_Msk (0x1UL << VPR_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ + #define VPR_INTPEND_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field. */ + #define VPR_INTPEND_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field. */ + #define VPR_INTPEND_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */ + #define VPR_INTPEND_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ + #define VPR_INTPEND_TRIGGERED10_Msk (0x1UL << VPR_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ + #define VPR_INTPEND_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field. */ + #define VPR_INTPEND_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field. */ + #define VPR_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */ + #define VPR_INTPEND_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ + #define VPR_INTPEND_TRIGGERED11_Msk (0x1UL << VPR_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ + #define VPR_INTPEND_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field. */ + #define VPR_INTPEND_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field. */ + #define VPR_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */ + #define VPR_INTPEND_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ + #define VPR_INTPEND_TRIGGERED12_Msk (0x1UL << VPR_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ + #define VPR_INTPEND_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field. */ + #define VPR_INTPEND_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field. */ + #define VPR_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */ + #define VPR_INTPEND_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ + #define VPR_INTPEND_TRIGGERED13_Msk (0x1UL << VPR_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ + #define VPR_INTPEND_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field. */ + #define VPR_INTPEND_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field. */ + #define VPR_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */ + #define VPR_INTPEND_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ + #define VPR_INTPEND_TRIGGERED14_Msk (0x1UL << VPR_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ + #define VPR_INTPEND_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field. */ + #define VPR_INTPEND_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field. */ + #define VPR_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */ + #define VPR_INTPEND_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ + #define VPR_INTPEND_TRIGGERED15_Msk (0x1UL << VPR_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ + #define VPR_INTPEND_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field. */ + #define VPR_INTPEND_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field. */ + #define VPR_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */ + #define VPR_INTPEND_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field. */ + #define VPR_INTPEND_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */ + #define VPR_INTPEND_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Msk (0x1UL << VPR_INTPEND_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field. */ + #define VPR_INTPEND_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */ + #define VPR_INTPEND_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Msk (0x1UL << VPR_INTPEND_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field. */ + #define VPR_INTPEND_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */ + #define VPR_INTPEND_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Msk (0x1UL << VPR_INTPEND_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field. */ + #define VPR_INTPEND_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */ + #define VPR_INTPEND_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Msk (0x1UL << VPR_INTPEND_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field. */ + #define VPR_INTPEND_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */ + #define VPR_INTPEND_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Msk (0x1UL << VPR_INTPEND_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field. */ + #define VPR_INTPEND_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */ + #define VPR_INTPEND_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Msk (0x1UL << VPR_INTPEND_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field. */ + #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */ + #define VPR_INTPEND_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field. */ + #define VPR_INTPEND_TRIGGERED23_Msk (0x1UL << VPR_INTPEND_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */ + #define VPR_INTPEND_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field. */ + #define VPR_INTPEND_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field. */ + #define VPR_INTPEND_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */ + #define VPR_INTPEND_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field. */ + #define VPR_INTPEND_TRIGGERED24_Msk (0x1UL << VPR_INTPEND_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */ + #define VPR_INTPEND_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field. */ + #define VPR_INTPEND_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field. */ + #define VPR_INTPEND_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */ + #define VPR_INTPEND_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field. */ + #define VPR_INTPEND_TRIGGERED25_Msk (0x1UL << VPR_INTPEND_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */ + #define VPR_INTPEND_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field. */ + #define VPR_INTPEND_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field. */ + #define VPR_INTPEND_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */ + #define VPR_INTPEND_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field. */ + #define VPR_INTPEND_TRIGGERED26_Msk (0x1UL << VPR_INTPEND_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */ + #define VPR_INTPEND_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field. */ + #define VPR_INTPEND_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field. */ + #define VPR_INTPEND_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */ + #define VPR_INTPEND_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field. */ + #define VPR_INTPEND_TRIGGERED27_Msk (0x1UL << VPR_INTPEND_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */ + #define VPR_INTPEND_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field. */ + #define VPR_INTPEND_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field. */ + #define VPR_INTPEND_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */ + #define VPR_INTPEND_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field. */ + #define VPR_INTPEND_TRIGGERED28_Msk (0x1UL << VPR_INTPEND_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */ + #define VPR_INTPEND_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field. */ + #define VPR_INTPEND_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field. */ + #define VPR_INTPEND_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */ + #define VPR_INTPEND_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field. */ + #define VPR_INTPEND_TRIGGERED29_Msk (0x1UL << VPR_INTPEND_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */ + #define VPR_INTPEND_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field. */ + #define VPR_INTPEND_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field. */ + #define VPR_INTPEND_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */ + #define VPR_INTPEND_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field. */ + #define VPR_INTPEND_TRIGGERED30_Msk (0x1UL << VPR_INTPEND_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */ + #define VPR_INTPEND_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field. */ + #define VPR_INTPEND_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field. */ + #define VPR_INTPEND_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending */ + +/* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */ + #define VPR_INTPEND_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field. */ + #define VPR_INTPEND_TRIGGERED31_Msk (0x1UL << VPR_INTPEND_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */ + #define VPR_INTPEND_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field. */ + #define VPR_INTPEND_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field. */ + #define VPR_INTPEND_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending */ + #define VPR_INTPEND_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending */ + + +/* VPR_CPURUN: State of the CPU after a core reset */ + #define VPR_CPURUN_ResetValue (0x00000000UL) /*!< Reset value of CPURUN register. */ + +/* EN @Bit 0 : Controls CPU running state after a core reset. */ + #define VPR_CPURUN_EN_Pos (0UL) /*!< Position of EN field. */ + #define VPR_CPURUN_EN_Msk (0x1UL << VPR_CPURUN_EN_Pos) /*!< Bit mask of EN field. */ + #define VPR_CPURUN_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define VPR_CPURUN_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define VPR_CPURUN_EN_Stopped (0x0UL) /*!< CPU stopped. If this is the CPU state after a core reset, setting this + bit will change the CPU state to CPU running.*/ + #define VPR_CPURUN_EN_Running (0x1UL) /*!< CPU running. If this is the CPU state after a core reset, clearing + this bit will change the CPU state to CPU stopped after a core reset.*/ + + +/* VPR_INITPC: Initial value of the PC at CPU start. */ + #define VPR_INITPC_ResetValue (0x00000000UL) /*!< Reset value of INITPC register. */ + +/* INITPC @Bits 0..31 : Initial value of the PC at CPU start. */ + #define VPR_INITPC_INITPC_Pos (0UL) /*!< Position of INITPC field. */ + #define VPR_INITPC_INITPC_Msk (0xFFFFFFFFUL << VPR_INITPC_INITPC_Pos) /*!< Bit mask of INITPC field. */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VPRCSR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief VPR CSR registers + */ +/** + * @brief [VPRCSR] (unspecified) + */ + +/** + * @brief [VPRCSR] (unspecified) + */ + +/** + * @brief MSTATUS [VPRCSR_MSTATUS] Machine Status + */ + #define VPRCSR_MSTATUS (0x00000300ul) + #define VPRCSR_MSTATUS_ResetValue (0x00001800UL) /*!< Reset value of MSTATUS register. */ + +/* MIE @Bit 3 : global interrupt enable for machine privilege mode */ + #define VPRCSR_MSTATUS_MIE_Pos (3UL) /*!< Position of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Msk (0x1UL << VPRCSR_MSTATUS_MIE_Pos) /*!< Bit mask of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Min (0x0UL) /*!< Min enumerator value of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Max (0x1UL) /*!< Max enumerator value of MIE field. */ + #define VPRCSR_MSTATUS_MIE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MSTATUS_MIE_Enabled (0x1UL) /*!< (unspecified) */ + +/* MPIE @Bit 7 : Exists to support nested traps. Value of the interrupt-enable bit active prior to the trap for machine + privilege mode */ + + #define VPRCSR_MSTATUS_MPIE_Pos (7UL) /*!< Position of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Msk (0x1UL << VPRCSR_MSTATUS_MPIE_Pos) /*!< Bit mask of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Min (0x0UL) /*!< Min enumerator value of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Max (0x1UL) /*!< Max enumerator value of MPIE field. */ + #define VPRCSR_MSTATUS_MPIE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MSTATUS_MPIE_Enabled (0x1UL) /*!< (unspecified) */ + +/* MPP @Bits 11..12 : Exists to support nested traps. Value of the privlege mode prior to the trap for machine privilege mode */ + #define VPRCSR_MSTATUS_MPP_Pos (11UL) /*!< Position of MPP field. */ + #define VPRCSR_MSTATUS_MPP_Msk (0x3UL << VPRCSR_MSTATUS_MPP_Pos) /*!< Bit mask of MPP field. */ + + +/** + * @brief MISA [VPRCSR_MISA] Machine ISA + */ + #define VPRCSR_MISA (0x00000301ul) + #define VPRCSR_MISA_ResetValue (0x40001014UL) /*!< Reset value of MISA register. */ + +/* A @Bit 0 : Atomic extension */ + #define VPRCSR_MISA_A_Pos (0UL) /*!< Position of A field. */ + #define VPRCSR_MISA_A_Msk (0x1UL << VPRCSR_MISA_A_Pos) /*!< Bit mask of A field. */ + #define VPRCSR_MISA_A_Min (0x0UL) /*!< Min enumerator value of A field. */ + #define VPRCSR_MISA_A_Max (0x1UL) /*!< Max enumerator value of A field. */ + #define VPRCSR_MISA_A_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_A_Enabled (0x1UL) /*!< (unspecified) */ + +/* B @Bit 1 : Bit-Manipulation extension */ + #define VPRCSR_MISA_B_Pos (1UL) /*!< Position of B field. */ + #define VPRCSR_MISA_B_Msk (0x1UL << VPRCSR_MISA_B_Pos) /*!< Bit mask of B field. */ + #define VPRCSR_MISA_B_Min (0x0UL) /*!< Min enumerator value of B field. */ + #define VPRCSR_MISA_B_Max (0x1UL) /*!< Max enumerator value of B field. */ + #define VPRCSR_MISA_B_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_B_Enabled (0x1UL) /*!< (unspecified) */ + +/* C @Bit 2 : Compressed extension */ + #define VPRCSR_MISA_C_Pos (2UL) /*!< Position of C field. */ + #define VPRCSR_MISA_C_Msk (0x1UL << VPRCSR_MISA_C_Pos) /*!< Bit mask of C field. */ + #define VPRCSR_MISA_C_Min (0x0UL) /*!< Min enumerator value of C field. */ + #define VPRCSR_MISA_C_Max (0x1UL) /*!< Max enumerator value of C field. */ + #define VPRCSR_MISA_C_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_C_Enabled (0x1UL) /*!< (unspecified) */ + +/* E @Bit 4 : RV32E base ISA */ + #define VPRCSR_MISA_E_Pos (4UL) /*!< Position of E field. */ + #define VPRCSR_MISA_E_Msk (0x1UL << VPRCSR_MISA_E_Pos) /*!< Bit mask of E field. */ + #define VPRCSR_MISA_E_Min (0x0UL) /*!< Min enumerator value of E field. */ + #define VPRCSR_MISA_E_Max (0x1UL) /*!< Max enumerator value of E field. */ + #define VPRCSR_MISA_E_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_E_Enabled (0x1UL) /*!< (unspecified) */ + +/* I @Bit 8 : RV32I/64I/128I base ISA */ + #define VPRCSR_MISA_I_Pos (8UL) /*!< Position of I field. */ + #define VPRCSR_MISA_I_Msk (0x1UL << VPRCSR_MISA_I_Pos) /*!< Bit mask of I field. */ + #define VPRCSR_MISA_I_Min (0x0UL) /*!< Min enumerator value of I field. */ + #define VPRCSR_MISA_I_Max (0x1UL) /*!< Max enumerator value of I field. */ + #define VPRCSR_MISA_I_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_I_Enabled (0x1UL) /*!< (unspecified) */ + +/* M @Bit 12 : Integer Multiply/Divide extension */ + #define VPRCSR_MISA_M_Pos (12UL) /*!< Position of M field. */ + #define VPRCSR_MISA_M_Msk (0x1UL << VPRCSR_MISA_M_Pos) /*!< Bit mask of M field. */ + #define VPRCSR_MISA_M_Min (0x0UL) /*!< Min enumerator value of M field. */ + #define VPRCSR_MISA_M_Max (0x1UL) /*!< Max enumerator value of M field. */ + #define VPRCSR_MISA_M_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_M_Enabled (0x1UL) /*!< (unspecified) */ + +/* N @Bit 13 : User-level interrupts supported */ + #define VPRCSR_MISA_N_Pos (13UL) /*!< Position of N field. */ + #define VPRCSR_MISA_N_Msk (0x1UL << VPRCSR_MISA_N_Pos) /*!< Bit mask of N field. */ + #define VPRCSR_MISA_N_Min (0x0UL) /*!< Min enumerator value of N field. */ + #define VPRCSR_MISA_N_Max (0x1UL) /*!< Max enumerator value of N field. */ + #define VPRCSR_MISA_N_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MISA_N_Enabled (0x1UL) /*!< (unspecified) */ + +/* MXL @Bits 30..31 : Machine XLEN */ + #define VPRCSR_MISA_MXL_Pos (30UL) /*!< Position of MXL field. */ + #define VPRCSR_MISA_MXL_Msk (0x3UL << VPRCSR_MISA_MXL_Pos) /*!< Bit mask of MXL field. */ + #define VPRCSR_MISA_MXL_Min (0x1UL) /*!< Min enumerator value of MXL field. */ + #define VPRCSR_MISA_MXL_Max (0x3UL) /*!< Max enumerator value of MXL field. */ + #define VPRCSR_MISA_MXL_XLEN32 (0x1UL) /*!< XLEN is 32 bits */ + #define VPRCSR_MISA_MXL_XLEN64 (0x2UL) /*!< XLEN is 64 bits */ + #define VPRCSR_MISA_MXL_XLEN128 (0x3UL) /*!< XLEN is 128 bits */ + + +/** + * @brief MTVEC [VPRCSR_MTVEC] Machine Trap-Vector + */ + #define VPRCSR_MTVEC (0x00000305ul) + #define VPRCSR_MTVEC_ResetValue (0x00000003UL) /*!< Reset value of MTVEC register. */ + +/* MODE @Bits 0..1 : Mode */ + #define VPRCSR_MTVEC_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_MTVEC_MODE_Msk (0x3UL << VPRCSR_MTVEC_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_MTVEC_MODE_Min (0x3UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_MTVEC_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_MTVEC_MODE_CLIC (0x3UL) /*!< Core Local Interrupt Controller (CLIC) interrupt handling mode */ + +/* BASE @Bits 2..31 : Vector base address */ + #define VPRCSR_MTVEC_BASE_Pos (2UL) /*!< Position of BASE field. */ + #define VPRCSR_MTVEC_BASE_Msk (0x3FFFFFFFUL << VPRCSR_MTVEC_BASE_Pos) /*!< Bit mask of BASE field. */ + + +/** + * @brief MTVT [VPRCSR_MTVT] Machine Trap Vector Table + */ + #define VPRCSR_MTVT (0x00000307ul) + #define VPRCSR_MTVT_ResetValue (0x00000000UL) /*!< Reset value of MTVT register. */ + +/* VAL @Bits 6..31 : Machine Trap Vector Table base address value for CLIC vectored interrupts */ + #define VPRCSR_MTVT_VAL_Pos (6UL) /*!< Position of VAL field. */ + #define VPRCSR_MTVT_VAL_Msk (0x3FFFFFFUL << VPRCSR_MTVT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCOUNTINHIBIT [VPRCSR_MCOUNTINHIBIT] Machine Counter-Inhibit + */ + #define VPRCSR_MCOUNTINHIBIT (0x00000320ul) + #define VPRCSR_MCOUNTINHIBIT_ResetValue (0x00000005UL) /*!< Reset value of MCOUNTINHIBIT register. */ + +/* CY @Bit 0 : (unspecified) */ + #define VPRCSR_MCOUNTINHIBIT_CY_Pos (0UL) /*!< Position of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_CY_Pos) /*!< Bit mask of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Min (0x0UL) /*!< Min enumerator value of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_Max (0x1UL) /*!< Max enumerator value of CY field. */ + #define VPRCSR_MCOUNTINHIBIT_CY_INCREMENT (0x0UL) /*!< MCYCLE increments as usual */ + #define VPRCSR_MCOUNTINHIBIT_CY_INHIBIT (0x1UL) /*!< MCYCLE doesn't increment */ + +/* IR @Bit 2 : (unspecified) */ + #define VPRCSR_MCOUNTINHIBIT_IR_Pos (2UL) /*!< Position of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_IR_Pos) /*!< Bit mask of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Min (0x0UL) /*!< Min enumerator value of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_Max (0x1UL) /*!< Max enumerator value of IR field. */ + #define VPRCSR_MCOUNTINHIBIT_IR_INCREMENT (0x0UL) /*!< MINSTRET increments as usual */ + #define VPRCSR_MCOUNTINHIBIT_IR_INHIBIT (0x1UL) /*!< MINSTRET doesn't increment */ + + +/** + * @brief MSCRATCH [VPRCSR_MSCRATCH] Machine Scratch + */ + #define VPRCSR_MSCRATCH (0x00000340ul) + #define VPRCSR_MSCRATCH_ResetValue (0x00000000UL) /*!< Reset value of MSCRATCH register. */ + +/* VAL @Bits 0..31 : Machine Scratch value */ + #define VPRCSR_MSCRATCH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MSCRATCH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MSCRATCH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MEPC [VPRCSR_MEPC] Machine Exception Program Counter + */ + #define VPRCSR_MEPC (0x00000341ul) + #define VPRCSR_MEPC_ResetValue (0x00000000UL) /*!< Reset value of MEPC register. */ + +/* VAL @Bits 0..31 : Machine Exception Program Counter value */ + #define VPRCSR_MEPC_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MEPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MEPC_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCAUSE [VPRCSR_MCAUSE] Machine Cause + */ + #define VPRCSR_MCAUSE (0x00000342ul) + #define VPRCSR_MCAUSE_ResetValue (0x30000000UL) /*!< Reset value of MCAUSE register. */ + +/* EXCEPTIONCODE @Bits 0..11 : Exception code */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Pos (0UL) /*!< Position of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Msk (0xFFFUL << VPRCSR_MCAUSE_EXCEPTIONCODE_Pos) /*!< Bit mask of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Min (0x0UL) /*!< Min enumerator value of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_Max (0x1FUL) /*!< Max enumerator value of EXCEPTIONCODE field. */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTADDRMISALIGN (0x000UL) /*!< Instruction Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTACCESSFAULT (0x001UL) /*!< Instruction Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_ILLEGALINST (0x002UL) /*!< Illegal Instruction */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BKPT (0x003UL) /*!< Breakpoint */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADADDRMISALIGN (0x004UL) /*!< Load Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADACCESSFAULT (0x005UL) /*!< Load Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREADDRMISALIGN (0x006UL) /*!< Store/AMO Address Misaligned */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREACCESSFAULT (0x007UL) /*!< Store/AMO Access Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_ECALLMMODE (0x00BUL) /*!< Environment Call M-Mode */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNSTACKING (0x018UL) /*!< Misaligned Stacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTSTACKING (0x019UL) /*!< Bus Fault on Stacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_INTVECTORFAULT (0x01AUL) /*!< Interrupt Vector Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNUNSTACKING (0x01BUL) /*!< Misaligned Unstacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTUNSTACKING (0x01CUL) /*!< Bus Fault on Unstacking */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADTIMEOUTFAULT (0x01DUL) /*!< Load Timeout Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STORETIMEOUTFAULT (0x01EUL) /*!< Store Timeout Fault */ + #define VPRCSR_MCAUSE_EXCEPTIONCODE_STACKINGEXCFAULT (0x01FUL) /*!< Fault on Exception Stacking */ + +/* MPIL @Bits 16..23 : Previous interrupt level */ + #define VPRCSR_MCAUSE_MPIL_Pos (16UL) /*!< Position of MPIL field. */ + #define VPRCSR_MCAUSE_MPIL_Msk (0xFFUL << VPRCSR_MCAUSE_MPIL_Pos) /*!< Bit mask of MPIL field. */ + +/* MPIE @Bit 27 : Previous interrupt enable, same as MSTATUS.MPIE */ + #define VPRCSR_MCAUSE_MPIE_Pos (27UL) /*!< Position of MPIE field. */ + #define VPRCSR_MCAUSE_MPIE_Msk (0x1UL << VPRCSR_MCAUSE_MPIE_Pos) /*!< Bit mask of MPIE field. */ + +/* MPP @Bits 28..29 : Previous privilege mode, same as MSTATUS.MPP */ + #define VPRCSR_MCAUSE_MPP_Pos (28UL) /*!< Position of MPP field. */ + #define VPRCSR_MCAUSE_MPP_Msk (0x3UL << VPRCSR_MCAUSE_MPP_Pos) /*!< Bit mask of MPP field. */ + +/* MINHV @Bit 30 : In hardware vectoring */ + #define VPRCSR_MCAUSE_MINHV_Pos (30UL) /*!< Position of MINHV field. */ + #define VPRCSR_MCAUSE_MINHV_Msk (0x1UL << VPRCSR_MCAUSE_MINHV_Pos) /*!< Bit mask of MINHV field. */ + +/* INTERRUPT @Bit 31 : Interrupt bit */ + #define VPRCSR_MCAUSE_INTERRUPT_Pos (31UL) /*!< Position of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Msk (0x1UL << VPRCSR_MCAUSE_INTERRUPT_Pos) /*!< Bit mask of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Min (0x0UL) /*!< Min enumerator value of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_Max (0x1UL) /*!< Max enumerator value of INTERRUPT field. */ + #define VPRCSR_MCAUSE_INTERRUPT_EXCEPTION (0x0UL) /*!< (unspecified) */ + #define VPRCSR_MCAUSE_INTERRUPT_INTERRUPT (0x1UL) /*!< (unspecified) */ + + +/** + * @brief MTVAL [VPRCSR_MTVAL] Machine Trap Value + */ + #define VPRCSR_MTVAL (0x00000343ul) + #define VPRCSR_MTVAL_ResetValue (0x00000000UL) /*!< Reset value of MTVAL register. */ + +/* VAL @Bits 0..31 : Machine Trap Value */ + #define VPRCSR_MTVAL_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MTVAL_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MTVAL_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINTSTATUS [VPRCSR_MINTSTATUS] M-mode Interrupt Status + */ + #define VPRCSR_MINTSTATUS (0x00000346ul) + #define VPRCSR_MINTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MINTSTATUS register. */ + +/* MIL @Bits 24..31 : M-Mode interrupt level */ + #define VPRCSR_MINTSTATUS_MIL_Pos (24UL) /*!< Position of MIL field. */ + #define VPRCSR_MINTSTATUS_MIL_Msk (0xFFUL << VPRCSR_MINTSTATUS_MIL_Pos) /*!< Bit mask of MIL field. */ + + +/** + * @brief MINTTHRESH [VPRCSR_MINTTHRESH] M-mode Interrupt-level Threshold + */ + #define VPRCSR_MINTTHRESH (0x00000347ul) + #define VPRCSR_MINTTHRESH_ResetValue (0x00000000UL) /*!< Reset value of MINTTHRESH register. */ + +/* TH @Bits 0..7 : M-Mode Interrupt-level Threshold */ + #define VPRCSR_MINTTHRESH_TH_Pos (0UL) /*!< Position of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Msk (0xFFUL << VPRCSR_MINTTHRESH_TH_Pos) /*!< Bit mask of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Min (0x0UL) /*!< Min enumerator value of TH field. */ + #define VPRCSR_MINTTHRESH_TH_Max (0xFFUL) /*!< Max enumerator value of TH field. */ + #define VPRCSR_MINTTHRESH_TH_DISABLED (0x00UL) /*!< Threshold disabled */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL0 (0x3FUL) /*!< Threshold level 0 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL1 (0x7FUL) /*!< Threshold level 1 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL2 (0xBFUL) /*!< Threshold level 2 */ + #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL3 (0xFFUL) /*!< Threshold level 3 */ + + +/** + * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base + */ + #define VPRCSR_MCLICBASE (0x00000350ul) + #define VPRCSR_MCLICBASE_ResetValue (0x00001000UL) /*!< Reset value of MCLICBASE register. */ + +/* VAL @Bits 0..31 : CLIC base address value */ + #define VPRCSR_MCLICBASE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCLICBASE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCLICBASE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TSELECT [VPRCSR_TSELECT] Trigger Select + */ + #define VPRCSR_TSELECT (0x000007A0ul) + #define VPRCSR_TSELECT_ResetValue (0x00000000UL) /*!< Reset value of TSELECT register. */ + +/* VAL @Bits 0..31 : Trigger Select value */ + #define VPRCSR_TSELECT_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_TSELECT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_TSELECT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TDATA1 [VPRCSR_TDATA1] Trigger Data 1 + */ + #define VPRCSR_TDATA1 (0x000007A1ul) + #define VPRCSR_TDATA1_ResetValue (0x00000000UL) /*!< Reset value of TDATA1 register. */ + +/* DATA @Bits 0..26 : Trigger Specific Data */ + #define VPRCSR_TDATA1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA1_DATA_Msk (0x7FFFFFFUL << VPRCSR_TDATA1_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* DMODE @Bit 27 : Debug Mode */ + #define VPRCSR_TDATA1_DMODE_Pos (27UL) /*!< Position of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Msk (0x1UL << VPRCSR_TDATA1_DMODE_Pos) /*!< Bit mask of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Min (0x0UL) /*!< Min enumerator value of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_Max (0x1UL) /*!< Max enumerator value of DMODE field. */ + #define VPRCSR_TDATA1_DMODE_BOTH (0x0UL) /*!< Both Debug and M-mode can write the tdata registers at the selected + tselect.*/ + #define VPRCSR_TDATA1_DMODE_ONLYDEBUG (0x1UL) /*!< Only Debug Mode can write the tdata registers at the selected tselect. + Writes from other modes are ignored.*/ + +/* TYPE @Bits 28..31 : Type */ + #define VPRCSR_TDATA1_TYPE_Pos (28UL) /*!< Position of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Msk (0xFUL << VPRCSR_TDATA1_TYPE_Pos) /*!< Bit mask of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Min (0x0UL) /*!< Min enumerator value of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_Max (0xFUL) /*!< Max enumerator value of TYPE field. */ + #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL) /*!< There is no trigger at this tselect */ + #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL) /*!< The trigger is an address match trigger. The remaining bits in this + register act as described in mcontrol*/ + #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL) /*!< This trigger is a remapping trigger. The remaining bits in this + register behave as described in remapping functionality*/ + + +/** + * @brief TDATA2 [VPRCSR_TDATA2] Trigger Data 2 + */ + #define VPRCSR_TDATA2 (0x000007A2ul) + #define VPRCSR_TDATA2_ResetValue (0x00000000UL) /*!< Reset value of TDATA2 register. */ + +/* DATA @Bits 0..31 : Trigger Specific Data */ + #define VPRCSR_TDATA2_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA2_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA2_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/** + * @brief TDATA3 [VPRCSR_TDATA3] Trigger Data 3 + */ + #define VPRCSR_TDATA3 (0x000007A3ul) + #define VPRCSR_TDATA3_ResetValue (0x00000000UL) /*!< Reset value of TDATA3 register. */ + +/* DATA @Bits 0..31 : Trigger Specific Data */ + #define VPRCSR_TDATA3_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_TDATA3_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA3_DATA_Pos) /*!< Bit mask of DATA field. */ + + +/** + * @brief TINFO [VPRCSR_TINFO] Trigger Info + */ + #define VPRCSR_TINFO (0x000007A4ul) + #define VPRCSR_TINFO_ResetValue (0x00000000UL) /*!< Reset value of TINFO register. */ + +/* INFO @Bits 0..15 : Trigger Info value */ + #define VPRCSR_TINFO_INFO_Pos (0UL) /*!< Position of INFO field. */ + #define VPRCSR_TINFO_INFO_Msk (0xFFFFUL << VPRCSR_TINFO_INFO_Pos) /*!< Bit mask of INFO field. */ + + +/** + * @brief TCONTROL [VPRCSR_TCONTROL] Trigger Control + */ + #define VPRCSR_TCONTROL (0x000007A5ul) + #define VPRCSR_TCONTROL_ResetValue (0x00000000UL) /*!< Reset value of TCONTROL register. */ + +/* MTE @Bit 3 : Mode Trigger Enable */ + #define VPRCSR_TCONTROL_MTE_Pos (3UL) /*!< Position of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Msk (0x1UL << VPRCSR_TCONTROL_MTE_Pos) /*!< Bit mask of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Min (0x0UL) /*!< Min enumerator value of MTE field. */ + #define VPRCSR_TCONTROL_MTE_Max (0x1UL) /*!< Max enumerator value of MTE field. */ + #define VPRCSR_TCONTROL_MTE_DONTMATCH (0x0UL) /*!< Triggers with action=0 do not match/fire while the hart is in M-mode */ + #define VPRCSR_TCONTROL_MTE_MATCH (0x1UL) /*!< Triggers do match/fire while the hart is in M-mode. When a trap into + M-mode is taken, mte is set to 0. When mret is executed, mte is set to + the value of mpte*/ + +/* MPTE @Bit 7 : Mode Previous Trigger Enable */ + #define VPRCSR_TCONTROL_MPTE_Pos (7UL) /*!< Position of MPTE field. */ + #define VPRCSR_TCONTROL_MPTE_Msk (0x1UL << VPRCSR_TCONTROL_MPTE_Pos) /*!< Bit mask of MPTE field. */ + + +/** + * @brief DCSR [VPRCSR_DCSR] Debug Control and Status + */ + #define VPRCSR_DCSR (0x000007B0ul) + #define VPRCSR_DCSR_ResetValue (0x40000003UL) /*!< Reset value of DCSR register. */ + +/* PRV @Bits 0..1 : Privilege level */ + #define VPRCSR_DCSR_PRV_Pos (0UL) /*!< Position of PRV field. */ + #define VPRCSR_DCSR_PRV_Msk (0x3UL << VPRCSR_DCSR_PRV_Pos) /*!< Bit mask of PRV field. */ + #define VPRCSR_DCSR_PRV_Min (0x3UL) /*!< Min enumerator value of PRV field. */ + #define VPRCSR_DCSR_PRV_Max (0x3UL) /*!< Max enumerator value of PRV field. */ + #define VPRCSR_DCSR_PRV_MACHINE (0x3UL) /*!< (unspecified) */ + +/* STEP @Bit 2 : Step */ + #define VPRCSR_DCSR_STEP_Pos (2UL) /*!< Position of STEP field. */ + #define VPRCSR_DCSR_STEP_Msk (0x1UL << VPRCSR_DCSR_STEP_Pos) /*!< Bit mask of STEP field. */ + +/* CAUSE @Bits 6..8 : Debug Mode enter cause */ + #define VPRCSR_DCSR_CAUSE_Pos (6UL) /*!< Position of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Msk (0x7UL << VPRCSR_DCSR_CAUSE_Pos) /*!< Bit mask of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Min (0x1UL) /*!< Min enumerator value of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_Max (0x5UL) /*!< Max enumerator value of CAUSE field. */ + #define VPRCSR_DCSR_CAUSE_EBREAK (0x1UL) /*!< An ebreak instruction was executed. (priority 3) */ + #define VPRCSR_DCSR_CAUSE_TRIGGER (0x2UL) /*!< The Trigger Module caused a breakpoint exception. (priority 4, + highest)*/ + #define VPRCSR_DCSR_CAUSE_HALTREQ (0x3UL) /*!< The debugger requested entry to Debug Mode using haltreq. (priority + 1)*/ + #define VPRCSR_DCSR_CAUSE_STEP (0x4UL) /*!< The hart single stepped because step was set. (priority 0, lowest) */ + #define VPRCSR_DCSR_CAUSE_RESETHALTREQ (0x5UL) /*!< The hart halted directly out of reset due to resethaltreq. It is also + acceptable to report 3 when this happens. (priority 2)*/ + +/* STEPIE @Bit 11 : Step Interrupt Enable */ + #define VPRCSR_DCSR_STEPIE_Pos (11UL) /*!< Position of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Msk (0x1UL << VPRCSR_DCSR_STEPIE_Pos) /*!< Bit mask of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Min (0x0UL) /*!< Min enumerator value of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Max (0x1UL) /*!< Max enumerator value of STEPIE field. */ + #define VPRCSR_DCSR_STEPIE_Disabled (0x0UL) /*!< Interrupts are disabled during single stepping */ + #define VPRCSR_DCSR_STEPIE_Enabled (0x1UL) /*!< Interrupts are enabled during single stepping. Implementations may + hard wire this bit to 0. In that case interrupt behavior can be + emulated by the debugger.*/ + +/* EBREAKM @Bit 15 : M-mode ebreak */ + #define VPRCSR_DCSR_EBREAKM_Pos (15UL) /*!< Position of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Msk (0x1UL << VPRCSR_DCSR_EBREAKM_Pos) /*!< Bit mask of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Min (0x0UL) /*!< Min enumerator value of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_Max (0x1UL) /*!< Max enumerator value of EBREAKM field. */ + #define VPRCSR_DCSR_EBREAKM_SPEC (0x0UL) /*!< ebreak instructions in M-mode behave as described in the Privileged + Spe*/ + #define VPRCSR_DCSR_EBREAKM_ENTERDBG (0x1UL) /*!< ebreak instructions in M-mode enter Debug Mode */ + +/* XDEBUGVER @Bits 28..31 : External Debug version */ + #define VPRCSR_DCSR_XDEBUGVER_Pos (28UL) /*!< Position of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Msk (0xFUL << VPRCSR_DCSR_XDEBUGVER_Pos) /*!< Bit mask of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Min (0x4UL) /*!< Min enumerator value of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_Max (0x4UL) /*!< Max enumerator value of XDEBUGVER field. */ + #define VPRCSR_DCSR_XDEBUGVER_STDDBG (0x4UL) /*!< External debug support exists as it is described in this document */ + + +/** + * @brief DPC [VPRCSR_DPC] Debug PC + */ + #define VPRCSR_DPC (0x000007B1ul) + #define VPRCSR_DPC_ResetValue (0x00000000UL) /*!< Reset value of DPC register. */ + +/* VAL @Bits 0..31 : Debug PC value */ + #define VPRCSR_DPC_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_DPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_DPC_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCYCLE [VPRCSR_MCYCLE] Machine Cycle Counter + */ + #define VPRCSR_MCYCLE (0x00000B00ul) + #define VPRCSR_MCYCLE_ResetValue (0x00000000UL) /*!< Reset value of MCYCLE register. */ + +/* VAL @Bits 0..31 : Machine Cycle Counter value */ + #define VPRCSR_MCYCLE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINSTRET [VPRCSR_MINSTRET] Machine Instruction Counter + */ + #define VPRCSR_MINSTRET (0x00000B02ul) + #define VPRCSR_MINSTRET_ResetValue (0x00000000UL) /*!< Reset value of MINSTRET register. */ + +/* VAL @Bits 0..31 : Machine Instruction Counter value */ + #define VPRCSR_MINSTRET_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRET_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MCYCLEH [VPRCSR_MCYCLEH] Machine Cycle Counter (Upper part) + */ + #define VPRCSR_MCYCLEH (0x00000B80ul) + #define VPRCSR_MCYCLEH_ResetValue (0x00000000UL) /*!< Reset value of MCYCLEH register. */ + +/* VAL @Bits 0..31 : Machine Cycle Counter value */ + #define VPRCSR_MCYCLEH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLEH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MINSTRETH [VPRCSR_MINSTRETH] Machine Instruction Counter (Upper part) + */ + #define VPRCSR_MINSTRETH (0x00000B82ul) + #define VPRCSR_MINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of MINSTRETH register. */ + +/* VAL @Bits 0..31 : Machine Instruction Counter (Upper part) value */ + #define VPRCSR_MINSTRETH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_MINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRETH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UCYCLE [VPRCSR_UCYCLE] User Cycle Counter + */ + #define VPRCSR_UCYCLE (0x00000C00ul) + #define VPRCSR_UCYCLE_ResetValue (0x00000000UL) /*!< Reset value of UCYCLE register. */ + +/* VAL @Bits 0..31 : User Cycle Counter value */ + #define VPRCSR_UCYCLE_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLE_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UINSTRET [VPRCSR_UINSTRET] User Instruction Counter + */ + #define VPRCSR_UINSTRET (0x00000C02ul) + #define VPRCSR_UINSTRET_ResetValue (0x00000000UL) /*!< Reset value of UINSTRET register. */ + +/* VAL @Bits 0..31 : User Instruction Counter value */ + #define VPRCSR_UINSTRET_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRET_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UCYCLEH [VPRCSR_UCYCLEH] User Cycle Counter (Upper part) + */ + #define VPRCSR_UCYCLEH (0x00000C80ul) + #define VPRCSR_UCYCLEH_ResetValue (0x00000000UL) /*!< Reset value of UCYCLEH register. */ + +/* VAL @Bits 0..31 : User Cycle Counter value */ + #define VPRCSR_UCYCLEH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLEH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief UINSTRETH [VPRCSR_UINSTRETH] User Instruction Counter (Upper part) + */ + #define VPRCSR_UINSTRETH (0x00000C82ul) + #define VPRCSR_UINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of UINSTRETH register. */ + +/* VAL @Bits 0..31 : User Instruction Counter (Upper part) value */ + #define VPRCSR_UINSTRETH_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_UINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRETH_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief MVENDORID [VPRCSR_MVENDORID] Machine Vendor ID + */ + #define VPRCSR_MVENDORID (0x00000F11ul) + #define VPRCSR_MVENDORID_ResetValue (0x00000144UL) /*!< Reset value of MVENDORID register. */ + +/* OFFSET @Bits 0..6 : MVENDORID encodes the final byte in the Offset field, discarding the parity bit */ + #define VPRCSR_MVENDORID_OFFSET_Pos (0UL) /*!< Position of OFFSET field. */ + #define VPRCSR_MVENDORID_OFFSET_Msk (0x7FUL << VPRCSR_MVENDORID_OFFSET_Pos) /*!< Bit mask of OFFSET field. */ + +/* BANK @Bits 7..31 : MVENDORID encodes the number of one-byte continuation codes in the Bank field */ + #define VPRCSR_MVENDORID_BANK_Pos (7UL) /*!< Position of BANK field. */ + #define VPRCSR_MVENDORID_BANK_Msk (0x1FFFFFFUL << VPRCSR_MVENDORID_BANK_Pos) /*!< Bit mask of BANK field. */ + + +/** + * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID + */ + #define VPRCSR_MARCHID (0x00000F12ul) + #define VPRCSR_MARCHID_ResetValue (0x800000AEUL) /*!< Reset value of MARCHID register. */ + +/* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */ + #define VPRCSR_MARCHID_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ + #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ + +/* HIBERNATE @Bit 2 : Indicates the HIBERNATE parameter option */ + #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL) /*!< Position of HIBERNATE field. */ + #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field. */ + +/* DBG @Bit 3 : Indicates the DBG parameter option */ + #define VPRCSR_MARCHID_DBG_Pos (3UL) /*!< Position of DBG field. */ + #define VPRCSR_MARCHID_DBG_Msk (0x1UL << VPRCSR_MARCHID_DBG_Pos) /*!< Bit mask of DBG field. */ + +/* REMAP @Bit 4 : Indicates the REMAP parameter option */ + #define VPRCSR_MARCHID_REMAP_Pos (4UL) /*!< Position of REMAP field. */ + #define VPRCSR_MARCHID_REMAP_Msk (0x1UL << VPRCSR_MARCHID_REMAP_Pos) /*!< Bit mask of REMAP field. */ + +/* BUSWIDTH @Bit 5 : Indicates the BUS_WIDTH parameter option */ + #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL) /*!< Position of BUSWIDTH field. */ + #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field. */ + +/* BKPT @Bits 6..9 : Indicates the BKPT parameter option */ + #define VPRCSR_MARCHID_BKPT_Pos (6UL) /*!< Position of BKPT field. */ + #define VPRCSR_MARCHID_BKPT_Msk (0xFUL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* IMPLEM @Bit 31 : Indicates a non-open implementation */ + #define VPRCSR_MARCHID_IMPLEM_Pos (31UL) /*!< Position of IMPLEM field. */ + #define VPRCSR_MARCHID_IMPLEM_Msk (0x1UL << VPRCSR_MARCHID_IMPLEM_Pos) /*!< Bit mask of IMPLEM field. */ + + +/** + * @brief MIMPID [VPRCSR_MIMPID] Machine Implementation ID + */ + #define VPRCSR_MIMPID (0x00000F13ul) + #define VPRCSR_MIMPID_ResetValue (0x00010300UL) /*!< Reset value of MIMPID register. */ + +/* PATCHREV @Bits 0..7 : Indicates the number of the patch revision */ + #define VPRCSR_MIMPID_PATCHREV_Pos (0UL) /*!< Position of PATCHREV field. */ + #define VPRCSR_MIMPID_PATCHREV_Msk (0xFFUL << VPRCSR_MIMPID_PATCHREV_Pos) /*!< Bit mask of PATCHREV field. */ + +/* MINORREV @Bits 8..15 : Indicates the number of the minor revision */ + #define VPRCSR_MIMPID_MINORREV_Pos (8UL) /*!< Position of MINORREV field. */ + #define VPRCSR_MIMPID_MINORREV_Msk (0xFFUL << VPRCSR_MIMPID_MINORREV_Pos) /*!< Bit mask of MINORREV field. */ + +/* MAJORREV @Bits 16..23 : Indicates the number of the major revison */ + #define VPRCSR_MIMPID_MAJORREV_Pos (16UL) /*!< Position of MAJORREV field. */ + #define VPRCSR_MIMPID_MAJORREV_Msk (0xFFUL << VPRCSR_MIMPID_MAJORREV_Pos) /*!< Bit mask of MAJORREV field. */ + + +/** + * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID + */ + #define VPRCSR_MHARTID (0x00000F14ul) + #define VPRCSR_MHARTID_ResetValue (0x00000000UL) /*!< Reset value of MHARTID register. */ + +/* HARTNUM @Bits 0..31 : Machine Hart ID value */ + #define VPRCSR_MHARTID_HARTNUM_Pos (0UL) /*!< Position of HARTNUM field. */ + #define VPRCSR_MHARTID_HARTNUM_Msk (0xFFFFFFFFUL << VPRCSR_MHARTID_HARTNUM_Pos) /*!< Bit mask of HARTNUM field. */ + + +/** + * @brief NORDIC [VPRCSR_NORDIC] (unspecified) + */ + +/** + * @brief VPRNORDICCTRL [VPRCSR_NORDIC_VPRNORDICCTRL] Nordic Core Control + */ + #define VPRCSR_NORDIC_VPRNORDICCTRL (0x000007C0ul) + #define VPRCSR_NORDIC_VPRNORDICCTRL_ResetValue (0x00000000UL) /*!< Reset value of VPRNORDICCTRL register. */ + +/* ENABLERTPERIPH @Bit 0 : Control bit to enable Real-Time Peripherals */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos (0UL) /*!< Position of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos) /*!< Bit mask + of ENABLERTPERIPH field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Min (0x0UL) /*!< Min enumerator value of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Max (0x1UL) /*!< Max enumerator value of ENABLERTPERIPH field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Enabled (0x1UL) /*!< (unspecified) */ + +/* ENABLEREMAP @Bit 3 : Enable remap feature */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos (3UL) /*!< Position of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos) /*!< Bit mask of + ENABLEREMAP field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Min (0x0UL) /*!< Min enumerator value of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Max (0x1UL) /*!< Max enumerator value of ENABLEREMAP field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Enabled (0x1UL) /*!< (unspecified) */ + +/* CNTIRQENABLE @Bit 6 : Enables the generation of IRQ number COUNTER_IRQ_NUM */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos (6UL) /*!< Position of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos) /*!< Bit mask of + CNTIRQENABLE field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Min (0x0UL) /*!< Min enumerator value of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Max (0x1UL) /*!< Max enumerator value of CNTIRQENABLE field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Enabled (0x1UL) /*!< (unspecified) */ + +/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos) /*!< Bit mask of + NORDICKEY field.*/ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled */ + + +/** + * @brief VPRNORDICSLEEPCTRL [VPRCSR_NORDIC_VPRNORDICSLEEPCTRL] Nordic Sleep Control + */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL (0x000007C1ul) + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICSLEEPCTRL register. */ + +/* SLEEPSTATE @Bits 0..3 : Sleep State */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk (0xFUL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos) /*!< Bit + mask of SLEEPSTATE field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Min (0x0UL) /*!< Min enumerator value of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Max (0xFUL) /*!< Max enumerator value of SLEEPSTATE field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_WAIT (0x0UL) /*!< Sleep is not turning off the clock */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_RESET (0x2UL) /*!< Sleep state default reset value. Going to sleep with + sleep state = RESET has the same effect as going to + sleep with sleep state = WAIT*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_SLEEP (0x5UL) /*!< Sleep is turning the clock off */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_DEEPSLEEP (0x7UL) /*!< Sleep is turning the clock off and power is turned + off*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_HIBERNATE (0xFUL) /*!< sleep is turning the clock off and all the + registers are saved automatically, restart by a + reset*/ + +/* RETURNTOSLEEP @Bit 16 : Return to Sleep */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos (16UL) /*!< Position of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos) /*!< + Bit mask of RETURNTOSLEEP field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Min (0x0UL) /*!< Min enumerator value of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Max (0x1UL) /*!< Max enumerator value of RETURNTOSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Enabled (0x1UL) /*!< (unspecified) */ + +/* STACKONSLEEP @Bit 17 : Stack on Sleep */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos (17UL) /*!< Position of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos) /*!< + Bit mask of STACKONSLEEP field.*/ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Min (0x0UL) /*!< Min enumerator value of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Max (0x1UL) /*!< Max enumerator value of STACKONSLEEP field. */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Enabled (0x1UL) /*!< (unspecified) */ + + +/** + * @brief VPRNORDICFEATURESDISABLE [VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE] (unspecified) + */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE (0x000007C2ul) + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICFEATURESDISABLE + register.*/ + +/* DISABLECLICROUNDROBIN @Bit 3 : Disable CLIC Round Robin */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos (3UL) /*!< Position of DISABLECLICROUNDROBIN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos) + /*!< Bit mask of DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Min (0x0UL) /*!< Min enumerator value of + DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Max (0x1UL) /*!< Max enumerator value of + DISABLECLICROUNDROBIN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Disabled (0x1UL) /*!< (unspecified) */ + +/* UNRECOVRETURN @Bit 4 : Unrecoverable Return */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos (4UL) /*!< Position of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos) + /*!< Bit mask of UNRECOVRETURN field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Min (0x0UL) /*!< Min enumerator value of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Max (0x1UL) /*!< Max enumerator value of UNRECOVRETURN field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Disabled (0x0UL) /*!< (unspecified) */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled (0x1UL) /*!< (unspecified) */ + +/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos) + /*!< Bit mask of NORDICKEY field.*/ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field. */ + #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled */ + + +/** + * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO + */ + #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul) + #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x00000000UL) /*!< Reset value of VIOPINS register. */ + +/* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */ + #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_VIOPINS_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_VIOPINS_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters + */ + #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul) + #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x00000016UL) /*!< Reset value of EXTPARAMS register. */ + +/* MULDIV @Bits 0..1 : value of MULDIV */ + #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL) /*!< Position of MULDIV field. */ + #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Msk (0x3UL << VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos) /*!< Bit mask of MULDIV field. */ + +/* DBG @Bit 2 : value of DBG */ + #define VPRCSR_NORDIC_EXTPARAMS_DBG_Pos (2UL) /*!< Position of DBG field. */ + #define VPRCSR_NORDIC_EXTPARAMS_DBG_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_DBG_Pos) /*!< Bit mask of DBG field. */ + +/* BKPT @Bits 3..6 : value of BKPT */ + #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos (3UL) /*!< Position of BKPT field. */ + #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Msk (0xFUL << VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos) /*!< Bit mask of BKPT field. */ + +/* REMAP @Bit 7 : value of REMAP */ + #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos (7UL) /*!< Position of REMAP field. */ + #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos) /*!< Bit mask of REMAP field. */ + + +/** + * @brief RTPERIPHCTRL [VPRCSR_NORDIC_RTPERIPHCTRL] RT peripheral control + */ + #define VPRCSR_NORDIC_RTPERIPHCTRL (0x000007CCul) + #define VPRCSR_NORDIC_RTPERIPHCTRL_ResetValue (0x00000000UL) /*!< Reset value of RTPERIPHCTRL register. */ + +/* CLOCKPOLARITY @Bit 0 : Clock polarity */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos (0UL) /*!< Position of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos) /*!< Bit mask of + CLOCKPOLARITY field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Min (0x0UL) /*!< Min enumerator value of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Max (0x1UL) /*!< Max enumerator value of CLOCKPOLARITY field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Low (0x0UL) /*!< Clock polarity is low */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_High (0x1UL) /*!< Clock polarity is High */ + +/* STOPCOUNTERS @Bit 4 : Stop counters CNT0 and CNT1 on OUTB under-run */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos (4UL) /*!< Position of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos) /*!< Bit mask of + STOPCOUNTERS field.*/ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Min (0x0UL) /*!< Min enumerator value of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Max (0x1UL) /*!< Max enumerator value of STOPCOUNTERS field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_NoStop (0x0UL) /*!< Counters do not stop on OUTB under-run */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Stop (0x1UL) /*!< Counters stop on OUTB under-run */ + +/* INSEL @Bit 8 : Input pin selection */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos (8UL) /*!< Position of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos) /*!< Bit mask of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Min (0x0UL) /*!< Min enumerator value of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Max (0x1UL) /*!< Max enumerator value of INSEL field. */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SamePin (0x0UL) /*!< Sample on same OUT pin */ + #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SeparatePin (0x1UL) /*!< Sample on separate pin */ + + +/** + * @brief CNTMODE0 [VPRCSR_NORDIC_CNTMODE0] CNT0 Mode + */ + #define VPRCSR_NORDIC_CNTMODE0 (0x000007D0ul) + #define VPRCSR_NORDIC_CNTMODE0_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE0 register. */ + +/* CNTMODE0 @Bits 0..1 : CNT0 Mode */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos (0UL) /*!< Position of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Msk (0x3UL << VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos) /*!< Bit mask of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Min (0x0UL) /*!< Min enumerator value of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Max (0x3UL) /*!< Max enumerator value of CNTMODE0 field. */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_STOP (0x0UL) /*!< CNT0 stops at 0 */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_WRAP (0x1UL) /*!< CNT0 will continue counting from 0xFFFF */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_RELOAD (0x2UL) /*!< CNT0 will continue counting from the value in CNTTOP */ + #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGCOMB (0x3UL) /*!< In Trigger mode CNT0 stops counting at 0. Counting will restart + when a VIO event happens*/ + + +/** + * @brief CNTMODE1 [VPRCSR_NORDIC_CNTMODE1] CNT1 Mode + */ + #define VPRCSR_NORDIC_CNTMODE1 (0x000007D1ul) + #define VPRCSR_NORDIC_CNTMODE1_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE1 register. */ + +/* CNTMODE1 @Bits 0..1 : CNT1 Mode */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos (0UL) /*!< Position of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Msk (0x3UL << VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos) /*!< Bit mask of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Min (0x0UL) /*!< Min enumerator value of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Max (0x3UL) /*!< Max enumerator value of CNTMODE1 field. */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_STOP (0x0UL) /*!< CNT1 stops at 0 */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_WRAP (0x1UL) /*!< CNT1 will continue counting from 0xFFFF */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_RELOAD (0x2UL) /*!< CNT1 will continue counting from the value in CNTTOP */ + #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGCOMB (0x3UL) /*!< In combine mode mode CNT1 acts as an extension of CNT0 (16 most + significant bits of the 32-bit CNT)*/ + + +/** + * @brief CNT [VPRCSR_NORDIC_CNT] 32-bit Counter + */ + #define VPRCSR_NORDIC_CNT (0x000007D2ul) + #define VPRCSR_NORDIC_CNT_ResetValue (0x00000000UL) /*!< Reset value of CNT register. */ + +/* CNT0 @Bits 0..15 : 16-bit Counter 0 */ + #define VPRCSR_NORDIC_CNT_CNT0_Pos (0UL) /*!< Position of CNT0 field. */ + #define VPRCSR_NORDIC_CNT_CNT0_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT0_Pos) /*!< Bit mask of CNT0 field. */ + +/* CNT1 @Bits 16..31 : 16-bit Counter 1 */ + #define VPRCSR_NORDIC_CNT_CNT1_Pos (16UL) /*!< Position of CNT1 field. */ + #define VPRCSR_NORDIC_CNT_CNT1_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT1_Pos) /*!< Bit mask of CNT1 field. */ + + +/** + * @brief CNTTOP [VPRCSR_NORDIC_CNTTOP] Counter Top + */ + #define VPRCSR_NORDIC_CNTTOP (0x000007D3ul) + #define VPRCSR_NORDIC_CNTTOP_ResetValue (0x00000000UL) /*!< Reset value of CNTTOP register. */ + +/* CNT0RELOAD @Bits 0..15 : Reload value for CNT0 */ + #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos (0UL) /*!< Position of CNT0RELOAD field. */ + #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos) /*!< Bit mask of CNT0RELOAD + field.*/ + +/* CNT1RELOAD @Bits 16..31 : Reload value for CNT1 */ + #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos (16UL) /*!< Position of CNT1RELOAD field. */ + #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos) /*!< Bit mask of CNT1RELOAD + field.*/ + + +/** + * @brief CNTADD [VPRCSR_NORDIC_CNTADD] CNT Add + */ + #define VPRCSR_NORDIC_CNTADD (0x000007D4ul) + #define VPRCSR_NORDIC_CNTADD_ResetValue (0x00000000UL) /*!< Reset value of CNTADD register. */ + +/* VAL @Bits 0..31 : Value added to CNT */ + #define VPRCSR_NORDIC_CNTADD_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNT0 [VPRCSR_NORDIC_CNT0] 16 bit Counter 0 + */ + #define VPRCSR_NORDIC_CNT0 (0x000007D5ul) + #define VPRCSR_NORDIC_CNT0_ResetValue (0x00000000UL) /*!< Reset value of CNT0 register. */ + +/* VAL @Bits 0..15 : CNT0 value */ + #define VPRCSR_NORDIC_CNT0_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNT0_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT0_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNTADD0 [VPRCSR_NORDIC_CNTADD0] CNT0 Add + */ + #define VPRCSR_NORDIC_CNTADD0 (0x000007D6ul) + #define VPRCSR_NORDIC_CNTADD0_ResetValue (0x00000000UL) /*!< Reset value of CNTADD0 register. */ + +/* VAL @Bits 0..31 : Value added to CNT0 */ + #define VPRCSR_NORDIC_CNTADD0_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD0_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD0_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNT1 [VPRCSR_NORDIC_CNT1] 16-bit Counter 1 + */ + #define VPRCSR_NORDIC_CNT1 (0x000007D7ul) + #define VPRCSR_NORDIC_CNT1_ResetValue (0x00000000UL) /*!< Reset value of CNT1 register. */ + +/* VAL @Bits 0..15 : CNT1 value */ + #define VPRCSR_NORDIC_CNT1_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNT1_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT1_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief CNTADD1 [VPRCSR_NORDIC_CNTADD1] CNT1 Add + */ + #define VPRCSR_NORDIC_CNTADD1 (0x000007D8ul) + #define VPRCSR_NORDIC_CNTADD1_ResetValue (0x00000000UL) /*!< Reset value of CNTADD1 register. */ + +/* VAL @Bits 0..31 : Value added to CNT1 */ + #define VPRCSR_NORDIC_CNTADD1_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_CNTADD1_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD1_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief WAIT0 [VPRCSR_NORDIC_WAIT0] Wait 0 + */ + #define VPRCSR_NORDIC_WAIT0 (0x000007DAul) + #define VPRCSR_NORDIC_WAIT0_ResetValue (0x00000000UL) /*!< Reset value of WAIT0 register. */ + +/* DATA @Bits 0..15 : Value to write to CNT0 */ + #define VPRCSR_NORDIC_WAIT0_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_NORDIC_WAIT0_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT0_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* WRITEDATA @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos (16UL) /*!< Position of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Min (0x0UL) /*!< Min enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Max (0x1UL) /*!< Max enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT0 reaches 0 */ + #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT0 and then wait until CNT0 reaches 0 */ + + +/** + * @brief WAIT1 [VPRCSR_NORDIC_WAIT1] Wait 1 + */ + #define VPRCSR_NORDIC_WAIT1 (0x000007DBul) + #define VPRCSR_NORDIC_WAIT1_ResetValue (0x00000000UL) /*!< Reset value of WAIT1 register. */ + +/* DATA @Bits 0..15 : Value to write to CNT1 */ + #define VPRCSR_NORDIC_WAIT1_DATA_Pos (0UL) /*!< Position of DATA field. */ + #define VPRCSR_NORDIC_WAIT1_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT1_DATA_Pos) /*!< Bit mask of DATA field. */ + +/* WRITEDATA @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos (16UL) /*!< Position of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Min (0x0UL) /*!< Min enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Max (0x1UL) /*!< Max enumerator value of WRITEDATA field. */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT1 reaches 0 */ + #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT1 and then wait until CNT1 reaches 0 */ + + +/** + * @brief WAIT [VPRCSR_NORDIC_WAIT] Wait + */ + #define VPRCSR_NORDIC_WAIT (0x000007DCul) + #define VPRCSR_NORDIC_WAIT_ResetValue (0x00000000UL) /*!< Reset value of WAIT register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_WAIT_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_WAIT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_WAIT_VAL_Pos) /*!< Bit mask of VAL field. */ + + +/** + * @brief TASKS [VPRCSR_NORDIC_TASKS] DPPI Tasks + */ + #define VPRCSR_NORDIC_TASKS (0x000007E0ul) + #define VPRCSR_NORDIC_TASKS_ResetValue (0x00000000UL) /*!< Reset value of TASKS register. */ + +/* TASKS0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Pos (0UL) /*!< Position of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS0_Pos) /*!< Bit mask of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Min (0x0UL) /*!< Min enumerator value of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Max (0x1UL) /*!< Max enumerator value of TASKS0 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Disabled (0x0UL) /*!< TASKS[0] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS0_Enabled (0x1UL) /*!< TASKS[0] enabled */ + +/* TASKS1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Pos (1UL) /*!< Position of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS1_Pos) /*!< Bit mask of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Min (0x0UL) /*!< Min enumerator value of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Max (0x1UL) /*!< Max enumerator value of TASKS1 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Disabled (0x0UL) /*!< TASKS[1] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS1_Enabled (0x1UL) /*!< TASKS[1] enabled */ + +/* TASKS2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Pos (2UL) /*!< Position of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS2_Pos) /*!< Bit mask of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Min (0x0UL) /*!< Min enumerator value of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Max (0x1UL) /*!< Max enumerator value of TASKS2 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Disabled (0x0UL) /*!< TASKS[2] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS2_Enabled (0x1UL) /*!< TASKS[2] enabled */ + +/* TASKS3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Pos (3UL) /*!< Position of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS3_Pos) /*!< Bit mask of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Min (0x0UL) /*!< Min enumerator value of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Max (0x1UL) /*!< Max enumerator value of TASKS3 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Disabled (0x0UL) /*!< TASKS[3] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS3_Enabled (0x1UL) /*!< TASKS[3] enabled */ + +/* TASKS4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Pos (4UL) /*!< Position of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS4_Pos) /*!< Bit mask of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Min (0x0UL) /*!< Min enumerator value of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Max (0x1UL) /*!< Max enumerator value of TASKS4 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Disabled (0x0UL) /*!< TASKS[4] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS4_Enabled (0x1UL) /*!< TASKS[4] enabled */ + +/* TASKS5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Pos (5UL) /*!< Position of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS5_Pos) /*!< Bit mask of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Min (0x0UL) /*!< Min enumerator value of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Max (0x1UL) /*!< Max enumerator value of TASKS5 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Disabled (0x0UL) /*!< TASKS[5] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS5_Enabled (0x1UL) /*!< TASKS[5] enabled */ + +/* TASKS6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Pos (6UL) /*!< Position of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS6_Pos) /*!< Bit mask of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Min (0x0UL) /*!< Min enumerator value of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Max (0x1UL) /*!< Max enumerator value of TASKS6 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Disabled (0x0UL) /*!< TASKS[6] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS6_Enabled (0x1UL) /*!< TASKS[6] enabled */ + +/* TASKS7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Pos (7UL) /*!< Position of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS7_Pos) /*!< Bit mask of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Min (0x0UL) /*!< Min enumerator value of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Max (0x1UL) /*!< Max enumerator value of TASKS7 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Disabled (0x0UL) /*!< TASKS[7] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS7_Enabled (0x1UL) /*!< TASKS[7] enabled */ + +/* TASKS8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Pos (8UL) /*!< Position of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS8_Pos) /*!< Bit mask of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Min (0x0UL) /*!< Min enumerator value of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Max (0x1UL) /*!< Max enumerator value of TASKS8 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Disabled (0x0UL) /*!< TASKS[8] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS8_Enabled (0x1UL) /*!< TASKS[8] enabled */ + +/* TASKS9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Pos (9UL) /*!< Position of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS9_Pos) /*!< Bit mask of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Min (0x0UL) /*!< Min enumerator value of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Max (0x1UL) /*!< Max enumerator value of TASKS9 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Disabled (0x0UL) /*!< TASKS[9] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS9_Enabled (0x1UL) /*!< TASKS[9] enabled */ + +/* TASKS10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Pos (10UL) /*!< Position of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS10_Pos) /*!< Bit mask of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Min (0x0UL) /*!< Min enumerator value of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Max (0x1UL) /*!< Max enumerator value of TASKS10 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Disabled (0x0UL) /*!< TASKS[10] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS10_Enabled (0x1UL) /*!< TASKS[10] enabled */ + +/* TASKS11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Pos (11UL) /*!< Position of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS11_Pos) /*!< Bit mask of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Min (0x0UL) /*!< Min enumerator value of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Max (0x1UL) /*!< Max enumerator value of TASKS11 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Disabled (0x0UL) /*!< TASKS[11] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS11_Enabled (0x1UL) /*!< TASKS[11] enabled */ + +/* TASKS12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Pos (12UL) /*!< Position of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS12_Pos) /*!< Bit mask of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Min (0x0UL) /*!< Min enumerator value of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Max (0x1UL) /*!< Max enumerator value of TASKS12 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Disabled (0x0UL) /*!< TASKS[12] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS12_Enabled (0x1UL) /*!< TASKS[12] enabled */ + +/* TASKS13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Pos (13UL) /*!< Position of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS13_Pos) /*!< Bit mask of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Min (0x0UL) /*!< Min enumerator value of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Max (0x1UL) /*!< Max enumerator value of TASKS13 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Disabled (0x0UL) /*!< TASKS[13] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS13_Enabled (0x1UL) /*!< TASKS[13] enabled */ + +/* TASKS14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Pos (14UL) /*!< Position of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS14_Pos) /*!< Bit mask of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Min (0x0UL) /*!< Min enumerator value of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Max (0x1UL) /*!< Max enumerator value of TASKS14 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Disabled (0x0UL) /*!< TASKS[14] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS14_Enabled (0x1UL) /*!< TASKS[14] enabled */ + +/* TASKS15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Pos (15UL) /*!< Position of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS15_Pos) /*!< Bit mask of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Min (0x0UL) /*!< Min enumerator value of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Max (0x1UL) /*!< Max enumerator value of TASKS15 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Disabled (0x0UL) /*!< TASKS[15] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS15_Enabled (0x1UL) /*!< TASKS[15] enabled */ + +/* TASKS16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Pos (16UL) /*!< Position of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS16_Pos) /*!< Bit mask of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Min (0x0UL) /*!< Min enumerator value of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Max (0x1UL) /*!< Max enumerator value of TASKS16 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Disabled (0x0UL) /*!< TASKS[16] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS16_Enabled (0x1UL) /*!< TASKS[16] enabled */ + +/* TASKS17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Pos (17UL) /*!< Position of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS17_Pos) /*!< Bit mask of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Min (0x0UL) /*!< Min enumerator value of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Max (0x1UL) /*!< Max enumerator value of TASKS17 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Disabled (0x0UL) /*!< TASKS[17] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS17_Enabled (0x1UL) /*!< TASKS[17] enabled */ + +/* TASKS18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Pos (18UL) /*!< Position of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS18_Pos) /*!< Bit mask of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Min (0x0UL) /*!< Min enumerator value of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Max (0x1UL) /*!< Max enumerator value of TASKS18 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Disabled (0x0UL) /*!< TASKS[18] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS18_Enabled (0x1UL) /*!< TASKS[18] enabled */ + +/* TASKS19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Pos (19UL) /*!< Position of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS19_Pos) /*!< Bit mask of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Min (0x0UL) /*!< Min enumerator value of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Max (0x1UL) /*!< Max enumerator value of TASKS19 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Disabled (0x0UL) /*!< TASKS[19] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS19_Enabled (0x1UL) /*!< TASKS[19] enabled */ + +/* TASKS20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Pos (20UL) /*!< Position of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS20_Pos) /*!< Bit mask of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Min (0x0UL) /*!< Min enumerator value of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Max (0x1UL) /*!< Max enumerator value of TASKS20 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Disabled (0x0UL) /*!< TASKS[20] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS20_Enabled (0x1UL) /*!< TASKS[20] enabled */ + +/* TASKS21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Pos (21UL) /*!< Position of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS21_Pos) /*!< Bit mask of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Min (0x0UL) /*!< Min enumerator value of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Max (0x1UL) /*!< Max enumerator value of TASKS21 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Disabled (0x0UL) /*!< TASKS[21] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS21_Enabled (0x1UL) /*!< TASKS[21] enabled */ + +/* TASKS22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Pos (22UL) /*!< Position of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS22_Pos) /*!< Bit mask of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Min (0x0UL) /*!< Min enumerator value of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Max (0x1UL) /*!< Max enumerator value of TASKS22 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Disabled (0x0UL) /*!< TASKS[22] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS22_Enabled (0x1UL) /*!< TASKS[22] enabled */ + +/* TASKS23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Pos (23UL) /*!< Position of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS23_Pos) /*!< Bit mask of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Min (0x0UL) /*!< Min enumerator value of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Max (0x1UL) /*!< Max enumerator value of TASKS23 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Disabled (0x0UL) /*!< TASKS[23] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS23_Enabled (0x1UL) /*!< TASKS[23] enabled */ + +/* TASKS24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Pos (24UL) /*!< Position of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS24_Pos) /*!< Bit mask of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Min (0x0UL) /*!< Min enumerator value of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Max (0x1UL) /*!< Max enumerator value of TASKS24 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Disabled (0x0UL) /*!< TASKS[24] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS24_Enabled (0x1UL) /*!< TASKS[24] enabled */ + +/* TASKS25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Pos (25UL) /*!< Position of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS25_Pos) /*!< Bit mask of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Min (0x0UL) /*!< Min enumerator value of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Max (0x1UL) /*!< Max enumerator value of TASKS25 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Disabled (0x0UL) /*!< TASKS[25] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS25_Enabled (0x1UL) /*!< TASKS[25] enabled */ + +/* TASKS26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Pos (26UL) /*!< Position of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS26_Pos) /*!< Bit mask of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Min (0x0UL) /*!< Min enumerator value of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Max (0x1UL) /*!< Max enumerator value of TASKS26 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Disabled (0x0UL) /*!< TASKS[26] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS26_Enabled (0x1UL) /*!< TASKS[26] enabled */ + +/* TASKS27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Pos (27UL) /*!< Position of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS27_Pos) /*!< Bit mask of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Min (0x0UL) /*!< Min enumerator value of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Max (0x1UL) /*!< Max enumerator value of TASKS27 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Disabled (0x0UL) /*!< TASKS[27] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS27_Enabled (0x1UL) /*!< TASKS[27] enabled */ + +/* TASKS28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Pos (28UL) /*!< Position of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS28_Pos) /*!< Bit mask of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Min (0x0UL) /*!< Min enumerator value of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Max (0x1UL) /*!< Max enumerator value of TASKS28 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Disabled (0x0UL) /*!< TASKS[28] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS28_Enabled (0x1UL) /*!< TASKS[28] enabled */ + +/* TASKS29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Pos (29UL) /*!< Position of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS29_Pos) /*!< Bit mask of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Min (0x0UL) /*!< Min enumerator value of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Max (0x1UL) /*!< Max enumerator value of TASKS29 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Disabled (0x0UL) /*!< TASKS[29] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS29_Enabled (0x1UL) /*!< TASKS[29] enabled */ + +/* TASKS30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Pos (30UL) /*!< Position of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS30_Pos) /*!< Bit mask of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Min (0x0UL) /*!< Min enumerator value of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Max (0x1UL) /*!< Max enumerator value of TASKS30 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Disabled (0x0UL) /*!< TASKS[30] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS30_Enabled (0x1UL) /*!< TASKS[30] enabled */ + +/* TASKS31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Pos (31UL) /*!< Position of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS31_Pos) /*!< Bit mask of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Min (0x0UL) /*!< Min enumerator value of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Max (0x1UL) /*!< Max enumerator value of TASKS31 field. */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Disabled (0x0UL) /*!< TASKS[31] diabled */ + #define VPRCSR_NORDIC_TASKS_TASKS31_Enabled (0x1UL) /*!< TASKS[31] enabled */ + + +/** + * @brief SUBSCRIBE [VPRCSR_NORDIC_SUBSCRIBE] Enable Task Subscription + */ + #define VPRCSR_NORDIC_SUBSCRIBE (0x000007E1ul) + #define VPRCSR_NORDIC_SUBSCRIBE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE register. */ + +/* SUBSCRIBE0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos (0UL) /*!< Position of SUBSCRIBE0 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos) /*!< Bit mask of SUBSCRIBE0 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE0 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE0 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Disabled (0x0UL) /*!< Subscribe disabled for TASK[0] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Enabled (0x1UL) /*!< Subscribe enabled for TASK[0] */ + +/* SUBSCRIBE1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos (1UL) /*!< Position of SUBSCRIBE1 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos) /*!< Bit mask of SUBSCRIBE1 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE1 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE1 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Disabled (0x0UL) /*!< Subscribe disabled for TASK[1] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Enabled (0x1UL) /*!< Subscribe enabled for TASK[1] */ + +/* SUBSCRIBE2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos (2UL) /*!< Position of SUBSCRIBE2 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos) /*!< Bit mask of SUBSCRIBE2 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE2 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE2 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Disabled (0x0UL) /*!< Subscribe disabled for TASK[2] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Enabled (0x1UL) /*!< Subscribe enabled for TASK[2] */ + +/* SUBSCRIBE3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos (3UL) /*!< Position of SUBSCRIBE3 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos) /*!< Bit mask of SUBSCRIBE3 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE3 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE3 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3] */ + +/* SUBSCRIBE4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos (4UL) /*!< Position of SUBSCRIBE4 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos) /*!< Bit mask of SUBSCRIBE4 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE4 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE4 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Disabled (0x0UL) /*!< Subscribe disabled for TASK[4] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Enabled (0x1UL) /*!< Subscribe enabled for TASK[4] */ + +/* SUBSCRIBE5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos (5UL) /*!< Position of SUBSCRIBE5 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos) /*!< Bit mask of SUBSCRIBE5 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE5 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE5 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Disabled (0x0UL) /*!< Subscribe disabled for TASK[5] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Enabled (0x1UL) /*!< Subscribe enabled for TASK[5] */ + +/* SUBSCRIBE6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos (6UL) /*!< Position of SUBSCRIBE6 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos) /*!< Bit mask of SUBSCRIBE6 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE6 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE6 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Disabled (0x0UL) /*!< Subscribe disabled for TASK[6] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Enabled (0x1UL) /*!< Subscribe enabled for TASK[6] */ + +/* SUBSCRIBE7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos (7UL) /*!< Position of SUBSCRIBE7 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos) /*!< Bit mask of SUBSCRIBE7 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE7 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE7 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Disabled (0x0UL) /*!< Subscribe disabled for TASK[7] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Enabled (0x1UL) /*!< Subscribe enabled for TASK[7] */ + +/* SUBSCRIBE8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos (8UL) /*!< Position of SUBSCRIBE8 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos) /*!< Bit mask of SUBSCRIBE8 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE8 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE8 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Disabled (0x0UL) /*!< Subscribe disabled for TASK[8] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Enabled (0x1UL) /*!< Subscribe enabled for TASK[8] */ + +/* SUBSCRIBE9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos (9UL) /*!< Position of SUBSCRIBE9 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos) /*!< Bit mask of SUBSCRIBE9 + field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE9 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE9 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Disabled (0x0UL) /*!< Subscribe disabled for TASK[9] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Enabled (0x1UL) /*!< Subscribe enabled for TASK[9] */ + +/* SUBSCRIBE10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos (10UL) /*!< Position of SUBSCRIBE10 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos) /*!< Bit mask of + SUBSCRIBE10 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE10 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE10 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Disabled (0x0UL) /*!< Subscribe disabled for TASK[10] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Enabled (0x1UL) /*!< Subscribe enabled for TASK[10] */ + +/* SUBSCRIBE11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos (11UL) /*!< Position of SUBSCRIBE11 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos) /*!< Bit mask of + SUBSCRIBE11 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE11 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE11 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Disabled (0x0UL) /*!< Subscribe disabled for TASK[11] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Enabled (0x1UL) /*!< Subscribe enabled for TASK[11] */ + +/* SUBSCRIBE12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos (12UL) /*!< Position of SUBSCRIBE12 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos) /*!< Bit mask of + SUBSCRIBE12 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE12 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE12 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Disabled (0x0UL) /*!< Subscribe disabled for TASK[12] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Enabled (0x1UL) /*!< Subscribe enabled for TASK[12] */ + +/* SUBSCRIBE13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos (13UL) /*!< Position of SUBSCRIBE13 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos) /*!< Bit mask of + SUBSCRIBE13 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE13 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE13 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Disabled (0x0UL) /*!< Subscribe disabled for TASK[13] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Enabled (0x1UL) /*!< Subscribe enabled for TASK[13] */ + +/* SUBSCRIBE14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos (14UL) /*!< Position of SUBSCRIBE14 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos) /*!< Bit mask of + SUBSCRIBE14 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE14 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE14 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Disabled (0x0UL) /*!< Subscribe disabled for TASK[14] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Enabled (0x1UL) /*!< Subscribe enabled for TASK[14] */ + +/* SUBSCRIBE15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos (15UL) /*!< Position of SUBSCRIBE15 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos) /*!< Bit mask of + SUBSCRIBE15 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE15 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE15 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Disabled (0x0UL) /*!< Subscribe disabled for TASK[15] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Enabled (0x1UL) /*!< Subscribe enabled for TASK[15] */ + +/* SUBSCRIBE16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of + SUBSCRIBE16 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16] */ + +/* SUBSCRIBE17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of + SUBSCRIBE17 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17] */ + +/* SUBSCRIBE18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of + SUBSCRIBE18 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18] */ + +/* SUBSCRIBE19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of + SUBSCRIBE19 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19] */ + +/* SUBSCRIBE20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos (20UL) /*!< Position of SUBSCRIBE20 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos) /*!< Bit mask of + SUBSCRIBE20 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE20 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE20 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Disabled (0x0UL) /*!< Subscribe disabled for TASK[20] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Enabled (0x1UL) /*!< Subscribe enabled for TASK[20] */ + +/* SUBSCRIBE21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos (21UL) /*!< Position of SUBSCRIBE21 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos) /*!< Bit mask of + SUBSCRIBE21 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE21 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE21 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Disabled (0x0UL) /*!< Subscribe disabled for TASK[21] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Enabled (0x1UL) /*!< Subscribe enabled for TASK[21] */ + +/* SUBSCRIBE22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos (22UL) /*!< Position of SUBSCRIBE22 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos) /*!< Bit mask of + SUBSCRIBE22 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE22 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE22 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Disabled (0x0UL) /*!< Subscribe disabled for TASK[22] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Enabled (0x1UL) /*!< Subscribe enabled for TASK[22] */ + +/* SUBSCRIBE23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos (23UL) /*!< Position of SUBSCRIBE23 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos) /*!< Bit mask of + SUBSCRIBE23 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE23 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE23 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Disabled (0x0UL) /*!< Subscribe disabled for TASK[23] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Enabled (0x1UL) /*!< Subscribe enabled for TASK[23] */ + +/* SUBSCRIBE24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos (24UL) /*!< Position of SUBSCRIBE24 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos) /*!< Bit mask of + SUBSCRIBE24 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE24 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE24 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Disabled (0x0UL) /*!< Subscribe disabled for TASK[24] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Enabled (0x1UL) /*!< Subscribe enabled for TASK[24] */ + +/* SUBSCRIBE25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos (25UL) /*!< Position of SUBSCRIBE25 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos) /*!< Bit mask of + SUBSCRIBE25 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE25 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE25 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Disabled (0x0UL) /*!< Subscribe disabled for TASK[25] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Enabled (0x1UL) /*!< Subscribe enabled for TASK[25] */ + +/* SUBSCRIBE26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos (26UL) /*!< Position of SUBSCRIBE26 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos) /*!< Bit mask of + SUBSCRIBE26 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE26 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE26 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Disabled (0x0UL) /*!< Subscribe disabled for TASK[26] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Enabled (0x1UL) /*!< Subscribe enabled for TASK[26] */ + +/* SUBSCRIBE27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos (27UL) /*!< Position of SUBSCRIBE27 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos) /*!< Bit mask of + SUBSCRIBE27 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE27 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE27 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Disabled (0x0UL) /*!< Subscribe disabled for TASK[27] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Enabled (0x1UL) /*!< Subscribe enabled for TASK[27] */ + +/* SUBSCRIBE28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos (28UL) /*!< Position of SUBSCRIBE28 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos) /*!< Bit mask of + SUBSCRIBE28 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE28 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE28 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Disabled (0x0UL) /*!< Subscribe disabled for TASK[28] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Enabled (0x1UL) /*!< Subscribe enabled for TASK[28] */ + +/* SUBSCRIBE29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos (29UL) /*!< Position of SUBSCRIBE29 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos) /*!< Bit mask of + SUBSCRIBE29 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE29 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE29 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Disabled (0x0UL) /*!< Subscribe disabled for TASK[29] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Enabled (0x1UL) /*!< Subscribe enabled for TASK[29] */ + +/* SUBSCRIBE30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos (30UL) /*!< Position of SUBSCRIBE30 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos) /*!< Bit mask of + SUBSCRIBE30 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE30 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE30 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Disabled (0x0UL) /*!< Subscribe disabled for TASK[30] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Enabled (0x1UL) /*!< Subscribe enabled for TASK[30] */ + +/* SUBSCRIBE31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos (31UL) /*!< Position of SUBSCRIBE31 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos) /*!< Bit mask of + SUBSCRIBE31 field.*/ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE31 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE31 field. */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Disabled (0x0UL) /*!< Subscribe disabled for TASK[31] */ + #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Enabled (0x1UL) /*!< Subscribe enabled for TASK[31] */ + + +/** + * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events + */ + #define VPRCSR_NORDIC_EVENTS (0x000007E2ul) + #define VPRCSR_NORDIC_EVENTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS register. */ + +/* EVENTS0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Pos (0UL) /*!< Position of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS0_Pos) /*!< Bit mask of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Min (0x0UL) /*!< Min enumerator value of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Max (0x1UL) /*!< Max enumerator value of EVENTS0 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Disabled (0x0UL) /*!< EVENTS[0] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS0_Enabled (0x1UL) /*!< EVENTS[0] enabled */ + +/* EVENTS1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Pos (1UL) /*!< Position of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS1_Pos) /*!< Bit mask of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Min (0x0UL) /*!< Min enumerator value of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Max (0x1UL) /*!< Max enumerator value of EVENTS1 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Disabled (0x0UL) /*!< EVENTS[1] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS1_Enabled (0x1UL) /*!< EVENTS[1] enabled */ + +/* EVENTS2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Pos (2UL) /*!< Position of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS2_Pos) /*!< Bit mask of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Min (0x0UL) /*!< Min enumerator value of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Max (0x1UL) /*!< Max enumerator value of EVENTS2 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Disabled (0x0UL) /*!< EVENTS[2] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS2_Enabled (0x1UL) /*!< EVENTS[2] enabled */ + +/* EVENTS3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Pos (3UL) /*!< Position of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS3_Pos) /*!< Bit mask of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Min (0x0UL) /*!< Min enumerator value of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Max (0x1UL) /*!< Max enumerator value of EVENTS3 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Disabled (0x0UL) /*!< EVENTS[3] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS3_Enabled (0x1UL) /*!< EVENTS[3] enabled */ + +/* EVENTS4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Pos (4UL) /*!< Position of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS4_Pos) /*!< Bit mask of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Min (0x0UL) /*!< Min enumerator value of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Max (0x1UL) /*!< Max enumerator value of EVENTS4 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Disabled (0x0UL) /*!< EVENTS[4] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS4_Enabled (0x1UL) /*!< EVENTS[4] enabled */ + +/* EVENTS5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Pos (5UL) /*!< Position of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS5_Pos) /*!< Bit mask of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Min (0x0UL) /*!< Min enumerator value of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Max (0x1UL) /*!< Max enumerator value of EVENTS5 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Disabled (0x0UL) /*!< EVENTS[5] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS5_Enabled (0x1UL) /*!< EVENTS[5] enabled */ + +/* EVENTS6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Pos (6UL) /*!< Position of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS6_Pos) /*!< Bit mask of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Min (0x0UL) /*!< Min enumerator value of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Max (0x1UL) /*!< Max enumerator value of EVENTS6 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Disabled (0x0UL) /*!< EVENTS[6] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS6_Enabled (0x1UL) /*!< EVENTS[6] enabled */ + +/* EVENTS7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Pos (7UL) /*!< Position of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS7_Pos) /*!< Bit mask of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Min (0x0UL) /*!< Min enumerator value of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Max (0x1UL) /*!< Max enumerator value of EVENTS7 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Disabled (0x0UL) /*!< EVENTS[7] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS7_Enabled (0x1UL) /*!< EVENTS[7] enabled */ + +/* EVENTS8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Pos (8UL) /*!< Position of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS8_Pos) /*!< Bit mask of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Min (0x0UL) /*!< Min enumerator value of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Max (0x1UL) /*!< Max enumerator value of EVENTS8 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Disabled (0x0UL) /*!< EVENTS[8] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS8_Enabled (0x1UL) /*!< EVENTS[8] enabled */ + +/* EVENTS9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Pos (9UL) /*!< Position of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS9_Pos) /*!< Bit mask of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Min (0x0UL) /*!< Min enumerator value of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Max (0x1UL) /*!< Max enumerator value of EVENTS9 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Disabled (0x0UL) /*!< EVENTS[9] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS9_Enabled (0x1UL) /*!< EVENTS[9] enabled */ + +/* EVENTS10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Pos (10UL) /*!< Position of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS10_Pos) /*!< Bit mask of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Min (0x0UL) /*!< Min enumerator value of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Max (0x1UL) /*!< Max enumerator value of EVENTS10 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Disabled (0x0UL) /*!< EVENTS[10] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS10_Enabled (0x1UL) /*!< EVENTS[10] enabled */ + +/* EVENTS11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Pos (11UL) /*!< Position of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS11_Pos) /*!< Bit mask of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Min (0x0UL) /*!< Min enumerator value of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Max (0x1UL) /*!< Max enumerator value of EVENTS11 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Disabled (0x0UL) /*!< EVENTS[11] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS11_Enabled (0x1UL) /*!< EVENTS[11] enabled */ + +/* EVENTS12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Pos (12UL) /*!< Position of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS12_Pos) /*!< Bit mask of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Min (0x0UL) /*!< Min enumerator value of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Max (0x1UL) /*!< Max enumerator value of EVENTS12 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Disabled (0x0UL) /*!< EVENTS[12] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS12_Enabled (0x1UL) /*!< EVENTS[12] enabled */ + +/* EVENTS13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Pos (13UL) /*!< Position of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS13_Pos) /*!< Bit mask of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Min (0x0UL) /*!< Min enumerator value of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Max (0x1UL) /*!< Max enumerator value of EVENTS13 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Disabled (0x0UL) /*!< EVENTS[13] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS13_Enabled (0x1UL) /*!< EVENTS[13] enabled */ + +/* EVENTS14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Pos (14UL) /*!< Position of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS14_Pos) /*!< Bit mask of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Min (0x0UL) /*!< Min enumerator value of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Max (0x1UL) /*!< Max enumerator value of EVENTS14 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Disabled (0x0UL) /*!< EVENTS[14] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS14_Enabled (0x1UL) /*!< EVENTS[14] enabled */ + +/* EVENTS15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Pos (15UL) /*!< Position of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS15_Pos) /*!< Bit mask of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Min (0x0UL) /*!< Min enumerator value of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Max (0x1UL) /*!< Max enumerator value of EVENTS15 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Disabled (0x0UL) /*!< EVENTS[15] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS15_Enabled (0x1UL) /*!< EVENTS[15] enabled */ + +/* EVENTS16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Pos (16UL) /*!< Position of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS16_Pos) /*!< Bit mask of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Min (0x0UL) /*!< Min enumerator value of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Max (0x1UL) /*!< Max enumerator value of EVENTS16 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Disabled (0x0UL) /*!< EVENTS[16] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS16_Enabled (0x1UL) /*!< EVENTS[16] enabled */ + +/* EVENTS17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Pos (17UL) /*!< Position of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS17_Pos) /*!< Bit mask of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Min (0x0UL) /*!< Min enumerator value of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Max (0x1UL) /*!< Max enumerator value of EVENTS17 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Disabled (0x0UL) /*!< EVENTS[17] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS17_Enabled (0x1UL) /*!< EVENTS[17] enabled */ + +/* EVENTS18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Pos (18UL) /*!< Position of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS18_Pos) /*!< Bit mask of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Min (0x0UL) /*!< Min enumerator value of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Max (0x1UL) /*!< Max enumerator value of EVENTS18 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Disabled (0x0UL) /*!< EVENTS[18] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS18_Enabled (0x1UL) /*!< EVENTS[18] enabled */ + +/* EVENTS19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Pos (19UL) /*!< Position of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS19_Pos) /*!< Bit mask of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Min (0x0UL) /*!< Min enumerator value of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Max (0x1UL) /*!< Max enumerator value of EVENTS19 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Disabled (0x0UL) /*!< EVENTS[19] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS19_Enabled (0x1UL) /*!< EVENTS[19] enabled */ + +/* EVENTS20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Pos (20UL) /*!< Position of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS20_Pos) /*!< Bit mask of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Min (0x0UL) /*!< Min enumerator value of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Max (0x1UL) /*!< Max enumerator value of EVENTS20 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Disabled (0x0UL) /*!< EVENTS[20] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS20_Enabled (0x1UL) /*!< EVENTS[20] enabled */ + +/* EVENTS21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Pos (21UL) /*!< Position of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS21_Pos) /*!< Bit mask of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Min (0x0UL) /*!< Min enumerator value of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Max (0x1UL) /*!< Max enumerator value of EVENTS21 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Disabled (0x0UL) /*!< EVENTS[21] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS21_Enabled (0x1UL) /*!< EVENTS[21] enabled */ + +/* EVENTS22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Pos (22UL) /*!< Position of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS22_Pos) /*!< Bit mask of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Min (0x0UL) /*!< Min enumerator value of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Max (0x1UL) /*!< Max enumerator value of EVENTS22 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Disabled (0x0UL) /*!< EVENTS[22] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS22_Enabled (0x1UL) /*!< EVENTS[22] enabled */ + +/* EVENTS23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Pos (23UL) /*!< Position of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS23_Pos) /*!< Bit mask of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Min (0x0UL) /*!< Min enumerator value of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Max (0x1UL) /*!< Max enumerator value of EVENTS23 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Disabled (0x0UL) /*!< EVENTS[23] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS23_Enabled (0x1UL) /*!< EVENTS[23] enabled */ + +/* EVENTS24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Pos (24UL) /*!< Position of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS24_Pos) /*!< Bit mask of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Min (0x0UL) /*!< Min enumerator value of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Max (0x1UL) /*!< Max enumerator value of EVENTS24 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Disabled (0x0UL) /*!< EVENTS[24] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS24_Enabled (0x1UL) /*!< EVENTS[24] enabled */ + +/* EVENTS25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Pos (25UL) /*!< Position of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS25_Pos) /*!< Bit mask of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Min (0x0UL) /*!< Min enumerator value of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Max (0x1UL) /*!< Max enumerator value of EVENTS25 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Disabled (0x0UL) /*!< EVENTS[25] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS25_Enabled (0x1UL) /*!< EVENTS[25] enabled */ + +/* EVENTS26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Pos (26UL) /*!< Position of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS26_Pos) /*!< Bit mask of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Min (0x0UL) /*!< Min enumerator value of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Max (0x1UL) /*!< Max enumerator value of EVENTS26 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Disabled (0x0UL) /*!< EVENTS[26] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS26_Enabled (0x1UL) /*!< EVENTS[26] enabled */ + +/* EVENTS27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Pos (27UL) /*!< Position of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS27_Pos) /*!< Bit mask of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Min (0x0UL) /*!< Min enumerator value of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Max (0x1UL) /*!< Max enumerator value of EVENTS27 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Disabled (0x0UL) /*!< EVENTS[27] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS27_Enabled (0x1UL) /*!< EVENTS[27] enabled */ + +/* EVENTS28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Pos (28UL) /*!< Position of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS28_Pos) /*!< Bit mask of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Min (0x0UL) /*!< Min enumerator value of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Max (0x1UL) /*!< Max enumerator value of EVENTS28 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Disabled (0x0UL) /*!< EVENTS[28] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS28_Enabled (0x1UL) /*!< EVENTS[28] enabled */ + +/* EVENTS29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Pos (29UL) /*!< Position of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS29_Pos) /*!< Bit mask of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Min (0x0UL) /*!< Min enumerator value of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Max (0x1UL) /*!< Max enumerator value of EVENTS29 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Disabled (0x0UL) /*!< EVENTS[29] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS29_Enabled (0x1UL) /*!< EVENTS[29] enabled */ + +/* EVENTS30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Pos (30UL) /*!< Position of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS30_Pos) /*!< Bit mask of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Min (0x0UL) /*!< Min enumerator value of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Max (0x1UL) /*!< Max enumerator value of EVENTS30 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Disabled (0x0UL) /*!< EVENTS[30] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS30_Enabled (0x1UL) /*!< EVENTS[30] enabled */ + +/* EVENTS31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Pos (31UL) /*!< Position of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS31_Pos) /*!< Bit mask of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Min (0x0UL) /*!< Min enumerator value of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Max (0x1UL) /*!< Max enumerator value of EVENTS31 field. */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Disabled (0x0UL) /*!< EVENTS[31] disabled */ + #define VPRCSR_NORDIC_EVENTS_EVENTS31_Enabled (0x1UL) /*!< EVENTS[31] enabled */ + + +/** + * @brief PUBLISH [VPRCSR_NORDIC_PUBLISH] Enable Event Publication + */ + #define VPRCSR_NORDIC_PUBLISH (0x000007E3ul) + #define VPRCSR_NORDIC_PUBLISH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH register. */ + +/* PUBLISH0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos (0UL) /*!< Position of PUBLISH0 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos) /*!< Bit mask of PUBLISH0 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Min (0x0UL) /*!< Min enumerator value of PUBLISH0 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Max (0x1UL) /*!< Max enumerator value of PUBLISH0 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Disabled (0x0UL) /*!< Publish disabled for EVENTS[0] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Enabled (0x1UL) /*!< Publish enabled for EVENTS[0] */ + +/* PUBLISH1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos (1UL) /*!< Position of PUBLISH1 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos) /*!< Bit mask of PUBLISH1 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Min (0x0UL) /*!< Min enumerator value of PUBLISH1 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Max (0x1UL) /*!< Max enumerator value of PUBLISH1 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Disabled (0x0UL) /*!< Publish disabled for EVENTS[1] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Enabled (0x1UL) /*!< Publish enabled for EVENTS[1] */ + +/* PUBLISH2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos (2UL) /*!< Position of PUBLISH2 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos) /*!< Bit mask of PUBLISH2 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Min (0x0UL) /*!< Min enumerator value of PUBLISH2 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Max (0x1UL) /*!< Max enumerator value of PUBLISH2 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Disabled (0x0UL) /*!< Publish disabled for EVENTS[2] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Enabled (0x1UL) /*!< Publish enabled for EVENTS[2] */ + +/* PUBLISH3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos (3UL) /*!< Position of PUBLISH3 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos) /*!< Bit mask of PUBLISH3 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Min (0x0UL) /*!< Min enumerator value of PUBLISH3 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Max (0x1UL) /*!< Max enumerator value of PUBLISH3 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3] */ + +/* PUBLISH4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos (4UL) /*!< Position of PUBLISH4 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos) /*!< Bit mask of PUBLISH4 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Min (0x0UL) /*!< Min enumerator value of PUBLISH4 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Max (0x1UL) /*!< Max enumerator value of PUBLISH4 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Disabled (0x0UL) /*!< Publish disabled for EVENTS[4] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Enabled (0x1UL) /*!< Publish enabled for EVENTS[4] */ + +/* PUBLISH5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos (5UL) /*!< Position of PUBLISH5 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos) /*!< Bit mask of PUBLISH5 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Min (0x0UL) /*!< Min enumerator value of PUBLISH5 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Max (0x1UL) /*!< Max enumerator value of PUBLISH5 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Disabled (0x0UL) /*!< Publish disabled for EVENTS[5] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Enabled (0x1UL) /*!< Publish enabled for EVENTS[5] */ + +/* PUBLISH6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos (6UL) /*!< Position of PUBLISH6 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos) /*!< Bit mask of PUBLISH6 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Min (0x0UL) /*!< Min enumerator value of PUBLISH6 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Max (0x1UL) /*!< Max enumerator value of PUBLISH6 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Disabled (0x0UL) /*!< Publish disabled for EVENTS[6] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Enabled (0x1UL) /*!< Publish enabled for EVENTS[6] */ + +/* PUBLISH7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos (7UL) /*!< Position of PUBLISH7 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos) /*!< Bit mask of PUBLISH7 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Min (0x0UL) /*!< Min enumerator value of PUBLISH7 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Max (0x1UL) /*!< Max enumerator value of PUBLISH7 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Disabled (0x0UL) /*!< Publish disabled for EVENTS[7] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Enabled (0x1UL) /*!< Publish enabled for EVENTS[7] */ + +/* PUBLISH8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos (8UL) /*!< Position of PUBLISH8 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos) /*!< Bit mask of PUBLISH8 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Min (0x0UL) /*!< Min enumerator value of PUBLISH8 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Max (0x1UL) /*!< Max enumerator value of PUBLISH8 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Disabled (0x0UL) /*!< Publish disabled for EVENTS[8] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Enabled (0x1UL) /*!< Publish enabled for EVENTS[8] */ + +/* PUBLISH9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos (9UL) /*!< Position of PUBLISH9 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos) /*!< Bit mask of PUBLISH9 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Min (0x0UL) /*!< Min enumerator value of PUBLISH9 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Max (0x1UL) /*!< Max enumerator value of PUBLISH9 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Disabled (0x0UL) /*!< Publish disabled for EVENTS[9] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Enabled (0x1UL) /*!< Publish enabled for EVENTS[9] */ + +/* PUBLISH10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos (10UL) /*!< Position of PUBLISH10 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos) /*!< Bit mask of PUBLISH10 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Min (0x0UL) /*!< Min enumerator value of PUBLISH10 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Max (0x1UL) /*!< Max enumerator value of PUBLISH10 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Disabled (0x0UL) /*!< Publish disabled for EVENTS[10] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Enabled (0x1UL) /*!< Publish enabled for EVENTS[10] */ + +/* PUBLISH11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos (11UL) /*!< Position of PUBLISH11 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos) /*!< Bit mask of PUBLISH11 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Min (0x0UL) /*!< Min enumerator value of PUBLISH11 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Max (0x1UL) /*!< Max enumerator value of PUBLISH11 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Disabled (0x0UL) /*!< Publish disabled for EVENTS[11] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Enabled (0x1UL) /*!< Publish enabled for EVENTS[11] */ + +/* PUBLISH12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos (12UL) /*!< Position of PUBLISH12 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos) /*!< Bit mask of PUBLISH12 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Min (0x0UL) /*!< Min enumerator value of PUBLISH12 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Max (0x1UL) /*!< Max enumerator value of PUBLISH12 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Disabled (0x0UL) /*!< Publish disabled for EVENTS[12] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Enabled (0x1UL) /*!< Publish enabled for EVENTS[12] */ + +/* PUBLISH13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos (13UL) /*!< Position of PUBLISH13 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos) /*!< Bit mask of PUBLISH13 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Min (0x0UL) /*!< Min enumerator value of PUBLISH13 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Max (0x1UL) /*!< Max enumerator value of PUBLISH13 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Disabled (0x0UL) /*!< Publish disabled for EVENTS[13] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Enabled (0x1UL) /*!< Publish enabled for EVENTS[13] */ + +/* PUBLISH14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos (14UL) /*!< Position of PUBLISH14 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos) /*!< Bit mask of PUBLISH14 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Min (0x0UL) /*!< Min enumerator value of PUBLISH14 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Max (0x1UL) /*!< Max enumerator value of PUBLISH14 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Disabled (0x0UL) /*!< Publish disabled for EVENTS[14] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Enabled (0x1UL) /*!< Publish enabled for EVENTS[14] */ + +/* PUBLISH15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos (15UL) /*!< Position of PUBLISH15 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos) /*!< Bit mask of PUBLISH15 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Min (0x0UL) /*!< Min enumerator value of PUBLISH15 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Max (0x1UL) /*!< Max enumerator value of PUBLISH15 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Disabled (0x0UL) /*!< Publish disabled for EVENTS[15] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Enabled (0x1UL) /*!< Publish enabled for EVENTS[15] */ + +/* PUBLISH16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16] */ + +/* PUBLISH17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17] */ + +/* PUBLISH18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18] */ + +/* PUBLISH19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19] */ + +/* PUBLISH20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos (20UL) /*!< Position of PUBLISH20 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos) /*!< Bit mask of PUBLISH20 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Min (0x0UL) /*!< Min enumerator value of PUBLISH20 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Max (0x1UL) /*!< Max enumerator value of PUBLISH20 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Disabled (0x0UL) /*!< Publish disabled for EVENTS[20] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Enabled (0x1UL) /*!< Publish enabled for EVENTS[20] */ + +/* PUBLISH21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos (21UL) /*!< Position of PUBLISH21 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos) /*!< Bit mask of PUBLISH21 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Min (0x0UL) /*!< Min enumerator value of PUBLISH21 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Max (0x1UL) /*!< Max enumerator value of PUBLISH21 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Disabled (0x0UL) /*!< Publish disabled for EVENTS[21] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Enabled (0x1UL) /*!< Publish enabled for EVENTS[21] */ + +/* PUBLISH22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos (22UL) /*!< Position of PUBLISH22 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos) /*!< Bit mask of PUBLISH22 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Min (0x0UL) /*!< Min enumerator value of PUBLISH22 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Max (0x1UL) /*!< Max enumerator value of PUBLISH22 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Disabled (0x0UL) /*!< Publish disabled for EVENTS[22] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Enabled (0x1UL) /*!< Publish enabled for EVENTS[22] */ + +/* PUBLISH23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos (23UL) /*!< Position of PUBLISH23 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos) /*!< Bit mask of PUBLISH23 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Min (0x0UL) /*!< Min enumerator value of PUBLISH23 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Max (0x1UL) /*!< Max enumerator value of PUBLISH23 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Disabled (0x0UL) /*!< Publish disabled for EVENTS[23] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Enabled (0x1UL) /*!< Publish enabled for EVENTS[23] */ + +/* PUBLISH24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos (24UL) /*!< Position of PUBLISH24 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos) /*!< Bit mask of PUBLISH24 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Min (0x0UL) /*!< Min enumerator value of PUBLISH24 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Max (0x1UL) /*!< Max enumerator value of PUBLISH24 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Disabled (0x0UL) /*!< Publish disabled for EVENTS[24] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Enabled (0x1UL) /*!< Publish enabled for EVENTS[24] */ + +/* PUBLISH25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos (25UL) /*!< Position of PUBLISH25 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos) /*!< Bit mask of PUBLISH25 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Min (0x0UL) /*!< Min enumerator value of PUBLISH25 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Max (0x1UL) /*!< Max enumerator value of PUBLISH25 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Disabled (0x0UL) /*!< Publish disabled for EVENTS[25] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Enabled (0x1UL) /*!< Publish enabled for EVENTS[25] */ + +/* PUBLISH26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos (26UL) /*!< Position of PUBLISH26 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos) /*!< Bit mask of PUBLISH26 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Min (0x0UL) /*!< Min enumerator value of PUBLISH26 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Max (0x1UL) /*!< Max enumerator value of PUBLISH26 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Disabled (0x0UL) /*!< Publish disabled for EVENTS[26] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Enabled (0x1UL) /*!< Publish enabled for EVENTS[26] */ + +/* PUBLISH27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos (27UL) /*!< Position of PUBLISH27 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos) /*!< Bit mask of PUBLISH27 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Min (0x0UL) /*!< Min enumerator value of PUBLISH27 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Max (0x1UL) /*!< Max enumerator value of PUBLISH27 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Disabled (0x0UL) /*!< Publish disabled for EVENTS[27] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Enabled (0x1UL) /*!< Publish enabled for EVENTS[27] */ + +/* PUBLISH28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos (28UL) /*!< Position of PUBLISH28 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos) /*!< Bit mask of PUBLISH28 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Min (0x0UL) /*!< Min enumerator value of PUBLISH28 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Max (0x1UL) /*!< Max enumerator value of PUBLISH28 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Disabled (0x0UL) /*!< Publish disabled for EVENTS[28] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Enabled (0x1UL) /*!< Publish enabled for EVENTS[28] */ + +/* PUBLISH29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos (29UL) /*!< Position of PUBLISH29 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos) /*!< Bit mask of PUBLISH29 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Min (0x0UL) /*!< Min enumerator value of PUBLISH29 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Max (0x1UL) /*!< Max enumerator value of PUBLISH29 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Disabled (0x0UL) /*!< Publish disabled for EVENTS[29] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Enabled (0x1UL) /*!< Publish enabled for EVENTS[29] */ + +/* PUBLISH30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos (30UL) /*!< Position of PUBLISH30 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos) /*!< Bit mask of PUBLISH30 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Min (0x0UL) /*!< Min enumerator value of PUBLISH30 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Max (0x1UL) /*!< Max enumerator value of PUBLISH30 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Disabled (0x0UL) /*!< Publish disabled for EVENTS[30] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Enabled (0x1UL) /*!< Publish enabled for EVENTS[30] */ + +/* PUBLISH31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos (31UL) /*!< Position of PUBLISH31 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos) /*!< Bit mask of PUBLISH31 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Min (0x0UL) /*!< Min enumerator value of PUBLISH31 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Max (0x1UL) /*!< Max enumerator value of PUBLISH31 field. */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Disabled (0x0UL) /*!< Publish disabled for EVENTS[31] */ + #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Enabled (0x1UL) /*!< Publish enabled for EVENTS[31] */ + + +/** + * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable + */ + #define VPRCSR_NORDIC_INTEN (0x000007E4ul) + #define VPRCSR_NORDIC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* INTEN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Pos (0UL) /*!< Position of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN0_Pos) /*!< Bit mask of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Min (0x0UL) /*!< Min enumerator value of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Max (0x1UL) /*!< Max enumerator value of INTEN0 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[0] */ + #define VPRCSR_NORDIC_INTEN_INTEN0_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[0] */ + +/* INTEN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Pos (1UL) /*!< Position of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN1_Pos) /*!< Bit mask of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Min (0x0UL) /*!< Min enumerator value of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Max (0x1UL) /*!< Max enumerator value of INTEN1 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[1] */ + #define VPRCSR_NORDIC_INTEN_INTEN1_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[1] */ + +/* INTEN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Pos (2UL) /*!< Position of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN2_Pos) /*!< Bit mask of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Min (0x0UL) /*!< Min enumerator value of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Max (0x1UL) /*!< Max enumerator value of INTEN2 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[2] */ + #define VPRCSR_NORDIC_INTEN_INTEN2_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[2] */ + +/* INTEN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Pos (3UL) /*!< Position of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN3_Pos) /*!< Bit mask of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Min (0x0UL) /*!< Min enumerator value of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Max (0x1UL) /*!< Max enumerator value of INTEN3 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[3] */ + #define VPRCSR_NORDIC_INTEN_INTEN3_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[3] */ + +/* INTEN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Pos (4UL) /*!< Position of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN4_Pos) /*!< Bit mask of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Min (0x0UL) /*!< Min enumerator value of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Max (0x1UL) /*!< Max enumerator value of INTEN4 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[4] */ + #define VPRCSR_NORDIC_INTEN_INTEN4_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[4] */ + +/* INTEN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Pos (5UL) /*!< Position of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN5_Pos) /*!< Bit mask of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Min (0x0UL) /*!< Min enumerator value of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Max (0x1UL) /*!< Max enumerator value of INTEN5 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[5] */ + #define VPRCSR_NORDIC_INTEN_INTEN5_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[5] */ + +/* INTEN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Pos (6UL) /*!< Position of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN6_Pos) /*!< Bit mask of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Min (0x0UL) /*!< Min enumerator value of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Max (0x1UL) /*!< Max enumerator value of INTEN6 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[6] */ + #define VPRCSR_NORDIC_INTEN_INTEN6_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[6] */ + +/* INTEN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Pos (7UL) /*!< Position of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN7_Pos) /*!< Bit mask of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Min (0x0UL) /*!< Min enumerator value of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Max (0x1UL) /*!< Max enumerator value of INTEN7 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[7] */ + #define VPRCSR_NORDIC_INTEN_INTEN7_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[7] */ + +/* INTEN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Pos (8UL) /*!< Position of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN8_Pos) /*!< Bit mask of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Min (0x0UL) /*!< Min enumerator value of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Max (0x1UL) /*!< Max enumerator value of INTEN8 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[8] */ + #define VPRCSR_NORDIC_INTEN_INTEN8_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[8] */ + +/* INTEN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Pos (9UL) /*!< Position of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN9_Pos) /*!< Bit mask of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Min (0x0UL) /*!< Min enumerator value of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Max (0x1UL) /*!< Max enumerator value of INTEN9 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[9] */ + #define VPRCSR_NORDIC_INTEN_INTEN9_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[9] */ + +/* INTEN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Pos (10UL) /*!< Position of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN10_Pos) /*!< Bit mask of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Min (0x0UL) /*!< Min enumerator value of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Max (0x1UL) /*!< Max enumerator value of INTEN10 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[10] */ + #define VPRCSR_NORDIC_INTEN_INTEN10_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[10] */ + +/* INTEN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Pos (11UL) /*!< Position of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN11_Pos) /*!< Bit mask of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Min (0x0UL) /*!< Min enumerator value of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Max (0x1UL) /*!< Max enumerator value of INTEN11 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[11] */ + #define VPRCSR_NORDIC_INTEN_INTEN11_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[11] */ + +/* INTEN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Pos (12UL) /*!< Position of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN12_Pos) /*!< Bit mask of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Min (0x0UL) /*!< Min enumerator value of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Max (0x1UL) /*!< Max enumerator value of INTEN12 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[12] */ + #define VPRCSR_NORDIC_INTEN_INTEN12_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[12] */ + +/* INTEN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Pos (13UL) /*!< Position of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN13_Pos) /*!< Bit mask of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Min (0x0UL) /*!< Min enumerator value of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Max (0x1UL) /*!< Max enumerator value of INTEN13 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[13] */ + #define VPRCSR_NORDIC_INTEN_INTEN13_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[13] */ + +/* INTEN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Pos (14UL) /*!< Position of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN14_Pos) /*!< Bit mask of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Min (0x0UL) /*!< Min enumerator value of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Max (0x1UL) /*!< Max enumerator value of INTEN14 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[14] */ + #define VPRCSR_NORDIC_INTEN_INTEN14_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[14] */ + +/* INTEN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Pos (15UL) /*!< Position of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN15_Pos) /*!< Bit mask of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Min (0x0UL) /*!< Min enumerator value of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Max (0x1UL) /*!< Max enumerator value of INTEN15 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[15] */ + #define VPRCSR_NORDIC_INTEN_INTEN15_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[15] */ + +/* INTEN16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Pos (16UL) /*!< Position of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN16_Pos) /*!< Bit mask of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Min (0x0UL) /*!< Min enumerator value of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Max (0x1UL) /*!< Max enumerator value of INTEN16 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[16] */ + #define VPRCSR_NORDIC_INTEN_INTEN16_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[16] */ + +/* INTEN17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Pos (17UL) /*!< Position of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN17_Pos) /*!< Bit mask of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Min (0x0UL) /*!< Min enumerator value of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Max (0x1UL) /*!< Max enumerator value of INTEN17 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[17] */ + #define VPRCSR_NORDIC_INTEN_INTEN17_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[17] */ + +/* INTEN18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Pos (18UL) /*!< Position of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN18_Pos) /*!< Bit mask of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Min (0x0UL) /*!< Min enumerator value of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Max (0x1UL) /*!< Max enumerator value of INTEN18 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[18] */ + #define VPRCSR_NORDIC_INTEN_INTEN18_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[18] */ + +/* INTEN19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Pos (19UL) /*!< Position of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN19_Pos) /*!< Bit mask of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Min (0x0UL) /*!< Min enumerator value of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Max (0x1UL) /*!< Max enumerator value of INTEN19 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[19] */ + #define VPRCSR_NORDIC_INTEN_INTEN19_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[19] */ + +/* INTEN20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Pos (20UL) /*!< Position of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN20_Pos) /*!< Bit mask of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Min (0x0UL) /*!< Min enumerator value of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Max (0x1UL) /*!< Max enumerator value of INTEN20 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[20] */ + #define VPRCSR_NORDIC_INTEN_INTEN20_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[20] */ + +/* INTEN21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Pos (21UL) /*!< Position of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN21_Pos) /*!< Bit mask of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Min (0x0UL) /*!< Min enumerator value of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Max (0x1UL) /*!< Max enumerator value of INTEN21 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[21] */ + #define VPRCSR_NORDIC_INTEN_INTEN21_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[21] */ + +/* INTEN22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Pos (22UL) /*!< Position of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN22_Pos) /*!< Bit mask of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Min (0x0UL) /*!< Min enumerator value of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Max (0x1UL) /*!< Max enumerator value of INTEN22 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[22] */ + #define VPRCSR_NORDIC_INTEN_INTEN22_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[22] */ + +/* INTEN23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Pos (23UL) /*!< Position of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN23_Pos) /*!< Bit mask of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Min (0x0UL) /*!< Min enumerator value of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Max (0x1UL) /*!< Max enumerator value of INTEN23 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[23] */ + #define VPRCSR_NORDIC_INTEN_INTEN23_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[23] */ + +/* INTEN24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Pos (24UL) /*!< Position of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN24_Pos) /*!< Bit mask of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Min (0x0UL) /*!< Min enumerator value of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Max (0x1UL) /*!< Max enumerator value of INTEN24 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[24] */ + #define VPRCSR_NORDIC_INTEN_INTEN24_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[24] */ + +/* INTEN25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Pos (25UL) /*!< Position of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN25_Pos) /*!< Bit mask of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Min (0x0UL) /*!< Min enumerator value of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Max (0x1UL) /*!< Max enumerator value of INTEN25 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[25] */ + #define VPRCSR_NORDIC_INTEN_INTEN25_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[25] */ + +/* INTEN26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Pos (26UL) /*!< Position of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN26_Pos) /*!< Bit mask of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Min (0x0UL) /*!< Min enumerator value of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Max (0x1UL) /*!< Max enumerator value of INTEN26 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[26] */ + #define VPRCSR_NORDIC_INTEN_INTEN26_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[26] */ + +/* INTEN27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Pos (27UL) /*!< Position of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN27_Pos) /*!< Bit mask of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Min (0x0UL) /*!< Min enumerator value of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Max (0x1UL) /*!< Max enumerator value of INTEN27 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[27] */ + #define VPRCSR_NORDIC_INTEN_INTEN27_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[27] */ + +/* INTEN28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Pos (28UL) /*!< Position of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN28_Pos) /*!< Bit mask of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Min (0x0UL) /*!< Min enumerator value of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Max (0x1UL) /*!< Max enumerator value of INTEN28 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[28] */ + #define VPRCSR_NORDIC_INTEN_INTEN28_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[28] */ + +/* INTEN29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Pos (29UL) /*!< Position of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN29_Pos) /*!< Bit mask of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Min (0x0UL) /*!< Min enumerator value of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Max (0x1UL) /*!< Max enumerator value of INTEN29 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[29] */ + #define VPRCSR_NORDIC_INTEN_INTEN29_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[29] */ + +/* INTEN30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Pos (30UL) /*!< Position of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN30_Pos) /*!< Bit mask of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Min (0x0UL) /*!< Min enumerator value of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Max (0x1UL) /*!< Max enumerator value of INTEN30 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[30] */ + #define VPRCSR_NORDIC_INTEN_INTEN30_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[30] */ + +/* INTEN31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Pos (31UL) /*!< Position of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN31_Pos) /*!< Bit mask of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Min (0x0UL) /*!< Min enumerator value of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Max (0x1UL) /*!< Max enumerator value of INTEN31 field. */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[31] */ + #define VPRCSR_NORDIC_INTEN_INTEN31_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[31] */ + + +/** + * @brief EVENTSB [VPRCSR_NORDIC_EVENTSB] Buffered DPPI Events + */ + #define VPRCSR_NORDIC_EVENTSB (0x000007E5ul) + #define VPRCSR_NORDIC_EVENTSB_ResetValue (0x00000000UL) /*!< Reset value of EVENTSB register. */ + +/* EVENTSB0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos (0UL) /*!< Position of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos) /*!< Bit mask of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Min (0x0UL) /*!< Min enumerator value of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Max (0x1UL) /*!< Max enumerator value of EVENTSB0 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Disabled (0x0UL) /*!< EVENTSB[0] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Enabled (0x1UL) /*!< EVENTSB[0] enabled */ + +/* EVENTSB1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos (1UL) /*!< Position of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos) /*!< Bit mask of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Min (0x0UL) /*!< Min enumerator value of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Max (0x1UL) /*!< Max enumerator value of EVENTSB1 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Disabled (0x0UL) /*!< EVENTSB[1] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Enabled (0x1UL) /*!< EVENTSB[1] enabled */ + +/* EVENTSB2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos (2UL) /*!< Position of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos) /*!< Bit mask of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Min (0x0UL) /*!< Min enumerator value of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Max (0x1UL) /*!< Max enumerator value of EVENTSB2 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Disabled (0x0UL) /*!< EVENTSB[2] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Enabled (0x1UL) /*!< EVENTSB[2] enabled */ + +/* EVENTSB3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos (3UL) /*!< Position of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos) /*!< Bit mask of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Min (0x0UL) /*!< Min enumerator value of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Max (0x1UL) /*!< Max enumerator value of EVENTSB3 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Disabled (0x0UL) /*!< EVENTSB[3] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Enabled (0x1UL) /*!< EVENTSB[3] enabled */ + +/* EVENTSB4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos (4UL) /*!< Position of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos) /*!< Bit mask of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Min (0x0UL) /*!< Min enumerator value of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Max (0x1UL) /*!< Max enumerator value of EVENTSB4 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Disabled (0x0UL) /*!< EVENTSB[4] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Enabled (0x1UL) /*!< EVENTSB[4] enabled */ + +/* EVENTSB5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos (5UL) /*!< Position of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos) /*!< Bit mask of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Min (0x0UL) /*!< Min enumerator value of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Max (0x1UL) /*!< Max enumerator value of EVENTSB5 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Disabled (0x0UL) /*!< EVENTSB[5] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Enabled (0x1UL) /*!< EVENTSB[5] enabled */ + +/* EVENTSB6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos (6UL) /*!< Position of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos) /*!< Bit mask of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Min (0x0UL) /*!< Min enumerator value of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Max (0x1UL) /*!< Max enumerator value of EVENTSB6 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Disabled (0x0UL) /*!< EVENTSB[6] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Enabled (0x1UL) /*!< EVENTSB[6] enabled */ + +/* EVENTSB7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos (7UL) /*!< Position of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos) /*!< Bit mask of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Min (0x0UL) /*!< Min enumerator value of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Max (0x1UL) /*!< Max enumerator value of EVENTSB7 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Disabled (0x0UL) /*!< EVENTSB[7] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Enabled (0x1UL) /*!< EVENTSB[7] enabled */ + +/* EVENTSB8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos (8UL) /*!< Position of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos) /*!< Bit mask of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Min (0x0UL) /*!< Min enumerator value of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Max (0x1UL) /*!< Max enumerator value of EVENTSB8 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Disabled (0x0UL) /*!< EVENTSB[8] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Enabled (0x1UL) /*!< EVENTSB[8] enabled */ + +/* EVENTSB9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos (9UL) /*!< Position of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos) /*!< Bit mask of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Min (0x0UL) /*!< Min enumerator value of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Max (0x1UL) /*!< Max enumerator value of EVENTSB9 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Disabled (0x0UL) /*!< EVENTSB[9] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Enabled (0x1UL) /*!< EVENTSB[9] enabled */ + +/* EVENTSB10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos (10UL) /*!< Position of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos) /*!< Bit mask of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Min (0x0UL) /*!< Min enumerator value of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Max (0x1UL) /*!< Max enumerator value of EVENTSB10 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Disabled (0x0UL) /*!< EVENTSB[10] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Enabled (0x1UL) /*!< EVENTSB[10] enabled */ + +/* EVENTSB11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos (11UL) /*!< Position of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos) /*!< Bit mask of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Min (0x0UL) /*!< Min enumerator value of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Max (0x1UL) /*!< Max enumerator value of EVENTSB11 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Disabled (0x0UL) /*!< EVENTSB[11] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Enabled (0x1UL) /*!< EVENTSB[11] enabled */ + +/* EVENTSB12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos (12UL) /*!< Position of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos) /*!< Bit mask of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Min (0x0UL) /*!< Min enumerator value of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Max (0x1UL) /*!< Max enumerator value of EVENTSB12 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Disabled (0x0UL) /*!< EVENTSB[12] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Enabled (0x1UL) /*!< EVENTSB[12] enabled */ + +/* EVENTSB13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos (13UL) /*!< Position of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos) /*!< Bit mask of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Min (0x0UL) /*!< Min enumerator value of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Max (0x1UL) /*!< Max enumerator value of EVENTSB13 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Disabled (0x0UL) /*!< EVENTSB[13] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Enabled (0x1UL) /*!< EVENTSB[13] enabled */ + +/* EVENTSB14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos (14UL) /*!< Position of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos) /*!< Bit mask of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Min (0x0UL) /*!< Min enumerator value of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Max (0x1UL) /*!< Max enumerator value of EVENTSB14 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Disabled (0x0UL) /*!< EVENTSB[14] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Enabled (0x1UL) /*!< EVENTSB[14] enabled */ + +/* EVENTSB15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos (15UL) /*!< Position of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos) /*!< Bit mask of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Min (0x0UL) /*!< Min enumerator value of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Max (0x1UL) /*!< Max enumerator value of EVENTSB15 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Disabled (0x0UL) /*!< EVENTSB[15] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Enabled (0x1UL) /*!< EVENTSB[15] enabled */ + +/* EVENTSB16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos (16UL) /*!< Position of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos) /*!< Bit mask of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Min (0x0UL) /*!< Min enumerator value of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Max (0x1UL) /*!< Max enumerator value of EVENTSB16 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Disabled (0x0UL) /*!< EVENTSB[16] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Enabled (0x1UL) /*!< EVENTSB[16] enabled */ + +/* EVENTSB17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos (17UL) /*!< Position of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos) /*!< Bit mask of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Min (0x0UL) /*!< Min enumerator value of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Max (0x1UL) /*!< Max enumerator value of EVENTSB17 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Disabled (0x0UL) /*!< EVENTSB[17] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Enabled (0x1UL) /*!< EVENTSB[17] enabled */ + +/* EVENTSB18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos (18UL) /*!< Position of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos) /*!< Bit mask of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Min (0x0UL) /*!< Min enumerator value of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Max (0x1UL) /*!< Max enumerator value of EVENTSB18 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Disabled (0x0UL) /*!< EVENTSB[18] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Enabled (0x1UL) /*!< EVENTSB[18] enabled */ + +/* EVENTSB19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos (19UL) /*!< Position of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos) /*!< Bit mask of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Min (0x0UL) /*!< Min enumerator value of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Max (0x1UL) /*!< Max enumerator value of EVENTSB19 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Disabled (0x0UL) /*!< EVENTSB[19] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Enabled (0x1UL) /*!< EVENTSB[19] enabled */ + +/* EVENTSB20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos (20UL) /*!< Position of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos) /*!< Bit mask of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Min (0x0UL) /*!< Min enumerator value of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Max (0x1UL) /*!< Max enumerator value of EVENTSB20 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Disabled (0x0UL) /*!< EVENTSB[20] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Enabled (0x1UL) /*!< EVENTSB[20] enabled */ + +/* EVENTSB21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos (21UL) /*!< Position of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos) /*!< Bit mask of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Min (0x0UL) /*!< Min enumerator value of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Max (0x1UL) /*!< Max enumerator value of EVENTSB21 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Disabled (0x0UL) /*!< EVENTSB[21] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Enabled (0x1UL) /*!< EVENTSB[21] enabled */ + +/* EVENTSB22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos (22UL) /*!< Position of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos) /*!< Bit mask of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Min (0x0UL) /*!< Min enumerator value of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Max (0x1UL) /*!< Max enumerator value of EVENTSB22 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Disabled (0x0UL) /*!< EVENTSB[22] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Enabled (0x1UL) /*!< EVENTSB[22] enabled */ + +/* EVENTSB23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos (23UL) /*!< Position of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos) /*!< Bit mask of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Min (0x0UL) /*!< Min enumerator value of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Max (0x1UL) /*!< Max enumerator value of EVENTSB23 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Disabled (0x0UL) /*!< EVENTSB[23] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Enabled (0x1UL) /*!< EVENTSB[23] enabled */ + +/* EVENTSB24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos (24UL) /*!< Position of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos) /*!< Bit mask of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Min (0x0UL) /*!< Min enumerator value of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Max (0x1UL) /*!< Max enumerator value of EVENTSB24 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Disabled (0x0UL) /*!< EVENTSB[24] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Enabled (0x1UL) /*!< EVENTSB[24] enabled */ + +/* EVENTSB25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos (25UL) /*!< Position of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos) /*!< Bit mask of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Min (0x0UL) /*!< Min enumerator value of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Max (0x1UL) /*!< Max enumerator value of EVENTSB25 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Disabled (0x0UL) /*!< EVENTSB[25] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Enabled (0x1UL) /*!< EVENTSB[25] enabled */ + +/* EVENTSB26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos (26UL) /*!< Position of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos) /*!< Bit mask of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Min (0x0UL) /*!< Min enumerator value of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Max (0x1UL) /*!< Max enumerator value of EVENTSB26 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Disabled (0x0UL) /*!< EVENTSB[26] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Enabled (0x1UL) /*!< EVENTSB[26] enabled */ + +/* EVENTSB27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos (27UL) /*!< Position of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos) /*!< Bit mask of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Min (0x0UL) /*!< Min enumerator value of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Max (0x1UL) /*!< Max enumerator value of EVENTSB27 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Disabled (0x0UL) /*!< EVENTSB[27] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Enabled (0x1UL) /*!< EVENTSB[27] enabled */ + +/* EVENTSB28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos (28UL) /*!< Position of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos) /*!< Bit mask of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Min (0x0UL) /*!< Min enumerator value of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Max (0x1UL) /*!< Max enumerator value of EVENTSB28 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Disabled (0x0UL) /*!< EVENTSB[28] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Enabled (0x1UL) /*!< EVENTSB[28] enabled */ + +/* EVENTSB29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos (29UL) /*!< Position of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos) /*!< Bit mask of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Min (0x0UL) /*!< Min enumerator value of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Max (0x1UL) /*!< Max enumerator value of EVENTSB29 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Disabled (0x0UL) /*!< EVENTSB[29] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Enabled (0x1UL) /*!< EVENTSB[29] enabled */ + +/* EVENTSB30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos (30UL) /*!< Position of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos) /*!< Bit mask of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Min (0x0UL) /*!< Min enumerator value of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Max (0x1UL) /*!< Max enumerator value of EVENTSB30 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Disabled (0x0UL) /*!< EVENTSB[30] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Enabled (0x1UL) /*!< EVENTSB[30] enabled */ + +/* EVENTSB31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos (31UL) /*!< Position of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos) /*!< Bit mask of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Min (0x0UL) /*!< Min enumerator value of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Max (0x1UL) /*!< Max enumerator value of EVENTSB31 field. */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Disabled (0x0UL) /*!< EVENTSB[31] disabled */ + #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Enabled (0x1UL) /*!< EVENTSB[31] enabled */ + + +/** + * @brief EVENTSBS [VPRCSR_NORDIC_EVENTSBS] EVENTSB Dirty Status + */ + #define VPRCSR_NORDIC_EVENTSBS (0x000007E6ul) + #define VPRCSR_NORDIC_EVENTSBS_ResetValue (0x00000000UL) /*!< Reset value of EVENTSBS register. */ + +/* EVENTSB @Bits 0..31 : Write to EVENTSB (if not dirty) */ + #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos (0UL) /*!< Position of EVENTSB field. */ + #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos) /*!< Bit mask of EVENTSB + field.*/ + +/* DIRTYBIT @Bit 0 : Read EVENTSB Dirty status */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUT [VPRCSR_NORDIC_OUT] GPIO Output value. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_OUT (0x00000BC0ul) + #define VPRCSR_NORDIC_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUT_PIN0_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN0_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUT_PIN1_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN1_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUT_PIN2_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN2_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUT_PIN3_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN3_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUT_PIN4_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN4_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUT_PIN5_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN5_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUT_PIN6_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN6_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUT_PIN7_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN7_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUT_PIN8_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN8_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUT_PIN9_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN9_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUT_PIN10_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN10_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUT_PIN11_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN11_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUT_PIN12_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN12_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUT_PIN13_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN13_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUT_PIN14_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN14_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUT_PIN15_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUT_PIN15_HIGH (0x1UL) /*!< Pin driver is high */ + + +/** + * @brief DIR [VPRCSR_NORDIC_DIR] GPIO pin Direction. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_DIR (0x00000BC1ul) + #define VPRCSR_NORDIC_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIR_PIN0_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN0_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIR_PIN1_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN1_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIR_PIN2_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN2_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIR_PIN3_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN3_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIR_PIN4_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN4_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIR_PIN5_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN5_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIR_PIN6_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN6_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIR_PIN7_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN7_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIR_PIN8_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN8_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIR_PIN9_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN9_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIR_PIN10_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN10_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIR_PIN11_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN11_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIR_PIN12_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN12_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIR_PIN13_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN13_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIR_PIN14_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN14_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIR_PIN15_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIR_PIN15_OUTPUT (0x1UL) /*!< Pin is set as output */ + + +/** + * @brief IN [VPRCSR_NORDIC_IN] GPIO Input. Real Time Peripherals VIO. + */ + #define VPRCSR_NORDIC_IN (0x00000BC2ul) + #define VPRCSR_NORDIC_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_IN_PIN0_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN0_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_IN_PIN1_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN1_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_IN_PIN2_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN2_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_IN_PIN3_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN3_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_IN_PIN4_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN4_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_IN_PIN5_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN5_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_IN_PIN6_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN6_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_IN_PIN7_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN7_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_IN_PIN8_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN8_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_IN_PIN9_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN9_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_IN_PIN10_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN10_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_IN_PIN11_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN11_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_IN_PIN12_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN12_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_IN_PIN13_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN13_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_IN_PIN14_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN14_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_IN_PIN15_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_IN_PIN15_HIGH (0x1UL) /*!< Pin is High */ + + +/** + * @brief INMODE [VPRCSR_NORDIC_INMODE] Input Mode + */ + #define VPRCSR_NORDIC_INMODE (0x00000BC3ul) + #define VPRCSR_NORDIC_INMODE_ResetValue (0x00000000UL) /*!< Reset value of INMODE register. */ + +/* MODE @Bits 0..1 : Input Mode */ + #define VPRCSR_NORDIC_INMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODE_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_INMODE_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_INMODE_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event */ + + +/** + * @brief OUTB [VPRCSR_NORDIC_OUTB] Buffered GPIO Output + */ + #define VPRCSR_NORDIC_OUTB (0x00000BC4ul) + #define VPRCSR_NORDIC_OUTB_ResetValue (0x00000000UL) /*!< Reset value of OUTB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTB_PIN0_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN0_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTB_PIN1_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN1_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTB_PIN2_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN2_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTB_PIN3_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN3_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTB_PIN4_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN4_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTB_PIN5_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN5_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTB_PIN6_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN6_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTB_PIN7_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN7_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTB_PIN8_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN8_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTB_PIN9_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN9_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTB_PIN10_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN10_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTB_PIN11_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN11_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTB_PIN12_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN12_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTB_PIN13_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN13_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTB_PIN14_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN14_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTB_PIN15_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN15_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN16 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN16_Pos) /*!< Bit mask of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Min (0x0UL) /*!< Min enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_Max (0x1UL) /*!< Max enumerator value of PIN16 field. */ + #define VPRCSR_NORDIC_OUTB_PIN16_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN16_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN17 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN17_Pos) /*!< Bit mask of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Min (0x0UL) /*!< Min enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_Max (0x1UL) /*!< Max enumerator value of PIN17 field. */ + #define VPRCSR_NORDIC_OUTB_PIN17_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN17_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN18 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN18_Pos) /*!< Bit mask of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Min (0x0UL) /*!< Min enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_Max (0x1UL) /*!< Max enumerator value of PIN18 field. */ + #define VPRCSR_NORDIC_OUTB_PIN18_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN18_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN19 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN19_Pos) /*!< Bit mask of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Min (0x0UL) /*!< Min enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_Max (0x1UL) /*!< Max enumerator value of PIN19 field. */ + #define VPRCSR_NORDIC_OUTB_PIN19_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN19_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN20 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN20_Pos) /*!< Bit mask of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Min (0x0UL) /*!< Min enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_Max (0x1UL) /*!< Max enumerator value of PIN20 field. */ + #define VPRCSR_NORDIC_OUTB_PIN20_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN20_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN21 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN21_Pos) /*!< Bit mask of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Min (0x0UL) /*!< Min enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_Max (0x1UL) /*!< Max enumerator value of PIN21 field. */ + #define VPRCSR_NORDIC_OUTB_PIN21_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN21_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN22 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN22_Pos) /*!< Bit mask of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Min (0x0UL) /*!< Min enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_Max (0x1UL) /*!< Max enumerator value of PIN22 field. */ + #define VPRCSR_NORDIC_OUTB_PIN22_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN22_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN23 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN23_Pos) /*!< Bit mask of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Min (0x0UL) /*!< Min enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_Max (0x1UL) /*!< Max enumerator value of PIN23 field. */ + #define VPRCSR_NORDIC_OUTB_PIN23_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN23_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN24 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN24_Pos) /*!< Bit mask of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Min (0x0UL) /*!< Min enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_Max (0x1UL) /*!< Max enumerator value of PIN24 field. */ + #define VPRCSR_NORDIC_OUTB_PIN24_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN24_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN25 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN25_Pos) /*!< Bit mask of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Min (0x0UL) /*!< Min enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_Max (0x1UL) /*!< Max enumerator value of PIN25 field. */ + #define VPRCSR_NORDIC_OUTB_PIN25_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN25_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN26 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN26_Pos) /*!< Bit mask of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Min (0x0UL) /*!< Min enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_Max (0x1UL) /*!< Max enumerator value of PIN26 field. */ + #define VPRCSR_NORDIC_OUTB_PIN26_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN26_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN27 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN27_Pos) /*!< Bit mask of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Min (0x0UL) /*!< Min enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_Max (0x1UL) /*!< Max enumerator value of PIN27 field. */ + #define VPRCSR_NORDIC_OUTB_PIN27_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN27_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN28 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN28_Pos) /*!< Bit mask of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Min (0x0UL) /*!< Min enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_Max (0x1UL) /*!< Max enumerator value of PIN28 field. */ + #define VPRCSR_NORDIC_OUTB_PIN28_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN28_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN29 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN29_Pos) /*!< Bit mask of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Min (0x0UL) /*!< Min enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_Max (0x1UL) /*!< Max enumerator value of PIN29 field. */ + #define VPRCSR_NORDIC_OUTB_PIN29_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN29_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN30 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN30_Pos) /*!< Bit mask of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Min (0x0UL) /*!< Min enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_Max (0x1UL) /*!< Max enumerator value of PIN30 field. */ + #define VPRCSR_NORDIC_OUTB_PIN30_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN30_HIGH (0x1UL) /*!< Pin driver is high */ + +/* PIN31 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTB_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN31_Pos) /*!< Bit mask of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Min (0x0UL) /*!< Min enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_Max (0x1UL) /*!< Max enumerator value of PIN31 field. */ + #define VPRCSR_NORDIC_OUTB_PIN31_LOW (0x0UL) /*!< Pin driver is low */ + #define VPRCSR_NORDIC_OUTB_PIN31_HIGH (0x1UL) /*!< Pin driver is high */ + + +/** + * @brief DIRB [VPRCSR_NORDIC_DIRB] Buffered GPIO pin Direction + */ + #define VPRCSR_NORDIC_DIRB (0x00000BC5ul) + #define VPRCSR_NORDIC_DIRB_ResetValue (0x00000000UL) /*!< Reset value of DIRB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRB_PIN0_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN0_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRB_PIN1_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN1_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRB_PIN2_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN2_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRB_PIN3_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN3_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRB_PIN4_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN4_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRB_PIN5_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN5_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRB_PIN6_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN6_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRB_PIN7_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN7_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRB_PIN8_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN8_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRB_PIN9_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN9_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRB_PIN10_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN10_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRB_PIN11_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN11_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRB_PIN12_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN12_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRB_PIN13_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN13_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRB_PIN14_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN14_OUTPUT (0x1UL) /*!< Pin is set as output */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRB_PIN15_INPUT (0x0UL) /*!< Pin is set as input */ + #define VPRCSR_NORDIC_DIRB_PIN15_OUTPUT (0x1UL) /*!< Pin is set as output */ + + +/** + * @brief DIROUT [VPRCSR_NORDIC_DIROUT] DIR and OUT concatenation + */ + #define VPRCSR_NORDIC_DIROUT (0x00000BC6ul) + #define VPRCSR_NORDIC_DIROUT_ResetValue (0x00000000UL) /*!< Reset value of DIROUT register. */ + +/* OUT @Bits 0..15 : GPIO Output */ + #define VPRCSR_NORDIC_DIROUT_OUT_Pos (0UL) /*!< Position of OUT field. */ + #define VPRCSR_NORDIC_DIROUT_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_OUT_Pos) /*!< Bit mask of OUT field. */ + +/* DIR @Bits 16..31 : GPIO pin Direction */ + #define VPRCSR_NORDIC_DIROUT_DIR_Pos (16UL) /*!< Position of DIR field. */ + #define VPRCSR_NORDIC_DIROUT_DIR_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_DIR_Pos) /*!< Bit mask of DIR field. */ + + +/** + * @brief DIROUTB [VPRCSR_NORDIC_DIROUTB] Concatenation of DIRB and OUTB + */ + #define VPRCSR_NORDIC_DIROUTB (0x00000BC7ul) + #define VPRCSR_NORDIC_DIROUTB_ResetValue (0x00000000UL) /*!< Reset value of DIROUTB register. */ + +/* OUTB @Bits 0..15 : Buffered GPIO Output */ + #define VPRCSR_NORDIC_DIROUTB_OUTB_Pos (0UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_DIROUTB_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_OUTB_Pos) /*!< Bit mask of OUTB field. */ + +/* DIRB @Bits 16..31 : Buffered GPIO pin Direction */ + #define VPRCSR_NORDIC_DIROUTB_DIRB_Pos (16UL) /*!< Position of DIRB field. */ + #define VPRCSR_NORDIC_DIROUTB_DIRB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_DIRB_Pos) /*!< Bit mask of DIRB field. */ + + +/** + * @brief OUTBRB [VPRCSR_NORDIC_OUTBRB] Byte reversed register OUTB + */ + #define VPRCSR_NORDIC_OUTBRB (0x00000BC8ul) + #define VPRCSR_NORDIC_OUTBRB_ResetValue (0x00000000UL) /*!< Reset value of OUTBRB register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRB_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_OUTBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief OUTBRW [VPRCSR_NORDIC_OUTBRW] Word reversed register OUTB + */ + #define VPRCSR_NORDIC_OUTBRW (0x00000BC9ul) + #define VPRCSR_NORDIC_OUTBRW_ResetValue (0x00000000UL) /*!< Reset value of OUTBRW register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRW_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_OUTBRW_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief INBRB [VPRCSR_NORDIC_INBRB] Byte reversed register INB + */ + #define VPRCSR_NORDIC_INBRB (0x00000BCAul) + #define VPRCSR_NORDIC_INBRB_ResetValue (0x00000000UL) /*!< Reset value of INBRB register. */ + +/* VAL @Bits 0..31 : (unspecified) */ + #define VPRCSR_NORDIC_INBRB_VAL_Pos (0UL) /*!< Position of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_INBRB_VAL_Pos) /*!< Bit mask of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field. */ + #define VPRCSR_NORDIC_INBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field. */ + + +/** + * @brief SHIFTCTRLB [VPRCSR_NORDIC_SHIFTCTRLB] Buffered IO shift control + */ + #define VPRCSR_NORDIC_SHIFTCTRLB (0x00000BCBul) + #define VPRCSR_NORDIC_SHIFTCTRLB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCTRLB register. */ + +/* Field group SHIFTCNTB : (unspecified) */ +/* VALUE @Bits 0..5 : Alias to SHIFTCNTB.VALUE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos) /*!< Bit mask + of VALUE field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Max (0x20UL) /*!< Max size of VALUE field. */ + +/* End field group SHIFTCNTB. */ + +/* Field group OUTMODEB : (unspecified) */ +/* MODE @Bits 8..10 : Alias to OUTMODEB.MODE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos (8UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos) /*!< Bit mask of + MODE field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock + line*/ + +/* FRAMEWIDTH @Bits 12..16 : Alias to OUTMODEB.FRAMEWIDTH register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos (12UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos) /*!< + Bit mask of FRAMEWIDTH field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + +/* End field group OUTMODEB. */ + +/* Field group INMODEB : (unspecified) */ +/* MODE @Bits 20..21 : Alias to INMODEB.MODE register */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos (20UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos) /*!< Bit mask of MODE + field.*/ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event */ + +/* End field group INMODEB. */ + + +/** + * @brief SHIFTCNTIN [VPRCSR_NORDIC_SHIFTCNTIN] Number of frames to be shifted from INB before new data is required + */ + #define VPRCSR_NORDIC_SHIFTCNTIN (0x00000BCDul) + #define VPRCSR_NORDIC_SHIFTCNTIN_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTIN register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Max (0x3FUL) /*!< Max size of VALUE field. */ + + +/** + * @brief SHIFTCNTOUT [VPRCSR_NORDIC_SHIFTCNTOUT] Number of frames to be shifted to OUTB before new data is required + */ + #define VPRCSR_NORDIC_SHIFTCNTOUT (0x00000BCEul) + #define VPRCSR_NORDIC_SHIFTCNTOUT_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTOUT register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Max (0x3FUL) /*!< Max size of VALUE field. */ + + +/** + * @brief SHIFTCNTB [VPRCSR_NORDIC_SHIFTCNTB] Buffered SHIFTCNTOUT register + */ + #define VPRCSR_NORDIC_SHIFTCNTB (0x00000BCFul) + #define VPRCSR_NORDIC_SHIFTCNTB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTB register. */ + +/* VALUE @Bits 0..5 : Value */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos) /*!< Bit mask of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field. */ + #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Max (0x20UL) /*!< Max size of VALUE field. */ + + +/** + * @brief OUTTGL [VPRCSR_NORDIC_OUTTGL] GPIO Output Toggle + */ + #define VPRCSR_NORDIC_OUTTGL (0x00000BD0ul) + #define VPRCSR_NORDIC_OUTTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIRTGL [VPRCSR_NORDIC_DIRTGL] GPIO pin Direction Toggle + */ + #define VPRCSR_NORDIC_DIRTGL (0x00000BD1ul) + #define VPRCSR_NORDIC_DIRTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBTGL [VPRCSR_NORDIC_OUTBTGL] Buffered GPIO Output Toggle + */ + #define VPRCSR_NORDIC_OUTBTGL (0x00000BD2ul) + #define VPRCSR_NORDIC_OUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIRBTGL [VPRCSR_NORDIC_DIRBTGL] Buffered GPIO pin Direction Toggle + */ + #define VPRCSR_NORDIC_DIRBTGL (0x00000BD3ul) + #define VPRCSR_NORDIC_DIRBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRBTGL register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIRBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIROUTTGL [VPRCSR_NORDIC_DIROUTTGL] DIROUT Toggle + */ + #define VPRCSR_NORDIC_DIROUTTGL (0x00000BD4ul) + #define VPRCSR_NORDIC_DIROUTTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTTGL register. */ + +/* OUT0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos) /*!< Bit mask of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Min (0x0UL) /*!< Min enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Max (0x1UL) /*!< Max enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos) /*!< Bit mask of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Min (0x0UL) /*!< Min enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Max (0x1UL) /*!< Max enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos) /*!< Bit mask of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Min (0x0UL) /*!< Min enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Max (0x1UL) /*!< Max enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos) /*!< Bit mask of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Min (0x0UL) /*!< Min enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Max (0x1UL) /*!< Max enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos) /*!< Bit mask of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Min (0x0UL) /*!< Min enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Max (0x1UL) /*!< Max enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos) /*!< Bit mask of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Min (0x0UL) /*!< Min enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Max (0x1UL) /*!< Max enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos) /*!< Bit mask of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Min (0x0UL) /*!< Min enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Max (0x1UL) /*!< Max enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos) /*!< Bit mask of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Min (0x0UL) /*!< Min enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Max (0x1UL) /*!< Max enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos (8UL) /*!< Position of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos) /*!< Bit mask of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Min (0x0UL) /*!< Min enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Max (0x1UL) /*!< Max enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos (9UL) /*!< Position of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos) /*!< Bit mask of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Min (0x0UL) /*!< Min enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Max (0x1UL) /*!< Max enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos (10UL) /*!< Position of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos) /*!< Bit mask of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Min (0x0UL) /*!< Min enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Max (0x1UL) /*!< Max enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos (11UL) /*!< Position of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos) /*!< Bit mask of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Min (0x0UL) /*!< Min enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Max (0x1UL) /*!< Max enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos (12UL) /*!< Position of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos) /*!< Bit mask of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Min (0x0UL) /*!< Min enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Max (0x1UL) /*!< Max enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos (13UL) /*!< Position of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos) /*!< Bit mask of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Min (0x0UL) /*!< Min enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Max (0x1UL) /*!< Max enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos (14UL) /*!< Position of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos) /*!< Bit mask of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Min (0x0UL) /*!< Min enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Max (0x1UL) /*!< Max enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos (15UL) /*!< Position of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos) /*!< Bit mask of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Min (0x0UL) /*!< Min enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Max (0x1UL) /*!< Max enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos (16UL) /*!< Position of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos) /*!< Bit mask of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Min (0x0UL) /*!< Min enumerator value of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Max (0x1UL) /*!< Max enumerator value of DIR0 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos (17UL) /*!< Position of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos) /*!< Bit mask of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Min (0x0UL) /*!< Min enumerator value of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Max (0x1UL) /*!< Max enumerator value of DIR1 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos (18UL) /*!< Position of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos) /*!< Bit mask of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Min (0x0UL) /*!< Min enumerator value of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Max (0x1UL) /*!< Max enumerator value of DIR2 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos (19UL) /*!< Position of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos) /*!< Bit mask of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Min (0x0UL) /*!< Min enumerator value of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Max (0x1UL) /*!< Max enumerator value of DIR3 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos (20UL) /*!< Position of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos) /*!< Bit mask of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Min (0x0UL) /*!< Min enumerator value of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Max (0x1UL) /*!< Max enumerator value of DIR4 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos (21UL) /*!< Position of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos) /*!< Bit mask of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Min (0x0UL) /*!< Min enumerator value of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Max (0x1UL) /*!< Max enumerator value of DIR5 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos (22UL) /*!< Position of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos) /*!< Bit mask of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Min (0x0UL) /*!< Min enumerator value of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Max (0x1UL) /*!< Max enumerator value of DIR6 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos (23UL) /*!< Position of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos) /*!< Bit mask of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Min (0x0UL) /*!< Min enumerator value of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Max (0x1UL) /*!< Max enumerator value of DIR7 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos (24UL) /*!< Position of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos) /*!< Bit mask of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Min (0x0UL) /*!< Min enumerator value of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Max (0x1UL) /*!< Max enumerator value of DIR8 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos (25UL) /*!< Position of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos) /*!< Bit mask of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Min (0x0UL) /*!< Min enumerator value of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Max (0x1UL) /*!< Max enumerator value of DIR9 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos (26UL) /*!< Position of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos) /*!< Bit mask of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Min (0x0UL) /*!< Min enumerator value of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Max (0x1UL) /*!< Max enumerator value of DIR10 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos (27UL) /*!< Position of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos) /*!< Bit mask of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Min (0x0UL) /*!< Min enumerator value of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Max (0x1UL) /*!< Max enumerator value of DIR11 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos (28UL) /*!< Position of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos) /*!< Bit mask of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Min (0x0UL) /*!< Min enumerator value of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Max (0x1UL) /*!< Max enumerator value of DIR12 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos (29UL) /*!< Position of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos) /*!< Bit mask of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Min (0x0UL) /*!< Min enumerator value of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Max (0x1UL) /*!< Max enumerator value of DIR13 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos (30UL) /*!< Position of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos) /*!< Bit mask of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Min (0x0UL) /*!< Min enumerator value of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Max (0x1UL) /*!< Max enumerator value of DIR14 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIR15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos (31UL) /*!< Position of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos) /*!< Bit mask of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Min (0x0UL) /*!< Min enumerator value of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Max (0x1UL) /*!< Max enumerator value of DIR15 field. */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTTGL_DIR15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief DIROUTBTGL [VPRCSR_NORDIC_DIROUTBTGL] DIROUTB Toggle + */ + #define VPRCSR_NORDIC_DIROUTBTGL (0x00000BD5ul) + #define VPRCSR_NORDIC_DIROUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBTGL register. */ + +/* OUTB0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos (0UL) /*!< Position of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos (1UL) /*!< Position of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos (2UL) /*!< Position of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos (3UL) /*!< Position of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos (4UL) /*!< Position of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos (5UL) /*!< Position of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos (6UL) /*!< Position of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos (7UL) /*!< Position of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos (8UL) /*!< Position of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos (9UL) /*!< Position of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos (10UL) /*!< Position of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos (11UL) /*!< Position of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos (12UL) /*!< Position of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos (13UL) /*!< Position of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos (14UL) /*!< Position of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos (15UL) /*!< Position of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos (16UL) /*!< Position of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos) /*!< Bit mask of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Min (0x0UL) /*!< Min enumerator value of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Max (0x1UL) /*!< Max enumerator value of DIRB0 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos (17UL) /*!< Position of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos) /*!< Bit mask of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Min (0x0UL) /*!< Min enumerator value of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Max (0x1UL) /*!< Max enumerator value of DIRB1 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos (18UL) /*!< Position of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos) /*!< Bit mask of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Min (0x0UL) /*!< Min enumerator value of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Max (0x1UL) /*!< Max enumerator value of DIRB2 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos (19UL) /*!< Position of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos) /*!< Bit mask of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Min (0x0UL) /*!< Min enumerator value of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Max (0x1UL) /*!< Max enumerator value of DIRB3 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos (20UL) /*!< Position of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos) /*!< Bit mask of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Min (0x0UL) /*!< Min enumerator value of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Max (0x1UL) /*!< Max enumerator value of DIRB4 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos (21UL) /*!< Position of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos) /*!< Bit mask of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Min (0x0UL) /*!< Min enumerator value of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Max (0x1UL) /*!< Max enumerator value of DIRB5 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos (22UL) /*!< Position of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos) /*!< Bit mask of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Min (0x0UL) /*!< Min enumerator value of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Max (0x1UL) /*!< Max enumerator value of DIRB6 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos (23UL) /*!< Position of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos) /*!< Bit mask of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Min (0x0UL) /*!< Min enumerator value of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Max (0x1UL) /*!< Max enumerator value of DIRB7 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos (24UL) /*!< Position of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos) /*!< Bit mask of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Min (0x0UL) /*!< Min enumerator value of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Max (0x1UL) /*!< Max enumerator value of DIRB8 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos (25UL) /*!< Position of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos) /*!< Bit mask of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Min (0x0UL) /*!< Min enumerator value of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Max (0x1UL) /*!< Max enumerator value of DIRB9 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos (26UL) /*!< Position of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos) /*!< Bit mask of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Min (0x0UL) /*!< Min enumerator value of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Max (0x1UL) /*!< Max enumerator value of DIRB10 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos (27UL) /*!< Position of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos) /*!< Bit mask of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Min (0x0UL) /*!< Min enumerator value of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Max (0x1UL) /*!< Max enumerator value of DIRB11 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos (28UL) /*!< Position of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos) /*!< Bit mask of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Min (0x0UL) /*!< Min enumerator value of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Max (0x1UL) /*!< Max enumerator value of DIRB12 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos (29UL) /*!< Position of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos) /*!< Bit mask of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Min (0x0UL) /*!< Min enumerator value of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Max (0x1UL) /*!< Max enumerator value of DIRB13 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos (30UL) /*!< Position of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos) /*!< Bit mask of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Min (0x0UL) /*!< Min enumerator value of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Max (0x1UL) /*!< Max enumerator value of DIRB14 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* DIRB15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos (31UL) /*!< Position of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos) /*!< Bit mask of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Min (0x0UL) /*!< Min enumerator value of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Max (0x1UL) /*!< Max enumerator value of DIRB15 field. */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBS [VPRCSR_NORDIC_OUTBS] Buffered GPIO Output Dirty Status + */ + #define VPRCSR_NORDIC_OUTBS (0x00000BD8ul) + #define VPRCSR_NORDIC_OUTBS_ResetValue (0x00000000UL) /*!< Reset value of OUTBS register. */ + +/* OUTB @Bits 0..31 : Write to OUTB (if not dirty) */ + #define VPRCSR_NORDIC_OUTBS_OUTB_Pos (0UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_OUTBS_OUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBS_OUTB_Pos) /*!< Bit mask of OUTB field. */ + +/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief DIRBS [VPRCSR_NORDIC_DIRBS] Buffered GPIO pin Direction Dirty Status + */ + #define VPRCSR_NORDIC_DIRBS (0x00000BD9ul) + #define VPRCSR_NORDIC_DIRBS_ResetValue (0x00000000UL) /*!< Reset value of DIRBS register. */ + +/* DIRB @Bits 0..31 : Write to DIRB (if not dirty) */ + #define VPRCSR_NORDIC_DIRBS_DIRB_Pos (0UL) /*!< Position of DIRB field. */ + #define VPRCSR_NORDIC_DIRBS_DIRB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIRBS_DIRB_Pos) /*!< Bit mask of DIRB field. */ + +/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief DIROUTBS [VPRCSR_NORDIC_DIROUTBS] Combination of DIRB and OUTB Dirty Status + */ + #define VPRCSR_NORDIC_DIROUTBS (0x00000BDAul) + #define VPRCSR_NORDIC_DIROUTBS_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBS register. */ + +/* DIROUTB @Bits 0..31 : Write to DIROUTB (if not dirty) */ + #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos (0UL) /*!< Position of DIROUTB field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos) /*!< Bit mask of DIROUTB + field.*/ + +/* DIRTYBIT @Bit 0 : Read Combination (OR) of DIRB and OUTB Dirty status */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUTBD [VPRCSR_NORDIC_OUTBD] Concatenation of Buffered GPIO Output and GPIO Output + */ + #define VPRCSR_NORDIC_OUTBD (0x00000BE0ul) + #define VPRCSR_NORDIC_OUTBD_ResetValue (0x00000000UL) /*!< Reset value of OUTBD register. */ + +/* OUT @Bits 0..15 : GPIO Output */ + #define VPRCSR_NORDIC_OUTBD_OUT_Pos (0UL) /*!< Position of OUT field. */ + #define VPRCSR_NORDIC_OUTBD_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUT_Pos) /*!< Bit mask of OUT field. */ + +/* OUTB @Bits 16..31 : Buffered GPIO Output */ + #define VPRCSR_NORDIC_OUTBD_OUTB_Pos (16UL) /*!< Position of OUTB field. */ + #define VPRCSR_NORDIC_OUTBD_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUTB_Pos) /*!< Bit mask of OUTB field. */ + + +/** + * @brief OUTBDTGL [VPRCSR_NORDIC_OUTBDTGL] OUTBD Toggle + */ + #define VPRCSR_NORDIC_OUTBDTGL (0x00000BE1ul) + #define VPRCSR_NORDIC_OUTBDTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBDTGL register. */ + +/* OUT0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos) /*!< Bit mask of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Min (0x0UL) /*!< Min enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Max (0x1UL) /*!< Max enumerator value of OUT0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos) /*!< Bit mask of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Min (0x0UL) /*!< Min enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Max (0x1UL) /*!< Max enumerator value of OUT1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos) /*!< Bit mask of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Min (0x0UL) /*!< Min enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Max (0x1UL) /*!< Max enumerator value of OUT2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos) /*!< Bit mask of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Min (0x0UL) /*!< Min enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Max (0x1UL) /*!< Max enumerator value of OUT3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos) /*!< Bit mask of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Min (0x0UL) /*!< Min enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Max (0x1UL) /*!< Max enumerator value of OUT4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos) /*!< Bit mask of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Min (0x0UL) /*!< Min enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Max (0x1UL) /*!< Max enumerator value of OUT5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos) /*!< Bit mask of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Min (0x0UL) /*!< Min enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Max (0x1UL) /*!< Max enumerator value of OUT6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos) /*!< Bit mask of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Min (0x0UL) /*!< Min enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Max (0x1UL) /*!< Max enumerator value of OUT7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos (8UL) /*!< Position of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos) /*!< Bit mask of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Min (0x0UL) /*!< Min enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Max (0x1UL) /*!< Max enumerator value of OUT8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos (9UL) /*!< Position of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos) /*!< Bit mask of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Min (0x0UL) /*!< Min enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Max (0x1UL) /*!< Max enumerator value of OUT9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos (10UL) /*!< Position of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos) /*!< Bit mask of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Min (0x0UL) /*!< Min enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Max (0x1UL) /*!< Max enumerator value of OUT10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos (11UL) /*!< Position of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos) /*!< Bit mask of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Min (0x0UL) /*!< Min enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Max (0x1UL) /*!< Max enumerator value of OUT11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos (12UL) /*!< Position of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos) /*!< Bit mask of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Min (0x0UL) /*!< Min enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Max (0x1UL) /*!< Max enumerator value of OUT12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos (13UL) /*!< Position of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos) /*!< Bit mask of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Min (0x0UL) /*!< Min enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Max (0x1UL) /*!< Max enumerator value of OUT13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos (14UL) /*!< Position of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos) /*!< Bit mask of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Min (0x0UL) /*!< Min enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Max (0x1UL) /*!< Max enumerator value of OUT14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUT15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos (15UL) /*!< Position of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos) /*!< Bit mask of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Min (0x0UL) /*!< Min enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Max (0x1UL) /*!< Max enumerator value of OUT15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB0 @Bit 16 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos (16UL) /*!< Position of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB1 @Bit 17 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos (17UL) /*!< Position of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB2 @Bit 18 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos (18UL) /*!< Position of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB3 @Bit 19 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos (19UL) /*!< Position of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB4 @Bit 20 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos (20UL) /*!< Position of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB5 @Bit 21 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos (21UL) /*!< Position of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB6 @Bit 22 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos (22UL) /*!< Position of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB7 @Bit 23 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos (23UL) /*!< Position of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB8 @Bit 24 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos (24UL) /*!< Position of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB9 @Bit 25 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos (25UL) /*!< Position of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB10 @Bit 26 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos (26UL) /*!< Position of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB11 @Bit 27 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos (27UL) /*!< Position of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB12 @Bit 28 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos (28UL) /*!< Position of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB13 @Bit 29 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos (29UL) /*!< Position of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB14 @Bit 30 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos (30UL) /*!< Position of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled */ + +/* OUTB15 @Bit 31 : (unspecified) */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos (31UL) /*!< Position of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field. */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged */ + #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled */ + + +/** + * @brief OUTBDS [VPRCSR_NORDIC_OUTBDS] OUTBD Dirty Status + */ + #define VPRCSR_NORDIC_OUTBDS (0x00000BE2ul) + #define VPRCSR_NORDIC_OUTBDS_ResetValue (0x00000000UL) /*!< Reset value of OUTBDS register. */ + +/* OUTBD @Bits 0..31 : Write to OUTBD register (if not dirty) */ + #define VPRCSR_NORDIC_OUTBDS_OUTBD_Pos (0UL) /*!< Position of OUTBD field. */ + #define VPRCSR_NORDIC_OUTBDS_OUTBD_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBDS_OUTBD_Pos) /*!< Bit mask of OUTBD field. */ + +/* DIRTYBIT @Bit 0 : Read OUTB and OUT parallel write Dirty status */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos (0UL) /*!< Position of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field. */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean */ + #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty */ + + +/** + * @brief OUTMODE [VPRCSR_NORDIC_OUTMODE] Serial output mode + */ + #define VPRCSR_NORDIC_OUTMODE (0x00000BE3ul) + #define VPRCSR_NORDIC_OUTMODE_ResetValue (0x00000000UL) /*!< Reset value of OUTMODE register. */ + +/* MODE @Bits 0..2 : Mode */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODE_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line */ + +/* SHIFTMODE @Bit 0 : Shift mode */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos (0UL) /*!< Position of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Msk (0x1UL << VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos) /*!< Bit mask of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Min (0x0UL) /*!< Min enumerator value of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Max (0x1UL) /*!< Max enumerator value of SHIFTMODE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Disabled (0x0UL) /*!< Shift mode is disabled */ + #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Enabled (0x1UL) /*!< Shift mode is enabled */ + +/* FRAMEWIDTH @Bits 16..20 : Frame width in bits */ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH + field.*/ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + +/* SHIFSIZE @Bits 16..19 : Shift size. Only applies if Shift mode is enabled */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos (16UL) /*!< Position of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Msk (0xFUL << VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos) /*!< Bit mask of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Min (0x0UL) /*!< Min enumerator value of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Max (0x4UL) /*!< Max enumerator value of SHIFSIZE field. */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT1 (0x0UL) /*!< Shift OUT by 1 bit */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT2 (0x1UL) /*!< Shift OUT by 2 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT4 (0x2UL) /*!< Shift OUT by 4 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT8 (0x3UL) /*!< Shift OUT by 8 bits */ + #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT16 (0x4UL) /*!< Shift OUT by 16 bits */ + + +/** + * @brief OUTMODEB [VPRCSR_NORDIC_OUTMODEB] Buffered OUTMODE register + */ + #define VPRCSR_NORDIC_OUTMODEB (0x00000BE4ul) + #define VPRCSR_NORDIC_OUTMODEB_ResetValue (0x00000000UL) /*!< Reset value of OUTMODEB register. */ + +/* MODE @Bits 0..2 : Mode */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODEB_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering */ + #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line */ + +/* FRAMEWIDTH @Bits 16..20 : Frame width in bits */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH + field.*/ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field. */ + #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field. */ + + +/** + * @brief INMODEB [VPRCSR_NORDIC_INMODEB] Buffered INMODE register + */ + #define VPRCSR_NORDIC_INMODEB (0x00000BE5ul) + #define VPRCSR_NORDIC_INMODEB_ResetValue (0x00000000UL) /*!< Reset value of INMODEB register. */ + +/* MODE @Bits 0..1 : Input Mode */ + #define VPRCSR_NORDIC_INMODEB_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODEB_MODE_Pos) /*!< Bit mask of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field. */ + #define VPRCSR_NORDIC_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping) */ + #define VPRCSR_NORDIC_INMODEB_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event */ + #define VPRCSR_NORDIC_INMODEB_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event */ + + +/** + * @brief INB [VPRCSR_NORDIC_INB] Buffered GPIO input + */ + #define VPRCSR_NORDIC_INB (0x00000BE6ul) + #define VPRCSR_NORDIC_INB_ResetValue (0x00000000UL) /*!< Reset value of INB register. */ + +/* PIN0 @Bit 0 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN0_Pos) /*!< Bit mask of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Min (0x0UL) /*!< Min enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_Max (0x1UL) /*!< Max enumerator value of PIN0 field. */ + #define VPRCSR_NORDIC_INB_PIN0_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN0_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN1 @Bit 1 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN1_Pos) /*!< Bit mask of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Min (0x0UL) /*!< Min enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_Max (0x1UL) /*!< Max enumerator value of PIN1 field. */ + #define VPRCSR_NORDIC_INB_PIN1_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN1_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN2 @Bit 2 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN2_Pos) /*!< Bit mask of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Min (0x0UL) /*!< Min enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_Max (0x1UL) /*!< Max enumerator value of PIN2 field. */ + #define VPRCSR_NORDIC_INB_PIN2_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN2_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN3 @Bit 3 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN3_Pos) /*!< Bit mask of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Min (0x0UL) /*!< Min enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_Max (0x1UL) /*!< Max enumerator value of PIN3 field. */ + #define VPRCSR_NORDIC_INB_PIN3_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN3_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN4 @Bit 4 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN4_Pos) /*!< Bit mask of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Min (0x0UL) /*!< Min enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_Max (0x1UL) /*!< Max enumerator value of PIN4 field. */ + #define VPRCSR_NORDIC_INB_PIN4_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN4_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN5 @Bit 5 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN5_Pos) /*!< Bit mask of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Min (0x0UL) /*!< Min enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_Max (0x1UL) /*!< Max enumerator value of PIN5 field. */ + #define VPRCSR_NORDIC_INB_PIN5_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN5_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN6 @Bit 6 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN6_Pos) /*!< Bit mask of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Min (0x0UL) /*!< Min enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_Max (0x1UL) /*!< Max enumerator value of PIN6 field. */ + #define VPRCSR_NORDIC_INB_PIN6_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN6_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN7 @Bit 7 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN7_Pos) /*!< Bit mask of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Min (0x0UL) /*!< Min enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_Max (0x1UL) /*!< Max enumerator value of PIN7 field. */ + #define VPRCSR_NORDIC_INB_PIN7_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN7_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN8 @Bit 8 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN8_Pos) /*!< Bit mask of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Min (0x0UL) /*!< Min enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_Max (0x1UL) /*!< Max enumerator value of PIN8 field. */ + #define VPRCSR_NORDIC_INB_PIN8_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN8_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN9 @Bit 9 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN9_Pos) /*!< Bit mask of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Min (0x0UL) /*!< Min enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_Max (0x1UL) /*!< Max enumerator value of PIN9 field. */ + #define VPRCSR_NORDIC_INB_PIN9_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN9_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN10 @Bit 10 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN10_Pos) /*!< Bit mask of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Min (0x0UL) /*!< Min enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_Max (0x1UL) /*!< Max enumerator value of PIN10 field. */ + #define VPRCSR_NORDIC_INB_PIN10_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN10_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN11 @Bit 11 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN11_Pos) /*!< Bit mask of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Min (0x0UL) /*!< Min enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_Max (0x1UL) /*!< Max enumerator value of PIN11 field. */ + #define VPRCSR_NORDIC_INB_PIN11_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN11_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN12 @Bit 12 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN12_Pos) /*!< Bit mask of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Min (0x0UL) /*!< Min enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_Max (0x1UL) /*!< Max enumerator value of PIN12 field. */ + #define VPRCSR_NORDIC_INB_PIN12_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN12_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN13 @Bit 13 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN13_Pos) /*!< Bit mask of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Min (0x0UL) /*!< Min enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_Max (0x1UL) /*!< Max enumerator value of PIN13 field. */ + #define VPRCSR_NORDIC_INB_PIN13_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN13_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN14 @Bit 14 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN14_Pos) /*!< Bit mask of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Min (0x0UL) /*!< Min enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_Max (0x1UL) /*!< Max enumerator value of PIN14 field. */ + #define VPRCSR_NORDIC_INB_PIN14_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN14_HIGH (0x1UL) /*!< Pin is High */ + +/* PIN15 @Bit 15 : (unspecified) */ + #define VPRCSR_NORDIC_INB_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN15_Pos) /*!< Bit mask of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Min (0x0UL) /*!< Min enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_Max (0x1UL) /*!< Max enumerator value of PIN15 field. */ + #define VPRCSR_NORDIC_INB_PIN15_LOW (0x0UL) /*!< Pin is Low */ + #define VPRCSR_NORDIC_INB_PIN15_HIGH (0x1UL) /*!< Pin is High */ + + + + +/* =========================================================================================================================== */ +/* ================ VPRPUBLIC ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ==================================================== Struct VPRPUBLIC ===================================================== */ +/** + * @brief VPR peripheral registers + */ + typedef struct { /*!< VPRPUBLIC Structure */ + __OM uint32_t TASKS_TRIGGER[32]; /*!< (@ 0x00000000) VPR task [n] register */ + } NRF_VPRPUBLIC_Type; /*!< Size = 128 (0x080) */ + +/* VPRPUBLIC_TASKS_TRIGGER: VPR task [n] register */ + #define VPRPUBLIC_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array. */ + #define VPRPUBLIC_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array. */ + #define VPRPUBLIC_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array. */ + #define VPRPUBLIC_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register. */ + +/* TASKS_TRIGGER @Bit 0 : VPR task [n] register */ + #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ + #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of + TASKS_TRIGGER field.*/ + #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field. */ + #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field. */ + #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* =========================================================================================================================== */ +/* ================ VTIM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief VTIM CSR registers + */ + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ +/* ======================================================= Struct WDT ======================================================== */ +/** + * @brief Watchdog Timer + */ + typedef struct { /*!< WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ + __IM uint32_t RESERVED[30]; + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ + __IM uint32_t RESERVED1[30]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ + __IM uint32_t RESERVED2[30]; + __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ + __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ + __IM uint32_t RESERVED3[95]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[6]; + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED5[53]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED6[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED7[4]; + __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ + __IM uint32_t RESERVED8[55]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload request n */ + } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + +/* WDT_TASKS_START: Start WDT */ + #define WDT_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Start WDT */ + #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + + +/* WDT_TASKS_STOP: Stop WDT */ + #define WDT_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register. */ + +/* TASKS_STOP @Bit 0 : Stop WDT */ + #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Min (0x1UL) /*!< Min enumerator value of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Max (0x1UL) /*!< Max enumerator value of TASKS_STOP field. */ + #define WDT_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ + + +/* WDT_SUBSCRIBE_START: Subscribe configuration for task START */ + #define WDT_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* WDT_SUBSCRIBE_STOP: Subscribe configuration for task STOP */ + #define WDT_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define WDT_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ + + +/* WDT_EVENTS_TIMEOUT: Watchdog timeout */ + #define WDT_EVENTS_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TIMEOUT register. */ + +/* EVENTS_TIMEOUT @Bit 0 : Watchdog timeout */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT + field.*/ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_TIMEOUT field. */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ + #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */ + + +/* WDT_EVENTS_STOPPED: Watchdog stopped */ + #define WDT_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register. */ + +/* EVENTS_STOPPED @Bit 0 : Watchdog stopped */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED + field.*/ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field. */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ + #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ + + +/* WDT_PUBLISH_TIMEOUT: Publish configuration for event TIMEOUT */ + #define WDT_PUBLISH_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TIMEOUT register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TIMEOUT will publish to */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_PUBLISH_TIMEOUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* WDT_PUBLISH_STOPPED: Publish configuration for event STOPPED */ + #define WDT_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */ + #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define WDT_PUBLISH_STOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define WDT_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define WDT_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define WDT_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ + + +/* WDT_INTENSET: Enable interrupt */ + #define WDT_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register. */ + +/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ + #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ + #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define WDT_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define WDT_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_INTENCLR: Disable interrupt */ + #define WDT_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register. */ + +/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ + #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ + #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define WDT_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define WDT_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_NMIENSET: Enable interrupt */ + #define WDT_NMIENSET_ResetValue (0x00000000UL) /*!< Reset value of NMIENSET register. */ + +/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ + #define WDT_NMIENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_NMIENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ + #define WDT_NMIENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */ + #define WDT_NMIENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_NMIENSET_STOPPED_Set (0x1UL) /*!< Enable */ + #define WDT_NMIENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_NMIENCLR: Disable interrupt */ + #define WDT_NMIENCLR_ResetValue (0x00000000UL) /*!< Reset value of NMIENCLR register. */ + +/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ + #define WDT_NMIENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of TIMEOUT field. */ + #define WDT_NMIENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ + #define WDT_NMIENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ + +/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */ + #define WDT_NMIENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Min (0x0UL) /*!< Min enumerator value of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Max (0x1UL) /*!< Max enumerator value of STOPPED field. */ + #define WDT_NMIENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ + #define WDT_NMIENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ + #define WDT_NMIENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ + + +/* WDT_RUNSTATUS: Run status */ + #define WDT_RUNSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RUNSTATUS register. */ + +/* RUNSTATUSWDT @Bit 0 : Indicates whether or not WDT is running */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Min (0x0UL) /*!< Min enumerator value of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Max (0x1UL) /*!< Max enumerator value of RUNSTATUSWDT field. */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog is not running */ + #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */ + + +/* WDT_REQSTATUS: Request status */ + #define WDT_REQSTATUS_ResetValue (0x00000001UL) /*!< Reset value of REQSTATUS register. */ + +/* RR0 @Bit 0 : Request status for RR[0] register */ + #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ + #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ + #define WDT_REQSTATUS_RR0_Min (0x0UL) /*!< Min enumerator value of RR0 field. */ + #define WDT_REQSTATUS_RR0_Max (0x1UL) /*!< Max enumerator value of RR0 field. */ + #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* RR1 @Bit 1 : Request status for RR[1] register */ + #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ + #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ + #define WDT_REQSTATUS_RR1_Min (0x0UL) /*!< Min enumerator value of RR1 field. */ + #define WDT_REQSTATUS_RR1_Max (0x1UL) /*!< Max enumerator value of RR1 field. */ + #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* RR2 @Bit 2 : Request status for RR[2] register */ + #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ + #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ + #define WDT_REQSTATUS_RR2_Min (0x0UL) /*!< Min enumerator value of RR2 field. */ + #define WDT_REQSTATUS_RR2_Max (0x1UL) /*!< Max enumerator value of RR2 field. */ + #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* RR3 @Bit 3 : Request status for RR[3] register */ + #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ + #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ + #define WDT_REQSTATUS_RR3_Min (0x0UL) /*!< Min enumerator value of RR3 field. */ + #define WDT_REQSTATUS_RR3_Max (0x1UL) /*!< Max enumerator value of RR3 field. */ + #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* RR4 @Bit 4 : Request status for RR[4] register */ + #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ + #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ + #define WDT_REQSTATUS_RR4_Min (0x0UL) /*!< Min enumerator value of RR4 field. */ + #define WDT_REQSTATUS_RR4_Max (0x1UL) /*!< Max enumerator value of RR4 field. */ + #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* RR5 @Bit 5 : Request status for RR[5] register */ + #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ + #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ + #define WDT_REQSTATUS_RR5_Min (0x0UL) /*!< Min enumerator value of RR5 field. */ + #define WDT_REQSTATUS_RR5_Max (0x1UL) /*!< Max enumerator value of RR5 field. */ + #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* RR6 @Bit 6 : Request status for RR[6] register */ + #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ + #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ + #define WDT_REQSTATUS_RR6_Min (0x0UL) /*!< Min enumerator value of RR6 field. */ + #define WDT_REQSTATUS_RR6_Max (0x1UL) /*!< Max enumerator value of RR6 field. */ + #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* RR7 @Bit 7 : Request status for RR[7] register */ + #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ + #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ + #define WDT_REQSTATUS_RR7_Min (0x0UL) /*!< Min enumerator value of RR7 field. */ + #define WDT_REQSTATUS_RR7_Max (0x1UL) /*!< Max enumerator value of RR7 field. */ + #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ + #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + + +/* WDT_CRV: Counter reload value */ + #define WDT_CRV_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CRV register. */ + +/* CRV @Bits 0..31 : Counter reload value in number of cycles of the 32.768 kHz clock */ + #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ + #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + #define WDT_CRV_CRV_Min (0x0000000FUL) /*!< Min value of CRV field. */ + #define WDT_CRV_CRV_Max (0xFFFFFFFFUL) /*!< Max size of CRV field. */ + + +/* WDT_RREN: Enable register for reload request registers */ + #define WDT_RREN_ResetValue (0x00000001UL) /*!< Reset value of RREN register. */ + +/* RR0 @Bit 0 : Enable or disable RR[0] register */ + #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ + #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ + #define WDT_RREN_RR0_Min (0x0UL) /*!< Min enumerator value of RR0 field. */ + #define WDT_RREN_RR0_Max (0x1UL) /*!< Max enumerator value of RR0 field. */ + #define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */ + #define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */ + +/* RR1 @Bit 1 : Enable or disable RR[1] register */ + #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ + #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ + #define WDT_RREN_RR1_Min (0x0UL) /*!< Min enumerator value of RR1 field. */ + #define WDT_RREN_RR1_Max (0x1UL) /*!< Max enumerator value of RR1 field. */ + #define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */ + #define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */ + +/* RR2 @Bit 2 : Enable or disable RR[2] register */ + #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ + #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ + #define WDT_RREN_RR2_Min (0x0UL) /*!< Min enumerator value of RR2 field. */ + #define WDT_RREN_RR2_Max (0x1UL) /*!< Max enumerator value of RR2 field. */ + #define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */ + #define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */ + +/* RR3 @Bit 3 : Enable or disable RR[3] register */ + #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ + #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ + #define WDT_RREN_RR3_Min (0x0UL) /*!< Min enumerator value of RR3 field. */ + #define WDT_RREN_RR3_Max (0x1UL) /*!< Max enumerator value of RR3 field. */ + #define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */ + #define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */ + +/* RR4 @Bit 4 : Enable or disable RR[4] register */ + #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ + #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ + #define WDT_RREN_RR4_Min (0x0UL) /*!< Min enumerator value of RR4 field. */ + #define WDT_RREN_RR4_Max (0x1UL) /*!< Max enumerator value of RR4 field. */ + #define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */ + #define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */ + +/* RR5 @Bit 5 : Enable or disable RR[5] register */ + #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ + #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ + #define WDT_RREN_RR5_Min (0x0UL) /*!< Min enumerator value of RR5 field. */ + #define WDT_RREN_RR5_Max (0x1UL) /*!< Max enumerator value of RR5 field. */ + #define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */ + #define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */ + +/* RR6 @Bit 6 : Enable or disable RR[6] register */ + #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ + #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ + #define WDT_RREN_RR6_Min (0x0UL) /*!< Min enumerator value of RR6 field. */ + #define WDT_RREN_RR6_Max (0x1UL) /*!< Max enumerator value of RR6 field. */ + #define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */ + #define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */ + +/* RR7 @Bit 7 : Enable or disable RR[7] register */ + #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ + #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ + #define WDT_RREN_RR7_Min (0x0UL) /*!< Min enumerator value of RR7 field. */ + #define WDT_RREN_RR7_Max (0x1UL) /*!< Max enumerator value of RR7 field. */ + #define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */ + #define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */ + + +/* WDT_CONFIG: Configuration register */ + #define WDT_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register. */ + +/* SLEEP @Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */ + #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Min (0x0UL) /*!< Min enumerator value of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Max (0x1UL) /*!< Max enumerator value of SLEEP field. */ + #define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause WDT while the CPU is sleeping */ + #define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep WDT running while the CPU is sleeping */ + +/* HALT @Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */ + #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ + #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ + #define WDT_CONFIG_HALT_Min (0x0UL) /*!< Min enumerator value of HALT field. */ + #define WDT_CONFIG_HALT_Max (0x1UL) /*!< Max enumerator value of HALT field. */ + #define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause WDT while the CPU is halted by the debugger */ + #define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep WDT running while the CPU is halted by the debugger */ + +/* STOPEN @Bit 6 : Allow stopping WDT */ + #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Min (0x0UL) /*!< Min enumerator value of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Max (0x1UL) /*!< Max enumerator value of STOPEN field. */ + #define WDT_CONFIG_STOPEN_Disable (0x0UL) /*!< Do not allow stopping WDT */ + #define WDT_CONFIG_STOPEN_Enable (0x1UL) /*!< Allow stopping WDT */ + + +/* WDT_TSEN: Task stop enable */ + #define WDT_TSEN_ResetValue (0x00000000UL) /*!< Reset value of TSEN register. */ + +/* TSEN @Bits 0..31 : Allow stopping WDT */ + #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */ + #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */ + #define WDT_TSEN_TSEN_Min (0x6E524635UL) /*!< Min enumerator value of TSEN field. */ + #define WDT_TSEN_TSEN_Max (0x6E524635UL) /*!< Max enumerator value of TSEN field. */ + #define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */ + + +/* WDT_RR: Reload request n */ + #define WDT_RR_MaxCount (8UL) /*!< Max size of RR[8] array. */ + #define WDT_RR_MaxIndex (7UL) /*!< Max index of RR[8] array. */ + #define WDT_RR_MinIndex (0UL) /*!< Min index of RR[8] array. */ + #define WDT_RR_ResetValue (0x00000000UL) /*!< Reset value of RR[8] register. */ + +/* RR @Bits 0..31 : Reload request register */ + #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ + #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ + #define WDT_RR_RR_Min (0x6E524635UL) /*!< Min enumerator value of RR field. */ + #define WDT_RR_RR_Max (0x6E524635UL) /*!< Max enumerator value of RR field. */ + #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* ========================================== End of section using anonymous unions ========================================== */ + +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_TYPES_H */ + diff --git a/mdk/nrf9230_enga_version.h b/mdk/nrf9230_enga_version.h new file mode 100644 index 000000000..b0d5295fa --- /dev/null +++ b/mdk/nrf9230_enga_version.h @@ -0,0 +1,53 @@ +/* + +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF9230_ENGA_VERSION_H +#define NRF9230_ENGA_VERSION_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#define MDK_SOURCE_VERSION_MAJOR 0 /*!< Major version of product specification. */ +#define MDK_SOURCE_VERSION_MINOR 2 /*!< Minor version of product specification. */ +#define MDK_SOURCE_VERSION_MICRO 30 /*!< Micro version of product specification. */ + + + +#ifdef __cplusplus +} +#endif +#endif /* NRF9230_ENGA_VERSION_H */ + diff --git a/mdk/nrf9230_enga_xxaa_application.ld b/mdk/nrf9230_enga_xxaa_application.ld new file mode 100644 index 000000000..5d57e24cf --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_application.ld @@ -0,0 +1,21 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0xE0A0000, LENGTH = 0x40000 /* Inside global MRAM0 */ + FLASH1 (rx) : ORIGIN = 0x2F840000, LENGTH = 0x4000 /* OTP0 */ + EXTFLASH (rx) : ORIGIN = 0x70000000, LENGTH = 0x20000000 + RAM (rwx) : ORIGIN = 0x22000000, LENGTH = 0x8000 + RAM1 (rwx) : ORIGIN = 0x2F000000, LENGTH = 0x80000 /* GRAM00 */ + RAM2 (rwx) : ORIGIN = 0x2F080000, LENGTH = 0x60000 /* GRAM01 */ + RAM3 (rwx) : ORIGIN = 0x2F880000, LENGTH = 0x10000 /* GRAM20 */ + RAM4 (rwx) : ORIGIN = 0x2F890000, LENGTH = 0x8000 /* GRAM21 */ + RAM5 (rwx) : ORIGIN = 0x2FC00000, LENGTH = 0x4000 /* GRAM30 (low-speed) */ + RAM6 (rwx) : ORIGIN = 0x2FC04000, LENGTH = 0x4000 /* GRAM31 (low-speed) */ +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf9230_enga_xxaa_application.sct b/mdk/nrf9230_enga_xxaa_application.sct new file mode 100644 index 000000000..d863df7fd --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_application.sct @@ -0,0 +1,56 @@ +LOAD 0x0E0A0000 0x00040000 +{ + FLASH0 0x0E0A0000 0x00040000 + { + *.o (RESET, +First) ; RESET is code section with I.V.T. + * (InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + FLASH1 0x2F840000 0x00004000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x70000000 0x20000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x22000000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x2F000000 0x00080000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM2 0x2F080000 0x00060000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM3 0x2F880000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM4 0x2F890000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM5 0x2FC00000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM6 0x2FC04000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9230_enga_xxaa_application_memory.h b/mdk/nrf9230_enga_xxaa_application_memory.h new file mode 100644 index 000000000..8f308ef50 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_application_memory.h @@ -0,0 +1,73 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x0E0A0000 +#define NRF_MEMORY_FLASH_SIZE 0x00040000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x0FFF8000 +#define NRF_MEMORY_UICR_SIZE 0x00000800 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x22000000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x52000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x42000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x52840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf9230_enga_xxaa_flpr.ld b/mdk/nrf9230_enga_xxaa_flpr.ld new file mode 100644 index 000000000..665f94b82 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_flpr.ld @@ -0,0 +1,21 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0xE100000, LENGTH = 0x20000 /* Inside global MRAM0 */ + FLASH1 (rx) : ORIGIN = 0x2F840000, LENGTH = 0x4000 /* OTP0 */ + EXTFLASH (rx) : ORIGIN = 0x70000000, LENGTH = 0x20000000 + RAM (rwx) : ORIGIN = 0x2F890000, LENGTH = 0x8000 /* All of GRAM21 */ + RAM1 (rwx) : ORIGIN = 0x2F000000, LENGTH = 0x80000 /* GRAM00 */ + RAM2 (rwx) : ORIGIN = 0x2F080000, LENGTH = 0x60000 /* GRAM01 */ + RAM3 (rwx) : ORIGIN = 0x2F880000, LENGTH = 0x10000 /* GRAM20 */ + RAM4 (rwx) : ORIGIN = 0x2F890000, LENGTH = 0x8000 /* GRAM21 */ + RAM5 (rwx) : ORIGIN = 0x2FC00000, LENGTH = 0x4000 /* GRAM30 (low-speed) */ + RAM6 (rwx) : ORIGIN = 0x2FC04000, LENGTH = 0x4000 /* GRAM31 (low-speed) */ +} + + +INCLUDE "nrf_common_riscv.ld" diff --git a/mdk/nrf9230_enga_xxaa_flpr.sct b/mdk/nrf9230_enga_xxaa_flpr.sct new file mode 100644 index 000000000..c432650e4 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_flpr.sct @@ -0,0 +1,56 @@ +LOAD 0x0E100000 0x00020000 +{ + FLASH0 0x0E100000 0x00020000 + { + *.o (RESET, +First) ; RESET is code section with I.V.T. + * (InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + FLASH1 0x2F840000 0x00004000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x70000000 0x20000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x2F890000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x2F000000 0x00080000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM2 0x2F080000 0x00060000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM3 0x2F880000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM4 0x2F890000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM5 0x2FC00000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM6 0x2FC04000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9230_enga_xxaa_flpr_memory.h b/mdk/nrf9230_enga_xxaa_flpr_memory.h new file mode 100644 index 000000000..c8cd66172 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_flpr_memory.h @@ -0,0 +1,69 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x0E100000 +#define NRF_MEMORY_FLASH_SIZE 0x00020000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x2F890000 +#define NRF_MEMORY_RAM_SIZE 0x00008000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x5F000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x4F000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x5F840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf9230_enga_xxaa_ppr.ld b/mdk/nrf9230_enga_xxaa_ppr.ld new file mode 100644 index 000000000..73d47d0fb --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_ppr.ld @@ -0,0 +1,21 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0xE0E0000, LENGTH = 0x20000 /* Inside global MRAM0 */ + FLASH1 (rx) : ORIGIN = 0x2F840000, LENGTH = 0x4000 /* OTP0 */ + EXTFLASH (rx) : ORIGIN = 0x70000000, LENGTH = 0x20000000 + RAM (rwx) : ORIGIN = 0x2FC00000, LENGTH = 0x4000 /* All of GRAM30 */ + RAM1 (rwx) : ORIGIN = 0x2F000000, LENGTH = 0x80000 /* GRAM00 */ + RAM2 (rwx) : ORIGIN = 0x2F080000, LENGTH = 0x60000 /* GRAM01 */ + RAM3 (rwx) : ORIGIN = 0x2F880000, LENGTH = 0x10000 /* GRAM20 */ + RAM4 (rwx) : ORIGIN = 0x2F890000, LENGTH = 0x8000 /* GRAM21 */ + RAM5 (rwx) : ORIGIN = 0x2FC00000, LENGTH = 0x4000 /* GRAM30 (low-speed) */ + RAM6 (rwx) : ORIGIN = 0x2FC04000, LENGTH = 0x4000 /* GRAM31 (low-speed) */ +} + + +INCLUDE "nrf_common_riscv.ld" diff --git a/mdk/nrf9230_enga_xxaa_ppr.sct b/mdk/nrf9230_enga_xxaa_ppr.sct new file mode 100644 index 000000000..39e9e7d08 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_ppr.sct @@ -0,0 +1,56 @@ +LOAD 0x0E0E0000 0x00020000 +{ + FLASH0 0x0E0E0000 0x00020000 + { + *.o (RESET, +First) ; RESET is code section with I.V.T. + * (InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + FLASH1 0x2F840000 0x00004000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x70000000 0x20000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x2FC00000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x2F000000 0x00080000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM2 0x2F080000 0x00060000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM3 0x2F880000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM4 0x2F890000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM5 0x2FC00000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM6 0x2FC04000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9230_enga_xxaa_ppr_memory.h b/mdk/nrf9230_enga_xxaa_ppr_memory.h new file mode 100644 index 000000000..13b572f61 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_ppr_memory.h @@ -0,0 +1,69 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 2048 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 2048 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x0E0E0000 +#define NRF_MEMORY_FLASH_SIZE 0x00020000 + +/* Device memory RAM: */ +#define NRF_MEMORY_RAM_BASE 0x2FC00000 +#define NRF_MEMORY_RAM_SIZE 0x00004000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x5F000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x4F000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x5F840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf9230_enga_xxaa_radiocore.ld b/mdk/nrf9230_enga_xxaa_radiocore.ld new file mode 100644 index 000000000..4e293d181 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_radiocore.ld @@ -0,0 +1,22 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0xE120000, LENGTH = 0x80000 /* Inside global MRAM0 */ + FLASH1 (rx) : ORIGIN = 0x2F840000, LENGTH = 0x4000 /* OTP0 */ + EXTFLASH (rx) : ORIGIN = 0x70000000, LENGTH = 0x20000000 + RAM (rwx) : ORIGIN = 0x23000000, LENGTH = 0x10000 /* Inside network RAM0 */ + RAM1 (rwx) : ORIGIN = 0x23010000, LENGTH = 0x8000 /* Inside network RAM0 */ + RAM2 (rwx) : ORIGIN = 0x2F000000, LENGTH = 0x80000 /* GRAM00 */ + RAM3 (rwx) : ORIGIN = 0x2F080000, LENGTH = 0x60000 /* GRAM01 */ + RAM4 (rwx) : ORIGIN = 0x2F880000, LENGTH = 0x10000 /* GRAM20 */ + RAM5 (rwx) : ORIGIN = 0x2F890000, LENGTH = 0x8000 /* GRAM21 */ + RAM6 (rwx) : ORIGIN = 0x2FC00000, LENGTH = 0x4000 /* GRAM30 (low-speed) */ + RAM7 (rwx) : ORIGIN = 0x2FC04000, LENGTH = 0x4000 /* GRAM31 (low-speed) */ +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf9230_enga_xxaa_radiocore.sct b/mdk/nrf9230_enga_xxaa_radiocore.sct new file mode 100644 index 000000000..e8012daa2 --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_radiocore.sct @@ -0,0 +1,61 @@ +LOAD 0x0E120000 0x00080000 +{ + FLASH0 0x0E120000 0x00080000 + { + *.o (RESET, +First) ; RESET is code section with I.V.T. + * (InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + FLASH1 0x2F840000 0x00004000 + { + + .ANY (+RO) + .ANY (+XO) + } + EXT_FLASH 0x70000000 0x20000000 + { + .ANY (ext_flash) ; Data or code allocated to external memory + } + RAM0 0x23000000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM1 0x23010000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM2 0x2F000000 0x00080000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM3 0x2F080000 0x00060000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM4 0x2F880000 0x00010000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM5 0x2F890000 0x00008000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM6 0x2FC00000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + + RAM7 0x2FC04000 0x00004000 + { + .ANY(+RW, +ZI) ; RW data and ZI data + } + +} \ No newline at end of file diff --git a/mdk/nrf9230_enga_xxaa_radiocore_memory.h b/mdk/nrf9230_enga_xxaa_radiocore_memory.h new file mode 100644 index 000000000..e8ea64afb --- /dev/null +++ b/mdk/nrf9230_enga_xxaa_radiocore_memory.h @@ -0,0 +1,77 @@ +/* +Copyright (c) 2010 - 2024, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_DEVICE_MEM_H_ +#define NRF_DEVICE_MEM_H_ + +#ifndef __DEFAULT_STACK_SIZE + #define __DEFAULT_STACK_SIZE 4096 +#endif +#ifndef __DEFAULT_HEAP_SIZE + #define __DEFAULT_HEAP_SIZE 4096 +#endif + +/* Device memory Flash: */ +#define NRF_MEMORY_FLASH_BASE 0x0E120000 +#define NRF_MEMORY_FLASH_SIZE 0x00080000 + +/* Device memory UICR: */ +#define NRF_MEMORY_UICR_BASE 0x0FFFA000 +#define NRF_MEMORY_UICR_SIZE 0x00000C00 + +/* Device memory RAM0: */ +#define NRF_MEMORY_RAM0_BASE 0x23000000 +#define NRF_MEMORY_RAM0_SIZE 0x00010000 + +/* Device memory RAM1: */ +#define NRF_MEMORY_RAM1_BASE 0x23010000 +#define NRF_MEMORY_RAM1_SIZE 0x00008000 + +/* Device memory PeripheralsAPBS: */ +#define NRF_MEMORY_PERIPHERALSAPBS_BASE 0x53000000 +#define NRF_MEMORY_PERIPHERALSAPBS_SIZE 0x00200000 + +/* Device memory PeripheralsAPBNS: */ +#define NRF_MEMORY_PERIPHERALSAPBNS_BASE 0x43000000 +#define NRF_MEMORY_PERIPHERALSAPBNS_SIZE 0x00200000 + +/* Device memory PeripheralsAHB: */ +#define NRF_MEMORY_PERIPHERALSAHB_BASE 0x53840000 +#define NRF_MEMORY_PERIPHERALSAHB_SIZE 0x00003000 + +/* Device memory SystemSFR: */ +#define NRF_MEMORY_SYSTEMSFR_BASE 0xE0000000 +#define NRF_MEMORY_SYSTEMSFR_SIZE 0x00100000 + + + +#endif diff --git a/mdk/nrf_mem.h b/mdk/nrf_mem.h index 90c5a0d26..e4ec57d7f 100644 --- a/mdk/nrf_mem.h +++ b/mdk/nrf_mem.h @@ -78,6 +78,19 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf9120_xxaa_memory.h" #elif defined(NRF9160_XXAA) #include "nrf9160_xxaa_memory.h" +#elif defined(NRF9230_ENGA_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf9230_enga_xxaa_application_memory.h" + #endif + #if defined(NRF_RADIOCORE) + #include "nrf9230_enga_xxaa_radiocore_memory.h" + #endif + #if defined(NRF_PPR) + #include "nrf9230_enga_xxaa_ppr_memory.h" + #endif + #if defined(NRF_FLPR) + #include "nrf9230_enga_xxaa_flpr_memory.h" + #endif #elif defined(NRF54H20_XXAA) #if defined(NRF_APPLICATION) #include "nrf54h20_xxaa_application_memory.h" diff --git a/mdk/nrf_peripherals.h b/mdk/nrf_peripherals.h index 69290005d..adbe43302 100644 --- a/mdk/nrf_peripherals.h +++ b/mdk/nrf_peripherals.h @@ -77,6 +77,9 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined(NRF9160_XXAA) #include "nrf9160_peripherals.h" +#elif defined (NRF9230_ENGA_XXAA) + #include "nrf9230_enga_peripherals.h" + #else #error "Device must be defined. See nrf_peripherals.h." #endif diff --git a/mdk/nrf_vectors.h b/mdk/nrf_vectors.h index d205023cf..94683783d 100644 --- a/mdk/nrf_vectors.h +++ b/mdk/nrf_vectors.h @@ -78,6 +78,19 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf9120_vectors.h" #elif defined(NRF9160_XXAA) #include "nrf9160_vectors.h" +#elif defined(NRF9230_ENGA_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf9230_enga_application_vectors.h" + #endif + #if defined(NRF_RADIOCORE) + #include "nrf9230_enga_radiocore_vectors.h" + #endif + #if defined(NRF_PPR) + #include "nrf9230_enga_ppr_vectors.h" + #endif + #if defined(NRF_FLPR) + #include "nrf9230_enga_flpr_vectors.h" + #endif #elif defined(NRF54H20_XXAA) #if defined(NRF_APPLICATION) #include "nrf54h20_application_vectors.h" diff --git a/mdk/ses_startup_nrf9230_enga_application.s b/mdk/ses_startup_nrf9230_enga_application.s new file mode 100644 index 000000000..030ad7542 --- /dev/null +++ b/mdk/ses_startup_nrf9230_enga_application.s @@ -0,0 +1,660 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + + +/************************************************************************************ + * Macros * + ************************************************************************************/ + +// Directly place a vector (word) in the vector table +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// Declare an exception handler with a weak definition +.macro EXC_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// Declare an interrupt handler with a weak definition +.macro ISR_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + + .thumb_func +nRFInitialize: + bx lr + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + EXC_HANDLER HardFault_Handler + EXC_HANDLER MemoryManagement_Handler + EXC_HANDLER BusFault_Handler + EXC_HANDLER UsageFault_Handler + EXC_HANDLER SecureFault_Handler + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + EXC_HANDLER SVC_Handler + EXC_HANDLER DebugMon_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + +/* External Interrupts */ + ISR_HANDLER SPU000_IRQHandler + ISR_HANDLER MPC_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER MVDMA_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPU010_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT010_IRQHandler + ISR_HANDLER WDT011_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT_0_IRQHandler + ISR_HANDLER IPCT_1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SWI0_IRQHandler + ISR_HANDLER SWI1_IRQHandler + ISR_HANDLER SWI2_IRQHandler + ISR_HANDLER SWI3_IRQHandler + ISR_HANDLER SWI4_IRQHandler + ISR_HANDLER SWI5_IRQHandler + ISR_HANDLER SWI6_IRQHandler + ISR_HANDLER SWI7_IRQHandler + ISR_HANDLER BELLBOARD_0_IRQHandler + ISR_HANDLER BELLBOARD_1_IRQHandler + ISR_HANDLER BELLBOARD_2_IRQHandler + ISR_HANDLER BELLBOARD_3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE130_0_IRQHandler + ISR_HANDLER GPIOTE130_1_IRQHandler + ISR_HANDLER GPIOTE131_0_IRQHandler + ISR_HANDLER GPIOTE131_1_IRQHandler + ISR_HANDLER GRTC_0_IRQHandler + ISR_HANDLER GRTC_1_IRQHandler + ISR_HANDLER GRTC_2_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TBM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER USBHS_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EXMIF_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT120_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C120_IRQHandler + ISR_HANDLER VPR121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN120_IRQHandler + ISR_HANDLER MVDMA120_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN121_IRQHandler + ISR_HANDLER MVDMA121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER120_IRQHandler + ISR_HANDLER TIMER121_IRQHandler + ISR_HANDLER PWM120_IRQHandler + ISR_HANDLER SPIS120_IRQHandler + ISR_HANDLER SPIM120_UARTE120_IRQHandler + ISR_HANDLER SPIM121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER VPR130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT130_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER RTC130_IRQHandler + ISR_HANDLER RTC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT131_IRQHandler + ISR_HANDLER WDT132_IRQHandler + ISR_HANDLER EGU130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SAADC_IRQHandler + ISR_HANDLER COMP_LPCOMP_IRQHandler + ISR_HANDLER TEMP_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S130_IRQHandler + ISR_HANDLER PDM_IRQHandler + ISR_HANDLER QDEC130_IRQHandler + ISR_HANDLER QDEC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER130_IRQHandler + ISR_HANDLER TIMER131_IRQHandler + ISR_HANDLER PWM130_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler + ISR_HANDLER SERIAL1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER132_IRQHandler + ISR_HANDLER TIMER133_IRQHandler + ISR_HANDLER PWM131_IRQHandler + ISR_HANDLER SERIAL2_IRQHandler + ISR_HANDLER SERIAL3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER134_IRQHandler + ISR_HANDLER TIMER135_IRQHandler + ISR_HANDLER PWM132_IRQHandler + ISR_HANDLER SERIAL4_IRQHandler + ISR_HANDLER SERIAL5_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER136_IRQHandler + ISR_HANDLER TIMER137_IRQHandler + ISR_HANDLER PWM133_IRQHandler + ISR_HANDLER SERIAL6_IRQHandler + ISR_HANDLER SERIAL7_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop diff --git a/mdk/ses_startup_nrf9230_enga_flpr.s b/mdk/ses_startup_nrf9230_enga_flpr.s new file mode 100644 index 000000000..74956df4b --- /dev/null +++ b/mdk/ses_startup_nrf9230_enga_flpr.s @@ -0,0 +1,646 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .section .init, "ax" + .align 0 + + +/************************************************************************************ + * Macros * + ************************************************************************************/ + +// Declare an exception handler with a weak definition +.macro EXC_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section + .section .init.\Name, "ax" + .weak \Name + .balign 2 +\Name: + j . // Endless loop +.endm + +// Declare an interrupt handler with a weak definition +.macro ISR_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .weak \Name + .balign 2 +\Name: + j . // Endless loop +#endif +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + +nRFInitialize: + ret + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .balign 8 + .global _vectors + +_vectors: + EXC_HANDLER UserSoftware_Handler + EXC_HANDLER SuperVisorSoftware_Handler + EXC_HANDLER MachineSoftware_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER UserTimer_Handler + EXC_HANDLER SuperVisorTimer_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER MachineTimer_Handler + EXC_HANDLER UserExternal_Handler + EXC_HANDLER SuperVisorExternal_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER MachineExternal_Handler + EXC_HANDLER CLICSoftware_Handler + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + +/* External Interrupts */ + ISR_HANDLER VPRCLIC_0_IRQHandler + ISR_HANDLER VPRCLIC_1_IRQHandler + ISR_HANDLER VPRCLIC_2_IRQHandler + ISR_HANDLER VPRCLIC_3_IRQHandler + ISR_HANDLER VPRCLIC_4_IRQHandler + ISR_HANDLER VPRCLIC_5_IRQHandler + ISR_HANDLER VPRCLIC_6_IRQHandler + ISR_HANDLER VPRCLIC_7_IRQHandler + ISR_HANDLER VPRCLIC_8_IRQHandler + ISR_HANDLER VPRCLIC_9_IRQHandler + ISR_HANDLER VPRCLIC_10_IRQHandler + ISR_HANDLER VPRCLIC_11_IRQHandler + ISR_HANDLER VPRCLIC_12_IRQHandler + ISR_HANDLER VPRCLIC_13_IRQHandler + ISR_HANDLER VPRCLIC_14_IRQHandler + ISR_HANDLER VPRCLIC_15_IRQHandler + ISR_HANDLER VPRCLIC_16_IRQHandler + ISR_HANDLER VPRCLIC_17_IRQHandler + ISR_HANDLER VPRCLIC_18_IRQHandler + ISR_HANDLER VPRCLIC_19_IRQHandler + ISR_HANDLER VPRCLIC_20_IRQHandler + ISR_HANDLER VPRCLIC_21_IRQHandler + ISR_HANDLER VPRCLIC_22_IRQHandler + ISR_HANDLER VPRCLIC_23_IRQHandler + ISR_HANDLER VPRCLIC_24_IRQHandler + ISR_HANDLER VPRCLIC_25_IRQHandler + ISR_HANDLER VPRCLIC_26_IRQHandler + ISR_HANDLER VPRCLIC_27_IRQHandler + ISR_HANDLER VPRCLIC_28_IRQHandler + ISR_HANDLER VPRCLIC_29_IRQHandler + ISR_HANDLER VPRCLIC_30_IRQHandler + ISR_HANDLER VPRCLIC_31_IRQHandler + ISR_HANDLER VPRTIM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE130_0_IRQHandler + ISR_HANDLER GPIOTE130_1_IRQHandler + ISR_HANDLER GPIOTE131_0_IRQHandler + ISR_HANDLER GPIOTE131_1_IRQHandler + ISR_HANDLER GRTC_0_IRQHandler + ISR_HANDLER GRTC_1_IRQHandler + ISR_HANDLER GRTC_2_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TBM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER USBHS_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EXMIF_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT120_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C120_IRQHandler + ISR_HANDLER VPR121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN120_IRQHandler + ISR_HANDLER MVDMA120_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN121_IRQHandler + ISR_HANDLER MVDMA121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER120_IRQHandler + ISR_HANDLER TIMER121_IRQHandler + ISR_HANDLER PWM120_IRQHandler + ISR_HANDLER SPIS120_IRQHandler + ISR_HANDLER SPIM120_UARTE120_IRQHandler + ISR_HANDLER SPIM121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER VPR130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT130_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER RTC130_IRQHandler + ISR_HANDLER RTC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT131_IRQHandler + ISR_HANDLER WDT132_IRQHandler + ISR_HANDLER EGU130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SAADC_IRQHandler + ISR_HANDLER COMP_LPCOMP_IRQHandler + ISR_HANDLER TEMP_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S130_IRQHandler + ISR_HANDLER PDM_IRQHandler + ISR_HANDLER QDEC130_IRQHandler + ISR_HANDLER QDEC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER130_IRQHandler + ISR_HANDLER TIMER131_IRQHandler + ISR_HANDLER PWM130_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler + ISR_HANDLER SERIAL1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER132_IRQHandler + ISR_HANDLER TIMER133_IRQHandler + ISR_HANDLER PWM131_IRQHandler + ISR_HANDLER SERIAL2_IRQHandler + ISR_HANDLER SERIAL3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER134_IRQHandler + ISR_HANDLER TIMER135_IRQHandler + ISR_HANDLER PWM132_IRQHandler + ISR_HANDLER SERIAL4_IRQHandler + ISR_HANDLER SERIAL5_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER136_IRQHandler + ISR_HANDLER TIMER137_IRQHandler + ISR_HANDLER PWM133_IRQHandler + ISR_HANDLER SERIAL6_IRQHandler + ISR_HANDLER SERIAL7_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + j . // Endless loop + diff --git a/mdk/ses_startup_nrf9230_enga_ppr.s b/mdk/ses_startup_nrf9230_enga_ppr.s new file mode 100644 index 000000000..d5e0dda4a --- /dev/null +++ b/mdk/ses_startup_nrf9230_enga_ppr.s @@ -0,0 +1,646 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .section .init, "ax" + .align 0 + + +/************************************************************************************ + * Macros * + ************************************************************************************/ + +// Declare an exception handler with a weak definition +.macro EXC_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section + .section .init.\Name, "ax" + .weak \Name + .balign 2 +\Name: + j . // Endless loop +.endm + +// Declare an interrupt handler with a weak definition +.macro ISR_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .weak \Name + .balign 2 +\Name: + j . // Endless loop +#endif +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + +nRFInitialize: + ret + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .balign 8 + .global _vectors + +_vectors: + EXC_HANDLER UserSoftware_Handler + EXC_HANDLER SuperVisorSoftware_Handler + EXC_HANDLER MachineSoftware_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER UserTimer_Handler + EXC_HANDLER SuperVisorTimer_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER MachineTimer_Handler + EXC_HANDLER UserExternal_Handler + EXC_HANDLER SuperVisorExternal_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER MachineExternal_Handler + EXC_HANDLER CLICSoftware_Handler + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + +/* External Interrupts */ + ISR_HANDLER VPRCLIC_0_IRQHandler + ISR_HANDLER VPRCLIC_1_IRQHandler + ISR_HANDLER VPRCLIC_2_IRQHandler + ISR_HANDLER VPRCLIC_3_IRQHandler + ISR_HANDLER VPRCLIC_4_IRQHandler + ISR_HANDLER VPRCLIC_5_IRQHandler + ISR_HANDLER VPRCLIC_6_IRQHandler + ISR_HANDLER VPRCLIC_7_IRQHandler + ISR_HANDLER VPRCLIC_8_IRQHandler + ISR_HANDLER VPRCLIC_9_IRQHandler + ISR_HANDLER VPRCLIC_10_IRQHandler + ISR_HANDLER VPRCLIC_11_IRQHandler + ISR_HANDLER VPRCLIC_12_IRQHandler + ISR_HANDLER VPRCLIC_13_IRQHandler + ISR_HANDLER VPRCLIC_14_IRQHandler + ISR_HANDLER VPRCLIC_15_IRQHandler + ISR_HANDLER VPRTIM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE130_0_IRQHandler + ISR_HANDLER GPIOTE130_1_IRQHandler + ISR_HANDLER GPIOTE131_0_IRQHandler + ISR_HANDLER GPIOTE131_1_IRQHandler + ISR_HANDLER GRTC_0_IRQHandler + ISR_HANDLER GRTC_1_IRQHandler + ISR_HANDLER GRTC_2_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TBM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER USBHS_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EXMIF_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT120_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C120_IRQHandler + ISR_HANDLER VPR121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN120_IRQHandler + ISR_HANDLER MVDMA120_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN121_IRQHandler + ISR_HANDLER MVDMA121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER120_IRQHandler + ISR_HANDLER TIMER121_IRQHandler + ISR_HANDLER PWM120_IRQHandler + ISR_HANDLER SPIS120_IRQHandler + ISR_HANDLER SPIM120_UARTE120_IRQHandler + ISR_HANDLER SPIM121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER VPR130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT130_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER RTC130_IRQHandler + ISR_HANDLER RTC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT131_IRQHandler + ISR_HANDLER WDT132_IRQHandler + ISR_HANDLER EGU130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SAADC_IRQHandler + ISR_HANDLER COMP_LPCOMP_IRQHandler + ISR_HANDLER TEMP_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S130_IRQHandler + ISR_HANDLER PDM_IRQHandler + ISR_HANDLER QDEC130_IRQHandler + ISR_HANDLER QDEC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER130_IRQHandler + ISR_HANDLER TIMER131_IRQHandler + ISR_HANDLER PWM130_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler + ISR_HANDLER SERIAL1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER132_IRQHandler + ISR_HANDLER TIMER133_IRQHandler + ISR_HANDLER PWM131_IRQHandler + ISR_HANDLER SERIAL2_IRQHandler + ISR_HANDLER SERIAL3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER134_IRQHandler + ISR_HANDLER TIMER135_IRQHandler + ISR_HANDLER PWM132_IRQHandler + ISR_HANDLER SERIAL4_IRQHandler + ISR_HANDLER SERIAL5_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER136_IRQHandler + ISR_HANDLER TIMER137_IRQHandler + ISR_HANDLER PWM133_IRQHandler + ISR_HANDLER SERIAL6_IRQHandler + ISR_HANDLER SERIAL7_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + j . // Endless loop + diff --git a/mdk/ses_startup_nrf9230_enga_radiocore.s b/mdk/ses_startup_nrf9230_enga_radiocore.s new file mode 100644 index 000000000..7c19178ed --- /dev/null +++ b/mdk/ses_startup_nrf9230_enga_radiocore.s @@ -0,0 +1,660 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + + +/************************************************************************************ + * Macros * + ************************************************************************************/ + +// Directly place a vector (word) in the vector table +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// Declare an exception handler with a weak definition +.macro EXC_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// Declare an interrupt handler with a weak definition +.macro ISR_HANDLER Name= + // Insert vector in vector table + .section .vectors, "ax" + .word \Name + // Insert dummy handler in init section +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// Place a reserved vector in vector table +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + .extern afterInitialize + + .thumb_func +nRFInitialize: + bx lr + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + EXC_HANDLER HardFault_Handler + EXC_HANDLER MemoryManagement_Handler + EXC_HANDLER BusFault_Handler + EXC_HANDLER UsageFault_Handler + EXC_HANDLER SecureFault_Handler + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + ISR_RESERVED /* Reserved */ + EXC_HANDLER SVC_Handler + EXC_HANDLER DebugMon_Handler + ISR_RESERVED /* Reserved */ + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + +/* External Interrupts */ + ISR_HANDLER SPU000_IRQHandler + ISR_HANDLER MPC_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER MVDMA_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPU010_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT010_IRQHandler + ISR_HANDLER WDT011_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPU020_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EGU020_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER020_IRQHandler + ISR_HANDLER TIMER021_IRQHandler + ISR_HANDLER TIMER022_IRQHandler + ISR_HANDLER RTC_IRQHandler + ISR_HANDLER RADIO_0_IRQHandler + ISR_HANDLER RADIO_1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SPU030_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER VPR_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER AAR030_CCM030_IRQHandler + ISR_HANDLER ECB030_IRQHandler + ISR_HANDLER AAR031_CCM031_IRQHandler + ISR_HANDLER ECB031_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT_0_IRQHandler + ISR_HANDLER IPCT_1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SWI0_IRQHandler + ISR_HANDLER SWI1_IRQHandler + ISR_HANDLER SWI2_IRQHandler + ISR_HANDLER SWI3_IRQHandler + ISR_HANDLER SWI4_IRQHandler + ISR_HANDLER SWI5_IRQHandler + ISR_HANDLER SWI6_IRQHandler + ISR_HANDLER SWI7_IRQHandler + ISR_HANDLER BELLBOARD_0_IRQHandler + ISR_HANDLER BELLBOARD_1_IRQHandler + ISR_HANDLER BELLBOARD_2_IRQHandler + ISR_HANDLER BELLBOARD_3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER GPIOTE130_0_IRQHandler + ISR_HANDLER GPIOTE130_1_IRQHandler + ISR_HANDLER GPIOTE131_0_IRQHandler + ISR_HANDLER GPIOTE131_1_IRQHandler + ISR_HANDLER GRTC_0_IRQHandler + ISR_HANDLER GRTC_1_IRQHandler + ISR_HANDLER GRTC_2_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TBM_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER USBHS_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER EXMIF_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT120_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C120_IRQHandler + ISR_HANDLER VPR121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN120_IRQHandler + ISR_HANDLER MVDMA120_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER CAN121_IRQHandler + ISR_HANDLER MVDMA121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I3C121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER120_IRQHandler + ISR_HANDLER TIMER121_IRQHandler + ISR_HANDLER PWM120_IRQHandler + ISR_HANDLER SPIS120_IRQHandler + ISR_HANDLER SPIM120_UARTE120_IRQHandler + ISR_HANDLER SPIM121_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER VPR130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER IPCT130_0_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER RTC130_IRQHandler + ISR_HANDLER RTC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER WDT131_IRQHandler + ISR_HANDLER WDT132_IRQHandler + ISR_HANDLER EGU130_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER SAADC_IRQHandler + ISR_HANDLER COMP_LPCOMP_IRQHandler + ISR_HANDLER TEMP_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S130_IRQHandler + ISR_HANDLER PDM_IRQHandler + ISR_HANDLER QDEC130_IRQHandler + ISR_HANDLER QDEC131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER I2S131_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER130_IRQHandler + ISR_HANDLER TIMER131_IRQHandler + ISR_HANDLER PWM130_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler + ISR_HANDLER SERIAL1_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER132_IRQHandler + ISR_HANDLER TIMER133_IRQHandler + ISR_HANDLER PWM131_IRQHandler + ISR_HANDLER SERIAL2_IRQHandler + ISR_HANDLER SERIAL3_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER134_IRQHandler + ISR_HANDLER TIMER135_IRQHandler + ISR_HANDLER PWM132_IRQHandler + ISR_HANDLER SERIAL4_IRQHandler + ISR_HANDLER SERIAL5_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_HANDLER TIMER136_IRQHandler + ISR_HANDLER TIMER137_IRQHandler + ISR_HANDLER PWM133_IRQHandler + ISR_HANDLER SERIAL6_IRQHandler + ISR_HANDLER SERIAL7_IRQHandler + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ + ISR_RESERVED_DUMMY /* Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop diff --git a/mdk/system_nrf92.c b/mdk/system_nrf92.c new file mode 100644 index 000000000..80dd06dd9 --- /dev/null +++ b/mdk/system_nrf92.c @@ -0,0 +1,115 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "system_nrf92.h" +#include "system_config_sau.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_MHZ (1000000UL) +#if defined(NRF_PPR) + #define __SYSTEM_CLOCK_DEFAULT (16ul * __SYSTEM_CLOCK_MHZ) +#elif defined(NRF_RADIOCORE) + #define __SYSTEM_CLOCK_DEFAULT (256ul * __SYSTEM_CLOCK_MHZ) +#else + #define __SYSTEM_CLOCK_DEFAULT (320ul * __SYSTEM_CLOCK_MHZ) +#endif + +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_DEFAULT; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; +#endif + +void SystemCoreClockUpdate(void) +{ + #if defined(NRF_PPR) + /* PPR clock is always 16MHz */ + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; + #elif defined(NRF_FLPR) + /* FLPR does not have access to its HSFLL, assume default speed. */ + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; + #else + #if !defined(NRF_SKIP_CORECLOCKDETECT) && !defined(NRF_TRUSTZONE_NONSECURE) + + /* CPU should have access to its local HSFLL, measure CPU frequency. */ + /* If HSFLL is in closed loop mode it's always measuring, and we can just pick the result.*/ + /* Otherwise, start a frequncy measurement.*/ + if ((NRF_HSFLL->CLOCKSTATUS & HSFLL_CLOCKSTATUS_MODE_Msk) != HSFLL_CLOCKSTATUS_MODE_ClosedLoop) + { + /* Start HSFLL frequency measurement */ + NRF_HSFLL->EVENTS_FREQMDONE = 0ul; + NRF_HSFLL->TASKS_FREQMEAS = 1ul; + for (volatile uint32_t i = 0ul; i < 200ul && NRF_HSFLL->EVENTS_FREQMDONE != 1ul; i++) + { + /* Wait until frequency measurement is done */ + } + + if (NRF_HSFLL->EVENTS_FREQMDONE != 1ul) + { + /* Clock measurement never completed, return default CPU clock speed */ + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; + return; + } + } + + /* Frequency measurement result is a multiple of 16MHz */ + SystemCoreClock = NRF_HSFLL->FREQM.MEAS * 16ul * __SYSTEM_CLOCK_MHZ; + #else + SystemCoreClock = __SYSTEM_CLOCK_DEFAULT; + #endif + #endif +} + +void SystemInit(void) +{ + #ifdef __CORTEX_M + #if !defined(NRF_TRUSTZONE_NONSECURE) && defined(__ARM_FEATURE_CMSE) + #if defined(__FPU_PRESENT) && __FPU_PRESENT + /* Allow Non-Secure code to run FPU instructions. + * If only the secure code should control FPU power state these registers should be configured accordingly in the secure application code. */ + SCB->NSACR |= (3UL << 10ul); + #endif + + #ifndef NRF_SKIP_SAU_CONFIGURATION + configure_default_sau(); + #endif + #endif + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1ul) + SCB->CPACR |= (3UL << 20ul) | (3UL << 22ul); + __DSB(); + __ISB(); + #endif + #endif +} + +/*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf92.h b/mdk/system_nrf92.h new file mode 100644 index 000000000..b95686c57 --- /dev/null +++ b/mdk/system_nrf92.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2024 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF92_H +#define SYSTEM_NRF92_H +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* SYSTEM_NRF92_H */ diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index 429686209..520ca2436 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -35,6 +35,10 @@ #define NRFX_COREDEP_H__ #include +#if NRFX_CHECK(ISA_RISCV) +#include +#include +#endif /** * @defgroup nrfx_coredep Core-dependent functionality @@ -87,17 +91,6 @@ #error "Unknown device" #endif -#if NRFX_CHECK(ISA_RISCV) -/** @brief Slowdown for RISCV cores. */ -#if !defined(NRFX_DELAY_RISCV_SLOWDOWN) -#if defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA) -#define NRFX_DELAY_RISCV_SLOWDOWN 15 -#else -#define NRFX_DELAY_RISCV_SLOWDOWN 50 -#endif // defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA) -#endif // !defined(NRFX_DELAY_RISCV_SLOWDOWN) -#endif - /** * @brief Function for delaying execution for a number of microseconds. * @@ -192,11 +185,26 @@ NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; delay_cycles(cycles); #elif NRFX_CHECK(ISA_RISCV) +#if !NRFX_CHECK(NRFX_COREDEP_VPR_LEGACY) + nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_TRIGGER_COMBINED); + nrf_vpr_csr_vtim_combined_counter_set(time_us * NRFX_DELAY_CPU_FREQ_MHZ); + nrf_vpr_csr_vtim_combined_wait_trigger(); +#else + #if !defined(NRFX_DELAY_RISCV_SLOWDOWN) + #if defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA) + #define NRFX_DELAY_RISCV_SLOWDOWN 15 + #else + #define NRFX_DELAY_RISCV_SLOWDOWN 50 + #endif // defined(NRF54L15_XXAA) || defined(NRF54L15_ENGA_XXAA) + #endif // !defined(NRFX_DELAY_RISCV_SLOWDOWN) + for (volatile uint32_t i = 0; - i < ((NRFX_DELAY_CPU_FREQ_MHZ * time_us) / NRFX_DELAY_RISCV_SLOWDOWN); - i++) - {} -#endif + i < ((NRFX_DELAY_CPU_FREQ_MHZ * time_us) / NRFX_DELAY_RISCV_SLOWDOWN); + i++) + {} + +#endif // !NRFX_CHECK(NRFX_CONFIG_COREDEP_VPR_LEGACY) +#endif // NRFX_CHECK(ISA_ARM) } #endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY) diff --git a/templates/nrfx_config_common.h b/templates/nrfx_config_common.h index 41af4097c..e06ed09f4 100644 --- a/templates/nrfx_config_common.h +++ b/templates/nrfx_config_common.h @@ -45,7 +45,7 @@ /** @brief Symbol specifying minor version of the nrfx API to be used. */ #ifndef NRFX_CONFIG_API_VER_MINOR -#define NRFX_CONFIG_API_VER_MINOR 2 +#define NRFX_CONFIG_API_VER_MINOR 3 #endif /** @brief Symbol specifying micro version of the nrfx API to be used. */ diff --git a/templates/nrfx_config_nrf54h20_enga_flpr.h b/templates/nrfx_config_nrf54h20_enga_flpr.h index 6bfc4ffe4..2ea93fe96 100644 --- a/templates/nrfx_config_nrf54h20_enga_flpr.h +++ b/templates/nrfx_config_nrf54h20_enga_flpr.h @@ -90,6 +90,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_enga_ppr.h b/templates/nrfx_config_nrf54h20_enga_ppr.h index 4cb8e7d55..d32adc8bb 100644 --- a/templates/nrfx_config_nrf54h20_enga_ppr.h +++ b/templates/nrfx_config_nrf54h20_enga_ppr.h @@ -90,6 +90,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_flpr.h b/templates/nrfx_config_nrf54h20_flpr.h index c9c5d5ff9..415be7643 100644 --- a/templates/nrfx_config_nrf54h20_flpr.h +++ b/templates/nrfx_config_nrf54h20_flpr.h @@ -90,6 +90,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_ENABLED * diff --git a/templates/nrfx_config_nrf54h20_ppr.h b/templates/nrfx_config_nrf54h20_ppr.h index fc5adb941..7ef1ce8f3 100644 --- a/templates/nrfx_config_nrf54h20_ppr.h +++ b/templates/nrfx_config_nrf54h20_ppr.h @@ -90,6 +90,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_enga_application.h b/templates/nrfx_config_nrf54l15_enga_application.h index 5ece3d326..60ff23515 100644 --- a/templates/nrfx_config_nrf54l15_enga_application.h +++ b/templates/nrfx_config_nrf54l15_enga_application.h @@ -626,6 +626,75 @@ #define NRFX_PRS_BOX_5_ENABLED 0 #endif +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM20_ENABLED +#define NRFX_PWM20_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM21_ENABLED +#define NRFX_PWM21_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM22_ENABLED +#define NRFX_PWM22_ENABLED 0 +#endif + /** * @brief NRFX_QDEC_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_enga_flpr.h b/templates/nrfx_config_nrf54l15_enga_flpr.h index 5134a32d0..93e3b1bd7 100644 --- a/templates/nrfx_config_nrf54l15_enga_flpr.h +++ b/templates/nrfx_config_nrf54l15_enga_flpr.h @@ -163,6 +163,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED * @@ -626,6 +635,75 @@ #define NRFX_PRS_BOX_5_ENABLED 0 #endif +/** + * @brief NRFX_PWM_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 3. + */ +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PWM20_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM20_ENABLED +#define NRFX_PWM20_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM21_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM21_ENABLED +#define NRFX_PWM21_ENABLED 0 +#endif + +/** + * @brief NRFX_PWM22_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_PWM22_ENABLED +#define NRFX_PWM22_ENABLED 0 +#endif + /** * @brief NRFX_QDEC_ENABLED * diff --git a/templates/nrfx_config_nrf54l15_flpr.h b/templates/nrfx_config_nrf54l15_flpr.h index aa9562819..e5d4c45ff 100644 --- a/templates/nrfx_config_nrf54l15_flpr.h +++ b/templates/nrfx_config_nrf54l15_flpr.h @@ -163,6 +163,15 @@ #define NRFX_COMP_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_COREDEP_VPR_LEGACY + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_COREDEP_VPR_LEGACY +#define NRFX_COREDEP_VPR_LEGACY 0 +#endif + /** * @brief NRFX_DPPI_CONFIG_LOG_ENABLED *